#include <stdio.h>
#include <math.h>
#include <time.h>
#include <cuda.h>
//Code written by Alan Fleming

//CONSTANTS
#define MATRIXSIZE 8
#define BLOCKSIZE 4

void mul_matrix_cpu(float *M, float *N, float *P, int width){
	for( int i = 0; i<width; i++){
		for( int j = 0; j<width; j++){
			float sum = 0;
			for (int k = 0; k < width; k++){
				sum += M[i * width + k] * N[k * width + j];
			}
			P[i * width + j] = sum;
		}
	}
}

__global__ void mul_matrix_gpu(float *M, float *N, float *P, int width) {
	//Assuming matrix is width x width
	//Assuming tile size = blockdim.x
	__shared__ float ds_M[BLOCKSIZE * BLOCKSIZE];
	__shared__ float ds_N[BLOCKSIZE * BLOCKSIZE];

	//Calculate row and collumn
	int row = blockIdx.y * blockDim.x + threadIdx.y;
	int col = blockIdx.x * blockDim.x + threadIdx.x;
	//initialize Pvalue
	float Pvalue = 0;

	for (int i = 0; i < (width / blockDim.x); ++i) {
		//copy global memory into shared memory
		ds_M[threadIdx.y  * blockDim.x + threadIdx.x] = M[row * width + i * blockDim.x + threadIdx.x];
		ds_N[threadIdx.y * blockDim.x + threadIdx.x] = N[col + (i * blockDim.x + threadIdx.y) * width];		
		//ensure all data is copied
		__syncthreads();
		
		//Preform partial multiplications
		for(int k = 0; k < blockDim.x; ++k) {
			Pvalue += ds_M[threadIdx.y * blockDim.x + k] * ds_N[k * blockDim.x + threadIdx.x];
		}
		__syncthreads();
	}
	//Load final product into output memory
	P[row * width + col] = Pvalue;
}

bool verify(float *A, float *B, float *C, int width) {
	//Tolerance to check
	const float tolerance = 1e-6;
	for(int i = 0; i < width; ++i){
		for(int k = 0; k < width; ++k) {
			float sum = 0;
			for(int j = 0; j < width; ++j) {
				sum += A[i * width + j] * B[j * width + k];
			}
			
			//get the absolute value of the error for comparison
			float error = fabs(sum - C[i * width + k])/sum;
			//Check if error is too large
			if(error > tolerance) {
				printf("TEST FAILED\n\n");
				return false;
			}
		}
	}
	printf("TEST PASSED\n\n");
	return true;
}

int main(int argc, char *argv[]){
	//allocate system memory for array
	float *a = (float *)malloc(sizeof(float) * MATRIXSIZE * MATRIXSIZE );	//first matrix
	float *b = (float *)malloc(sizeof(float) * MATRIXSIZE * MATRIXSIZE ); //second matrix
	float *c = (float *)malloc(sizeof(float) * MATRIXSIZE * MATRIXSIZE ); //resulting matrix

	int init =1325;
	for (int i=0;i<MATRIXSIZE;i++){
	    for (int j=0;j<MATRIXSIZE;j++){
		init= 3125 * init % 6553;
		a[i * MATRIXSIZE + j]= ( init -1000 ) % 6553;
		b[i * MATRIXSIZE + j]= init % 251;
	    }
	}
	
	//get cpu start time
	clock_t t1 = clock();
	//run function
	mul_matrix_cpu(a, b, c, MATRIXSIZE);
	//get cpu stop time
	clock_t t2 = clock();
	//calculate runtime
	float cpuTime = (float(t2 - t1)/CLOCKS_PER_SEC*1000);

	//allocate memory on gpu
	float *dev_a, *dev_b, *dev_c;
	cudaMalloc((void **)(&dev_a),MATRIXSIZE * MATRIXSIZE * sizeof(float));
	cudaMalloc((void **)(&dev_b),MATRIXSIZE * MATRIXSIZE * sizeof(float));
	cudaMalloc((void **)(&dev_c),MATRIXSIZE * MATRIXSIZE * sizeof(float));

	//copy matrices to gpu
	cudaMemcpy(dev_a,a, MATRIXSIZE * MATRIXSIZE * sizeof(float),cudaMemcpyHostToDevice);
	cudaMemcpy(dev_b,b, MATRIXSIZE * MATRIXSIZE * sizeof(float),cudaMemcpyHostToDevice);

	//calculate dimensions for gpu
	dim3 dimBlock(BLOCKSIZE,BLOCKSIZE);
	dim3 dimGrid( ceil(double(MATRIXSIZE)/dimBlock.x), ceil(double(MATRIXSIZE) /dimBlock.y));

	//Set up cuda events for recording runtime
	cudaEvent_t start,stop;
	float gpuTime; 
	cudaEventCreate(&start);
	cudaEventCreate(&stop);
	cudaEventRecord(start,0);

	// do some work on the GPU
	mul_matrix_gpu<<<dimGrid, dimBlock>>>(dev_a, dev_b, dev_c, MATRIXSIZE);

	//calculate runtime 
	cudaEventRecord(stop,0);
	cudaEventSynchronize(stop);
	cudaEventElapsedTime(&gpuTime,start,stop);

	//destroy cuda events
	cudaEventDestroy(start);
	cudaEventDestroy(stop);

	//copy memory from device
	cudaMemcpy(c,dev_c, MATRIXSIZE * MATRIXSIZE * sizeof(int),cudaMemcpyDeviceToHost);

	//print results
	printf("CPU Runtime: %f\nGpu Runtime: %f\nSpeedup: %f\n", (double)cpuTime, (double)gpuTime, double(cpuTime / gpuTime));

	//verify results
	verify(a,b,c, MATRIXSIZE);

	//free memory
	free(a);
	free(b);
	free(c);
	cudaFree(dev_a);
	cudaFree(dev_b);
	cudaFree(dev_c);
	//exit program
	return 0;
}

	.file	"tmpxft_003981a0_00000000-6_matrixMul.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2032:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z14mul_matrix_cpuPfS_S_i
	.type	_Z14mul_matrix_cpuPfS_S_i, @function
_Z14mul_matrix_cpuPfS_S_i:
.LFB2027:
	.cfi_startproc
	endbr64
	movq	%rdi, %r10
	xorl	%r9d, %r9d
	movslq	%ecx, %rdi
	movq	%rsi, %r11
	salq	$2, %rdi
	xorl	%esi, %esi
	cmpl	%ecx, %r9d
	jl	.L11
	ret
.L11:
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
.L7:
	xorl	%eax, %eax
	leaq	(%r10,%rsi), %rbp
	leaq	(%rdx,%rsi), %r12
.L6:
	leaq	(%r11,%rax,4), %rbx
	xorl	%r8d, %r8d
	xorps	%xmm0, %xmm0
.L4:
	movss	0(%rbp,%r8,4), %xmm1
	mulss	(%rbx), %xmm1
	incq	%r8
	addq	%rdi, %rbx
	addss	%xmm1, %xmm0
	cmpl	%r8d, %ecx
	jg	.L4
	movss	%xmm0, (%r12,%rax,4)
	incq	%rax
	cmpl	%eax, %ecx
	jg	.L6
	incl	%r9d
	addq	%rdi, %rsi
	cmpl	%ecx, %r9d
	jl	.L7
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z14mul_matrix_cpuPfS_S_i, .-_Z14mul_matrix_cpuPfS_S_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC3:
	.string	"TEST FAILED\n\n"
.LC4:
	.string	"TEST PASSED\n\n"
	.text
	.globl	_Z6verifyPfS_S_i
	.type	_Z6verifyPfS_S_i, @function
_Z6verifyPfS_S_i:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movslq	%ecx, %rcx
	movq	%rsi, %r10
	movq	%rdi, %r9
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	movq	%rcx, %rax
	movq	%rdx, %r11
	salq	$2, %rcx
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	xorl	%esi, %esi
	xorl	%r8d, %r8d
	movss	.LC1(%rip), %xmm2
.L14:
	cmpl	%eax, %r8d
	jge	.L26
	xorl	%edx, %edx
	leaq	(%r9,%rsi), %rbp
	leaq	(%r11,%rsi), %r12
.L20:
	leaq	(%r10,%rdx,4), %rbx
	xorl	%edi, %edi
	xorps	%xmm1, %xmm1
.L15:
	movss	0(%rbp,%rdi,4), %xmm0
	mulss	(%rbx), %xmm0
	incq	%rdi
	addq	%rcx, %rbx
	addss	%xmm0, %xmm1
	cmpl	%edi, %eax
	jg	.L15
	movaps	%xmm1, %xmm0
	subss	(%r12,%rdx,4), %xmm0
	andps	%xmm2, %xmm0
	divss	%xmm1, %xmm0
	comiss	.LC2(%rip), %xmm0
	jbe	.L24
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	xorl	%eax, %eax
	jmp	.L13
.L24:
	incq	%rdx
	cmpl	%edx, %eax
	jg	.L20
	incl	%r8d
	addq	%rcx, %rsi
	jmp	.L14
.L26:
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movb	$1, %al
.L13:
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z6verifyPfS_S_i, .-_Z6verifyPfS_S_i
	.globl	_Z39__device_stub__Z14mul_matrix_gpuPfS_S_iPfS_S_i
	.type	_Z39__device_stub__Z14mul_matrix_gpuPfS_S_iPfS_S_i, @function
_Z39__device_stub__Z14mul_matrix_gpuPfS_S_iPfS_S_i:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L27
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z14mul_matrix_gpuPfS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L27:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L29
	call	__stack_chk_fail@PLT
.L29:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z39__device_stub__Z14mul_matrix_gpuPfS_S_iPfS_S_i, .-_Z39__device_stub__Z14mul_matrix_gpuPfS_S_iPfS_S_i
	.globl	_Z14mul_matrix_gpuPfS_S_i
	.type	_Z14mul_matrix_gpuPfS_S_i, @function
_Z14mul_matrix_gpuPfS_S_i:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z14mul_matrix_gpuPfS_S_iPfS_S_i
	.cfi_endproc
.LFE2055:
	.size	_Z14mul_matrix_gpuPfS_S_i, .-_Z14mul_matrix_gpuPfS_S_i
	.section	.rodata.str1.1
.LC7:
	.string	"CPU Runtime: %f\nGpu Runtime: %f\nSpeedup: %f\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	$256, %edi
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	subq	$88, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$256, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	movl	$256, %edi
	movq	%rax, %rbx
	call	malloc@PLT
	xorl	%edi, %edi
	movl	$1325, %ecx
	movl	$6553, %r8d
	movq	%rax, %r12
	movl	$251, %r10d
.L33:
	movq	%rdi, %rsi
	xorl	%r9d, %r9d
.L34:
	imull	$3125, %ecx, %eax
	incl	%r9d
	cltd
	idivl	%r8d
	leal	-1000(%rdx), %eax
	movl	%edx, %ecx
	cltd
	idivl	%r8d
	movl	%ecx, %eax
	cvtsi2ssl	%edx, %xmm0
	cltd
	idivl	%r10d
	movss	%xmm0, 0(%rbp,%rsi)
	cvtsi2ssl	%edx, %xmm0
	movss	%xmm0, (%rbx,%rsi)
	addq	$4, %rsi
	cmpl	$8, %r9d
	jne	.L34
	addq	$32, %rdi
	cmpq	$256, %rdi
	jne	.L33
	call	clock@PLT
	movl	$8, %ecx
	movq	%r12, %rdx
	movq	%rbx, %rsi
	movq	%rbp, %rdi
	movq	%rax, %r13
	call	_Z14mul_matrix_cpuPfS_S_i
	call	clock@PLT
	leaq	8(%rsp), %rdi
	movl	$256, %esi
	subq	%r13, %rax
	cvtsi2ssq	%rax, %xmm0
	divss	.LC5(%rip), %xmm0
	mulss	.LC6(%rip), %xmm0
	movd	%xmm0, %r13d
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$256, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$256, %esi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$256, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$256, %edx
	call	cudaMemcpy@PLT
	leaq	32(%rsp), %rdi
	movabsq	$8589934594, %rax
	movl	$1, 68(%rsp)
	movq	%rax, 60(%rsp)
	call	cudaEventCreate@PLT
	leaq	40(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	60(%rsp), %rdi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	68(%rsp), %esi
	movl	$1, %ecx
	movabsq	$17179869188, %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L36
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	$8, %ecx
	movq	8(%rsp), %rdi
	call	_Z39__device_stub__Z14mul_matrix_gpuPfS_S_iPfS_S_i
.L36:
	movq	40(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	40(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	leaq	4(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movq	32(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	40(%rsp), %rdi
	call	cudaEventDestroy@PLT
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movq	%r12, %rdi
	movl	$256, %edx
	call	cudaMemcpy@PLT
	movss	4(%rsp), %xmm1
	movb	$3, %al
	movd	%r13d, %xmm2
	movd	%r13d, %xmm3
	leaq	.LC7(%rip), %rsi
	movl	$2, %edi
	divss	%xmm1, %xmm2
	cvtss2sd	%xmm3, %xmm0
	cvtss2sd	%xmm1, %xmm1
	cvtss2sd	%xmm2, %xmm2
	call	__printf_chk@PLT
	movq	%r12, %rdx
	movq	%rbx, %rsi
	movl	$8, %ecx
	movq	%rbp, %rdi
	call	_Z6verifyPfS_S_i
	movq	%rbp, %rdi
	call	free@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	%r12, %rdi
	call	free@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L37
	call	__stack_chk_fail@PLT
.L37:
	addq	$88, %rsp
	.cfi_def_cfa_offset 40
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	main, .-main
	.section	.rodata.str1.1
.LC8:
	.string	"_Z14mul_matrix_gpuPfS_S_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC8(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z14mul_matrix_gpuPfS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2057:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst16,"aM",@progbits,16
	.align 16
.LC1:
	.long	2147483647
	.long	0
	.long	0
	.long	0
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC2:
	.long	897988541
	.align 4
.LC5:
	.long	1232348160
	.align 4
.LC6:
	.long	1148846080
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <math.h>
#include <time.h>
#include <hip/hip_runtime.h>
//Code written by Alan Fleming

//CONSTANTS
#define MATRIXSIZE 8
#define BLOCKSIZE 4

void mul_matrix_cpu(float *M, float *N, float *P, int width){
	for( int i = 0; i<width; i++){
		for( int j = 0; j<width; j++){
			float sum = 0;
			for (int k = 0; k < width; k++){
				sum += M[i * width + k] * N[k * width + j];
			}
			P[i * width + j] = sum;
		}
	}
}

__global__ void mul_matrix_gpu(float *M, float *N, float *P, int width) {
	//Assuming matrix is width x width
	//Assuming tile size = blockdim.x
	__shared__ float ds_M[BLOCKSIZE * BLOCKSIZE];
	__shared__ float ds_N[BLOCKSIZE * BLOCKSIZE];

	//Calculate row and collumn
	int row = blockIdx.y * blockDim.x + threadIdx.y;
	int col = blockIdx.x * blockDim.x + threadIdx.x;
	//initialize Pvalue
	float Pvalue = 0;

	for (int i = 0; i < (width / blockDim.x); ++i) {
		//copy global memory into shared memory
		ds_M[threadIdx.y  * blockDim.x + threadIdx.x] = M[row * width + i * blockDim.x + threadIdx.x];
		ds_N[threadIdx.y * blockDim.x + threadIdx.x] = N[col + (i * blockDim.x + threadIdx.y) * width];		
		//ensure all data is copied
		__syncthreads();
		
		//Preform partial multiplications
		for(int k = 0; k < blockDim.x; ++k) {
			Pvalue += ds_M[threadIdx.y * blockDim.x + k] * ds_N[k * blockDim.x + threadIdx.x];
		}
		__syncthreads();
	}
	//Load final product into output memory
	P[row * width + col] = Pvalue;
}

bool verify(float *A, float *B, float *C, int width) {
	//Tolerance to check
	const float tolerance = 1e-6;
	for(int i = 0; i < width; ++i){
		for(int k = 0; k < width; ++k) {
			float sum = 0;
			for(int j = 0; j < width; ++j) {
				sum += A[i * width + j] * B[j * width + k];
			}
			
			//get the absolute value of the error for comparison
			float error = fabs(sum - C[i * width + k])/sum;
			//Check if error is too large
			if(error > tolerance) {
				printf("TEST FAILED\n\n");
				return false;
			}
		}
	}
	printf("TEST PASSED\n\n");
	return true;
}

int main(int argc, char *argv[]){
	//allocate system memory for array
	float *a = (float *)malloc(sizeof(float) * MATRIXSIZE * MATRIXSIZE );	//first matrix
	float *b = (float *)malloc(sizeof(float) * MATRIXSIZE * MATRIXSIZE ); //second matrix
	float *c = (float *)malloc(sizeof(float) * MATRIXSIZE * MATRIXSIZE ); //resulting matrix

	int init =1325;
	for (int i=0;i<MATRIXSIZE;i++){
	    for (int j=0;j<MATRIXSIZE;j++){
		init= 3125 * init % 6553;
		a[i * MATRIXSIZE + j]= ( init -1000 ) % 6553;
		b[i * MATRIXSIZE + j]= init % 251;
	    }
	}
	
	//get cpu start time
	clock_t t1 = clock();
	//run function
	mul_matrix_cpu(a, b, c, MATRIXSIZE);
	//get cpu stop time
	clock_t t2 = clock();
	//calculate runtime
	float cpuTime = (float(t2 - t1)/CLOCKS_PER_SEC*1000);

	//allocate memory on gpu
	float *dev_a, *dev_b, *dev_c;
	hipMalloc((void **)(&dev_a),MATRIXSIZE * MATRIXSIZE * sizeof(float));
	hipMalloc((void **)(&dev_b),MATRIXSIZE * MATRIXSIZE * sizeof(float));
	hipMalloc((void **)(&dev_c),MATRIXSIZE * MATRIXSIZE * sizeof(float));

	//copy matrices to gpu
	hipMemcpy(dev_a,a, MATRIXSIZE * MATRIXSIZE * sizeof(float),hipMemcpyHostToDevice);
	hipMemcpy(dev_b,b, MATRIXSIZE * MATRIXSIZE * sizeof(float),hipMemcpyHostToDevice);

	//calculate dimensions for gpu
	dim3 dimBlock(BLOCKSIZE,BLOCKSIZE);
	dim3 dimGrid( ceil(double(MATRIXSIZE)/dimBlock.x), ceil(double(MATRIXSIZE) /dimBlock.y));

	//Set up cuda events for recording runtime
	hipEvent_t start,stop;
	float gpuTime; 
	hipEventCreate(&start);
	hipEventCreate(&stop);
	hipEventRecord(start,0);

	// do some work on the GPU
	mul_matrix_gpu<<<dimGrid, dimBlock>>>(dev_a, dev_b, dev_c, MATRIXSIZE);

	//calculate runtime 
	hipEventRecord(stop,0);
	hipEventSynchronize(stop);
	hipEventElapsedTime(&gpuTime,start,stop);

	//destroy cuda events
	hipEventDestroy(start);
	hipEventDestroy(stop);

	//copy memory from device
	hipMemcpy(c,dev_c, MATRIXSIZE * MATRIXSIZE * sizeof(int),hipMemcpyDeviceToHost);

	//print results
	printf("CPU Runtime: %f\nGpu Runtime: %f\nSpeedup: %f\n", (double)cpuTime, (double)gpuTime, double(cpuTime / gpuTime));

	//verify results
	verify(a,b,c, MATRIXSIZE);

	//free memory
	free(a);
	free(b);
	free(c);
	hipFree(dev_a);
	hipFree(dev_b);
	hipFree(dev_c);
	//exit program
	return 0;
}

	.text
	.file	"matrixMul.hip"
	.globl	_Z14mul_matrix_cpuPfS_S_i       # -- Begin function _Z14mul_matrix_cpuPfS_S_i
	.type	_Z14mul_matrix_cpuPfS_S_i,@function
_Z14mul_matrix_cpuPfS_S_i:              # @_Z14mul_matrix_cpuPfS_S_i
	.cfi_startproc
# %bb.0:
	testl	%ecx, %ecx
	jle	.LBB0_8
# %bb.1:                                # %.preheader26.lr.ph
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	%ecx, %eax
	leaq	(,%rax,4), %r8
	xorl	%r9d, %r9d
	xorl	%r10d, %r10d
.LBB0_2:                                # %.preheader.lr.ph
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB0_3 Depth 2
                                        #       Child Loop BB0_4 Depth 3
	movl	%r9d, %r11d
	leaq	(%rdi,%r11,4), %r11
	movq	%r10, %rbx
	imulq	%rax, %rbx
	leaq	(%rdx,%rbx,4), %rbx
	movq	%rsi, %r14
	xorl	%r15d, %r15d
.LBB0_3:                                # %.preheader
                                        #   Parent Loop BB0_2 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB0_4 Depth 3
	xorps	%xmm0, %xmm0
	movq	%r14, %r12
	xorl	%r13d, %r13d
.LBB0_4:                                #   Parent Loop BB0_2 Depth=1
                                        #     Parent Loop BB0_3 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movss	(%r11,%r13,4), %xmm1            # xmm1 = mem[0],zero,zero,zero
	mulss	(%r12), %xmm1
	addss	%xmm1, %xmm0
	incq	%r13
	addq	%r8, %r12
	cmpq	%r13, %rax
	jne	.LBB0_4
# %bb.5:                                # %._crit_edge
                                        #   in Loop: Header=BB0_3 Depth=2
	movss	%xmm0, (%rbx,%r15,4)
	incq	%r15
	addq	$4, %r14
	cmpq	%rax, %r15
	jne	.LBB0_3
# %bb.6:                                # %._crit_edge30
                                        #   in Loop: Header=BB0_2 Depth=1
	incq	%r10
	addl	%ecx, %r9d
	cmpq	%rax, %r10
	jne	.LBB0_2
# %bb.7:
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	.cfi_restore %r12
	.cfi_restore %r13
	.cfi_restore %r14
	.cfi_restore %r15
.LBB0_8:                                # %._crit_edge32
	retq
.Lfunc_end0:
	.size	_Z14mul_matrix_cpuPfS_S_i, .Lfunc_end0-_Z14mul_matrix_cpuPfS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z29__device_stub__mul_matrix_gpuPfS_S_i # -- Begin function _Z29__device_stub__mul_matrix_gpuPfS_S_i
	.type	_Z29__device_stub__mul_matrix_gpuPfS_S_i,@function
_Z29__device_stub__mul_matrix_gpuPfS_S_i: # @_Z29__device_stub__mul_matrix_gpuPfS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14mul_matrix_gpuPfS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z29__device_stub__mul_matrix_gpuPfS_S_i, .Lfunc_end1-_Z29__device_stub__mul_matrix_gpuPfS_S_i
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function _Z6verifyPfS_S_i
.LCPI2_0:
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0
.LCPI2_1:
	.long	0x358637bd                      # float 9.99999997E-7
	.text
	.globl	_Z6verifyPfS_S_i
	.type	_Z6verifyPfS_S_i,@function
_Z6verifyPfS_S_i:                       # @_Z6verifyPfS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rdi, %r14
	movl	$.Lstr.1, %edi
	testl	%ecx, %ecx
	jle	.LBB2_1
# %bb.2:                                # %.preheader44.lr.ph
	movl	%ecx, %r8d
	leaq	(,%r8,4), %r9
	xorl	%r10d, %r10d
	movaps	.LCPI2_0(%rip), %xmm0           # xmm0 = [NaN,NaN,NaN,NaN]
	movss	.LCPI2_1(%rip), %xmm1           # xmm1 = mem[0],zero,zero,zero
	xorl	%r11d, %r11d
	xorl	%ebx, %ebx
	movq	%rdx, 16(%rsp)                  # 8-byte Spill
	movq	%r14, 8(%rsp)                   # 8-byte Spill
.LBB2_3:                                # %.preheader.lr.ph
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_5 Depth 2
                                        #       Child Loop BB2_6 Depth 3
	movl	%r10d, %eax
	leaq	(%r14,%rax,4), %r14
	movq	%r11, %rax
	imulq	%r8, %rax
	leaq	(%rdx,%rax,4), %r15
	movq	%rsi, %rdi
	movq	%rsi, %r12
	xorl	%r13d, %r13d
.LBB2_5:                                # %.preheader
                                        #   Parent Loop BB2_3 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB2_6 Depth 3
	xorps	%xmm2, %xmm2
	movq	%r12, %rbp
	xorl	%eax, %eax
.LBB2_6:                                #   Parent Loop BB2_3 Depth=1
                                        #     Parent Loop BB2_5 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movss	(%r14,%rax,4), %xmm3            # xmm3 = mem[0],zero,zero,zero
	mulss	(%rbp), %xmm3
	addss	%xmm3, %xmm2
	incq	%rax
	addq	%r9, %rbp
	cmpq	%rax, %r8
	jne	.LBB2_6
# %bb.7:                                # %.critedge
                                        #   in Loop: Header=BB2_5 Depth=2
	movaps	%xmm2, %xmm3
	subss	(%r15,%r13,4), %xmm3
	andps	%xmm0, %xmm3
	divss	%xmm2, %xmm3
	ucomiss	%xmm1, %xmm3
	ja	.LBB2_8
# %bb.4:                                #   in Loop: Header=BB2_5 Depth=2
	incq	%r13
	addq	$4, %r12
	cmpq	%r8, %r13
	jne	.LBB2_5
# %bb.9:                                # %.critedge41
                                        #   in Loop: Header=BB2_3 Depth=1
	incq	%r11
	cmpq	%r8, %r11
	setae	%bl
	addl	%ecx, %r10d
	cmpq	%r8, %r11
	movq	16(%rsp), %rdx                  # 8-byte Reload
	movq	%rdi, %rsi
	movq	8(%rsp), %r14                   # 8-byte Reload
	jne	.LBB2_3
# %bb.10:
	movl	$.Lstr.1, %edi
	jmp	.LBB2_11
.LBB2_8:
	movl	$.Lstr, %edi
	jmp	.LBB2_11
.LBB2_1:
	movb	$1, %bl
.LBB2_11:                               # %.critedge43
	callq	puts@PLT
	andb	$1, %bl
	movl	%ebx, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z6verifyPfS_S_i, .Lfunc_end2-_Z6verifyPfS_S_i
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI3_0:
	.long	0x49742400                      # float 1.0E+6
.LCPI3_1:
	.long	0x447a0000                      # float 1000
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$256, %edi                      # imm = 0x100
	callq	malloc
	movq	%rax, %rbx
	movl	$256, %edi                      # imm = 0x100
	callq	malloc
	movq	%rax, %r14
	movl	$256, %edi                      # imm = 0x100
	callq	malloc
	movq	%rax, %r15
	movl	$1325, %edi                     # imm = 0x52D
	xorl	%eax, %eax
	movl	$2684600343, %ecx               # imm = 0xA003C017
	movq	%rbx, %rdx
	movq	%r14, %rsi
.LBB3_1:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_2 Depth 2
	xorl	%r8d, %r8d
.LBB3_2:                                #   Parent Loop BB3_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	imull	$3125, %edi, %r9d               # imm = 0xC35
	movq	%r9, %rdi
	imulq	%rcx, %rdi
	shrq	$44, %rdi
	imull	$6553, %edi, %r10d              # imm = 0x1999
	movl	%r9d, %edi
	subl	%r10d, %edi
	negl	%r10d
	addl	%r10d, %r9d
	addl	$-1000, %r9d                    # imm = 0xFC18
	xorps	%xmm0, %xmm0
	cvtsi2ss	%r9d, %xmm0
	imull	$2089, %edi, %r9d               # imm = 0x829
	shrl	$19, %r9d
	imull	$251, %r9d, %r9d
	movl	%edi, %r10d
	subl	%r9d, %r10d
	movswl	%r10w, %r9d
	xorps	%xmm1, %xmm1
	cvtsi2ss	%r9d, %xmm1
	movss	%xmm0, (%rdx,%r8,4)
	movss	%xmm1, (%rsi,%r8,4)
	incq	%r8
	cmpq	$8, %r8
	jne	.LBB3_2
# %bb.3:                                #   in Loop: Header=BB3_1 Depth=1
	incq	%rax
	addq	$32, %rsi
	addq	$32, %rdx
	cmpq	$8, %rax
	jne	.LBB3_1
# %bb.4:
	xorl	%r12d, %r12d
	callq	clock
	movq	%rax, 8(%rsp)                   # 8-byte Spill
	movq	%rbx, %rax
.LBB3_5:                                # %.preheader.lr.ph.i
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_6 Depth 2
                                        #       Child Loop BB3_7 Depth 3
	movq	%r12, %rcx
	shlq	$5, %rcx
	addq	%r15, %rcx
	movq	%r14, %rdx
	xorl	%esi, %esi
.LBB3_6:                                # %.preheader.i
                                        #   Parent Loop BB3_5 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB3_7 Depth 3
	xorps	%xmm0, %xmm0
	xorl	%edi, %edi
.LBB3_7:                                #   Parent Loop BB3_5 Depth=1
                                        #     Parent Loop BB3_6 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movss	(%rax,%rdi), %xmm1              # xmm1 = mem[0],zero,zero,zero
	mulss	(%rdx,%rdi,8), %xmm1
	addss	%xmm1, %xmm0
	addq	$4, %rdi
	cmpq	$32, %rdi
	jne	.LBB3_7
# %bb.8:                                # %._crit_edge.i
                                        #   in Loop: Header=BB3_6 Depth=2
	movss	%xmm0, (%rcx,%rsi,4)
	incq	%rsi
	addq	$4, %rdx
	cmpq	$8, %rsi
	jne	.LBB3_6
# %bb.9:                                # %._crit_edge30.i
                                        #   in Loop: Header=BB3_5 Depth=1
	incq	%r12
	addq	$32, %rax
	cmpq	$8, %r12
	jne	.LBB3_5
# %bb.10:                               # %_Z14mul_matrix_cpuPfS_S_i.exit
	callq	clock
	movq	%rax, %r13
	leaq	40(%rsp), %rbp
	movl	$256, %esi                      # imm = 0x100
	movq	%rbp, %rdi
	callq	hipMalloc
	leaq	32(%rsp), %r12
	movl	$256, %esi                      # imm = 0x100
	movq	%r12, %rdi
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movl	$256, %esi                      # imm = 0x100
	callq	hipMalloc
	movq	(%rbp), %rdi
	movl	$256, %edx                      # imm = 0x100
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r12), %rdi
	movl	$256, %edx                      # imm = 0x100
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	24(%rsp), %r12
	movq	%r12, %rdi
	callq	hipEventCreate
	movq	%rsp, %rdi
	callq	hipEventCreate
	movq	(%r12), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movabsq	$8589934594, %rdi               # imm = 0x200000002
	movabsq	$17179869188, %rdx              # imm = 0x400000004
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_12
# %bb.11:
	movq	40(%rsp), %rdi
	movq	32(%rsp), %rsi
	movq	16(%rsp), %rdx
	movl	$8, %ecx
	callq	_Z29__device_stub__mul_matrix_gpuPfS_S_i
.LBB3_12:
	subq	8(%rsp), %r13                   # 8-byte Folded Reload
	xorps	%xmm0, %xmm0
	cvtsi2ss	%r13, %xmm0
	divss	.LCPI3_0(%rip), %xmm0
	mulss	.LCPI3_1(%rip), %xmm0
	movss	%xmm0, 8(%rsp)                  # 4-byte Spill
	movq	(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	(%rsp), %rdi
	callq	hipEventSynchronize
	movq	24(%rsp), %rsi
	movq	(%rsp), %rdx
	leaq	52(%rsp), %r12
	movq	%r12, %rdi
	callq	hipEventElapsedTime
	movq	24(%rsp), %rdi
	callq	hipEventDestroy
	movq	(%rsp), %rdi
	callq	hipEventDestroy
	movq	16(%rsp), %rsi
	movl	$256, %edx                      # imm = 0x100
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movss	8(%rsp), %xmm3                  # 4-byte Reload
                                        # xmm3 = mem[0],zero,zero,zero
	xorps	%xmm0, %xmm0
	cvtss2sd	%xmm3, %xmm0
	movss	(%r12), %xmm2                   # xmm2 = mem[0],zero,zero,zero
	cvtss2sd	%xmm2, %xmm1
	divss	%xmm2, %xmm3
	xorps	%xmm2, %xmm2
	cvtss2sd	%xmm3, %xmm2
	movl	$.L.str.2, %edi
	movb	$3, %al
	callq	printf
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movq	%r15, %rdx
	movl	$8, %ecx
	callq	_Z6verifyPfS_S_i
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14mul_matrix_gpuPfS_S_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z14mul_matrix_gpuPfS_S_i,@object # @_Z14mul_matrix_gpuPfS_S_i
	.section	.rodata,"a",@progbits
	.globl	_Z14mul_matrix_gpuPfS_S_i
	.p2align	3, 0x0
_Z14mul_matrix_gpuPfS_S_i:
	.quad	_Z29__device_stub__mul_matrix_gpuPfS_S_i
	.size	_Z14mul_matrix_gpuPfS_S_i, 8

	.type	.L.str.2,@object                # @.str.2
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.2:
	.asciz	"CPU Runtime: %f\nGpu Runtime: %f\nSpeedup: %f\n"
	.size	.L.str.2, 45

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z14mul_matrix_gpuPfS_S_i"
	.size	.L__unnamed_1, 26

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"TEST FAILED\n"
	.size	.Lstr, 13

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"TEST PASSED\n"
	.size	.Lstr.1, 13

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z29__device_stub__mul_matrix_gpuPfS_S_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z14mul_matrix_gpuPfS_S_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z14mul_matrix_gpuPfS_S_i ; -- Begin function _Z14mul_matrix_gpuPfS_S_i
	.globl	_Z14mul_matrix_gpuPfS_S_i
	.p2align	8
	.type	_Z14mul_matrix_gpuPfS_S_i,@function
_Z14mul_matrix_gpuPfS_S_i:              ; @_Z14mul_matrix_gpuPfS_S_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x2c
	s_load_b32 s2, s[0:1], 0x18
	v_bfe_u32 v2, v0, 10, 10
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[4:5], null, s15, s3, v[2:3]
	v_and_b32_e32 v3, 0x3ff, v0
	v_mov_b32_e32 v5, 0
	s_cmp_gt_u32 s3, s2
	v_mad_u64_u32 v[0:1], null, s14, s3, v[3:4]
	v_mul_lo_u32 v1, v4, s2
	s_cbranch_scc1 .LBB0_5
; %bb.1:                                ; %.lr.ph
	v_cvt_f32_u32_e32 v4, s3
	s_sub_i32 s10, 0, s3
	v_mul_u32_u24_e32 v9, s3, v2
	s_delay_alu instid0(VALU_DEP_3)
	v_add_nc_u32_e32 v6, v1, v3
	v_lshl_add_u32 v7, v3, 2, 64
	v_rcp_iflag_f32_e32 v4, v4
	s_mov_b32 s8, 0
	v_add_lshl_u32 v8, v9, v3, 2
	v_mov_b32_e32 v5, 0
	v_lshlrev_b32_e32 v9, 2, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v10, 64, v8
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v4, 0x4f7ffffe, v4
	v_cvt_u32_f32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s9, v4
	v_mov_b32_e32 v4, 0
	s_mul_i32 s10, s10, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s10, s9, s10
	s_add_i32 s9, s9, s10
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s9, s2, s9
	s_mul_i32 s10, s9, s3
	s_add_i32 s11, s9, 1
	s_sub_i32 s10, s2, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s12, s10, s3
	s_cmp_ge_u32 s10, s3
	s_cselect_b32 s9, s11, s9
	s_cselect_b32 s10, s12, s10
	s_add_i32 s11, s9, 1
	s_cmp_ge_u32 s10, s3
	s_cselect_b32 s9, s11, s9
	s_max_u32 s10, s3, 1
	s_lshl_b32 s11, s3, 2
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_3 Depth 2
	s_mul_i32 s12, s8, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v13, s12, v2
	v_add_nc_u32_e32 v3, s12, v6
	s_mov_b32 s12, s10
	v_mad_u64_u32 v[11:12], null, v13, s2, v[0:1]
	v_mov_b32_e32 v12, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[13:14], 2, v[3:4]
	v_mov_b32_e32 v3, v9
	v_lshlrev_b64 v[11:12], 2, v[11:12]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v13, vcc_lo, s4, v13
	v_add_co_ci_u32_e32 v14, vcc_lo, s5, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v11, vcc_lo, s6, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
	global_load_b32 v13, v[13:14], off
	global_load_b32 v12, v[11:12], off
	v_mov_b32_e32 v11, v7
	s_waitcnt vmcnt(1)
	ds_store_b32 v8, v13
	s_waitcnt vmcnt(0)
	ds_store_b32 v10, v12
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB0_3:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	ds_load_b32 v12, v3
	ds_load_b32 v13, v11
	v_add_nc_u32_e32 v11, s11, v11
	v_add_nc_u32_e32 v3, 4, v3
	s_add_i32 s12, s12, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s12, 0
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v5, v12, v13
	s_cbranch_scc0 .LBB0_3
; %bb.4:                                ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s8, s8, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_u32 s8, s9
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_2
.LBB0_5:                                ; %Flow44
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v1, v0
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v5, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14mul_matrix_gpuPfS_S_i
		.amdhsa_group_segment_fixed_size 128
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z14mul_matrix_gpuPfS_S_i, .Lfunc_end0-_Z14mul_matrix_gpuPfS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 556
; NumSgprs: 18
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 128 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 128
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z14mul_matrix_gpuPfS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z14mul_matrix_gpuPfS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     15
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
