// *----------------------------------------------
// 	Author Contact Information:
// 	Hao Gao
// 	hao.gao@emory.edu || hao.gao.2012@gmail.com
// 	Department of Mathematics and Computer Science, Emory University
// 	Department of Radiology and Imaging Sciences, Emory University
//
// 	Copyright (c) Hao Gao 2012
// ----------------------------------------------*/
//
// If you find this code useful, you may cite the following reference:
// H. Gao. "Fast parallel algorithms for the X-ray transform and its adjoint", Medical Physics (2012).
// The full source codes are available at https://sites.google.com/site/fastxraytransform

#include <math.h>
#include <malloc.h>
#define ABS(a) (a>0?a:-(a))

#define BLOCK_SIZE_x 16
#define BLOCK_SIZE_y 16

extern "C" void Ax_cone_mf_gpu_new(float *X,float *y,float *yNorm,float *sd_phi,float *sd_z,float *y_det,float *z_det,int *id_Y,int *Nv,
float SO,float OD,float scale,float dz,int nx,int ny,int nz,int nt,int na,int nb,int nv,int tmp_size,int nv_block);

__global__ void Ax_cone_mf_gpu_kernel_new(float *x,float *y,float *yNorm,float *sd_phi,float *sd_z,float *y_det,float *z_det,int *id_Y,
float SO,float OD,float scale,float dz,int nx,int ny,int nz,int na,int nb,int nv2)
// Please note that this version has O(Nx) per thread, since GPU threads are already saturated.
// O(1) per thread can be achieved by parallelizing the "for" loop here, given sufficient number of GPU threads.
{
	int bx=blockIdx.x;
	int by=blockIdx.y;
	int tx0=threadIdx.x;
	int ty0=threadIdx.y;

	int ia=bx*BLOCK_SIZE_x+tx0;
	int ib2=by*BLOCK_SIZE_y+ty0;

    if(ia<na&&ib2<nb*nv2)
    {
		int nd,nx2,ny2,nz2,iv0,iv,ib,id,ix,iy,iz,cx1,cx2,cy1,cy2,cz1,cz2;
		float norm,cos_phi,sin_phi,x1,y1,x2,y2,z1,z2,xx1,yy1,zz1,xx2,yy2,zz2,slope1,slope2,l,d,tmp,rx,ry,rz;

		nx2=nx/2;ny2=ny/2;nz2=nz/2;
		nd=na*nb;

		iv0=(int)floor((float)ib2/(float)nb);
		ib=ib2-iv0*nb;
		iv=id_Y[iv0];
		id=iv0*nd+ib*na+ia;

        cos_phi=cosf(sd_phi[iv]);sin_phi=sinf(sd_phi[iv]);
        x1=cos_phi*(-SO);
        y1=sin_phi*(-SO);
        z1=sd_z[iv];
		x2=cos_phi*OD-sin_phi*y_det[ia];
        y2=sin_phi*OD+cos_phi*y_det[ia];
		z2=z_det[ib]+sd_z[iv];
        norm = sqrt(pow(x1-x2,2)+pow(y1-y2,2)+pow(z1-z2,2))*scale;

		y[id]=0;
        // assuming z1-z2 is small
        if(ABS(x1-x2)>ABS(y1-y2))
        {   slope1=(y2-y1)/(x2-x1);
            slope2=(z2-z1)/(x2-x1);
            for(ix=0;ix<nx;ix++)
            {   xx1=(float)(ix-nx2);xx2=xx1+1;
                if(slope1>=0)
                {   yy1=y1+slope1*(xx1-x1)+ny2;
                    yy2=y1+slope1*(xx2-x1)+ny2;
                }
                else
                {   yy1=y1+slope1*(xx2-x1)+ny2;
                    yy2=y1+slope1*(xx1-x1)+ny2;
                }
                cy1=(int)floor(yy1);
                cy2=(int)floor(yy2);
                if(slope2>=0)
                {   zz1=(z1+slope2*(xx1-x1))/dz+nz2;
                    zz2=(z1+slope2*(xx2-x1))/dz+nz2;
                }
                else
                {   zz1=(z1+slope2*(xx2-x1))/dz+nz2;
                    zz2=(z1+slope2*(xx1-x1))/dz+nz2;
                }
                cz1=(int)floor(zz1);
                cz2=(int)floor(zz2);

                if(cy2==cy1)
                {   if(cy1>=0&&cy1<=ny-1)
                    {   if(cz2==cz1)
                        {   if(cz1>=0&&cz1<=nz-1)// 11
                            {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                iy=cy1;iz=cz1;y[id]+=l*x[iz*ny*nx+iy*nx+ix];
                            }
                        }
                        else
                        {   if(cz2>0&&cz2<nz)// 12
                            {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                rz=(cz2-zz1)/(zz2-zz1);
                                iy=cy1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];
                                iy=cy1;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];
                            }
                            else
                            {   if(cz2==0)// 13
                                {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    rz=(cz2-zz1)/(zz2-zz1);
                                    iy=cy1;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];
                                }
                                if(cz2==nz)// 14
                                {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    rz=(cz2-zz1)/(zz2-zz1);
                                    iy=cy1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];
                                }
                            }
                        }
                    }
                }
                else
                {   if(cy2>0&&cy2<ny)
                    {   if(cz2==cz1)
                        {   if(cz1>=0&&cz1<=nz-1)// 21
                            {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                ry=(cy2-yy1)/d;
                                iy=cy1;iz=cz1;y[id]+=ry*l*x[iz*ny*nx+iy*nx+ix];
                                iy=cy2;iz=cz1;y[id]+=(1-ry)*l*x[iz*ny*nx+iy*nx+ix];
                            }
                        }
                        else
                        {   if(cz2>0&&cz2<nz)// 22
                            {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                ry=(cy2-yy1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                if(ry>rz)
                                {   iy=cy1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];
                                    iy=cy1;iz=cz2;y[id]+=(ry-rz)*l*x[iz*ny*nx+iy*nx+ix];
                                    iy=cy2;iz=cz2;y[id]+=(1-ry)*l*x[iz*ny*nx+iy*nx+ix];
                                }
                                else
                                {   iy=cy1;iz=cz1;y[id]+=ry*l*x[iz*ny*nx+iy*nx+ix];
                                    iy=cy2;iz=cz1;y[id]+=(rz-ry)*l*x[iz*ny*nx+iy*nx+ix];
                                    iy=cy2;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];
                                }
                            }
                            else
                            {   if(cz2==0)// 23
                                {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    ry=(cy2-yy1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                    if(ry>rz)
                                    {   iy=cy1;iz=cz2;y[id]+=(ry-rz)*l*x[iz*ny*nx+iy*nx+ix];
                                        iy=cy2;iz=cz2;y[id]+=(1-ry)*l*x[iz*ny*nx+iy*nx+ix];
                                    }
                                    else
                                    {   iy=cy2;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];
                                    }
                                }
                                if(cz2==nz)// 24
                                {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    ry=(cy2-yy1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                    if(ry>rz)
                                    {   iy=cy1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];
                                    }
                                    else
                                    {   iy=cy1;iz=cz1;y[id]+=ry*l*x[iz*ny*nx+iy*nx+ix];
                                        iy=cy2;iz=cz1;y[id]+=(rz-ry)*l*x[iz*ny*nx+iy*nx+ix];
                                    }
                                }
                            }
                        }
                    }
                    else
                    {   if(cy2==0)
                        {   if(cz2==cz1)
                            {   if(cz1>=0&&cz1<=nz-1)// 31
                                {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    ry=(cy2-yy1)/d;
                                    iy=cy2;iz=cz1;y[id]+=(1-ry)*l*x[iz*ny*nx+iy*nx+ix];
                                }
                            }
                            else
                            {   if(cz2>0&&cz2<nz)// 32
                                {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    ry=(cy2-yy1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                    if(ry>rz)
                                    {   iy=cy2;iz=cz2;y[id]+=(1-ry)*l*x[iz*ny*nx+iy*nx+ix];
                                    }
                                    else
                                    {   iy=cy2;iz=cz1;y[id]+=(rz-ry)*l*x[iz*ny*nx+iy*nx+ix];
                                        iy=cy2;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];
                                    }
                                }
                                else
                                {   if(cz2==0)// 33
                                    {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                        ry=(cy2-yy1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                        if(ry>rz)
                                        {   iy=cy2;iz=cz2;y[id]+=(1-ry)*l*x[iz*ny*nx+iy*nx+ix];
                                        }
                                        else
                                        {   iy=cy2;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];
                                        }
                                    }
                                    if(cz2==nz)// 34
                                    {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                        ry=(cy2-yy1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                        if(ry>rz)
                                        {
                                        }
                                        else
                                        {   iy=cy2;iz=cz1;y[id]+=(rz-ry)*l*x[iz*ny*nx+iy*nx+ix];
                                        }
                                    }
                                }
                            }
                        }

                        if(cy2==ny)
                        {   if(cz2==cz1)
                            {   if(cz1>=0&&cz1<=nz-1)// 41
                                {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    ry=(cy2-yy1)/d;
                                    iy=cy1;iz=cz1;y[id]+=ry*l*x[iz*ny*nx+iy*nx+ix];
                                }
                            }
                            else
                            {   if(cz2>0&&cz2<nz)// 42
                                {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    ry=(cy2-yy1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                    if(ry>rz)
                                    {   iy=cy1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];
                                        iy=cy1;iz=cz2;y[id]+=(ry-rz)*l*x[iz*ny*nx+iy*nx+ix];
                                    }
                                    else
                                    {   iy=cy1;iz=cz1;y[id]+=ry*l*x[iz*ny*nx+iy*nx+ix];
                                    }
                                }
                                else
                                {   if(cz2==0)// 43
                                    {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                        ry=(cy2-yy1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                        if(ry>rz)
                                        {   iy=cy1;iz=cz2;y[id]+=(ry-rz)*l*x[iz*ny*nx+iy*nx+ix];
                                        }
                                        else
                                        {
                                        }
                                    }
                                    if(cz2==nz)// 44
                                    {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                        ry=(cy2-yy1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                        if(ry>rz)
                                        {   iy=cy1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];
                                        }
                                        else
                                        {   iy=cy1;iz=cz1;y[id]+=ry*l*x[iz*ny*nx+iy*nx+ix];
                                        }
                                    }
                                }
                            }
                        }
                    }
                }
            }
        }
        else
        {   slope1=(x2-x1)/(y2-y1);
            slope2=(z2-z1)/(y2-y1);
            for(iy=0;iy<ny;iy++)
            {   yy1=(float)(iy-ny2);yy2=yy1+1;
                if(slope1>=0)
                {   xx1=x1+slope1*(yy1-y1)+nx2;
                    xx2=x1+slope1*(yy2-y1)+nx2;
                }
                else
                {   xx1=x1+slope1*(yy2-y1)+nx2;
                    xx2=x1+slope1*(yy1-y1)+nx2;
                }
                cx1=(int)floor(xx1);
                cx2=(int)floor(xx2);
                if(slope2>=0)
                {   zz1=(z1+slope2*(yy1-y1))/dz+nz2;
                    zz2=(z1+slope2*(yy2-y1))/dz+nz2;
                }
                else
                {   zz1=(z1+slope2*(yy2-y1))/dz+nz2;
                    zz2=(z1+slope2*(yy1-y1))/dz+nz2;
                }
                cz1=(int)floor(zz1);
                cz2=(int)floor(zz2);

                if(cx2==cx1)
                {   if(cx1>=0&&cx1<=nx-1)
                    {   if(cz2==cz1)
                        {   if(cz1>=0&&cz1<=nz-1)// 11
                            {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                ix=cx1;iz=cz1;y[id]+=l*x[iz*ny*nx+iy*nx+ix];
                            }
                        }
                        else
                        {   if(cz2>0&&cz2<nz)// 12
                            {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                rz=(cz2-zz1)/(zz2-zz1);
                                ix=cx1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];
                                ix=cx1;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];
                            }
                            else
                            {   if(cz2==0)// 13
                                {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    rz=(cz2-zz1)/(zz2-zz1);
                                    ix=cx1;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];
                                }
                                if(cz2==nz)// 14
                                {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    rz=(cz2-zz1)/(zz2-zz1);
                                    ix=cx1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];
                                }
                            }
                        }
                    }
                }
                else
                {   if(cx2>0&&cx2<nx)
                    {   if(cz2==cz1)
                        {   if(cz1>=0&&cz1<=nz-1)// 21
                            {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                rx=(cx2-xx1)/d;
                                ix=cx1;iz=cz1;y[id]+=rx*l*x[iz*ny*nx+iy*nx+ix];
                                ix=cx2;iz=cz1;y[id]+=(1-rx)*l*x[iz*ny*nx+iy*nx+ix];
                            }
                        }
                        else
                        {   if(cz2>0&&cz2<nz)// 22
                            {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                rx=(cx2-xx1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                if(rx>rz)
                                {   ix=cx1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];
                                    ix=cx1;iz=cz2;y[id]+=(rx-rz)*l*x[iz*ny*nx+iy*nx+ix];
                                    ix=cx2;iz=cz2;y[id]+=(1-rx)*l*x[iz*ny*nx+iy*nx+ix];
                                }
                                else
                                {   ix=cx1;iz=cz1;y[id]+=rx*l*x[iz*ny*nx+iy*nx+ix];
                                    ix=cx2;iz=cz1;y[id]+=(rz-rx)*l*x[iz*ny*nx+iy*nx+ix];
                                    ix=cx2;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];
                                }
                            }
                            else
                            {   if(cz2==0)// 23
                                {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    rx=(cx2-xx1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                    if(rx>rz)
                                    {   ix=cx1;iz=cz2;y[id]+=(rx-rz)*l*x[iz*ny*nx+iy*nx+ix];
                                        ix=cx2;iz=cz2;y[id]+=(1-rx)*l*x[iz*ny*nx+iy*nx+ix];
                                    }
                                    else
                                    {   ix=cx2;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];
                                    }
                                }
                                if(cz2==nz)// 24
                                {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    rx=(cx2-xx1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                    if(rx>rz)
                                    {   ix=cx1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];
                                    }
                                    else
                                    {   ix=cx1;iz=cz1;y[id]+=rx*l*x[iz*ny*nx+iy*nx+ix];
                                        ix=cx2;iz=cz1;y[id]+=(rz-rx)*l*x[iz*ny*nx+iy*nx+ix];
                                    }
                                }
                            }
                        }
                    }
                    else
                    {   if(cx2==0)
                        {   if(cz2==cz1)
                            {   if(cz1>=0&&cz1<=nz-1)// 31
                                {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    rx=(cx2-xx1)/d;
                                    ix=cx2;iz=cz1;y[id]+=(1-rx)*l*x[iz*ny*nx+iy*nx+ix];
                                }
                            }
                            else
                            {   if(cz2>0&&cz2<nz)// 32
                                {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    rx=(cx2-xx1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                    if(rx>rz)
                                    {   ix=cx2;iz=cz2;y[id]+=(1-rx)*l*x[iz*ny*nx+iy*nx+ix];
                                    }
                                    else
                                    {   ix=cx2;iz=cz1;y[id]+=(rz-rx)*l*x[iz*ny*nx+iy*nx+ix];
                                        ix=cx2;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];
                                    }
                                }
                                else
                                {   if(cz2==0)// 33
                                    {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                        rx=(cx2-xx1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                        if(rx>rz)
                                        {   ix=cx2;iz=cz2;y[id]+=(1-rx)*l*x[iz*ny*nx+iy*nx+ix];
                                        }
                                        else
                                        {   ix=cx2;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];
                                        }
                                    }
                                    if(cz2==nz)// 34
                                    {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                        rx=(cx2-xx1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                        if(rx>rz)
                                        {
                                        }
                                        else
                                        {   ix=cx2;iz=cz1;y[id]+=(rz-rx)*l*x[iz*ny*nx+iy*nx+ix];
                                        }
                                    }
                                }
                            }
                        }

                        if(cx2==nx)
                        {   if(cz2==cz1)
                            {   if(cz1>=0&&cz1<=nz-1)// 41
                                {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    rx=(cx2-xx1)/d;
                                    ix=cx1;iz=cz1;y[id]+=rx*l*x[iz*ny*nx+iy*nx+ix];
                                }
                            }
                            else
                            {   if(cz2>0&&cz2<nz)// 42
                                {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    rx=(cx2-xx1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                    if(rx>rz)
                                    {   ix=cx1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];
                                        ix=cx1;iz=cz2;y[id]+=(rx-rz)*l*x[iz*ny*nx+iy*nx+ix];
                                    }
                                    else
                                    {   ix=cx1;iz=cz1;y[id]+=rx*l*x[iz*ny*nx+iy*nx+ix];
                                    }
                                }
                                else
                                {   if(cz2==0)// 43
                                    {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                        rx=(cx2-xx1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                        if(rx>rz)
                                        {   ix=cx1;iz=cz2;y[id]+=(rx-rz)*l*x[iz*ny*nx+iy*nx+ix];
                                        }
                                        else
                                        {
                                        }
                                    }
                                    if(cz2==nz)// 44
                                    {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                        rx=(cx2-xx1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                        if(rx>rz)
                                        {   ix=cx1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];
                                        }
                                        else
                                        {   ix=cx1;iz=cz1;y[id]+=rx*l*x[iz*ny*nx+iy*nx+ix];
                                        }
                                    }
                                }
                            }
                        }
                    }
                }
            }
        }
        y[id]*=scale;
        yNorm[id] = y[id]/norm;
    }
}

void Ax_cone_mf_gpu_new(float *X,float *y,float *yNorm,float *sd_phi,float *sd_z,float *y_det,float *z_det,int *id_Y,int *Nv,
float SO,float OD,float scale,float dz,int nx,int ny,int nz,int nt,int na,int nb,int nv,int tmp_size,int nv_block)
//assuming dx=dy; during the computation, dx=dy=1; after the computation, the "dx=dy=scale" is taken into account.
//the input can be multiple 3D images, e.g., temporally-resolved images from 4DCT.
//the user needs to supply
//      "id_X" -- the image index for each projection
//      "id_Y" -- the projection index for each image
//      "nv_block" -- to deal with the GPU time limit
{   float *y_d,*yNorm_d,*x_d,*sd_phi_d,*sd_z_d,*y_det_d,*z_det_d;
	int *id_Y_d,nd,N,id,v0,it,i,n,nv2;

	N=nx*ny*nz;
	nd=na*nb;

	cudaMalloc(&y_d,nv_block*nd*sizeof(float));
    cudaMalloc(&yNorm_d,nv_block*nd*sizeof(float));
	cudaMalloc(&x_d,N*sizeof(float));

	cudaMalloc(&sd_phi_d,nv*sizeof(float));
    cudaMemcpy(sd_phi_d,sd_phi,nv*sizeof(float),cudaMemcpyHostToDevice);
	cudaMalloc(&sd_z_d,nv*sizeof(float));
    cudaMemcpy(sd_z_d,sd_z,nv*sizeof(float),cudaMemcpyHostToDevice);
	cudaMalloc(&y_det_d,na*sizeof(float));
    cudaMemcpy(y_det_d,y_det,na*sizeof(float),cudaMemcpyHostToDevice);
	cudaMalloc(&z_det_d,nb*sizeof(float));
    cudaMemcpy(z_det_d,z_det,nb*sizeof(float),cudaMemcpyHostToDevice);
	cudaMalloc(&id_Y_d,nt*tmp_size*sizeof(int));
    cudaMemcpy(id_Y_d,id_Y,nt*tmp_size*sizeof(int),cudaMemcpyHostToDevice);

	dim3 dimBlock(BLOCK_SIZE_x,BLOCK_SIZE_y);

	id=0;
	for(it=0;it<nt;it++)
	{	cudaMemcpy(x_d,&X[it*N],N*sizeof(float),cudaMemcpyHostToDevice);
		n=(Nv[it]+nv_block-1)/nv_block;
		v0=0;
		for(i=0;i<n;i++)
		{	if(i<n-1)
			{nv2=nv_block;}
			else
			{nv2=Nv[it]-nv_block*(n-1);}
			dim3 dimGrid_t((na+dimBlock.x-1)/dimBlock.x,(nv2*nb+dimBlock.y-1)/dimBlock.y);
			Ax_cone_mf_gpu_kernel_new<<<dimGrid_t, dimBlock>>>(x_d,y_d,yNorm_d,sd_phi_d,sd_z_d,y_det_d,z_det_d,&id_Y_d[it*tmp_size+v0],
			SO,OD,scale,dz,nx,ny,nz,na,nb,nv2);
			cudaThreadSynchronize();
			cudaMemcpy(&y[id*nd],y_d,nv2*nd*sizeof(float),cudaMemcpyDeviceToHost);
            cudaMemcpy(&yNorm[id*nd],yNorm_d,nv2*nd*sizeof(float),cudaMemcpyDeviceToHost);
			v0+=nv2;id+=nv2;
		}
	}

    cudaFree(y_d);cudaFree(yNorm_d);cudaFree(x_d);cudaFree(sd_phi_d);cudaFree(sd_z_d);cudaFree(y_det_d);cudaFree(z_det_d);cudaFree(id_Y_d);
}

	.file	"tmpxft_002d6179_00000000-6_Ax_cone_mf_gpu_new.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0, @function
_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0:
.LFB2173:
	.cfi_startproc
	jmp	cudaMalloc@PLT
	.cfi_endproc
.LFE2173:
	.size	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0, .-_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	.globl	_Z69__device_stub__Z25Ax_cone_mf_gpu_kernel_newPfS_S_S_S_S_S_PiffffiiiiiiPfS_S_S_S_S_S_Piffffiiiiii
	.type	_Z69__device_stub__Z25Ax_cone_mf_gpu_kernel_newPfS_S_S_S_S_S_PiffffiiiiiiPfS_S_S_S_S_S_Piffffiiiiii, @function
_Z69__device_stub__Z25Ax_cone_mf_gpu_kernel_newPfS_S_S_S_S_S_PiffffiiiiiiPfS_S_S_S_S_S_Piffffiiiiii:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$312, %rsp
	.cfi_def_cfa_offset 320
	movq	320(%rsp), %rax
	movq	%rdi, 72(%rsp)
	leaq	104(%rsp), %rdi
	movq	%rsi, 64(%rsp)
	leaq	116(%rsp), %rsi
	movq	%rax, 24(%rsp)
	movq	328(%rsp), %rax
	movq	%rdx, 56(%rsp)
	leaq	88(%rsp), %rdx
	movq	%rcx, 48(%rsp)
	leaq	96(%rsp), %rcx
	movq	%r8, 40(%rsp)
	movq	%r9, 32(%rsp)
	movq	%rax, 16(%rsp)
	movss	%xmm0, 12(%rsp)
	movss	%xmm1, 8(%rsp)
	movss	%xmm2, 4(%rsp)
	movss	%xmm3, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 296(%rsp)
	xorl	%eax, %eax
	leaq	72(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 232(%rsp)
	movq	%rsp, %rax
	movq	%rax, 240(%rsp)
	leaq	336(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	344(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	352(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	360(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	368(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	376(%rsp), %rax
	movq	%rax, 288(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 104(%rsp)
	movl	$1, 112(%rsp)
	movq	%rax, 116(%rsp)
	movl	$1, 124(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L3
	pushq	96(%rsp)
	.cfi_def_cfa_offset 328
	leaq	_Z25Ax_cone_mf_gpu_kernel_newPfS_S_S_S_S_S_Piffffiiiiii(%rip), %rdi
	pushq	96(%rsp)
	.cfi_def_cfa_offset 336
	movq	132(%rsp), %rcx
	movl	140(%rsp), %r8d
	movq	120(%rsp), %rsi
	movl	128(%rsp), %edx
	leaq	168(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 328
	popq	%rdx
	.cfi_def_cfa_offset 320
.L3:
	movq	296(%rsp), %rax
	subq	%fs:40, %rax
	je	.L5
	call	__stack_chk_fail@PLT
.L5:
	addq	$312, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z69__device_stub__Z25Ax_cone_mf_gpu_kernel_newPfS_S_S_S_S_S_PiffffiiiiiiPfS_S_S_S_S_S_Piffffiiiiii, .-_Z69__device_stub__Z25Ax_cone_mf_gpu_kernel_newPfS_S_S_S_S_S_PiffffiiiiiiPfS_S_S_S_S_S_Piffffiiiiii
	.globl	_Z25Ax_cone_mf_gpu_kernel_newPfS_S_S_S_S_S_Piffffiiiiii
	.type	_Z25Ax_cone_mf_gpu_kernel_newPfS_S_S_S_S_S_Piffffiiiiii, @function
_Z25Ax_cone_mf_gpu_kernel_newPfS_S_S_S_S_S_Piffffiiiiii:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z69__device_stub__Z25Ax_cone_mf_gpu_kernel_newPfS_S_S_S_S_S_PiffffiiiiiiPfS_S_S_S_S_S_Piffffiiiiii
	.cfi_endproc
.LFE2053:
	.size	_Z25Ax_cone_mf_gpu_kernel_newPfS_S_S_S_S_S_Piffffiiiiii, .-_Z25Ax_cone_mf_gpu_kernel_newPfS_S_S_S_S_S_Piffffiiiiii
	.globl	Ax_cone_mf_gpu_new
	.type	Ax_cone_mf_gpu_new, @function
Ax_cone_mf_gpu_new:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rdi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rcx, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%r8, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%r9, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$200, %rsp
	.cfi_def_cfa_offset 256
	movq	264(%rsp), %rax
	movq	%rdx, 56(%rsp)
	leaq	96(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	movq	256(%rsp), %r15
	movq	%rax, 8(%rsp)
	movq	272(%rsp), %rax
	movss	%xmm0, 64(%rsp)
	movl	280(%rsp), %ebx
	imull	288(%rsp), %ebx
	movq	%rax, 24(%rsp)
	imull	296(%rsp), %ebx
	movss	%xmm1, 68(%rsp)
	movss	%xmm2, 72(%rsp)
	movss	%xmm3, 76(%rsp)
	movslq	%ebx, %rbx
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	movl	312(%rsp), %eax
	imull	320(%rsp), %eax
	movl	%eax, 32(%rsp)
	movl	344(%rsp), %esi
	imull	%eax, %esi
	movslq	%esi, %rsi
	salq	$2, %rsi
	movq	%rsi, (%rsp)
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	movq	(%rsp), %rsi
	leaq	104(%rsp), %rdi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	0(,%rbx,4), %rax
	leaq	112(%rsp), %rdi
	movq	%rax, %rsi
	movq	%rax, (%rsp)
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	movslq	328(%rsp), %rbx
	leaq	120(%rsp), %rdi
	salq	$2, %rbx
	movq	%rbx, %rsi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	movq	120(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r13, %rsi
	movl	$1, %ecx
	xorl	%r13d, %r13d
	call	cudaMemcpy@PLT
	movq	%rbx, %rsi
	leaq	128(%rsp), %rdi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%r12, %rsi
	movq	128(%rsp), %rdi
	call	cudaMemcpy@PLT
	movslq	312(%rsp), %rbx
	leaq	136(%rsp), %rdi
	salq	$2, %rbx
	movq	%rbx, %rsi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%rbp, %rsi
	movq	136(%rsp), %rdi
	xorl	%ebp, %ebp
	call	cudaMemcpy@PLT
	movslq	320(%rsp), %rbx
	leaq	144(%rsp), %rdi
	salq	$2, %rbx
	movq	%rbx, %rsi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	movq	%rbx, %rdx
	movl	$1, %ecx
	movq	%r15, %rsi
	movq	144(%rsp), %rdi
	xorl	%r15d, %r15d
	call	cudaMemcpy@PLT
	movl	304(%rsp), %ebx
	imull	336(%rsp), %ebx
	leaq	152(%rsp), %rdi
	movslq	%ebx, %rbx
	salq	$2, %rbx
	movq	%rbx, %rsi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	movq	8(%rsp), %rsi
	movl	$1, %ecx
	movq	%rbx, %rdx
	movq	152(%rsp), %rdi
	call	cudaMemcpy@PLT
	movl	312(%rsp), %eax
	movq	%r14, 16(%rsp)
	movl	$1, 168(%rsp)
	addl	$15, %eax
	shrl	$4, %eax
	movl	%eax, 44(%rsp)
.L10:
	cmpl	%ebp, 304(%rsp)
	jle	.L19
	movq	(%rsp), %rdx
	movq	16(%rsp), %rsi
	xorl	%r12d, %r12d
	xorl	%r14d, %r14d
	movq	112(%rsp), %rdi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rcx
	movl	344(%rsp), %eax
	addl	(%rcx,%rbp,4), %eax
	decl	%eax
	cltd
	idivl	344(%rsp)
	movl	%eax, 36(%rsp)
	decl	%eax
	movl	%eax, 8(%rsp)
	imull	344(%rsp), %eax
	movl	%eax, 40(%rsp)
.L11:
	movl	36(%rsp), %eax
	cmpl	%eax, %r12d
	jge	.L20
	movl	344(%rsp), %ebx
	cmpl	%r12d, 8(%rsp)
	jg	.L12
	movq	24(%rsp), %rax
	movl	(%rax,%rbp,4), %eax
	movl	%eax, %ebx
	movl	%eax, 80(%rsp)
	movl	40(%rsp), %eax
	subl	%eax, %ebx
.L12:
	movl	44(%rsp), %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %esi
	movl	168(%rsp), %ecx
	movabsq	$68719476752, %rdx
	movl	%eax, 172(%rsp)
	movl	320(%rsp), %eax
	imull	%ebx, %eax
	addl	$15, %eax
	shrl	$4, %eax
	movl	%eax, 176(%rsp)
	movq	172(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	%rbx
	.cfi_def_cfa_offset 264
	movl	328(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 272
	movl	328(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 280
	movl	320(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 288
	movl	320(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 296
	movl	320(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 304
	leal	0(%r13,%r14), %eax
	movq	200(%rsp), %rdx
	cltq
	leaq	(%rdx,%rax,4), %rax
	pushq	%rax
	.cfi_def_cfa_offset 312
	pushq	200(%rsp)
	.cfi_def_cfa_offset 320
	movq	200(%rsp), %r9
	movss	140(%rsp), %xmm3
	movq	192(%rsp), %r8
	movq	184(%rsp), %rcx
	movq	168(%rsp), %rdx
	movq	160(%rsp), %rsi
	movss	136(%rsp), %xmm2
	movss	132(%rsp), %xmm1
	movss	128(%rsp), %xmm0
	movq	176(%rsp), %rdi
	call	_Z69__device_stub__Z25Ax_cone_mf_gpu_kernel_newPfS_S_S_S_S_S_PiffffiiiiiiPfS_S_S_S_S_S_Piffffiiiiii
	addq	$64, %rsp
	.cfi_def_cfa_offset 256
.L13:
	call	cudaThreadSynchronize@PLT
	movl	32(%rsp), %r8d
	movl	32(%rsp), %edx
	movl	$2, %ecx
	movq	48(%rsp), %rax
	movq	96(%rsp), %rsi
	addl	%ebx, %r14d
	incl	%r12d
	imull	%r15d, %r8d
	addl	%ebx, %r15d
	imull	%ebx, %edx
	movslq	%r8d, %r8
	salq	$2, %r8
	movslq	%edx, %rdx
	salq	$2, %rdx
	leaq	(%rax,%r8), %rdi
	movq	%r8, 88(%rsp)
	movq	%rdx, 80(%rsp)
	call	cudaMemcpy@PLT
	movq	56(%rsp), %rax
	movq	88(%rsp), %r8
	movl	$2, %ecx
	movq	80(%rsp), %rdx
	movq	104(%rsp), %rsi
	leaq	(%rax,%r8), %rdi
	call	cudaMemcpy@PLT
	jmp	.L11
.L20:
	movq	(%rsp), %rcx
	incq	%rbp
	addq	%rcx, 16(%rsp)
	addl	336(%rsp), %r13d
	jmp	.L10
.L19:
	movq	96(%rsp), %rdi
	call	cudaFree@PLT
	movq	104(%rsp), %rdi
	call	cudaFree@PLT
	movq	112(%rsp), %rdi
	call	cudaFree@PLT
	movq	120(%rsp), %rdi
	call	cudaFree@PLT
	movq	128(%rsp), %rdi
	call	cudaFree@PLT
	movq	136(%rsp), %rdi
	call	cudaFree@PLT
	movq	144(%rsp), %rdi
	call	cudaFree@PLT
	movq	152(%rsp), %rdi
	call	cudaFree@PLT
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L16
	call	__stack_chk_fail@PLT
.L16:
	addq	$200, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	Ax_cone_mf_gpu_new, .-Ax_cone_mf_gpu_new
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z25Ax_cone_mf_gpu_kernel_newPfS_S_S_S_S_S_Piffffiiiiii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z25Ax_cone_mf_gpu_kernel_newPfS_S_S_S_S_S_Piffffiiiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

// *----------------------------------------------
// 	Author Contact Information:
// 	Hao Gao
// 	hao.gao@emory.edu || hao.gao.2012@gmail.com
// 	Department of Mathematics and Computer Science, Emory University
// 	Department of Radiology and Imaging Sciences, Emory University
//
// 	Copyright (c) Hao Gao 2012
// ----------------------------------------------*/
//
// If you find this code useful, you may cite the following reference:
// H. Gao. "Fast parallel algorithms for the X-ray transform and its adjoint", Medical Physics (2012).
// The full source codes are available at https://sites.google.com/site/fastxraytransform


#include <hip/hip_runtime.h>
#include <math.h>
#include <malloc.h>
#define ABS(a) (a>0?a:-(a))

#define BLOCK_SIZE_x 16
#define BLOCK_SIZE_y 16

extern "C" void Ax_cone_mf_gpu_new(float *X,float *y,float *yNorm,float *sd_phi,float *sd_z,float *y_det,float *z_det,int *id_Y,int *Nv,
float SO,float OD,float scale,float dz,int nx,int ny,int nz,int nt,int na,int nb,int nv,int tmp_size,int nv_block);

__global__ void Ax_cone_mf_gpu_kernel_new(float *x,float *y,float *yNorm,float *sd_phi,float *sd_z,float *y_det,float *z_det,int *id_Y,
float SO,float OD,float scale,float dz,int nx,int ny,int nz,int na,int nb,int nv2)
// Please note that this version has O(Nx) per thread, since GPU threads are already saturated.
// O(1) per thread can be achieved by parallelizing the "for" loop here, given sufficient number of GPU threads.
{
	int bx=blockIdx.x;
	int by=blockIdx.y;
	int tx0=threadIdx.x;
	int ty0=threadIdx.y;

	int ia=bx*BLOCK_SIZE_x+tx0;
	int ib2=by*BLOCK_SIZE_y+ty0;

    if(ia<na&&ib2<nb*nv2)
    {
		int nd,nx2,ny2,nz2,iv0,iv,ib,id,ix,iy,iz,cx1,cx2,cy1,cy2,cz1,cz2;
		float norm,cos_phi,sin_phi,x1,y1,x2,y2,z1,z2,xx1,yy1,zz1,xx2,yy2,zz2,slope1,slope2,l,d,tmp,rx,ry,rz;

		nx2=nx/2;ny2=ny/2;nz2=nz/2;
		nd=na*nb;

		iv0=(int)floor((float)ib2/(float)nb);
		ib=ib2-iv0*nb;
		iv=id_Y[iv0];
		id=iv0*nd+ib*na+ia;

        cos_phi=cosf(sd_phi[iv]);sin_phi=sinf(sd_phi[iv]);
        x1=cos_phi*(-SO);
        y1=sin_phi*(-SO);
        z1=sd_z[iv];
		x2=cos_phi*OD-sin_phi*y_det[ia];
        y2=sin_phi*OD+cos_phi*y_det[ia];
		z2=z_det[ib]+sd_z[iv];
        norm = sqrt(pow(x1-x2,2)+pow(y1-y2,2)+pow(z1-z2,2))*scale;

		y[id]=0;
        // assuming z1-z2 is small
        if(ABS(x1-x2)>ABS(y1-y2))
        {   slope1=(y2-y1)/(x2-x1);
            slope2=(z2-z1)/(x2-x1);
            for(ix=0;ix<nx;ix++)
            {   xx1=(float)(ix-nx2);xx2=xx1+1;
                if(slope1>=0)
                {   yy1=y1+slope1*(xx1-x1)+ny2;
                    yy2=y1+slope1*(xx2-x1)+ny2;
                }
                else
                {   yy1=y1+slope1*(xx2-x1)+ny2;
                    yy2=y1+slope1*(xx1-x1)+ny2;
                }
                cy1=(int)floor(yy1);
                cy2=(int)floor(yy2);
                if(slope2>=0)
                {   zz1=(z1+slope2*(xx1-x1))/dz+nz2;
                    zz2=(z1+slope2*(xx2-x1))/dz+nz2;
                }
                else
                {   zz1=(z1+slope2*(xx2-x1))/dz+nz2;
                    zz2=(z1+slope2*(xx1-x1))/dz+nz2;
                }
                cz1=(int)floor(zz1);
                cz2=(int)floor(zz2);

                if(cy2==cy1)
                {   if(cy1>=0&&cy1<=ny-1)
                    {   if(cz2==cz1)
                        {   if(cz1>=0&&cz1<=nz-1)// 11
                            {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                iy=cy1;iz=cz1;y[id]+=l*x[iz*ny*nx+iy*nx+ix];
                            }
                        }
                        else
                        {   if(cz2>0&&cz2<nz)// 12
                            {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                rz=(cz2-zz1)/(zz2-zz1);
                                iy=cy1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];
                                iy=cy1;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];
                            }
                            else
                            {   if(cz2==0)// 13
                                {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    rz=(cz2-zz1)/(zz2-zz1);
                                    iy=cy1;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];
                                }
                                if(cz2==nz)// 14
                                {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    rz=(cz2-zz1)/(zz2-zz1);
                                    iy=cy1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];
                                }
                            }
                        }
                    }
                }
                else
                {   if(cy2>0&&cy2<ny)
                    {   if(cz2==cz1)
                        {   if(cz1>=0&&cz1<=nz-1)// 21
                            {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                ry=(cy2-yy1)/d;
                                iy=cy1;iz=cz1;y[id]+=ry*l*x[iz*ny*nx+iy*nx+ix];
                                iy=cy2;iz=cz1;y[id]+=(1-ry)*l*x[iz*ny*nx+iy*nx+ix];
                            }
                        }
                        else
                        {   if(cz2>0&&cz2<nz)// 22
                            {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                ry=(cy2-yy1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                if(ry>rz)
                                {   iy=cy1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];
                                    iy=cy1;iz=cz2;y[id]+=(ry-rz)*l*x[iz*ny*nx+iy*nx+ix];
                                    iy=cy2;iz=cz2;y[id]+=(1-ry)*l*x[iz*ny*nx+iy*nx+ix];
                                }
                                else
                                {   iy=cy1;iz=cz1;y[id]+=ry*l*x[iz*ny*nx+iy*nx+ix];
                                    iy=cy2;iz=cz1;y[id]+=(rz-ry)*l*x[iz*ny*nx+iy*nx+ix];
                                    iy=cy2;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];
                                }
                            }
                            else
                            {   if(cz2==0)// 23
                                {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    ry=(cy2-yy1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                    if(ry>rz)
                                    {   iy=cy1;iz=cz2;y[id]+=(ry-rz)*l*x[iz*ny*nx+iy*nx+ix];
                                        iy=cy2;iz=cz2;y[id]+=(1-ry)*l*x[iz*ny*nx+iy*nx+ix];
                                    }
                                    else
                                    {   iy=cy2;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];
                                    }
                                }
                                if(cz2==nz)// 24
                                {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    ry=(cy2-yy1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                    if(ry>rz)
                                    {   iy=cy1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];
                                    }
                                    else
                                    {   iy=cy1;iz=cz1;y[id]+=ry*l*x[iz*ny*nx+iy*nx+ix];
                                        iy=cy2;iz=cz1;y[id]+=(rz-ry)*l*x[iz*ny*nx+iy*nx+ix];
                                    }
                                }
                            }
                        }
                    }
                    else
                    {   if(cy2==0)
                        {   if(cz2==cz1)
                            {   if(cz1>=0&&cz1<=nz-1)// 31
                                {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    ry=(cy2-yy1)/d;
                                    iy=cy2;iz=cz1;y[id]+=(1-ry)*l*x[iz*ny*nx+iy*nx+ix];
                                }
                            }
                            else
                            {   if(cz2>0&&cz2<nz)// 32
                                {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    ry=(cy2-yy1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                    if(ry>rz)
                                    {   iy=cy2;iz=cz2;y[id]+=(1-ry)*l*x[iz*ny*nx+iy*nx+ix];
                                    }
                                    else
                                    {   iy=cy2;iz=cz1;y[id]+=(rz-ry)*l*x[iz*ny*nx+iy*nx+ix];
                                        iy=cy2;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];
                                    }
                                }
                                else
                                {   if(cz2==0)// 33
                                    {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                        ry=(cy2-yy1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                        if(ry>rz)
                                        {   iy=cy2;iz=cz2;y[id]+=(1-ry)*l*x[iz*ny*nx+iy*nx+ix];
                                        }
                                        else
                                        {   iy=cy2;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];
                                        }
                                    }
                                    if(cz2==nz)// 34
                                    {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                        ry=(cy2-yy1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                        if(ry>rz)
                                        {
                                        }
                                        else
                                        {   iy=cy2;iz=cz1;y[id]+=(rz-ry)*l*x[iz*ny*nx+iy*nx+ix];
                                        }
                                    }
                                }
                            }
                        }

                        if(cy2==ny)
                        {   if(cz2==cz1)
                            {   if(cz1>=0&&cz1<=nz-1)// 41
                                {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    ry=(cy2-yy1)/d;
                                    iy=cy1;iz=cz1;y[id]+=ry*l*x[iz*ny*nx+iy*nx+ix];
                                }
                            }
                            else
                            {   if(cz2>0&&cz2<nz)// 42
                                {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    ry=(cy2-yy1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                    if(ry>rz)
                                    {   iy=cy1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];
                                        iy=cy1;iz=cz2;y[id]+=(ry-rz)*l*x[iz*ny*nx+iy*nx+ix];
                                    }
                                    else
                                    {   iy=cy1;iz=cz1;y[id]+=ry*l*x[iz*ny*nx+iy*nx+ix];
                                    }
                                }
                                else
                                {   if(cz2==0)// 43
                                    {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                        ry=(cy2-yy1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                        if(ry>rz)
                                        {   iy=cy1;iz=cz2;y[id]+=(ry-rz)*l*x[iz*ny*nx+iy*nx+ix];
                                        }
                                        else
                                        {
                                        }
                                    }
                                    if(cz2==nz)// 44
                                    {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                        ry=(cy2-yy1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                        if(ry>rz)
                                        {   iy=cy1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];
                                        }
                                        else
                                        {   iy=cy1;iz=cz1;y[id]+=ry*l*x[iz*ny*nx+iy*nx+ix];
                                        }
                                    }
                                }
                            }
                        }
                    }
                }
            }
        }
        else
        {   slope1=(x2-x1)/(y2-y1);
            slope2=(z2-z1)/(y2-y1);
            for(iy=0;iy<ny;iy++)
            {   yy1=(float)(iy-ny2);yy2=yy1+1;
                if(slope1>=0)
                {   xx1=x1+slope1*(yy1-y1)+nx2;
                    xx2=x1+slope1*(yy2-y1)+nx2;
                }
                else
                {   xx1=x1+slope1*(yy2-y1)+nx2;
                    xx2=x1+slope1*(yy1-y1)+nx2;
                }
                cx1=(int)floor(xx1);
                cx2=(int)floor(xx2);
                if(slope2>=0)
                {   zz1=(z1+slope2*(yy1-y1))/dz+nz2;
                    zz2=(z1+slope2*(yy2-y1))/dz+nz2;
                }
                else
                {   zz1=(z1+slope2*(yy2-y1))/dz+nz2;
                    zz2=(z1+slope2*(yy1-y1))/dz+nz2;
                }
                cz1=(int)floor(zz1);
                cz2=(int)floor(zz2);

                if(cx2==cx1)
                {   if(cx1>=0&&cx1<=nx-1)
                    {   if(cz2==cz1)
                        {   if(cz1>=0&&cz1<=nz-1)// 11
                            {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                ix=cx1;iz=cz1;y[id]+=l*x[iz*ny*nx+iy*nx+ix];
                            }
                        }
                        else
                        {   if(cz2>0&&cz2<nz)// 12
                            {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                rz=(cz2-zz1)/(zz2-zz1);
                                ix=cx1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];
                                ix=cx1;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];
                            }
                            else
                            {   if(cz2==0)// 13
                                {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    rz=(cz2-zz1)/(zz2-zz1);
                                    ix=cx1;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];
                                }
                                if(cz2==nz)// 14
                                {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    rz=(cz2-zz1)/(zz2-zz1);
                                    ix=cx1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];
                                }
                            }
                        }
                    }
                }
                else
                {   if(cx2>0&&cx2<nx)
                    {   if(cz2==cz1)
                        {   if(cz1>=0&&cz1<=nz-1)// 21
                            {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                rx=(cx2-xx1)/d;
                                ix=cx1;iz=cz1;y[id]+=rx*l*x[iz*ny*nx+iy*nx+ix];
                                ix=cx2;iz=cz1;y[id]+=(1-rx)*l*x[iz*ny*nx+iy*nx+ix];
                            }
                        }
                        else
                        {   if(cz2>0&&cz2<nz)// 22
                            {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                rx=(cx2-xx1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                if(rx>rz)
                                {   ix=cx1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];
                                    ix=cx1;iz=cz2;y[id]+=(rx-rz)*l*x[iz*ny*nx+iy*nx+ix];
                                    ix=cx2;iz=cz2;y[id]+=(1-rx)*l*x[iz*ny*nx+iy*nx+ix];
                                }
                                else
                                {   ix=cx1;iz=cz1;y[id]+=rx*l*x[iz*ny*nx+iy*nx+ix];
                                    ix=cx2;iz=cz1;y[id]+=(rz-rx)*l*x[iz*ny*nx+iy*nx+ix];
                                    ix=cx2;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];
                                }
                            }
                            else
                            {   if(cz2==0)// 23
                                {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    rx=(cx2-xx1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                    if(rx>rz)
                                    {   ix=cx1;iz=cz2;y[id]+=(rx-rz)*l*x[iz*ny*nx+iy*nx+ix];
                                        ix=cx2;iz=cz2;y[id]+=(1-rx)*l*x[iz*ny*nx+iy*nx+ix];
                                    }
                                    else
                                    {   ix=cx2;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];
                                    }
                                }
                                if(cz2==nz)// 24
                                {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    rx=(cx2-xx1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                    if(rx>rz)
                                    {   ix=cx1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];
                                    }
                                    else
                                    {   ix=cx1;iz=cz1;y[id]+=rx*l*x[iz*ny*nx+iy*nx+ix];
                                        ix=cx2;iz=cz1;y[id]+=(rz-rx)*l*x[iz*ny*nx+iy*nx+ix];
                                    }
                                }
                            }
                        }
                    }
                    else
                    {   if(cx2==0)
                        {   if(cz2==cz1)
                            {   if(cz1>=0&&cz1<=nz-1)// 31
                                {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    rx=(cx2-xx1)/d;
                                    ix=cx2;iz=cz1;y[id]+=(1-rx)*l*x[iz*ny*nx+iy*nx+ix];
                                }
                            }
                            else
                            {   if(cz2>0&&cz2<nz)// 32
                                {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    rx=(cx2-xx1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                    if(rx>rz)
                                    {   ix=cx2;iz=cz2;y[id]+=(1-rx)*l*x[iz*ny*nx+iy*nx+ix];
                                    }
                                    else
                                    {   ix=cx2;iz=cz1;y[id]+=(rz-rx)*l*x[iz*ny*nx+iy*nx+ix];
                                        ix=cx2;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];
                                    }
                                }
                                else
                                {   if(cz2==0)// 33
                                    {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                        rx=(cx2-xx1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                        if(rx>rz)
                                        {   ix=cx2;iz=cz2;y[id]+=(1-rx)*l*x[iz*ny*nx+iy*nx+ix];
                                        }
                                        else
                                        {   ix=cx2;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];
                                        }
                                    }
                                    if(cz2==nz)// 34
                                    {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                        rx=(cx2-xx1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                        if(rx>rz)
                                        {
                                        }
                                        else
                                        {   ix=cx2;iz=cz1;y[id]+=(rz-rx)*l*x[iz*ny*nx+iy*nx+ix];
                                        }
                                    }
                                }
                            }
                        }

                        if(cx2==nx)
                        {   if(cz2==cz1)
                            {   if(cz1>=0&&cz1<=nz-1)// 41
                                {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    rx=(cx2-xx1)/d;
                                    ix=cx1;iz=cz1;y[id]+=rx*l*x[iz*ny*nx+iy*nx+ix];
                                }
                            }
                            else
                            {   if(cz2>0&&cz2<nz)// 42
                                {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    rx=(cx2-xx1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                    if(rx>rz)
                                    {   ix=cx1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];
                                        ix=cx1;iz=cz2;y[id]+=(rx-rz)*l*x[iz*ny*nx+iy*nx+ix];
                                    }
                                    else
                                    {   ix=cx1;iz=cz1;y[id]+=rx*l*x[iz*ny*nx+iy*nx+ix];
                                    }
                                }
                                else
                                {   if(cz2==0)// 43
                                    {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                        rx=(cx2-xx1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                        if(rx>rz)
                                        {   ix=cx1;iz=cz2;y[id]+=(rx-rz)*l*x[iz*ny*nx+iy*nx+ix];
                                        }
                                        else
                                        {
                                        }
                                    }
                                    if(cz2==nz)// 44
                                    {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                        rx=(cx2-xx1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                        if(rx>rz)
                                        {   ix=cx1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];
                                        }
                                        else
                                        {   ix=cx1;iz=cz1;y[id]+=rx*l*x[iz*ny*nx+iy*nx+ix];
                                        }
                                    }
                                }
                            }
                        }
                    }
                }
            }
        }
        y[id]*=scale;
        yNorm[id] = y[id]/norm;
    }
}

void Ax_cone_mf_gpu_new(float *X,float *y,float *yNorm,float *sd_phi,float *sd_z,float *y_det,float *z_det,int *id_Y,int *Nv,
float SO,float OD,float scale,float dz,int nx,int ny,int nz,int nt,int na,int nb,int nv,int tmp_size,int nv_block)
//assuming dx=dy; during the computation, dx=dy=1; after the computation, the "dx=dy=scale" is taken into account.
//the input can be multiple 3D images, e.g., temporally-resolved images from 4DCT.
//the user needs to supply
//      "id_X" -- the image index for each projection
//      "id_Y" -- the projection index for each image
//      "nv_block" -- to deal with the GPU time limit
{   float *y_d,*yNorm_d,*x_d,*sd_phi_d,*sd_z_d,*y_det_d,*z_det_d;
	int *id_Y_d,nd,N,id,v0,it,i,n,nv2;

	N=nx*ny*nz;
	nd=na*nb;

	hipMalloc(&y_d,nv_block*nd*sizeof(float));
    hipMalloc(&yNorm_d,nv_block*nd*sizeof(float));
	hipMalloc(&x_d,N*sizeof(float));

	hipMalloc(&sd_phi_d,nv*sizeof(float));
    hipMemcpy(sd_phi_d,sd_phi,nv*sizeof(float),hipMemcpyHostToDevice);
	hipMalloc(&sd_z_d,nv*sizeof(float));
    hipMemcpy(sd_z_d,sd_z,nv*sizeof(float),hipMemcpyHostToDevice);
	hipMalloc(&y_det_d,na*sizeof(float));
    hipMemcpy(y_det_d,y_det,na*sizeof(float),hipMemcpyHostToDevice);
	hipMalloc(&z_det_d,nb*sizeof(float));
    hipMemcpy(z_det_d,z_det,nb*sizeof(float),hipMemcpyHostToDevice);
	hipMalloc(&id_Y_d,nt*tmp_size*sizeof(int));
    hipMemcpy(id_Y_d,id_Y,nt*tmp_size*sizeof(int),hipMemcpyHostToDevice);

	dim3 dimBlock(BLOCK_SIZE_x,BLOCK_SIZE_y);

	id=0;
	for(it=0;it<nt;it++)
	{	hipMemcpy(x_d,&X[it*N],N*sizeof(float),hipMemcpyHostToDevice);
		n=(Nv[it]+nv_block-1)/nv_block;
		v0=0;
		for(i=0;i<n;i++)
		{	if(i<n-1)
			{nv2=nv_block;}
			else
			{nv2=Nv[it]-nv_block*(n-1);}
			dim3 dimGrid_t((na+dimBlock.x-1)/dimBlock.x,(nv2*nb+dimBlock.y-1)/dimBlock.y);
			Ax_cone_mf_gpu_kernel_new<<<dimGrid_t, dimBlock>>>(x_d,y_d,yNorm_d,sd_phi_d,sd_z_d,y_det_d,z_det_d,&id_Y_d[it*tmp_size+v0],
			SO,OD,scale,dz,nx,ny,nz,na,nb,nv2);
			hipDeviceSynchronize();
			hipMemcpy(&y[id*nd],y_d,nv2*nd*sizeof(float),hipMemcpyDeviceToHost);
            hipMemcpy(&yNorm[id*nd],yNorm_d,nv2*nd*sizeof(float),hipMemcpyDeviceToHost);
			v0+=nv2;id+=nv2;
		}
	}

    hipFree(y_d);hipFree(yNorm_d);hipFree(x_d);hipFree(sd_phi_d);hipFree(sd_z_d);hipFree(y_det_d);hipFree(z_det_d);hipFree(id_Y_d);
}

	.text
	.file	"Ax_cone_mf_gpu_new.hip"
	.globl	_Z40__device_stub__Ax_cone_mf_gpu_kernel_newPfS_S_S_S_S_S_Piffffiiiiii # -- Begin function _Z40__device_stub__Ax_cone_mf_gpu_kernel_newPfS_S_S_S_S_S_Piffffiiiiii
	.type	_Z40__device_stub__Ax_cone_mf_gpu_kernel_newPfS_S_S_S_S_S_Piffffiiiiii,@function
_Z40__device_stub__Ax_cone_mf_gpu_kernel_newPfS_S_S_S_S_S_Piffffiiiiii: # @_Z40__device_stub__Ax_cone_mf_gpu_kernel_newPfS_S_S_S_S_S_Piffffiiiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$256, %rsp                      # imm = 0x100
	.cfi_def_cfa_offset 304
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	12(%rsp), %r9
	movss	%xmm0, (%r9)
	leaq	8(%rsp), %r10
	movss	%xmm1, (%r10)
	leaq	4(%rsp), %r11
	movss	%xmm2, (%r11)
	movq	%rsp, %r14
	movss	%xmm3, (%r14)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 56(%rbx)
	movq	%r9, 64(%rbx)
	movq	%r10, 72(%rbx)
	movq	%r11, 80(%rbx)
	movq	%r14, 88(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	328(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	344(%rsp), %rax
	movq	%rax, 120(%rbx)
	leaq	352(%rsp), %rax
	movq	%rax, 128(%rbx)
	leaq	360(%rsp), %rax
	movq	%rax, 136(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z25Ax_cone_mf_gpu_kernel_newPfS_S_S_S_S_S_Piffffiiiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$272, %rsp                      # imm = 0x110
	.cfi_adjust_cfa_offset -272
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z40__device_stub__Ax_cone_mf_gpu_kernel_newPfS_S_S_S_S_S_Piffffiiiiii, .Lfunc_end0-_Z40__device_stub__Ax_cone_mf_gpu_kernel_newPfS_S_S_S_S_S_Piffffiiiiii
	.cfi_endproc
                                        # -- End function
	.globl	Ax_cone_mf_gpu_new              # -- Begin function Ax_cone_mf_gpu_new
	.type	Ax_cone_mf_gpu_new,@function
Ax_cone_mf_gpu_new:                     # @Ax_cone_mf_gpu_new
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$216, %rsp
	.cfi_def_cfa_offset 272
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movss	%xmm3, 76(%rsp)                 # 4-byte Spill
	movss	%xmm2, 72(%rsp)                 # 4-byte Spill
	movss	%xmm1, 68(%rsp)                 # 4-byte Spill
	movss	%xmm0, 64(%rsp)                 # 4-byte Spill
	movq	%r9, 8(%rsp)                    # 8-byte Spill
	movq	%r8, 24(%rsp)                   # 8-byte Spill
	movq	%rcx, 16(%rsp)                  # 8-byte Spill
	movq	%rdx, 208(%rsp)                 # 8-byte Spill
	movq	%rsi, 200(%rsp)                 # 8-byte Spill
	movq	%rdi, 176(%rsp)                 # 8-byte Spill
	movslq	336(%rsp), %r13
	movslq	328(%rsp), %r14
	movl	360(%rsp), %esi
	movl	312(%rsp), %eax
	movl	304(%rsp), %ecx
	movl	296(%rsp), %edx
	movl	%ecx, %r12d
	imull	%edx, %r12d
	imull	%eax, %r12d
	movl	%r13d, %eax
	imull	%r14d, %eax
	movl	%eax, 84(%rsp)                  # 4-byte Spill
	imull	%esi, %eax
	movslq	%eax, %rbp
	shlq	$2, %rbp
	movl	320(%rsp), %ebx
	movslq	344(%rsp), %r15
	leaq	48(%rsp), %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	leaq	40(%rsp), %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	movslq	%r12d, %rax
	movq	%rax, 168(%rsp)                 # 8-byte Spill
	leaq	(,%rax,4), %rsi
	leaq	32(%rsp), %rdi
	movq	%rsi, 160(%rsp)                 # 8-byte Spill
	callq	hipMalloc
	shlq	$2, %r15
	leaq	136(%rsp), %rbp
	movq	%rbp, %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	movq	(%rbp), %rdi
	movq	16(%rsp), %rsi                  # 8-byte Reload
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	128(%rsp), %rbp
	movq	%rbp, %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	movq	(%rbp), %rdi
	movq	24(%rsp), %rsi                  # 8-byte Reload
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%r14, 88(%rsp)                  # 8-byte Spill
	movq	%r14, %r15
	movl	352(%rsp), %r14d
	shlq	$2, %r15
	leaq	120(%rsp), %rbp
	movq	%rbp, %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	movq	(%rbp), %rdi
	movq	8(%rsp), %rsi                   # 8-byte Reload
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%r13, 8(%rsp)                   # 8-byte Spill
	movq	%r13, %r15
	shlq	$2, %r15
	leaq	112(%rsp), %rbp
	movq	%rbp, %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	movq	(%rbp), %rdi
	movq	272(%rsp), %rsi
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	%r14d, %eax
	imull	%ebx, %eax
	movslq	%eax, %r15
	shlq	$2, %r15
	leaq	104(%rsp), %rbp
	movq	%rbp, %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	movq	(%rbp), %rdi
	movq	280(%rsp), %rsi
	movq	%r15, %rdx
	movl	360(%rsp), %r15d
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%ebx, %ebx
	jle	.LBB1_10
# %bb.1:                                # %.lr.ph97
	leal	-1(%r15), %eax
	movl	%eax, 60(%rsp)                  # 4-byte Spill
	movq	88(%rsp), %rax                  # 8-byte Reload
	addl	$15, %eax
	shrl	$4, %eax
	movq	%rax, 192(%rsp)                 # 8-byte Spill
	movslq	%r14d, %rax
	movq	%rax, 144(%rsp)                 # 8-byte Spill
	movl	%ebx, %eax
	movq	%rax, 152(%rsp)                 # 8-byte Spill
	xorl	%ebx, %ebx
	xorl	%r13d, %r13d
.LBB1_2:                                # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_4 Depth 2
	movq	32(%rsp), %rdi
	movq	%rbx, %rax
	imulq	168(%rsp), %rax                 # 8-byte Folded Reload
	movq	176(%rsp), %rcx                 # 8-byte Reload
	leaq	(%rcx,%rax,4), %rsi
	movq	160(%rsp), %rdx                 # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movq	288(%rsp), %rax
	movl	(%rax,%rbx,4), %eax
	addl	60(%rsp), %eax                  # 4-byte Folded Reload
	cltd
	idivl	%r15d
                                        # kill: def $eax killed $eax def $rax
	testl	%eax, %eax
	movq	%rbx, 96(%rsp)                  # 8-byte Spill
	jle	.LBB1_9
# %bb.3:                                # %.lr.ph
                                        #   in Loop: Header=BB1_2 Depth=1
	leal	-1(%rax), %ecx
	movl	%ecx, 16(%rsp)                  # 4-byte Spill
	imull	%r15d, %ecx
	movl	%ecx, 80(%rsp)                  # 4-byte Spill
	imulq	144(%rsp), %rbx                 # 8-byte Folded Reload
	xorl	%r14d, %r14d
	shlq	$2, %rbx
	movq	%rbx, 184(%rsp)                 # 8-byte Spill
	xorl	%r12d, %r12d
	movq	%rax, 24(%rsp)                  # 8-byte Spill
.LBB1_4:                                #   Parent Loop BB1_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	%r15d, %ebx
	cmpl	16(%rsp), %r12d                 # 4-byte Folded Reload
	jl	.LBB1_6
# %bb.5:                                #   in Loop: Header=BB1_4 Depth=2
	movq	288(%rsp), %rax
	movq	96(%rsp), %rcx                  # 8-byte Reload
	movl	(%rax,%rcx,4), %ebx
	subl	80(%rsp), %ebx                  # 4-byte Folded Reload
.LBB1_6:                                #   in Loop: Header=BB1_4 Depth=2
	movl	%ebx, %edi
	imull	8(%rsp), %edi                   # 4-byte Folded Reload
	addl	$15, %edi
	shrl	$4, %edi
	shlq	$32, %rdi
	addq	192(%rsp), %rdi                 # 8-byte Folded Reload
	movl	$1, %esi
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_8
# %bb.7:                                #   in Loop: Header=BB1_4 Depth=2
	movq	32(%rsp), %rdi
	movq	48(%rsp), %rsi
	movq	40(%rsp), %rdx
	movq	136(%rsp), %rcx
	movq	128(%rsp), %r8
	movq	120(%rsp), %r9
	movslq	%r14d, %rax
	movq	104(%rsp), %r10
	addq	184(%rsp), %r10                 # 8-byte Folded Reload
	leaq	(%r10,%rax,4), %rax
	movss	64(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movss	68(%rsp), %xmm1                 # 4-byte Reload
                                        # xmm1 = mem[0],zero,zero,zero
	movss	72(%rsp), %xmm2                 # 4-byte Reload
                                        # xmm2 = mem[0],zero,zero,zero
	movss	76(%rsp), %xmm3                 # 4-byte Reload
                                        # xmm3 = mem[0],zero,zero,zero
	pushq	%rbx
	.cfi_adjust_cfa_offset 8
	pushq	16(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	104(%rsp)                       # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	movl	336(%rsp), %r10d
	pushq	%r10
	.cfi_adjust_cfa_offset 8
	movl	336(%rsp), %r10d
	pushq	%r10
	.cfi_adjust_cfa_offset 8
	movl	336(%rsp), %r10d
	pushq	%r10
	.cfi_adjust_cfa_offset 8
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	168(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z40__device_stub__Ax_cone_mf_gpu_kernel_newPfS_S_S_S_S_S_Piffffiiiiii
	addq	$64, %rsp
	.cfi_adjust_cfa_offset -64
.LBB1_8:                                #   in Loop: Header=BB1_4 Depth=2
	callq	hipDeviceSynchronize
	movl	%r13d, %eax
	movl	84(%rsp), %ecx                  # 4-byte Reload
	imull	%ecx, %eax
	movslq	%eax, %rbp
	movq	200(%rsp), %rax                 # 8-byte Reload
	leaq	(%rax,%rbp,4), %rdi
	movq	48(%rsp), %rsi
	movl	%ebx, %eax
	imull	%ecx, %eax
	movslq	%eax, %r15
	shlq	$2, %r15
	movq	%r15, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	208(%rsp), %rax                 # 8-byte Reload
	leaq	(%rax,%rbp,4), %rdi
	movq	40(%rsp), %rsi
	movq	%r15, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	addl	%ebx, %r14d
	addl	%ebx, %r13d
	incl	%r12d
	movq	24(%rsp), %rax                  # 8-byte Reload
	cmpl	%r12d, %eax
	movl	360(%rsp), %r15d
	jne	.LBB1_4
.LBB1_9:                                # %._crit_edge
                                        #   in Loop: Header=BB1_2 Depth=1
	movq	96(%rsp), %rbx                  # 8-byte Reload
	incq	%rbx
	cmpq	152(%rsp), %rbx                 # 8-byte Folded Reload
	jne	.LBB1_2
.LBB1_10:                               # %._crit_edge98
	movq	48(%rsp), %rdi
	callq	hipFree
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	136(%rsp), %rdi
	callq	hipFree
	movq	128(%rsp), %rdi
	callq	hipFree
	movq	120(%rsp), %rdi
	callq	hipFree
	movq	112(%rsp), %rdi
	callq	hipFree
	movq	104(%rsp), %rdi
	callq	hipFree
	addq	$216, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	Ax_cone_mf_gpu_new, .Lfunc_end1-Ax_cone_mf_gpu_new
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z25Ax_cone_mf_gpu_kernel_newPfS_S_S_S_S_S_Piffffiiiiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z25Ax_cone_mf_gpu_kernel_newPfS_S_S_S_S_S_Piffffiiiiii,@object # @_Z25Ax_cone_mf_gpu_kernel_newPfS_S_S_S_S_S_Piffffiiiiii
	.section	.rodata,"a",@progbits
	.globl	_Z25Ax_cone_mf_gpu_kernel_newPfS_S_S_S_S_S_Piffffiiiiii
	.p2align	3, 0x0
_Z25Ax_cone_mf_gpu_kernel_newPfS_S_S_S_S_S_Piffffiiiiii:
	.quad	_Z40__device_stub__Ax_cone_mf_gpu_kernel_newPfS_S_S_S_S_S_Piffffiiiiii
	.size	_Z25Ax_cone_mf_gpu_kernel_newPfS_S_S_S_S_S_Piffffiiiiii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z25Ax_cone_mf_gpu_kernel_newPfS_S_S_S_S_S_Piffffiiiiii"
	.size	.L__unnamed_1, 56

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z40__device_stub__Ax_cone_mf_gpu_kernel_newPfS_S_S_S_S_S_Piffffiiiiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z25Ax_cone_mf_gpu_kernel_newPfS_S_S_S_S_S_Piffffiiiiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z25Ax_cone_mf_gpu_kernel_newPfS_S_S_S_S_S_Piffffiiiiii ; -- Begin function _Z25Ax_cone_mf_gpu_kernel_newPfS_S_S_S_S_S_Piffffiiiiii
	.globl	_Z25Ax_cone_mf_gpu_kernel_newPfS_S_S_S_S_S_Piffffiiiiii
	.p2align	8
	.type	_Z25Ax_cone_mf_gpu_kernel_newPfS_S_S_S_S_S_Piffffiiiiii,@function
_Z25Ax_cone_mf_gpu_kernel_newPfS_S_S_S_S_S_Piffffiiiiii: ; @_Z25Ax_cone_mf_gpu_kernel_newPfS_S_S_S_S_S_Piffffiiiiii
; %bb.0:
	s_clause 0x1
	s_load_b64 s[4:5], s[0:1], 0x60
	s_load_b256 s[24:31], s[0:1], 0x40
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v2, v0, 10, 10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v0, s14, 4, v1
	v_lshl_add_u32 v6, s15, 4, v2
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s5, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s31, v0
	v_cmp_gt_i32_e64 s2, s2, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_224
; %bb.1:
	v_cvt_f32_i32_e32 v1, v6
	v_cvt_f32_i32_e32 v2, s4
	s_load_b512 s[8:23], s[0:1], 0x0
                                        ; implicit-def: $vgpr9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v3, null, v2, v2, v1
	v_div_scale_f32 v7, vcc_lo, v1, v2, v1
	v_rcp_f32_e32 v4, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v5, -v3, v4, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v5, v4
	v_mul_f32_e32 v5, v7, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v8, -v3, v5, v7
	v_fmac_f32_e32 v5, v8, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v3, -v3, v5, v7
	v_div_fmas_f32 v3, v3, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v1, v3, v2, v1
	v_floor_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_i32_f32_e32 v4, v1
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[4:5]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v1, vcc_lo, s22, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s23, v2, vcc_lo
	global_load_b32 v1, v[1:2], off
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, s14, v2
	v_add_co_ci_u32_e32 v8, vcc_lo, s15, v3, vcc_lo
	global_load_b32 v5, v[7:8], off
                                        ; implicit-def: $vgpr8
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v7, 0x7fffffff, v5
	v_cmp_ngt_f32_e64 s2, 0x48000000, |v5|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v1, 23, v7
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s0
	s_cbranch_execz .LBB0_3
; %bb.2:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v10, 0
	v_and_or_b32 v18, v7, s0, 0x800000
	v_add_nc_u32_e32 v16, 0xffffff88, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[8:9], null, 0xfe5163ab, v18, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v16
	v_cndmask_b32_e64 v17, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[11:12], null, 0x3c439041, v18, v[9:10]
	v_add_nc_u32_e32 v17, v17, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v9, v12
	v_cmp_lt_u32_e64 s0, 31, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[12:13], null, 0xdb629599, v18, v[9:10]
	v_cndmask_b32_e64 v19, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v8, v12, v8 :: v_dual_add_nc_u32 v19, v19, v17
	v_mov_b32_e32 v9, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s1, 31, v19
	v_mad_u64_u32 v[13:14], null, 0xf534ddc0, v18, v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v9, v14
	v_cndmask_b32_e32 v11, v13, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[14:15], null, 0xfc2757d1, v18, v[9:10]
	v_cndmask_b32_e64 v8, v11, v8, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v9, v15
	v_mad_u64_u32 v[15:16], null, 0x4e441529, v18, v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v9, v16
	v_mad_u64_u32 v[16:17], null, 0xa2f9836e, v18, v[9:10]
	v_cndmask_b32_e64 v9, 0, 0xffffffe0, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v10, v15, v13 :: v_dual_add_nc_u32 v9, v9, v19
	v_dual_cndmask_b32 v16, v16, v14 :: v_dual_cndmask_b32 v15, v17, v15
	v_cndmask_b32_e32 v14, v14, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_eq_u32_e32 vcc_lo, 0, v9
	v_cndmask_b32_e64 v13, v16, v10, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v15, v15, v16, s0
	v_cndmask_b32_e64 v10, v10, v14, s0
	v_sub_nc_u32_e32 v16, 32, v9
	v_cndmask_b32_e64 v14, v14, v11, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v15, v15, v13, s1
	v_cndmask_b32_e64 v13, v13, v10, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v10, v10, v14, s1
	v_cndmask_b32_e64 v8, v14, v8, s1
	v_alignbit_b32 v17, v15, v13, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v12, v13, v10, v16
	v_cndmask_b32_e32 v9, v17, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v15, v10, v8, v16
	v_cndmask_b32_e32 v11, v12, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v12, v9, 29, 1
	v_cndmask_b32_e32 v10, v15, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v13, v9, v11, 30
	v_sub_nc_u32_e32 v14, 0, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v11, v11, v10, 30
	v_alignbit_b32 v8, v10, v8, 30
	v_xor_b32_e32 v13, v13, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v10, v11, v14
	v_xor_b32_e32 v8, v8, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v15, v13
	v_min_u32_e32 v15, 32, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v11, 31, v15
	v_lshlrev_b32_e32 v17, 23, v15
	v_alignbit_b32 v13, v13, v10, v11
	v_alignbit_b32 v8, v10, v8, v11
	v_lshrrev_b32_e32 v11, 29, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v10, v13, v8, 9
	v_lshlrev_b32_e32 v11, 31, v11
	v_lshrrev_b32_e32 v13, 9, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v14, v10
	v_or_b32_e32 v16, 0.5, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v14, 32, v14
	v_sub_nc_u32_e32 v16, v16, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v18, 31, v14
	v_alignbit_b32 v8, v10, v8, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v10, v13, v16
	v_add_lshl_u32 v13, v14, v15, 23
	v_lshrrev_b32_e32 v8, 9, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v14, 0x3fc90fda, v10
	v_sub_nc_u32_e32 v8, v8, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v13, 0x3fc90fda, v10, -v14
	v_add_nc_u32_e32 v8, 0x33000000, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmamk_f32 v10, v10, 0x33a22168, v13
	v_or_b32_e32 v8, v8, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v10, 0x3fc90fda, v8
	v_lshrrev_b32_e32 v9, 30, v9
	v_dual_add_f32 v8, v14, v10 :: v_dual_add_nc_u32 v9, v12, v9
.LBB0_3:                                ; %Flow2415
	s_or_saveexec_b32 s0, s3
	v_mul_f32_e64 v10, 0x3f22f983, |v5|
	s_xor_b32 exec_lo, exec_lo, s0
; %bb.4:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v9, v10
	v_fma_f32 v8, 0xbfc90fda, v9, |v5|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v8, v9, 0xb3a22168, v8
	v_fmamk_f32 v8, v9, 0xa7c234c4, v8
	v_cvt_i32_f32_e32 v9, v9
; %bb.5:                                ; %_ZL4cosff.exit
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr12
                                        ; implicit-def: $vgpr11
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB0_7
; %bb.6:
	s_mov_b32 s0, 0x7fffff
	v_mov_b32_e32 v12, 0
	v_and_or_b32 v20, v7, s0, 0x800000
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[10:11], null, 0xfe5163ab, v20, 0
	v_mad_u64_u32 v[13:14], null, 0x3c439041, v20, v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v11, v14
	v_mad_u64_u32 v[14:15], null, 0xdb629599, v20, v[11:12]
	v_add_nc_u32_e32 v1, 0xffffff88, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v1
	v_mov_b32_e32 v11, v15
	v_cndmask_b32_e64 v18, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[15:16], null, 0xf534ddc0, v20, v[11:12]
	v_cndmask_b32_e32 v10, v14, v10, vcc_lo
	v_add_nc_u32_e32 v1, v18, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v11, v16
	v_cmp_lt_u32_e64 s0, 31, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[16:17], null, 0xfc2757d1, v20, v[11:12]
	v_cndmask_b32_e64 v19, 0, 0xffffffe0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v1, v19, v1
	v_mov_b32_e32 v11, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s1, 31, v1
	v_mad_u64_u32 v[17:18], null, 0x4e441529, v20, v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v11, v18
	v_mad_u64_u32 v[18:19], null, 0xa2f9836e, v20, v[11:12]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v11, 0, 0xffffffe0, s1
	v_dual_cndmask_b32 v12, v17, v15 :: v_dual_add_nc_u32 v1, v11, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v18, v18, v16 :: v_dual_cndmask_b32 v17, v19, v17
	v_dual_cndmask_b32 v16, v16, v14 :: v_dual_cndmask_b32 v11, v15, v13
	v_cmp_eq_u32_e32 vcc_lo, 0, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v13, v18, v12, s0
	v_cndmask_b32_e64 v15, v17, v18, s0
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v12, v12, v16, s0
	v_sub_nc_u32_e32 v17, 32, v1
	v_cndmask_b32_e64 v16, v16, v11, s0
	v_cndmask_b32_e64 v10, v11, v10, s0
	v_cndmask_b32_e64 v15, v15, v13, s1
	v_cndmask_b32_e64 v13, v13, v12, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v12, v12, v16, s1
	v_cndmask_b32_e64 v10, v16, v10, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v18, v15, v13, v17
	v_alignbit_b32 v14, v13, v12, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v16, v12, v10, v17
	v_cndmask_b32_e32 v1, v18, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v11, v14, v13 :: v_dual_cndmask_b32 v12, v16, v12
	v_bfe_u32 v13, v1, 29, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v14, v1, v11, 30
	v_alignbit_b32 v11, v11, v12, 30
	v_alignbit_b32 v10, v12, v10, 30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v15, 0, v13
	v_xor_b32_e32 v14, v14, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v11, v11, v15
	v_xor_b32_e32 v10, v10, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v16, v14
	v_min_u32_e32 v16, 32, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v12, 31, v16
	v_lshlrev_b32_e32 v18, 23, v16
	v_alignbit_b32 v14, v14, v11, v12
	v_alignbit_b32 v10, v11, v10, v12
	v_lshrrev_b32_e32 v12, 29, v1
	v_lshrrev_b32_e32 v1, 30, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v11, v14, v10, 9
	v_lshlrev_b32_e32 v12, 31, v12
	v_lshrrev_b32_e32 v14, 9, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v15, v11
	v_or_b32_e32 v17, 0.5, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min_u32_e32 v15, 32, v15
	v_sub_nc_u32_e32 v17, v17, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v19, 31, v15
	v_alignbit_b32 v10, v11, v10, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_or_b32_e32 v11, v14, v17
	v_add_lshl_u32 v14, v15, v16, 23
	v_lshrrev_b32_e32 v10, 9, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v15, 0x3fc90fda, v11
	v_sub_nc_u32_e32 v10, v10, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v10, 0x33000000, v10
	v_or_b32_e32 v10, v10, v12
	v_add_nc_u32_e32 v12, v13, v1
	v_fma_f32 v14, 0x3fc90fda, v11, -v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v11, v11, 0x33a22168, v14
	v_fmac_f32_e32 v11, 0x3fc90fda, v10
                                        ; implicit-def: $vgpr10
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v11, v15, v11
.LBB0_7:                                ; %Flow2414
	s_and_not1_saveexec_b32 s0, s2
; %bb.8:
	v_rndne_f32_e32 v1, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v10, 0xbfc90fda, v1, |v5|
	v_cvt_i32_f32_e32 v12, v1
	v_fmamk_f32 v10, v1, 0xb3a22168, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v11, v1, 0xa7c234c4, v10
; %bb.9:                                ; %_ZL4sinff.exit
	s_or_b32 exec_lo, exec_lo, s0
	v_mad_u64_u32 v[14:15], null, v6, s31, v[0:1]
	v_ashrrev_i32_e32 v1, 31, v0
	v_mul_lo_u32 v4, v4, s4
	s_mov_b32 s0, 0xb94c1982
	s_mov_b32 s1, 0x37d75334
	v_xor_b32_e32 v7, v7, v5
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_lshr_b32 s2, s30, 31
	s_mov_b32 s6, s8
	s_add_i32 s2, s30, s2
	v_sub_nc_u32_e32 v15, v6, v4
	s_mov_b32 s7, s9
	v_add_co_u32 v0, vcc_lo, s18, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s19, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_ashrrev_i32_e32 v16, 31, v15
	v_add_co_u32 v2, vcc_lo, s16, v2
	global_load_b32 v4, v[0:1], off
	v_add_co_ci_u32_e32 v3, vcc_lo, s17, v3, vcc_lo
	v_lshlrev_b64 v[0:1], 2, v[15:16]
	s_ashr_i32 s16, s2, 1
	v_lshlrev_b32_e32 v6, 30, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, s20, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s21, v1, vcc_lo
	global_load_b32 v10, v[2:3], off
	global_load_b32 v2, v[0:1], off
	v_dual_mul_f32 v0, v8, v8 :: v_dual_and_b32 v1, 1, v9
	v_mul_f32_e32 v3, v11, v11
	v_and_b32_e32 v9, 1, v12
	v_lshlrev_b32_e32 v12, 30, v12
	s_delay_alu instid0(VALU_DEP_4)
	v_fmaak_f32 v13, s0, v0, 0x3c0881c4
	v_cmp_eq_u32_e32 vcc_lo, 0, v1
	v_fmaak_f32 v16, s0, v3, 0x3c0881c4
	v_fmaak_f32 v17, s1, v3, 0xbab64f3b
	v_and_b32_e32 v6, 0x80000000, v6
	v_fmaak_f32 v13, v0, v13, 0xbe2aaa9d
	s_lshr_b32 s0, s28, 31
	v_fmaak_f32 v16, v3, v16, 0xbe2aaa9d
	v_fmaak_f32 v17, v3, v17, 0x3d2aabf7
	s_add_i32 s0, s28, s0
	v_mul_f32_e32 v13, v0, v13
	v_fmaak_f32 v15, s1, v0, 0xbab64f3b
	v_mul_f32_e32 v16, v3, v16
	v_fmaak_f32 v17, v3, v17, 0xbf000004
	s_lshr_b32 s1, s29, 31
	v_fmac_f32_e32 v8, v8, v13
	v_fmaak_f32 v15, v0, v15, 0x3d2aabf7
	v_fmac_f32_e32 v11, v11, v16
	v_fma_f32 v3, v3, v17, 1.0
	s_add_i32 s1, s29, s1
	s_ashr_i32 s5, s0, 1
	v_fmaak_f32 v15, v0, v15, 0xbf000004
	s_ashr_i32 s15, s1, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v0, v0, v15, 1.0
	v_ashrrev_i32_e32 v15, 31, v14
	v_cndmask_b32_e64 v0, -v8, v0, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v9
	v_dual_mov_b32 v9, 0 :: v_dual_and_b32 v12, 0x80000000, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v0, v6, v0
	v_cndmask_b32_e32 v1, v3, v11, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v5, 0x1f8
	v_xor3_b32 v1, v7, v12, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v8, 0x7fc00000, v0, vcc_lo
	v_cndmask_b32_e32 v12, 0x7fc00000, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e64 v11, v8, -s24
	v_mul_f32_e32 v5, s25, v12
	s_waitcnt vmcnt(2)
	v_mul_f32_e32 v0, v4, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v5, v8, v4
	v_fma_f32 v13, v8, s25, -v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f32 v6, v12, -s24, -v5
	v_lshlrev_b64 v[0:1], 2, v[14:15]
	v_mul_f32_e64 v12, v12, -s24
	v_fma_f32 v7, v8, -s24, -v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_cmp_lt_f32_e32 vcc_lo, 0, v6
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v14, v10, v2
	v_cndmask_b32_e64 v4, -v6, v6, vcc_lo
	v_cmp_lt_f32_e32 vcc_lo, 0, v7
	v_sub_f32_e32 v8, v10, v14
	v_cndmask_b32_e64 v15, -v7, v7, vcc_lo
	v_add_co_u32 v2, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_cmp_ngt_f32_e32 vcc_lo, v15, v4
	v_sub_f32_e32 v4, v14, v10
	global_store_b32 v[2:3], v9, off
	s_and_saveexec_b32 s0, vcc_lo
	s_xor_b32 s17, exec_lo, s0
	s_cbranch_execz .LBB0_116
; %bb.10:
	s_cmp_lt_i32 s29, 1
	s_cbranch_scc1 .LBB0_115
; %bb.11:                               ; %.lr.ph
	v_sub_f32_e32 v9, v13, v11
	v_sub_f32_e32 v5, v5, v12
	s_mov_b32 s10, 0
	s_sub_i32 s18, 0, s15
	s_mov_b32 s14, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_scale_f32 v14, null, v5, v5, v9
	v_div_scale_f32 v15, null, v5, v5, v4
	v_div_scale_f32 v19, vcc_lo, v9, v5, v9
	v_rcp_f32_e32 v16, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v17, v15
	s_waitcnt_depctr 0xfff
	v_fma_f32 v13, -v14, v16, 1.0
	v_fma_f32 v18, -v15, v17, 1.0
	v_dual_fmac_f32 v16, v13, v16 :: v_dual_fmac_f32 v17, v18, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v18, v19, v16
	v_fma_f32 v13, -v14, v18, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v18, v13, v16
	v_cvt_f32_i32_e32 v13, s5
	v_fma_f32 v19, -v14, v18, v19
	v_mul_f32_e32 v14, v6, v6
	v_div_scale_f32 v20, s0, v4, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v14, v7, v7 :: v_dual_mul_f32 v21, v20, v17
	v_fma_f32 v22, -v15, v21, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v21, v22, v17
	v_div_fmas_f32 v18, v19, v16, v18
	s_mov_b32 vcc_lo, s0
	v_cvt_f32_i32_e32 v16, s30
	v_fma_f32 v15, -v15, v21, v20
	v_fma_f32 v20, v8, v8, v14
	s_delay_alu instid0(VALU_DEP_2)
	v_div_fmas_f32 v19, v15, v17, v21
	v_div_fixup_f32 v17, v18, v5, v9
	v_cvt_f32_i32_e32 v15, s16
	v_mov_b32_e32 v9, 0
	v_mov_b32_e32 v21, 0
	v_div_fixup_f32 v18, v19, v5, v4
	v_cvt_f32_i32_e32 v19, s28
	v_cmp_nle_f32_e64 s0, 0, v17
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_nle_f32_e64 s1, 0, v18
.LBB0_12:                               ; =>This Inner Loop Header: Depth=1
	s_add_i32 s2, s18, s14
	s_mov_b32 s4, 0
	s_waitcnt vmcnt(0)
	v_cvt_f32_i32_e32 v4, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, 1.0, v4
	v_cndmask_b32_e64 v22, v5, v4, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v22, v22, v12
	v_fma_f32 v24, v18, v22, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v22, null, s27, s27, v24
	v_div_scale_f32 v30, vcc_lo, v24, s27, v24
	v_rcp_f32_e32 v26, v22
	s_waitcnt_depctr 0xfff
	v_fma_f32 v28, -v22, v26, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v26, v28, v26
	v_cndmask_b32_e64 v33, v4, v5, s0
	v_cndmask_b32_e64 v23, v4, v5, s1
	v_cndmask_b32_e64 v4, v5, v4, s0
	v_sub_f32_e32 v5, v33, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v4, v4, v12
	v_fma_f32 v5, v17, v5, v11
	v_sub_f32_e32 v23, v23, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v4, v17, v4, v11
	v_fma_f32 v23, v18, v23, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v25, null, s27, s27, v23
	v_div_scale_f32 v28, s2, v23, s27, v23
	v_rcp_f32_e32 v27, v25
	s_waitcnt_depctr 0xfff
	v_fma_f32 v29, -v25, v27, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v27, v29, v27
	v_mul_f32_e32 v29, v30, v26
	v_mul_f32_e32 v31, v28, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v32, -v22, v29, v30
	v_fma_f32 v34, -v25, v31, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v29, v32, v26
	v_fmac_f32_e32 v31, v34, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v22, -v22, v29, v30
	v_fma_f32 v25, -v25, v31, v28
	s_delay_alu instid0(VALU_DEP_2)
	v_div_fmas_f32 v26, v22, v26, v29
	s_mov_b32 vcc_lo, s2
	v_add_f32_e32 v22, v5, v13
	s_mov_b32 s2, exec_lo
	v_div_fmas_f32 v25, v25, v27, v31
	v_div_fixup_f32 v5, v26, s27, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v24, v25, s27, v23
	v_dual_add_f32 v26, v5, v15 :: v_dual_add_f32 v23, v4, v13
	v_floor_f32_e32 v4, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v25, v24, v15
	v_floor_f32_e32 v24, v26
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_floor_f32_e32 v5, v23
	v_cvt_i32_f32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_floor_f32_e32 v28, v25
	v_cvt_i32_f32_e32 v27, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_i32_f32_e32 v5, v5
	v_cvt_i32_f32_e32 v24, v28
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_ne_u32_e64 v5, v4
	s_xor_b32 s19, exec_lo, s2
	s_cbranch_execz .LBB0_94
; %bb.13:                               ;   in Loop: Header=BB0_12 Depth=1
	v_cmp_gt_i32_e32 vcc_lo, 1, v5
	v_cmp_le_i32_e64 s2, s28, v5
	s_mov_b32 s11, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s20, exec_lo, s3
	s_cbranch_execz .LBB0_65
; %bb.14:                               ;   in Loop: Header=BB0_12 Depth=1
	s_mov_b32 s21, exec_lo
	v_cmpx_eq_u32_e32 0, v5
	s_cbranch_execz .LBB0_38
; %bb.15:                               ;   in Loop: Header=BB0_12 Depth=1
                                        ; implicit-def: $vgpr28
                                        ; implicit-def: $vgpr29
	s_mov_b32 s2, exec_lo
	v_cmpx_ne_u32_e64 v27, v24
	s_xor_b32 s22, exec_lo, s2
	s_cbranch_execz .LBB0_31
; %bb.16:                               ;   in Loop: Header=BB0_12 Depth=1
	v_cmp_gt_i32_e32 vcc_lo, 1, v27
	v_cmp_le_i32_e64 s2, s30, v27
                                        ; implicit-def: $vgpr28
                                        ; implicit-def: $vgpr29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s23, exec_lo, s3
	s_cbranch_execz .LBB0_24
; %bb.17:                               ;   in Loop: Header=BB0_12 Depth=1
	s_mov_b32 s24, exec_lo
	v_cmpx_eq_u32_e32 0, v27
	s_cbranch_execz .LBB0_19
; %bb.18:                               ; %.sink.split2172
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_ashr_i32 s11, s10, 31
	v_sub_f32_e32 v29, v23, v22
	s_lshl_b64 s[2:3], s[10:11], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s2, s8, s2
	s_addc_u32 s3, s9, s3
	v_fma_f32 v30, v29, v29, 1.0
	global_load_b32 v28, v21, s[2:3]
	v_mul_f32_e32 v30, v20, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v31, null, v14, v14, v30
	v_rcp_f32_e32 v32, v31
	s_waitcnt_depctr 0xfff
	v_fma_f32 v33, -v31, v32, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v32, v33, v32
	v_div_scale_f32 v33, vcc_lo, v30, v14, v30
	v_mul_f32_e32 v34, v33, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v35, -v31, v34, v33
	v_fmac_f32_e32 v34, v35, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v31, -v31, v34, v33
	v_div_scale_f32 v33, null, v29, v29, -v22
	v_div_fmas_f32 v31, v31, v32, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v30, v31, v14, v30
	v_dual_sub_f32 v31, v26, v25 :: v_dual_mul_f32 v32, 0x4f800000, v30
	v_cmp_gt_f32_e64 s2, 0xf800000, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f32 v34, null, v31, v31, -v25
	v_cndmask_b32_e64 v30, v30, v32, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v35, v34
	v_rcp_f32_e32 v32, v33
	v_sqrt_f32_e32 v36, v30
	s_delay_alu instid0(TRANS32_DEP_3)
	v_fma_f32 v38, -v34, v35, 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v37, -v33, v32, 1.0
	v_add_nc_u32_e32 v39, -1, v36
	v_fmac_f32_e32 v35, v38, v35
	v_div_scale_f32 v38, s3, -v25, v31, -v25
	v_add_nc_u32_e32 v40, 1, v36
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v42, -v39, v36, v30
	v_mul_f32_e32 v43, v38, v35
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v44, -v40, v36, v30
	v_cmp_ge_f32_e64 s4, 0, v42
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v36, v36, v39, s4
	v_fma_f32 v39, -v34, v43, v38
	v_fmac_f32_e32 v32, v37, v32
	v_div_scale_f32 v37, vcc_lo, -v22, v29, -v22
	v_cmp_lt_f32_e64 s4, 0, v44
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v43, v39, v35
	v_mul_f32_e32 v41, v37, v32
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v34, -v34, v43, v38
	v_fma_f32 v45, -v33, v41, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v41, v45, v32
	v_fma_f32 v33, -v33, v41, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v32, v33, v32, v41
	s_mov_b32 vcc_lo, s3
	v_div_fmas_f32 v33, v34, v35, v43
	v_cmp_class_f32_e64 vcc_lo, v30, 0x260
	v_div_fixup_f32 v29, v32, v29, -v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v31, v33, v31, -v25
	v_sub_f32_e32 v33, 1.0, v29
	v_cndmask_b32_e64 v36, v36, v40, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v32, 1.0, v31 :: v_dual_mul_f32 v37, 0x37800000, v36
	v_cndmask_b32_e64 v34, v36, v37, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v30, v34, v30, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, v29, v31
	v_dual_cndmask_b32 v29, v32, v30 :: v_dual_cndmask_b32 v30, v30, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v29, v30, v29
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v9, v29, v28
	global_store_b32 v[2:3], v9, off
.LBB0_19:                               ;   in Loop: Header=BB0_12 Depth=1
	s_or_b32 exec_lo, exec_lo, s24
	s_mov_b32 s2, 0
	s_mov_b32 s3, exec_lo
                                        ; implicit-def: $vgpr28
	v_cmpx_eq_u32_e64 s30, v27
	s_cbranch_execz .LBB0_23
; %bb.20:                               ;   in Loop: Header=BB0_12 Depth=1
	v_dual_sub_f32 v29, v23, v22 :: v_dual_sub_f32 v28, v16, v25
	v_sub_f32_e32 v31, v26, v25
	s_mov_b32 s4, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f32 v30, null, v29, v29, -v22
	v_div_scale_f32 v32, null, v31, v31, v28
	v_div_scale_f32 v37, vcc_lo, -v22, v29, -v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v33, v30
	v_rcp_f32_e32 v34, v32
	s_waitcnt_depctr 0xfff
	v_fma_f32 v35, -v30, v33, 1.0
	v_fma_f32 v36, -v32, v34, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v34, v36, v34 :: v_dual_fmac_f32 v33, v35, v33
	v_div_scale_f32 v35, s2, v28, v31, v28
	v_mul_f32_e32 v38, v35, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v40, -v32, v38, v35
	v_fmac_f32_e32 v38, v40, v34
	v_mul_f32_e32 v36, v37, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v32, -v32, v38, v35
	v_fma_f32 v39, -v30, v36, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v36, v39, v33
	v_fma_f32 v30, -v30, v36, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v30, v30, v33, v36
	s_mov_b32 vcc_lo, s2
	s_mov_b32 s2, exec_lo
	v_div_fmas_f32 v32, v32, v34, v38
	v_div_fixup_f32 v30, v30, v29, -v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v31, v32, v31, v28
                                        ; implicit-def: $vgpr28
	v_cmpx_ngt_f32_e32 v30, v31
	s_xor_b32 s11, exec_lo, s2
	s_cbranch_execz .LBB0_22
; %bb.21:                               ;   in Loop: Header=BB0_12 Depth=1
	v_fma_f32 v28, v29, v29, 1.0
	s_mov_b32 s4, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v28, v20, v28
	v_div_scale_f32 v29, null, v14, v14, v28
	v_div_scale_f32 v34, vcc_lo, v28, v14, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v32, v29
	s_waitcnt_depctr 0xfff
	v_fma_f32 v33, -v29, v32, 1.0
	v_fmac_f32_e32 v32, v33, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v33, v34, v32
	v_fma_f32 v35, -v29, v33, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v33, v35, v32
	v_fma_f32 v29, -v29, v33, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v29, v29, v32, v33
	v_div_fixup_f32 v28, v29, v14, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v29, 0x4f800000, v28
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v28
	v_cndmask_b32_e32 v28, v28, v29, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v29, v28
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v32, -1, v29
	v_add_nc_u32_e32 v33, 1, v29
	v_fma_f32 v34, -v32, v29, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v35, -v33, v29, v28
	v_cmp_ge_f32_e64 s2, 0, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v29, v29, v32, s2
	v_cmp_lt_f32_e64 s2, 0, v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v29, v29, v33, s2
	v_mul_f32_e32 v32, 0x37800000, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v29, v29, v32, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v28, 0x260
	v_dual_cndmask_b32 v28, v29, v28 :: v_dual_sub_f32 v29, v31, v30
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v28, v28, v29
.LBB0_22:                               ; %Flow2322
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s2, s4, exec_lo
.LBB0_23:                               ; %Flow2321
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	v_mov_b32_e32 v29, v24
	s_and_b32 s11, s2, exec_lo
.LBB0_24:                               ; %Flow2320
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_and_not1_saveexec_b32 s23, s23
	s_cbranch_execz .LBB0_30
; %bb.25:                               ;   in Loop: Header=BB0_12 Depth=1
	v_sub_f32_e32 v28, v23, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v29, v28, v28, 1.0
	v_mul_f32_e32 v29, v20, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v30, null, v14, v14, v29
	v_div_scale_f32 v33, vcc_lo, v29, v14, v29
	v_rcp_f32_e32 v31, v30
	s_waitcnt_depctr 0xfff
	v_fma_f32 v32, -v30, v31, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v31, v32, v31
	v_mul_f32_e32 v32, v33, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v34, -v30, v32, v33
	v_fmac_f32_e32 v32, v34, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v30, -v30, v32, v33
	v_cvt_f32_i32_e32 v33, v27
	v_div_fmas_f32 v30, v30, v31, v32
	v_sub_f32_e32 v31, v26, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v32, v33, v25
	v_div_scale_f32 v33, null, v28, v28, -v22
	v_div_fixup_f32 v29, v30, v14, v29
	v_div_scale_f32 v38, vcc_lo, -v22, v28, -v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_scale_f32 v30, null, v31, v31, v32
	v_mul_f32_e32 v35, 0x4f800000, v29
	v_rcp_f32_e32 v34, v33
	v_cmp_gt_f32_e64 s2, 0xf800000, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v36, v30
	v_cndmask_b32_e64 v29, v29, v35, s2
	s_waitcnt_depctr 0xfff
	v_fma_f32 v35, -v33, v34, 1.0
	v_sqrt_f32_e32 v37, v29
	v_fma_f32 v39, -v30, v36, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v34, v35, v34
	v_div_scale_f32 v35, s3, v32, v31, v32
	s_waitcnt_depctr 0xfff
	v_dual_fmac_f32 v36, v39, v36 :: v_dual_add_nc_u32 v43, 1, v37
	v_dual_mul_f32 v39, v38, v34 :: v_dual_add_nc_u32 v40, -1, v37
	v_mul_f32_e32 v41, v35, v36
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v42, -v33, v39, v38
	v_fma_f32 v44, -v40, v37, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v45, -v30, v41, v35
	v_fmac_f32_e32 v39, v42, v34
	v_fma_f32 v42, -v43, v37, v29
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_ge_f32_e64 s4, 0, v44
	v_fmac_f32_e32 v41, v45, v36
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v33, -v33, v39, v38
	v_cndmask_b32_e64 v37, v37, v40, s4
	v_cmp_lt_f32_e64 s4, 0, v42
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v30, -v30, v41, v35
	v_div_fmas_f32 v33, v33, v34, v39
	s_mov_b32 vcc_lo, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v37, v37, v43, s4
	v_div_fmas_f32 v35, v30, v36, v41
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_div_fixup_f32 v30, v33, v28, -v22
	v_cmp_class_f32_e64 vcc_lo, v29, 0x260
	v_mul_f32_e32 v34, 0x37800000, v37
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v31, v35, v31, v32
	v_cndmask_b32_e64 v28, v37, v34, s2
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v29, v28, v29, vcc_lo
                                        ; implicit-def: $vgpr28
	v_cmpx_ngt_f32_e32 v30, v31
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB0_27
; %bb.26:                               ;   in Loop: Header=BB0_12 Depth=1
	v_mad_u64_u32 v[32:33], null, v24, s29, s[14:15]
	v_dual_sub_f32 v30, v31, v30 :: v_dual_sub_f32 v31, 1.0, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v30, v29, v30
	v_mul_lo_u32 v32, v32, s28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v33, 31, v32
	v_lshlrev_b64 v[32:33], 2, v[32:33]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v32, vcc_lo, s8, v32
	v_add_co_ci_u32_e32 v33, vcc_lo, s9, v33, vcc_lo
	global_load_b32 v28, v[32:33], off
	s_waitcnt vmcnt(0)
	v_dual_fmac_f32 v9, v30, v28 :: v_dual_mul_f32 v28, v29, v31
                                        ; implicit-def: $vgpr30
                                        ; implicit-def: $vgpr29
	global_store_b32 v[2:3], v9, off
.LBB0_27:                               ; %Flow2316
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_and_not1_saveexec_b32 s2, s2
; %bb.28:                               ;   in Loop: Header=BB0_12 Depth=1
	v_sub_f32_e32 v28, 1.0, v30
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v28, v28, v29
; %bb.29:                               ; %Flow2317
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	v_mov_b32_e32 v29, v27
	s_or_b32 s11, s11, exec_lo
.LBB0_30:                               ; %Flow2323
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_or_b32 exec_lo, exec_lo, s23
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s4, s11, exec_lo
.LBB0_31:                               ; %Flow2319
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_and_not1_saveexec_b32 s11, s22
	s_cbranch_execz .LBB0_35
; %bb.32:                               ;   in Loop: Header=BB0_12 Depth=1
	v_cmp_lt_i32_e32 vcc_lo, -1, v24
	v_cmp_gt_i32_e64 s2, s30, v24
                                        ; implicit-def: $vgpr28
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s3, vcc_lo, s2
	s_mov_b32 s2, s4
	s_and_saveexec_b32 s22, s3
	s_cbranch_execz .LBB0_34
; %bb.33:                               ;   in Loop: Header=BB0_12 Depth=1
	v_sub_f32_e32 v28, v23, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v29, v28, v28, 1.0
	v_mul_f32_e32 v29, v20, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v30, null, v14, v14, v29
	v_div_scale_f32 v33, vcc_lo, v29, v14, v29
	v_rcp_f32_e32 v31, v30
	s_waitcnt_depctr 0xfff
	v_fma_f32 v32, -v30, v31, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v31, v32, v31
	v_mul_f32_e32 v32, v33, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v34, -v30, v32, v33
	v_fmac_f32_e32 v32, v34, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v30, -v30, v32, v33
	v_div_fmas_f32 v30, v30, v31, v32
	v_div_scale_f32 v34, vcc_lo, -v22, v28, -v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v29, v30, v14, v29
	v_div_scale_f32 v30, null, v28, v28, -v22
	v_mul_f32_e32 v31, 0x4f800000, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v32, v30
	v_cmp_gt_f32_e64 s2, 0xf800000, v29
	v_cndmask_b32_e64 v29, v29, v31, s2
	s_waitcnt_depctr 0xfff
	v_fma_f32 v33, -v30, v32, 1.0
	v_sqrt_f32_e32 v31, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v32, v33, v32
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v35, v34, v32 :: v_dual_add_nc_u32 v36, 1, v31
	v_fma_f32 v38, -v30, v35, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v39, -v36, v31, v29
	v_fmac_f32_e32 v35, v38, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v30, -v30, v35, v34
	v_div_fmas_f32 v30, v30, v32, v35
	v_cmp_class_f32_e64 vcc_lo, v29, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v28, v30, v28, -v22
	v_dual_sub_f32 v28, 1.0, v28 :: v_dual_add_nc_u32 v33, -1, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v37, -v33, v31, v29
	v_cmp_ge_f32_e64 s3, 0, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v31, v31, v33, s3
	v_cmp_lt_f32_e64 s3, 0, v39
	v_cndmask_b32_e64 v31, v31, v36, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v33, 0x37800000, v31
	v_cndmask_b32_e64 v31, v31, v33, s2
	s_or_b32 s2, s4, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v29, v31, v29, vcc_lo
	v_mul_f32_e32 v28, v28, v29
.LBB0_34:                               ; %Flow2325
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	v_mov_b32_e32 v29, v24
	s_and_not1_b32 s3, s4, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s4, s3, s2
.LBB0_35:                               ; %Flow2324
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	s_and_saveexec_b32 s2, s4
	s_cbranch_execz .LBB0_37
; %bb.36:                               ; %.sink.split2175
                                        ;   in Loop: Header=BB0_12 Depth=1
	v_mad_u64_u32 v[30:31], null, v29, s29, s[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v29, v30, s28
	v_ashrrev_i32_e32 v30, 31, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[29:30], 2, v[29:30]
	v_add_co_u32 v29, vcc_lo, s8, v29
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v30, vcc_lo, s9, v30, vcc_lo
	global_load_b32 v29, v[29:30], off
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v9, v28, v29
	global_store_b32 v[2:3], v9, off
.LBB0_37:                               ; %Flow2326
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
.LBB0_38:                               ;   in Loop: Header=BB0_12 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s21
	s_mov_b32 s2, 0
	s_mov_b32 s11, exec_lo
	v_cmpx_eq_u32_e64 s28, v5
	s_cbranch_execz .LBB0_64
; %bb.39:                               ;   in Loop: Header=BB0_12 Depth=1
	s_mov_b32 s4, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_ne_u32_e64 v27, v24
	s_xor_b32 s21, exec_lo, s2
	s_cbranch_execz .LBB0_59
; %bb.40:                               ;   in Loop: Header=BB0_12 Depth=1
	v_cmp_gt_i32_e32 vcc_lo, 1, v27
	v_cmp_le_i32_e64 s2, s30, v27
	s_mov_b32 s23, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s22, exec_lo, s3
	s_cbranch_execz .LBB0_52
; %bb.41:                               ;   in Loop: Header=BB0_12 Depth=1
	s_mov_b32 s3, exec_lo
	v_cmpx_eq_u32_e32 0, v27
	s_cbranch_execz .LBB0_45
; %bb.42:                               ;   in Loop: Header=BB0_12 Depth=1
	v_sub_f32_e32 v5, v23, v22
	v_dual_sub_f32 v28, v19, v22 :: v_dual_sub_f32 v29, v26, v25
	s_mov_b32 s4, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f32 v30, null, v5, v5, v28
	v_div_scale_f32 v31, null, v29, v29, -v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v32, v30
	v_rcp_f32_e32 v33, v31
	s_waitcnt_depctr 0xfff
	v_fma_f32 v34, -v30, v32, 1.0
	v_fma_f32 v35, -v31, v33, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v32, v34, v32
	v_div_scale_f32 v36, vcc_lo, v28, v5, v28
	v_div_scale_f32 v34, s2, -v25, v29, -v25
	v_fmac_f32_e32 v33, v35, v33
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v35, v36, v32
	v_mul_f32_e32 v37, v34, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v38, -v30, v35, v36
	v_fma_f32 v39, -v31, v37, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v35, v38, v32
	v_fmac_f32_e32 v37, v39, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v30, -v30, v35, v36
	v_fma_f32 v31, -v31, v37, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v30, v30, v32, v35
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f32 v31, v31, v33, v37
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v28, v30, v5, v28
	v_div_fixup_f32 v29, v31, v29, -v25
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_f32_e32 v28, v29
	s_cbranch_execz .LBB0_44
; %bb.43:                               ;   in Loop: Header=BB0_12 Depth=1
	v_fma_f32 v5, v5, v5, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v5, v20, v5 :: v_dual_add_nc_u32 v30, s10, v4
	v_ashrrev_i32_e32 v31, 31, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[30:31], 2, v[30:31]
	v_add_co_u32 v30, vcc_lo, s8, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v31, vcc_lo, s9, v31, vcc_lo
	global_load_b32 v30, v[30:31], off
	v_div_scale_f32 v31, null, v14, v14, v5
	v_sub_f32_e32 v28, v28, v29
	v_rcp_f32_e32 v32, v31
	s_waitcnt_depctr 0xfff
	v_fma_f32 v33, -v31, v32, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v32, v33, v32
	v_div_scale_f32 v33, vcc_lo, v5, v14, v5
	v_mul_f32_e32 v34, v33, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v35, -v31, v34, v33
	v_fmac_f32_e32 v34, v35, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v31, -v31, v34, v33
	v_div_fmas_f32 v31, v31, v32, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v5, v31, v14, v5
	v_mul_f32_e32 v31, 0x4f800000, v5
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v5, v5, v31, vcc_lo
	v_sqrt_f32_e32 v31, v5
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v32, -1, v31
	v_add_nc_u32_e32 v33, 1, v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v34, -v32, v31, v5
	v_fma_f32 v35, -v33, v31, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s2, 0, v34
	v_cndmask_b32_e64 v31, v31, v32, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s2, 0, v35
	v_cndmask_b32_e64 v31, v31, v33, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v32, 0x37800000, v31
	v_cndmask_b32_e32 v31, v31, v32, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v5, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v5, v31, v5, vcc_lo
	v_mul_f32_e32 v5, v5, v28
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v9, v5, v30
	global_store_b32 v[2:3], v9, off
.LBB0_44:                               ; %Flow2313
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_45:                               ;   in Loop: Header=BB0_12 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s2, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_eq_u32_e64 s30, v27
	s_xor_b32 s23, exec_lo, s3
	s_cbranch_execz .LBB0_51
; %bb.46:                               ;   in Loop: Header=BB0_12 Depth=1
	v_mad_u64_u32 v[27:28], null, v24, s29, s[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[28:29], null, v27, s28, v[4:5]
	v_ashrrev_i32_e32 v29, 31, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[28:29]
	v_add_co_u32 v4, vcc_lo, s8, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	v_sub_f32_e32 v5, v23, v22
	v_sub_f32_e32 v22, v19, v22
	v_fma_f32 v23, v5, v5, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v23, v20, v23
	v_div_scale_f32 v24, null, v14, v14, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v27, v24
	s_waitcnt_depctr 0xfff
	v_fma_f32 v28, -v24, v27, 1.0
	v_fmac_f32_e32 v27, v28, v27
	v_div_scale_f32 v28, vcc_lo, v23, v14, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v29, v28, v27
	v_fma_f32 v30, -v24, v29, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v29, v30, v27
	v_fma_f32 v24, -v24, v29, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v24, v24, v27, v29
	v_div_fixup_f32 v23, v24, v14, v23
	v_sub_f32_e32 v24, v16, v25
	v_sub_f32_e32 v25, v26, v25
	v_div_scale_f32 v27, null, v5, v5, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v26, 0x4f800000, v23
	v_cmp_gt_f32_e64 s2, 0xf800000, v23
	v_div_scale_f32 v28, null, v25, v25, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v26, v23, v26, s2
	v_rcp_f32_e32 v23, v27
	v_rcp_f32_e32 v29, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_3)
	v_sqrt_f32_e32 v30, v26
	v_fma_f32 v31, -v27, v23, 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v32, -v28, v29, 1.0
	v_add_nc_u32_e32 v33, -1, v30
	v_fmac_f32_e32 v23, v31, v23
	v_div_scale_f32 v31, vcc_lo, v22, v5, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v29, v32, v29
	v_div_scale_f32 v32, s3, v24, v25, v24
	v_add_nc_u32_e32 v34, 1, v30
	v_fma_f32 v36, -v33, v30, v26
	v_mul_f32_e32 v35, v31, v23
	v_mul_f32_e32 v37, v32, v29
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v38, -v34, v30, v26
	v_cmp_ge_f32_e64 s4, 0, v36
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v39, -v27, v35, v31
	v_cndmask_b32_e64 v30, v30, v33, s4
	v_fma_f32 v33, -v28, v37, v32
	v_cmp_lt_f32_e64 s4, 0, v38
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v35, v39, v23
	v_fmac_f32_e32 v37, v33, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v30, v30, v34, s4
	v_fma_f32 v27, -v27, v35, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v28, -v28, v37, v32
	v_mul_f32_e32 v31, 0x37800000, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v23, v27, v23, v35
	s_mov_b32 vcc_lo, s3
	v_div_fmas_f32 v27, v28, v29, v37
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e64 v28, v30, v31, s2
	v_cmp_class_f32_e64 vcc_lo, v26, 0x260
	v_div_fixup_f32 v23, v23, v5, v22
	s_mov_b32 s2, exec_lo
	v_div_fixup_f32 v22, v27, v25, v24
	v_cndmask_b32_e32 v5, v28, v26, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_ngt_f32_e32 v23, v22
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB0_48
; %bb.47:                               ;   in Loop: Header=BB0_12 Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v23, v5
                                        ; implicit-def: $vgpr22
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v9, v5, v4
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr4
.LBB0_48:                               ; %Flow
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_and_not1_saveexec_b32 s2, s2
	s_cbranch_execz .LBB0_50
; %bb.49:                               ;   in Loop: Header=BB0_12 Depth=1
	v_mul_f32_e32 v5, v5, v22
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v9, v5, v4
.LBB0_50:                               ; %Flow2312
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
.LBB0_51:                               ; %Flow2341
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_or_b32 exec_lo, exec_lo, s23
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s23, s2, exec_lo
                                        ; implicit-def: $vgpr27
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr23
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr25
                                        ; implicit-def: $vgpr26
                                        ; implicit-def: $vgpr24
.LBB0_52:                               ; %Flow2340
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_and_not1_saveexec_b32 s22, s22
	s_cbranch_execz .LBB0_58
; %bb.53:                               ;   in Loop: Header=BB0_12 Depth=1
	v_mad_u64_u32 v[28:29], null, v24, s29, s[14:15]
	v_sub_f32_e32 v23, v23, v22
	v_sub_f32_e32 v22, v19, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f32 v24, v23, v23, 1.0
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[29:30], null, v28, s28, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v24, v20, v24
	v_ashrrev_i32_e32 v30, 31, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[28:29], 2, v[29:30]
	v_add_co_u32 v28, vcc_lo, s8, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v29, vcc_lo, s9, v29, vcc_lo
	global_load_b32 v5, v[28:29], off
	v_div_scale_f32 v28, null, v14, v14, v24
	v_rcp_f32_e32 v29, v28
	s_waitcnt_depctr 0xfff
	v_fma_f32 v30, -v28, v29, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v29, v30, v29
	v_div_scale_f32 v30, vcc_lo, v24, v14, v24
	v_mul_f32_e32 v31, v30, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v32, -v28, v31, v30
	v_fmac_f32_e32 v31, v32, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v28, -v28, v31, v30
	v_div_fmas_f32 v28, v28, v29, v31
	v_cvt_f32_i32_e32 v29, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v24, v28, v14, v24
	v_sub_f32_e32 v28, v29, v25
	v_sub_f32_e32 v25, v26, v25
	v_div_scale_f32 v29, null, v23, v23, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v26, 0x4f800000, v24
	v_cmp_gt_f32_e64 s2, 0xf800000, v24
	v_cndmask_b32_e64 v26, v24, v26, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v24, v29
	v_sqrt_f32_e32 v32, v26
	s_waitcnt_depctr 0xfff
	v_fma_f32 v33, -v29, v24, 1.0
	v_add_nc_u32_e32 v36, 1, v32
	v_add_nc_u32_e32 v35, -1, v32
	v_div_scale_f32 v30, null, v25, v25, v28
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v24, v33, v24
	v_div_scale_f32 v33, vcc_lo, v22, v23, v22
	v_rcp_f32_e32 v31, v30
	v_fma_f32 v38, -v35, v32, v26
	v_fma_f32 v40, -v36, v32, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v37, v33, v24
	v_cmp_ge_f32_e64 s4, 0, v38
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f32 v41, -v29, v37, v33
	s_waitcnt_depctr 0xfff
	v_fma_f32 v34, -v30, v31, 1.0
	v_cndmask_b32_e64 v32, v32, v35, s4
	v_cmp_lt_f32_e64 s4, 0, v40
	v_fmac_f32_e32 v37, v41, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v31, v34, v31
	v_div_scale_f32 v34, s3, v28, v25, v28
	v_cndmask_b32_e64 v32, v32, v36, s4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v29, -v29, v37, v33
	v_mul_f32_e32 v39, v34, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v33, 0x37800000, v32
	v_div_fmas_f32 v24, v29, v24, v37
	s_mov_b32 vcc_lo, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v35, -v30, v39, v34
	v_div_fixup_f32 v24, v24, v23, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v39, v35, v31
	v_fma_f32 v30, -v30, v39, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v29, v30, v31, v39
	v_cndmask_b32_e64 v30, v32, v33, s2
	v_cmp_class_f32_e64 vcc_lo, v26, 0x260
	s_mov_b32 s2, exec_lo
	v_div_fixup_f32 v23, v29, v25, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v22, v30, v26, vcc_lo
	v_cmpx_ngt_f32_e32 v24, v23
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB0_55
; %bb.54:                               ;   in Loop: Header=BB0_12 Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v4, v24, v22
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr23
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr27
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v9, v4, v5
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr4
.LBB0_55:                               ; %Flow2314
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_and_not1_saveexec_b32 s2, s2
	s_cbranch_execz .LBB0_57
; %bb.56:                               ;   in Loop: Header=BB0_12 Depth=1
	v_mad_u64_u32 v[25:26], null, v27, s29, s[14:15]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[26:27], null, v25, s28, v[4:5]
	v_mul_f32_e32 v4, v22, v23
	v_fmac_f32_e32 v9, v4, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v27, 31, v26
	global_store_b32 v[2:3], v9, off
	v_lshlrev_b64 v[25:26], 2, v[26:27]
	v_add_co_u32 v4, vcc_lo, s8, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v26, vcc_lo
	global_load_b32 v4, v[4:5], off
	v_sub_f32_e32 v5, v24, v23
	v_mul_f32_e32 v5, v22, v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v9, v5, v4
.LBB0_57:                               ; %Flow2315
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s23, s23, exec_lo
.LBB0_58:                               ; %Flow2342
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s4, s23, exec_lo
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr4
.LBB0_59:                               ; %Flow2339
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_and_not1_saveexec_b32 s21, s21
	s_cbranch_execz .LBB0_63
; %bb.60:                               ;   in Loop: Header=BB0_12 Depth=1
	v_cmp_lt_i32_e32 vcc_lo, -1, v24
	v_cmp_gt_i32_e64 s2, s30, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s2
	s_mov_b32 s2, s4
	s_and_saveexec_b32 s22, s3
	s_xor_b32 s22, exec_lo, s22
	s_cbranch_execz .LBB0_62
; %bb.61:                               ;   in Loop: Header=BB0_12 Depth=1
	v_mad_u64_u32 v[25:26], null, v24, s29, s[14:15]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[26:27], null, v25, s28, v[4:5]
	v_ashrrev_i32_e32 v27, 31, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[26:27]
	v_add_co_u32 v4, vcc_lo, s8, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	v_sub_f32_e32 v5, v23, v22
	v_sub_f32_e32 v22, v19, v22
	v_fma_f32 v23, v5, v5, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v23, v20, v23
	v_div_scale_f32 v24, null, v14, v14, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v25, v24
	s_waitcnt_depctr 0xfff
	v_fma_f32 v26, -v24, v25, 1.0
	v_fmac_f32_e32 v25, v26, v25
	v_div_scale_f32 v26, vcc_lo, v23, v14, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v27, v26, v25
	v_fma_f32 v28, -v24, v27, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v27, v28, v25
	v_fma_f32 v24, -v24, v27, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v24, v24, v25, v27
	v_div_fixup_f32 v23, v24, v14, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v24, 0x4f800000, v23
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v23
	v_div_scale_f32 v25, null, v5, v5, v22
	v_cndmask_b32_e32 v23, v23, v24, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v24, v25
	v_sqrt_f32_e32 v26, v23
	s_waitcnt_depctr 0xfff
	v_fma_f32 v27, -v25, v24, 1.0
	v_add_nc_u32_e32 v28, -1, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v24, v27, v24 :: v_dual_add_nc_u32 v29, 1, v26
	v_div_scale_f32 v27, s2, v22, v5, v22
	v_fma_f32 v30, -v28, v26, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v31, -v29, v26, v23
	v_mul_f32_e32 v32, v27, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s3, 0, v30
	v_cndmask_b32_e64 v26, v26, v28, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_lt_f32_e64 s3, 0, v31
	v_fma_f32 v28, -v25, v32, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v26, v26, v29, s3
	v_fmac_f32_e32 v32, v28, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v28, 0x37800000, v26
	v_fma_f32 v25, -v25, v32, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v26, v26, v28, vcc_lo
	s_mov_b32 vcc_lo, s2
	s_or_b32 s2, s4, exec_lo
	v_div_fmas_f32 v24, v25, v24, v32
	v_cmp_class_f32_e64 vcc_lo, v23, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v5, v24, v5, v22
	v_cndmask_b32_e32 v23, v26, v23, vcc_lo
	v_mul_f32_e32 v5, v5, v23
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v9, v5, v4
.LBB0_62:                               ; %Flow2344
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s3, s4, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_or_b32 s4, s3, s2
.LBB0_63:                               ; %Flow2343
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_or_b32 exec_lo, exec_lo, s21
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s2, s4, exec_lo
.LBB0_64:                               ; %Flow2338
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s11, s2, exec_lo
                                        ; implicit-def: $vgpr23
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr26
                                        ; implicit-def: $vgpr25
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr27
.LBB0_65:                               ; %Flow2337
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_and_not1_saveexec_b32 s20, s20
	s_cbranch_execz .LBB0_93
; %bb.66:                               ;   in Loop: Header=BB0_12 Depth=1
	s_mov_b32 s4, s11
	s_mov_b32 s2, exec_lo
	v_cmpx_ne_u32_e64 v27, v24
	s_xor_b32 s21, exec_lo, s2
	s_cbranch_execz .LBB0_88
; %bb.67:                               ;   in Loop: Header=BB0_12 Depth=1
	v_cmp_gt_i32_e32 vcc_lo, 1, v27
	v_cmp_le_i32_e64 s2, s30, v27
	s_mov_b32 s23, s11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s22, exec_lo, s3
	s_cbranch_execz .LBB0_81
; %bb.68:                               ;   in Loop: Header=BB0_12 Depth=1
	s_mov_b32 s23, exec_lo
	v_cmpx_eq_u32_e32 0, v27
	s_cbranch_execz .LBB0_74
; %bb.69:                               ;   in Loop: Header=BB0_12 Depth=1
	v_sub_f32_e32 v28, v23, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v29, v28, v28, 1.0
	v_mul_f32_e32 v29, v20, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v30, null, v14, v14, v29
	v_div_scale_f32 v33, vcc_lo, v29, v14, v29
	v_rcp_f32_e32 v31, v30
	s_waitcnt_depctr 0xfff
	v_fma_f32 v32, -v30, v31, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v31, v32, v31
	v_mul_f32_e32 v32, v33, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v34, -v30, v32, v33
	v_fmac_f32_e32 v32, v34, v31
	s_waitcnt vmcnt(0)
	v_cvt_f32_i32_e32 v34, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v30, -v30, v32, v33
	v_sub_f32_e32 v33, v34, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v30, v30, v31, v32
	v_sub_f32_e32 v31, v26, v25
	v_div_scale_f32 v32, null, v28, v28, v33
	v_div_scale_f32 v38, vcc_lo, v33, v28, v33
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_fixup_f32 v29, v30, v14, v29
	v_div_scale_f32 v30, null, v31, v31, -v25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v34, v32
	v_mul_f32_e32 v35, 0x4f800000, v29
	v_cmp_gt_f32_e64 s2, 0xf800000, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v36, v30
	v_cndmask_b32_e64 v35, v29, v35, s2
	s_waitcnt_depctr 0xfff
	v_fma_f32 v29, -v32, v34, 1.0
	v_sqrt_f32_e32 v37, v35
	v_fma_f32 v39, -v30, v36, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v34, v29, v34
	v_dual_fmac_f32 v36, v39, v36 :: v_dual_mul_f32 v39, v38, v34
	v_div_scale_f32 v29, s3, -v25, v31, -v25
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v40, -1, v37
	v_add_nc_u32_e32 v43, 1, v37
	v_fma_f32 v42, -v32, v39, v38
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v44, -v40, v37, v35
	v_fmac_f32_e32 v39, v42, v34
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v42, -v43, v37, v35
	v_cmp_ge_f32_e64 s4, 0, v44
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v32, -v32, v39, v38
	v_cndmask_b32_e64 v37, v37, v40, s4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s4, 0, v42
	v_cndmask_b32_e64 v37, v37, v43, s4
	v_mul_f32_e32 v41, v29, v36
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v45, -v30, v41, v29
	v_fmac_f32_e32 v41, v45, v36
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_fma_f32 v29, -v30, v41, v29
	v_div_fmas_f32 v30, v32, v34, v39
	v_mul_f32_e32 v32, 0x37800000, v37
	s_mov_b32 vcc_lo, s3
	v_div_fmas_f32 v34, v29, v36, v41
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v29, v30, v28, v33
	v_cndmask_b32_e64 v28, v37, v32, s2
	v_cmp_class_f32_e64 vcc_lo, v35, 0x260
	s_mov_b32 s2, exec_lo
	v_div_fixup_f32 v31, v34, v31, -v25
                                        ; implicit-def: $vgpr30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v28, v28, v35, vcc_lo
	v_cmpx_ngt_f32_e32 v29, v31
	s_xor_b32 s2, exec_lo, s2
; %bb.70:                               ;   in Loop: Header=BB0_12 Depth=1
	v_sub_f32_e32 v30, 1.0, v31
                                        ; implicit-def: $vgpr29
                                        ; implicit-def: $vgpr31
; %bb.71:                               ; %Flow2329
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_and_not1_saveexec_b32 s2, s2
	s_cbranch_execz .LBB0_73
; %bb.72:                               ;   in Loop: Header=BB0_12 Depth=1
	v_dual_sub_f32 v31, v29, v31 :: v_dual_add_nc_u32 v32, s10, v4
	v_sub_f32_e32 v29, 1.0, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v33, 31, v32
	v_mul_f32_e32 v31, v28, v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[32:33], 2, v[32:33]
	v_add_co_u32 v32, vcc_lo, s8, v32
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v33, vcc_lo, s9, v33, vcc_lo
	global_load_b32 v30, v[32:33], off
	s_waitcnt vmcnt(0)
	v_dual_fmac_f32 v9, v31, v30 :: v_dual_mov_b32 v30, v28
	v_mov_b32_e32 v28, v29
	global_store_b32 v[2:3], v9, off
.LBB0_73:                               ; %.sink.split2169
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v28, v28, v30 :: v_dual_add_nc_u32 v31, s10, v5
	v_ashrrev_i32_e32 v32, 31, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[31:32], 2, v[31:32]
	v_add_co_u32 v31, vcc_lo, s8, v31
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v32, vcc_lo, s9, v32, vcc_lo
	global_load_b32 v29, v[31:32], off
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v9, v28, v29
	global_store_b32 v[2:3], v9, off
.LBB0_74:                               ; %Flow2330
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_or_b32 exec_lo, exec_lo, s23
	s_mov_b32 s2, s11
	s_mov_b32 s3, exec_lo
	v_cmpx_eq_u32_e64 s30, v27
	s_xor_b32 s23, exec_lo, s3
	s_cbranch_execz .LBB0_80
; %bb.75:                               ;   in Loop: Header=BB0_12 Depth=1
	v_mad_u64_u32 v[27:28], null, v24, s29, s[14:15]
	v_dual_sub_f32 v23, v23, v22 :: v_dual_sub_f32 v26, v26, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v24, v27, s28
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v27, v24, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v28, 31, v27
	v_lshlrev_b64 v[27:28], 2, v[27:28]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v27, vcc_lo, s8, v27
	v_add_co_ci_u32_e32 v28, vcc_lo, s9, v28, vcc_lo
	global_load_b32 v4, v[27:28], off
	v_fma_f32 v27, v23, v23, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v27, v20, v27
	v_div_scale_f32 v28, null, v14, v14, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v29, v28
	s_waitcnt_depctr 0xfff
	v_fma_f32 v30, -v28, v29, 1.0
	v_fmac_f32_e32 v29, v30, v29
	v_div_scale_f32 v30, vcc_lo, v27, v14, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v31, v30, v29
	v_fma_f32 v32, -v28, v31, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v31, v32, v29
	v_fma_f32 v28, -v28, v31, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v28, v28, v29, v31
	v_cvt_f32_i32_e32 v29, v5
	v_div_fixup_f32 v27, v28, v14, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v22, v29, v22
	v_dual_sub_f32 v28, v16, v25 :: v_dual_mul_f32 v25, 0x4f800000, v27
	v_cmp_gt_f32_e64 s2, 0xf800000, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_scale_f32 v29, null, v23, v23, v22
	v_div_scale_f32 v30, null, v26, v26, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v27, v27, v25, s2
	v_rcp_f32_e32 v25, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v31, v30
	v_sqrt_f32_e32 v32, v27
	s_delay_alu instid0(TRANS32_DEP_3)
	v_fma_f32 v33, -v29, v25, 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v34, -v30, v31, 1.0
	v_add_nc_u32_e32 v35, -1, v32
	v_fmac_f32_e32 v25, v33, v25
	v_div_scale_f32 v33, vcc_lo, v22, v23, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v31, v34, v31
	v_div_scale_f32 v34, s3, v28, v26, v28
	v_add_nc_u32_e32 v36, 1, v32
	v_fma_f32 v38, -v35, v32, v27
	v_mul_f32_e32 v37, v33, v25
	v_mul_f32_e32 v39, v34, v31
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v40, -v36, v32, v27
	v_cmp_ge_f32_e64 s4, 0, v38
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v41, -v29, v37, v33
	v_cndmask_b32_e64 v32, v32, v35, s4
	v_fma_f32 v35, -v30, v39, v34
	v_cmp_lt_f32_e64 s4, 0, v40
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v37, v41, v25
	v_fmac_f32_e32 v39, v35, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v32, v32, v36, s4
	v_fma_f32 v29, -v29, v37, v33
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v30, -v30, v39, v34
	v_mul_f32_e32 v33, 0x37800000, v32
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v25, v29, v25, v37
	s_mov_b32 vcc_lo, s3
	v_div_fmas_f32 v29, v30, v31, v39
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e64 v30, v32, v33, s2
	v_cmp_class_f32_e64 vcc_lo, v27, 0x260
	v_div_fixup_f32 v25, v25, v23, v22
	s_mov_b32 s2, exec_lo
	v_div_fixup_f32 v23, v29, v26, v28
	v_cndmask_b32_e32 v22, v30, v27, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_ngt_f32_e32 v25, v23
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB0_77
; %bb.76:                               ;   in Loop: Header=BB0_12 Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v5, v25, v22 :: v_dual_add_nc_u32 v26, v24, v5
	v_ashrrev_i32_e32 v27, 31, v26
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v9, v5, v4
	v_lshlrev_b64 v[26:27], 2, v[26:27]
	global_store_b32 v[2:3], v9, off
	v_add_co_u32 v4, vcc_lo, s8, v26
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v27, vcc_lo
	global_load_b32 v4, v[4:5], off
	v_sub_f32_e32 v5, v23, v25
                                        ; implicit-def: $vgpr23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v22, v5
                                        ; implicit-def: $vgpr22
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v9, v5, v4
                                        ; implicit-def: $vgpr4
.LBB0_77:                               ; %Flow2327
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_and_not1_saveexec_b32 s2, s2
	s_cbranch_execz .LBB0_79
; %bb.78:                               ;   in Loop: Header=BB0_12 Depth=1
	v_mul_f32_e32 v5, v22, v23
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v9, v5, v4
.LBB0_79:                               ; %Flow2328
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s2, s11, exec_lo
.LBB0_80:                               ; %Flow2348
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_or_b32 exec_lo, exec_lo, s23
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s3, s11, exec_lo
	s_and_b32 s2, s2, exec_lo
                                        ; implicit-def: $vgpr23
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr26
                                        ; implicit-def: $vgpr25
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr27
	s_or_b32 s23, s3, s2
.LBB0_81:                               ; %Flow2347
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_and_not1_saveexec_b32 s22, s22
	s_cbranch_execz .LBB0_87
; %bb.82:                               ;   in Loop: Header=BB0_12 Depth=1
	v_mad_u64_u32 v[28:29], null, v24, s29, s[14:15]
	v_dual_sub_f32 v23, v23, v22 :: v_dual_sub_f32 v26, v26, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v28, v28, s28
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v29, v28, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v30, 31, v29
	v_lshlrev_b64 v[29:30], 2, v[29:30]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v29, vcc_lo, s8, v29
	v_add_co_ci_u32_e32 v30, vcc_lo, s9, v30, vcc_lo
	global_load_b32 v24, v[29:30], off
	v_fma_f32 v29, v23, v23, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v29, v20, v29
	v_div_scale_f32 v30, null, v14, v14, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v31, v30
	s_waitcnt_depctr 0xfff
	v_fma_f32 v32, -v30, v31, 1.0
	v_fmac_f32_e32 v31, v32, v31
	v_div_scale_f32 v32, vcc_lo, v29, v14, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v33, v32, v31
	v_fma_f32 v34, -v30, v33, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v33, v34, v31
	v_fma_f32 v30, -v30, v33, v32
	v_cvt_f32_i32_e32 v32, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v30, v30, v31, v33
	v_cvt_f32_i32_e32 v31, v5
	v_div_fixup_f32 v29, v30, v14, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v22, v31, v22
	v_sub_f32_e32 v30, v32, v25
	v_mul_f32_e32 v25, 0x4f800000, v29
	v_cmp_gt_f32_e64 s2, 0xf800000, v29
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_scale_f32 v31, null, v23, v23, v22
	v_div_scale_f32 v32, null, v26, v26, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v29, v29, v25, s2
	v_rcp_f32_e32 v25, v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v33, v32
	v_sqrt_f32_e32 v34, v29
	s_delay_alu instid0(TRANS32_DEP_3)
	v_fma_f32 v35, -v31, v25, 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v36, -v32, v33, 1.0
	v_add_nc_u32_e32 v37, -1, v34
	v_fmac_f32_e32 v25, v35, v25
	v_div_scale_f32 v35, vcc_lo, v22, v23, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v33, v36, v33
	v_div_scale_f32 v36, s3, v30, v26, v30
	v_add_nc_u32_e32 v38, 1, v34
	v_fma_f32 v40, -v37, v34, v29
	v_mul_f32_e32 v39, v35, v25
	v_mul_f32_e32 v41, v36, v33
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v42, -v38, v34, v29
	v_cmp_ge_f32_e64 s4, 0, v40
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v43, -v31, v39, v35
	v_cndmask_b32_e64 v34, v34, v37, s4
	v_fma_f32 v37, -v32, v41, v36
	v_cmp_lt_f32_e64 s4, 0, v42
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v39, v43, v25
	v_fmac_f32_e32 v41, v37, v33
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v34, v34, v38, s4
	v_fma_f32 v31, -v31, v39, v35
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v32, -v32, v41, v36
	v_mul_f32_e32 v35, 0x37800000, v34
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v25, v31, v25, v39
	s_mov_b32 vcc_lo, s3
	v_div_fmas_f32 v31, v32, v33, v41
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e64 v32, v34, v35, s2
	v_cmp_class_f32_e64 vcc_lo, v29, 0x260
	v_div_fixup_f32 v25, v25, v23, v22
	s_mov_b32 s2, exec_lo
	v_div_fixup_f32 v23, v31, v26, v30
	v_cndmask_b32_e32 v22, v32, v29, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_ngt_f32_e32 v25, v23
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB0_84
; %bb.83:                               ;   in Loop: Header=BB0_12 Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v4, v25, v22
	s_waitcnt vmcnt(0)
	v_dual_fmac_f32 v9, v4, v24 :: v_dual_sub_f32 v4, v23, v25
	v_add_nc_u32_e32 v28, v28, v5
	global_store_b32 v[2:3], v9, off
	v_mul_f32_e32 v25, v22, v4
	v_ashrrev_i32_e32 v29, 31, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[28:29], 2, v[28:29]
	v_add_co_u32 v28, vcc_lo, s8, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v29, vcc_lo, s9, v29, vcc_lo
	global_load_b32 v24, v[28:29], off
	v_mad_u64_u32 v[28:29], null, v27, s29, s[14:15]
	v_mad_u64_u32 v[26:27], null, v28, s28, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v27, 31, v26
	v_lshlrev_b64 v[4:5], 2, v[26:27]
                                        ; implicit-def: $vgpr27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s8, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v9, v25, v24
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr25
	global_store_b32 v[2:3], v9, off
	global_load_b32 v4, v[4:5], off
	v_sub_f32_e32 v5, 1.0, v23
                                        ; implicit-def: $vgpr23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v22, v5
                                        ; implicit-def: $vgpr22
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v9, v5, v4
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr5
.LBB0_84:                               ; %Flow2331
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_and_not1_saveexec_b32 s2, s2
	s_cbranch_execz .LBB0_86
; %bb.85:                               ;   in Loop: Header=BB0_12 Depth=1
	v_mad_u64_u32 v[28:29], null, v27, s29, s[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v28, v28, s28
	v_add_nc_u32_e32 v26, v28, v4
	v_mul_f32_e32 v4, v22, v23
	v_sub_f32_e32 v23, v25, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v27, 31, v26
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v9, v4, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v23, v22, v23 :: v_dual_add_nc_u32 v4, v28, v5
	v_lshlrev_b64 v[26:27], 2, v[26:27]
	global_store_b32 v[2:3], v9, off
	v_ashrrev_i32_e32 v5, 31, v4
	v_add_co_u32 v26, vcc_lo, s8, v26
	v_add_co_ci_u32_e32 v27, vcc_lo, s9, v27, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	global_load_b32 v24, v[26:27], off
	v_add_co_u32 v4, vcc_lo, s8, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v9, v23, v24
	global_store_b32 v[2:3], v9, off
	global_load_b32 v4, v[4:5], off
	v_sub_f32_e32 v5, 1.0, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v5, v22
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v9, v5, v4
.LBB0_86:                               ; %Flow2332
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s23, s23, exec_lo
.LBB0_87:                               ; %Flow2349
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s2, s11, exec_lo
	s_and_b32 s3, s23, exec_lo
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr4
	s_or_b32 s4, s2, s3
.LBB0_88:                               ; %Flow2346
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_and_not1_saveexec_b32 s21, s21
	s_cbranch_execz .LBB0_92
; %bb.89:                               ;   in Loop: Header=BB0_12 Depth=1
	s_waitcnt vmcnt(0)
	v_cmp_lt_i32_e32 vcc_lo, -1, v24
	v_cmp_gt_i32_e64 s2, s30, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s2
	s_mov_b32 s2, s4
	s_and_saveexec_b32 s22, s3
	s_xor_b32 s22, exec_lo, s22
	s_cbranch_execz .LBB0_91
; %bb.90:                               ;   in Loop: Header=BB0_12 Depth=1
	v_mad_u64_u32 v[25:26], null, v24, s29, s[14:15]
	v_sub_f32_e32 v23, v23, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v26, v25, s28
	v_add_nc_u32_e32 v24, v26, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v4, v23, v23, 1.0
	v_ashrrev_i32_e32 v25, 31, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v4, v20, v4
	v_lshlrev_b64 v[24:25], 2, v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v24, vcc_lo, s8, v24
	v_add_co_ci_u32_e32 v25, vcc_lo, s9, v25, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_div_scale_f32 v29, vcc_lo, v4, v14, v4
	global_load_b32 v24, v[24:25], off
	v_div_scale_f32 v25, null, v14, v14, v4
	v_rcp_f32_e32 v27, v25
	s_waitcnt_depctr 0xfff
	v_fma_f32 v28, -v25, v27, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v27, v28, v27
	v_mul_f32_e32 v28, v29, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v30, -v25, v28, v29
	v_fmac_f32_e32 v28, v30, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f32 v25, -v25, v28, v29
	v_cvt_f32_i32_e32 v29, v5
	v_sub_f32_e32 v22, v29, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v25, v25, v27, v28
	v_div_scale_f32 v30, vcc_lo, v22, v23, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v4, v25, v14, v4
	v_div_scale_f32 v25, null, v23, v23, v22
	v_mul_f32_e32 v27, 0x4f800000, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v28, v25
	v_cmp_gt_f32_e64 s2, 0xf800000, v4
	v_cndmask_b32_e64 v27, v4, v27, s2
	s_waitcnt_depctr 0xfff
	v_fma_f32 v29, -v25, v28, 1.0
	v_sqrt_f32_e32 v4, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v28, v29, v28
	v_mul_f32_e32 v31, v30, v28
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v29, -1, v4
	v_fma_f32 v34, -v25, v31, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v33, -v29, v4, v27
	v_fmac_f32_e32 v31, v34, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ge_f32_e64 s3, 0, v33
	v_fma_f32 v25, -v25, v31, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v25, v25, v28, v31
	v_cmp_class_f32_e64 vcc_lo, v27, 0x260
	v_add_nc_u32_e32 v32, 1, v4
	v_div_fixup_f32 v22, v25, v23, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v35, -v32, v4, v27
	v_cndmask_b32_e64 v4, v4, v29, s3
	v_cmp_lt_f32_e64 s3, 0, v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v4, v4, v32, s3
	v_mul_f32_e32 v29, 0x37800000, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v28, v4, v29, s2
	v_add_nc_u32_e32 v4, v26, v5
	s_or_b32 s2, s4, exec_lo
	v_cndmask_b32_e32 v23, v28, v27, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v5, 31, v4
	v_mul_f32_e32 v25, v22, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v4, vcc_lo, s8, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v9, v25, v24
	global_store_b32 v[2:3], v9, off
	global_load_b32 v4, v[4:5], off
	v_sub_f32_e32 v5, 1.0, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v5, v23
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v9, v5, v4
.LBB0_91:                               ; %Flow2351
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s3, s4, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_or_b32 s4, s3, s2
.LBB0_92:                               ; %Flow2350
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_or_b32 exec_lo, exec_lo, s21
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s2, s11, exec_lo
	s_and_b32 s3, s4, exec_lo
	s_or_b32 s11, s2, s3
.LBB0_93:                               ; %Flow2345
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_or_b32 exec_lo, exec_lo, s20
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s4, s11, exec_lo
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr27
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr25
                                        ; implicit-def: $vgpr26
.LBB0_94:                               ; %Flow2336
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_and_not1_saveexec_b32 s11, s19
	s_cbranch_execz .LBB0_112
; %bb.95:                               ;   in Loop: Header=BB0_12 Depth=1
	s_waitcnt vmcnt(0)
	v_cmp_lt_i32_e32 vcc_lo, -1, v4
	v_cmp_gt_i32_e64 s2, s28, v4
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s3, vcc_lo, s2
	s_mov_b32 s2, s4
	s_and_saveexec_b32 s19, s3
	s_cbranch_execz .LBB0_111
; %bb.96:                               ;   in Loop: Header=BB0_12 Depth=1
	s_mov_b32 s3, s4
	s_mov_b32 s2, exec_lo
	v_cmpx_ne_u32_e64 v27, v24
	s_xor_b32 s20, exec_lo, s2
	s_cbranch_execz .LBB0_106
; %bb.97:                               ;   in Loop: Header=BB0_12 Depth=1
	v_cmp_gt_i32_e32 vcc_lo, 1, v27
	v_cmp_le_i32_e64 s2, s30, v27
	s_mov_b32 s22, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s21, exec_lo, s3
	s_cbranch_execz .LBB0_103
; %bb.98:                               ;   in Loop: Header=BB0_12 Depth=1
	s_mov_b32 s22, exec_lo
	v_cmpx_eq_u32_e32 0, v27
	s_cbranch_execz .LBB0_100
; %bb.99:                               ;   in Loop: Header=BB0_12 Depth=1
	v_add_nc_u32_e32 v28, s10, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v29, 31, v28
	v_lshlrev_b64 v[28:29], 2, v[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v28, vcc_lo, s8, v28
	v_add_co_ci_u32_e32 v29, vcc_lo, s9, v29, vcc_lo
	global_load_b32 v5, v[28:29], off
	v_sub_f32_e32 v28, v23, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v28, v28, v28, 1.0
	v_mul_f32_e32 v28, v20, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v29, null, v14, v14, v28
	v_rcp_f32_e32 v30, v29
	s_waitcnt_depctr 0xfff
	v_fma_f32 v31, -v29, v30, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v30, v31, v30
	v_div_scale_f32 v31, vcc_lo, v28, v14, v28
	v_mul_f32_e32 v32, v31, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v33, -v29, v32, v31
	v_fmac_f32_e32 v32, v33, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v29, -v29, v32, v31
	v_div_fmas_f32 v29, v29, v30, v32
	v_sub_f32_e32 v30, v26, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v28, v29, v14, v28
	v_div_scale_f32 v29, null, v30, v30, -v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v31, 0x4f800000, v28
	v_cmp_gt_f32_e64 s2, 0xf800000, v28
	v_rcp_f32_e32 v32, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v28, v28, v31, s2
	v_sqrt_f32_e32 v31, v28
	s_waitcnt_depctr 0xfff
	v_fma_f32 v33, -v29, v32, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v32, v33, v32
	v_div_scale_f32 v33, vcc_lo, -v25, v30, -v25
	v_add_nc_u32_e32 v34, -1, v31
	v_dual_mul_f32 v36, v33, v32 :: v_dual_add_nc_u32 v35, 1, v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v37, -v34, v31, v28
	v_fma_f32 v38, -v35, v31, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v39, -v29, v36, v33
	v_cmp_ge_f32_e64 s3, 0, v37
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v36, v39, v32
	v_cndmask_b32_e64 v31, v31, v34, s3
	v_cmp_lt_f32_e64 s3, 0, v38
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v29, -v29, v36, v33
	v_cndmask_b32_e64 v31, v31, v35, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v29, v29, v32, v36
	v_cmp_class_f32_e64 vcc_lo, v28, 0x260
	v_mul_f32_e32 v33, 0x37800000, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v29, v29, v30, -v25
	v_cndmask_b32_e64 v31, v31, v33, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v29, 1.0, v29 :: v_dual_cndmask_b32 v28, v31, v28
	v_mul_f32_e32 v28, v28, v29
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v9, v28, v5
	global_store_b32 v[2:3], v9, off
.LBB0_100:                              ;   in Loop: Header=BB0_12 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	s_mov_b32 s2, s4
	s_mov_b32 s3, exec_lo
	v_cmpx_eq_u32_e64 s30, v27
	s_xor_b32 s22, exec_lo, s3
	s_cbranch_execz .LBB0_102
; %bb.101:                              ;   in Loop: Header=BB0_12 Depth=1
	v_mad_u64_u32 v[27:28], null, v24, s29, s[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[28:29], null, v27, s28, v[4:5]
	v_ashrrev_i32_e32 v29, 31, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[28:29]
	v_add_co_u32 v4, vcc_lo, s8, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	v_sub_f32_e32 v5, v23, v22
	v_fma_f32 v5, v5, v5, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v20, v5
	v_div_scale_f32 v22, null, v14, v14, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v23, v22
	s_waitcnt_depctr 0xfff
	v_fma_f32 v24, -v22, v23, 1.0
	v_fmac_f32_e32 v23, v24, v23
	v_div_scale_f32 v24, vcc_lo, v5, v14, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v27, v24, v23
	v_fma_f32 v28, -v22, v27, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v27, v28, v23
	v_fma_f32 v22, -v22, v27, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v22, v22, v23, v27
	v_sub_f32_e32 v23, v26, v25
	v_div_fixup_f32 v5, v22, v14, v5
	v_sub_f32_e32 v22, v16, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v24, 0x4f800000, v5
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v5
	v_div_scale_f32 v25, null, v23, v23, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v5, v5, v24, vcc_lo
	v_rcp_f32_e32 v24, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v26, v5
	s_waitcnt_depctr 0xfff
	v_fma_f32 v27, -v25, v24, 1.0
	v_add_nc_u32_e32 v28, -1, v26
	v_fmac_f32_e32 v24, v27, v24
	v_div_scale_f32 v27, s2, v22, v23, v22
	v_add_nc_u32_e32 v29, 1, v26
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v30, -v28, v26, v5
	v_mul_f32_e32 v32, v27, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v31, -v29, v26, v5
	v_cmp_ge_f32_e64 s3, 0, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v26, v26, v28, s3
	v_cmp_lt_f32_e64 s3, 0, v31
	v_fma_f32 v28, -v25, v32, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v26, v26, v29, s3
	v_fmac_f32_e32 v32, v28, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v28, 0x37800000, v26
	v_fma_f32 v25, -v25, v32, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v26, v26, v28, vcc_lo
	s_mov_b32 vcc_lo, s2
	s_or_b32 s2, s4, exec_lo
	v_div_fmas_f32 v24, v25, v24, v32
	v_cmp_class_f32_e64 vcc_lo, v5, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v22, v24, v23, v22
	v_cndmask_b32_e32 v5, v26, v5, vcc_lo
	v_mul_f32_e32 v5, v5, v22
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v9, v5, v4
.LBB0_102:                              ; %Flow2356
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s3, s4, exec_lo
	s_and_b32 s2, s2, exec_lo
                                        ; implicit-def: $vgpr23
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr27
                                        ; implicit-def: $vgpr25
                                        ; implicit-def: $vgpr26
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr4
	s_or_b32 s22, s3, s2
.LBB0_103:                              ; %Flow2355
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_and_not1_saveexec_b32 s21, s21
	s_cbranch_execz .LBB0_105
; %bb.104:                              ;   in Loop: Header=BB0_12 Depth=1
	v_mad_u64_u32 v[28:29], null, v24, s29, s[14:15]
	s_or_b32 s22, s22, exec_lo
	v_sub_f32_e32 v26, v26, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[29:30], null, v28, s28, v[4:5]
	v_sub_f32_e32 v5, v23, v22
	v_fma_f32 v5, v5, v5, 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v30, 31, v29
	v_mul_f32_e32 v5, v20, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[28:29], 2, v[29:30]
	v_div_scale_f32 v22, null, v14, v14, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v28, vcc_lo, s8, v28
	v_add_co_ci_u32_e32 v29, vcc_lo, s9, v29, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v23, v22
	global_load_b32 v28, v[28:29], off
	v_div_scale_f32 v29, vcc_lo, v5, v14, v5
	v_fma_f32 v24, -v22, v23, 1.0
	v_fmac_f32_e32 v23, v24, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v24, v29, v23
	v_fma_f32 v30, -v22, v24, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v24, v30, v23
	v_fma_f32 v22, -v22, v24, v29
	v_cvt_f32_i32_e32 v29, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v22, v22, v23, v24
	v_div_fixup_f32 v5, v22, v14, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v22, 0x4f800000, v5
	v_cmp_gt_f32_e64 s2, 0xf800000, v5
	v_cndmask_b32_e64 v5, v5, v22, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sqrt_f32_e32 v22, v5
	s_waitcnt_depctr 0xfff
	v_dual_sub_f32 v25, v29, v25 :: v_dual_add_nc_u32 v32, 1, v22
	v_div_scale_f32 v24, null, v26, v26, v25
	v_div_scale_f32 v30, vcc_lo, v25, v26, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v35, -v32, v22, v5
	v_rcp_f32_e32 v29, v24
	s_waitcnt_depctr 0xfff
	v_fma_f32 v23, -v24, v29, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v29, v23, v29
	v_add_nc_u32_e32 v23, -1, v22
	v_mul_f32_e32 v31, v30, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v33, -v23, v22, v5
	v_fma_f32 v34, -v24, v31, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ge_f32_e64 s3, 0, v33
	v_fmac_f32_e32 v31, v34, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v33, v22, v23, s3
	v_cmp_lt_f32_e64 s3, 0, v35
	v_mad_u64_u32 v[22:23], null, v27, s29, s[14:15]
	v_fma_f32 v30, -v24, v31, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v27, v33, v32, s3
	v_mad_u64_u32 v[23:24], null, v22, s28, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v4, 0x37800000, v27
	v_div_fmas_f32 v22, v30, v29, v31
	v_cmp_class_f32_e64 vcc_lo, v5, 0x260
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v4, v27, v4, s2
	v_ashrrev_i32_e32 v24, 31, v23
	v_div_fixup_f32 v22, v22, v26, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v25, v4, v5, vcc_lo
	v_lshlrev_b64 v[4:5], 2, v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v26, v25, v22
	v_add_co_u32 v4, vcc_lo, s8, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v9, v26, v28
	global_store_b32 v[2:3], v9, off
	global_load_b32 v4, v[4:5], off
	v_sub_f32_e32 v5, 1.0, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v25, v5
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v9, v5, v4
.LBB0_105:                              ; %Flow2357
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_or_b32 exec_lo, exec_lo, s21
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s2, s4, exec_lo
	s_and_b32 s3, s22, exec_lo
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr4
	s_or_b32 s3, s2, s3
.LBB0_106:                              ; %Flow2354
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_and_not1_saveexec_b32 s20, s20
	s_cbranch_execz .LBB0_110
; %bb.107:                              ;   in Loop: Header=BB0_12 Depth=1
	v_cmp_lt_i32_e32 vcc_lo, -1, v24
	v_cmp_gt_i32_e64 s2, s30, v24
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s22, vcc_lo, s2
	s_mov_b32 s2, s3
	s_and_saveexec_b32 s21, s22
	s_cbranch_execz .LBB0_109
; %bb.108:                              ;   in Loop: Header=BB0_12 Depth=1
	v_mad_u64_u32 v[25:26], null, v24, s29, s[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[26:27], null, v25, s28, v[4:5]
	v_ashrrev_i32_e32 v27, 31, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[26:27]
	v_add_co_u32 v4, vcc_lo, s8, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	v_sub_f32_e32 v5, v23, v22
	v_fma_f32 v5, v5, v5, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v20, v5
	v_div_scale_f32 v22, null, v14, v14, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v23, v22
	s_waitcnt_depctr 0xfff
	v_fma_f32 v24, -v22, v23, 1.0
	v_fmac_f32_e32 v23, v24, v23
	v_div_scale_f32 v24, vcc_lo, v5, v14, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v25, v24, v23
	v_fma_f32 v26, -v22, v25, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v25, v26, v23
	v_fma_f32 v22, -v22, v25, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v22, v22, v23, v25
	v_div_fixup_f32 v5, v22, v14, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v22, 0x4f800000, v5
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v5
	v_cndmask_b32_e32 v5, v5, v22, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v22, v5
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v23, -1, v22
	v_add_nc_u32_e32 v24, 1, v22
	v_fma_f32 v25, -v23, v22, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v26, -v24, v22, v5
	v_cmp_ge_f32_e64 s2, 0, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v22, v22, v23, s2
	v_cmp_lt_f32_e64 s2, 0, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v22, v22, v24, s2
	s_or_b32 s2, s3, exec_lo
	v_mul_f32_e32 v23, 0x37800000, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v22, v22, v23, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v5, 0x260
	v_cndmask_b32_e32 v5, v22, v5, vcc_lo
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v9, v5, v4
.LBB0_109:                              ; %Flow2359
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_or_b32 exec_lo, exec_lo, s21
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s3, s3, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_or_b32 s3, s3, s2
.LBB0_110:                              ; %Flow2358
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_or_b32 exec_lo, exec_lo, s20
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s2, s4, exec_lo
	s_and_b32 s3, s3, exec_lo
	s_or_b32 s2, s2, s3
.LBB0_111:                              ; %Flow2353
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_or_b32 exec_lo, exec_lo, s19
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s3, s4, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_or_b32 s4, s3, s2
.LBB0_112:                              ; %Flow2352
                                        ;   in Loop: Header=BB0_12 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	s_and_saveexec_b32 s2, s4
	s_cbranch_execz .LBB0_114
; %bb.113:                              ; %.sink.split2178
                                        ;   in Loop: Header=BB0_12 Depth=1
	global_store_b32 v[2:3], v9, off
.LBB0_114:                              ;   in Loop: Header=BB0_12 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_add_i32 s14, s14, 1
	s_add_i32 s10, s10, s28
	s_cmp_lg_u32 s29, s14
	s_cbranch_scc1 .LBB0_12
.LBB0_115:                              ; %Flow2361
                                        ; implicit-def: $vgpr11
                                        ; implicit-def: $vgpr12
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr13
                                        ; implicit-def: $vgpr4
.LBB0_116:                              ; %Flow2413
	s_and_not1_saveexec_b32 s14, s17
	s_cbranch_execz .LBB0_223
; %bb.117:
	s_cmp_lt_i32 s28, 1
	s_cbranch_scc1 .LBB0_222
; %bb.118:                              ; %.lr.ph2116
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v5, v5, v12
	v_sub_f32_e32 v9, v13, v11
	s_sub_i32 s5, 0, s5
	s_mov_b64 s[10:11], 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_scale_f32 v14, null, v9, v9, v5
	v_div_scale_f32 v15, null, v9, v9, v4
	v_div_scale_f32 v19, vcc_lo, v5, v9, v5
	v_rcp_f32_e32 v16, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v17, v15
	s_waitcnt_depctr 0xfff
	v_fma_f32 v13, -v14, v16, 1.0
	v_fma_f32 v18, -v15, v17, 1.0
	v_dual_fmac_f32 v16, v13, v16 :: v_dual_fmac_f32 v17, v18, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v18, v19, v16
	v_div_scale_f32 v20, s0, v4, v9, v4
	v_fma_f32 v13, -v14, v18, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v21, v20, v17 :: v_dual_fmac_f32 v18, v13, v16
	v_fma_f32 v22, -v15, v21, v20
	v_cvt_f32_i32_e32 v13, s15
	s_mul_i32 s15, s29, s28
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f32 v19, -v14, v18, v19
	v_mul_f32_e32 v14, v6, v6
	v_fmac_f32_e32 v21, v22, v17
	v_div_fmas_f32 v18, v19, v16, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v14, v7, v7
	v_fma_f32 v15, -v15, v21, v20
	s_mov_b32 vcc_lo, s0
	v_cvt_f32_i32_e32 v16, s30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v20, v8, v8, v14
	v_div_fmas_f32 v19, v15, v17, v21
	v_div_fixup_f32 v17, v18, v9, v5
	v_cvt_f32_i32_e32 v15, s16
	v_mov_b32_e32 v21, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_div_fixup_f32 v18, v19, v9, v4
	v_cvt_f32_i32_e32 v19, s29
	v_mov_b32_e32 v9, 0
	v_cmp_nle_f32_e64 s0, 0, v17
	v_cmp_nle_f32_e64 s1, 0, v18
.LBB0_119:                              ; =>This Inner Loop Header: Depth=1
	s_add_i32 s2, s5, s10
	s_mov_b32 s4, 0
	s_waitcnt vmcnt(0)
	v_cvt_f32_i32_e32 v4, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, 1.0, v4
	v_cndmask_b32_e64 v22, v5, v4, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v22, v22, v11
	v_cndmask_b32_e64 v23, v4, v5, s1
	v_cndmask_b32_e64 v33, v4, v5, s0
	v_cndmask_b32_e64 v4, v5, v4, s0
	v_fma_f32 v24, v18, v22, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v5, v33, v11
	v_sub_f32_e32 v4, v4, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_div_scale_f32 v22, null, s27, s27, v24
	v_div_scale_f32 v30, vcc_lo, v24, s27, v24
	v_fma_f32 v5, v17, v5, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v26, v22
	v_fma_f32 v4, v17, v4, v12
	s_waitcnt_depctr 0xfff
	v_fma_f32 v28, -v22, v26, 1.0
	v_dual_sub_f32 v23, v23, v11 :: v_dual_fmac_f32 v26, v28, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v23, v18, v23, v10
	v_div_scale_f32 v25, null, s27, s27, v23
	v_div_scale_f32 v28, s2, v23, s27, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v27, v25
	s_waitcnt_depctr 0xfff
	v_fma_f32 v29, -v25, v27, 1.0
	v_fmac_f32_e32 v27, v29, v27
	v_mul_f32_e32 v29, v30, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v31, v28, v27
	v_fma_f32 v32, -v22, v29, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v29, v32, v26
	v_fma_f32 v22, -v22, v29, v30
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fmas_f32 v26, v22, v26, v29
	v_add_f32_e32 v22, v5, v13
	v_fma_f32 v34, -v25, v31, v28
	s_mov_b32 vcc_lo, s2
	s_mov_b32 s2, exec_lo
	v_div_fixup_f32 v5, v26, s27, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v31, v34, v27
	v_add_f32_e32 v26, v5, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v25, -v25, v31, v28
	v_div_fmas_f32 v25, v25, v27, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v24, v25, s27, v23
	v_add_f32_e32 v23, v4, v13
	v_floor_f32_e32 v4, v22
	v_add_f32_e32 v25, v24, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_floor_f32_e32 v5, v23
	v_floor_f32_e32 v24, v26
	v_cvt_i32_f32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_floor_f32_e32 v28, v25
	v_cvt_i32_f32_e32 v5, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_i32_f32_e32 v27, v24
	v_cvt_i32_f32_e32 v24, v28
	s_delay_alu instid0(VALU_DEP_3)
	v_cmpx_ne_u32_e64 v5, v4
	s_xor_b32 s16, exec_lo, s2
	s_cbranch_execz .LBB0_201
; %bb.120:                              ;   in Loop: Header=BB0_119 Depth=1
	v_cmp_gt_i32_e32 vcc_lo, 1, v5
	v_cmp_le_i32_e64 s2, s29, v5
	s_mov_b32 s18, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s17, exec_lo, s3
	s_cbranch_execz .LBB0_172
; %bb.121:                              ;   in Loop: Header=BB0_119 Depth=1
	s_mov_b32 s18, exec_lo
	v_cmpx_eq_u32_e32 0, v5
	s_cbranch_execz .LBB0_145
; %bb.122:                              ;   in Loop: Header=BB0_119 Depth=1
                                        ; implicit-def: $vgpr28
                                        ; implicit-def: $vgpr29
	s_mov_b32 s2, exec_lo
	v_cmpx_ne_u32_e64 v27, v24
	s_xor_b32 s19, exec_lo, s2
	s_cbranch_execz .LBB0_138
; %bb.123:                              ;   in Loop: Header=BB0_119 Depth=1
	v_cmp_gt_i32_e32 vcc_lo, 1, v27
	v_cmp_le_i32_e64 s2, s30, v27
	s_mov_b32 s21, 0
                                        ; implicit-def: $vgpr28
                                        ; implicit-def: $vgpr29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s20, exec_lo, s3
	s_cbranch_execz .LBB0_131
; %bb.124:                              ;   in Loop: Header=BB0_119 Depth=1
	s_mov_b32 s21, exec_lo
	v_cmpx_eq_u32_e32 0, v27
	s_cbranch_execz .LBB0_126
; %bb.125:                              ; %.sink.split2158
                                        ;   in Loop: Header=BB0_119 Depth=1
	global_load_b32 v28, v21, s[6:7]
	v_sub_f32_e32 v29, v23, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v30, v29, v29, 1.0
	v_mul_f32_e32 v30, v20, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v31, null, v14, v14, v30
	v_rcp_f32_e32 v32, v31
	s_waitcnt_depctr 0xfff
	v_fma_f32 v33, -v31, v32, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v32, v33, v32
	v_div_scale_f32 v33, vcc_lo, v30, v14, v30
	v_mul_f32_e32 v34, v33, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v35, -v31, v34, v33
	v_fmac_f32_e32 v34, v35, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v31, -v31, v34, v33
	v_div_scale_f32 v33, null, v29, v29, -v22
	v_div_fmas_f32 v31, v31, v32, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v30, v31, v14, v30
	v_dual_sub_f32 v31, v26, v25 :: v_dual_mul_f32 v32, 0x4f800000, v30
	v_cmp_gt_f32_e64 s2, 0xf800000, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f32 v34, null, v31, v31, -v25
	v_cndmask_b32_e64 v30, v30, v32, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v35, v34
	v_rcp_f32_e32 v32, v33
	v_sqrt_f32_e32 v36, v30
	s_delay_alu instid0(TRANS32_DEP_3)
	v_fma_f32 v38, -v34, v35, 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v37, -v33, v32, 1.0
	v_add_nc_u32_e32 v39, -1, v36
	v_fmac_f32_e32 v35, v38, v35
	v_div_scale_f32 v38, s3, -v25, v31, -v25
	v_add_nc_u32_e32 v40, 1, v36
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v42, -v39, v36, v30
	v_mul_f32_e32 v43, v38, v35
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v44, -v40, v36, v30
	v_cmp_ge_f32_e64 s4, 0, v42
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v36, v36, v39, s4
	v_fma_f32 v39, -v34, v43, v38
	v_fmac_f32_e32 v32, v37, v32
	v_div_scale_f32 v37, vcc_lo, -v22, v29, -v22
	v_cmp_lt_f32_e64 s4, 0, v44
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v43, v39, v35
	v_mul_f32_e32 v41, v37, v32
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v34, -v34, v43, v38
	v_fma_f32 v45, -v33, v41, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v41, v45, v32
	v_fma_f32 v33, -v33, v41, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v32, v33, v32, v41
	s_mov_b32 vcc_lo, s3
	v_div_fmas_f32 v33, v34, v35, v43
	v_cmp_class_f32_e64 vcc_lo, v30, 0x260
	v_div_fixup_f32 v29, v32, v29, -v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v31, v33, v31, -v25
	v_sub_f32_e32 v33, 1.0, v29
	v_cndmask_b32_e64 v36, v36, v40, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v32, 1.0, v31 :: v_dual_mul_f32 v37, 0x37800000, v36
	v_cndmask_b32_e64 v34, v36, v37, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v30, v34, v30, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, v29, v31
	v_dual_cndmask_b32 v29, v32, v30 :: v_dual_cndmask_b32 v30, v30, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v29, v30, v29
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v9, v29, v28
	global_store_b32 v[2:3], v9, off
.LBB0_126:                              ;   in Loop: Header=BB0_119 Depth=1
	s_or_b32 exec_lo, exec_lo, s21
	s_mov_b32 s2, 0
	s_mov_b32 s3, exec_lo
                                        ; implicit-def: $vgpr28
	v_cmpx_eq_u32_e64 s30, v27
	s_cbranch_execz .LBB0_130
; %bb.127:                              ;   in Loop: Header=BB0_119 Depth=1
	v_dual_sub_f32 v29, v23, v22 :: v_dual_sub_f32 v28, v16, v25
	v_sub_f32_e32 v31, v26, v25
	s_mov_b32 s4, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f32 v30, null, v29, v29, -v22
	v_div_scale_f32 v32, null, v31, v31, v28
	v_div_scale_f32 v37, vcc_lo, -v22, v29, -v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v33, v30
	v_rcp_f32_e32 v34, v32
	s_waitcnt_depctr 0xfff
	v_fma_f32 v35, -v30, v33, 1.0
	v_fma_f32 v36, -v32, v34, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v34, v36, v34 :: v_dual_fmac_f32 v33, v35, v33
	v_div_scale_f32 v35, s2, v28, v31, v28
	v_mul_f32_e32 v38, v35, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v40, -v32, v38, v35
	v_fmac_f32_e32 v38, v40, v34
	v_mul_f32_e32 v36, v37, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v32, -v32, v38, v35
	v_fma_f32 v39, -v30, v36, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v36, v39, v33
	v_fma_f32 v30, -v30, v36, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v30, v30, v33, v36
	s_mov_b32 vcc_lo, s2
	s_mov_b32 s2, exec_lo
	v_div_fmas_f32 v32, v32, v34, v38
	v_div_fixup_f32 v30, v30, v29, -v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v31, v32, v31, v28
                                        ; implicit-def: $vgpr28
	v_cmpx_ngt_f32_e32 v30, v31
	s_xor_b32 s21, exec_lo, s2
	s_cbranch_execz .LBB0_129
; %bb.128:                              ;   in Loop: Header=BB0_119 Depth=1
	v_fma_f32 v28, v29, v29, 1.0
	s_mov_b32 s4, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v28, v20, v28
	v_div_scale_f32 v29, null, v14, v14, v28
	v_div_scale_f32 v34, vcc_lo, v28, v14, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v32, v29
	s_waitcnt_depctr 0xfff
	v_fma_f32 v33, -v29, v32, 1.0
	v_fmac_f32_e32 v32, v33, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v33, v34, v32
	v_fma_f32 v35, -v29, v33, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v33, v35, v32
	v_fma_f32 v29, -v29, v33, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v29, v29, v32, v33
	v_div_fixup_f32 v28, v29, v14, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v29, 0x4f800000, v28
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v28
	v_cndmask_b32_e32 v28, v28, v29, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v29, v28
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v32, -1, v29
	v_add_nc_u32_e32 v33, 1, v29
	v_fma_f32 v34, -v32, v29, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v35, -v33, v29, v28
	v_cmp_ge_f32_e64 s2, 0, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v29, v29, v32, s2
	v_cmp_lt_f32_e64 s2, 0, v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v29, v29, v33, s2
	v_mul_f32_e32 v32, 0x37800000, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v29, v29, v32, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v28, 0x260
	v_dual_cndmask_b32 v28, v29, v28 :: v_dual_sub_f32 v29, v31, v30
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v28, v28, v29
.LBB0_129:                              ; %Flow2373
                                        ;   in Loop: Header=BB0_119 Depth=1
	s_or_b32 exec_lo, exec_lo, s21
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s2, s4, exec_lo
.LBB0_130:                              ; %Flow2372
                                        ;   in Loop: Header=BB0_119 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	v_mov_b32_e32 v29, v24
	s_and_b32 s21, s2, exec_lo
.LBB0_131:                              ; %Flow2371
                                        ;   in Loop: Header=BB0_119 Depth=1
	s_and_not1_saveexec_b32 s20, s20
	s_cbranch_execz .LBB0_137
; %bb.132:                              ;   in Loop: Header=BB0_119 Depth=1
	v_sub_f32_e32 v28, v23, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v29, v28, v28, 1.0
	v_mul_f32_e32 v29, v20, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v30, null, v14, v14, v29
	v_div_scale_f32 v33, vcc_lo, v29, v14, v29
	v_rcp_f32_e32 v31, v30
	s_waitcnt_depctr 0xfff
	v_fma_f32 v32, -v30, v31, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v31, v32, v31
	v_mul_f32_e32 v32, v33, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v34, -v30, v32, v33
	v_fmac_f32_e32 v32, v34, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v30, -v30, v32, v33
	v_cvt_f32_i32_e32 v33, v27
	v_div_fmas_f32 v30, v30, v31, v32
	v_sub_f32_e32 v31, v26, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v32, v33, v25
	v_div_scale_f32 v33, null, v28, v28, -v22
	v_div_fixup_f32 v29, v30, v14, v29
	v_div_scale_f32 v38, vcc_lo, -v22, v28, -v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_scale_f32 v30, null, v31, v31, v32
	v_mul_f32_e32 v35, 0x4f800000, v29
	v_rcp_f32_e32 v34, v33
	v_cmp_gt_f32_e64 s2, 0xf800000, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v36, v30
	v_cndmask_b32_e64 v29, v29, v35, s2
	s_waitcnt_depctr 0xfff
	v_fma_f32 v35, -v33, v34, 1.0
	v_sqrt_f32_e32 v37, v29
	v_fma_f32 v39, -v30, v36, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v34, v35, v34
	v_div_scale_f32 v35, s3, v32, v31, v32
	s_waitcnt_depctr 0xfff
	v_dual_fmac_f32 v36, v39, v36 :: v_dual_add_nc_u32 v43, 1, v37
	v_dual_mul_f32 v39, v38, v34 :: v_dual_add_nc_u32 v40, -1, v37
	v_mul_f32_e32 v41, v35, v36
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v42, -v33, v39, v38
	v_fma_f32 v44, -v40, v37, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v45, -v30, v41, v35
	v_fmac_f32_e32 v39, v42, v34
	v_fma_f32 v42, -v43, v37, v29
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_ge_f32_e64 s4, 0, v44
	v_fmac_f32_e32 v41, v45, v36
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v33, -v33, v39, v38
	v_cndmask_b32_e64 v37, v37, v40, s4
	v_cmp_lt_f32_e64 s4, 0, v42
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v30, -v30, v41, v35
	v_div_fmas_f32 v33, v33, v34, v39
	s_mov_b32 vcc_lo, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v37, v37, v43, s4
	v_div_fmas_f32 v35, v30, v36, v41
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_div_fixup_f32 v30, v33, v28, -v22
	v_cmp_class_f32_e64 vcc_lo, v29, 0x260
	v_mul_f32_e32 v34, 0x37800000, v37
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v31, v35, v31, v32
	v_cndmask_b32_e64 v28, v37, v34, s2
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v29, v28, v29, vcc_lo
                                        ; implicit-def: $vgpr28
	v_cmpx_ngt_f32_e32 v30, v31
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB0_134
; %bb.133:                              ;   in Loop: Header=BB0_119 Depth=1
	v_mad_u64_u32 v[32:33], null, s15, v24, s[10:11]
	v_dual_sub_f32 v30, v31, v30 :: v_dual_sub_f32 v31, 1.0, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v30, v29, v30
	v_ashrrev_i32_e32 v33, 31, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[32:33], 2, v[32:33]
	v_add_co_u32 v32, vcc_lo, s8, v32
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v33, vcc_lo, s9, v33, vcc_lo
	global_load_b32 v28, v[32:33], off
	s_waitcnt vmcnt(0)
	v_dual_fmac_f32 v9, v30, v28 :: v_dual_mul_f32 v28, v29, v31
                                        ; implicit-def: $vgpr30
                                        ; implicit-def: $vgpr29
	global_store_b32 v[2:3], v9, off
.LBB0_134:                              ; %Flow2367
                                        ;   in Loop: Header=BB0_119 Depth=1
	s_and_not1_saveexec_b32 s2, s2
; %bb.135:                              ;   in Loop: Header=BB0_119 Depth=1
	v_sub_f32_e32 v28, 1.0, v30
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v28, v28, v29
; %bb.136:                              ; %Flow2368
                                        ;   in Loop: Header=BB0_119 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	v_mov_b32_e32 v29, v27
	s_or_b32 s21, s21, exec_lo
.LBB0_137:                              ; %Flow2374
                                        ;   in Loop: Header=BB0_119 Depth=1
	s_or_b32 exec_lo, exec_lo, s20
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s4, s21, exec_lo
.LBB0_138:                              ; %Flow2370
                                        ;   in Loop: Header=BB0_119 Depth=1
	s_and_not1_saveexec_b32 s19, s19
	s_cbranch_execz .LBB0_142
; %bb.139:                              ;   in Loop: Header=BB0_119 Depth=1
	v_cmp_lt_i32_e32 vcc_lo, -1, v24
	v_cmp_gt_i32_e64 s2, s30, v24
                                        ; implicit-def: $vgpr28
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s3, vcc_lo, s2
	s_mov_b32 s2, s4
	s_and_saveexec_b32 s20, s3
	s_cbranch_execz .LBB0_141
; %bb.140:                              ;   in Loop: Header=BB0_119 Depth=1
	v_sub_f32_e32 v28, v23, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v29, v28, v28, 1.0
	v_mul_f32_e32 v29, v20, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v30, null, v14, v14, v29
	v_div_scale_f32 v33, vcc_lo, v29, v14, v29
	v_rcp_f32_e32 v31, v30
	s_waitcnt_depctr 0xfff
	v_fma_f32 v32, -v30, v31, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v31, v32, v31
	v_mul_f32_e32 v32, v33, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v34, -v30, v32, v33
	v_fmac_f32_e32 v32, v34, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v30, -v30, v32, v33
	v_div_fmas_f32 v30, v30, v31, v32
	v_div_scale_f32 v34, vcc_lo, -v22, v28, -v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v29, v30, v14, v29
	v_div_scale_f32 v30, null, v28, v28, -v22
	v_mul_f32_e32 v31, 0x4f800000, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v32, v30
	v_cmp_gt_f32_e64 s2, 0xf800000, v29
	v_cndmask_b32_e64 v29, v29, v31, s2
	s_waitcnt_depctr 0xfff
	v_fma_f32 v33, -v30, v32, 1.0
	v_sqrt_f32_e32 v31, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v32, v33, v32
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v35, v34, v32 :: v_dual_add_nc_u32 v36, 1, v31
	v_fma_f32 v38, -v30, v35, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v39, -v36, v31, v29
	v_fmac_f32_e32 v35, v38, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v30, -v30, v35, v34
	v_div_fmas_f32 v30, v30, v32, v35
	v_cmp_class_f32_e64 vcc_lo, v29, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v28, v30, v28, -v22
	v_dual_sub_f32 v28, 1.0, v28 :: v_dual_add_nc_u32 v33, -1, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v37, -v33, v31, v29
	v_cmp_ge_f32_e64 s3, 0, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v31, v31, v33, s3
	v_cmp_lt_f32_e64 s3, 0, v39
	v_cndmask_b32_e64 v31, v31, v36, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v33, 0x37800000, v31
	v_cndmask_b32_e64 v31, v31, v33, s2
	s_or_b32 s2, s4, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v29, v31, v29, vcc_lo
	v_mul_f32_e32 v28, v28, v29
.LBB0_141:                              ; %Flow2376
                                        ;   in Loop: Header=BB0_119 Depth=1
	s_or_b32 exec_lo, exec_lo, s20
	v_mov_b32_e32 v29, v24
	s_and_not1_b32 s3, s4, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s4, s3, s2
.LBB0_142:                              ; %Flow2375
                                        ;   in Loop: Header=BB0_119 Depth=1
	s_or_b32 exec_lo, exec_lo, s19
	s_and_saveexec_b32 s2, s4
	s_cbranch_execz .LBB0_144
; %bb.143:                              ; %.sink.split2161
                                        ;   in Loop: Header=BB0_119 Depth=1
	v_mul_lo_u32 v29, s15, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v30, 31, v29
	v_add_co_u32 v29, vcc_lo, s10, v29
	v_add_co_ci_u32_e32 v30, vcc_lo, s11, v30, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[29:30], 2, v[29:30]
	v_add_co_u32 v29, vcc_lo, s8, v29
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v30, vcc_lo, s9, v30, vcc_lo
	global_load_b32 v29, v[29:30], off
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v9, v28, v29
	global_store_b32 v[2:3], v9, off
.LBB0_144:                              ; %Flow2377
                                        ;   in Loop: Header=BB0_119 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
.LBB0_145:                              ;   in Loop: Header=BB0_119 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s18
	s_mov_b32 s2, 0
	s_mov_b32 s18, exec_lo
	v_cmpx_eq_u32_e64 s29, v5
	s_cbranch_execz .LBB0_171
; %bb.146:                              ;   in Loop: Header=BB0_119 Depth=1
	s_mov_b32 s4, 0
	s_mov_b32 s2, exec_lo
	v_cmpx_ne_u32_e64 v27, v24
	s_xor_b32 s19, exec_lo, s2
	s_cbranch_execz .LBB0_166
; %bb.147:                              ;   in Loop: Header=BB0_119 Depth=1
	v_cmp_gt_i32_e32 vcc_lo, 1, v27
	v_cmp_le_i32_e64 s2, s30, v27
	s_mov_b32 s21, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s20, exec_lo, s3
	s_cbranch_execz .LBB0_159
; %bb.148:                              ;   in Loop: Header=BB0_119 Depth=1
	s_mov_b32 s3, exec_lo
	v_cmpx_eq_u32_e32 0, v27
	s_cbranch_execz .LBB0_152
; %bb.149:                              ;   in Loop: Header=BB0_119 Depth=1
	v_sub_f32_e32 v5, v23, v22
	v_dual_sub_f32 v28, v19, v22 :: v_dual_sub_f32 v29, v26, v25
	s_mov_b32 s4, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f32 v30, null, v5, v5, v28
	v_div_scale_f32 v31, null, v29, v29, -v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v32, v30
	v_rcp_f32_e32 v33, v31
	s_waitcnt_depctr 0xfff
	v_fma_f32 v34, -v30, v32, 1.0
	v_fma_f32 v35, -v31, v33, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v32, v34, v32
	v_div_scale_f32 v36, vcc_lo, v28, v5, v28
	v_div_scale_f32 v34, s2, -v25, v29, -v25
	v_fmac_f32_e32 v33, v35, v33
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v35, v36, v32
	v_mul_f32_e32 v37, v34, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v38, -v30, v35, v36
	v_fma_f32 v39, -v31, v37, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v35, v38, v32
	v_fmac_f32_e32 v37, v39, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v30, -v30, v35, v36
	v_fma_f32 v31, -v31, v37, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v30, v30, v32, v35
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f32 v31, v31, v33, v37
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v28, v30, v5, v28
	v_div_fixup_f32 v29, v31, v29, -v25
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_f32_e32 v28, v29
	s_cbranch_execz .LBB0_151
; %bb.150:                              ;   in Loop: Header=BB0_119 Depth=1
	v_mad_u64_u32 v[30:31], null, v4, s28, s[10:11]
	v_fma_f32 v5, v5, v5, 1.0
	v_sub_f32_e32 v28, v28, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v5, v20, v5
	v_ashrrev_i32_e32 v31, 31, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[30:31], 2, v[30:31]
	v_add_co_u32 v30, vcc_lo, s8, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v31, vcc_lo, s9, v31, vcc_lo
	global_load_b32 v30, v[30:31], off
	v_div_scale_f32 v31, null, v14, v14, v5
	v_rcp_f32_e32 v32, v31
	s_waitcnt_depctr 0xfff
	v_fma_f32 v33, -v31, v32, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v32, v33, v32
	v_div_scale_f32 v33, vcc_lo, v5, v14, v5
	v_mul_f32_e32 v34, v33, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v35, -v31, v34, v33
	v_fmac_f32_e32 v34, v35, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v31, -v31, v34, v33
	v_div_fmas_f32 v31, v31, v32, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v5, v31, v14, v5
	v_mul_f32_e32 v31, 0x4f800000, v5
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v5, v5, v31, vcc_lo
	v_sqrt_f32_e32 v31, v5
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v32, -1, v31
	v_add_nc_u32_e32 v33, 1, v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v34, -v32, v31, v5
	v_fma_f32 v35, -v33, v31, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s2, 0, v34
	v_cndmask_b32_e64 v31, v31, v32, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s2, 0, v35
	v_cndmask_b32_e64 v31, v31, v33, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v32, 0x37800000, v31
	v_cndmask_b32_e32 v31, v31, v32, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v5, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v5, v31, v5, vcc_lo
	v_mul_f32_e32 v5, v5, v28
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v9, v5, v30
	global_store_b32 v[2:3], v9, off
.LBB0_151:                              ; %Flow2364
                                        ;   in Loop: Header=BB0_119 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_152:                              ;   in Loop: Header=BB0_119 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_mov_b32 s2, 0
	s_mov_b32 s3, exec_lo
	v_cmpx_eq_u32_e64 s30, v27
	s_xor_b32 s21, exec_lo, s3
	s_cbranch_execz .LBB0_158
; %bb.153:                              ;   in Loop: Header=BB0_119 Depth=1
	v_mad_u64_u32 v[27:28], null, v24, s29, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v27, s28, s[10:11]
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v4, vcc_lo, s8, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	v_sub_f32_e32 v5, v23, v22
	v_sub_f32_e32 v22, v19, v22
	v_fma_f32 v23, v5, v5, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v23, v20, v23
	v_div_scale_f32 v24, null, v14, v14, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v27, v24
	s_waitcnt_depctr 0xfff
	v_fma_f32 v28, -v24, v27, 1.0
	v_fmac_f32_e32 v27, v28, v27
	v_div_scale_f32 v28, vcc_lo, v23, v14, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v29, v28, v27
	v_fma_f32 v30, -v24, v29, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v29, v30, v27
	v_fma_f32 v24, -v24, v29, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v24, v24, v27, v29
	v_div_fixup_f32 v23, v24, v14, v23
	v_sub_f32_e32 v24, v16, v25
	v_sub_f32_e32 v25, v26, v25
	v_div_scale_f32 v27, null, v5, v5, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v26, 0x4f800000, v23
	v_cmp_gt_f32_e64 s2, 0xf800000, v23
	v_div_scale_f32 v28, null, v25, v25, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v26, v23, v26, s2
	v_rcp_f32_e32 v23, v27
	v_rcp_f32_e32 v29, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_3)
	v_sqrt_f32_e32 v30, v26
	v_fma_f32 v31, -v27, v23, 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v32, -v28, v29, 1.0
	v_add_nc_u32_e32 v33, -1, v30
	v_fmac_f32_e32 v23, v31, v23
	v_div_scale_f32 v31, vcc_lo, v22, v5, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v29, v32, v29
	v_div_scale_f32 v32, s3, v24, v25, v24
	v_add_nc_u32_e32 v34, 1, v30
	v_fma_f32 v36, -v33, v30, v26
	v_mul_f32_e32 v35, v31, v23
	v_mul_f32_e32 v37, v32, v29
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v38, -v34, v30, v26
	v_cmp_ge_f32_e64 s4, 0, v36
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v39, -v27, v35, v31
	v_cndmask_b32_e64 v30, v30, v33, s4
	v_fma_f32 v33, -v28, v37, v32
	v_cmp_lt_f32_e64 s4, 0, v38
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v35, v39, v23
	v_fmac_f32_e32 v37, v33, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v30, v30, v34, s4
	v_fma_f32 v27, -v27, v35, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v28, -v28, v37, v32
	v_mul_f32_e32 v31, 0x37800000, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v23, v27, v23, v35
	s_mov_b32 vcc_lo, s3
	v_div_fmas_f32 v27, v28, v29, v37
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e64 v28, v30, v31, s2
	v_cmp_class_f32_e64 vcc_lo, v26, 0x260
	v_div_fixup_f32 v23, v23, v5, v22
	s_mov_b32 s2, exec_lo
	v_div_fixup_f32 v22, v27, v25, v24
	v_cndmask_b32_e32 v5, v28, v26, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_ngt_f32_e32 v23, v22
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB0_155
; %bb.154:                              ;   in Loop: Header=BB0_119 Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v23, v5
                                        ; implicit-def: $vgpr22
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v9, v5, v4
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr4
.LBB0_155:                              ; %Flow2362
                                        ;   in Loop: Header=BB0_119 Depth=1
	s_and_not1_saveexec_b32 s2, s2
	s_cbranch_execz .LBB0_157
; %bb.156:                              ;   in Loop: Header=BB0_119 Depth=1
	v_mul_f32_e32 v5, v5, v22
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v9, v5, v4
.LBB0_157:                              ; %Flow2363
                                        ;   in Loop: Header=BB0_119 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
.LBB0_158:                              ; %Flow2392
                                        ;   in Loop: Header=BB0_119 Depth=1
	s_or_b32 exec_lo, exec_lo, s21
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s21, s2, exec_lo
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr27
                                        ; implicit-def: $vgpr23
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr25
                                        ; implicit-def: $vgpr26
                                        ; implicit-def: $vgpr24
.LBB0_159:                              ; %Flow2391
                                        ;   in Loop: Header=BB0_119 Depth=1
	s_and_not1_saveexec_b32 s20, s20
	s_cbranch_execz .LBB0_165
; %bb.160:                              ;   in Loop: Header=BB0_119 Depth=1
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[28:29], null, v24, s29, v[4:5]
	v_sub_f32_e32 v23, v23, v22
	v_sub_f32_e32 v22, v19, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v24, v23, v23, 1.0
	v_mad_u64_u32 v[29:30], null, v28, s28, s[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v24, v20, v24
	v_ashrrev_i32_e32 v30, 31, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[28:29], 2, v[29:30]
	v_add_co_u32 v28, vcc_lo, s8, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v29, vcc_lo, s9, v29, vcc_lo
	global_load_b32 v5, v[28:29], off
	v_div_scale_f32 v28, null, v14, v14, v24
	v_rcp_f32_e32 v29, v28
	s_waitcnt_depctr 0xfff
	v_fma_f32 v30, -v28, v29, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v29, v30, v29
	v_div_scale_f32 v30, vcc_lo, v24, v14, v24
	v_mul_f32_e32 v31, v30, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v32, -v28, v31, v30
	v_fmac_f32_e32 v31, v32, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v28, -v28, v31, v30
	v_div_fmas_f32 v28, v28, v29, v31
	v_cvt_f32_i32_e32 v29, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v24, v28, v14, v24
	v_sub_f32_e32 v28, v29, v25
	v_sub_f32_e32 v25, v26, v25
	v_div_scale_f32 v29, null, v23, v23, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v26, 0x4f800000, v24
	v_cmp_gt_f32_e64 s2, 0xf800000, v24
	v_cndmask_b32_e64 v26, v24, v26, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v24, v29
	v_sqrt_f32_e32 v32, v26
	s_waitcnt_depctr 0xfff
	v_fma_f32 v33, -v29, v24, 1.0
	v_add_nc_u32_e32 v36, 1, v32
	v_add_nc_u32_e32 v35, -1, v32
	v_div_scale_f32 v30, null, v25, v25, v28
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v24, v33, v24
	v_div_scale_f32 v33, vcc_lo, v22, v23, v22
	v_rcp_f32_e32 v31, v30
	v_fma_f32 v38, -v35, v32, v26
	v_fma_f32 v40, -v36, v32, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v37, v33, v24
	v_cmp_ge_f32_e64 s4, 0, v38
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f32 v41, -v29, v37, v33
	s_waitcnt_depctr 0xfff
	v_fma_f32 v34, -v30, v31, 1.0
	v_cndmask_b32_e64 v32, v32, v35, s4
	v_cmp_lt_f32_e64 s4, 0, v40
	v_fmac_f32_e32 v37, v41, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v31, v34, v31
	v_div_scale_f32 v34, s3, v28, v25, v28
	v_cndmask_b32_e64 v32, v32, v36, s4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v29, -v29, v37, v33
	v_mul_f32_e32 v39, v34, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v33, 0x37800000, v32
	v_div_fmas_f32 v24, v29, v24, v37
	s_mov_b32 vcc_lo, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v35, -v30, v39, v34
	v_div_fixup_f32 v24, v24, v23, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v39, v35, v31
	v_fma_f32 v30, -v30, v39, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v29, v30, v31, v39
	v_cndmask_b32_e64 v30, v32, v33, s2
	v_cmp_class_f32_e64 vcc_lo, v26, 0x260
	s_mov_b32 s2, exec_lo
	v_div_fixup_f32 v23, v29, v25, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v22, v30, v26, vcc_lo
	v_cmpx_ngt_f32_e32 v24, v23
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB0_162
; %bb.161:                              ;   in Loop: Header=BB0_119 Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v4, v24, v22
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr23
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr27
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v9, v4, v5
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr4
.LBB0_162:                              ; %Flow2365
                                        ;   in Loop: Header=BB0_119 Depth=1
	s_and_not1_saveexec_b32 s2, s2
	s_cbranch_execz .LBB0_164
; %bb.163:                              ;   in Loop: Header=BB0_119 Depth=1
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[25:26], null, v27, s29, v[4:5]
	v_mul_f32_e32 v4, v22, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v9, v4, v5
	v_mad_u64_u32 v[26:27], null, v25, s28, s[10:11]
	global_store_b32 v[2:3], v9, off
	v_ashrrev_i32_e32 v27, 31, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[25:26], 2, v[26:27]
	v_add_co_u32 v4, vcc_lo, s8, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v26, vcc_lo
	global_load_b32 v4, v[4:5], off
	v_sub_f32_e32 v5, v24, v23
	v_mul_f32_e32 v5, v22, v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v9, v5, v4
.LBB0_164:                              ; %Flow2366
                                        ;   in Loop: Header=BB0_119 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s21, s21, exec_lo
.LBB0_165:                              ; %Flow2393
                                        ;   in Loop: Header=BB0_119 Depth=1
	s_or_b32 exec_lo, exec_lo, s20
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s4, s21, exec_lo
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr4
.LBB0_166:                              ; %Flow2390
                                        ;   in Loop: Header=BB0_119 Depth=1
	s_and_not1_saveexec_b32 s19, s19
	s_cbranch_execz .LBB0_170
; %bb.167:                              ;   in Loop: Header=BB0_119 Depth=1
	v_cmp_lt_i32_e32 vcc_lo, -1, v24
	v_cmp_gt_i32_e64 s2, s30, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s2
	s_mov_b32 s2, s4
	s_and_saveexec_b32 s20, s3
	s_xor_b32 s20, exec_lo, s20
	s_cbranch_execz .LBB0_169
; %bb.168:                              ;   in Loop: Header=BB0_119 Depth=1
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[25:26], null, v24, s29, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v25, s28, s[10:11]
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v4, vcc_lo, s8, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	v_sub_f32_e32 v5, v23, v22
	v_sub_f32_e32 v22, v19, v22
	v_fma_f32 v23, v5, v5, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v23, v20, v23
	v_div_scale_f32 v24, null, v14, v14, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v25, v24
	s_waitcnt_depctr 0xfff
	v_fma_f32 v26, -v24, v25, 1.0
	v_fmac_f32_e32 v25, v26, v25
	v_div_scale_f32 v26, vcc_lo, v23, v14, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v27, v26, v25
	v_fma_f32 v28, -v24, v27, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v27, v28, v25
	v_fma_f32 v24, -v24, v27, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v24, v24, v25, v27
	v_div_fixup_f32 v23, v24, v14, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v24, 0x4f800000, v23
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v23
	v_div_scale_f32 v25, null, v5, v5, v22
	v_cndmask_b32_e32 v23, v23, v24, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v24, v25
	v_sqrt_f32_e32 v26, v23
	s_waitcnt_depctr 0xfff
	v_fma_f32 v27, -v25, v24, 1.0
	v_add_nc_u32_e32 v28, -1, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v24, v27, v24 :: v_dual_add_nc_u32 v29, 1, v26
	v_div_scale_f32 v27, s2, v22, v5, v22
	v_fma_f32 v30, -v28, v26, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v31, -v29, v26, v23
	v_mul_f32_e32 v32, v27, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s3, 0, v30
	v_cndmask_b32_e64 v26, v26, v28, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_lt_f32_e64 s3, 0, v31
	v_fma_f32 v28, -v25, v32, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v26, v26, v29, s3
	v_fmac_f32_e32 v32, v28, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v28, 0x37800000, v26
	v_fma_f32 v25, -v25, v32, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v26, v26, v28, vcc_lo
	s_mov_b32 vcc_lo, s2
	s_or_b32 s2, s4, exec_lo
	v_div_fmas_f32 v24, v25, v24, v32
	v_cmp_class_f32_e64 vcc_lo, v23, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v5, v24, v5, v22
	v_cndmask_b32_e32 v23, v26, v23, vcc_lo
	v_mul_f32_e32 v5, v5, v23
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v9, v5, v4
.LBB0_169:                              ; %Flow2395
                                        ;   in Loop: Header=BB0_119 Depth=1
	s_or_b32 exec_lo, exec_lo, s20
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s3, s4, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_or_b32 s4, s3, s2
.LBB0_170:                              ; %Flow2394
                                        ;   in Loop: Header=BB0_119 Depth=1
	s_or_b32 exec_lo, exec_lo, s19
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s2, s4, exec_lo
.LBB0_171:                              ; %Flow2389
                                        ;   in Loop: Header=BB0_119 Depth=1
	s_or_b32 exec_lo, exec_lo, s18
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s18, s2, exec_lo
                                        ; implicit-def: $vgpr23
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr26
                                        ; implicit-def: $vgpr25
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr27
.LBB0_172:                              ; %Flow2388
                                        ;   in Loop: Header=BB0_119 Depth=1
	s_and_not1_saveexec_b32 s17, s17
	s_cbranch_execz .LBB0_200
; %bb.173:                              ;   in Loop: Header=BB0_119 Depth=1
	s_mov_b32 s4, s18
	s_mov_b32 s2, exec_lo
	v_cmpx_ne_u32_e64 v27, v24
	s_xor_b32 s19, exec_lo, s2
	s_cbranch_execz .LBB0_195
; %bb.174:                              ;   in Loop: Header=BB0_119 Depth=1
	v_cmp_gt_i32_e32 vcc_lo, 1, v27
	v_cmp_le_i32_e64 s2, s30, v27
	s_mov_b32 s21, s18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s20, exec_lo, s3
	s_cbranch_execz .LBB0_188
; %bb.175:                              ;   in Loop: Header=BB0_119 Depth=1
	s_mov_b32 s21, exec_lo
	v_cmpx_eq_u32_e32 0, v27
	s_cbranch_execz .LBB0_181
; %bb.176:                              ;   in Loop: Header=BB0_119 Depth=1
	v_sub_f32_e32 v28, v23, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v29, v28, v28, 1.0
	v_mul_f32_e32 v29, v20, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v30, null, v14, v14, v29
	v_div_scale_f32 v33, vcc_lo, v29, v14, v29
	v_rcp_f32_e32 v31, v30
	s_waitcnt_depctr 0xfff
	v_fma_f32 v32, -v30, v31, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v31, v32, v31
	v_mul_f32_e32 v32, v33, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v34, -v30, v32, v33
	v_fmac_f32_e32 v32, v34, v31
	s_waitcnt vmcnt(0)
	v_cvt_f32_i32_e32 v34, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v30, -v30, v32, v33
	v_sub_f32_e32 v33, v34, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v30, v30, v31, v32
	v_sub_f32_e32 v31, v26, v25
	v_div_scale_f32 v32, null, v28, v28, v33
	v_div_scale_f32 v38, vcc_lo, v33, v28, v33
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_fixup_f32 v29, v30, v14, v29
	v_div_scale_f32 v30, null, v31, v31, -v25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v34, v32
	v_mul_f32_e32 v35, 0x4f800000, v29
	v_cmp_gt_f32_e64 s2, 0xf800000, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v36, v30
	v_cndmask_b32_e64 v35, v29, v35, s2
	s_waitcnt_depctr 0xfff
	v_fma_f32 v29, -v32, v34, 1.0
	v_sqrt_f32_e32 v37, v35
	v_fma_f32 v39, -v30, v36, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v34, v29, v34
	v_dual_fmac_f32 v36, v39, v36 :: v_dual_mul_f32 v39, v38, v34
	v_div_scale_f32 v29, s3, -v25, v31, -v25
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v40, -1, v37
	v_add_nc_u32_e32 v43, 1, v37
	v_fma_f32 v42, -v32, v39, v38
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v44, -v40, v37, v35
	v_fmac_f32_e32 v39, v42, v34
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v42, -v43, v37, v35
	v_cmp_ge_f32_e64 s4, 0, v44
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v32, -v32, v39, v38
	v_cndmask_b32_e64 v37, v37, v40, s4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s4, 0, v42
	v_cndmask_b32_e64 v37, v37, v43, s4
	v_mul_f32_e32 v41, v29, v36
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v45, -v30, v41, v29
	v_fmac_f32_e32 v41, v45, v36
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_fma_f32 v29, -v30, v41, v29
	v_div_fmas_f32 v30, v32, v34, v39
	v_mul_f32_e32 v32, 0x37800000, v37
	s_mov_b32 vcc_lo, s3
	v_div_fmas_f32 v34, v29, v36, v41
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v29, v30, v28, v33
	v_cndmask_b32_e64 v28, v37, v32, s2
	v_cmp_class_f32_e64 vcc_lo, v35, 0x260
	s_mov_b32 s2, exec_lo
	v_div_fixup_f32 v31, v34, v31, -v25
                                        ; implicit-def: $vgpr30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v28, v28, v35, vcc_lo
	v_cmpx_ngt_f32_e32 v29, v31
	s_xor_b32 s2, exec_lo, s2
; %bb.177:                              ;   in Loop: Header=BB0_119 Depth=1
	v_sub_f32_e32 v30, 1.0, v31
                                        ; implicit-def: $vgpr29
                                        ; implicit-def: $vgpr31
; %bb.178:                              ; %Flow2380
                                        ;   in Loop: Header=BB0_119 Depth=1
	s_and_not1_saveexec_b32 s2, s2
	s_cbranch_execz .LBB0_180
; %bb.179:                              ;   in Loop: Header=BB0_119 Depth=1
	v_mad_u64_u32 v[32:33], null, v4, s28, s[10:11]
	v_sub_f32_e32 v31, v29, v31
	v_sub_f32_e32 v29, 1.0, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v31, v28, v31
	v_ashrrev_i32_e32 v33, 31, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[32:33], 2, v[32:33]
	v_add_co_u32 v32, vcc_lo, s8, v32
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v33, vcc_lo, s9, v33, vcc_lo
	global_load_b32 v30, v[32:33], off
	s_waitcnt vmcnt(0)
	v_dual_fmac_f32 v9, v31, v30 :: v_dual_mov_b32 v30, v28
	v_mov_b32_e32 v28, v29
	global_store_b32 v[2:3], v9, off
.LBB0_180:                              ; %.sink.split
                                        ;   in Loop: Header=BB0_119 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	v_mad_u64_u32 v[31:32], null, v5, s28, s[10:11]
	v_mul_f32_e32 v28, v28, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v32, 31, v31
	v_lshlrev_b64 v[31:32], 2, v[31:32]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v31, vcc_lo, s8, v31
	v_add_co_ci_u32_e32 v32, vcc_lo, s9, v32, vcc_lo
	global_load_b32 v29, v[31:32], off
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v9, v28, v29
	global_store_b32 v[2:3], v9, off
.LBB0_181:                              ; %Flow2381
                                        ;   in Loop: Header=BB0_119 Depth=1
	s_or_b32 exec_lo, exec_lo, s21
	s_mov_b32 s2, s18
	s_mov_b32 s3, exec_lo
	v_cmpx_eq_u32_e64 s30, v27
	s_xor_b32 s21, exec_lo, s3
	s_cbranch_execz .LBB0_187
; %bb.182:                              ;   in Loop: Header=BB0_119 Depth=1
	v_mul_lo_u32 v24, v24, s29
	v_dual_sub_f32 v26, v26, v25 :: v_dual_sub_f32 v23, v23, v22
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, v24, v4
	v_mad_u64_u32 v[27:28], null, v4, s28, s[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v28, 31, v27
	v_lshlrev_b64 v[27:28], 2, v[27:28]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v27, vcc_lo, s8, v27
	v_add_co_ci_u32_e32 v28, vcc_lo, s9, v28, vcc_lo
	global_load_b32 v4, v[27:28], off
	v_fma_f32 v27, v23, v23, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v27, v20, v27
	v_div_scale_f32 v28, null, v14, v14, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v29, v28
	s_waitcnt_depctr 0xfff
	v_fma_f32 v30, -v28, v29, 1.0
	v_fmac_f32_e32 v29, v30, v29
	v_div_scale_f32 v30, vcc_lo, v27, v14, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v31, v30, v29
	v_fma_f32 v32, -v28, v31, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v31, v32, v29
	v_fma_f32 v28, -v28, v31, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v28, v28, v29, v31
	v_cvt_f32_i32_e32 v29, v5
	v_sub_f32_e32 v22, v29, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v27, v28, v14, v27
	v_sub_f32_e32 v28, v16, v25
	v_div_scale_f32 v29, null, v23, v23, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v25, 0x4f800000, v27
	v_cmp_gt_f32_e64 s2, 0xf800000, v27
	v_cndmask_b32_e64 v27, v27, v25, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v25, v29
	v_sqrt_f32_e32 v32, v27
	s_waitcnt_depctr 0xfff
	v_fma_f32 v33, -v29, v25, 1.0
	v_add_nc_u32_e32 v35, -1, v32
	v_div_scale_f32 v30, null, v26, v26, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v25, v33, v25
	v_div_scale_f32 v33, vcc_lo, v22, v23, v22
	v_rcp_f32_e32 v31, v30
	v_add_nc_u32_e32 v36, 1, v32
	v_fma_f32 v38, -v35, v32, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v37, v33, v25
	v_fma_f32 v40, -v36, v32, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_ge_f32_e64 s4, 0, v38
	v_fma_f32 v41, -v29, v37, v33
	s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v34, -v30, v31, 1.0
	v_cndmask_b32_e64 v32, v32, v35, s4
	v_cmp_lt_f32_e64 s4, 0, v40
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v37, v41, v25
	v_fmac_f32_e32 v31, v34, v31
	v_div_scale_f32 v34, s3, v28, v26, v28
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v32, v32, v36, s4
	v_fma_f32 v29, -v29, v37, v33
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v39, v34, v31
	v_mul_f32_e32 v33, 0x37800000, v32
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v25, v29, v25, v37
	s_mov_b32 vcc_lo, s3
	v_fma_f32 v35, -v30, v39, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v25, v25, v23, v22
	v_fmac_f32_e32 v39, v35, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v30, -v30, v39, v34
	v_div_fmas_f32 v29, v30, v31, v39
	v_cndmask_b32_e64 v30, v32, v33, s2
	v_cmp_class_f32_e64 vcc_lo, v27, 0x260
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v23, v29, v26, v28
	v_cndmask_b32_e32 v22, v30, v27, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_ngt_f32_e32 v25, v23
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB0_184
; %bb.183:                              ;   in Loop: Header=BB0_119 Depth=1
	v_add_nc_u32_e32 v5, v24, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[26:27], null, v5, s28, s[10:11]
	v_mul_f32_e32 v5, v25, v22
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v9, v5, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v27, 31, v26
	global_store_b32 v[2:3], v9, off
	v_lshlrev_b64 v[26:27], 2, v[26:27]
	v_add_co_u32 v4, vcc_lo, s8, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v27, vcc_lo
	global_load_b32 v4, v[4:5], off
	v_sub_f32_e32 v5, v23, v25
                                        ; implicit-def: $vgpr23
	v_mul_f32_e32 v5, v22, v5
                                        ; implicit-def: $vgpr22
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v9, v5, v4
                                        ; implicit-def: $vgpr4
.LBB0_184:                              ; %Flow2378
                                        ;   in Loop: Header=BB0_119 Depth=1
	s_and_not1_saveexec_b32 s2, s2
	s_cbranch_execz .LBB0_186
; %bb.185:                              ;   in Loop: Header=BB0_119 Depth=1
	v_mul_f32_e32 v5, v22, v23
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v9, v5, v4
.LBB0_186:                              ; %Flow2379
                                        ;   in Loop: Header=BB0_119 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s2, s18, exec_lo
.LBB0_187:                              ; %Flow2399
                                        ;   in Loop: Header=BB0_119 Depth=1
	s_or_b32 exec_lo, exec_lo, s21
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s3, s18, exec_lo
	s_and_b32 s2, s2, exec_lo
                                        ; implicit-def: $vgpr23
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr26
                                        ; implicit-def: $vgpr25
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr27
	s_or_b32 s21, s3, s2
.LBB0_188:                              ; %Flow2398
                                        ;   in Loop: Header=BB0_119 Depth=1
	s_and_not1_saveexec_b32 s20, s20
	s_cbranch_execz .LBB0_194
; %bb.189:                              ;   in Loop: Header=BB0_119 Depth=1
	v_mul_lo_u32 v28, v24, s29
	v_dual_sub_f32 v23, v23, v22 :: v_dual_sub_f32 v26, v26, v25
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v24, v28, v4
	v_mad_u64_u32 v[29:30], null, v24, s28, s[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v30, 31, v29
	v_lshlrev_b64 v[29:30], 2, v[29:30]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v29, vcc_lo, s8, v29
	v_add_co_ci_u32_e32 v30, vcc_lo, s9, v30, vcc_lo
	global_load_b32 v24, v[29:30], off
	v_fma_f32 v29, v23, v23, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v29, v20, v29
	v_div_scale_f32 v30, null, v14, v14, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v31, v30
	s_waitcnt_depctr 0xfff
	v_fma_f32 v32, -v30, v31, 1.0
	v_fmac_f32_e32 v31, v32, v31
	v_div_scale_f32 v32, vcc_lo, v29, v14, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v33, v32, v31
	v_fma_f32 v34, -v30, v33, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v33, v34, v31
	v_fma_f32 v30, -v30, v33, v32
	v_cvt_f32_i32_e32 v32, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v30, v30, v31, v33
	v_cvt_f32_i32_e32 v31, v5
	v_sub_f32_e32 v22, v31, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v29, v30, v14, v29
	v_sub_f32_e32 v30, v32, v25
	v_div_scale_f32 v31, null, v23, v23, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v25, 0x4f800000, v29
	v_cmp_gt_f32_e64 s2, 0xf800000, v29
	v_div_scale_f32 v32, null, v26, v26, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v29, v29, v25, s2
	v_rcp_f32_e32 v25, v31
	v_rcp_f32_e32 v33, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_3)
	v_sqrt_f32_e32 v34, v29
	v_fma_f32 v35, -v31, v25, 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v36, -v32, v33, 1.0
	v_add_nc_u32_e32 v37, -1, v34
	v_fmac_f32_e32 v25, v35, v25
	v_div_scale_f32 v35, vcc_lo, v22, v23, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v33, v36, v33
	v_div_scale_f32 v36, s3, v30, v26, v30
	v_add_nc_u32_e32 v38, 1, v34
	v_fma_f32 v40, -v37, v34, v29
	v_mul_f32_e32 v39, v35, v25
	v_mul_f32_e32 v41, v36, v33
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v42, -v38, v34, v29
	v_cmp_ge_f32_e64 s4, 0, v40
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v43, -v31, v39, v35
	v_cndmask_b32_e64 v34, v34, v37, s4
	v_fma_f32 v37, -v32, v41, v36
	v_cmp_lt_f32_e64 s4, 0, v42
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v39, v43, v25
	v_fmac_f32_e32 v41, v37, v33
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v34, v34, v38, s4
	v_fma_f32 v31, -v31, v39, v35
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v32, -v32, v41, v36
	v_mul_f32_e32 v35, 0x37800000, v34
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v25, v31, v25, v39
	s_mov_b32 vcc_lo, s3
	v_div_fmas_f32 v31, v32, v33, v41
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e64 v32, v34, v35, s2
	v_cmp_class_f32_e64 vcc_lo, v29, 0x260
	v_div_fixup_f32 v25, v25, v23, v22
	s_mov_b32 s2, exec_lo
	v_div_fixup_f32 v23, v31, v26, v30
	v_cndmask_b32_e32 v22, v32, v29, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_ngt_f32_e32 v25, v23
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB0_191
; %bb.190:                              ;   in Loop: Header=BB0_119 Depth=1
	v_add_nc_u32_e32 v4, v28, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[28:29], null, v4, s28, s[10:11]
	v_dual_mul_f32 v4, v25, v22 :: v_dual_sub_f32 v25, v23, v25
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v9, v4, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v29, 31, v28
	v_mul_f32_e32 v25, v22, v25
	global_store_b32 v[2:3], v9, off
	v_lshlrev_b64 v[28:29], 2, v[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v28, vcc_lo, s8, v28
	v_add_co_ci_u32_e32 v29, vcc_lo, s9, v29, vcc_lo
	global_load_b32 v24, v[28:29], off
	v_mad_u64_u32 v[28:29], null, v27, s29, v[5:6]
                                        ; implicit-def: $vgpr27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v28, s28, s[10:11]
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v4, vcc_lo, s8, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v9, v25, v24
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr25
	global_store_b32 v[2:3], v9, off
	global_load_b32 v4, v[4:5], off
	v_sub_f32_e32 v5, 1.0, v23
                                        ; implicit-def: $vgpr23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v22, v5
                                        ; implicit-def: $vgpr22
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v9, v5, v4
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr5
.LBB0_191:                              ; %Flow2382
                                        ;   in Loop: Header=BB0_119 Depth=1
	s_and_not1_saveexec_b32 s2, s2
	s_cbranch_execz .LBB0_193
; %bb.192:                              ;   in Loop: Header=BB0_119 Depth=1
	v_mul_lo_u32 v28, v27, s29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, v28, v4
	v_mad_u64_u32 v[26:27], null, v4, s28, s[10:11]
	v_mul_f32_e32 v4, v22, v23
	v_sub_f32_e32 v23, v25, v23
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v9, v4, v24
	v_ashrrev_i32_e32 v27, 31, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v23, v22, v23
	global_store_b32 v[2:3], v9, off
	v_lshlrev_b64 v[26:27], 2, v[26:27]
	v_add_co_u32 v26, vcc_lo, s8, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v27, vcc_lo, s9, v27, vcc_lo
	global_load_b32 v24, v[26:27], off
	v_add_nc_u32_e32 v26, v28, v5
	v_mad_u64_u32 v[4:5], null, v26, s28, s[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s8, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v9, v23, v24
	global_store_b32 v[2:3], v9, off
	global_load_b32 v4, v[4:5], off
	v_sub_f32_e32 v5, 1.0, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v5, v22
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v9, v5, v4
.LBB0_193:                              ; %Flow2383
                                        ;   in Loop: Header=BB0_119 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s21, s21, exec_lo
.LBB0_194:                              ; %Flow2400
                                        ;   in Loop: Header=BB0_119 Depth=1
	s_or_b32 exec_lo, exec_lo, s20
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s2, s18, exec_lo
	s_and_b32 s3, s21, exec_lo
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr4
	s_or_b32 s4, s2, s3
.LBB0_195:                              ; %Flow2397
                                        ;   in Loop: Header=BB0_119 Depth=1
	s_and_not1_saveexec_b32 s19, s19
	s_cbranch_execz .LBB0_199
; %bb.196:                              ;   in Loop: Header=BB0_119 Depth=1
	s_waitcnt vmcnt(0)
	v_cmp_lt_i32_e32 vcc_lo, -1, v24
	v_cmp_gt_i32_e64 s2, s30, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s2
	s_mov_b32 s2, s4
	s_and_saveexec_b32 s20, s3
	s_xor_b32 s20, exec_lo, s20
	s_cbranch_execz .LBB0_198
; %bb.197:                              ;   in Loop: Header=BB0_119 Depth=1
	v_mul_lo_u32 v26, v24, s29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v23, v23, v22 :: v_dual_add_nc_u32 v4, v26, v4
	v_mad_u64_u32 v[24:25], null, v4, s28, s[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v4, v23, v23, 1.0
	v_mul_f32_e32 v4, v20, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v25, 31, v24
	v_lshlrev_b64 v[24:25], 2, v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v24, vcc_lo, s8, v24
	v_add_co_ci_u32_e32 v25, vcc_lo, s9, v25, vcc_lo
	v_div_scale_f32 v29, vcc_lo, v4, v14, v4
	global_load_b32 v24, v[24:25], off
	v_div_scale_f32 v25, null, v14, v14, v4
	v_add_nc_u32_e32 v26, v26, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v27, v25
	s_waitcnt_depctr 0xfff
	v_fma_f32 v28, -v25, v27, 1.0
	v_fmac_f32_e32 v27, v28, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v28, v29, v27
	v_fma_f32 v30, -v25, v28, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v28, v30, v27
	v_fma_f32 v25, -v25, v28, v29
	v_cvt_f32_i32_e32 v29, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v22, v29, v22
	v_div_fmas_f32 v25, v25, v27, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f32 v30, vcc_lo, v22, v23, v22
	v_div_fixup_f32 v4, v25, v14, v4
	v_div_scale_f32 v25, null, v23, v23, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v27, 0x4f800000, v4
	v_rcp_f32_e32 v28, v25
	v_cmp_gt_f32_e64 s2, 0xf800000, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v27, v4, v27, s2
	s_waitcnt_depctr 0xfff
	v_fma_f32 v29, -v25, v28, 1.0
	v_sqrt_f32_e32 v4, v27
	v_fmac_f32_e32 v28, v29, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v31, v30, v28
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v29, -1, v4
	v_fma_f32 v34, -v25, v31, v30
	v_fma_f32 v33, -v29, v4, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v31, v34, v28
	v_cmp_ge_f32_e64 s3, 0, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v25, -v25, v31, v30
	v_div_fmas_f32 v25, v25, v28, v31
	v_cmp_class_f32_e64 vcc_lo, v27, 0x260
	v_add_nc_u32_e32 v32, 1, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v22, v25, v23, v22
	v_fma_f32 v35, -v32, v4, v27
	v_cndmask_b32_e64 v4, v4, v29, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s3, 0, v35
	v_cndmask_b32_e64 v29, v4, v32, s3
	v_mad_u64_u32 v[4:5], null, v26, s28, s[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, 0x37800000, v29
	v_cndmask_b32_e64 v5, v29, v5, s2
	s_or_b32 s2, s4, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v23, v5, v27, vcc_lo
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v25, v22, v23
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s8, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v9, v25, v24
	global_store_b32 v[2:3], v9, off
	global_load_b32 v4, v[4:5], off
	v_sub_f32_e32 v5, 1.0, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v5, v23
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v9, v5, v4
.LBB0_198:                              ; %Flow2402
                                        ;   in Loop: Header=BB0_119 Depth=1
	s_or_b32 exec_lo, exec_lo, s20
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s3, s4, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_or_b32 s4, s3, s2
.LBB0_199:                              ; %Flow2401
                                        ;   in Loop: Header=BB0_119 Depth=1
	s_or_b32 exec_lo, exec_lo, s19
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s2, s18, exec_lo
	s_and_b32 s3, s4, exec_lo
	s_or_b32 s18, s2, s3
.LBB0_200:                              ; %Flow2396
                                        ;   in Loop: Header=BB0_119 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s4, s18, exec_lo
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr27
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr25
                                        ; implicit-def: $vgpr26
.LBB0_201:                              ; %Flow2387
                                        ;   in Loop: Header=BB0_119 Depth=1
	s_and_not1_saveexec_b32 s16, s16
	s_cbranch_execz .LBB0_219
; %bb.202:                              ;   in Loop: Header=BB0_119 Depth=1
	s_waitcnt vmcnt(0)
	v_cmp_lt_i32_e32 vcc_lo, -1, v4
	v_cmp_gt_i32_e64 s2, s29, v4
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s3, vcc_lo, s2
	s_mov_b32 s2, s4
	s_and_saveexec_b32 s17, s3
	s_cbranch_execz .LBB0_218
; %bb.203:                              ;   in Loop: Header=BB0_119 Depth=1
	s_mov_b32 s3, s4
	s_mov_b32 s2, exec_lo
	v_cmpx_ne_u32_e64 v27, v24
	s_xor_b32 s18, exec_lo, s2
	s_cbranch_execz .LBB0_213
; %bb.204:                              ;   in Loop: Header=BB0_119 Depth=1
	v_cmp_gt_i32_e32 vcc_lo, 1, v27
	v_cmp_le_i32_e64 s2, s30, v27
	s_mov_b32 s20, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s19, exec_lo, s3
	s_cbranch_execz .LBB0_210
; %bb.205:                              ;   in Loop: Header=BB0_119 Depth=1
	s_mov_b32 s20, exec_lo
	v_cmpx_eq_u32_e32 0, v27
	s_cbranch_execz .LBB0_207
; %bb.206:                              ;   in Loop: Header=BB0_119 Depth=1
	v_mad_u64_u32 v[28:29], null, v4, s28, s[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v29, 31, v28
	v_lshlrev_b64 v[28:29], 2, v[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v28, vcc_lo, s8, v28
	v_add_co_ci_u32_e32 v29, vcc_lo, s9, v29, vcc_lo
	global_load_b32 v5, v[28:29], off
	v_sub_f32_e32 v28, v23, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v28, v28, v28, 1.0
	v_mul_f32_e32 v28, v20, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v29, null, v14, v14, v28
	v_rcp_f32_e32 v30, v29
	s_waitcnt_depctr 0xfff
	v_fma_f32 v31, -v29, v30, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v30, v31, v30
	v_div_scale_f32 v31, vcc_lo, v28, v14, v28
	v_mul_f32_e32 v32, v31, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v33, -v29, v32, v31
	v_fmac_f32_e32 v32, v33, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v29, -v29, v32, v31
	v_div_fmas_f32 v29, v29, v30, v32
	v_sub_f32_e32 v30, v26, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v28, v29, v14, v28
	v_div_scale_f32 v29, null, v30, v30, -v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v31, 0x4f800000, v28
	v_cmp_gt_f32_e64 s2, 0xf800000, v28
	v_rcp_f32_e32 v32, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v28, v28, v31, s2
	v_sqrt_f32_e32 v31, v28
	s_waitcnt_depctr 0xfff
	v_fma_f32 v33, -v29, v32, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v32, v33, v32
	v_div_scale_f32 v33, vcc_lo, -v25, v30, -v25
	v_add_nc_u32_e32 v34, -1, v31
	v_dual_mul_f32 v36, v33, v32 :: v_dual_add_nc_u32 v35, 1, v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v37, -v34, v31, v28
	v_fma_f32 v38, -v35, v31, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v39, -v29, v36, v33
	v_cmp_ge_f32_e64 s3, 0, v37
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v36, v39, v32
	v_cndmask_b32_e64 v31, v31, v34, s3
	v_cmp_lt_f32_e64 s3, 0, v38
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v29, -v29, v36, v33
	v_cndmask_b32_e64 v31, v31, v35, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v29, v29, v32, v36
	v_cmp_class_f32_e64 vcc_lo, v28, 0x260
	v_mul_f32_e32 v33, 0x37800000, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v29, v29, v30, -v25
	v_cndmask_b32_e64 v31, v31, v33, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v29, 1.0, v29 :: v_dual_cndmask_b32 v28, v31, v28
	v_mul_f32_e32 v28, v28, v29
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v9, v28, v5
	global_store_b32 v[2:3], v9, off
.LBB0_207:                              ;   in Loop: Header=BB0_119 Depth=1
	s_or_b32 exec_lo, exec_lo, s20
	s_mov_b32 s2, s4
	s_mov_b32 s3, exec_lo
	v_cmpx_eq_u32_e64 s30, v27
	s_xor_b32 s20, exec_lo, s3
	s_cbranch_execz .LBB0_209
; %bb.208:                              ;   in Loop: Header=BB0_119 Depth=1
	v_mad_u64_u32 v[27:28], null, v24, s29, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v27, s28, s[10:11]
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v4, vcc_lo, s8, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	v_sub_f32_e32 v5, v23, v22
	v_fma_f32 v5, v5, v5, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v20, v5
	v_div_scale_f32 v22, null, v14, v14, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v23, v22
	s_waitcnt_depctr 0xfff
	v_fma_f32 v24, -v22, v23, 1.0
	v_fmac_f32_e32 v23, v24, v23
	v_div_scale_f32 v24, vcc_lo, v5, v14, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v27, v24, v23
	v_fma_f32 v28, -v22, v27, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v27, v28, v23
	v_fma_f32 v22, -v22, v27, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v22, v22, v23, v27
	v_sub_f32_e32 v23, v26, v25
	v_div_fixup_f32 v5, v22, v14, v5
	v_sub_f32_e32 v22, v16, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v24, 0x4f800000, v5
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v5
	v_div_scale_f32 v25, null, v23, v23, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v5, v5, v24, vcc_lo
	v_rcp_f32_e32 v24, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v26, v5
	s_waitcnt_depctr 0xfff
	v_fma_f32 v27, -v25, v24, 1.0
	v_add_nc_u32_e32 v28, -1, v26
	v_fmac_f32_e32 v24, v27, v24
	v_div_scale_f32 v27, s2, v22, v23, v22
	v_add_nc_u32_e32 v29, 1, v26
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v30, -v28, v26, v5
	v_mul_f32_e32 v32, v27, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v31, -v29, v26, v5
	v_cmp_ge_f32_e64 s3, 0, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v26, v26, v28, s3
	v_cmp_lt_f32_e64 s3, 0, v31
	v_fma_f32 v28, -v25, v32, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v26, v26, v29, s3
	v_fmac_f32_e32 v32, v28, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v28, 0x37800000, v26
	v_fma_f32 v25, -v25, v32, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v26, v26, v28, vcc_lo
	s_mov_b32 vcc_lo, s2
	s_or_b32 s2, s4, exec_lo
	v_div_fmas_f32 v24, v25, v24, v32
	v_cmp_class_f32_e64 vcc_lo, v5, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v22, v24, v23, v22
	v_cndmask_b32_e32 v5, v26, v5, vcc_lo
	v_mul_f32_e32 v5, v5, v22
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v9, v5, v4
.LBB0_209:                              ; %Flow2407
                                        ;   in Loop: Header=BB0_119 Depth=1
	s_or_b32 exec_lo, exec_lo, s20
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s3, s4, exec_lo
	s_and_b32 s2, s2, exec_lo
                                        ; implicit-def: $vgpr23
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr27
                                        ; implicit-def: $vgpr25
                                        ; implicit-def: $vgpr26
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr24
	s_or_b32 s20, s3, s2
.LBB0_210:                              ; %Flow2406
                                        ;   in Loop: Header=BB0_119 Depth=1
	s_and_not1_saveexec_b32 s19, s19
	s_cbranch_execz .LBB0_212
; %bb.211:                              ;   in Loop: Header=BB0_119 Depth=1
	v_mad_u64_u32 v[28:29], null, v24, s29, v[4:5]
	v_sub_f32_e32 v5, v23, v22
	s_or_b32 s20, s20, exec_lo
	v_sub_f32_e32 v26, v26, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v5, v5, v5, 1.0
	v_mad_u64_u32 v[29:30], null, v28, s28, s[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v5, v20, v5
	v_ashrrev_i32_e32 v30, 31, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f32 v22, null, v14, v14, v5
	v_lshlrev_b64 v[28:29], 2, v[29:30]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v23, v22
	v_add_co_u32 v28, vcc_lo, s8, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v29, vcc_lo, s9, v29, vcc_lo
	global_load_b32 v24, v[28:29], off
	v_fma_f32 v28, -v22, v23, 1.0
	v_div_scale_f32 v29, vcc_lo, v5, v14, v5
	v_fmac_f32_e32 v23, v28, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v28, v29, v23
	v_fma_f32 v30, -v22, v28, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v28, v30, v23
	v_fma_f32 v22, -v22, v28, v29
	v_cvt_f32_i32_e32 v29, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v22, v22, v23, v28
	v_sub_f32_e32 v25, v29, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v5, v22, v14, v5
	v_div_scale_f32 v28, null, v26, v26, v25
	v_div_scale_f32 v31, vcc_lo, v25, v26, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v22, 0x4f800000, v5
	v_cmp_gt_f32_e64 s2, 0xf800000, v5
	v_rcp_f32_e32 v29, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v30, v5, v22, s2
	v_sqrt_f32_e32 v5, v30
	s_waitcnt_depctr 0xfff
	v_fma_f32 v22, -v28, v29, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v29, v22, v29
	v_add_nc_u32_e32 v22, -1, v5
	v_add_nc_u32_e32 v33, 1, v5
	v_mul_f32_e32 v32, v31, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v23, -v22, v5, v30
	v_fma_f32 v35, -v33, v5, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v34, -v28, v32, v31
	v_cmp_ge_f32_e64 s3, 0, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v32, v34, v29
	v_cndmask_b32_e64 v5, v5, v22, s3
	v_cmp_lt_f32_e64 s3, 0, v35
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[22:23], null, v27, s29, v[4:5]
	v_cndmask_b32_e64 v23, v5, v33, s3
	v_fma_f32 v27, -v28, v32, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[4:5], null, v22, s28, s[10:11]
	v_mul_f32_e32 v5, 0x37800000, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v22, v27, v29, v32
	v_cmp_class_f32_e64 vcc_lo, v30, 0x260
	v_cndmask_b32_e64 v5, v23, v5, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v22, v22, v26, v25
	v_cndmask_b32_e32 v23, v5, v30, vcc_lo
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v25, v23, v22
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s8, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v9, v25, v24
	global_store_b32 v[2:3], v9, off
	global_load_b32 v4, v[4:5], off
	v_sub_f32_e32 v5, 1.0, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v23, v5
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v9, v5, v4
.LBB0_212:                              ; %Flow2408
                                        ;   in Loop: Header=BB0_119 Depth=1
	s_or_b32 exec_lo, exec_lo, s19
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s2, s4, exec_lo
	s_and_b32 s3, s20, exec_lo
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr4
	s_or_b32 s3, s2, s3
.LBB0_213:                              ; %Flow2405
                                        ;   in Loop: Header=BB0_119 Depth=1
	s_and_not1_saveexec_b32 s18, s18
	s_cbranch_execz .LBB0_217
; %bb.214:                              ;   in Loop: Header=BB0_119 Depth=1
	v_cmp_lt_i32_e32 vcc_lo, -1, v24
	v_cmp_gt_i32_e64 s2, s30, v24
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s20, vcc_lo, s2
	s_mov_b32 s2, s3
	s_and_saveexec_b32 s19, s20
	s_cbranch_execz .LBB0_216
; %bb.215:                              ;   in Loop: Header=BB0_119 Depth=1
	v_mad_u64_u32 v[25:26], null, v24, s29, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v25, s28, s[10:11]
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v4, vcc_lo, s8, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	v_sub_f32_e32 v5, v23, v22
	v_fma_f32 v5, v5, v5, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v20, v5
	v_div_scale_f32 v22, null, v14, v14, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v23, v22
	s_waitcnt_depctr 0xfff
	v_fma_f32 v24, -v22, v23, 1.0
	v_fmac_f32_e32 v23, v24, v23
	v_div_scale_f32 v24, vcc_lo, v5, v14, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v25, v24, v23
	v_fma_f32 v26, -v22, v25, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v25, v26, v23
	v_fma_f32 v22, -v22, v25, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v22, v22, v23, v25
	v_div_fixup_f32 v5, v22, v14, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v22, 0x4f800000, v5
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v5
	v_cndmask_b32_e32 v5, v5, v22, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v22, v5
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v23, -1, v22
	v_add_nc_u32_e32 v24, 1, v22
	v_fma_f32 v25, -v23, v22, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v26, -v24, v22, v5
	v_cmp_ge_f32_e64 s2, 0, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v22, v22, v23, s2
	v_cmp_lt_f32_e64 s2, 0, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v22, v22, v24, s2
	s_or_b32 s2, s3, exec_lo
	v_mul_f32_e32 v23, 0x37800000, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v22, v22, v23, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v5, 0x260
	v_cndmask_b32_e32 v5, v22, v5, vcc_lo
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v9, v5, v4
.LBB0_216:                              ; %Flow2410
                                        ;   in Loop: Header=BB0_119 Depth=1
	s_or_b32 exec_lo, exec_lo, s19
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s3, s3, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_or_b32 s3, s3, s2
.LBB0_217:                              ; %Flow2409
                                        ;   in Loop: Header=BB0_119 Depth=1
	s_or_b32 exec_lo, exec_lo, s18
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s2, s4, exec_lo
	s_and_b32 s3, s3, exec_lo
	s_or_b32 s2, s2, s3
.LBB0_218:                              ; %Flow2404
                                        ;   in Loop: Header=BB0_119 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s3, s4, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_or_b32 s4, s3, s2
.LBB0_219:                              ; %Flow2403
                                        ;   in Loop: Header=BB0_119 Depth=1
	s_or_b32 exec_lo, exec_lo, s16
	s_and_saveexec_b32 s2, s4
	s_cbranch_execz .LBB0_221
; %bb.220:                              ; %.sink.split2164
                                        ;   in Loop: Header=BB0_119 Depth=1
	global_store_b32 v[2:3], v9, off
.LBB0_221:                              ;   in Loop: Header=BB0_119 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_add_u32 s10, s10, 1
	s_addc_u32 s11, s11, 0
	s_add_u32 s6, s6, 4
	s_addc_u32 s7, s7, 0
	s_cmp_eq_u32 s28, s10
	s_cbranch_scc0 .LBB0_119
	s_branch .LBB0_223
.LBB0_222:
	v_mov_b32_e32 v9, 0
.LBB0_223:                              ; %.loopexit
	s_or_b32 exec_lo, exec_lo, s14
	s_waitcnt vmcnt(0)
	v_frexp_mant_f32_e64 v4, |v7|
	v_frexp_mant_f32_e64 v11, |v6|
	v_frexp_exp_i32_f32_e32 v10, v7
	v_frexp_exp_i32_f32_e32 v13, v8
	v_frexp_exp_i32_f32_e32 v12, v6
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v4
	v_cmp_gt_f32_e64 s0, 0x3f2aaaab, v11
	s_mov_b32 s2, 0x3e76c4e1
	v_cndmask_b32_e64 v5, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v14, 0, 1, s0
	v_subrev_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	v_subrev_co_ci_u32_e64 v12, vcc_lo, 0, v12, s0
	v_ldexp_f32 v4, v4, v5
	v_frexp_mant_f32_e64 v5, |v8|
	v_ldexp_f32 v11, v11, v14
	v_cvt_f32_i32_e32 v10, v10
	v_cvt_f32_i32_e32 v12, v12
	v_add_f32_e32 v15, 1.0, v4
	v_cmp_gt_f32_e64 s1, 0x3f2aaaab, v5
	v_cmp_neq_f32_e64 s0, 0x7f800000, |v7|
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v16, 0, 1, s1
	v_subrev_co_ci_u32_e64 v13, vcc_lo, 0, v13, s1
	v_ldexp_f32 v5, v5, v16
	v_add_f32_e32 v16, 1.0, v11
	v_rcp_f32_e32 v17, v15
	v_add_f32_e32 v14, -1.0, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v24, -1.0, v11 :: v_dual_add_f32 v25, -1.0, v5
	v_dual_add_f32 v18, 1.0, v5 :: v_dual_add_f32 v27, -1.0, v16
	v_rcp_f32_e32 v20, v16
	v_add_f32_e32 v22, -1.0, v15
	v_cvt_f32_i32_e32 v13, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(TRANS32_DEP_3)
	v_rcp_f32_e32 v21, v18
	v_mul_f32_e32 v19, v14, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v11, v11, v27 :: v_dual_sub_f32 v4, v4, v22
	v_mul_f32_e32 v23, v15, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_fma_f32 v15, v19, v15, -v23
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v26, v25, v21 :: v_dual_fmac_f32 v15, v19, v4
	v_dual_mul_f32 v22, v24, v20 :: v_dual_mul_f32 v29, v18, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v28, -1.0, v18 :: v_dual_add_f32 v27, v23, v15
	v_mul_f32_e32 v4, v16, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v18, v26, v18, -v29
	v_dual_sub_f32 v5, v5, v28 :: v_dual_mul_f32 v28, 0x3f317218, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v16, v22, v16, -v4
	v_dual_fmac_f32 v18, v26, v5 :: v_dual_mul_f32 v5, 0x3f317218, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v16, v22, v11
	v_sub_f32_e32 v11, v27, v23
	v_dual_add_f32 v31, v29, v18 :: v_dual_sub_f32 v30, v14, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v23, v4, v16 :: v_dual_mul_f32 v32, 0x3f317218, v13
	v_dual_sub_f32 v11, v11, v15 :: v_dual_sub_f32 v14, v14, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v29, v31, v29
	v_dual_sub_f32 v15, v24, v23 :: v_dual_sub_f32 v4, v23, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v14, v14, v27
	v_sub_f32_e32 v27, v25, v31
	v_dual_add_f32 v11, v11, v14 :: v_dual_sub_f32 v14, v24, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v4, v4, v16 :: v_dual_add_f32 v11, v30, v11
	v_sub_f32_e32 v14, v14, v23
	v_fma_f32 v23, 0x3f317218, v10, -v28
	v_sub_f32_e32 v24, v25, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v11, v17, v11 :: v_dual_add_f32 v4, v4, v14
	v_sub_f32_e32 v16, v29, v18
	v_dual_fmac_f32 v23, 0xb102e308, v10 :: v_dual_sub_f32 v18, v24, v31
	v_fma_f32 v24, 0x3f317218, v12, -v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f32_e32 v10, v19, v11
	v_add_f32_e32 v4, v15, v4
	v_fmac_f32_e32 v24, 0xb102e308, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v12, v10, v19
	v_mul_f32_e32 v4, v20, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v11, v11, v12
	v_add_f32_e32 v12, v22, v4
	v_add_f32_e32 v14, v16, v18
	v_fma_f32 v16, 0x3f317218, v13, -v32
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v25, v12, v12
	v_dual_mul_f32 v15, v10, v10 :: v_dual_add_f32 v20, v11, v11
	v_fmac_f32_e32 v16, 0xb102e308, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v19, v10, v10, -v15
	v_dual_add_f32 v14, v27, v14 :: v_dual_fmac_f32 v19, v10, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v13, v21, v14
	v_sub_f32_e32 v21, v12, v22
	v_fma_f32 v20, v12, v12, -v25
	v_add_f32_e32 v17, v26, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v22, v17, v26
	v_dual_sub_f32 v13, v13, v22 :: v_dual_add_f32 v22, v15, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v29, v13, v13
	v_dual_fmaak_f32 v31, s2, v22, 0x3e91f4c4 :: v_dual_sub_f32 v4, v4, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v27, v4, v4
	v_fmac_f32_e32 v20, v12, v27
	v_ldexp_f32 v27, v10, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v33, v25, v20
	v_sub_f32_e32 v25, v33, v25
	v_dual_mul_f32 v26, v17, v17 :: v_dual_sub_f32 v15, v22, v15
	v_dual_add_f32 v18, v5, v24 :: v_dual_fmaak_f32 v31, v22, v31, 0x3ecccdef
	v_mul_f32_e32 v35, v10, v22
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f32 v21, v17, v17, -v26
	v_add_f32_e32 v14, v28, v23
	v_sub_f32_e32 v15, v19, v15
	v_fmaak_f32 v37, s2, v33, 0x3e91f4c4
	v_fma_f32 v41, v22, v10, -v35
	v_dual_fmac_f32 v21, v17, v29 :: v_dual_mul_f32 v36, v22, v31
	v_ldexp_f32 v29, v11, 1
	v_sub_f32_e32 v5, v18, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v41, v22, v11
	v_fma_f32 v19, v22, v31, -v36
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v28, v14, v28 :: v_dual_fmac_f32 v41, v15, v10
	v_dual_fmac_f32 v19, v15, v31 :: v_dual_add_f32 v34, v26, v21
	v_dual_add_f32 v30, v32, v16 :: v_dual_fmaak_f32 v31, v33, v37, 0x3ecccdef
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v39, s2, v34, 0x3e91f4c4 :: v_dual_mul_f32 v38, v12, v33
	v_fmaak_f32 v37, v34, v39, 0x3ecccdef
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_add_f32 v39, v36, v19 :: v_dual_mul_f32 v40, v17, v34
	v_sub_f32_e32 v20, v20, v25
	v_fma_f32 v25, v33, v12, -v38
	v_sub_f32_e32 v26, v34, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v22, 0x3f2aaaaa, v39 :: v_dual_fmac_f32 v25, v33, v4
	v_sub_f32_e32 v21, v21, v26
	v_fma_f32 v26, v34, v17, -v40
	v_dual_sub_f32 v11, v39, v36 :: v_dual_mul_f32 v36, v33, v31
	v_ldexp_f32 v4, v4, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v26, v34, v13 :: v_dual_sub_f32 v11, v19, v11
	v_dual_mul_f32 v42, v34, v37 :: v_dual_add_f32 v19, 0xbf2aaaaa, v22
	v_fma_f32 v10, v33, v31, -v36
	v_add_f32_e32 v33, v35, v41
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v11, 0x31739010, v11
	v_fma_f32 v15, v34, v37, -v42
	v_dual_fmac_f32 v25, v20, v12 :: v_dual_fmac_f32 v26, v21, v17
	v_fmac_f32_e32 v10, v20, v31
	v_sub_f32_e32 v19, v39, v19
	v_ldexp_f32 v12, v12, 1
	v_ldexp_f32 v17, v17, 1
	v_ldexp_f32 v13, v13, 1
	v_dual_add_f32 v20, v36, v10 :: v_dual_fmac_f32 v15, v21, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_add_f32 v34, 0x3f2aaaaa, v20 :: v_dual_add_f32 v21, v42, v15
	v_add_f32_e32 v11, v11, v19
	v_sub_f32_e32 v19, v33, v35
	v_dual_sub_f32 v35, v20, v36 :: v_dual_add_f32 v36, 0x3f2aaaaa, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v31, v22, v11
	v_sub_f32_e32 v22, v22, v31
	v_mul_f32_e32 v37, v33, v31
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v10, v10, v35 :: v_dual_add_f32 v35, 0xbf2aaaaa, v34
	v_add_f32_e32 v11, v11, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v22, v33, v31, -v37
	v_add_f32_e32 v10, 0x31739010, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v20, v20, v35
	v_sub_f32_e32 v19, v41, v19
	v_dual_fmac_f32 v22, v33, v11 :: v_dual_add_f32 v11, v38, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v10, v10, v20
	v_sub_f32_e32 v20, v11, v38
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v20, v25, v20
	v_dual_sub_f32 v39, v21, v42 :: v_dual_fmac_f32 v22, v19, v31
	v_add_f32_e32 v19, v40, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v15, v15, v39
	v_add_f32_e32 v39, 0xbf2aaaaa, v36
	v_add_f32_e32 v15, 0x31739010, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v21, v21, v39
	v_add_f32_e32 v15, v15, v21
	v_add_f32_e32 v21, v34, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v34, v34, v21
	v_mul_f32_e32 v38, v11, v21
	v_add_f32_e32 v10, v10, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v34, v11, v21, -v38
	v_fmac_f32_e32 v34, v11, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v31, v37, v22 :: v_dual_fmac_f32 v34, v20, v21
	v_sub_f32_e32 v37, v31, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v33, v19, v40 :: v_dual_sub_f32 v22, v22, v37
	v_sub_f32_e32 v10, v26, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v22, v29, v22 :: v_dual_add_f32 v25, v36, v15
	v_sub_f32_e32 v36, v36, v25
	v_mul_f32_e32 v39, v19, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v15, v15, v36
	v_fma_f32 v29, v19, v25, -v39
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v29, v19, v15
	v_sub_f32_e32 v15, v23, v28
	v_fmac_f32_e32 v29, v10, v25
	v_dual_add_f32 v10, v38, v34 :: v_dual_add_f32 v35, v27, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v23, v10, v38
	v_sub_f32_e32 v27, v35, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v23, v34, v23
	v_sub_f32_e32 v27, v31, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v4, v4, v23
	v_dual_add_f32 v11, v22, v27 :: v_dual_add_f32 v22, v12, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v12, v22, v12
	v_dual_sub_f32 v10, v10, v12 :: v_dual_add_f32 v21, v39, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v4, v4, v10
	v_add_f32_e32 v28, v17, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v17, v28, v17
	v_dual_sub_f32 v10, v21, v17 :: v_dual_add_f32 v19, v35, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v17, v22, v4
	v_add_f32_e32 v20, v14, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v27, v19, v35 :: v_dual_sub_f32 v22, v17, v22
	v_dual_sub_f32 v26, v21, v39 :: v_dual_add_f32 v21, v18, v17
	v_sub_f32_e32 v25, v20, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v11, v11, v27 :: v_dual_sub_f32 v4, v4, v22
	v_sub_f32_e32 v31, v20, v25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v12, v19, v25 :: v_dual_sub_f32 v19, v29, v26
	v_sub_f32_e32 v14, v14, v31
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v23, v15, v11
	v_dual_add_f32 v13, v13, v19 :: v_dual_add_f32 v12, v12, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v14, v23, v15
	v_add_f32_e32 v10, v13, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v12, v23, v12
	v_sub_f32_e32 v13, v23, v14
	v_sub_f32_e32 v11, v11, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v19, v20, v12
	v_sub_f32_e32 v13, v15, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v15, v21, v18 :: v_dual_sub_f32 v14, v19, v20
	v_dual_add_f32 v20, v28, v10 :: v_dual_add_f32 v11, v11, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v13, v21, v15 :: v_dual_sub_f32 v12, v12, v14
	v_add_f32_e32 v14, v30, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_add_f32 v11, v11, v12 :: v_dual_sub_f32 v12, v18, v13
	v_sub_f32_e32 v13, v30, v32
	v_dual_sub_f32 v18, v14, v30 :: v_dual_sub_f32 v5, v24, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v13, v16, v13
	v_dual_sub_f32 v16, v20, v18 :: v_dual_sub_f32 v15, v17, v15
	v_sub_f32_e32 v24, v14, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v12, v15, v12
	v_sub_f32_e32 v15, v20, v28
	v_sub_f32_e32 v10, v10, v15
	v_add_f32_e32 v23, v19, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v15, v30, v24 :: v_dual_add_f32 v18, v13, v10
	v_sub_f32_e32 v19, v23, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v15, v16, v15
	v_sub_f32_e32 v11, v11, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v19, v18, v13
	v_add_f32_e32 v17, v5, v4
	v_add_f32_e32 v15, v18, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v10, v10, v19
	v_sub_f32_e32 v22, v17, v5
	v_add_f32_e32 v12, v17, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v25, v17, v22
	v_dual_add_f32 v17, v21, v12 :: v_dual_sub_f32 v4, v4, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v5, v5, v25
	v_sub_f32_e32 v16, v17, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v4, v4, v5
	v_dual_sub_f32 v5, v12, v16 :: v_dual_sub_f32 v12, v18, v19
	v_add_f32_e32 v18, v14, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v4, v4, v5 :: v_dual_sub_f32 v5, v13, v12
	v_dual_sub_f32 v12, v18, v14 :: v_dual_mul_f32 v21, 0, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v20, v23, v23 :: v_dual_add_f32 v5, v10, v5
	v_dual_sub_f32 v10, v15, v12 :: v_dual_fmac_f32 v21, 2.0, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v11, v17, v4
	v_fma_f32 v16, v23, 2.0, -v20
	v_cmp_class_f32_e64 vcc_lo, v20, 0x204
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v5, v5, v10
	v_dual_sub_f32 v13, v11, v17 :: v_dual_mul_f32 v14, 0, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v15, v18, v5
	v_dual_sub_f32 v4, v4, v13 :: v_dual_add_f32 v13, v11, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v14, 2.0, v4
	v_fma_f32 v11, v11, 2.0, -v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v4, v15, v18
	v_dual_add_f32 v11, v11, v14 :: v_dual_sub_f32 v4, v5, v4
	v_add_f32_e32 v5, v15, v15
	v_mul_f32_e32 v14, 0, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v18, v13, v11
	v_fma_f32 v15, v15, 2.0, -v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v14, 2.0, v4
	v_add_f32_e32 v14, v15, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v22, v5, v14
	v_add_f32_e32 v12, v16, v21
	v_add_f32_e32 v10, v20, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v16, v10, v20, vcc_lo
	v_sub_f32_e32 v10, v10, v20
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v10, v12, v10
	v_cndmask_b32_e64 v17, 0, 0x37000000, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v13, 0x204
	v_sub_f32_e32 v19, v16, v17
	v_cndmask_b32_e32 v4, v18, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v4
	v_cndmask_b32_e64 v21, 0, 0x37000000, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v15, 0x3fb8aa3b, v19
	v_cmp_class_f32_e64 vcc_lo, v5, 0x204
	v_fma_f32 v23, 0x3fb8aa3b, v19, -v15
	v_rndne_f32_e32 v24, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v26, v22, v5 :: v_dual_fmac_f32 v23, 0x32a5705f, v19
	v_sub_f32_e32 v15, v15, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v26
	v_add_f32_e32 v15, v15, v23
	v_cndmask_b32_e64 v28, 0, 0x37000000, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v16|
	v_cvt_i32_f32_e32 v16, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_exp_f32_e32 v12, v15
	v_dual_sub_f32 v23, v26, v28 :: v_dual_cndmask_b32 v10, 0, v10
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v19
	v_sub_f32_e32 v13, v18, v13
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_mul_f32 v15, 0x3fb8aa3b, v23 :: v_dual_add_f32 v10, v17, v10
	v_sub_f32_e32 v5, v22, v5
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v12, v12, v16
	v_fma_f32 v24, 0x3fb8aa3b, v23, -v15
	v_rndne_f32_e32 v30, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v5, v14, v5 :: v_dual_cndmask_b32 v12, 0, v12
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v19
	v_dual_sub_f32 v25, v4, v21 :: v_dual_fmac_f32 v24, 0x32a5705f, v23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v15, v15, v30
	v_dual_sub_f32 v11, v11, v13 :: v_dual_cndmask_b32 v12, 0x7f800000, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v27, 0x3fb8aa3b, v25
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v4|
	v_add_f32_e32 v15, v15, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v10, v12, v10, v12
	v_fma_f32 v20, 0x3fb8aa3b, v25, -v27
	v_rndne_f32_e32 v29, v27
	s_delay_alu instid0(VALU_DEP_4)
	v_exp_f32_e32 v13, v15
	v_cndmask_b32_e32 v4, 0, v11, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v25
	v_fmac_f32_e32 v20, 0x32a5705f, v25
	v_sub_f32_e32 v27, v27, v29
	v_cvt_i32_f32_e32 v17, v29
	v_cvt_i32_f32_e32 v11, v30
	v_add_f32_e32 v4, v21, v4
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f32_e32 v20, v27, v20
	s_delay_alu instid0(TRANS32_DEP_1) | instid1(VALU_DEP_3)
	v_ldexp_f32 v11, v13, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_exp_f32_e32 v16, v20
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v15, v16, v17
	v_cndmask_b32_e32 v15, 0, v15, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v13, 0x7f800000, v15, vcc_lo
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v26|
	v_fma_f32 v4, v13, v4, v13
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_f32_e32 v5, v28, v5
	v_cndmask_b32_e32 v11, 0, v11, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v23
	v_cndmask_b32_e32 v11, 0x7f800000, v11, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f32 v5, v11, v5, v11
	v_cndmask_b32_e32 v10, v10, v12, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v13
	v_cndmask_b32_e64 v10, 0x7f800000, |v10|, s0
	v_cndmask_b32_e32 v4, v4, v13, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v11
	v_cmp_neq_f32_e64 s0, 0x7f800000, |v6|
	v_cndmask_b32_e32 v5, v5, v11, vcc_lo
	v_cmp_neq_f32_e32 vcc_lo, 0, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v4, 0x7f800000, |v4|, s0
	v_cmp_neq_f32_e64 s0, 0x7f800000, |v8|
	v_cndmask_b32_e32 v7, 0, v10, vcc_lo
	v_cmp_neq_f32_e32 vcc_lo, 0, v6
	v_cndmask_b32_e64 v5, 0x7f800000, |v5|, s0
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	v_cmp_neq_f32_e32 vcc_lo, 0, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v4, v7, v4 :: v_dual_cndmask_b32 v5, 0, v5
	v_add_f32_e32 v4, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v5, 0x4f800000, v4
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v4
	v_cndmask_b32_e32 v4, v4, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v5, v4
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v6, -1, v5
	v_add_nc_u32_e32 v7, 1, v5
	v_fma_f32 v8, -v6, v5, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v10, -v7, v5, v4
	v_cmp_ge_f32_e64 s0, 0, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v5, v5, v6, s0
	v_cmp_lt_f32_e64 s0, 0, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v5, v5, v7, s0
	v_mul_f32_e32 v6, 0x37800000, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v5, v5, v6, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v4, 0x260
	v_dual_cndmask_b32 v4, v5, v4 :: v_dual_mul_f32 v5, s26, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v4, s26, v4
	v_div_scale_f32 v6, null, v4, v4, v5
	v_div_scale_f32 v9, vcc_lo, v5, v4, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v7, v6
	s_waitcnt_depctr 0xfff
	v_fma_f32 v8, -v6, v7, 1.0
	v_fmac_f32_e32 v7, v8, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v8, v9, v7
	v_fma_f32 v10, -v6, v8, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v8, v10, v7
	v_fma_f32 v6, -v6, v8, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v6, v6, v7, v8
	v_add_co_u32 v0, vcc_lo, s12, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s13, v1, vcc_lo
	v_div_fixup_f32 v4, v6, v4, v5
	global_store_b32 v[2:3], v5, off
	global_store_b32 v[0:1], v4, off
.LBB0_224:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z25Ax_cone_mf_gpu_kernel_newPfS_S_S_S_S_S_Piffffiiiiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 104
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 46
		.amdhsa_next_free_sgpr 32
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z25Ax_cone_mf_gpu_kernel_newPfS_S_S_S_S_S_Piffffiiiiii, .Lfunc_end0-_Z25Ax_cone_mf_gpu_kernel_newPfS_S_S_S_S_S_Piffffiiiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 26220
; NumSgprs: 34
; NumVgprs: 46
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 34
; NumVGPRsForWavesPerEU: 46
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .offset:         64
        .size:           4
        .value_kind:     by_value
      - .offset:         68
        .size:           4
        .value_kind:     by_value
      - .offset:         72
        .size:           4
        .value_kind:     by_value
      - .offset:         76
        .size:           4
        .value_kind:     by_value
      - .offset:         80
        .size:           4
        .value_kind:     by_value
      - .offset:         84
        .size:           4
        .value_kind:     by_value
      - .offset:         88
        .size:           4
        .value_kind:     by_value
      - .offset:         92
        .size:           4
        .value_kind:     by_value
      - .offset:         96
        .size:           4
        .value_kind:     by_value
      - .offset:         100
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 104
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z25Ax_cone_mf_gpu_kernel_newPfS_S_S_S_S_S_Piffffiiiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     34
    .sgpr_spill_count: 0
    .symbol:         _Z25Ax_cone_mf_gpu_kernel_newPfS_S_S_S_S_S_Piffffiiiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     46
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
