/* Voxel sampling GPU implementation
 * Author Zhaoyu SU
 * All Rights Reserved. Sep., 2019.
 */
#include <stdio.h>
#include <iostream>
#include <float.h>


__device__ int get_batch_id(int* accu_list, int batch_size, int id) {
    for (int b=0; b<batch_size-1; b++) {
        if (id >= accu_list[b]) {
            if(id < accu_list[b+1])
                return b;
        }
    }
    return batch_size - 1;
}


__global__ void bev_occupy_gpu_kernel(int batch_size, int input_point_num,
                                      int output_w, int output_l, float resolution,
                                      const float* input_coors,
                                      const int* input_num_list,
                                      int* input_accu_list,
                                      int* output_occupy) {
    const int output_img_size = output_w * output_l;
    int point_id = threadIdx.x + blockIdx.x * blockDim.x;
    if (point_id < input_point_num) {
        int center_grid_coor_x = (int)floor(input_coors[point_id*3 + 0] / resolution);
        int center_grid_coor_y = (int)floor(input_coors[point_id*3 + 1] / resolution);
        int batch_id = get_batch_id(input_accu_list, batch_size, point_id);
        int output_idx = batch_id * output_img_size + center_grid_coor_x * output_l + center_grid_coor_y;
        atomicAdd(&output_occupy[output_idx], 1);
    }
}



void bev_occupy_gpu_launcher(int batch_size, int input_point_num,
                             int output_w, int output_l, float resolution,
                             const float* input_coors,
                             const int* input_num_list,
                             int* input_accu_list,
                             int* output_occupy) {
    if (batch_size*input_point_num <=0) {
        printf("BevOccupyOp ERROR: Invalid CUDA input dimensions.\n");
        return;
    }

    int blockSize;      // The launch configurator returned block size
    int minGridSize;    // The minimum grid size needed to achieve the maximum occupancy for a full device launch
    int gridSize;       // The actual grid size needed, based on input size


    cudaOccupancyMaxPotentialBlockSize(&minGridSize, &blockSize, bev_occupy_gpu_kernel, 0, input_point_num);
    gridSize = (input_point_num + blockSize - 1) / blockSize;
    bev_occupy_gpu_kernel<<<gridSize, blockSize>>>(batch_size, input_point_num,
                                                   output_w, output_l, resolution,
                                                   input_coors,
                                                   input_num_list,
                                                   input_accu_list,
                                                   output_occupy);
}


	.file	"tmpxft_00204de1_00000000-6_bev_occupy.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3639:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3639:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z12get_batch_idPiii
	.type	_Z12get_batch_idPiii, @function
_Z12get_batch_idPiii:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3635:
	.size	_Z12get_batch_idPiii, .-_Z12get_batch_idPiii
	.globl	_Z55__device_stub__Z21bev_occupy_gpu_kerneliiiifPKfPKiPiS3_iiiifPKfPKiPiS3_
	.type	_Z55__device_stub__Z21bev_occupy_gpu_kerneliiiifPKfPKiPiS3_iiiifPKfPKiPiS3_, @function
_Z55__device_stub__Z21bev_occupy_gpu_kerneliiiifPKfPKiPiS3_iiiifPKfPKiPiS3_:
.LFB3661:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	224(%rsp), %rax
	movl	%edi, 60(%rsp)
	leaq	80(%rsp), %rdi
	movl	%esi, 56(%rsp)
	leaq	92(%rsp), %rsi
	movq	%rax, 16(%rsp)
	movq	232(%rsp), %rax
	movl	%edx, 52(%rsp)
	leaq	64(%rsp), %rdx
	movl	%ecx, 48(%rsp)
	leaq	72(%rsp), %rcx
	movq	%r8, 32(%rsp)
	movq	%r9, 24(%rsp)
	movq	%rax, 8(%rsp)
	movss	%xmm0, 44(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	60(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 128(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	52(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	44(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	72(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z21bev_occupy_gpu_kerneliiiifPKfPKiPiS3_(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 240
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L4:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3661:
	.size	_Z55__device_stub__Z21bev_occupy_gpu_kerneliiiifPKfPKiPiS3_iiiifPKfPKiPiS3_, .-_Z55__device_stub__Z21bev_occupy_gpu_kerneliiiifPKfPKiPiS3_iiiifPKfPKiPiS3_
	.globl	_Z21bev_occupy_gpu_kerneliiiifPKfPKiPiS3_
	.type	_Z21bev_occupy_gpu_kerneliiiifPKfPKiPiS3_, @function
_Z21bev_occupy_gpu_kerneliiiifPKfPKiPiS3_:
.LFB3662:
	.cfi_startproc
	endbr64
	jmp	_Z55__device_stub__Z21bev_occupy_gpu_kerneliiiifPKfPKiPiS3_iiiifPKfPKiPiS3_
	.cfi_endproc
.LFE3662:
	.size	_Z21bev_occupy_gpu_kerneliiiifPKfPKiPiS3_, .-_Z21bev_occupy_gpu_kerneliiiifPKfPKiPiS3_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"BevOccupyOp ERROR: Invalid CUDA input dimensions.\n"
	.text
	.globl	_Z23bev_occupy_gpu_launcheriiiifPKfPKiPiS3_
	.type	_Z23bev_occupy_gpu_launcheriiiifPKfPKiPiS3_, @function
_Z23bev_occupy_gpu_launcheriiiifPKfPKiPiS3_:
.LFB3636:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$248, %rsp
	.cfi_def_cfa_offset 304
	movl	%edx, 4(%rsp)
	movq	304(%rsp), %r14
	movl	%ecx, 8(%rsp)
	movq	312(%rsp), %r15
	movq	%r8, 16(%rsp)
	movq	%r9, 24(%rsp)
	movss	%xmm0, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 232(%rsp)
	movl	%edi, %eax
	imull	%esi, %eax
	testl	%eax, %eax
	jg	.L11
	movq	232(%rsp), %rax
	subq	%fs:40, %rax
	jne	.L27
	addq	$248, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	leaq	.LC0(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	__printf_chk@PLT
.L11:
	.cfi_restore_state
	movl	%edi, %r13d
	leaq	48(%rsp), %rdi
	movl	%esi, %ebp
	call	cudaGetDevice@PLT
	testl	%eax, %eax
	jne	.L14
	movl	48(%rsp), %edx
	leaq	52(%rsp), %rdi
	movl	$39, %esi
	call	cudaDeviceGetAttribute@PLT
	testl	%eax, %eax
	jne	.L14
	movl	48(%rsp), %edx
	leaq	56(%rsp), %rdi
	movl	$10, %esi
	call	cudaDeviceGetAttribute@PLT
	testl	%eax, %eax
	jne	.L14
	movl	48(%rsp), %edx
	leaq	60(%rsp), %rdi
	movl	$1, %esi
	call	cudaDeviceGetAttribute@PLT
	testl	%eax, %eax
	jne	.L14
	movl	48(%rsp), %edx
	leaq	64(%rsp), %rdi
	movl	$16, %esi
	call	cudaDeviceGetAttribute@PLT
	testl	%eax, %eax
	jne	.L14
	leaq	88(%rsp), %rdi
	leaq	_Z21bev_occupy_gpu_kerneliiiifPKfPKiPiS3_(%rip), %rsi
	call	cudaFuncGetAttributes@PLT
	testl	%eax, %eax
	jne	.L14
	movl	52(%rsp), %eax
	movl	60(%rsp), %ebx
	testl	%ebp, %ebp
	movl	112(%rsp), %edx
	movl	56(%rsp), %r10d
	movl	%eax, (%rsp)
	movl	%ebp, %eax
	cmove	%ebx, %eax
	cmpl	%edx, %ebx
	cmovg	%edx, %ebx
	cmpl	%eax, %ebx
	cmovg	%eax, %ebx
	xorl	%r11d, %r11d
	xorl	%r12d, %r12d
	leal	-1(%r10,%rbx), %r9d
	movl	%r9d, %eax
	cltd
	idivl	%r10d
	subl	%edx, %r9d
.L17:
	testl	%r9d, %r9d
	jle	.L14
	cmpl	%r9d, %ebx
	movl	%r9d, %edx
	leaq	76(%rsp), %rdi
	movl	%r11d, 44(%rsp)
	cmovle	%ebx, %edx
	xorl	%r8d, %r8d
	xorl	%ecx, %ecx
	movl	%r10d, 40(%rsp)
	leaq	_Z21bev_occupy_gpu_kerneliiiifPKfPKiPiS3_(%rip), %rsi
	movl	%r9d, 36(%rsp)
	movl	%edx, 32(%rsp)
	call	cudaOccupancyMaxActiveBlocksPerMultiprocessorWithFlags@PLT
	testl	%eax, %eax
	jne	.L14
	movl	32(%rsp), %edx
	movl	76(%rsp), %eax
	movl	44(%rsp), %r11d
	movl	36(%rsp), %r9d
	imull	%edx, %eax
	movl	40(%rsp), %r10d
	cmpl	%r11d, %eax
	jle	.L18
	movl	%eax, %r11d
	movl	%edx, %r12d
.L18:
	cmpl	%r11d, (%rsp)
	je	.L14
	subl	%r10d, %r9d
	jmp	.L17
.L14:
	leal	-1(%r12,%rbp), %eax
	movl	%r12d, 76(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rcx
	cltd
	idivl	%r12d
	movq	%rcx, 68(%rsp)
	movl	72(%rsp), %esi
	movq	%rcx, 80(%rsp)
	movl	84(%rsp), %ecx
	movq	76(%rsp), %rdx
	movl	%eax, 64(%rsp)
	movq	64(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	movq	232(%rsp), %rax
	subq	%fs:40, %rax
	jne	.L27
	movq	24(%rsp), %r9
	movq	16(%rsp), %r8
	movl	%ebp, %esi
	movl	%r13d, %edi
	movl	8(%rsp), %ecx
	movl	4(%rsp), %edx
	movq	%r15, 312(%rsp)
	movq	%r14, 304(%rsp)
	movss	12(%rsp), %xmm0
	addq	$248, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z55__device_stub__Z21bev_occupy_gpu_kerneliiiifPKfPKiPiS3_iiiifPKfPKiPiS3_
.L10:
	.cfi_restore_state
	movq	232(%rsp), %rax
	subq	%fs:40, %rax
	je	.L22
.L27:
	call	__stack_chk_fail@PLT
.L22:
	addq	$248, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3636:
	.size	_Z23bev_occupy_gpu_launcheriiiifPKfPKiPiS3_, .-_Z23bev_occupy_gpu_launcheriiiifPKfPKiPiS3_
	.section	.rodata.str1.1
.LC1:
	.string	"_Z21bev_occupy_gpu_kerneliiiifPKfPKiPiS3_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3664:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC1(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z21bev_occupy_gpu_kerneliiiifPKfPKiPiS3_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3664:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/* Voxel sampling GPU implementation
 * Author Zhaoyu SU
 * All Rights Reserved. Sep., 2019.
 */

#include <hip/hip_runtime.h>
#include <stdio.h>
#include <iostream>
#include <float.h>


__device__ int get_batch_id(int* accu_list, int batch_size, int id) {
    for (int b=0; b<batch_size-1; b++) {
        if (id >= accu_list[b]) {
            if(id < accu_list[b+1])
                return b;
        }
    }
    return batch_size - 1;
}


__global__ void bev_occupy_gpu_kernel(int batch_size, int input_point_num,
                                      int output_w, int output_l, float resolution,
                                      const float* input_coors,
                                      const int* input_num_list,
                                      int* input_accu_list,
                                      int* output_occupy) {
    const int output_img_size = output_w * output_l;
    int point_id = threadIdx.x + blockIdx.x * blockDim.x;
    if (point_id < input_point_num) {
        int center_grid_coor_x = (int)floor(input_coors[point_id*3 + 0] / resolution);
        int center_grid_coor_y = (int)floor(input_coors[point_id*3 + 1] / resolution);
        int batch_id = get_batch_id(input_accu_list, batch_size, point_id);
        int output_idx = batch_id * output_img_size + center_grid_coor_x * output_l + center_grid_coor_y;
        atomicAdd(&output_occupy[output_idx], 1);
    }
}



void bev_occupy_gpu_launcher(int batch_size, int input_point_num,
                             int output_w, int output_l, float resolution,
                             const float* input_coors,
                             const int* input_num_list,
                             int* input_accu_list,
                             int* output_occupy) {
    if (batch_size*input_point_num <=0) {
        printf("BevOccupyOp ERROR: Invalid CUDA input dimensions.\n");
        return;
    }

    int blockSize;      // The launch configurator returned block size
    int minGridSize;    // The minimum grid size needed to achieve the maximum occupancy for a full device launch
    int gridSize;       // The actual grid size needed, based on input size


    hipOccupancyMaxPotentialBlockSize(&minGridSize, &blockSize, bev_occupy_gpu_kernel, 0, input_point_num);
    gridSize = (input_point_num + blockSize - 1) / blockSize;
    bev_occupy_gpu_kernel<<<gridSize, blockSize>>>(batch_size, input_point_num,
                                                   output_w, output_l, resolution,
                                                   input_coors,
                                                   input_num_list,
                                                   input_accu_list,
                                                   output_occupy);
}


	.text
	.file	"bev_occupy.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z36__device_stub__bev_occupy_gpu_kerneliiiifPKfPKiPiS3_ # -- Begin function _Z36__device_stub__bev_occupy_gpu_kerneliiiifPKfPKiPiS3_
	.type	_Z36__device_stub__bev_occupy_gpu_kerneliiiifPKfPKiPiS3_,@function
_Z36__device_stub__bev_occupy_gpu_kerneliiiifPKfPKiPiS3_: # @_Z36__device_stub__bev_occupy_gpu_kerneliiiifPKfPKiPiS3_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	28(%rsp), %rax
	movl	%edi, (%rax)
	leaq	24(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	20(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	16(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	12(%rsp), %rcx
	movss	%xmm0, (%rcx)
	leaq	56(%rsp), %r10
	movq	%r8, (%r10)
	leaq	48(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r10, 40(%rbx)
	movq	%r8, 48(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z21bev_occupy_gpu_kerneliiiifPKfPKiPiS3_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z36__device_stub__bev_occupy_gpu_kerneliiiifPKfPKiPiS3_, .Lfunc_end0-_Z36__device_stub__bev_occupy_gpu_kerneliiiifPKfPKiPiS3_
	.cfi_endproc
                                        # -- End function
	.globl	_Z23bev_occupy_gpu_launcheriiiifPKfPKiPiS3_ # -- Begin function _Z23bev_occupy_gpu_launcheriiiifPKfPKiPiS3_
	.type	_Z23bev_occupy_gpu_launcheriiiifPKfPKiPiS3_,@function
_Z23bev_occupy_gpu_launcheriiiifPKfPKiPiS3_: # @_Z23bev_occupy_gpu_launcheriiiifPKfPKiPiS3_
	.cfi_startproc
# %bb.0:
	movl	%esi, %eax
	imull	%edi, %eax
	testl	%eax, %eax
	jle	.LBB1_4
# %bb.1:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r8, %r14
	movl	%ecx, %ebp
	movl	%edx, %r15d
	movl	%esi, %r12d
	movl	%edi, %r13d
	movss	%xmm0, 4(%rsp)                  # 4-byte Spill
	movq	%r9, 24(%rsp)                   # 8-byte Spill
	movq	104(%rsp), %rax
	movq	%rax, 8(%rsp)                   # 8-byte Spill
	movq	96(%rsp), %rax
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	leaq	32(%rsp), %rdi
	leaq	36(%rsp), %rbx
	movl	$_Z21bev_occupy_gpu_kerneliiiifPKfPKiPiS3_, %edx
	movq	%rbx, %rsi
	xorl	%ecx, %ecx
	movl	%r12d, %r8d
	callq	hipOccupancyMaxPotentialBlockSize
	movl	(%rbx), %ecx
	leal	(%r12,%rcx), %eax
	decl	%eax
	cltd
	idivl	%ecx
                                        # kill: def $eax killed $eax def $rax
	btsq	$32, %rax
	btsq	$32, %rcx
	movq	%rax, %rdi
	movl	$1, %esi
	movq	%rcx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_3
# %bb.2:
	movl	%r13d, %edi
	movl	%r12d, %esi
	movl	%r15d, %edx
	movl	%ebp, %ecx
	movss	4(%rsp), %xmm0                  # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movq	%r14, %r8
	movq	24(%rsp), %r9                   # 8-byte Reload
	pushq	8(%rsp)                         # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	24(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	callq	_Z36__device_stub__bev_occupy_gpu_kerneliiiifPKfPKiPiS3_
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
.LBB1_3:
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB1_4:
	.cfi_restore %rbx
	.cfi_restore %rbp
	.cfi_restore %r12
	.cfi_restore %r13
	.cfi_restore %r14
	.cfi_restore %r15
	movl	$.Lstr, %edi
	jmp	puts@PLT                        # TAILCALL
.Lfunc_end1:
	.size	_Z23bev_occupy_gpu_launcheriiiifPKfPKiPiS3_, .Lfunc_end1-_Z23bev_occupy_gpu_launcheriiiifPKfPKiPiS3_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z21bev_occupy_gpu_kerneliiiifPKfPKiPiS3_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z21bev_occupy_gpu_kerneliiiifPKfPKiPiS3_,@object # @_Z21bev_occupy_gpu_kerneliiiifPKfPKiPiS3_
	.section	.rodata,"a",@progbits
	.globl	_Z21bev_occupy_gpu_kerneliiiifPKfPKiPiS3_
	.p2align	3, 0x0
_Z21bev_occupy_gpu_kerneliiiifPKfPKiPiS3_:
	.quad	_Z36__device_stub__bev_occupy_gpu_kerneliiiifPKfPKiPiS3_
	.size	_Z21bev_occupy_gpu_kerneliiiifPKfPKiPiS3_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z21bev_occupy_gpu_kerneliiiifPKfPKiPiS3_"
	.size	.L__unnamed_1, 42

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"BevOccupyOp ERROR: Invalid CUDA input dimensions."
	.size	.Lstr, 50

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z36__device_stub__bev_occupy_gpu_kerneliiiifPKfPKiPiS3_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z21bev_occupy_gpu_kerneliiiifPKfPKiPiS3_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z21bev_occupy_gpu_kerneliiiifPKfPKiPiS3_ ; -- Begin function _Z21bev_occupy_gpu_kerneliiiifPKfPKiPiS3_
	.globl	_Z21bev_occupy_gpu_kerneliiiifPKfPKiPiS3_
	.p2align	8
	.type	_Z21bev_occupy_gpu_kerneliiiifPKfPKiPiS3_,@function
_Z21bev_occupy_gpu_kerneliiiifPKfPKiPiS3_: ; @_Z21bev_occupy_gpu_kerneliiiifPKfPKiPiS3_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x44
	s_load_b128 s[4:7], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s5, v2
	s_cbranch_execz .LBB0_10
; %bb.1:
	s_load_b64 s[2:3], s[0:1], 0x18
	v_lshl_add_u32 v0, v2, 1, v2
	v_mov_b32_e32 v3, 0
	s_add_i32 s8, s4, -1
	s_cmp_lt_i32 s4, 2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_load_b64 v[0:1], v[0:1], off
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x28
	s_cbranch_scc1 .LBB0_9
; %bb.2:                                ; %.lr.ph.i.preheader
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_mov_b32 s4, 0
	s_mov_b32 s9, 0
.LBB0_3:                                ; %.lr.ph.i
                                        ; =>This Inner Loop Header: Depth=1
	s_add_u32 s10, s0, -4
	s_addc_u32 s11, s1, -1
	s_load_b32 s11, s[10:11], 0x0
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e64 s10, s11, v2
	v_cmp_le_i32_e32 vcc_lo, s11, v2
	s_and_saveexec_b32 s11, vcc_lo
	s_cbranch_execz .LBB0_5
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=1
	s_load_b32 s12, s[0:1], 0x0
	s_and_not1_b32 s10, s10, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmp_le_i32_e32 vcc_lo, s12, v2
	s_and_b32 s12, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s10, s10, s12
.LBB0_5:                                ; %Flow
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	v_mov_b32_e32 v3, s9
	s_mov_b32 s12, -1
	s_and_saveexec_b32 s11, s10
; %bb.6:                                ;   in Loop: Header=BB0_3 Depth=1
	s_add_i32 s9, s9, 1
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_cmp_eq_u32 s8, s9
	v_mov_b32_e32 v3, s8
	s_cselect_b32 s10, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_not1_b32 s12, s10, exec_lo
; %bb.7:                                ; %Flow48
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s10, exec_lo, s12
	s_or_b32 s4, s10, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB0_3
; %bb.8:                                ; %Flow49
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_9:                                ; %_Z12get_batch_idPiii.exit
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_div_scale_f32 v2, null, s5, s5, v0
	v_div_scale_f32 v5, null, s5, s5, v1
	v_div_scale_f32 v10, s0, v1, s5, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v4, v2
	v_rcp_f32_e32 v6, v5
	v_div_scale_f32 v8, vcc_lo, v0, s5, v0
	v_min_i32_e32 v3, s8, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v7, -v2, v4, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v7, v4
	v_fma_f32 v7, -v5, v6, 1.0
	v_fmac_f32_e32 v6, v7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v11, v10, v6
	v_mul_f32_e32 v9, v8, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v7, -v2, v9, v8
	v_fmac_f32_e32 v9, v7, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v7, -v5, v11, v10
	v_fma_f32 v2, -v2, v9, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v11, v7, v6
	v_div_fmas_f32 v2, v2, v4, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v4, -v5, v11, v10
	s_mov_b32 vcc_lo, s0
	v_div_fixup_f32 v0, v2, s5, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v2, v4, v6, v11
	v_floor_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v1, v2, s5, v1
	v_cvt_i32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_floor_f32_e32 v4, v1
	v_mad_u64_u32 v[1:2], null, v3, s6, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_i32_f32_e32 v0, v4
	v_mad_u64_u32 v[2:3], null, v1, s7, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	v_mov_b32_e32 v2, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_atomic_add_u32 v[0:1], v2, off
.LBB0_10:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z21bev_occupy_gpu_kerneliiiifPKfPKiPiS3_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z21bev_occupy_gpu_kerneliiiifPKfPKiPiS3_, .Lfunc_end0-_Z21bev_occupy_gpu_kerneliiiifPKfPKiPiS3_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 620
; NumSgprs: 18
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z21bev_occupy_gpu_kerneliiiifPKfPKiPiS3_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z21bev_occupy_gpu_kerneliiiifPKfPKiPiS3_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
