#include <bits/stdc++.h>
#include <cuda_runtime.h>

using namespace std;

void initialize(int *A, int N) {
    for (int i = 0; i < N; i++)
        A[i] = (rand()%N + 1);
}

__device__ void swap(int *A, int i, int j) {
    int temp = A[i];
    A[i] = A[j];
    A[j] = temp;
}

__device__ void cuda_merge(int start, int end, int dir, int *A) {
    int length = end-start+1;
    for (int j = length/2; j > 0; j = j/2) {
        for (int i = start; i+j < start+length; i++)
            if (dir == (A[i] > A[i+j]))
                swap(A, i, i+j);
    }
}

__global__ void cuda_sort(int *A, int length) {    
    int start = blockIdx.x*length;
    if ((start/length)%2 == 0)
        cuda_merge(start, start+length-1, 1, A);
    else
        cuda_merge(start, start+length-1, 0, A);
}

void bitonic_sort(int start, int end, int *A) {
    int length = end-start+1;
    for (int j = 2; j <= length; j = j*2)
        cuda_sort<<<length/j, 1>>>(A, j);
}

int main(void) {

    int N = 6, *A, *d_A;
    A = (int *)malloc(sizeof(int)*(1 << N));
    cudaMalloc((void **)&d_A, sizeof(int)*(1 << N));
    initialize(A, (1 << N));

    cudaMemcpy(d_A, A, sizeof(int)*(1 << N), cudaMemcpyHostToDevice);
    bitonic_sort(0, (1 << N)-1, d_A);
    cudaMemcpy(A, d_A, sizeof(int)*(1 << N), cudaMemcpyDeviceToHost);

    for (int i = 0; i < (1 << N); i++)
        printf("%d ", A[i]);
    printf("\n");

    free(A); cudaFree(d_A);
    return 0;
}
	.file	"tmpxft_0022367f_00000000-6_problem-3c.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB10832:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE10832:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z10initializePii
	.type	_Z10initializePii, @function
_Z10initializePii:
.LFB10825:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movq	%rdi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	xorl	%ebp, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	movl	%esi, %ebx
.L3:
	cmpl	%ebp, %ebx
	jle	.L7
	call	rand@PLT
	cltd
	idivl	%ebx
	incl	%edx
	movl	%edx, (%r12,%rbp,4)
	incq	%rbp
	jmp	.L3
.L7:
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE10825:
	.size	_Z10initializePii, .-_Z10initializePii
	.globl	_Z4swapPiii
	.type	_Z4swapPiii, @function
_Z4swapPiii:
.LFB10826:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE10826:
	.size	_Z4swapPiii, .-_Z4swapPiii
	.globl	_Z10cuda_mergeiiiPi
	.type	_Z10cuda_mergeiiiPi, @function
_Z10cuda_mergeiiiPi:
.LFB10827:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE10827:
	.size	_Z10cuda_mergeiiiPi, .-_Z10cuda_mergeiiiPi
	.globl	_Z29__device_stub__Z9cuda_sortPiiPii
	.type	_Z29__device_stub__Z9cuda_sortPiiPii, @function
_Z29__device_stub__Z9cuda_sortPiiPii:
.LFB10854:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movl	%esi, 4(%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z9cuda_sortPii(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L12:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE10854:
	.size	_Z29__device_stub__Z9cuda_sortPiiPii, .-_Z29__device_stub__Z9cuda_sortPiiPii
	.globl	_Z9cuda_sortPii
	.type	_Z9cuda_sortPii, @function
_Z9cuda_sortPii:
.LFB10855:
	.cfi_startproc
	endbr64
	jmp	_Z29__device_stub__Z9cuda_sortPiiPii
	.cfi_endproc
.LFE10855:
	.size	_Z9cuda_sortPii, .-_Z9cuda_sortPii
	.globl	_Z12bitonic_sortiiPi
	.type	_Z12bitonic_sortiiPi, @function
_Z12bitonic_sortiiPi:
.LFB10828:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	subl	%edi, %esi
	movabsq	$4294967297, %r13
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movq	%rdx, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movl	$2, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	leal	1(%rsi), %ebx
	subq	$40, %rsp
	.cfi_def_cfa_offset 80
.L18:
	cmpl	%ebx, %ebp
	jg	.L22
	movl	%ebx, %eax
	movq	%r13, 12(%rsp)
	movl	16(%rsp), %esi
	xorl	%r9d, %r9d
	cltd
	xorl	%r8d, %r8d
	movl	$1, %ecx
	idivl	%ebp
	movq	%r13, %rdx
	movl	%eax, 8(%rsp)
	movq	8(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	movl	%ebp, %esi
	movq	%r12, %rdi
	call	_Z29__device_stub__Z9cuda_sortPiiPii
.L19:
	addl	%ebp, %ebp
	jmp	.L18
.L22:
	addq	$40, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE10828:
	.size	_Z12bitonic_sortiiPi, .-_Z12bitonic_sortiiPi
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"%d "
.LC1:
	.string	"\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB10829:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$256, %edi
	leaq	.LC0(%rip), %r12
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	xorl	%ebp, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$16, %rsp
	.cfi_def_cfa_offset 48
	movq	%fs:40, %rax
	movq	%rax, 8(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movq	%rsp, %rdi
	movl	$256, %esi
	movq	%rax, %rbx
	call	cudaMalloc@PLT
	movl	$64, %esi
	movq	%rbx, %rdi
	call	_Z10initializePii
	movq	(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$256, %edx
	call	cudaMemcpy@PLT
	movq	(%rsp), %rdx
	movl	$63, %esi
	xorl	%edi, %edi
	call	_Z12bitonic_sortiiPi
	movq	(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	movl	$256, %edx
	call	cudaMemcpy@PLT
.L24:
	movl	(%rbx,%rbp,4), %edx
	movq	%r12, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%rbp
	call	__printf_chk@PLT
	cmpq	$64, %rbp
	jne	.L24
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rax
	subq	%fs:40, %rax
	je	.L25
	call	__stack_chk_fail@PLT
.L25:
	addq	$16, %rsp
	.cfi_def_cfa_offset 32
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE10829:
	.size	main, .-main
	.section	.rodata.str1.1
.LC2:
	.string	"_Z9cuda_sortPii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB10857:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z9cuda_sortPii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE10857:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <bits/stdc++.h>
#include <hip/hip_runtime.h>

using namespace std;

void initialize(int *A, int N) {
    for (int i = 0; i < N; i++)
        A[i] = (rand()%N + 1);
}

__device__ void swap(int *A, int i, int j) {
    int temp = A[i];
    A[i] = A[j];
    A[j] = temp;
}

__device__ void cuda_merge(int start, int end, int dir, int *A) {
    int length = end-start+1;
    for (int j = length/2; j > 0; j = j/2) {
        for (int i = start; i+j < start+length; i++)
            if (dir == (A[i] > A[i+j]))
                swap(A, i, i+j);
    }
}

__global__ void cuda_sort(int *A, int length) {    
    int start = blockIdx.x*length;
    if ((start/length)%2 == 0)
        cuda_merge(start, start+length-1, 1, A);
    else
        cuda_merge(start, start+length-1, 0, A);
}

void bitonic_sort(int start, int end, int *A) {
    int length = end-start+1;
    for (int j = 2; j <= length; j = j*2)
        cuda_sort<<<length/j, 1>>>(A, j);
}

int main(void) {

    int N = 6, *A, *d_A;
    A = (int *)malloc(sizeof(int)*(1 << N));
    hipMalloc((void **)&d_A, sizeof(int)*(1 << N));
    initialize(A, (1 << N));

    hipMemcpy(d_A, A, sizeof(int)*(1 << N), hipMemcpyHostToDevice);
    bitonic_sort(0, (1 << N)-1, d_A);
    hipMemcpy(A, d_A, sizeof(int)*(1 << N), hipMemcpyDeviceToHost);

    for (int i = 0; i < (1 << N); i++)
        printf("%d ", A[i]);
    printf("\n");

    free(A); hipFree(d_A);
    return 0;
}
	.text
	.file	"problem-3c.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z10initializePii               # -- Begin function _Z10initializePii
	.type	_Z10initializePii,@function
_Z10initializePii:                      # @_Z10initializePii
	.cfi_startproc
# %bb.0:
	testl	%esi, %esi
	jle	.LBB0_4
# %bb.1:                                # %.lr.ph.preheader
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	%esi, %ebx
	movq	%rdi, %r14
	movl	%esi, %r15d
	xorl	%r12d, %r12d
.LBB0_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	cltd
	idivl	%ebx
	incl	%edx
	movl	%edx, (%r14,%r12,4)
	incq	%r12
	cmpq	%r12, %r15
	jne	.LBB0_2
# %bb.3:
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	.cfi_restore %r12
	.cfi_restore %r14
	.cfi_restore %r15
.LBB0_4:                                # %._crit_edge
	retq
.Lfunc_end0:
	.size	_Z10initializePii, .Lfunc_end0-_Z10initializePii
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__cuda_sortPii # -- Begin function _Z24__device_stub__cuda_sortPii
	.type	_Z24__device_stub__cuda_sortPii,@function
_Z24__device_stub__cuda_sortPii:        # @_Z24__device_stub__cuda_sortPii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9cuda_sortPii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z24__device_stub__cuda_sortPii, .Lfunc_end1-_Z24__device_stub__cuda_sortPii
	.cfi_endproc
                                        # -- End function
	.globl	_Z12bitonic_sortiiPi            # -- Begin function _Z12bitonic_sortiiPi
	.type	_Z12bitonic_sortiiPi,@function
_Z12bitonic_sortiiPi:                   # @_Z12bitonic_sortiiPi
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%esi, %ebp
	subl	%edi, %ebp
	testl	%ebp, %ebp
	jle	.LBB2_5
# %bb.1:                                # %.lr.ph.preheader
	movq	%rdx, %rbx
	incl	%ebp
	movl	$2, %r14d
	movabsq	$4294967296, %r12               # imm = 0x100000000
	leaq	1(%r12), %r15
.LBB2_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	%ebp, %eax
	xorl	%edx, %edx
	divl	%r14d
                                        # kill: def $eax killed $eax def $rax
	orq	%r12, %rax
	movq	%rax, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_4
# %bb.3:                                #   in Loop: Header=BB2_2 Depth=1
	movq	%rbx, %rdi
	movl	%r14d, %esi
	callq	_Z24__device_stub__cuda_sortPii
.LBB2_4:                                #   in Loop: Header=BB2_2 Depth=1
	addl	%r14d, %r14d
	cmpl	%ebp, %r14d
	jle	.LBB2_2
.LBB2_5:                                # %._crit_edge
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z12bitonic_sortiiPi, .Lfunc_end2-_Z12bitonic_sortiiPi
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	pushq	%rax
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movl	$256, %edi                      # imm = 0x100
	callq	malloc
	movq	%rax, %rbx
	movq	%rsp, %rdi
	movl	$256, %esi                      # imm = 0x100
	callq	hipMalloc
	xorl	%r14d, %r14d
.LBB3_1:                                # %.lr.ph.i
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
                                        # kill: def $eax killed $eax def $rax
	leal	63(%rax), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	andl	$-64, %ecx
	negl	%ecx
	addl	%ecx, %eax
	incl	%eax
	movl	%eax, (%rbx,%r14,4)
	incq	%r14
	cmpq	$64, %r14
	jne	.LBB3_1
# %bb.2:                                # %_Z10initializePii.exit
	movq	(%rsp), %rdi
	movl	$256, %edx                      # imm = 0x100
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rsp), %rdx
	xorl	%edi, %edi
	movl	$63, %esi
	callq	_Z12bitonic_sortiiPi
	movq	(%rsp), %rsi
	movl	$256, %edx                      # imm = 0x100
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	xorl	%r14d, %r14d
.LBB3_3:                                # =>This Inner Loop Header: Depth=1
	movl	(%rbx,%r14,4), %esi
	movl	$.L.str, %edi
	xorl	%eax, %eax
	callq	printf
	incq	%r14
	cmpq	$64, %r14
	jne	.LBB3_3
# %bb.4:
	movl	$10, %edi
	callq	putchar@PLT
	movq	%rbx, %rdi
	callq	free
	movq	(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9cuda_sortPii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z9cuda_sortPii,@object         # @_Z9cuda_sortPii
	.section	.rodata,"a",@progbits
	.globl	_Z9cuda_sortPii
	.p2align	3, 0x0
_Z9cuda_sortPii:
	.quad	_Z24__device_stub__cuda_sortPii
	.size	_Z9cuda_sortPii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"%d "
	.size	.L.str, 4

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z9cuda_sortPii"
	.size	.L__unnamed_1, 16

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z24__device_stub__cuda_sortPii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z9cuda_sortPii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z9cuda_sortPii         ; -- Begin function _Z9cuda_sortPii
	.globl	_Z9cuda_sortPii
	.p2align	8
	.type	_Z9cuda_sortPii,@function
_Z9cuda_sortPii:                        ; @_Z9cuda_sortPii
; %bb.0:
	s_load_b32 s14, s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s4, s14, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s14, s4
	s_xor_b32 s5, s2, s4
	s_mul_i32 s2, s15, s14
	v_cvt_f32_u32_e32 v0, s5
	s_sub_i32 s7, 0, s5
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s8, s2, s3
	v_rcp_iflag_f32_e32 v0, v0
	s_xor_b32 s8, s8, s3
	s_xor_b32 s9, s3, s4
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_readfirstlane_b32 s6, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s7, s7, s6
	s_mul_hi_u32 s7, s6, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s6, s6, s7
	s_mul_hi_u32 s6, s8, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s7, s6, s5
	s_sub_i32 s4, s8, s7
	s_add_i32 s7, s6, 1
	s_sub_i32 s8, s4, s5
	s_cmp_ge_u32 s4, s5
	s_cselect_b32 s6, s7, s6
	s_cselect_b32 s4, s8, s4
	s_add_i32 s7, s6, 1
	s_cmp_ge_u32 s4, s5
	s_cselect_b32 s4, s7, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_xor_b32 s6, s4, s9
	s_load_b64 s[4:5], s[0:1], 0x0
	s_sub_i32 s0, s6, s9
	s_bitcmp1_b32 s0, 0
	s_cselect_b32 s0, -1, 0
	s_add_i32 s15, s2, s14
	s_cmp_gt_i32 s14, 1
	s_cselect_b32 s1, -1, 0
	s_and_b32 vcc_lo, exec_lo, s0
	v_cndmask_b32_e64 v0, 0, 1, s1
	s_mov_b32 s1, -1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e64 s0, 1, v0
	s_cbranch_vccz .LBB0_10
; %bb.1:
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_9
; %bb.2:                                ; %.preheader.i13.preheader
	s_lshl_b64 s[6:7], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s6, s4, s6
	s_addc_u32 s7, s5, s7
	s_mov_b32 s1, s14
.LBB0_3:                                ; %.preheader.i13
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_5 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshr_b32 s16, s1, 1
	s_cmp_ge_i32 s16, s14
	s_cbranch_scc1 .LBB0_8
; %bb.4:                                ; %.lr.ph.i18.preheader
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_add_i32 s8, s16, s2
	s_mov_b64 s[10:11], s[6:7]
.LBB0_5:                                ; %.lr.ph.i18
                                        ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_ashr_i32 s9, s8, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[12:13], s[8:9], 2
	s_add_u32 s12, s4, s12
	s_addc_u32 s13, s5, s13
	s_clause 0x1
	global_load_b32 v1, v0, s[10:11]
	global_load_b32 v2, v0, s[12:13]
	s_waitcnt vmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, v1, v2
	s_cbranch_vccnz .LBB0_7
; %bb.6:                                ;   in Loop: Header=BB0_5 Depth=2
	s_clause 0x1
	global_store_b32 v0, v2, s[10:11]
	global_store_b32 v0, v1, s[12:13]
.LBB0_7:                                ;   in Loop: Header=BB0_5 Depth=2
	s_add_i32 s8, s8, 1
	s_add_u32 s10, s10, 4
	s_addc_u32 s11, s11, 0
	s_cmp_ge_i32 s8, s15
	s_cbranch_scc0 .LBB0_5
.LBB0_8:                                ; %._crit_edge.i16
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_cmp_lt_u32 s1, 4
	s_mov_b32 s1, s16
	s_cbranch_scc0 .LBB0_3
.LBB0_9:                                ; %Flow38
	s_mov_b32 s1, 0
.LBB0_10:                               ; %Flow43
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_19
; %bb.11:
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_19
; %bb.12:                               ; %.preheader.i.preheader
	s_lshl_b64 s[0:1], s[2:3], 2
	v_mov_b32_e32 v0, 0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s4, s0
	s_addc_u32 s1, s5, s1
	s_mov_b32 s3, s14
.LBB0_13:                               ; %.preheader.i
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_15 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshr_b32 s12, s3, 1
	s_cmp_ge_i32 s12, s14
	s_cbranch_scc1 .LBB0_18
; %bb.14:                               ; %.lr.ph.i.preheader
                                        ;   in Loop: Header=BB0_13 Depth=1
	s_add_i32 s6, s12, s2
	s_mov_b64 s[8:9], s[0:1]
.LBB0_15:                               ; %.lr.ph.i
                                        ;   Parent Loop BB0_13 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_ashr_i32 s7, s6, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[10:11], s[6:7], 2
	s_add_u32 s10, s4, s10
	s_addc_u32 s11, s5, s11
	s_clause 0x1
	global_load_b32 v1, v0, s[8:9]
	global_load_b32 v2, v0, s[10:11]
	s_waitcnt vmcnt(0)
	v_cmp_le_i32_e32 vcc_lo, v1, v2
	s_cbranch_vccnz .LBB0_17
; %bb.16:                               ;   in Loop: Header=BB0_15 Depth=2
	s_clause 0x1
	global_store_b32 v0, v2, s[8:9]
	global_store_b32 v0, v1, s[10:11]
.LBB0_17:                               ;   in Loop: Header=BB0_15 Depth=2
	s_add_i32 s6, s6, 1
	s_add_u32 s8, s8, 4
	s_addc_u32 s9, s9, 0
	s_cmp_ge_i32 s6, s15
	s_cbranch_scc0 .LBB0_15
.LBB0_18:                               ; %._crit_edge.i
                                        ;   in Loop: Header=BB0_13 Depth=1
	s_cmp_lt_u32 s3, 4
	s_mov_b32 s3, s12
	s_cbranch_scc0 .LBB0_13
.LBB0_19:                               ; %_Z10cuda_mergeiiiPi.exit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9cuda_sortPii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 12
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 3
		.amdhsa_next_free_sgpr 17
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z9cuda_sortPii, .Lfunc_end0-_Z9cuda_sortPii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 584
; NumSgprs: 19
; NumVgprs: 3
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 19
; NumVGPRsForWavesPerEU: 3
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 12
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9cuda_sortPii
    .private_segment_fixed_size: 0
    .sgpr_count:     19
    .sgpr_spill_count: 0
    .symbol:         _Z9cuda_sortPii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     3
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
