/*MIT License

Copyright (c) 2019 Xavier Martinez

Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/

#define NBTHREADS 256
#define EMPTYCELL INT_MAX-1
#define PROBERADIUS (1.4f)
#define EPSILON (0.001f)

#include <thrust/binary_search.h>

#include "operators.cu"
#include "MarchingCubes.cu"



struct compare_int2 {
    __host__ __device__ __forceinline__ bool operator()(int2 a, int2 b) {return a.x < b.x;}
};
struct compare_int {
    __host__ __device__ __forceinline__ bool operator()(int a, int b) {return a < b;}
};
struct compare_float3 {
    __device__ __host__ bool operator()(float3 a, float3 b) {
        if      (a.x <= b.x && a.y <= b.y && a.z < b.z) return true;
        else if (a.x <= b.x && a.y < b.y) return true;
        else if (a.x < b.x) return true;
        else return false;
    }
};
struct sort_float3 {
    __host__ __device__
    bool operator()(const float3 &a, const float3 &b) const {

        if      (a.x <= b.x && a.y <= b.y && a.z < b.z) return true;
        else if (a.x <= b.x && a.y < b.y) return true;
        else if (a.x < b.x) return true;
        else return false;
    }
};

struct compare_int3 {
    __host__ __device__ bool operator()(int3 a, int3 b) {
        if      (a.x <= b.x && a.y <= b.y && a.z < b.z) return true;
        else if (a.x <= b.x && a.y < b.y) return true;
        else if (a.x < b.x) return true;
        else return false;
    }
};
struct samefloat3 {
    __host__ __device__ bool operator()(float3 a, float3 b) {
        if (abs(a.x - b.x) > EPSILON)
            return false;
        if (abs(a.y - b.y) > EPSILON)
            return false;
        if (abs(a.z - b.z) > EPSILON)
            return false;

        return true;
    }
};
struct sameint3 {
    __host__ __device__ bool operator()(int3 a, int3 b) {
        if (a.x != b.x)
            return false;
        if (a.y != b.y)
            return false;
        if (a.z != b.z)
            return false;

        return true;
    }
};


template<typename T>
struct lessf3 : public thrust::binary_function<T, T, bool>
{
    __host__ __device__ bool operator()(const T &a, const T &b) const {
        if      (a.x <= b.x && a.y <= b.y && a.z < b.z) return true;
        else if (a.x <= b.x && a.y < b.y) return true;
        else if (a.x < b.x) return true;
        else return false;
    }
};

struct add_uint2 {
    __device__
    uint2 operator()(const uint2& a, const uint2& b) const {
        uint2 r;
        r.x = a.x + b.x;
        r.y = a.y + b.y;
        return r;
    }
};

struct is_notempty
{
    __host__ __device__
    bool operator()(const int &x) const
    {
        return x != EMPTYCELL;
    }
};


__global__ void memsetCudaFloat(float *data, float val, int N){
    unsigned int index = blockDim.x * blockIdx.x + threadIdx.x;
    
    if (index >= N) {
        return;
    }
    data[index] = val;
}
__global__ void memsetCudaInt(int *data, int val, int N) {
    unsigned int index = blockDim.x * blockIdx.x + threadIdx.x;
    
    if (index >= N) {
        return;
    }
    data[index] = val;
}
__global__ void memsetCudaInt2(int2 *data, int2 val, int N) {
    unsigned int index = blockDim.x * blockIdx.x + threadIdx.x;
    
    if (index >= N) {
        return;
    }
    data[index] = val;
}
__global__ void memsetCudaUInt2(uint2 *data, uint2 val, int N) {
    unsigned int index = blockDim.x * blockIdx.x + threadIdx.x;
    
    if (index >= N) {
        return;
    }
    data[index] = val;
}
__host__ __device__ int3 spaceToGrid(float3 pos3D, float3 originGrid, float dx) {
    float3 tmp = ((pos3D - originGrid) / dx);
    return make_int3(tmp.x, tmp.y, tmp.z);

}
__host__ __device__ float3 gridToSpace(int3 cellPos, float3 originGrid, float dx) {
    return (originGrid + (make_float3(cellPos.x, cellPos.y, cellPos.z) * dx) );
    //return originGrid + (convert_float3(cellPos) * dx) + (dx / 2.0f);
}

__host__ __device__ int flatten3DTo1D(int3 id3d, int3 gridDim) {
    return (gridDim.y * gridDim.z * id3d.x) + (gridDim.z * id3d.y) + id3d.z;
}
// __host__ __device__ int flatten3DTo1D(int3 id3d, int3 gridDim) {
//     // return id3d.x + gridDim.x * (id3d.y + gridDim.z * id3d.z);
//     return id3d.x + id3d.y * gridDim.x + id3d.z * gridDim.x * gridDim.y;
// }


__host__ __device__ int3 unflatten1DTo3D(int index, int3 gridDim) {
    int3 res;
    // res.x = index % gridDim.x;
    // res.y = (index / gridDim.x) % gridDim.y;
    // res.z = index / (gridDim.x * gridDim.y);
    res.x = index / (gridDim.y * gridDim.z); //Note the integer division . This is x
    res.y = (index - res.x * gridDim.y * gridDim.z) / gridDim.z; //This is y
    res.z = index - res.x * gridDim.y * gridDim.z - res.y * gridDim.z; //This is z
    return res;
}

inline __host__ __device__ float fast_distance(float3 p1, float3 p2) {
    float x = (p1.x - p2.x) * (p1.x - p2.x);
    float y = (p1.y - p2.y) * (p1.y - p2.y);
    float z = (p1.z - p2.z) * (p1.z - p2.z);

    return sqrt( x + y + z);
}
inline __host__ __device__ float sqr_distance(float3 p1, float3 p2) {
    float x = (p1.x - p2.x) * (p1.x - p2.x);
    float y = (p1.y - p2.y) * (p1.y - p2.y);
    float z = (p1.z - p2.z) * (p1.z - p2.z);

    return x + y + z;
}



inline __host__ __device__ float3 clamp(float3 f, float a, float b)
{
    return make_float3(max(a, min(f.x, b)),
                       max(a, min(f.y, b)),
                       max(a, min(f.z, b))
                      );
}
inline __host__ __device__ int3 clamp(int3 f, int a, int b)
{
    return make_int3(max(a, min(f.x, b)),
                     max(a, min(f.y, b)),
                     max(a, min(f.z, b))
                    );
}
inline __host__ __device__ int clamp(int f, int a, int b)
{
    return max(a, min(f, b));
}

// inline __device__ int lessThan(float x, float y) {
//     return max(sign(y - x), 0);
// }

// calculate cell address as the hash value for each atom
__global__ void hashAtoms(unsigned int natoms,
                          float4*  xyzr,
                          int3 gridDim,
                          float4 originGridDDx,
                          int2 * atomHashIndex,
                          unsigned natomsnextPow2) {


    unsigned int index = blockDim.x * blockIdx.x + threadIdx.x;

    if (index >= natomsnextPow2)
        return;

    if (index >= natoms) {
        atomHashIndex[index].x = INT_MAX;
        atomHashIndex[index].y = INT_MAX;
        return;
    }

    float4 atom = xyzr[index];// read atom coordinate and radius
    float3 pos = make_float3(atom.x, atom.y, atom.z);
    // compute cell index, clamped to fall within grid bounds
    float3 originGrid = make_float3(originGridDDx.x, originGridDDx.y, originGridDDx.z);
    float dx = originGridDDx.w;
    int3 cell = spaceToGrid(pos, originGrid, dx);

    int hash = flatten3DTo1D(cell, gridDim);

    atomHashIndex[index].x = hash;// atoms hashed to cell address
    atomHashIndex[index].y = index; // original atom index

}


//https://github.com/FROL256/opencl_bitonic_sort_by_key/blob/master/bitonic_sort_gpu.h

inline __device__ int getKey(int2 v) { return v.x; }
inline __device__ int getVal(int2 v) { return v.y; }

inline __device__ bool compare(int2 a, int2 b) { return getKey(a) < getKey(b); }

__global__ void bitonic_pass_kernel(int2* theArray, int stage, int passOfStage, int a_invertModeOn)
{
    int j = blockDim.x * blockIdx.x + threadIdx.x;

    const int r     = 1 << (passOfStage);
    const int lmask = r - 1;

    const int left  = ((j >> passOfStage) << (passOfStage + 1)) + (j & lmask);
    const int right = left + r;

    const int2 a = theArray[left];
    const int2 b = theArray[right];

    const bool cmpRes = compare(a, b);

    const int2 minElem = cmpRes ? a : b;
    const int2 maxElem = cmpRes ? b : a;

    const int oddEven = j >> stage;

    const bool isSwap = (oddEven & 1) & a_invertModeOn;

    const int minId = isSwap ? right : left;
    const int maxId = isSwap ? left  : right;

    theArray[minId] = minElem;
    theArray[maxId] = maxElem;
}


__global__ void bitonic_512( int2* theArray, int stage, int passOfStageBegin, int a_invertModeOn)
{
    int tid = blockDim.x * blockIdx.x + threadIdx.x;
    int lid = threadIdx.x;

    int blockId = (tid / 256);

    __shared__ int2 s_array[512];

    s_array[lid + 0]   = theArray[blockId * 512 + lid + 0];
    s_array[lid + 256] = theArray[blockId * 512 + lid + 256];

    __syncthreads();

    for (int passOfStage = passOfStageBegin; passOfStage >= 0; passOfStage--)
    {
        const int j     = lid;
        const int r     = 1 << (passOfStage);
        const int lmask = r - 1;

        const int left  = ((j >> passOfStage) << (passOfStage + 1)) + (j & lmask);
        const int right = left + r;

        const int2 a = s_array[left];
        const int2 b = s_array[right];

        const bool cmpRes = compare(a, b);

        const int2 minElem = cmpRes ? a : b;
        const int2 maxElem = cmpRes ? b : a;

        const int oddEven = tid >> stage; // (j >> stage)

        const bool isSwap = (oddEven & 1) & a_invertModeOn;

        const int minId = isSwap ? right : left;
        const int maxId = isSwap ? left  : right;

        s_array[minId] = minElem;
        s_array[maxId] = maxElem;

        __syncthreads();
    }

    theArray[blockId * 512 + lid + 0]   = s_array[lid + 0];
    theArray[blockId * 512 + lid + 256] = s_array[lid + 256];

}


__global__ void sortCell(unsigned int natoms, float4 *xyzr, int2 *atomHashIndex,
                         float4 *sorted_xyzr,
                         int2 *cellStartEnd) {

    int hash;
    int id;
    // __local int local_hash[NBTHREADS + 1];
    unsigned int index = blockDim.x * blockIdx.x + threadIdx.x;

    if (index >= natoms)
        return;

    hash = atomHashIndex[index].x;
    id = atomHashIndex[index].y;

    int hashm1;
    if (index != 0)
        hashm1 = atomHashIndex[index - 1].x;
    else
        hashm1 = hash;


    if (index == 0 || hash != hashm1) {
        cellStartEnd[hash].x = index; // set start
        if (index > 0)
            cellStartEnd[hashm1].y = index; // set end
    }

    if (index == natoms - 1) {
        cellStartEnd[hash].y = index + 1; // set end
    }

    // Reorder atoms according to sorted indices
    sorted_xyzr[index] = xyzr[id];

}


inline __host__ __device__ float computeInOrOut(int3 id3DNeigh, int2 *cellStartEnd, float4 *sorted_xyzr, float3 spacePosSES, float dx, int3 gridDimNeighbor) {
    //Loop over neighbors to compute if the cell is:
    // 1) - ouside => result = PROBERADIUS
    // 2) - inside => result = -dx
    // 3) - at the border =>  result = 0.0
    int3 curgridId;
    float result = PROBERADIUS;
    bool nearProbe = false;

// #pragma unroll
    for (int x = -1; x <= 1; x++) {
        curgridId.x = clamp(id3DNeigh.x + x, 0, gridDimNeighbor.x - 1);
// #pragma unroll
        for (int y = -1; y <= 1; y++) {
            curgridId.y = clamp(id3DNeigh.y + y, 0, gridDimNeighbor.x - 1);
// #pragma unroll
            for (int z = -1; z <= 1; z++) {
                curgridId.z = clamp(id3DNeigh.z + z, 0, gridDimNeighbor.x - 1);

                int neighcellhash = flatten3DTo1D(curgridId, gridDimNeighbor);
                int idStart = cellStartEnd[neighcellhash].x;
                int idStop = cellStartEnd[neighcellhash].y;

                if (idStart < EMPTYCELL) {
                    for (int id = idStart; id < idStop; id++) {
                        float4 xyzr = sorted_xyzr[id];
                        float rad = xyzr.w;
                        float3 pos = make_float3(xyzr.x, xyzr.y, xyzr.z);
                        // float d = sqr_distance(pos, spacePosSES);
                        float d = fast_distance(pos, spacePosSES);

                        // minDist = min(d, minDist);
                        // if (d < rad * rad)
                        if (d < rad - dx)
                            return -dx;
                        // if (d < (PROBERADIUS + rad) * (PROBERADIUS + rad))
                        if (d < (PROBERADIUS + rad) )
                            nearProbe = true;
                    }
                }
            }
        }
    }    

    //float result = (1 - nearProbe) * PROBERADIUS;
    if (nearProbe)
        result = 0.0f;
    return result;
}

__global__ void probeIntersection(int * checkFill,
                                  int2 * atomHashIndex,
                                  int3 gridDimNeighbor,
                                  float4 originGridNeighborDDx,
                                  int3 gridDimSES,
                                  int3 sliceGridDimSES,
                                  // int3 smallsliceGridDimSES,
                                  float4 originGridSESDx,
                                  int2 *cellStartEnd,
                                  float4 * sorted_xyzr,
                                  float *gridValues,
                                  int3 offsetGrid,
                                  unsigned int N,
                                  int sliceNb) {

    // Get global position in X direction
    unsigned int i = (threadIdx.x + blockIdx.x * blockDim.x);
    // Get global position in Y direction
    unsigned int j = (threadIdx.y + blockIdx.y * blockDim.y);
    // Get global position in Z direction
    unsigned int k = (threadIdx.z + blockIdx.z * blockDim.z);

    int3 ijk = make_int3(i, j, k);

    if (i >= sliceGridDimSES.x - 1)
        return;
    if (j >= sliceGridDimSES.y - 1)
        return;
    if (k >= sliceGridDimSES.z - 1)
        return;



    int hash = flatten3DTo1D(ijk, sliceGridDimSES);

    // if(hash >= sliceNb)
    //     return;


    int3 ijkOffset = make_int3(i + offsetGrid.x, j + offsetGrid.y, k + offsetGrid.z);
    int hashOffset = flatten3DTo1D(ijkOffset, gridDimSES);

    if (ijkOffset.x >= gridDimSES.x - 1)
        return;
    if (ijkOffset.y >= gridDimSES.y - 1)
        return;
    if (ijkOffset.z >= gridDimSES.z - 1)
        return;


    float3 originGridNeighbor = make_float3(originGridNeighborDDx.x, originGridNeighborDDx.y, originGridNeighborDDx.z);
    float dxNeighbor = originGridNeighborDDx.w;
    float dxSES = originGridSESDx.w;

    float3 spacePos3DCellSES = gridToSpace(ijkOffset, originGridNeighbor, dxSES);

    // id of the current cell in the neighbor grid
    int3 gridPos3DCellNeighbor = spaceToGrid(spacePos3DCellSES, originGridNeighbor, dxNeighbor);


    //Loop over neighbors to compute if the cell is:
    // 1) - ouside => result = PROBERADIUS
    // 2) - inside => result = -dx
    // 3) - at the border =>  result = 0.0
    float result = computeInOrOut(gridPos3DCellNeighbor, cellStartEnd, sorted_xyzr, spacePos3DCellSES, dxSES, gridDimNeighbor);


    //If should process => record id, if not record a large number
    int fill = EMPTYCELL;

    int range = (int)ceil(PROBERADIUS / dxSES);
    if (abs(result) < EPSILON){
        fill = hash;
        // if(i < range || j < range || k < range || i > smallsliceGridDimSES.x + range || j > smallsliceGridDimSES.y + range || k > smallsliceGridDimSES.z + range){
        //     fill = EMPTYCELL;
        // }
    }

    checkFill[hash] = fill;
    gridValues[hash] = result;

}


__global__ void distanceFieldRefine(int * checkFill, int2 * atomHashIndex, int3 gridDimNeighbor,
                                    float4 originGridNeighborDDx, int3 gridDimSES, int3 sliceGridDimSES,
                                    float4 originGridSESDx, int2 * cellStartEnd, float4 * sorted_xyzr,
                                    float *gridValues, unsigned int totalCells, unsigned int notEmptyCells,
                                    int3 offsetGrid, unsigned int of) {

    int id = (threadIdx.x + blockIdx.x * blockDim.x) + of;


    if (id >= notEmptyCells) {
        return;
    }

    int hash = checkFill[id];

    int3 ijk = unflatten1DTo3D(hash, sliceGridDimSES);

    //From slice to real id in the full size grid
    int3 ijkOffset = make_int3(ijk.x + offsetGrid.x, ijk.y + offsetGrid.y, ijk.z + offsetGrid.z);
    int hashOffset = flatten3DTo1D(ijkOffset, gridDimSES);

    float3 originGridSES = make_float3(originGridSESDx.x, originGridSESDx.y, originGridSESDx.z);

    float dxSES = originGridSESDx.w;

    float3 spacePos3DCellSES = gridToSpace(ijkOffset, originGridSES, dxSES);

    float newresult = -dxSES;

    const int idSESRangeToSearch = (int)ceil(PROBERADIUS / dxSES);
    const float pme = PROBERADIUS - EPSILON;
    float minDist = 100000.0f;

    int3 curgridSESId;

    //Find the closest outside SES cell in the range [-probeRadius, +probeRadius]
// #pragma unroll
    for (int x = -idSESRangeToSearch; x <= idSESRangeToSearch; x++) {

        curgridSESId.x = clamp(ijk.x + x , 0, sliceGridDimSES.x - 1);
// #pragma unroll
        for (int y = -idSESRangeToSearch; y <= idSESRangeToSearch; y++) {
            curgridSESId.y = clamp(ijk.y + y , 0, sliceGridDimSES.y - 1);
// #pragma unroll
            for (int z = -idSESRangeToSearch; z <= idSESRangeToSearch; z++) {
                curgridSESId.z = clamp(ijk.z + z , 0, sliceGridDimSES.z - 1);
                int curgrid1DSESId = flatten3DTo1D(curgridSESId, sliceGridDimSES);

                if (gridValues[curgrid1DSESId] > pme) {//Outside
                    
                    int3 curgrid3DSESIdOffset = make_int3(curgridSESId.x + offsetGrid.x,
                                                        curgridSESId.y + offsetGrid.y,
                                                        curgridSESId.z + offsetGrid.z);

                    float3 spacePosSES = gridToSpace(curgrid3DSESIdOffset, originGridSES, dxSES);
                    //Distance from our current grid cell to the outside grid cell
                    float d = fast_distance(spacePosSES, spacePos3DCellSES);
                    minDist = min(d, minDist);
                }
            }
        }
    }
    if (minDist < 999.0f)
        newresult =  PROBERADIUS - minDist;

    gridValues[hash] = newresult;

}

inline __host__ __device__ int computeClosestAtom(float3 vert, int3 id3DNeigh, int2 *cellStartEnd, float4 *sorted_xyzr, int3 gridDimNeighbor) {


    int closestId = -1;
    float minD = 999999.0f;
    int3 curgridId;
// #pragma unroll
    for (int x = -1; x <= 1; x++) {
        curgridId.x = clamp(id3DNeigh.x + x, 0, gridDimNeighbor.x - 1);
// #pragma unroll
        for (int y = -1; y <= 1; y++) {
            curgridId.y = clamp(id3DNeigh.y + y, 0, gridDimNeighbor.x - 1);
// #pragma unroll
            for (int z = -1; z <= 1; z++) {
                curgridId.z = clamp(id3DNeigh.z + z, 0, gridDimNeighbor.x - 1);

                int neighcellhash = flatten3DTo1D(curgridId, gridDimNeighbor);
                int idStart = cellStartEnd[neighcellhash].x;
                int idStop = cellStartEnd[neighcellhash].y;

                if (idStart < EMPTYCELL) {
                    for (int id = idStart; id < idStop; id++) {
                        float4 xyzr = sorted_xyzr[id];
                        float3 pos = make_float3(xyzr.x, xyzr.y, xyzr.z);
                        // float d = sqr_distance(pos, vert);
                        float d = fast_distance(pos, vert);
                        if(d < minD){
                            minD = d;
                            closestId = id;
                        }
                    }
                }
            }
        }
    }
    return closestId;


}

__global__ void closestAtomPerVertex(int *atomIdPerVert, float3 *vertices, unsigned int Nvert, int3 gridDimNeighbor,
                                    float4 originGridNeighborDDx,
                                    float4 originGridSESDx, int2 * cellStartEnd, float4 * sorted_xyzr) {

    int id = (threadIdx.x + blockIdx.x * blockDim.x);

    if(id >= Nvert)
        return;

    float3 vert = vertices[id];

    float3 originGridNeighbor = make_float3(originGridNeighborDDx.x, originGridNeighborDDx.y, originGridNeighborDDx.z);
    float dxNeighbor = originGridNeighborDDx.w;

    int3 gridPos3DCellNeighbor = spaceToGrid(vert, originGridNeighbor, dxNeighbor);

    atomIdPerVert[id] = computeClosestAtom(vert, gridPos3DCellNeighbor, cellStartEnd, sorted_xyzr, gridDimNeighbor);
}

__global__ void resetGridValuesSlice(const int3 offset, const int rangeSearchRefine, const int3 sliceGridDimSES, float *gridValues){

    // Get global position in X direction
    unsigned int i = (threadIdx.x + blockIdx.x * blockDim.x);
    // Get global position in Y direction
    unsigned int j = (threadIdx.y + blockIdx.y * blockDim.y);
    // Get global position in Z direction
    unsigned int k = (threadIdx.z + blockIdx.z * blockDim.z);

    int3 ijk = make_int3(i, j, k);

    if (i >= sliceGridDimSES.x - 1)
        return;
    if (j >= sliceGridDimSES.y - 1)
        return;
    if (k >= sliceGridDimSES.z - 1)
        return;


    int hash = flatten3DTo1D(ijk, sliceGridDimSES);

    if(i >= sliceGridDimSES.x - rangeSearchRefine)
        gridValues[hash] = PROBERADIUS;
    if(j >= sliceGridDimSES.y - rangeSearchRefine)
        gridValues[hash] = PROBERADIUS;
    if(k >= sliceGridDimSES.z - rangeSearchRefine)
        gridValues[hash] = PROBERADIUS;

    if(offset.x != 0){
        if(i < rangeSearchRefine)
            gridValues[hash] = PROBERADIUS;
    }
    else{
        if(i >= sliceGridDimSES.x - rangeSearchRefine * 2)
            gridValues[hash] = PROBERADIUS;
    }
    if(offset.y != 0){
        if(j < rangeSearchRefine)
            gridValues[hash] = PROBERADIUS;
    }
    else{
        if(j >= sliceGridDimSES.y - rangeSearchRefine * 2)
            gridValues[hash] = PROBERADIUS;
    }
    if(offset.z != 0){
        if(k < rangeSearchRefine)
            gridValues[hash] = PROBERADIUS;
    }
    else{
        if(k >= sliceGridDimSES.z - rangeSearchRefine * 2)
            gridValues[hash] = PROBERADIUS;
    }


}
	.file	"tmpxft_002ca048_00000000-6_Kernels.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.section	.text.nvtxEtiGetModuleFunctionTable_v3,"axG",@progbits,nvtxEtiGetModuleFunctionTable_v3,comdat
	.weak	nvtxEtiGetModuleFunctionTable_v3
	.hidden	nvtxEtiGetModuleFunctionTable_v3
	.type	nvtxEtiGetModuleFunctionTable_v3, @function
nvtxEtiGetModuleFunctionTable_v3:
.LFB6263:
	.cfi_startproc
	endbr64
	decl	%edi
	xorl	%eax, %eax
	cmpl	$5, %edi
	ja	.L1
	leaq	.L4(%rip), %rcx
	movslq	(%rcx,%rdi,4), %rax
	addq	%rcx, %rax
	notrack jmp	*%rax
	.section	.rodata.nvtxEtiGetModuleFunctionTable_v3,"aG",@progbits,nvtxEtiGetModuleFunctionTable_v3,comdat
	.align 4
	.align 4
.L4:
	.long	.L9-.L4
	.long	.L14-.L4
	.long	.L7-.L4
	.long	.L6-.L4
	.long	.L5-.L4
	.long	.L3-.L4
	.section	.text.nvtxEtiGetModuleFunctionTable_v3,"axG",@progbits,nvtxEtiGetModuleFunctionTable_v3,comdat
.L9:
	leaq	560+nvtxGlobals_v3(%rip), %rcx
	jmp	.L18
.L7:
	leaq	776+nvtxGlobals_v3(%rip), %rcx
	movl	$128, %eax
	jmp	.L8
.L6:
	leaq	904+nvtxGlobals_v3(%rip), %rcx
	jmp	.L19
.L5:
	leaq	968+nvtxGlobals_v3(%rip), %rcx
.L18:
	movl	$136, %eax
	jmp	.L8
.L3:
	leaq	1104+nvtxGlobals_v3(%rip), %rcx
.L19:
	movl	$64, %eax
	jmp	.L8
.L14:
	leaq	696+nvtxGlobals_v3(%rip), %rcx
	movl	$80, %eax
.L8:
	testq	%rdx, %rdx
	je	.L10
	shrl	$3, %eax
	decl	%eax
	movl	%eax, (%rdx)
.L10:
	testq	%rsi, %rsi
	jne	.L11
.L12:
	movl	$1, %eax
	ret
.L11:
	movq	%rcx, (%rsi)
	jmp	.L12
.L1:
	ret
	.cfi_endproc
.LFE6263:
	.size	nvtxEtiGetModuleFunctionTable_v3, .-nvtxEtiGetModuleFunctionTable_v3
	.section	.text.nvtxGetExportTable_v3,"axG",@progbits,nvtxGetExportTable_v3,comdat
	.weak	nvtxGetExportTable_v3
	.hidden	nvtxGetExportTable_v3
	.type	nvtxGetExportTable_v3, @function
nvtxGetExportTable_v3:
.LFB6264:
	.cfi_startproc
	endbr64
	leaq	8+nvtxGlobals_v3(%rip), %rax
	cmpl	$1, %edi
	je	.L21
	cmpl	$3, %edi
	leaq	16(%rax), %rax
	movl	$0, %edx
	cmovne	%rdx, %rax
.L21:
	ret
	.cfi_endproc
.LFE6264:
	.size	nvtxGetExportTable_v3, .-nvtxGetExportTable_v3
	.section	.text.nvtxEtiSetInjectionNvtxVersion_v3,"axG",@progbits,nvtxEtiSetInjectionNvtxVersion_v3,comdat
	.weak	nvtxEtiSetInjectionNvtxVersion_v3
	.hidden	nvtxEtiSetInjectionNvtxVersion_v3
	.type	nvtxEtiSetInjectionNvtxVersion_v3, @function
nvtxEtiSetInjectionNvtxVersion_v3:
.LFB6265:
	.cfi_startproc
	endbr64
	ret
	.cfi_endproc
.LFE6265:
	.size	nvtxEtiSetInjectionNvtxVersion_v3, .-nvtxEtiSetInjectionNvtxVersion_v3
	.text
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB9892:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE9892:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0, @function
_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0:
.LFB10765:
	.cfi_startproc
	jmp	cudaLaunchKernel@PLT
	.cfi_endproc
.LFE10765:
	.size	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0, .-_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	.section	.text._ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv,"axG",@progbits,_ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv,comdat
	.weak	_ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv
	.hidden	_ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv
	.type	_ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv, @function
_ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv:
.LFB10337:
	.cfi_startproc
	endbr64
	subq	$72, %rsp
	.cfi_def_cfa_offset 80
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	movabsq	$4294967297, %rax
	leaq	16(%rsp), %rcx
	leaq	8(%rsp), %rdx
	movl	$1, 32(%rsp)
	leaq	36(%rsp), %rsi
	leaq	24(%rsp), %rdi
	movl	$1, 44(%rsp)
	movq	%rax, 24(%rsp)
	movq	%rax, 36(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L29
	pushq	16(%rsp)
	.cfi_def_cfa_offset 88
	leaq	_ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv(%rip), %rdi
	pushq	16(%rsp)
	.cfi_def_cfa_offset 96
	movq	52(%rsp), %rcx
	movl	60(%rsp), %r8d
	movq	40(%rsp), %rsi
	movl	48(%rsp), %edx
	leaq	64(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 88
	popq	%rdx
	.cfi_def_cfa_offset 80
.L29:
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L31
	call	__stack_chk_fail@PLT
.L31:
	addq	$72, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE10337:
	.size	_ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv, .-_ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv
	.section	.text.nvtxSetInitFunctionsToNoops_v3,"axG",@progbits,nvtxSetInitFunctionsToNoops_v3,comdat
	.weak	nvtxSetInitFunctionsToNoops_v3
	.hidden	nvtxSetInitFunctionsToNoops_v3
	.type	nvtxSetInitFunctionsToNoops_v3, @function
nvtxSetInitFunctionsToNoops_v3:
.LFB6330:
	.cfi_startproc
	endbr64
	testl	%edi, %edi
	leaq	nvtxMarkEx_impl_init_v3(%rip), %rdx
	setne	%al
	cmpq	%rdx, 48+nvtxGlobals_v3(%rip)
	je	.L162
	testb	%al, %al
	je	.L34
.L162:
	xorl	%r10d, %r10d
	movq	%r10, 48+nvtxGlobals_v3(%rip)
.L34:
	leaq	nvtxMarkA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 56+nvtxGlobals_v3(%rip)
	je	.L163
	testb	%al, %al
	je	.L36
.L163:
	xorl	%r9d, %r9d
	movq	%r9, 56+nvtxGlobals_v3(%rip)
.L36:
	leaq	nvtxMarkW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 64+nvtxGlobals_v3(%rip)
	je	.L164
	testb	%al, %al
	je	.L38
.L164:
	xorl	%r8d, %r8d
	movq	%r8, 64+nvtxGlobals_v3(%rip)
.L38:
	leaq	nvtxRangeStartEx_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 72+nvtxGlobals_v3(%rip)
	je	.L165
	testb	%al, %al
	je	.L40
.L165:
	xorl	%edi, %edi
	movq	%rdi, 72+nvtxGlobals_v3(%rip)
.L40:
	leaq	nvtxRangeStartA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 80+nvtxGlobals_v3(%rip)
	je	.L166
	testb	%al, %al
	je	.L42
.L166:
	xorl	%esi, %esi
	movq	%rsi, 80+nvtxGlobals_v3(%rip)
.L42:
	leaq	nvtxRangeStartW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 88+nvtxGlobals_v3(%rip)
	je	.L167
	testb	%al, %al
	je	.L44
.L167:
	xorl	%ecx, %ecx
	movq	%rcx, 88+nvtxGlobals_v3(%rip)
.L44:
	leaq	nvtxRangeEnd_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 96+nvtxGlobals_v3(%rip)
	je	.L168
	testb	%al, %al
	je	.L46
.L168:
	xorl	%edx, %edx
	movq	%rdx, 96+nvtxGlobals_v3(%rip)
.L46:
	leaq	nvtxRangePushEx_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 104+nvtxGlobals_v3(%rip)
	je	.L169
	testb	%al, %al
	je	.L48
.L169:
	xorl	%r11d, %r11d
	movq	%r11, 104+nvtxGlobals_v3(%rip)
.L48:
	leaq	nvtxRangePushA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 112+nvtxGlobals_v3(%rip)
	je	.L170
	testb	%al, %al
	je	.L50
.L170:
	xorl	%r10d, %r10d
	movq	%r10, 112+nvtxGlobals_v3(%rip)
.L50:
	leaq	nvtxRangePushW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 120+nvtxGlobals_v3(%rip)
	je	.L171
	testb	%al, %al
	je	.L52
.L171:
	xorl	%r9d, %r9d
	movq	%r9, 120+nvtxGlobals_v3(%rip)
.L52:
	leaq	nvtxRangePop_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 128+nvtxGlobals_v3(%rip)
	je	.L172
	testb	%al, %al
	je	.L54
.L172:
	xorl	%r8d, %r8d
	movq	%r8, 128+nvtxGlobals_v3(%rip)
.L54:
	leaq	nvtxNameCategoryA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 136+nvtxGlobals_v3(%rip)
	je	.L173
	testb	%al, %al
	je	.L56
.L173:
	xorl	%edi, %edi
	movq	%rdi, 136+nvtxGlobals_v3(%rip)
.L56:
	leaq	nvtxNameCategoryW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 144+nvtxGlobals_v3(%rip)
	je	.L174
	testb	%al, %al
	je	.L58
.L174:
	xorl	%esi, %esi
	movq	%rsi, 144+nvtxGlobals_v3(%rip)
.L58:
	leaq	nvtxNameOsThreadA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 152+nvtxGlobals_v3(%rip)
	je	.L175
	testb	%al, %al
	je	.L60
.L175:
	xorl	%ecx, %ecx
	movq	%rcx, 152+nvtxGlobals_v3(%rip)
.L60:
	leaq	nvtxNameOsThreadW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 160+nvtxGlobals_v3(%rip)
	je	.L176
	testb	%al, %al
	je	.L62
.L176:
	xorl	%edx, %edx
	movq	%rdx, 160+nvtxGlobals_v3(%rip)
.L62:
	leaq	nvtxNameCuDeviceA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 168+nvtxGlobals_v3(%rip)
	je	.L177
	testb	%al, %al
	je	.L64
.L177:
	xorl	%r11d, %r11d
	movq	%r11, 168+nvtxGlobals_v3(%rip)
.L64:
	leaq	nvtxNameCuDeviceW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 176+nvtxGlobals_v3(%rip)
	je	.L178
	testb	%al, %al
	je	.L66
.L178:
	xorl	%r10d, %r10d
	movq	%r10, 176+nvtxGlobals_v3(%rip)
.L66:
	leaq	nvtxNameCuContextA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 184+nvtxGlobals_v3(%rip)
	je	.L179
	testb	%al, %al
	je	.L68
.L179:
	xorl	%r9d, %r9d
	movq	%r9, 184+nvtxGlobals_v3(%rip)
.L68:
	leaq	nvtxNameCuContextW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 192+nvtxGlobals_v3(%rip)
	je	.L180
	testb	%al, %al
	je	.L70
.L180:
	xorl	%r8d, %r8d
	movq	%r8, 192+nvtxGlobals_v3(%rip)
.L70:
	leaq	nvtxNameCuStreamA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 200+nvtxGlobals_v3(%rip)
	je	.L181
	testb	%al, %al
	je	.L72
.L181:
	xorl	%edi, %edi
	movq	%rdi, 200+nvtxGlobals_v3(%rip)
.L72:
	leaq	nvtxNameCuStreamW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 208+nvtxGlobals_v3(%rip)
	je	.L182
	testb	%al, %al
	je	.L74
.L182:
	xorl	%esi, %esi
	movq	%rsi, 208+nvtxGlobals_v3(%rip)
.L74:
	leaq	nvtxNameCuEventA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 216+nvtxGlobals_v3(%rip)
	je	.L183
	testb	%al, %al
	je	.L76
.L183:
	xorl	%ecx, %ecx
	movq	%rcx, 216+nvtxGlobals_v3(%rip)
.L76:
	leaq	nvtxNameCuEventW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 224+nvtxGlobals_v3(%rip)
	je	.L184
	testb	%al, %al
	je	.L78
.L184:
	xorl	%edx, %edx
	movq	%rdx, 224+nvtxGlobals_v3(%rip)
.L78:
	leaq	nvtxNameClDeviceA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 232+nvtxGlobals_v3(%rip)
	je	.L185
	testb	%al, %al
	je	.L80
.L185:
	xorl	%r11d, %r11d
	movq	%r11, 232+nvtxGlobals_v3(%rip)
.L80:
	leaq	nvtxNameClDeviceW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 240+nvtxGlobals_v3(%rip)
	je	.L186
	testb	%al, %al
	je	.L82
.L186:
	xorl	%r10d, %r10d
	movq	%r10, 240+nvtxGlobals_v3(%rip)
.L82:
	leaq	nvtxNameClContextA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 248+nvtxGlobals_v3(%rip)
	je	.L187
	testb	%al, %al
	je	.L84
.L187:
	xorl	%r9d, %r9d
	movq	%r9, 248+nvtxGlobals_v3(%rip)
.L84:
	leaq	nvtxNameClContextW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 256+nvtxGlobals_v3(%rip)
	je	.L188
	testb	%al, %al
	je	.L86
.L188:
	xorl	%r8d, %r8d
	movq	%r8, 256+nvtxGlobals_v3(%rip)
.L86:
	leaq	nvtxNameClCommandQueueA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 264+nvtxGlobals_v3(%rip)
	je	.L189
	testb	%al, %al
	je	.L88
.L189:
	xorl	%edi, %edi
	movq	%rdi, 264+nvtxGlobals_v3(%rip)
.L88:
	leaq	nvtxNameClCommandQueueW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 272+nvtxGlobals_v3(%rip)
	je	.L190
	testb	%al, %al
	je	.L90
.L190:
	xorl	%esi, %esi
	movq	%rsi, 272+nvtxGlobals_v3(%rip)
.L90:
	leaq	nvtxNameClMemObjectA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 280+nvtxGlobals_v3(%rip)
	je	.L191
	testb	%al, %al
	je	.L92
.L191:
	xorl	%ecx, %ecx
	movq	%rcx, 280+nvtxGlobals_v3(%rip)
.L92:
	leaq	nvtxNameClMemObjectW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 288+nvtxGlobals_v3(%rip)
	je	.L192
	testb	%al, %al
	je	.L94
.L192:
	xorl	%edx, %edx
	movq	%rdx, 288+nvtxGlobals_v3(%rip)
.L94:
	leaq	nvtxNameClSamplerA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 296+nvtxGlobals_v3(%rip)
	je	.L193
	testb	%al, %al
	je	.L96
.L193:
	xorl	%r11d, %r11d
	movq	%r11, 296+nvtxGlobals_v3(%rip)
.L96:
	leaq	nvtxNameClSamplerW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 304+nvtxGlobals_v3(%rip)
	je	.L194
	testb	%al, %al
	je	.L98
.L194:
	xorl	%r10d, %r10d
	movq	%r10, 304+nvtxGlobals_v3(%rip)
.L98:
	leaq	nvtxNameClProgramA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 312+nvtxGlobals_v3(%rip)
	je	.L195
	testb	%al, %al
	je	.L100
.L195:
	xorl	%r9d, %r9d
	movq	%r9, 312+nvtxGlobals_v3(%rip)
.L100:
	leaq	nvtxNameClProgramW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 320+nvtxGlobals_v3(%rip)
	je	.L196
	testb	%al, %al
	je	.L102
.L196:
	xorl	%r8d, %r8d
	movq	%r8, 320+nvtxGlobals_v3(%rip)
.L102:
	leaq	nvtxNameClEventA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 328+nvtxGlobals_v3(%rip)
	je	.L197
	testb	%al, %al
	je	.L104
.L197:
	xorl	%edi, %edi
	movq	%rdi, 328+nvtxGlobals_v3(%rip)
.L104:
	leaq	nvtxNameClEventW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 336+nvtxGlobals_v3(%rip)
	je	.L198
	testb	%al, %al
	je	.L106
.L198:
	xorl	%esi, %esi
	movq	%rsi, 336+nvtxGlobals_v3(%rip)
.L106:
	leaq	nvtxNameCudaDeviceA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 344+nvtxGlobals_v3(%rip)
	je	.L199
	testb	%al, %al
	je	.L108
.L199:
	xorl	%ecx, %ecx
	movq	%rcx, 344+nvtxGlobals_v3(%rip)
.L108:
	leaq	nvtxNameCudaDeviceW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 352+nvtxGlobals_v3(%rip)
	je	.L200
	testb	%al, %al
	je	.L110
.L200:
	xorl	%edx, %edx
	movq	%rdx, 352+nvtxGlobals_v3(%rip)
.L110:
	leaq	nvtxNameCudaStreamA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 360+nvtxGlobals_v3(%rip)
	je	.L201
	testb	%al, %al
	je	.L112
.L201:
	xorl	%r11d, %r11d
	movq	%r11, 360+nvtxGlobals_v3(%rip)
.L112:
	leaq	nvtxNameCudaStreamW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 368+nvtxGlobals_v3(%rip)
	je	.L202
	testb	%al, %al
	je	.L114
.L202:
	xorl	%r10d, %r10d
	movq	%r10, 368+nvtxGlobals_v3(%rip)
.L114:
	leaq	nvtxNameCudaEventA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 376+nvtxGlobals_v3(%rip)
	je	.L203
	testb	%al, %al
	je	.L116
.L203:
	xorl	%r9d, %r9d
	movq	%r9, 376+nvtxGlobals_v3(%rip)
.L116:
	leaq	nvtxNameCudaEventW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 384+nvtxGlobals_v3(%rip)
	je	.L204
	testb	%al, %al
	je	.L118
.L204:
	xorl	%r8d, %r8d
	movq	%r8, 384+nvtxGlobals_v3(%rip)
.L118:
	leaq	nvtxDomainMarkEx_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 392+nvtxGlobals_v3(%rip)
	je	.L205
	testb	%al, %al
	je	.L120
.L205:
	xorl	%edi, %edi
	movq	%rdi, 392+nvtxGlobals_v3(%rip)
.L120:
	leaq	nvtxDomainRangeStartEx_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 400+nvtxGlobals_v3(%rip)
	je	.L206
	testb	%al, %al
	je	.L122
.L206:
	xorl	%esi, %esi
	movq	%rsi, 400+nvtxGlobals_v3(%rip)
.L122:
	leaq	nvtxDomainRangeEnd_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 408+nvtxGlobals_v3(%rip)
	je	.L207
	testb	%al, %al
	je	.L124
.L207:
	xorl	%ecx, %ecx
	movq	%rcx, 408+nvtxGlobals_v3(%rip)
.L124:
	leaq	nvtxDomainRangePushEx_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 416+nvtxGlobals_v3(%rip)
	je	.L208
	testb	%al, %al
	je	.L126
.L208:
	xorl	%edx, %edx
	movq	%rdx, 416+nvtxGlobals_v3(%rip)
.L126:
	leaq	nvtxDomainRangePop_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 424+nvtxGlobals_v3(%rip)
	je	.L209
	testb	%al, %al
	je	.L128
.L209:
	xorl	%r11d, %r11d
	movq	%r11, 424+nvtxGlobals_v3(%rip)
.L128:
	leaq	nvtxDomainResourceCreate_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 432+nvtxGlobals_v3(%rip)
	je	.L210
	testb	%al, %al
	je	.L130
.L210:
	xorl	%r10d, %r10d
	movq	%r10, 432+nvtxGlobals_v3(%rip)
.L130:
	leaq	nvtxDomainResourceDestroy_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 440+nvtxGlobals_v3(%rip)
	je	.L211
	testb	%al, %al
	je	.L132
.L211:
	xorl	%r9d, %r9d
	movq	%r9, 440+nvtxGlobals_v3(%rip)
.L132:
	leaq	nvtxDomainNameCategoryA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 448+nvtxGlobals_v3(%rip)
	je	.L212
	testb	%al, %al
	je	.L134
.L212:
	xorl	%r8d, %r8d
	movq	%r8, 448+nvtxGlobals_v3(%rip)
.L134:
	leaq	nvtxDomainNameCategoryW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 456+nvtxGlobals_v3(%rip)
	je	.L213
	testb	%al, %al
	je	.L136
.L213:
	xorl	%edi, %edi
	movq	%rdi, 456+nvtxGlobals_v3(%rip)
.L136:
	leaq	nvtxDomainRegisterStringA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 464+nvtxGlobals_v3(%rip)
	je	.L214
	testb	%al, %al
	je	.L138
.L214:
	xorl	%esi, %esi
	movq	%rsi, 464+nvtxGlobals_v3(%rip)
.L138:
	leaq	nvtxDomainRegisterStringW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 472+nvtxGlobals_v3(%rip)
	je	.L215
	testb	%al, %al
	je	.L140
.L215:
	xorl	%ecx, %ecx
	movq	%rcx, 472+nvtxGlobals_v3(%rip)
.L140:
	leaq	nvtxDomainCreateA_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 480+nvtxGlobals_v3(%rip)
	je	.L216
	testb	%al, %al
	je	.L142
.L216:
	xorl	%edx, %edx
	movq	%rdx, 480+nvtxGlobals_v3(%rip)
.L142:
	leaq	nvtxDomainCreateW_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 488+nvtxGlobals_v3(%rip)
	je	.L217
	testb	%al, %al
	je	.L144
.L217:
	xorl	%r11d, %r11d
	movq	%r11, 488+nvtxGlobals_v3(%rip)
.L144:
	leaq	nvtxDomainDestroy_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 496+nvtxGlobals_v3(%rip)
	je	.L218
	testb	%al, %al
	je	.L146
.L218:
	xorl	%r10d, %r10d
	movq	%r10, 496+nvtxGlobals_v3(%rip)
.L146:
	leaq	nvtxInitialize_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 504+nvtxGlobals_v3(%rip)
	je	.L219
	testb	%al, %al
	je	.L148
.L219:
	xorl	%r9d, %r9d
	movq	%r9, 504+nvtxGlobals_v3(%rip)
.L148:
	leaq	nvtxDomainSyncUserCreate_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 512+nvtxGlobals_v3(%rip)
	je	.L220
	testb	%al, %al
	je	.L150
.L220:
	xorl	%r8d, %r8d
	movq	%r8, 512+nvtxGlobals_v3(%rip)
.L150:
	leaq	nvtxDomainSyncUserDestroy_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 520+nvtxGlobals_v3(%rip)
	je	.L221
	testb	%al, %al
	je	.L152
.L221:
	xorl	%edi, %edi
	movq	%rdi, 520+nvtxGlobals_v3(%rip)
.L152:
	leaq	nvtxDomainSyncUserAcquireStart_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 528+nvtxGlobals_v3(%rip)
	je	.L222
	testb	%al, %al
	je	.L154
.L222:
	xorl	%esi, %esi
	movq	%rsi, 528+nvtxGlobals_v3(%rip)
.L154:
	leaq	nvtxDomainSyncUserAcquireFailed_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 536+nvtxGlobals_v3(%rip)
	je	.L223
	testb	%al, %al
	je	.L156
.L223:
	xorl	%ecx, %ecx
	movq	%rcx, 536+nvtxGlobals_v3(%rip)
.L156:
	leaq	nvtxDomainSyncUserAcquireSuccess_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 544+nvtxGlobals_v3(%rip)
	je	.L224
	testb	%al, %al
	je	.L158
.L224:
	xorl	%edx, %edx
	movq	%rdx, 544+nvtxGlobals_v3(%rip)
.L158:
	leaq	nvtxDomainSyncUserReleasing_impl_init_v3(%rip), %rdx
	cmpq	%rdx, 552+nvtxGlobals_v3(%rip)
	je	.L225
	testb	%al, %al
	je	.L33
.L225:
	xorl	%eax, %eax
	movq	%rax, 552+nvtxGlobals_v3(%rip)
.L33:
	ret
	.cfi_endproc
.LFE6330:
	.size	nvtxSetInitFunctionsToNoops_v3, .-nvtxSetInitFunctionsToNoops_v3
	.section	.rodata.nvtxInitializeInjectionLibrary_v3.str1.1,"aMS",@progbits,1
.LC0:
	.string	"NVTX_INJECTION64_PATH"
.LC1:
	.string	"InitializeInjectionNvtx2"
	.section	.text.nvtxInitializeInjectionLibrary_v3,"axG",@progbits,nvtxInitializeInjectionLibrary_v3,comdat
	.weak	nvtxInitializeInjectionLibrary_v3
	.hidden	nvtxInitializeInjectionLibrary_v3
	.type	nvtxInitializeInjectionLibrary_v3, @function
nvtxInitializeInjectionLibrary_v3:
.LFB6331:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	.LC0(%rip), %rdi
	call	getenv@PLT
	movq	%rax, %rbx
	testq	%rax, %rax
	je	.L419
	movl	$1, %esi
	movq	%rax, %rdi
	call	dlopen@PLT
	movl	$4, %edx
	movq	%rax, %rbx
	testq	%rax, %rax
	je	.L418
	leaq	.LC1(%rip), %rsi
	movq	%rax, %rdi
	call	dlsym@PLT
	testq	%rax, %rax
	jne	.L421
	movq	%rbx, %rdi
	call	dlclose@PLT
	movl	$5, %edx
	jmp	.L418
.L419:
	movq	InitializeInjectionNvtx2_fnptr(%rip), %rax
	movl	$7, %edx
	testq	%rax, %rax
	je	.L418
.L421:
	leaq	nvtxGetExportTable_v3(%rip), %rdi
	call	*%rax
	xorl	%edx, %edx
	testl	%eax, %eax
	jne	.L418
	testq	%rbx, %rbx
	je	.L422
	movq	%rbx, %rdi
	call	dlclose@PLT
.L422:
	movl	$6, %edx
.L418:
	movl	%edx, %eax
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6331:
	.size	nvtxInitializeInjectionLibrary_v3, .-nvtxInitializeInjectionLibrary_v3
	.section	.text.nvtxInitOnce_v3,"axG",@progbits,nvtxInitOnce_v3,comdat
	.weak	nvtxInitOnce_v3
	.hidden	nvtxInitOnce_v3
	.type	nvtxInitOnce_v3, @function
nvtxInitOnce_v3:
.LFB6332:
	.cfi_startproc
	endbr64
	movl	nvtxGlobals_v3(%rip), %eax
	cmpl	$2, %eax
	je	.L438
	pushq	%rdx
	.cfi_def_cfa_offset 16
	movl	$1, %eax
	xorl	%edx, %edx
	mfence
	lock cmpxchgl	%edx, nvtxGlobals_v3(%rip)
	testl	%eax, %eax
	jne	.L441
	call	nvtxInitializeInjectionLibrary_v3
	xorl	%edi, %edi
	testl	%eax, %eax
	setne	%dil
	call	nvtxSetInitFunctionsToNoops_v3
	movl	$2, %eax
	mfence
	xchgl	nvtxGlobals_v3(%rip), %eax
	jmp	.L430
.L441:
	mfence
	movl	nvtxGlobals_v3(%rip), %eax
	cmpl	$2, %eax
	je	.L430
	call	sched_yield@PLT
	jmp	.L441
.L430:
	popq	%rax
	.cfi_def_cfa_offset 8
	ret
.L438:
	ret
	.cfi_endproc
.LFE6332:
	.size	nvtxInitOnce_v3, .-nvtxInitOnce_v3
	.section	.text.nvtxDomainSyncUserReleasing_impl_init_v3,"axG",@progbits,nvtxDomainSyncUserReleasing_impl_init_v3,comdat
	.weak	nvtxDomainSyncUserReleasing_impl_init_v3
	.hidden	nvtxDomainSyncUserReleasing_impl_init_v3
	.type	nvtxDomainSyncUserReleasing_impl_init_v3, @function
nvtxDomainSyncUserReleasing_impl_init_v3:
.LFB6329:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	552+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L442
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L442:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6329:
	.size	nvtxDomainSyncUserReleasing_impl_init_v3, .-nvtxDomainSyncUserReleasing_impl_init_v3
	.section	.text.nvtxDomainSyncUserAcquireSuccess_impl_init_v3,"axG",@progbits,nvtxDomainSyncUserAcquireSuccess_impl_init_v3,comdat
	.weak	nvtxDomainSyncUserAcquireSuccess_impl_init_v3
	.hidden	nvtxDomainSyncUserAcquireSuccess_impl_init_v3
	.type	nvtxDomainSyncUserAcquireSuccess_impl_init_v3, @function
nvtxDomainSyncUserAcquireSuccess_impl_init_v3:
.LFB6328:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	544+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L445
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L445:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6328:
	.size	nvtxDomainSyncUserAcquireSuccess_impl_init_v3, .-nvtxDomainSyncUserAcquireSuccess_impl_init_v3
	.section	.text.nvtxDomainSyncUserAcquireFailed_impl_init_v3,"axG",@progbits,nvtxDomainSyncUserAcquireFailed_impl_init_v3,comdat
	.weak	nvtxDomainSyncUserAcquireFailed_impl_init_v3
	.hidden	nvtxDomainSyncUserAcquireFailed_impl_init_v3
	.type	nvtxDomainSyncUserAcquireFailed_impl_init_v3, @function
nvtxDomainSyncUserAcquireFailed_impl_init_v3:
.LFB6327:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	536+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L448
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L448:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6327:
	.size	nvtxDomainSyncUserAcquireFailed_impl_init_v3, .-nvtxDomainSyncUserAcquireFailed_impl_init_v3
	.section	.text.nvtxDomainSyncUserAcquireStart_impl_init_v3,"axG",@progbits,nvtxDomainSyncUserAcquireStart_impl_init_v3,comdat
	.weak	nvtxDomainSyncUserAcquireStart_impl_init_v3
	.hidden	nvtxDomainSyncUserAcquireStart_impl_init_v3
	.type	nvtxDomainSyncUserAcquireStart_impl_init_v3, @function
nvtxDomainSyncUserAcquireStart_impl_init_v3:
.LFB6326:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	528+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L451
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L451:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6326:
	.size	nvtxDomainSyncUserAcquireStart_impl_init_v3, .-nvtxDomainSyncUserAcquireStart_impl_init_v3
	.section	.text.nvtxDomainSyncUserDestroy_impl_init_v3,"axG",@progbits,nvtxDomainSyncUserDestroy_impl_init_v3,comdat
	.weak	nvtxDomainSyncUserDestroy_impl_init_v3
	.hidden	nvtxDomainSyncUserDestroy_impl_init_v3
	.type	nvtxDomainSyncUserDestroy_impl_init_v3, @function
nvtxDomainSyncUserDestroy_impl_init_v3:
.LFB6325:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	520+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L454
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L454:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6325:
	.size	nvtxDomainSyncUserDestroy_impl_init_v3, .-nvtxDomainSyncUserDestroy_impl_init_v3
	.section	.text.nvtxDomainSyncUserCreate_impl_init_v3,"axG",@progbits,nvtxDomainSyncUserCreate_impl_init_v3,comdat
	.weak	nvtxDomainSyncUserCreate_impl_init_v3
	.hidden	nvtxDomainSyncUserCreate_impl_init_v3
	.type	nvtxDomainSyncUserCreate_impl_init_v3, @function
nvtxDomainSyncUserCreate_impl_init_v3:
.LFB6324:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	512+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L458
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L458:
	.cfi_restore_state
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6324:
	.size	nvtxDomainSyncUserCreate_impl_init_v3, .-nvtxDomainSyncUserCreate_impl_init_v3
	.section	.text.nvtxInitialize_impl_init_v3,"axG",@progbits,nvtxInitialize_impl_init_v3,comdat
	.weak	nvtxInitialize_impl_init_v3
	.hidden	nvtxInitialize_impl_init_v3
	.type	nvtxInitialize_impl_init_v3, @function
nvtxInitialize_impl_init_v3:
.LFB6295:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	504+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L460
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L460:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6295:
	.size	nvtxInitialize_impl_init_v3, .-nvtxInitialize_impl_init_v3
	.section	.text.nvtxDomainDestroy_impl_init_v3,"axG",@progbits,nvtxDomainDestroy_impl_init_v3,comdat
	.weak	nvtxDomainDestroy_impl_init_v3
	.hidden	nvtxDomainDestroy_impl_init_v3
	.type	nvtxDomainDestroy_impl_init_v3, @function
nvtxDomainDestroy_impl_init_v3:
.LFB6294:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	496+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L463
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L463:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6294:
	.size	nvtxDomainDestroy_impl_init_v3, .-nvtxDomainDestroy_impl_init_v3
	.section	.text.nvtxDomainCreateW_impl_init_v3,"axG",@progbits,nvtxDomainCreateW_impl_init_v3,comdat
	.weak	nvtxDomainCreateW_impl_init_v3
	.hidden	nvtxDomainCreateW_impl_init_v3
	.type	nvtxDomainCreateW_impl_init_v3, @function
nvtxDomainCreateW_impl_init_v3:
.LFB6293:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	488+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L467
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L467:
	.cfi_restore_state
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6293:
	.size	nvtxDomainCreateW_impl_init_v3, .-nvtxDomainCreateW_impl_init_v3
	.section	.text.nvtxDomainCreateA_impl_init_v3,"axG",@progbits,nvtxDomainCreateA_impl_init_v3,comdat
	.weak	nvtxDomainCreateA_impl_init_v3
	.hidden	nvtxDomainCreateA_impl_init_v3
	.type	nvtxDomainCreateA_impl_init_v3, @function
nvtxDomainCreateA_impl_init_v3:
.LFB6292:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	480+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L470
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L470:
	.cfi_restore_state
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6292:
	.size	nvtxDomainCreateA_impl_init_v3, .-nvtxDomainCreateA_impl_init_v3
	.section	.text.nvtxDomainRegisterStringW_impl_init_v3,"axG",@progbits,nvtxDomainRegisterStringW_impl_init_v3,comdat
	.weak	nvtxDomainRegisterStringW_impl_init_v3
	.hidden	nvtxDomainRegisterStringW_impl_init_v3
	.type	nvtxDomainRegisterStringW_impl_init_v3, @function
nvtxDomainRegisterStringW_impl_init_v3:
.LFB6291:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	472+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L473
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L473:
	.cfi_restore_state
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6291:
	.size	nvtxDomainRegisterStringW_impl_init_v3, .-nvtxDomainRegisterStringW_impl_init_v3
	.section	.text.nvtxDomainRegisterStringA_impl_init_v3,"axG",@progbits,nvtxDomainRegisterStringA_impl_init_v3,comdat
	.weak	nvtxDomainRegisterStringA_impl_init_v3
	.hidden	nvtxDomainRegisterStringA_impl_init_v3
	.type	nvtxDomainRegisterStringA_impl_init_v3, @function
nvtxDomainRegisterStringA_impl_init_v3:
.LFB6290:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	464+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L476
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L476:
	.cfi_restore_state
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6290:
	.size	nvtxDomainRegisterStringA_impl_init_v3, .-nvtxDomainRegisterStringA_impl_init_v3
	.section	.text.nvtxDomainNameCategoryW_impl_init_v3,"axG",@progbits,nvtxDomainNameCategoryW_impl_init_v3,comdat
	.weak	nvtxDomainNameCategoryW_impl_init_v3
	.hidden	nvtxDomainNameCategoryW_impl_init_v3
	.type	nvtxDomainNameCategoryW_impl_init_v3, @function
nvtxDomainNameCategoryW_impl_init_v3:
.LFB6289:
	.cfi_startproc
	endbr64
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	%rdi, 24(%rsp)
	movl	%esi, 20(%rsp)
	movq	%rdx, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	456+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L478
	movq	8(%rsp), %rdx
	movl	20(%rsp), %esi
	movq	24(%rsp), %rdi
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L478:
	.cfi_restore_state
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6289:
	.size	nvtxDomainNameCategoryW_impl_init_v3, .-nvtxDomainNameCategoryW_impl_init_v3
	.section	.text.nvtxDomainNameCategoryA_impl_init_v3,"axG",@progbits,nvtxDomainNameCategoryA_impl_init_v3,comdat
	.weak	nvtxDomainNameCategoryA_impl_init_v3
	.hidden	nvtxDomainNameCategoryA_impl_init_v3
	.type	nvtxDomainNameCategoryA_impl_init_v3, @function
nvtxDomainNameCategoryA_impl_init_v3:
.LFB6288:
	.cfi_startproc
	endbr64
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	%rdi, 24(%rsp)
	movl	%esi, 20(%rsp)
	movq	%rdx, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	448+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L481
	movq	8(%rsp), %rdx
	movl	20(%rsp), %esi
	movq	24(%rsp), %rdi
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L481:
	.cfi_restore_state
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6288:
	.size	nvtxDomainNameCategoryA_impl_init_v3, .-nvtxDomainNameCategoryA_impl_init_v3
	.section	.text.nvtxDomainResourceDestroy_impl_init_v3,"axG",@progbits,nvtxDomainResourceDestroy_impl_init_v3,comdat
	.weak	nvtxDomainResourceDestroy_impl_init_v3
	.hidden	nvtxDomainResourceDestroy_impl_init_v3
	.type	nvtxDomainResourceDestroy_impl_init_v3, @function
nvtxDomainResourceDestroy_impl_init_v3:
.LFB6287:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	440+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L484
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L484:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6287:
	.size	nvtxDomainResourceDestroy_impl_init_v3, .-nvtxDomainResourceDestroy_impl_init_v3
	.section	.text.nvtxDomainResourceCreate_impl_init_v3,"axG",@progbits,nvtxDomainResourceCreate_impl_init_v3,comdat
	.weak	nvtxDomainResourceCreate_impl_init_v3
	.hidden	nvtxDomainResourceCreate_impl_init_v3
	.type	nvtxDomainResourceCreate_impl_init_v3, @function
nvtxDomainResourceCreate_impl_init_v3:
.LFB6286:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	432+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L488
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L488:
	.cfi_restore_state
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6286:
	.size	nvtxDomainResourceCreate_impl_init_v3, .-nvtxDomainResourceCreate_impl_init_v3
	.section	.text.nvtxDomainRangePop_impl_init_v3,"axG",@progbits,nvtxDomainRangePop_impl_init_v3,comdat
	.weak	nvtxDomainRangePop_impl_init_v3
	.hidden	nvtxDomainRangePop_impl_init_v3
	.type	nvtxDomainRangePop_impl_init_v3, @function
nvtxDomainRangePop_impl_init_v3:
.LFB6285:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	424+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L491
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L491:
	.cfi_restore_state
	movl	$-2, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6285:
	.size	nvtxDomainRangePop_impl_init_v3, .-nvtxDomainRangePop_impl_init_v3
	.section	.text.nvtxDomainRangePushEx_impl_init_v3,"axG",@progbits,nvtxDomainRangePushEx_impl_init_v3,comdat
	.weak	nvtxDomainRangePushEx_impl_init_v3
	.hidden	nvtxDomainRangePushEx_impl_init_v3
	.type	nvtxDomainRangePushEx_impl_init_v3, @function
nvtxDomainRangePushEx_impl_init_v3:
.LFB6284:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	416+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L494
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L494:
	.cfi_restore_state
	movl	$-2, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6284:
	.size	nvtxDomainRangePushEx_impl_init_v3, .-nvtxDomainRangePushEx_impl_init_v3
	.section	.text.nvtxDomainRangeEnd_impl_init_v3,"axG",@progbits,nvtxDomainRangeEnd_impl_init_v3,comdat
	.weak	nvtxDomainRangeEnd_impl_init_v3
	.hidden	nvtxDomainRangeEnd_impl_init_v3
	.type	nvtxDomainRangeEnd_impl_init_v3, @function
nvtxDomainRangeEnd_impl_init_v3:
.LFB6283:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	408+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L496
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L496:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6283:
	.size	nvtxDomainRangeEnd_impl_init_v3, .-nvtxDomainRangeEnd_impl_init_v3
	.section	.text.nvtxDomainRangeStartEx_impl_init_v3,"axG",@progbits,nvtxDomainRangeStartEx_impl_init_v3,comdat
	.weak	nvtxDomainRangeStartEx_impl_init_v3
	.hidden	nvtxDomainRangeStartEx_impl_init_v3
	.type	nvtxDomainRangeStartEx_impl_init_v3, @function
nvtxDomainRangeStartEx_impl_init_v3:
.LFB6282:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	400+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L500
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L500:
	.cfi_restore_state
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6282:
	.size	nvtxDomainRangeStartEx_impl_init_v3, .-nvtxDomainRangeStartEx_impl_init_v3
	.section	.text.nvtxDomainMarkEx_impl_init_v3,"axG",@progbits,nvtxDomainMarkEx_impl_init_v3,comdat
	.weak	nvtxDomainMarkEx_impl_init_v3
	.hidden	nvtxDomainMarkEx_impl_init_v3
	.type	nvtxDomainMarkEx_impl_init_v3, @function
nvtxDomainMarkEx_impl_init_v3:
.LFB6281:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	392+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L502
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L502:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6281:
	.size	nvtxDomainMarkEx_impl_init_v3, .-nvtxDomainMarkEx_impl_init_v3
	.section	.text.nvtxNameCudaEventW_impl_init_v3,"axG",@progbits,nvtxNameCudaEventW_impl_init_v3,comdat
	.weak	nvtxNameCudaEventW_impl_init_v3
	.hidden	nvtxNameCudaEventW_impl_init_v3
	.type	nvtxNameCudaEventW_impl_init_v3, @function
nvtxNameCudaEventW_impl_init_v3:
.LFB6309:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	384+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L505
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L505:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6309:
	.size	nvtxNameCudaEventW_impl_init_v3, .-nvtxNameCudaEventW_impl_init_v3
	.section	.text.nvtxNameCudaEventA_impl_init_v3,"axG",@progbits,nvtxNameCudaEventA_impl_init_v3,comdat
	.weak	nvtxNameCudaEventA_impl_init_v3
	.hidden	nvtxNameCudaEventA_impl_init_v3
	.type	nvtxNameCudaEventA_impl_init_v3, @function
nvtxNameCudaEventA_impl_init_v3:
.LFB6308:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	376+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L508
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L508:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6308:
	.size	nvtxNameCudaEventA_impl_init_v3, .-nvtxNameCudaEventA_impl_init_v3
	.section	.text.nvtxNameCudaStreamW_impl_init_v3,"axG",@progbits,nvtxNameCudaStreamW_impl_init_v3,comdat
	.weak	nvtxNameCudaStreamW_impl_init_v3
	.hidden	nvtxNameCudaStreamW_impl_init_v3
	.type	nvtxNameCudaStreamW_impl_init_v3, @function
nvtxNameCudaStreamW_impl_init_v3:
.LFB6307:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	368+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L511
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L511:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6307:
	.size	nvtxNameCudaStreamW_impl_init_v3, .-nvtxNameCudaStreamW_impl_init_v3
	.section	.text.nvtxNameCudaStreamA_impl_init_v3,"axG",@progbits,nvtxNameCudaStreamA_impl_init_v3,comdat
	.weak	nvtxNameCudaStreamA_impl_init_v3
	.hidden	nvtxNameCudaStreamA_impl_init_v3
	.type	nvtxNameCudaStreamA_impl_init_v3, @function
nvtxNameCudaStreamA_impl_init_v3:
.LFB6306:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	360+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L514
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L514:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6306:
	.size	nvtxNameCudaStreamA_impl_init_v3, .-nvtxNameCudaStreamA_impl_init_v3
	.section	.text.nvtxNameCudaDeviceW_impl_init_v3,"axG",@progbits,nvtxNameCudaDeviceW_impl_init_v3,comdat
	.weak	nvtxNameCudaDeviceW_impl_init_v3
	.hidden	nvtxNameCudaDeviceW_impl_init_v3
	.type	nvtxNameCudaDeviceW_impl_init_v3, @function
nvtxNameCudaDeviceW_impl_init_v3:
.LFB6305:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	%edi, 12(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	352+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L517
	movq	(%rsp), %rsi
	movl	12(%rsp), %edi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L517:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6305:
	.size	nvtxNameCudaDeviceW_impl_init_v3, .-nvtxNameCudaDeviceW_impl_init_v3
	.section	.text.nvtxNameCudaDeviceA_impl_init_v3,"axG",@progbits,nvtxNameCudaDeviceA_impl_init_v3,comdat
	.weak	nvtxNameCudaDeviceA_impl_init_v3
	.hidden	nvtxNameCudaDeviceA_impl_init_v3
	.type	nvtxNameCudaDeviceA_impl_init_v3, @function
nvtxNameCudaDeviceA_impl_init_v3:
.LFB6304:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	%edi, 12(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	344+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L520
	movq	(%rsp), %rsi
	movl	12(%rsp), %edi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L520:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6304:
	.size	nvtxNameCudaDeviceA_impl_init_v3, .-nvtxNameCudaDeviceA_impl_init_v3
	.section	.text.nvtxNameClEventW_impl_init_v3,"axG",@progbits,nvtxNameClEventW_impl_init_v3,comdat
	.weak	nvtxNameClEventW_impl_init_v3
	.hidden	nvtxNameClEventW_impl_init_v3
	.type	nvtxNameClEventW_impl_init_v3, @function
nvtxNameClEventW_impl_init_v3:
.LFB6323:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	336+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L523
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L523:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6323:
	.size	nvtxNameClEventW_impl_init_v3, .-nvtxNameClEventW_impl_init_v3
	.section	.text.nvtxNameClEventA_impl_init_v3,"axG",@progbits,nvtxNameClEventA_impl_init_v3,comdat
	.weak	nvtxNameClEventA_impl_init_v3
	.hidden	nvtxNameClEventA_impl_init_v3
	.type	nvtxNameClEventA_impl_init_v3, @function
nvtxNameClEventA_impl_init_v3:
.LFB6322:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	328+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L526
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L526:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6322:
	.size	nvtxNameClEventA_impl_init_v3, .-nvtxNameClEventA_impl_init_v3
	.section	.text.nvtxNameClProgramW_impl_init_v3,"axG",@progbits,nvtxNameClProgramW_impl_init_v3,comdat
	.weak	nvtxNameClProgramW_impl_init_v3
	.hidden	nvtxNameClProgramW_impl_init_v3
	.type	nvtxNameClProgramW_impl_init_v3, @function
nvtxNameClProgramW_impl_init_v3:
.LFB6321:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	320+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L529
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L529:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6321:
	.size	nvtxNameClProgramW_impl_init_v3, .-nvtxNameClProgramW_impl_init_v3
	.section	.text.nvtxNameClProgramA_impl_init_v3,"axG",@progbits,nvtxNameClProgramA_impl_init_v3,comdat
	.weak	nvtxNameClProgramA_impl_init_v3
	.hidden	nvtxNameClProgramA_impl_init_v3
	.type	nvtxNameClProgramA_impl_init_v3, @function
nvtxNameClProgramA_impl_init_v3:
.LFB6320:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	312+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L532
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L532:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6320:
	.size	nvtxNameClProgramA_impl_init_v3, .-nvtxNameClProgramA_impl_init_v3
	.section	.text.nvtxNameClSamplerW_impl_init_v3,"axG",@progbits,nvtxNameClSamplerW_impl_init_v3,comdat
	.weak	nvtxNameClSamplerW_impl_init_v3
	.hidden	nvtxNameClSamplerW_impl_init_v3
	.type	nvtxNameClSamplerW_impl_init_v3, @function
nvtxNameClSamplerW_impl_init_v3:
.LFB6319:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	304+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L535
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L535:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6319:
	.size	nvtxNameClSamplerW_impl_init_v3, .-nvtxNameClSamplerW_impl_init_v3
	.section	.text.nvtxNameClSamplerA_impl_init_v3,"axG",@progbits,nvtxNameClSamplerA_impl_init_v3,comdat
	.weak	nvtxNameClSamplerA_impl_init_v3
	.hidden	nvtxNameClSamplerA_impl_init_v3
	.type	nvtxNameClSamplerA_impl_init_v3, @function
nvtxNameClSamplerA_impl_init_v3:
.LFB6318:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	296+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L538
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L538:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6318:
	.size	nvtxNameClSamplerA_impl_init_v3, .-nvtxNameClSamplerA_impl_init_v3
	.section	.text.nvtxNameClMemObjectW_impl_init_v3,"axG",@progbits,nvtxNameClMemObjectW_impl_init_v3,comdat
	.weak	nvtxNameClMemObjectW_impl_init_v3
	.hidden	nvtxNameClMemObjectW_impl_init_v3
	.type	nvtxNameClMemObjectW_impl_init_v3, @function
nvtxNameClMemObjectW_impl_init_v3:
.LFB6317:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	288+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L541
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L541:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6317:
	.size	nvtxNameClMemObjectW_impl_init_v3, .-nvtxNameClMemObjectW_impl_init_v3
	.section	.text.nvtxNameClMemObjectA_impl_init_v3,"axG",@progbits,nvtxNameClMemObjectA_impl_init_v3,comdat
	.weak	nvtxNameClMemObjectA_impl_init_v3
	.hidden	nvtxNameClMemObjectA_impl_init_v3
	.type	nvtxNameClMemObjectA_impl_init_v3, @function
nvtxNameClMemObjectA_impl_init_v3:
.LFB6316:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	280+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L544
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L544:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6316:
	.size	nvtxNameClMemObjectA_impl_init_v3, .-nvtxNameClMemObjectA_impl_init_v3
	.section	.text.nvtxNameClCommandQueueW_impl_init_v3,"axG",@progbits,nvtxNameClCommandQueueW_impl_init_v3,comdat
	.weak	nvtxNameClCommandQueueW_impl_init_v3
	.hidden	nvtxNameClCommandQueueW_impl_init_v3
	.type	nvtxNameClCommandQueueW_impl_init_v3, @function
nvtxNameClCommandQueueW_impl_init_v3:
.LFB6315:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	272+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L547
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L547:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6315:
	.size	nvtxNameClCommandQueueW_impl_init_v3, .-nvtxNameClCommandQueueW_impl_init_v3
	.section	.text.nvtxNameClCommandQueueA_impl_init_v3,"axG",@progbits,nvtxNameClCommandQueueA_impl_init_v3,comdat
	.weak	nvtxNameClCommandQueueA_impl_init_v3
	.hidden	nvtxNameClCommandQueueA_impl_init_v3
	.type	nvtxNameClCommandQueueA_impl_init_v3, @function
nvtxNameClCommandQueueA_impl_init_v3:
.LFB6314:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	264+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L550
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L550:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6314:
	.size	nvtxNameClCommandQueueA_impl_init_v3, .-nvtxNameClCommandQueueA_impl_init_v3
	.section	.text.nvtxNameClContextW_impl_init_v3,"axG",@progbits,nvtxNameClContextW_impl_init_v3,comdat
	.weak	nvtxNameClContextW_impl_init_v3
	.hidden	nvtxNameClContextW_impl_init_v3
	.type	nvtxNameClContextW_impl_init_v3, @function
nvtxNameClContextW_impl_init_v3:
.LFB6313:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	256+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L553
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L553:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6313:
	.size	nvtxNameClContextW_impl_init_v3, .-nvtxNameClContextW_impl_init_v3
	.section	.text.nvtxNameClContextA_impl_init_v3,"axG",@progbits,nvtxNameClContextA_impl_init_v3,comdat
	.weak	nvtxNameClContextA_impl_init_v3
	.hidden	nvtxNameClContextA_impl_init_v3
	.type	nvtxNameClContextA_impl_init_v3, @function
nvtxNameClContextA_impl_init_v3:
.LFB6312:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	248+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L556
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L556:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6312:
	.size	nvtxNameClContextA_impl_init_v3, .-nvtxNameClContextA_impl_init_v3
	.section	.text.nvtxNameClDeviceW_impl_init_v3,"axG",@progbits,nvtxNameClDeviceW_impl_init_v3,comdat
	.weak	nvtxNameClDeviceW_impl_init_v3
	.hidden	nvtxNameClDeviceW_impl_init_v3
	.type	nvtxNameClDeviceW_impl_init_v3, @function
nvtxNameClDeviceW_impl_init_v3:
.LFB6311:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	240+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L559
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L559:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6311:
	.size	nvtxNameClDeviceW_impl_init_v3, .-nvtxNameClDeviceW_impl_init_v3
	.section	.text.nvtxNameClDeviceA_impl_init_v3,"axG",@progbits,nvtxNameClDeviceA_impl_init_v3,comdat
	.weak	nvtxNameClDeviceA_impl_init_v3
	.hidden	nvtxNameClDeviceA_impl_init_v3
	.type	nvtxNameClDeviceA_impl_init_v3, @function
nvtxNameClDeviceA_impl_init_v3:
.LFB6310:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	232+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L562
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L562:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6310:
	.size	nvtxNameClDeviceA_impl_init_v3, .-nvtxNameClDeviceA_impl_init_v3
	.section	.text.nvtxNameCuEventW_impl_init_v3,"axG",@progbits,nvtxNameCuEventW_impl_init_v3,comdat
	.weak	nvtxNameCuEventW_impl_init_v3
	.hidden	nvtxNameCuEventW_impl_init_v3
	.type	nvtxNameCuEventW_impl_init_v3, @function
nvtxNameCuEventW_impl_init_v3:
.LFB6303:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	224+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L565
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L565:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6303:
	.size	nvtxNameCuEventW_impl_init_v3, .-nvtxNameCuEventW_impl_init_v3
	.section	.text.nvtxNameCuEventA_impl_init_v3,"axG",@progbits,nvtxNameCuEventA_impl_init_v3,comdat
	.weak	nvtxNameCuEventA_impl_init_v3
	.hidden	nvtxNameCuEventA_impl_init_v3
	.type	nvtxNameCuEventA_impl_init_v3, @function
nvtxNameCuEventA_impl_init_v3:
.LFB6302:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	216+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L568
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L568:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6302:
	.size	nvtxNameCuEventA_impl_init_v3, .-nvtxNameCuEventA_impl_init_v3
	.section	.text.nvtxNameCuStreamW_impl_init_v3,"axG",@progbits,nvtxNameCuStreamW_impl_init_v3,comdat
	.weak	nvtxNameCuStreamW_impl_init_v3
	.hidden	nvtxNameCuStreamW_impl_init_v3
	.type	nvtxNameCuStreamW_impl_init_v3, @function
nvtxNameCuStreamW_impl_init_v3:
.LFB6301:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	208+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L571
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L571:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6301:
	.size	nvtxNameCuStreamW_impl_init_v3, .-nvtxNameCuStreamW_impl_init_v3
	.section	.text.nvtxNameCuStreamA_impl_init_v3,"axG",@progbits,nvtxNameCuStreamA_impl_init_v3,comdat
	.weak	nvtxNameCuStreamA_impl_init_v3
	.hidden	nvtxNameCuStreamA_impl_init_v3
	.type	nvtxNameCuStreamA_impl_init_v3, @function
nvtxNameCuStreamA_impl_init_v3:
.LFB6300:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	200+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L574
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L574:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6300:
	.size	nvtxNameCuStreamA_impl_init_v3, .-nvtxNameCuStreamA_impl_init_v3
	.section	.text.nvtxNameCuContextW_impl_init_v3,"axG",@progbits,nvtxNameCuContextW_impl_init_v3,comdat
	.weak	nvtxNameCuContextW_impl_init_v3
	.hidden	nvtxNameCuContextW_impl_init_v3
	.type	nvtxNameCuContextW_impl_init_v3, @function
nvtxNameCuContextW_impl_init_v3:
.LFB6299:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	192+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L577
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L577:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6299:
	.size	nvtxNameCuContextW_impl_init_v3, .-nvtxNameCuContextW_impl_init_v3
	.section	.text.nvtxNameCuContextA_impl_init_v3,"axG",@progbits,nvtxNameCuContextA_impl_init_v3,comdat
	.weak	nvtxNameCuContextA_impl_init_v3
	.hidden	nvtxNameCuContextA_impl_init_v3
	.type	nvtxNameCuContextA_impl_init_v3, @function
nvtxNameCuContextA_impl_init_v3:
.LFB6298:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	184+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L580
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L580:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6298:
	.size	nvtxNameCuContextA_impl_init_v3, .-nvtxNameCuContextA_impl_init_v3
	.section	.text.nvtxNameCuDeviceW_impl_init_v3,"axG",@progbits,nvtxNameCuDeviceW_impl_init_v3,comdat
	.weak	nvtxNameCuDeviceW_impl_init_v3
	.hidden	nvtxNameCuDeviceW_impl_init_v3
	.type	nvtxNameCuDeviceW_impl_init_v3, @function
nvtxNameCuDeviceW_impl_init_v3:
.LFB6297:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	%edi, 12(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	176+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L583
	movq	(%rsp), %rsi
	movl	12(%rsp), %edi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L583:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6297:
	.size	nvtxNameCuDeviceW_impl_init_v3, .-nvtxNameCuDeviceW_impl_init_v3
	.section	.text.nvtxNameCuDeviceA_impl_init_v3,"axG",@progbits,nvtxNameCuDeviceA_impl_init_v3,comdat
	.weak	nvtxNameCuDeviceA_impl_init_v3
	.hidden	nvtxNameCuDeviceA_impl_init_v3
	.type	nvtxNameCuDeviceA_impl_init_v3, @function
nvtxNameCuDeviceA_impl_init_v3:
.LFB6296:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	%edi, 12(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	168+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L586
	movq	(%rsp), %rsi
	movl	12(%rsp), %edi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L586:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6296:
	.size	nvtxNameCuDeviceA_impl_init_v3, .-nvtxNameCuDeviceA_impl_init_v3
	.section	.text.nvtxNameOsThreadW_impl_init_v3,"axG",@progbits,nvtxNameOsThreadW_impl_init_v3,comdat
	.weak	nvtxNameOsThreadW_impl_init_v3
	.hidden	nvtxNameOsThreadW_impl_init_v3
	.type	nvtxNameOsThreadW_impl_init_v3, @function
nvtxNameOsThreadW_impl_init_v3:
.LFB6280:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	%edi, 12(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	160+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L589
	movq	(%rsp), %rsi
	movl	12(%rsp), %edi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L589:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6280:
	.size	nvtxNameOsThreadW_impl_init_v3, .-nvtxNameOsThreadW_impl_init_v3
	.section	.text.nvtxNameOsThreadA_impl_init_v3,"axG",@progbits,nvtxNameOsThreadA_impl_init_v3,comdat
	.weak	nvtxNameOsThreadA_impl_init_v3
	.hidden	nvtxNameOsThreadA_impl_init_v3
	.type	nvtxNameOsThreadA_impl_init_v3, @function
nvtxNameOsThreadA_impl_init_v3:
.LFB6279:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	%edi, 12(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	152+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L592
	movq	(%rsp), %rsi
	movl	12(%rsp), %edi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L592:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6279:
	.size	nvtxNameOsThreadA_impl_init_v3, .-nvtxNameOsThreadA_impl_init_v3
	.section	.text.nvtxNameCategoryW_impl_init_v3,"axG",@progbits,nvtxNameCategoryW_impl_init_v3,comdat
	.weak	nvtxNameCategoryW_impl_init_v3
	.hidden	nvtxNameCategoryW_impl_init_v3
	.type	nvtxNameCategoryW_impl_init_v3, @function
nvtxNameCategoryW_impl_init_v3:
.LFB6278:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	%edi, 12(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	144+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L595
	movq	(%rsp), %rsi
	movl	12(%rsp), %edi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L595:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6278:
	.size	nvtxNameCategoryW_impl_init_v3, .-nvtxNameCategoryW_impl_init_v3
	.section	.text.nvtxNameCategoryA_impl_init_v3,"axG",@progbits,nvtxNameCategoryA_impl_init_v3,comdat
	.weak	nvtxNameCategoryA_impl_init_v3
	.hidden	nvtxNameCategoryA_impl_init_v3
	.type	nvtxNameCategoryA_impl_init_v3, @function
nvtxNameCategoryA_impl_init_v3:
.LFB6277:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	%edi, 12(%rsp)
	movq	%rsi, (%rsp)
	call	nvtxInitOnce_v3
	movq	136+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L598
	movq	(%rsp), %rsi
	movl	12(%rsp), %edi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L598:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6277:
	.size	nvtxNameCategoryA_impl_init_v3, .-nvtxNameCategoryA_impl_init_v3
	.section	.text.nvtxRangePop_impl_init_v3,"axG",@progbits,nvtxRangePop_impl_init_v3,comdat
	.weak	nvtxRangePop_impl_init_v3
	.hidden	nvtxRangePop_impl_init_v3
	.type	nvtxRangePop_impl_init_v3, @function
nvtxRangePop_impl_init_v3:
.LFB6276:
	.cfi_startproc
	endbr64
	pushq	%rsi
	.cfi_def_cfa_offset 16
	call	nvtxInitOnce_v3
	movq	128+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L602
	popq	%rcx
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L602:
	.cfi_restore_state
	movl	$-2, %eax
	popq	%rdx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6276:
	.size	nvtxRangePop_impl_init_v3, .-nvtxRangePop_impl_init_v3
	.section	.text.nvtxRangePushW_impl_init_v3,"axG",@progbits,nvtxRangePushW_impl_init_v3,comdat
	.weak	nvtxRangePushW_impl_init_v3
	.hidden	nvtxRangePushW_impl_init_v3
	.type	nvtxRangePushW_impl_init_v3, @function
nvtxRangePushW_impl_init_v3:
.LFB6275:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	120+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L605
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L605:
	.cfi_restore_state
	movl	$-2, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6275:
	.size	nvtxRangePushW_impl_init_v3, .-nvtxRangePushW_impl_init_v3
	.section	.text.nvtxRangePushA_impl_init_v3,"axG",@progbits,nvtxRangePushA_impl_init_v3,comdat
	.weak	nvtxRangePushA_impl_init_v3
	.hidden	nvtxRangePushA_impl_init_v3
	.type	nvtxRangePushA_impl_init_v3, @function
nvtxRangePushA_impl_init_v3:
.LFB6274:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	112+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L608
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L608:
	.cfi_restore_state
	movl	$-2, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6274:
	.size	nvtxRangePushA_impl_init_v3, .-nvtxRangePushA_impl_init_v3
	.section	.text.nvtxRangePushEx_impl_init_v3,"axG",@progbits,nvtxRangePushEx_impl_init_v3,comdat
	.weak	nvtxRangePushEx_impl_init_v3
	.hidden	nvtxRangePushEx_impl_init_v3
	.type	nvtxRangePushEx_impl_init_v3, @function
nvtxRangePushEx_impl_init_v3:
.LFB6273:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	104+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L611
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L611:
	.cfi_restore_state
	movl	$-2, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6273:
	.size	nvtxRangePushEx_impl_init_v3, .-nvtxRangePushEx_impl_init_v3
	.section	.text.nvtxRangeEnd_impl_init_v3,"axG",@progbits,nvtxRangeEnd_impl_init_v3,comdat
	.weak	nvtxRangeEnd_impl_init_v3
	.hidden	nvtxRangeEnd_impl_init_v3
	.type	nvtxRangeEnd_impl_init_v3, @function
nvtxRangeEnd_impl_init_v3:
.LFB6272:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	96+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L613
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L613:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6272:
	.size	nvtxRangeEnd_impl_init_v3, .-nvtxRangeEnd_impl_init_v3
	.section	.text.nvtxRangeStartW_impl_init_v3,"axG",@progbits,nvtxRangeStartW_impl_init_v3,comdat
	.weak	nvtxRangeStartW_impl_init_v3
	.hidden	nvtxRangeStartW_impl_init_v3
	.type	nvtxRangeStartW_impl_init_v3, @function
nvtxRangeStartW_impl_init_v3:
.LFB6271:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	88+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L617
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L617:
	.cfi_restore_state
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6271:
	.size	nvtxRangeStartW_impl_init_v3, .-nvtxRangeStartW_impl_init_v3
	.section	.text.nvtxRangeStartA_impl_init_v3,"axG",@progbits,nvtxRangeStartA_impl_init_v3,comdat
	.weak	nvtxRangeStartA_impl_init_v3
	.hidden	nvtxRangeStartA_impl_init_v3
	.type	nvtxRangeStartA_impl_init_v3, @function
nvtxRangeStartA_impl_init_v3:
.LFB6270:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	80+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L620
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L620:
	.cfi_restore_state
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6270:
	.size	nvtxRangeStartA_impl_init_v3, .-nvtxRangeStartA_impl_init_v3
	.section	.text.nvtxRangeStartEx_impl_init_v3,"axG",@progbits,nvtxRangeStartEx_impl_init_v3,comdat
	.weak	nvtxRangeStartEx_impl_init_v3
	.hidden	nvtxRangeStartEx_impl_init_v3
	.type	nvtxRangeStartEx_impl_init_v3, @function
nvtxRangeStartEx_impl_init_v3:
.LFB6269:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	72+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L623
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L623:
	.cfi_restore_state
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6269:
	.size	nvtxRangeStartEx_impl_init_v3, .-nvtxRangeStartEx_impl_init_v3
	.section	.text.nvtxMarkW_impl_init_v3,"axG",@progbits,nvtxMarkW_impl_init_v3,comdat
	.weak	nvtxMarkW_impl_init_v3
	.hidden	nvtxMarkW_impl_init_v3
	.type	nvtxMarkW_impl_init_v3, @function
nvtxMarkW_impl_init_v3:
.LFB6268:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	64+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L625
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L625:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6268:
	.size	nvtxMarkW_impl_init_v3, .-nvtxMarkW_impl_init_v3
	.section	.text.nvtxMarkA_impl_init_v3,"axG",@progbits,nvtxMarkA_impl_init_v3,comdat
	.weak	nvtxMarkA_impl_init_v3
	.hidden	nvtxMarkA_impl_init_v3
	.type	nvtxMarkA_impl_init_v3, @function
nvtxMarkA_impl_init_v3:
.LFB6267:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	56+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L628
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L628:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6267:
	.size	nvtxMarkA_impl_init_v3, .-nvtxMarkA_impl_init_v3
	.section	.text.nvtxMarkEx_impl_init_v3,"axG",@progbits,nvtxMarkEx_impl_init_v3,comdat
	.weak	nvtxMarkEx_impl_init_v3
	.hidden	nvtxMarkEx_impl_init_v3
	.type	nvtxMarkEx_impl_init_v3, @function
nvtxMarkEx_impl_init_v3:
.LFB6266:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rdi, 8(%rsp)
	call	nvtxInitOnce_v3
	movq	48+nvtxGlobals_v3(%rip), %rax
	testq	%rax, %rax
	je	.L631
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	jmp	*%rax
.L631:
	.cfi_restore_state
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE6266:
	.size	nvtxMarkEx_impl_init_v3, .-nvtxMarkEx_impl_init_v3
	.text
	.globl	_Z19linearInterpolationf5pointS_
	.type	_Z19linearInterpolationf5pointS_, @function
_Z19linearInterpolationf5pointS_:
.LFB9859:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$56, %rsp
	.cfi_def_cfa_offset 64
	movq	%rdi, 16(%rsp)
	movl	$1, 44(%rsp)
	movl	44(%rsp), %edi
	movq	%rsi, 24(%rsp)
	movq	%rdx, (%rsp)
	movq	%rcx, 8(%rsp)
	call	exit@PLT
	.cfi_endproc
.LFE9859:
	.size	_Z19linearInterpolationf5pointS_, .-_Z19linearInterpolationf5pointS_
	.globl	_Z12gridPosition5uint36float3f
	.type	_Z12gridPosition5uint36float3f, @function
_Z12gridPosition5uint36float3f:
.LFB9863:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$56, %rsp
	.cfi_def_cfa_offset 64
	movq	%rdi, 16(%rsp)
	movl	$1, 44(%rsp)
	movl	44(%rsp), %edi
	movl	%esi, 24(%rsp)
	movq	%xmm0, (%rsp)
	movss	%xmm1, 8(%rsp)
	call	exit@PLT
	.cfi_endproc
.LFE9863:
	.size	_Z12gridPosition5uint36float3f, .-_Z12gridPosition5uint36float3f
	.globl	_Z10grid1DTo3Dj4int3
	.type	_Z10grid1DTo3Dj4int3, @function
_Z10grid1DTo3Dj4int3:
.LFB9864:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movl	$1, 28(%rsp)
	movl	28(%rsp), %edi
	movq	%rsi, (%rsp)
	movl	%edx, 8(%rsp)
	call	exit@PLT
	.cfi_endproc
.LFE9864:
	.size	_Z10grid1DTo3Dj4int3, .-_Z10grid1DTo3Dj4int3
	.globl	_Z12vertexInterpf6float3S_ff
	.type	_Z12vertexInterpf6float3S_ff, @function
_Z12vertexInterpf6float3S_ff:
.LFB9865:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$56, %rsp
	.cfi_def_cfa_offset 64
	movl	$1, 44(%rsp)
	movl	44(%rsp), %edi
	movq	%xmm1, 16(%rsp)
	movss	%xmm2, 24(%rsp)
	movq	%xmm3, (%rsp)
	movss	%xmm4, 8(%rsp)
	call	exit@PLT
	.cfi_endproc
.LFE9865:
	.size	_Z12vertexInterpf6float3S_ff, .-_Z12vertexInterpf6float3S_ff
	.globl	_Z11spaceToGrid6float3S_f
	.type	_Z11spaceToGrid6float3S_f, @function
_Z11spaceToGrid6float3S_f:
.LFB9876:
	.cfi_startproc
	endbr64
	movq	%xmm0, -40(%rsp)
	movss	-36(%rsp), %xmm0
	subss	%xmm3, %xmm1
	movq	%xmm2, -56(%rsp)
	subss	-52(%rsp), %xmm0
	divss	%xmm4, %xmm1
	divss	%xmm4, %xmm0
	cvttss2sil	%xmm1, %edx
	movl	%edx, %edx
	cvttss2sil	%xmm0, %eax
	movss	-40(%rsp), %xmm0
	subss	-56(%rsp), %xmm0
	divss	%xmm4, %xmm0
	movl	%eax, -16(%rsp)
	cvttss2sil	%xmm0, %ecx
	movl	%ecx, -20(%rsp)
	movq	-20(%rsp), %rax
	ret
	.cfi_endproc
.LFE9876:
	.size	_Z11spaceToGrid6float3S_f, .-_Z11spaceToGrid6float3S_f
	.globl	_Z11gridToSpace4int36float3f
	.type	_Z11gridToSpace4int36float3f, @function
_Z11gridToSpace4int36float3f:
.LFB9877:
	.cfi_startproc
	endbr64
	cvtsi2ssl	%esi, %xmm4
	movq	%xmm0, -56(%rsp)
	movq	%rdi, -40(%rsp)
	cvtsi2ssl	-36(%rsp), %xmm0
	cvtsi2ssl	-40(%rsp), %xmm3
	mulss	%xmm2, %xmm4
	mulss	%xmm2, %xmm0
	mulss	%xmm2, %xmm3
	addss	-52(%rsp), %xmm0
	addss	-56(%rsp), %xmm3
	addss	%xmm4, %xmm1
	movss	%xmm0, -16(%rsp)
	movss	%xmm3, -20(%rsp)
	movq	-20(%rsp), %xmm0
	ret
	.cfi_endproc
.LFE9877:
	.size	_Z11gridToSpace4int36float3f, .-_Z11gridToSpace4int36float3f
	.globl	_Z13flatten3DTo1D4int3S_
	.type	_Z13flatten3DTo1D4int3S_, @function
_Z13flatten3DTo1D4int3S_:
.LFB9878:
	.cfi_startproc
	endbr64
	movq	%rdx, -32(%rsp)
	movl	-28(%rsp), %eax
	movq	%rdi, -16(%rsp)
	imull	%ecx, %eax
	imull	-12(%rsp), %ecx
	imull	%edi, %eax
	addl	%ecx, %eax
	addl	%esi, %eax
	ret
	.cfi_endproc
.LFE9878:
	.size	_Z13flatten3DTo1D4int3S_, .-_Z13flatten3DTo1D4int3S_
	.globl	_Z15unflatten1DTo3Di4int3
	.type	_Z15unflatten1DTo3Di4int3, @function
_Z15unflatten1DTo3Di4int3:
.LFB9879:
	.cfi_startproc
	endbr64
	movq	%rsi, -40(%rsp)
	movl	-36(%rsp), %esi
	movl	%edi, %eax
	movl	%edx, %ecx
	movl	%esi, %r8d
	imull	%edx, %r8d
	cltd
	idivl	%r8d
	imull	%eax, %esi
	movl	%eax, %r8d
	movl	%edi, %eax
	movl	%r8d, -20(%rsp)
	imull	%ecx, %esi
	subl	%esi, %eax
	cltd
	idivl	%ecx
	movl	%eax, -16(%rsp)
	movl	%edx, %edx
	movq	-20(%rsp), %rax
	ret
	.cfi_endproc
.LFE9879:
	.size	_Z15unflatten1DTo3Di4int3, .-_Z15unflatten1DTo3Di4int3
	.globl	_Z55__device_stub__Z18countVertexPerCellf4int3PKfP5uint2iS_fRK4int3PKfP5uint2iS1_
	.type	_Z55__device_stub__Z18countVertexPerCellf4int3PKfP5uint2iS_fRK4int3PKfP5uint2iS1_, @function
_Z55__device_stub__Z18countVertexPerCellf4int3PKfP5uint2iS_fRK4int3PKfP5uint2iS1_:
.LFB9914:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 24(%rsp)
	leaq	40(%rsp), %rcx
	movss	%xmm0, 28(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movq	%rdi, 80(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rax, 72(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	movabsq	$4294967297, %rax
	movq	%r8, 112(%rsp)
	movq	%rax, 48(%rsp)
	movl	$1, 56(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L646
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z18countVertexPerCellf4int3PKfP5uint2iS_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	88(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L646:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L648
	call	__stack_chk_fail@PLT
.L648:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE9914:
	.size	_Z55__device_stub__Z18countVertexPerCellf4int3PKfP5uint2iS_fRK4int3PKfP5uint2iS1_, .-_Z55__device_stub__Z18countVertexPerCellf4int3PKfP5uint2iS_fRK4int3PKfP5uint2iS1_
	.globl	_Z18countVertexPerCellf4int3PKfP5uint2iS_
	.type	_Z18countVertexPerCellf4int3PKfP5uint2iS_, @function
_Z18countVertexPerCellf4int3PKfP5uint2iS_:
.LFB9915:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	%esi, %eax
	movq	%rdx, %rsi
	movq	%rcx, %rdx
	movq	%rdi, (%rsp)
	movl	%r8d, %ecx
	movq	%rsp, %rdi
	leaq	32(%rsp), %r8
	movl	%eax, 8(%rsp)
	call	_Z55__device_stub__Z18countVertexPerCellf4int3PKfP5uint2iS_fRK4int3PKfP5uint2iS1_
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE9915:
	.size	_Z18countVertexPerCellf4int3PKfP5uint2iS_, .-_Z18countVertexPerCellf4int3PKfP5uint2iS_
	.globl	_Z53__device_stub__Z13compactVoxelsPjPK5uint2jjj4int3iS3_PjPK5uint2jjjR4int3iRKS3_
	.type	_Z53__device_stub__Z13compactVoxelsPjPK5uint2jjj4int3iS3_PjPK5uint2jjjR4int3iRKS3_, @function
_Z53__device_stub__Z13compactVoxelsPjPK5uint2jjj4int3iS3_PjPK5uint2jjjR4int3iRKS3_:
.LFB9916:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movq	%r9, 112(%rsp)
	movq	%rax, 72(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 80(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	160(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	168(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L652
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z13compactVoxelsPjPK5uint2jjj4int3iS3_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	88(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L652:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L654
	call	__stack_chk_fail@PLT
.L654:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE9916:
	.size	_Z53__device_stub__Z13compactVoxelsPjPK5uint2jjj4int3iS3_PjPK5uint2jjjR4int3iRKS3_, .-_Z53__device_stub__Z13compactVoxelsPjPK5uint2jjj4int3iS3_PjPK5uint2jjjR4int3iRKS3_
	.globl	_Z13compactVoxelsPjPK5uint2jjj4int3iS3_
	.type	_Z13compactVoxelsPjPK5uint2jjj4int3iS3_, @function
_Z13compactVoxelsPjPK5uint2jjj4int3iS3_:
.LFB9917:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	32(%rsp), %rax
	pushq	%rax
	.cfi_def_cfa_offset 24
	pushq	%r9
	.cfi_def_cfa_offset 32
	leaq	32(%rsp), %r9
	call	_Z53__device_stub__Z13compactVoxelsPjPK5uint2jjj4int3iS3_PjPK5uint2jjjR4int3iRKS3_
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE9917:
	.size	_Z13compactVoxelsPjPK5uint2jjj4int3iS3_, .-_Z13compactVoxelsPjPK5uint2jjj4int3iS3_
	.globl	_Z86__device_stub__Z28generateTriangleVerticesSMEMP6float3PKjPK5uint2PKf6float4fjj4int3S9_P6float3PKjPK5uint2PKfR6float4fjjR4int3SB_
	.type	_Z86__device_stub__Z28generateTriangleVerticesSMEMP6float3PKjPK5uint2PKf6float4fjj4int3S9_P6float3PKjPK5uint2PKfR6float4fjjR4int3SB_, @function
_Z86__device_stub__Z28generateTriangleVerticesSMEMP6float3PKjPK5uint2PKf6float4fjj4int3S9_P6float3PKjPK5uint2PKfR6float4fjjR4int3SB_:
.LFB9918:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r9d, 8(%rsp)
	movss	%xmm0, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movq	%r8, 120(%rsp)
	movq	%rax, 88(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	192(%rsp), %rax
	movq	%rax, 144(%rsp)
	movq	200(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 152(%rsp)
	movq	208(%rsp), %rax
	movl	$1, 84(%rsp)
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L658
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z28generateTriangleVerticesSMEMP6float3PKjPK5uint2PKf6float4fjj4int3S9_(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	104(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L658:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L660
	call	__stack_chk_fail@PLT
.L660:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE9918:
	.size	_Z86__device_stub__Z28generateTriangleVerticesSMEMP6float3PKjPK5uint2PKf6float4fjj4int3S9_P6float3PKjPK5uint2PKfR6float4fjjR4int3SB_, .-_Z86__device_stub__Z28generateTriangleVerticesSMEMP6float3PKjPK5uint2PKf6float4fjj4int3S9_P6float3PKjPK5uint2PKfR6float4fjjR4int3SB_
	.globl	_Z28generateTriangleVerticesSMEMP6float3PKjPK5uint2PKf6float4fjj4int3S9_
	.type	_Z28generateTriangleVerticesSMEMP6float3PKjPK5uint2PKf6float4fjj4int3S9_, @function
_Z28generateTriangleVerticesSMEMP6float3PKjPK5uint2PKf6float4fjj4int3S9_:
.LFB9919:
	.cfi_startproc
	endbr64
	subq	$32, %rsp
	.cfi_def_cfa_offset 40
	leaq	56(%rsp), %rax
	movq	%xmm0, 8(%rsp)
	movaps	%xmm2, %xmm0
	movq	%xmm1, 16(%rsp)
	pushq	%rax
	.cfi_def_cfa_offset 48
	leaq	48(%rsp), %rax
	pushq	%rax
	.cfi_def_cfa_offset 56
	pushq	%r9
	.cfi_def_cfa_offset 64
	movl	%r8d, %r9d
	leaq	32(%rsp), %r8
	call	_Z86__device_stub__Z28generateTriangleVerticesSMEMP6float3PKjPK5uint2PKf6float4fjj4int3S9_P6float3PKjPK5uint2PKfR6float4fjjR4int3SB_
	addq	$56, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE9919:
	.size	_Z28generateTriangleVerticesSMEMP6float3PKjPK5uint2PKf6float4fjj4int3S9_, .-_Z28generateTriangleVerticesSMEMP6float3PKjPK5uint2PKf6float4fjj4int3S9_
	.globl	_Z41__device_stub__Z13groupVerticesP6float3jfP6float3jf
	.type	_Z41__device_stub__Z13groupVerticesP6float3jfP6float3jf, @function
_Z41__device_stub__Z13groupVerticesP6float3jfP6float3jf:
.LFB9920:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movl	%esi, 4(%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movss	%xmm0, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 64(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 72(%rsp)
	movq	%rsp, %rax
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L664
	pushq	32(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z13groupVerticesP6float3jf(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 128
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	80(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L664:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L666
	call	__stack_chk_fail@PLT
.L666:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE9920:
	.size	_Z41__device_stub__Z13groupVerticesP6float3jfP6float3jf, .-_Z41__device_stub__Z13groupVerticesP6float3jfP6float3jf
	.globl	_Z13groupVerticesP6float3jf
	.type	_Z13groupVerticesP6float3jf, @function
_Z13groupVerticesP6float3jf:
.LFB9921:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z13groupVerticesP6float3jfP6float3jf
	.cfi_endproc
.LFE9921:
	.size	_Z13groupVerticesP6float3jf, .-_Z13groupVerticesP6float3jf
	.globl	_Z46__device_stub__Z15LaplacianSmoothP6float3PijjjP6float3Pijjj
	.type	_Z46__device_stub__Z15LaplacianSmoothP6float3PijjjP6float3Pijjj, @function
_Z46__device_stub__Z15LaplacianSmoothP6float3PijjjP6float3Pijjj:
.LFB9922:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L669
	pushq	48(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z15LaplacianSmoothP6float3Pijjj(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 160
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L669:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L671
	call	__stack_chk_fail@PLT
.L671:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE9922:
	.size	_Z46__device_stub__Z15LaplacianSmoothP6float3PijjjP6float3Pijjj, .-_Z46__device_stub__Z15LaplacianSmoothP6float3PijjjP6float3Pijjj
	.globl	_Z15LaplacianSmoothP6float3Pijjj
	.type	_Z15LaplacianSmoothP6float3Pijjj, @function
_Z15LaplacianSmoothP6float3Pijjj:
.LFB9923:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z15LaplacianSmoothP6float3PijjjP6float3Pijjj
	.cfi_endproc
.LFE9923:
	.size	_Z15LaplacianSmoothP6float3Pijjj, .-_Z15LaplacianSmoothP6float3Pijjj
	.globl	_Z37__device_stub__Z15memsetCudaFloatPffiPffi
	.type	_Z37__device_stub__Z15memsetCudaFloatPffiPffi, @function
_Z37__device_stub__Z15memsetCudaFloatPffiPffi:
.LFB9924:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movl	%esi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movss	%xmm0, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 64(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 72(%rsp)
	movq	%rsp, %rax
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L674
	pushq	32(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z15memsetCudaFloatPffi(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 128
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	80(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L674:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L676
	call	__stack_chk_fail@PLT
.L676:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE9924:
	.size	_Z37__device_stub__Z15memsetCudaFloatPffiPffi, .-_Z37__device_stub__Z15memsetCudaFloatPffiPffi
	.globl	_Z15memsetCudaFloatPffi
	.type	_Z15memsetCudaFloatPffi, @function
_Z15memsetCudaFloatPffi:
.LFB9925:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z15memsetCudaFloatPffiPffi
	.cfi_endproc
.LFE9925:
	.size	_Z15memsetCudaFloatPffi, .-_Z15memsetCudaFloatPffi
	.globl	_Z35__device_stub__Z13memsetCudaIntPiiiPiii
	.type	_Z35__device_stub__Z13memsetCudaIntPiiiPiii, @function
_Z35__device_stub__Z13memsetCudaIntPiiiPiii:
.LFB9926:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	40(%rsp), %rdi
	movl	%esi, 4(%rsp)
	leaq	52(%rsp), %rsi
	movl	%edx, (%rsp)
	leaq	24(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 64(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 72(%rsp)
	movq	%rsp, %rax
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L679
	pushq	32(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z13memsetCudaIntPiii(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 128
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	80(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L679:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L681
	call	__stack_chk_fail@PLT
.L681:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE9926:
	.size	_Z35__device_stub__Z13memsetCudaIntPiiiPiii, .-_Z35__device_stub__Z13memsetCudaIntPiiiPiii
	.globl	_Z13memsetCudaIntPiii
	.type	_Z13memsetCudaIntPiii, @function
_Z13memsetCudaIntPiii:
.LFB9927:
	.cfi_startproc
	endbr64
	jmp	_Z35__device_stub__Z13memsetCudaIntPiiiPiii
	.cfi_endproc
.LFE9927:
	.size	_Z13memsetCudaIntPiii, .-_Z13memsetCudaIntPiii
	.globl	_Z41__device_stub__Z14memsetCudaInt2P4int2S_iP4int2RS_i
	.type	_Z41__device_stub__Z14memsetCudaInt2P4int2S_iP4int2RS_i, @function
_Z41__device_stub__Z14memsetCudaInt2P4int2S_iP4int2RS_i:
.LFB9928:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	40(%rsp), %rdi
	movl	%edx, 4(%rsp)
	leaq	24(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movq	%rsi, 72(%rsp)
	leaq	52(%rsp), %rsi
	movq	%rax, 64(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movl	$1, 48(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L684
	pushq	32(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z14memsetCudaInt2P4int2S_i(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 128
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	80(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L684:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L686
	call	__stack_chk_fail@PLT
.L686:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE9928:
	.size	_Z41__device_stub__Z14memsetCudaInt2P4int2S_iP4int2RS_i, .-_Z41__device_stub__Z14memsetCudaInt2P4int2S_iP4int2RS_i
	.globl	_Z14memsetCudaInt2P4int2S_i
	.type	_Z14memsetCudaInt2P4int2S_i, @function
_Z14memsetCudaInt2P4int2S_i:
.LFB9929:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rsi, 8(%rsp)
	leaq	8(%rsp), %rsi
	call	_Z41__device_stub__Z14memsetCudaInt2P4int2S_iP4int2RS_i
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE9929:
	.size	_Z14memsetCudaInt2P4int2S_i, .-_Z14memsetCudaInt2P4int2S_i
	.globl	_Z43__device_stub__Z15memsetCudaUInt2P5uint2S_iP5uint2RS_i
	.type	_Z43__device_stub__Z15memsetCudaUInt2P5uint2S_iP5uint2RS_i, @function
_Z43__device_stub__Z15memsetCudaUInt2P5uint2S_iP5uint2RS_i:
.LFB9930:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	40(%rsp), %rdi
	movl	%edx, 4(%rsp)
	leaq	24(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movq	%rsi, 72(%rsp)
	leaq	52(%rsp), %rsi
	movq	%rax, 64(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movl	$1, 48(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L690
	pushq	32(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z15memsetCudaUInt2P5uint2S_i(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 128
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	80(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L690:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L692
	call	__stack_chk_fail@PLT
.L692:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE9930:
	.size	_Z43__device_stub__Z15memsetCudaUInt2P5uint2S_iP5uint2RS_i, .-_Z43__device_stub__Z15memsetCudaUInt2P5uint2S_iP5uint2RS_i
	.globl	_Z15memsetCudaUInt2P5uint2S_i
	.type	_Z15memsetCudaUInt2P5uint2S_i, @function
_Z15memsetCudaUInt2P5uint2S_i:
.LFB9931:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%rsi, 8(%rsp)
	leaq	8(%rsp), %rsi
	call	_Z43__device_stub__Z15memsetCudaUInt2P5uint2S_iP5uint2RS_i
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE9931:
	.size	_Z15memsetCudaUInt2P5uint2S_i, .-_Z15memsetCudaUInt2P5uint2S_i
	.globl	_Z49__device_stub__Z9hashAtomsjP6float44int3S_P4int2jjP6float4R4int3RS_P4int2j
	.type	_Z49__device_stub__Z9hashAtomsjP6float44int3S_P4int2jjP6float4R4int3RS_P4int2j, @function
_Z49__device_stub__Z9hashAtomsjP6float44int3S_P4int2jjP6float4R4int3RS_P4int2j:
.LFB9932:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movl	%edi, 28(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%r8, 8(%rsp)
	movl	%r9d, 24(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movq	%rdx, 88(%rsp)
	leaq	32(%rsp), %rdx
	movq	%rax, 72(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 80(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	24(%rsp), %rax
	movq	%rcx, 96(%rsp)
	leaq	40(%rsp), %rcx
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movl	$1, 56(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L696
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z9hashAtomsjP6float44int3S_P4int2j(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	88(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L696:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L698
	call	__stack_chk_fail@PLT
.L698:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE9932:
	.size	_Z49__device_stub__Z9hashAtomsjP6float44int3S_P4int2jjP6float4R4int3RS_P4int2j, .-_Z49__device_stub__Z9hashAtomsjP6float44int3S_P4int2jjP6float4R4int3RS_P4int2j
	.globl	_Z9hashAtomsjP6float44int3S_P4int2j
	.type	_Z9hashAtomsjP6float44int3S_P4int2j, @function
_Z9hashAtomsjP6float44int3S_P4int2j:
.LFB9933:
	.cfi_startproc
	endbr64
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	%rdx, 16(%rsp)
	leaq	16(%rsp), %rdx
	movl	%ecx, 24(%rsp)
	movq	%rsp, %rcx
	movq	%xmm0, (%rsp)
	movq	%xmm1, 8(%rsp)
	call	_Z49__device_stub__Z9hashAtomsjP6float44int3S_P4int2jjP6float4R4int3RS_P4int2j
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE9933:
	.size	_Z9hashAtomsjP6float44int3S_P4int2j, .-_Z9hashAtomsjP6float44int3S_P4int2j
	.globl	_Z46__device_stub__Z19bitonic_pass_kernelP4int2iiiP4int2iii
	.type	_Z46__device_stub__Z19bitonic_pass_kernelP4int2iiiP4int2iii, @function
_Z46__device_stub__Z19bitonic_pass_kernelP4int2iiiP4int2iii:
.LFB9934:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	40(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 72(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L702
	pushq	40(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z19bitonic_pass_kernelP4int2iii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 144
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	88(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L702:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L704
	call	__stack_chk_fail@PLT
.L704:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE9934:
	.size	_Z46__device_stub__Z19bitonic_pass_kernelP4int2iiiP4int2iii, .-_Z46__device_stub__Z19bitonic_pass_kernelP4int2iiiP4int2iii
	.globl	_Z19bitonic_pass_kernelP4int2iii
	.type	_Z19bitonic_pass_kernelP4int2iii, @function
_Z19bitonic_pass_kernelP4int2iii:
.LFB9935:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z19bitonic_pass_kernelP4int2iiiP4int2iii
	.cfi_endproc
.LFE9935:
	.size	_Z19bitonic_pass_kernelP4int2iii, .-_Z19bitonic_pass_kernelP4int2iii
	.globl	_Z38__device_stub__Z11bitonic_512P4int2iiiP4int2iii
	.type	_Z38__device_stub__Z11bitonic_512P4int2iiiP4int2iii, @function
_Z38__device_stub__Z11bitonic_512P4int2iiiP4int2iii:
.LFB9936:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	40(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 72(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L707
	pushq	40(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z11bitonic_512P4int2iii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 144
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	88(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L707:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L709
	call	__stack_chk_fail@PLT
.L709:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE9936:
	.size	_Z38__device_stub__Z11bitonic_512P4int2iiiP4int2iii, .-_Z38__device_stub__Z11bitonic_512P4int2iiiP4int2iii
	.globl	_Z11bitonic_512P4int2iii
	.type	_Z11bitonic_512P4int2iii, @function
_Z11bitonic_512P4int2iii:
.LFB9937:
	.cfi_startproc
	endbr64
	jmp	_Z38__device_stub__Z11bitonic_512P4int2iiiP4int2iii
	.cfi_endproc
.LFE9937:
	.size	_Z11bitonic_512P4int2iii, .-_Z11bitonic_512P4int2iii
	.globl	_Z46__device_stub__Z8sortCelljP6float4P4int2S0_S2_jP6float4P4int2S0_S2_
	.type	_Z46__device_stub__Z8sortCelljP6float4P4int2S0_S2_jP6float4P4int2S0_S2_, @function
_Z46__device_stub__Z8sortCelljP6float4P4int2S0_S2_jP6float4P4int2S0_S2_:
.LFB9938:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movl	%edi, 44(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 96(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L712
	pushq	64(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z8sortCelljP6float4P4int2S0_S2_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 176
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	112(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L712:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L714
	call	__stack_chk_fail@PLT
.L714:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE9938:
	.size	_Z46__device_stub__Z8sortCelljP6float4P4int2S0_S2_jP6float4P4int2S0_S2_, .-_Z46__device_stub__Z8sortCelljP6float4P4int2S0_S2_jP6float4P4int2S0_S2_
	.globl	_Z8sortCelljP6float4P4int2S0_S2_
	.type	_Z8sortCelljP6float4P4int2S0_S2_, @function
_Z8sortCelljP6float4P4int2S0_S2_:
.LFB9939:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z8sortCelljP6float4P4int2S0_S2_jP6float4P4int2S0_S2_
	.cfi_endproc
.LFE9939:
	.size	_Z8sortCelljP6float4P4int2S0_S2_, .-_Z8sortCelljP6float4P4int2S0_S2_
	.globl	_Z78__device_stub__Z17probeIntersectionPiP4int24int36float4S2_S2_S3_S1_PS3_PfS2_jiPiP4int2R4int3R6float4S3_S3_S5_S1_PS4_PfS3_ji
	.type	_Z78__device_stub__Z17probeIntersectionPiP4int24int36float4S2_S2_S3_S1_PS3_PfS2_jiPiP4int2R4int3R6float4S3_S3_S5_S1_PS4_PfS3_ji, @function
_Z78__device_stub__Z17probeIntersectionPiP4int24int36float4S2_S2_S3_S1_PS3_PfS2_jiPiP4int2R4int3R6float4S3_S3_S5_S1_PS4_PfS3_ji:
.LFB9940:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	232(%rsp), %rax
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rax, 24(%rsp)
	movq	240(%rsp), %rax
	movq	%rax, 16(%rsp)
	movq	248(%rsp), %rax
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movq	%rdx, 112(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rax, 96(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 104(%rsp)
	movq	224(%rsp), %rax
	movq	%rcx, 120(%rsp)
	leaq	64(%rsp), %rcx
	movq	%rax, 144(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 168(%rsp)
	movq	256(%rsp), %rax
	movq	%r8, 128(%rsp)
	movq	%rax, 176(%rsp)
	leaq	264(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%r9, 136(%rsp)
	movq	%rax, 72(%rsp)
	movl	$1, 80(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L717
	pushq	64(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z17probeIntersectionPiP4int24int36float4S2_S2_S3_S1_PS3_PfS2_ji(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 240
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	112(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L717:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L719
	call	__stack_chk_fail@PLT
.L719:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE9940:
	.size	_Z78__device_stub__Z17probeIntersectionPiP4int24int36float4S2_S2_S3_S1_PS3_PfS2_jiPiP4int2R4int3R6float4S3_S3_S5_S1_PS4_PfS3_ji, .-_Z78__device_stub__Z17probeIntersectionPiP4int24int36float4S2_S2_S3_S1_PS3_PfS2_jiPiP4int2R4int3R6float4S3_S3_S5_S1_PS4_PfS3_ji
	.globl	_Z17probeIntersectionPiP4int24int36float4S2_S2_S3_S1_PS3_PfS2_ji
	.type	_Z17probeIntersectionPiP4int24int36float4S2_S2_S3_S1_PS3_PfS2_ji, @function
_Z17probeIntersectionPiP4int24int36float4S2_S2_S3_S1_PS3_PfS2_ji:
.LFB9941:
	.cfi_startproc
	endbr64
	subq	$72, %rsp
	.cfi_def_cfa_offset 80
	movq	%rdx, 48(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 56(%rsp)
	leaq	32(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movl	%r9d, 24(%rsp)
	movq	%xmm0, 32(%rsp)
	movq	%xmm1, 40(%rsp)
	movq	%xmm2, (%rsp)
	movq	%xmm3, 8(%rsp)
	pushq	%rax
	.cfi_def_cfa_offset 88
	movl	152(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 96
	movl	152(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 104
	leaq	144(%rsp), %rax
	pushq	%rax
	.cfi_def_cfa_offset 112
	pushq	144(%rsp)
	.cfi_def_cfa_offset 120
	pushq	144(%rsp)
	.cfi_def_cfa_offset 128
	pushq	144(%rsp)
	.cfi_def_cfa_offset 136
	leaq	56(%rsp), %rax
	pushq	%rax
	.cfi_def_cfa_offset 144
	leaq	144(%rsp), %r9
	leaq	80(%rsp), %r8
	call	_Z78__device_stub__Z17probeIntersectionPiP4int24int36float4S2_S2_S3_S1_PS3_PfS2_jiPiP4int2R4int3R6float4S3_S3_S5_S1_PS4_PfS3_ji
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE9941:
	.size	_Z17probeIntersectionPiP4int24int36float4S2_S2_S3_S1_PS3_PfS2_ji, .-_Z17probeIntersectionPiP4int24int36float4S2_S2_S3_S1_PS3_PfS2_ji
	.globl	_Z81__device_stub__Z19distanceFieldRefinePiP4int24int36float4S2_S2_S3_S1_PS3_PfjjS2_jPiP4int2R4int3R6float4S3_S3_S5_S1_PS4_PfjjS3_j
	.type	_Z81__device_stub__Z19distanceFieldRefinePiP4int24int36float4S2_S2_S3_S1_PS3_PfjjS2_jPiP4int2R4int3R6float4S3_S3_S5_S1_PS4_PfjjS3_j, @function
_Z81__device_stub__Z19distanceFieldRefinePiP4int24int36float4S2_S2_S3_S1_PS3_PfjjS2_jPiP4int2R4int3R6float4S3_S3_S5_S1_PS4_PfjjS3_j:
.LFB9942:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	232(%rsp), %rax
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rax, 24(%rsp)
	movq	240(%rsp), %rax
	movq	%rax, 16(%rsp)
	movq	248(%rsp), %rax
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movq	%rdx, 104(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rax, 88(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 96(%rsp)
	movq	224(%rsp), %rax
	movq	%rcx, 112(%rsp)
	leaq	56(%rsp), %rcx
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	264(%rsp), %rax
	movq	%rax, 176(%rsp)
	movq	272(%rsp), %rax
	movq	%r8, 120(%rsp)
	movq	%rax, 184(%rsp)
	leaq	280(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%r9, 128(%rsp)
	movq	%rax, 64(%rsp)
	movl	$1, 72(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L723
	pushq	56(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z19distanceFieldRefinePiP4int24int36float4S2_S2_S3_S1_PS3_PfjjS2_j(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 240
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	104(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L723:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L725
	call	__stack_chk_fail@PLT
.L725:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE9942:
	.size	_Z81__device_stub__Z19distanceFieldRefinePiP4int24int36float4S2_S2_S3_S1_PS3_PfjjS2_jPiP4int2R4int3R6float4S3_S3_S5_S1_PS4_PfjjS3_j, .-_Z81__device_stub__Z19distanceFieldRefinePiP4int24int36float4S2_S2_S3_S1_PS3_PfjjS2_jPiP4int2R4int3R6float4S3_S3_S5_S1_PS4_PfjjS3_j
	.globl	_Z19distanceFieldRefinePiP4int24int36float4S2_S2_S3_S1_PS3_PfjjS2_j
	.type	_Z19distanceFieldRefinePiP4int24int36float4S2_S2_S3_S1_PS3_PfjjS2_j, @function
_Z19distanceFieldRefinePiP4int24int36float4S2_S2_S3_S1_PS3_PfjjS2_j:
.LFB9943:
	.cfi_startproc
	endbr64
	subq	$72, %rsp
	.cfi_def_cfa_offset 80
	movl	152(%rsp), %eax
	movq	%rdx, 48(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 56(%rsp)
	leaq	32(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movl	%r9d, 24(%rsp)
	movq	%xmm0, 32(%rsp)
	movq	%xmm1, 40(%rsp)
	movq	%xmm2, (%rsp)
	movq	%xmm3, 8(%rsp)
	pushq	%rax
	.cfi_def_cfa_offset 88
	leaq	144(%rsp), %rax
	pushq	%rax
	.cfi_def_cfa_offset 96
	movl	144(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 104
	movl	144(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 112
	pushq	144(%rsp)
	.cfi_def_cfa_offset 120
	pushq	144(%rsp)
	.cfi_def_cfa_offset 128
	pushq	144(%rsp)
	.cfi_def_cfa_offset 136
	leaq	56(%rsp), %rax
	pushq	%rax
	.cfi_def_cfa_offset 144
	leaq	144(%rsp), %r9
	leaq	80(%rsp), %r8
	call	_Z81__device_stub__Z19distanceFieldRefinePiP4int24int36float4S2_S2_S3_S1_PS3_PfjjS2_jPiP4int2R4int3R6float4S3_S3_S5_S1_PS4_PfjjS3_j
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE9943:
	.size	_Z19distanceFieldRefinePiP4int24int36float4S2_S2_S3_S1_PS3_PfjjS2_j, .-_Z19distanceFieldRefinePiP4int24int36float4S2_S2_S3_S1_PS3_PfjjS2_j
	.globl	_Z74__device_stub__Z20closestAtomPerVertexPiP6float3j4int36float4S3_P4int2PS3_PiP6float3jR4int3R6float4S5_P4int2PS4_
	.type	_Z74__device_stub__Z20closestAtomPerVertexPiP6float3j4int36float4S3_P4int2PS3_PiP6float3jR4int3R6float4S5_P4int2PS4_, @function
_Z74__device_stub__Z20closestAtomPerVertexPiP6float3j4int36float4S3_P4int2PS3_PiP6float3jR4int3R6float4S5_P4int2PS4_:
.LFB9944:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	176(%rsp), %rax
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rax, 16(%rsp)
	movq	184(%rsp), %rax
	movl	%edx, 28(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movq	%rcx, 112(%rsp)
	leaq	56(%rsp), %rcx
	movq	%rax, 88(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 96(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%r8, 120(%rsp)
	movq	%r9, 128(%rsp)
	movq	%rax, 64(%rsp)
	movl	$1, 72(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L729
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z20closestAtomPerVertexPiP6float3j4int36float4S3_P4int2PS3_(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	104(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L729:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L731
	call	__stack_chk_fail@PLT
.L731:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE9944:
	.size	_Z74__device_stub__Z20closestAtomPerVertexPiP6float3j4int36float4S3_P4int2PS3_PiP6float3jR4int3R6float4S5_P4int2PS4_, .-_Z74__device_stub__Z20closestAtomPerVertexPiP6float3j4int36float4S3_P4int2PS3_PiP6float3jR4int3R6float4S5_P4int2PS4_
	.globl	_Z20closestAtomPerVertexPiP6float3j4int36float4S3_P4int2PS3_
	.type	_Z20closestAtomPerVertexPiP6float3j4int36float4S3_P4int2PS3_, @function
_Z20closestAtomPerVertexPiP6float3j4int36float4S3_P4int2PS3_:
.LFB9945:
	.cfi_startproc
	endbr64
	subq	$56, %rsp
	.cfi_def_cfa_offset 64
	movq	%rcx, 32(%rsp)
	leaq	32(%rsp), %rcx
	movl	%r8d, 40(%rsp)
	movq	%xmm0, 16(%rsp)
	movq	%xmm1, 24(%rsp)
	movq	%xmm2, (%rsp)
	movq	%xmm3, 8(%rsp)
	pushq	64(%rsp)
	.cfi_def_cfa_offset 72
	pushq	%r9
	.cfi_def_cfa_offset 80
	leaq	16(%rsp), %r9
	leaq	32(%rsp), %r8
	call	_Z74__device_stub__Z20closestAtomPerVertexPiP6float3j4int36float4S3_P4int2PS3_PiP6float3jR4int3R6float4S5_P4int2PS4_
	addq	$72, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE9945:
	.size	_Z20closestAtomPerVertexPiP6float3j4int36float4S3_P4int2PS3_, .-_Z20closestAtomPerVertexPiP6float3j4int36float4S3_P4int2PS3_
	.globl	_Z48__device_stub__Z20resetGridValuesSlice4int3iS_PfRK4int3iS1_Pf
	.type	_Z48__device_stub__Z20resetGridValuesSlice4int3iS_PfRK4int3iS1_Pf, @function
_Z48__device_stub__Z20resetGridValuesSlice4int3iS_PfRK4int3iS1_Pf:
.LFB9946:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movl	%esi, 12(%rsp)
	leaq	44(%rsp), %rsi
	movq	%rcx, (%rsp)
	leaq	24(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	32(%rsp), %rdi
	movq	%rax, 64(%rsp)
	movq	%rsp, %rax
	movq	%rdx, 72(%rsp)
	leaq	16(%rsp), %rdx
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movl	$1, 40(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L735
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z20resetGridValuesSlice4int3iS_Pf(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	72(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L735:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L737
	call	__stack_chk_fail@PLT
.L737:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE9946:
	.size	_Z48__device_stub__Z20resetGridValuesSlice4int3iS_PfRK4int3iS1_Pf, .-_Z48__device_stub__Z20resetGridValuesSlice4int3iS_PfRK4int3iS1_Pf
	.globl	_Z20resetGridValuesSlice4int3iS_Pf
	.type	_Z20resetGridValuesSlice4int3iS_Pf, @function
_Z20resetGridValuesSlice4int3iS_Pf:
.LFB9947:
	.cfi_startproc
	endbr64
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movl	%esi, %r10d
	movq	%rcx, %rax
	movl	%edx, %esi
	movq	%rdi, 16(%rsp)
	movq	%rsp, %rdx
	leaq	16(%rsp), %rdi
	movq	%r9, %rcx
	movl	%r10d, 24(%rsp)
	movq	%rax, (%rsp)
	movl	%r8d, 8(%rsp)
	call	_Z48__device_stub__Z20resetGridValuesSlice4int3iS_PfRK4int3iS1_Pf
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE9947:
	.size	_Z20resetGridValuesSlice4int3iS_Pf, .-_Z20resetGridValuesSlice4int3iS_Pf
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"_ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv"
.LC3:
	.string	"_Z20resetGridValuesSlice4int3iS_Pf"
.LC4:
	.string	"_Z20closestAtomPerVertexPiP6float3j4int36float4S3_P4int2PS3_"
.LC5:
	.string	"_Z19distanceFieldRefinePiP4int24int36float4S2_S2_S3_S1_PS3_PfjjS2_j"
.LC6:
	.string	"_Z17probeIntersectionPiP4int24int36float4S2_S2_S3_S1_PS3_PfS2_ji"
.LC7:
	.string	"_Z8sortCelljP6float4P4int2S0_S2_"
.LC8:
	.string	"_Z11bitonic_512P4int2iii"
.LC9:
	.string	"_Z19bitonic_pass_kernelP4int2iii"
.LC10:
	.string	"_Z9hashAtomsjP6float44int3S_P4int2j"
.LC11:
	.string	"_Z15memsetCudaUInt2P5uint2S_i"
.LC12:
	.string	"_Z14memsetCudaInt2P4int2S_i"
.LC13:
	.string	"_Z13memsetCudaIntPiii"
.LC14:
	.string	"_Z15memsetCudaFloatPffi"
.LC15:
	.string	"_Z15LaplacianSmoothP6float3Pijjj"
.LC16:
	.string	"_Z13groupVerticesP6float3jf"
.LC17:
	.string	"_Z28generateTriangleVerticesSMEMP6float3PKjPK5uint2PKf6float4fjj4int3S9_"
.LC18:
	.string	"_Z13compactVoxelsPjPK5uint2jjj4int3iS3_"
.LC19:
	.string	"_Z18countVertexPerCellf4int3PKfP5uint2iS_"
.LC20:
	.string	"edgeTable"
.LC21:
	.string	"triTable"
.LC22:
	.string	"nbTriTable"
.LC23:
	.string	"_ZN41_INTERNAL_2bb75ba9_10_Kernels_cu_43bec5d94cuda3std3__45__cpo5beginE"
.LC24:
	.string	"_ZN41_INTERNAL_2bb75ba9_10_Kernels_cu_43bec5d94cuda3std3__45__cpo3endE"
.LC25:
	.string	"_ZN41_INTERNAL_2bb75ba9_10_Kernels_cu_43bec5d94cuda3std3__45__cpo6cbeginE"
.LC26:
	.string	"_ZN41_INTERNAL_2bb75ba9_10_Kernels_cu_43bec5d94cuda3std3__45__cpo4cendE"
.LC27:
	.string	"_ZN41_INTERNAL_2bb75ba9_10_Kernels_cu_43bec5d94cuda3std3__443_GLOBAL__N__2bb75ba9_10_Kernels_cu_43bec5d96ignoreE"
.LC28:
	.string	"_ZN41_INTERNAL_2bb75ba9_10_Kernels_cu_43bec5d94cuda3std3__419piecewise_constructE"
.LC29:
	.string	"_ZN41_INTERNAL_2bb75ba9_10_Kernels_cu_43bec5d94cuda3std3__48in_placeE"
.LC30:
	.string	"_ZN41_INTERNAL_2bb75ba9_10_Kernels_cu_43bec5d94cuda3std3__47nulloptE"
.LC31:
	.string	"_ZN41_INTERNAL_2bb75ba9_10_Kernels_cu_43bec5d94cuda3std6ranges3__45__cpo4swapE"
.LC32:
	.string	"_ZN41_INTERNAL_2bb75ba9_10_Kernels_cu_43bec5d94cuda3std6ranges3__45__cpo9iter_moveE"
.LC33:
	.string	"_ZN41_INTERNAL_2bb75ba9_10_Kernels_cu_43bec5d94cuda3std6ranges3__45__cpo7advanceE"
.LC34:
	.string	"_ZN41_INTERNAL_2bb75ba9_10_Kernels_cu_43bec5d96thrust20THRUST_200700_890_NS8cuda_cub3parE"
.LC35:
	.string	"_ZN41_INTERNAL_2bb75ba9_10_Kernels_cu_43bec5d96thrust20THRUST_200700_890_NS8cuda_cub10par_nosyncE"
.LC36:
	.string	"_ZN41_INTERNAL_2bb75ba9_10_Kernels_cu_43bec5d96thrust20THRUST_200700_890_NS6system6detail10sequential3seqE"
.LC37:
	.string	"_ZN41_INTERNAL_2bb75ba9_10_Kernels_cu_43bec5d96thrust20THRUST_200700_890_NS12placeholders2_1E"
.LC38:
	.string	"_ZN41_INTERNAL_2bb75ba9_10_Kernels_cu_43bec5d96thrust20THRUST_200700_890_NS12placeholders2_2E"
.LC39:
	.string	"_ZN41_INTERNAL_2bb75ba9_10_Kernels_cu_43bec5d96thrust20THRUST_200700_890_NS12placeholders2_3E"
.LC40:
	.string	"_ZN41_INTERNAL_2bb75ba9_10_Kernels_cu_43bec5d96thrust20THRUST_200700_890_NS12placeholders2_4E"
.LC41:
	.string	"_ZN41_INTERNAL_2bb75ba9_10_Kernels_cu_43bec5d96thrust20THRUST_200700_890_NS12placeholders2_5E"
.LC42:
	.string	"_ZN41_INTERNAL_2bb75ba9_10_Kernels_cu_43bec5d96thrust20THRUST_200700_890_NS12placeholders2_6E"
.LC43:
	.string	"_ZN41_INTERNAL_2bb75ba9_10_Kernels_cu_43bec5d96thrust20THRUST_200700_890_NS12placeholders2_7E"
.LC44:
	.string	"_ZN41_INTERNAL_2bb75ba9_10_Kernels_cu_43bec5d96thrust20THRUST_200700_890_NS12placeholders2_8E"
.LC45:
	.string	"_ZN41_INTERNAL_2bb75ba9_10_Kernels_cu_43bec5d96thrust20THRUST_200700_890_NS12placeholders2_9E"
.LC46:
	.string	"_ZN41_INTERNAL_2bb75ba9_10_Kernels_cu_43bec5d96thrust20THRUST_200700_890_NS12placeholders3_10E"
.LC47:
	.string	"_ZN41_INTERNAL_2bb75ba9_10_Kernels_cu_43bec5d96thrust20THRUST_200700_890_NS3seqE"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB9951:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_ZN3cub17CUB_200700_890_NS11EmptyKernelIvEEvv(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z20resetGridValuesSlice4int3iS_Pf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z20closestAtomPerVertexPiP6float3j4int36float4S3_P4int2PS3_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z19distanceFieldRefinePiP4int24int36float4S2_S2_S3_S1_PS3_PfjjS2_j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z17probeIntersectionPiP4int24int36float4S2_S2_S3_S1_PS3_PfS2_ji(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z8sortCelljP6float4P4int2S0_S2_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC8(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z11bitonic_512P4int2iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC9(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z19bitonic_pass_kernelP4int2iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC10(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_Z9hashAtomsjP6float44int3S_P4int2j(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC11(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z15memsetCudaUInt2P5uint2S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC12(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z14memsetCudaInt2P4int2S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC13(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z13memsetCudaIntPiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC14(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z15memsetCudaFloatPffi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC15(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z15LaplacianSmoothP6float3Pijjj(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC16(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z13groupVerticesP6float3jf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC17(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z28generateTriangleVerticesSMEMP6float3PKjPK5uint2PKf6float4fjj4int3S9_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC18(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_Z13compactVoxelsPjPK5uint2jjj4int3iS3_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC19(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z18countVertexPerCellf4int3PKfP5uint2iS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC20(%rip), %rdx
	movl	$1024, %r9d
	leaq	_ZL9edgeTable(%rip), %rsi
	pushq	$1
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC21(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$16384, %r9d
	leaq	_ZL8triTable(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC22(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1024, %r9d
	leaq	_ZL10nbTriTable(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC23(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__45__cpo5beginE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC24(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__45__cpo3endE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC25(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__45__cpo6cbeginE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC26(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__45__cpo4cendE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC27(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__443_GLOBAL__N__2bb75ba9_10_Kernels_cu_43bec5d96ignoreE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC28(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__419piecewise_constructE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC29(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__48in_placeE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC30(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__47nulloptE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC31(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC32(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC33(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo7advanceE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC34(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS8cuda_cubL3parE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC35(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS8cuda_cubL10par_nosyncE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC36(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS6system6detail10sequentialL3seqE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC37(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_1E(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC38(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_2E(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC39(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_3E(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC40(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_4E(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC41(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_5E(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC42(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_6E(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC43(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_7E(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC44(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_8E(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC45(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_9E(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC46(%rip), %rdx
	xorl	%r8d, %r8d
	movq	%rbx, %rdi
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS12placeholdersL3_10E(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC47(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$1, %r9d
	movq	%rdx, %rcx
	leaq	_ZN6thrust20THRUST_200700_890_NSL3seqE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r8
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE9951:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL10nbTriTable
	.comm	_ZL10nbTriTable,1024,32
	.local	_ZL8triTable
	.comm	_ZL8triTable,16384,32
	.local	_ZL9edgeTable
	.comm	_ZL9edgeTable,1024,32
	.section	.rodata
	.type	_ZN6thrust20THRUST_200700_890_NS8cuda_cubL10par_nosyncE, @object
	.size	_ZN6thrust20THRUST_200700_890_NS8cuda_cubL10par_nosyncE, 1
_ZN6thrust20THRUST_200700_890_NS8cuda_cubL10par_nosyncE:
	.zero	1
	.type	_ZN6thrust20THRUST_200700_890_NS8cuda_cubL3parE, @object
	.size	_ZN6thrust20THRUST_200700_890_NS8cuda_cubL3parE, 1
_ZN6thrust20THRUST_200700_890_NS8cuda_cubL3parE:
	.zero	1
	.type	_ZN6thrust20THRUST_200700_890_NSL3seqE, @object
	.size	_ZN6thrust20THRUST_200700_890_NSL3seqE, 1
_ZN6thrust20THRUST_200700_890_NSL3seqE:
	.zero	1
	.type	_ZN6thrust20THRUST_200700_890_NS12placeholdersL3_10E, @object
	.size	_ZN6thrust20THRUST_200700_890_NS12placeholdersL3_10E, 1
_ZN6thrust20THRUST_200700_890_NS12placeholdersL3_10E:
	.zero	1
	.type	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_9E, @object
	.size	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_9E, 1
_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_9E:
	.zero	1
	.type	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_8E, @object
	.size	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_8E, 1
_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_8E:
	.zero	1
	.type	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_7E, @object
	.size	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_7E, 1
_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_7E:
	.zero	1
	.type	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_6E, @object
	.size	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_6E, 1
_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_6E:
	.zero	1
	.type	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_5E, @object
	.size	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_5E, 1
_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_5E:
	.zero	1
	.type	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_4E, @object
	.size	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_4E, 1
_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_4E:
	.zero	1
	.type	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_3E, @object
	.size	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_3E, 1
_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_3E:
	.zero	1
	.type	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_2E, @object
	.size	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_2E, 1
_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_2E:
	.zero	1
	.type	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_1E, @object
	.size	_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_1E, 1
_ZN6thrust20THRUST_200700_890_NS12placeholdersL2_1E:
	.zero	1
	.weak	_ZN4cuda3std3__47nulloptE
	.section	.rodata._ZN4cuda3std3__47nulloptE,"aG",@progbits,_ZN4cuda3std3__47nulloptE,comdat
	.type	_ZN4cuda3std3__47nulloptE, @gnu_unique_object
	.size	_ZN4cuda3std3__47nulloptE, 1
_ZN4cuda3std3__47nulloptE:
	.zero	1
	.hidden	InitializeInjectionNvtx2_fnptr
	.weak	InitializeInjectionNvtx2_fnptr
	.bss
	.align 8
	.type	InitializeInjectionNvtx2_fnptr, @object
	.size	InitializeInjectionNvtx2_fnptr, 8
InitializeInjectionNvtx2_fnptr:
	.zero	8
	.hidden	nvtxGlobals_v3
	.weak	nvtxGlobals_v3
	.section	.data.rel.local,"aw"
	.align 32
	.type	nvtxGlobals_v3, @object
	.size	nvtxGlobals_v3, 1168
nvtxGlobals_v3:
	.long	0
	.zero	4
	.quad	16
	.quad	nvtxEtiGetModuleFunctionTable_v3
	.quad	24
	.long	3
	.long	0
	.quad	nvtxEtiSetInjectionNvtxVersion_v3
	.quad	nvtxMarkEx_impl_init_v3
	.quad	nvtxMarkA_impl_init_v3
	.quad	nvtxMarkW_impl_init_v3
	.quad	nvtxRangeStartEx_impl_init_v3
	.quad	nvtxRangeStartA_impl_init_v3
	.quad	nvtxRangeStartW_impl_init_v3
	.quad	nvtxRangeEnd_impl_init_v3
	.quad	nvtxRangePushEx_impl_init_v3
	.quad	nvtxRangePushA_impl_init_v3
	.quad	nvtxRangePushW_impl_init_v3
	.quad	nvtxRangePop_impl_init_v3
	.quad	nvtxNameCategoryA_impl_init_v3
	.quad	nvtxNameCategoryW_impl_init_v3
	.quad	nvtxNameOsThreadA_impl_init_v3
	.quad	nvtxNameOsThreadW_impl_init_v3
	.quad	nvtxNameCuDeviceA_impl_init_v3
	.quad	nvtxNameCuDeviceW_impl_init_v3
	.quad	nvtxNameCuContextA_impl_init_v3
	.quad	nvtxNameCuContextW_impl_init_v3
	.quad	nvtxNameCuStreamA_impl_init_v3
	.quad	nvtxNameCuStreamW_impl_init_v3
	.quad	nvtxNameCuEventA_impl_init_v3
	.quad	nvtxNameCuEventW_impl_init_v3
	.quad	nvtxNameClDeviceA_impl_init_v3
	.quad	nvtxNameClDeviceW_impl_init_v3
	.quad	nvtxNameClContextA_impl_init_v3
	.quad	nvtxNameClContextW_impl_init_v3
	.quad	nvtxNameClCommandQueueA_impl_init_v3
	.quad	nvtxNameClCommandQueueW_impl_init_v3
	.quad	nvtxNameClMemObjectA_impl_init_v3
	.quad	nvtxNameClMemObjectW_impl_init_v3
	.quad	nvtxNameClSamplerA_impl_init_v3
	.quad	nvtxNameClSamplerW_impl_init_v3
	.quad	nvtxNameClProgramA_impl_init_v3
	.quad	nvtxNameClProgramW_impl_init_v3
	.quad	nvtxNameClEventA_impl_init_v3
	.quad	nvtxNameClEventW_impl_init_v3
	.quad	nvtxNameCudaDeviceA_impl_init_v3
	.quad	nvtxNameCudaDeviceW_impl_init_v3
	.quad	nvtxNameCudaStreamA_impl_init_v3
	.quad	nvtxNameCudaStreamW_impl_init_v3
	.quad	nvtxNameCudaEventA_impl_init_v3
	.quad	nvtxNameCudaEventW_impl_init_v3
	.quad	nvtxDomainMarkEx_impl_init_v3
	.quad	nvtxDomainRangeStartEx_impl_init_v3
	.quad	nvtxDomainRangeEnd_impl_init_v3
	.quad	nvtxDomainRangePushEx_impl_init_v3
	.quad	nvtxDomainRangePop_impl_init_v3
	.quad	nvtxDomainResourceCreate_impl_init_v3
	.quad	nvtxDomainResourceDestroy_impl_init_v3
	.quad	nvtxDomainNameCategoryA_impl_init_v3
	.quad	nvtxDomainNameCategoryW_impl_init_v3
	.quad	nvtxDomainRegisterStringA_impl_init_v3
	.quad	nvtxDomainRegisterStringW_impl_init_v3
	.quad	nvtxDomainCreateA_impl_init_v3
	.quad	nvtxDomainCreateW_impl_init_v3
	.quad	nvtxDomainDestroy_impl_init_v3
	.quad	nvtxInitialize_impl_init_v3
	.quad	nvtxDomainSyncUserCreate_impl_init_v3
	.quad	nvtxDomainSyncUserDestroy_impl_init_v3
	.quad	nvtxDomainSyncUserAcquireStart_impl_init_v3
	.quad	nvtxDomainSyncUserAcquireFailed_impl_init_v3
	.quad	nvtxDomainSyncUserAcquireSuccess_impl_init_v3
	.quad	nvtxDomainSyncUserReleasing_impl_init_v3
	.quad	0
	.quad	nvtxGlobals_v3+48
	.quad	nvtxGlobals_v3+56
	.quad	nvtxGlobals_v3+64
	.quad	nvtxGlobals_v3+72
	.quad	nvtxGlobals_v3+80
	.quad	nvtxGlobals_v3+88
	.quad	nvtxGlobals_v3+96
	.quad	nvtxGlobals_v3+104
	.quad	nvtxGlobals_v3+112
	.quad	nvtxGlobals_v3+120
	.quad	nvtxGlobals_v3+128
	.quad	nvtxGlobals_v3+136
	.quad	nvtxGlobals_v3+144
	.quad	nvtxGlobals_v3+152
	.quad	nvtxGlobals_v3+160
	.quad	0
	.quad	0
	.quad	nvtxGlobals_v3+168
	.quad	nvtxGlobals_v3+176
	.quad	nvtxGlobals_v3+184
	.quad	nvtxGlobals_v3+192
	.quad	nvtxGlobals_v3+200
	.quad	nvtxGlobals_v3+208
	.quad	nvtxGlobals_v3+216
	.quad	nvtxGlobals_v3+224
	.quad	0
	.quad	0
	.quad	nvtxGlobals_v3+232
	.quad	nvtxGlobals_v3+240
	.quad	nvtxGlobals_v3+248
	.quad	nvtxGlobals_v3+256
	.quad	nvtxGlobals_v3+264
	.quad	nvtxGlobals_v3+272
	.quad	nvtxGlobals_v3+280
	.quad	nvtxGlobals_v3+288
	.quad	nvtxGlobals_v3+296
	.quad	nvtxGlobals_v3+304
	.quad	nvtxGlobals_v3+312
	.quad	nvtxGlobals_v3+320
	.quad	nvtxGlobals_v3+328
	.quad	nvtxGlobals_v3+336
	.quad	0
	.quad	0
	.quad	nvtxGlobals_v3+344
	.quad	nvtxGlobals_v3+352
	.quad	nvtxGlobals_v3+360
	.quad	nvtxGlobals_v3+368
	.quad	nvtxGlobals_v3+376
	.quad	nvtxGlobals_v3+384
	.quad	0
	.quad	0
	.quad	nvtxGlobals_v3+392
	.quad	nvtxGlobals_v3+400
	.quad	nvtxGlobals_v3+408
	.quad	nvtxGlobals_v3+416
	.quad	nvtxGlobals_v3+424
	.quad	nvtxGlobals_v3+432
	.quad	nvtxGlobals_v3+440
	.quad	nvtxGlobals_v3+448
	.quad	nvtxGlobals_v3+456
	.quad	nvtxGlobals_v3+464
	.quad	nvtxGlobals_v3+472
	.quad	nvtxGlobals_v3+480
	.quad	nvtxGlobals_v3+488
	.quad	nvtxGlobals_v3+496
	.quad	nvtxGlobals_v3+504
	.quad	0
	.quad	0
	.quad	nvtxGlobals_v3+512
	.quad	nvtxGlobals_v3+520
	.quad	nvtxGlobals_v3+528
	.quad	nvtxGlobals_v3+536
	.quad	nvtxGlobals_v3+544
	.quad	nvtxGlobals_v3+552
	.quad	0
	.section	.rodata
	.type	_ZN6thrust20THRUST_200700_890_NS6system6detail10sequentialL3seqE, @object
	.size	_ZN6thrust20THRUST_200700_890_NS6system6detail10sequentialL3seqE, 1
_ZN6thrust20THRUST_200700_890_NS6system6detail10sequentialL3seqE:
	.zero	1
	.weak	_ZN4cuda3std6ranges3__45__cpo7advanceE
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/*MIT License

Copyright (c) 2019 Xavier Martinez

Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/

#define NBTHREADS 256
#define EMPTYCELL INT_MAX-1
#define PROBERADIUS (1.4f)
#define EPSILON (0.001f)


#include <hip/hip_runtime.h>
#include <thrust/binary_search.h>

#include "operators.cu"
#include "MarchingCubes.cu"



struct compare_int2 {
    __host__ __device__ __forceinline__ bool operator()(int2 a, int2 b) {return a.x < b.x;}
};
struct compare_int {
    __host__ __device__ __forceinline__ bool operator()(int a, int b) {return a < b;}
};
struct compare_float3 {
    __device__ __host__ bool operator()(float3 a, float3 b) {
        if      (a.x <= b.x && a.y <= b.y && a.z < b.z) return true;
        else if (a.x <= b.x && a.y < b.y) return true;
        else if (a.x < b.x) return true;
        else return false;
    }
};
struct sort_float3 {
    __host__ __device__
    bool operator()(const float3 &a, const float3 &b) const {

        if      (a.x <= b.x && a.y <= b.y && a.z < b.z) return true;
        else if (a.x <= b.x && a.y < b.y) return true;
        else if (a.x < b.x) return true;
        else return false;
    }
};

struct compare_int3 {
    __host__ __device__ bool operator()(int3 a, int3 b) {
        if      (a.x <= b.x && a.y <= b.y && a.z < b.z) return true;
        else if (a.x <= b.x && a.y < b.y) return true;
        else if (a.x < b.x) return true;
        else return false;
    }
};
struct samefloat3 {
    __host__ __device__ bool operator()(float3 a, float3 b) {
        if (abs(a.x - b.x) > EPSILON)
            return false;
        if (abs(a.y - b.y) > EPSILON)
            return false;
        if (abs(a.z - b.z) > EPSILON)
            return false;

        return true;
    }
};
struct sameint3 {
    __host__ __device__ bool operator()(int3 a, int3 b) {
        if (a.x != b.x)
            return false;
        if (a.y != b.y)
            return false;
        if (a.z != b.z)
            return false;

        return true;
    }
};


template<typename T>
struct lessf3 : public thrust::binary_function<T, T, bool>
{
    __host__ __device__ bool operator()(const T &a, const T &b) const {
        if      (a.x <= b.x && a.y <= b.y && a.z < b.z) return true;
        else if (a.x <= b.x && a.y < b.y) return true;
        else if (a.x < b.x) return true;
        else return false;
    }
};

struct add_uint2 {
    __device__
    uint2 operator()(const uint2& a, const uint2& b) const {
        uint2 r;
        r.x = a.x + b.x;
        r.y = a.y + b.y;
        return r;
    }
};

struct is_notempty
{
    __host__ __device__
    bool operator()(const int &x) const
    {
        return x != EMPTYCELL;
    }
};


__global__ void memsetCudaFloat(float *data, float val, int N){
    unsigned int index = blockDim.x * blockIdx.x + threadIdx.x;
    
    if (index >= N) {
        return;
    }
    data[index] = val;
}
__global__ void memsetCudaInt(int *data, int val, int N) {
    unsigned int index = blockDim.x * blockIdx.x + threadIdx.x;
    
    if (index >= N) {
        return;
    }
    data[index] = val;
}
__global__ void memsetCudaInt2(int2 *data, int2 val, int N) {
    unsigned int index = blockDim.x * blockIdx.x + threadIdx.x;
    
    if (index >= N) {
        return;
    }
    data[index] = val;
}
__global__ void memsetCudaUInt2(uint2 *data, uint2 val, int N) {
    unsigned int index = blockDim.x * blockIdx.x + threadIdx.x;
    
    if (index >= N) {
        return;
    }
    data[index] = val;
}
__host__ __device__ int3 spaceToGrid(float3 pos3D, float3 originGrid, float dx) {
    float3 tmp = ((pos3D - originGrid) / dx);
    return make_int3(tmp.x, tmp.y, tmp.z);

}
__host__ __device__ float3 gridToSpace(int3 cellPos, float3 originGrid, float dx) {
    return (originGrid + (make_float3(cellPos.x, cellPos.y, cellPos.z) * dx) );
    //return originGrid + (convert_float3(cellPos) * dx) + (dx / 2.0f);
}

__host__ __device__ int flatten3DTo1D(int3 id3d, int3 gridDim) {
    return (gridDim.y * gridDim.z * id3d.x) + (gridDim.z * id3d.y) + id3d.z;
}
// __host__ __device__ int flatten3DTo1D(int3 id3d, int3 gridDim) {
//     // return id3d.x + gridDim.x * (id3d.y + gridDim.z * id3d.z);
//     return id3d.x + id3d.y * gridDim.x + id3d.z * gridDim.x * gridDim.y;
// }


__host__ __device__ int3 unflatten1DTo3D(int index, int3 gridDim) {
    int3 res;
    // res.x = index % gridDim.x;
    // res.y = (index / gridDim.x) % gridDim.y;
    // res.z = index / (gridDim.x * gridDim.y);
    res.x = index / (gridDim.y * gridDim.z); //Note the integer division . This is x
    res.y = (index - res.x * gridDim.y * gridDim.z) / gridDim.z; //This is y
    res.z = index - res.x * gridDim.y * gridDim.z - res.y * gridDim.z; //This is z
    return res;
}

inline __host__ __device__ float fast_distance(float3 p1, float3 p2) {
    float x = (p1.x - p2.x) * (p1.x - p2.x);
    float y = (p1.y - p2.y) * (p1.y - p2.y);
    float z = (p1.z - p2.z) * (p1.z - p2.z);

    return sqrt( x + y + z);
}
inline __host__ __device__ float sqr_distance(float3 p1, float3 p2) {
    float x = (p1.x - p2.x) * (p1.x - p2.x);
    float y = (p1.y - p2.y) * (p1.y - p2.y);
    float z = (p1.z - p2.z) * (p1.z - p2.z);

    return x + y + z;
}



inline __host__ __device__ float3 clamp(float3 f, float a, float b)
{
    return make_float3(max(a, min(f.x, b)),
                       max(a, min(f.y, b)),
                       max(a, min(f.z, b))
                      );
}
inline __host__ __device__ int3 clamp(int3 f, int a, int b)
{
    return make_int3(max(a, min(f.x, b)),
                     max(a, min(f.y, b)),
                     max(a, min(f.z, b))
                    );
}
inline __host__ __device__ int clamp(int f, int a, int b)
{
    return max(a, min(f, b));
}

// inline __device__ int lessThan(float x, float y) {
//     return max(sign(y - x), 0);
// }

// calculate cell address as the hash value for each atom
__global__ void hashAtoms(unsigned int natoms,
                          float4*  xyzr,
                          int3 gridDim,
                          float4 originGridDDx,
                          int2 * atomHashIndex,
                          unsigned natomsnextPow2) {


    unsigned int index = blockDim.x * blockIdx.x + threadIdx.x;

    if (index >= natomsnextPow2)
        return;

    if (index >= natoms) {
        atomHashIndex[index].x = INT_MAX;
        atomHashIndex[index].y = INT_MAX;
        return;
    }

    float4 atom = xyzr[index];// read atom coordinate and radius
    float3 pos = make_float3(atom.x, atom.y, atom.z);
    // compute cell index, clamped to fall within grid bounds
    float3 originGrid = make_float3(originGridDDx.x, originGridDDx.y, originGridDDx.z);
    float dx = originGridDDx.w;
    int3 cell = spaceToGrid(pos, originGrid, dx);

    int hash = flatten3DTo1D(cell, gridDim);

    atomHashIndex[index].x = hash;// atoms hashed to cell address
    atomHashIndex[index].y = index; // original atom index

}


//https://github.com/FROL256/opencl_bitonic_sort_by_key/blob/master/bitonic_sort_gpu.h

inline __device__ int getKey(int2 v) { return v.x; }
inline __device__ int getVal(int2 v) { return v.y; }

inline __device__ bool compare(int2 a, int2 b) { return getKey(a) < getKey(b); }

__global__ void bitonic_pass_kernel(int2* theArray, int stage, int passOfStage, int a_invertModeOn)
{
    int j = blockDim.x * blockIdx.x + threadIdx.x;

    const int r     = 1 << (passOfStage);
    const int lmask = r - 1;

    const int left  = ((j >> passOfStage) << (passOfStage + 1)) + (j & lmask);
    const int right = left + r;

    const int2 a = theArray[left];
    const int2 b = theArray[right];

    const bool cmpRes = compare(a, b);

    const int2 minElem = cmpRes ? a : b;
    const int2 maxElem = cmpRes ? b : a;

    const int oddEven = j >> stage;

    const bool isSwap = (oddEven & 1) & a_invertModeOn;

    const int minId = isSwap ? right : left;
    const int maxId = isSwap ? left  : right;

    theArray[minId] = minElem;
    theArray[maxId] = maxElem;
}


__global__ void bitonic_512( int2* theArray, int stage, int passOfStageBegin, int a_invertModeOn)
{
    int tid = blockDim.x * blockIdx.x + threadIdx.x;
    int lid = threadIdx.x;

    int blockId = (tid / 256);

    __shared__ int2 s_array[512];

    s_array[lid + 0]   = theArray[blockId * 512 + lid + 0];
    s_array[lid + 256] = theArray[blockId * 512 + lid + 256];

    __syncthreads();

    for (int passOfStage = passOfStageBegin; passOfStage >= 0; passOfStage--)
    {
        const int j     = lid;
        const int r     = 1 << (passOfStage);
        const int lmask = r - 1;

        const int left  = ((j >> passOfStage) << (passOfStage + 1)) + (j & lmask);
        const int right = left + r;

        const int2 a = s_array[left];
        const int2 b = s_array[right];

        const bool cmpRes = compare(a, b);

        const int2 minElem = cmpRes ? a : b;
        const int2 maxElem = cmpRes ? b : a;

        const int oddEven = tid >> stage; // (j >> stage)

        const bool isSwap = (oddEven & 1) & a_invertModeOn;

        const int minId = isSwap ? right : left;
        const int maxId = isSwap ? left  : right;

        s_array[minId] = minElem;
        s_array[maxId] = maxElem;

        __syncthreads();
    }

    theArray[blockId * 512 + lid + 0]   = s_array[lid + 0];
    theArray[blockId * 512 + lid + 256] = s_array[lid + 256];

}


__global__ void sortCell(unsigned int natoms, float4 *xyzr, int2 *atomHashIndex,
                         float4 *sorted_xyzr,
                         int2 *cellStartEnd) {

    int hash;
    int id;
    // __local int local_hash[NBTHREADS + 1];
    unsigned int index = blockDim.x * blockIdx.x + threadIdx.x;

    if (index >= natoms)
        return;

    hash = atomHashIndex[index].x;
    id = atomHashIndex[index].y;

    int hashm1;
    if (index != 0)
        hashm1 = atomHashIndex[index - 1].x;
    else
        hashm1 = hash;


    if (index == 0 || hash != hashm1) {
        cellStartEnd[hash].x = index; // set start
        if (index > 0)
            cellStartEnd[hashm1].y = index; // set end
    }

    if (index == natoms - 1) {
        cellStartEnd[hash].y = index + 1; // set end
    }

    // Reorder atoms according to sorted indices
    sorted_xyzr[index] = xyzr[id];

}


inline __host__ __device__ float computeInOrOut(int3 id3DNeigh, int2 *cellStartEnd, float4 *sorted_xyzr, float3 spacePosSES, float dx, int3 gridDimNeighbor) {
    //Loop over neighbors to compute if the cell is:
    // 1) - ouside => result = PROBERADIUS
    // 2) - inside => result = -dx
    // 3) - at the border =>  result = 0.0
    int3 curgridId;
    float result = PROBERADIUS;
    bool nearProbe = false;

// #pragma unroll
    for (int x = -1; x <= 1; x++) {
        curgridId.x = clamp(id3DNeigh.x + x, 0, gridDimNeighbor.x - 1);
// #pragma unroll
        for (int y = -1; y <= 1; y++) {
            curgridId.y = clamp(id3DNeigh.y + y, 0, gridDimNeighbor.x - 1);
// #pragma unroll
            for (int z = -1; z <= 1; z++) {
                curgridId.z = clamp(id3DNeigh.z + z, 0, gridDimNeighbor.x - 1);

                int neighcellhash = flatten3DTo1D(curgridId, gridDimNeighbor);
                int idStart = cellStartEnd[neighcellhash].x;
                int idStop = cellStartEnd[neighcellhash].y;

                if (idStart < EMPTYCELL) {
                    for (int id = idStart; id < idStop; id++) {
                        float4 xyzr = sorted_xyzr[id];
                        float rad = xyzr.w;
                        float3 pos = make_float3(xyzr.x, xyzr.y, xyzr.z);
                        // float d = sqr_distance(pos, spacePosSES);
                        float d = fast_distance(pos, spacePosSES);

                        // minDist = min(d, minDist);
                        // if (d < rad * rad)
                        if (d < rad - dx)
                            return -dx;
                        // if (d < (PROBERADIUS + rad) * (PROBERADIUS + rad))
                        if (d < (PROBERADIUS + rad) )
                            nearProbe = true;
                    }
                }
            }
        }
    }    

    //float result = (1 - nearProbe) * PROBERADIUS;
    if (nearProbe)
        result = 0.0f;
    return result;
}

__global__ void probeIntersection(int * checkFill,
                                  int2 * atomHashIndex,
                                  int3 gridDimNeighbor,
                                  float4 originGridNeighborDDx,
                                  int3 gridDimSES,
                                  int3 sliceGridDimSES,
                                  // int3 smallsliceGridDimSES,
                                  float4 originGridSESDx,
                                  int2 *cellStartEnd,
                                  float4 * sorted_xyzr,
                                  float *gridValues,
                                  int3 offsetGrid,
                                  unsigned int N,
                                  int sliceNb) {

    // Get global position in X direction
    unsigned int i = (threadIdx.x + blockIdx.x * blockDim.x);
    // Get global position in Y direction
    unsigned int j = (threadIdx.y + blockIdx.y * blockDim.y);
    // Get global position in Z direction
    unsigned int k = (threadIdx.z + blockIdx.z * blockDim.z);

    int3 ijk = make_int3(i, j, k);

    if (i >= sliceGridDimSES.x - 1)
        return;
    if (j >= sliceGridDimSES.y - 1)
        return;
    if (k >= sliceGridDimSES.z - 1)
        return;



    int hash = flatten3DTo1D(ijk, sliceGridDimSES);

    // if(hash >= sliceNb)
    //     return;


    int3 ijkOffset = make_int3(i + offsetGrid.x, j + offsetGrid.y, k + offsetGrid.z);
    int hashOffset = flatten3DTo1D(ijkOffset, gridDimSES);

    if (ijkOffset.x >= gridDimSES.x - 1)
        return;
    if (ijkOffset.y >= gridDimSES.y - 1)
        return;
    if (ijkOffset.z >= gridDimSES.z - 1)
        return;


    float3 originGridNeighbor = make_float3(originGridNeighborDDx.x, originGridNeighborDDx.y, originGridNeighborDDx.z);
    float dxNeighbor = originGridNeighborDDx.w;
    float dxSES = originGridSESDx.w;

    float3 spacePos3DCellSES = gridToSpace(ijkOffset, originGridNeighbor, dxSES);

    // id of the current cell in the neighbor grid
    int3 gridPos3DCellNeighbor = spaceToGrid(spacePos3DCellSES, originGridNeighbor, dxNeighbor);


    //Loop over neighbors to compute if the cell is:
    // 1) - ouside => result = PROBERADIUS
    // 2) - inside => result = -dx
    // 3) - at the border =>  result = 0.0
    float result = computeInOrOut(gridPos3DCellNeighbor, cellStartEnd, sorted_xyzr, spacePos3DCellSES, dxSES, gridDimNeighbor);


    //If should process => record id, if not record a large number
    int fill = EMPTYCELL;

    int range = (int)ceil(PROBERADIUS / dxSES);
    if (abs(result) < EPSILON){
        fill = hash;
        // if(i < range || j < range || k < range || i > smallsliceGridDimSES.x + range || j > smallsliceGridDimSES.y + range || k > smallsliceGridDimSES.z + range){
        //     fill = EMPTYCELL;
        // }
    }

    checkFill[hash] = fill;
    gridValues[hash] = result;

}


__global__ void distanceFieldRefine(int * checkFill, int2 * atomHashIndex, int3 gridDimNeighbor,
                                    float4 originGridNeighborDDx, int3 gridDimSES, int3 sliceGridDimSES,
                                    float4 originGridSESDx, int2 * cellStartEnd, float4 * sorted_xyzr,
                                    float *gridValues, unsigned int totalCells, unsigned int notEmptyCells,
                                    int3 offsetGrid, unsigned int of) {

    int id = (threadIdx.x + blockIdx.x * blockDim.x) + of;


    if (id >= notEmptyCells) {
        return;
    }

    int hash = checkFill[id];

    int3 ijk = unflatten1DTo3D(hash, sliceGridDimSES);

    //From slice to real id in the full size grid
    int3 ijkOffset = make_int3(ijk.x + offsetGrid.x, ijk.y + offsetGrid.y, ijk.z + offsetGrid.z);
    int hashOffset = flatten3DTo1D(ijkOffset, gridDimSES);

    float3 originGridSES = make_float3(originGridSESDx.x, originGridSESDx.y, originGridSESDx.z);

    float dxSES = originGridSESDx.w;

    float3 spacePos3DCellSES = gridToSpace(ijkOffset, originGridSES, dxSES);

    float newresult = -dxSES;

    const int idSESRangeToSearch = (int)ceil(PROBERADIUS / dxSES);
    const float pme = PROBERADIUS - EPSILON;
    float minDist = 100000.0f;

    int3 curgridSESId;

    //Find the closest outside SES cell in the range [-probeRadius, +probeRadius]
// #pragma unroll
    for (int x = -idSESRangeToSearch; x <= idSESRangeToSearch; x++) {

        curgridSESId.x = clamp(ijk.x + x , 0, sliceGridDimSES.x - 1);
// #pragma unroll
        for (int y = -idSESRangeToSearch; y <= idSESRangeToSearch; y++) {
            curgridSESId.y = clamp(ijk.y + y , 0, sliceGridDimSES.y - 1);
// #pragma unroll
            for (int z = -idSESRangeToSearch; z <= idSESRangeToSearch; z++) {
                curgridSESId.z = clamp(ijk.z + z , 0, sliceGridDimSES.z - 1);
                int curgrid1DSESId = flatten3DTo1D(curgridSESId, sliceGridDimSES);

                if (gridValues[curgrid1DSESId] > pme) {//Outside
                    
                    int3 curgrid3DSESIdOffset = make_int3(curgridSESId.x + offsetGrid.x,
                                                        curgridSESId.y + offsetGrid.y,
                                                        curgridSESId.z + offsetGrid.z);

                    float3 spacePosSES = gridToSpace(curgrid3DSESIdOffset, originGridSES, dxSES);
                    //Distance from our current grid cell to the outside grid cell
                    float d = fast_distance(spacePosSES, spacePos3DCellSES);
                    minDist = min(d, minDist);
                }
            }
        }
    }
    if (minDist < 999.0f)
        newresult =  PROBERADIUS - minDist;

    gridValues[hash] = newresult;

}

inline __host__ __device__ int computeClosestAtom(float3 vert, int3 id3DNeigh, int2 *cellStartEnd, float4 *sorted_xyzr, int3 gridDimNeighbor) {


    int closestId = -1;
    float minD = 999999.0f;
    int3 curgridId;
// #pragma unroll
    for (int x = -1; x <= 1; x++) {
        curgridId.x = clamp(id3DNeigh.x + x, 0, gridDimNeighbor.x - 1);
// #pragma unroll
        for (int y = -1; y <= 1; y++) {
            curgridId.y = clamp(id3DNeigh.y + y, 0, gridDimNeighbor.x - 1);
// #pragma unroll
            for (int z = -1; z <= 1; z++) {
                curgridId.z = clamp(id3DNeigh.z + z, 0, gridDimNeighbor.x - 1);

                int neighcellhash = flatten3DTo1D(curgridId, gridDimNeighbor);
                int idStart = cellStartEnd[neighcellhash].x;
                int idStop = cellStartEnd[neighcellhash].y;

                if (idStart < EMPTYCELL) {
                    for (int id = idStart; id < idStop; id++) {
                        float4 xyzr = sorted_xyzr[id];
                        float3 pos = make_float3(xyzr.x, xyzr.y, xyzr.z);
                        // float d = sqr_distance(pos, vert);
                        float d = fast_distance(pos, vert);
                        if(d < minD){
                            minD = d;
                            closestId = id;
                        }
                    }
                }
            }
        }
    }
    return closestId;


}

__global__ void closestAtomPerVertex(int *atomIdPerVert, float3 *vertices, unsigned int Nvert, int3 gridDimNeighbor,
                                    float4 originGridNeighborDDx,
                                    float4 originGridSESDx, int2 * cellStartEnd, float4 * sorted_xyzr) {

    int id = (threadIdx.x + blockIdx.x * blockDim.x);

    if(id >= Nvert)
        return;

    float3 vert = vertices[id];

    float3 originGridNeighbor = make_float3(originGridNeighborDDx.x, originGridNeighborDDx.y, originGridNeighborDDx.z);
    float dxNeighbor = originGridNeighborDDx.w;

    int3 gridPos3DCellNeighbor = spaceToGrid(vert, originGridNeighbor, dxNeighbor);

    atomIdPerVert[id] = computeClosestAtom(vert, gridPos3DCellNeighbor, cellStartEnd, sorted_xyzr, gridDimNeighbor);
}

__global__ void resetGridValuesSlice(const int3 offset, const int rangeSearchRefine, const int3 sliceGridDimSES, float *gridValues){

    // Get global position in X direction
    unsigned int i = (threadIdx.x + blockIdx.x * blockDim.x);
    // Get global position in Y direction
    unsigned int j = (threadIdx.y + blockIdx.y * blockDim.y);
    // Get global position in Z direction
    unsigned int k = (threadIdx.z + blockIdx.z * blockDim.z);

    int3 ijk = make_int3(i, j, k);

    if (i >= sliceGridDimSES.x - 1)
        return;
    if (j >= sliceGridDimSES.y - 1)
        return;
    if (k >= sliceGridDimSES.z - 1)
        return;


    int hash = flatten3DTo1D(ijk, sliceGridDimSES);

    if(i >= sliceGridDimSES.x - rangeSearchRefine)
        gridValues[hash] = PROBERADIUS;
    if(j >= sliceGridDimSES.y - rangeSearchRefine)
        gridValues[hash] = PROBERADIUS;
    if(k >= sliceGridDimSES.z - rangeSearchRefine)
        gridValues[hash] = PROBERADIUS;

    if(offset.x != 0){
        if(i < rangeSearchRefine)
            gridValues[hash] = PROBERADIUS;
    }
    else{
        if(i >= sliceGridDimSES.x - rangeSearchRefine * 2)
            gridValues[hash] = PROBERADIUS;
    }
    if(offset.y != 0){
        if(j < rangeSearchRefine)
            gridValues[hash] = PROBERADIUS;
    }
    else{
        if(j >= sliceGridDimSES.y - rangeSearchRefine * 2)
            gridValues[hash] = PROBERADIUS;
    }
    if(offset.z != 0){
        if(k < rangeSearchRefine)
            gridValues[hash] = PROBERADIUS;
    }
    else{
        if(k >= sliceGridDimSES.z - rangeSearchRefine * 2)
            gridValues[hash] = PROBERADIUS;
    }


}
	.text
	.file	"Kernels.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z33__device_stub__countVertexPerCellf15HIP_vector_typeIiLj3EEPKfPS_IjLj2EEiS0_ # -- Begin function _Z33__device_stub__countVertexPerCellf15HIP_vector_typeIiLj3EEPKfPS_IjLj2EEiS0_
	.type	_Z33__device_stub__countVertexPerCellf15HIP_vector_typeIiLj3EEPKfPS_IjLj2EEiS0_,@function
_Z33__device_stub__countVertexPerCellf15HIP_vector_typeIiLj3EEPKfPS_IjLj2EEiS0_: # @_Z33__device_stub__countVertexPerCellf15HIP_vector_typeIiLj3EEPKfPS_IjLj2EEiS0_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	80(%rsp), %rax
	movq	%rdi, (%rax)
	movl	%esi, 8(%rax)
	leaq	12(%rsp), %rsi
	movss	%xmm0, (%rsi)
	leaq	40(%rsp), %rdi
	movq	%rdx, (%rdi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	8(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rsi, (%rbx)
	movq	%rax, 8(%rbx)
	movq	%rdi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	192(%rsp), %rax
	movq	%rax, 40(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18countVertexPerCellf15HIP_vector_typeIiLj3EEPKfPS_IjLj2EEiS0_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z33__device_stub__countVertexPerCellf15HIP_vector_typeIiLj3EEPKfPS_IjLj2EEiS0_, .Lfunc_end0-_Z33__device_stub__countVertexPerCellf15HIP_vector_typeIiLj3EEPKfPS_IjLj2EEiS0_
	.cfi_endproc
                                        # -- End function
	.globl	_Z28__device_stub__compactVoxelsPjPK15HIP_vector_typeIjLj2EEjjjS0_IiLj3EEiS4_ # -- Begin function _Z28__device_stub__compactVoxelsPjPK15HIP_vector_typeIjLj2EEjjjS0_IiLj3EEiS4_
	.type	_Z28__device_stub__compactVoxelsPjPK15HIP_vector_typeIjLj2EEjjjS0_IiLj3EEiS4_,@function
_Z28__device_stub__compactVoxelsPjPK15HIP_vector_typeIjLj2EEjjjS0_IiLj3EEiS4_: # @_Z28__device_stub__compactVoxelsPjPK15HIP_vector_typeIjLj2EEjjjS0_IiLj3EEiS4_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	movq	%rsp, %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	192(%rsp), %rax
	movq	%rax, 40(%rbx)
	movq	%r8, 48(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13compactVoxelsPjPK15HIP_vector_typeIjLj2EEjjjS0_IiLj3EEiS4_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z28__device_stub__compactVoxelsPjPK15HIP_vector_typeIjLj2EEjjjS0_IiLj3EEiS4_, .Lfunc_end1-_Z28__device_stub__compactVoxelsPjPK15HIP_vector_typeIjLj2EEjjjS0_IiLj3EEiS4_
	.cfi_endproc
                                        # -- End function
	.globl	_Z43__device_stub__generateTriangleVerticesSMEMP15HIP_vector_typeIfLj3EEPKjPKS_IjLj2EEPKfS_IfLj4EEfjjS_IiLj3EESA_ # -- Begin function _Z43__device_stub__generateTriangleVerticesSMEMP15HIP_vector_typeIfLj3EEPKjPKS_IjLj2EEPKfS_IfLj4EEfjjS_IiLj3EESA_
	.type	_Z43__device_stub__generateTriangleVerticesSMEMP15HIP_vector_typeIfLj3EEPKjPKS_IjLj2EEPKfS_IfLj4EEfjjS_IiLj3EESA_,@function
_Z43__device_stub__generateTriangleVerticesSMEMP15HIP_vector_typeIfLj3EEPKjPKS_IjLj2EEPKfS_IfLj4EEfjjS_IiLj3EESA_: # @_Z43__device_stub__generateTriangleVerticesSMEMP15HIP_vector_typeIfLj3EEPKjPKS_IjLj2EEPKfS_IfLj4EEfjjS_IiLj3EESA_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	96(%rsp), %rax
	movsd	%xmm0, (%rax)
	movsd	%xmm1, 8(%rax)
	leaq	56(%rsp), %r10
	movq	%rdi, (%r10)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movss	%xmm2, (%rcx)
	leaq	8(%rsp), %r11
	movl	%r8d, (%r11)
	leaq	4(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	112(%rsp), %rbx
	movq	%r10, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rax, 32(%rbx)
	movq	%rcx, 40(%rbx)
	movq	%r11, 48(%rbx)
	movq	%r8, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z28generateTriangleVerticesSMEMP15HIP_vector_typeIfLj3EEPKjPKS_IjLj2EEPKfS_IfLj4EEfjjS_IiLj3EESA_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z43__device_stub__generateTriangleVerticesSMEMP15HIP_vector_typeIfLj3EEPKjPKS_IjLj2EEPKfS_IfLj4EEfjjS_IiLj3EESA_, .Lfunc_end2-_Z43__device_stub__generateTriangleVerticesSMEMP15HIP_vector_typeIfLj3EEPKjPKS_IjLj2EEPKfS_IfLj4EEfjjS_IiLj3EESA_
	.cfi_endproc
                                        # -- End function
	.globl	_Z28__device_stub__groupVerticesP15HIP_vector_typeIfLj3EEjf # -- Begin function _Z28__device_stub__groupVerticesP15HIP_vector_typeIfLj3EEjf
	.type	_Z28__device_stub__groupVerticesP15HIP_vector_typeIfLj3EEjf,@function
_Z28__device_stub__groupVerticesP15HIP_vector_typeIfLj3EEjf: # @_Z28__device_stub__groupVerticesP15HIP_vector_typeIfLj3EEjf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$96, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	movq	%rsp, %rdx
	movss	%xmm0, (%rdx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rdx, 16(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13groupVerticesP15HIP_vector_typeIfLj3EEjf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$112, %rsp
	.cfi_adjust_cfa_offset -112
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z28__device_stub__groupVerticesP15HIP_vector_typeIfLj3EEjf, .Lfunc_end3-_Z28__device_stub__groupVerticesP15HIP_vector_typeIfLj3EEjf
	.cfi_endproc
                                        # -- End function
	.globl	_Z30__device_stub__LaplacianSmoothP15HIP_vector_typeIfLj3EEPijjj # -- Begin function _Z30__device_stub__LaplacianSmoothP15HIP_vector_typeIfLj3EEPijjj
	.type	_Z30__device_stub__LaplacianSmoothP15HIP_vector_typeIfLj3EEPijjj,@function
_Z30__device_stub__LaplacianSmoothP15HIP_vector_typeIfLj3EEPijjj: # @_Z30__device_stub__LaplacianSmoothP15HIP_vector_typeIfLj3EEPijjj
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15LaplacianSmoothP15HIP_vector_typeIfLj3EEPijjj, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z30__device_stub__LaplacianSmoothP15HIP_vector_typeIfLj3EEPijjj, .Lfunc_end4-_Z30__device_stub__LaplacianSmoothP15HIP_vector_typeIfLj3EEPijjj
	.cfi_endproc
                                        # -- End function
	.globl	_Z30__device_stub__memsetCudaFloatPffi # -- Begin function _Z30__device_stub__memsetCudaFloatPffi
	.type	_Z30__device_stub__memsetCudaFloatPffi,@function
_Z30__device_stub__memsetCudaFloatPffi: # @_Z30__device_stub__memsetCudaFloatPffi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$96, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movss	%xmm0, (%rcx)
	movq	%rsp, %rdx
	movl	%esi, (%rdx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rdx, 16(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15memsetCudaFloatPffi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$112, %rsp
	.cfi_adjust_cfa_offset -112
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z30__device_stub__memsetCudaFloatPffi, .Lfunc_end5-_Z30__device_stub__memsetCudaFloatPffi
	.cfi_endproc
                                        # -- End function
	.globl	_Z28__device_stub__memsetCudaIntPiii # -- Begin function _Z28__device_stub__memsetCudaIntPiii
	.type	_Z28__device_stub__memsetCudaIntPiii,@function
_Z28__device_stub__memsetCudaIntPiii:   # @_Z28__device_stub__memsetCudaIntPiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$96, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	movq	%rsp, %rsi
	movl	%edx, (%rsi)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13memsetCudaIntPiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$112, %rsp
	.cfi_adjust_cfa_offset -112
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z28__device_stub__memsetCudaIntPiii, .Lfunc_end6-_Z28__device_stub__memsetCudaIntPiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z29__device_stub__memsetCudaInt2P15HIP_vector_typeIiLj2EES0_i # -- Begin function _Z29__device_stub__memsetCudaInt2P15HIP_vector_typeIiLj2EES0_i
	.type	_Z29__device_stub__memsetCudaInt2P15HIP_vector_typeIiLj2EES0_i,@function
_Z29__device_stub__memsetCudaInt2P15HIP_vector_typeIiLj2EES0_i: # @_Z29__device_stub__memsetCudaInt2P15HIP_vector_typeIiLj2EES0_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rsi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rdi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rcx, (%rbx)
	movq	%rax, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14memsetCudaInt2P15HIP_vector_typeIiLj2EES0_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_Z29__device_stub__memsetCudaInt2P15HIP_vector_typeIiLj2EES0_i, .Lfunc_end7-_Z29__device_stub__memsetCudaInt2P15HIP_vector_typeIiLj2EES0_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z30__device_stub__memsetCudaUInt2P15HIP_vector_typeIjLj2EES0_i # -- Begin function _Z30__device_stub__memsetCudaUInt2P15HIP_vector_typeIjLj2EES0_i
	.type	_Z30__device_stub__memsetCudaUInt2P15HIP_vector_typeIjLj2EES0_i,@function
_Z30__device_stub__memsetCudaUInt2P15HIP_vector_typeIjLj2EES0_i: # @_Z30__device_stub__memsetCudaUInt2P15HIP_vector_typeIjLj2EES0_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rsi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rdi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rcx, (%rbx)
	movq	%rax, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15memsetCudaUInt2P15HIP_vector_typeIjLj2EES0_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end8:
	.size	_Z30__device_stub__memsetCudaUInt2P15HIP_vector_typeIjLj2EES0_i, .Lfunc_end8-_Z30__device_stub__memsetCudaUInt2P15HIP_vector_typeIjLj2EES0_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z11spaceToGrid15HIP_vector_typeIfLj3EES0_f # -- Begin function _Z11spaceToGrid15HIP_vector_typeIfLj3EES0_f
	.type	_Z11spaceToGrid15HIP_vector_typeIfLj3EES0_f,@function
_Z11spaceToGrid15HIP_vector_typeIfLj3EES0_f: # @_Z11spaceToGrid15HIP_vector_typeIfLj3EES0_f
	.cfi_startproc
# %bb.0:
	subps	%xmm2, %xmm0
	movaps	%xmm0, %xmm2
	shufps	$85, %xmm0, %xmm2               # xmm2 = xmm2[1,1],xmm0[1,1]
	subss	%xmm3, %xmm1
	divss	%xmm4, %xmm0
	divss	%xmm4, %xmm2
	divss	%xmm4, %xmm1
	cvttss2si	%xmm0, %eax
	cvttss2si	%xmm2, %ecx
	cvttss2si	%xmm1, %edx
	shlq	$32, %rcx
	orq	%rcx, %rax
	retq
.Lfunc_end9:
	.size	_Z11spaceToGrid15HIP_vector_typeIfLj3EES0_f, .Lfunc_end9-_Z11spaceToGrid15HIP_vector_typeIfLj3EES0_f
	.cfi_endproc
                                        # -- End function
	.globl	_Z11gridToSpace15HIP_vector_typeIiLj3EES_IfLj3EEf # -- Begin function _Z11gridToSpace15HIP_vector_typeIiLj3EES_IfLj3EEf
	.type	_Z11gridToSpace15HIP_vector_typeIiLj3EES_IfLj3EEf,@function
_Z11gridToSpace15HIP_vector_typeIiLj3EES_IfLj3EEf: # @_Z11gridToSpace15HIP_vector_typeIiLj3EES_IfLj3EEf
	.cfi_startproc
# %bb.0:
	cvtsi2ss	%edi, %xmm3
	shrq	$32, %rdi
	cvtsi2ss	%edi, %xmm4
	cvtsi2ss	%esi, %xmm5
	mulss	%xmm2, %xmm3
	mulss	%xmm2, %xmm4
	mulss	%xmm2, %xmm5
	addss	%xmm0, %xmm3
	shufps	$85, %xmm0, %xmm0               # xmm0 = xmm0[1,1,1,1]
	addss	%xmm4, %xmm0
	unpcklps	%xmm0, %xmm3                    # xmm3 = xmm3[0],xmm0[0],xmm3[1],xmm0[1]
	addss	%xmm5, %xmm1
	movaps	%xmm3, %xmm0
	retq
.Lfunc_end10:
	.size	_Z11gridToSpace15HIP_vector_typeIiLj3EES_IfLj3EEf, .Lfunc_end10-_Z11gridToSpace15HIP_vector_typeIiLj3EES_IfLj3EEf
	.cfi_endproc
                                        # -- End function
	.globl	_Z13flatten3DTo1D15HIP_vector_typeIiLj3EES0_ # -- Begin function _Z13flatten3DTo1D15HIP_vector_typeIiLj3EES0_
	.type	_Z13flatten3DTo1D15HIP_vector_typeIiLj3EES0_,@function
_Z13flatten3DTo1D15HIP_vector_typeIiLj3EES0_: # @_Z13flatten3DTo1D15HIP_vector_typeIiLj3EES0_
	.cfi_startproc
# %bb.0:
	movq	%rdi, %rax
	shrq	$32, %rdi
	shrq	$32, %rdx
	imull	%edx, %eax
	addl	%edi, %eax
	imull	%ecx, %eax
	addl	%esi, %eax
                                        # kill: def $eax killed $eax killed $rax
	retq
.Lfunc_end11:
	.size	_Z13flatten3DTo1D15HIP_vector_typeIiLj3EES0_, .Lfunc_end11-_Z13flatten3DTo1D15HIP_vector_typeIiLj3EES0_
	.cfi_endproc
                                        # -- End function
	.globl	_Z15unflatten1DTo3Di15HIP_vector_typeIiLj3EE # -- Begin function _Z15unflatten1DTo3Di15HIP_vector_typeIiLj3EE
	.type	_Z15unflatten1DTo3Di15HIP_vector_typeIiLj3EE,@function
_Z15unflatten1DTo3Di15HIP_vector_typeIiLj3EE: # @_Z15unflatten1DTo3Di15HIP_vector_typeIiLj3EE
	.cfi_startproc
# %bb.0:
	movl	%edx, %ecx
	movl	%edi, %eax
	shrq	$32, %rsi
	imull	%edx, %esi
	cltd
	idivl	%esi
	movl	%eax, %esi
	movl	%edx, %eax
	cltd
	idivl	%ecx
                                        # kill: def $eax killed $eax def $rax
	shlq	$32, %rax
	orq	%rsi, %rax
	retq
.Lfunc_end12:
	.size	_Z15unflatten1DTo3Di15HIP_vector_typeIiLj3EE, .Lfunc_end12-_Z15unflatten1DTo3Di15HIP_vector_typeIiLj3EE
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__hashAtomsjP15HIP_vector_typeIfLj4EES_IiLj3EES0_PS_IiLj2EEj # -- Begin function _Z24__device_stub__hashAtomsjP15HIP_vector_typeIfLj4EES_IiLj3EES0_PS_IiLj2EEj
	.type	_Z24__device_stub__hashAtomsjP15HIP_vector_typeIfLj4EES_IiLj3EES0_PS_IiLj2EEj,@function
_Z24__device_stub__hashAtomsjP15HIP_vector_typeIfLj4EES_IiLj3EES0_PS_IiLj2EEj: # @_Z24__device_stub__hashAtomsjP15HIP_vector_typeIfLj4EES_IiLj3EES0_PS_IiLj2EEj
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	80(%rsp), %rax
	movq	%rdx, (%rax)
	movl	%ecx, 8(%rax)
	leaq	96(%rsp), %rcx
	movsd	%xmm0, (%rcx)
	movsd	%xmm1, 8(%rcx)
	leaq	12(%rsp), %rdx
	movl	%edi, (%rdx)
	leaq	40(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	32(%rsp), %rsi
	movq	%r8, (%rsi)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	112(%rsp), %rbx
	movq	%rdx, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rax, 16(%rbx)
	movq	%rcx, 24(%rbx)
	movq	%rsi, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9hashAtomsjP15HIP_vector_typeIfLj4EES_IiLj3EES0_PS_IiLj2EEj, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end13:
	.size	_Z24__device_stub__hashAtomsjP15HIP_vector_typeIfLj4EES_IiLj3EES0_PS_IiLj2EEj, .Lfunc_end13-_Z24__device_stub__hashAtomsjP15HIP_vector_typeIfLj4EES_IiLj3EES0_PS_IiLj2EEj
	.cfi_endproc
                                        # -- End function
	.globl	_Z34__device_stub__bitonic_pass_kernelP15HIP_vector_typeIiLj2EEiii # -- Begin function _Z34__device_stub__bitonic_pass_kernelP15HIP_vector_typeIiLj2EEiii
	.type	_Z34__device_stub__bitonic_pass_kernelP15HIP_vector_typeIiLj2EEiii,@function
_Z34__device_stub__bitonic_pass_kernelP15HIP_vector_typeIiLj2EEiii: # @_Z34__device_stub__bitonic_pass_kernelP15HIP_vector_typeIiLj2EEiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19bitonic_pass_kernelP15HIP_vector_typeIiLj2EEiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end14:
	.size	_Z34__device_stub__bitonic_pass_kernelP15HIP_vector_typeIiLj2EEiii, .Lfunc_end14-_Z34__device_stub__bitonic_pass_kernelP15HIP_vector_typeIiLj2EEiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__bitonic_512P15HIP_vector_typeIiLj2EEiii # -- Begin function _Z26__device_stub__bitonic_512P15HIP_vector_typeIiLj2EEiii
	.type	_Z26__device_stub__bitonic_512P15HIP_vector_typeIiLj2EEiii,@function
_Z26__device_stub__bitonic_512P15HIP_vector_typeIiLj2EEiii: # @_Z26__device_stub__bitonic_512P15HIP_vector_typeIiLj2EEiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11bitonic_512P15HIP_vector_typeIiLj2EEiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end15:
	.size	_Z26__device_stub__bitonic_512P15HIP_vector_typeIiLj2EEiii, .Lfunc_end15-_Z26__device_stub__bitonic_512P15HIP_vector_typeIiLj2EEiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__sortCelljP15HIP_vector_typeIfLj4EEPS_IiLj2EES1_S3_ # -- Begin function _Z23__device_stub__sortCelljP15HIP_vector_typeIfLj4EEPS_IiLj2EES1_S3_
	.type	_Z23__device_stub__sortCelljP15HIP_vector_typeIfLj4EEPS_IiLj2EES1_S3_,@function
_Z23__device_stub__sortCelljP15HIP_vector_typeIfLj4EEPS_IiLj2EES1_S3_: # @_Z23__device_stub__sortCelljP15HIP_vector_typeIfLj4EEPS_IiLj2EES1_S3_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	56(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	48(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8sortCelljP15HIP_vector_typeIfLj4EEPS_IiLj2EES1_S3_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end16:
	.size	_Z23__device_stub__sortCelljP15HIP_vector_typeIfLj4EEPS_IiLj2EES1_S3_, .Lfunc_end16-_Z23__device_stub__sortCelljP15HIP_vector_typeIfLj4EEPS_IiLj2EES1_S3_
	.cfi_endproc
                                        # -- End function
	.globl	_Z32__device_stub__probeIntersectionPiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfS3_ji # -- Begin function _Z32__device_stub__probeIntersectionPiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfS3_ji
	.type	_Z32__device_stub__probeIntersectionPiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfS3_ji,@function
_Z32__device_stub__probeIntersectionPiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfS3_ji: # @_Z32__device_stub__probeIntersectionPiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfS3_ji
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$240, %rsp
	.cfi_def_cfa_offset 288
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	80(%rsp), %rax
	movq	%rdx, (%rax)
	movl	%ecx, 8(%rax)
	leaq	112(%rsp), %rcx
	movsd	%xmm0, (%rcx)
	movsd	%xmm1, 8(%rcx)
	leaq	64(%rsp), %rdx
	movq	%r8, (%rdx)
	movl	%r9d, 8(%rdx)
	leaq	96(%rsp), %r8
	movsd	%xmm2, (%r8)
	movsd	%xmm3, 8(%r8)
	leaq	24(%rsp), %r9
	movq	%rdi, (%r9)
	leaq	16(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	128(%rsp), %rbx
	movq	%r9, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rax, 16(%rbx)
	movq	%rcx, 24(%rbx)
	movq	%rdx, 32(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 40(%rbx)
	movq	%r8, 48(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	328(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	344(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	352(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17probeIntersectionPiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfS3_ji, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$256, %rsp                      # imm = 0x100
	.cfi_adjust_cfa_offset -256
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end17:
	.size	_Z32__device_stub__probeIntersectionPiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfS3_ji, .Lfunc_end17-_Z32__device_stub__probeIntersectionPiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfS3_ji
	.cfi_endproc
                                        # -- End function
	.globl	_Z34__device_stub__distanceFieldRefinePiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfjjS3_j # -- Begin function _Z34__device_stub__distanceFieldRefinePiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfjjS3_j
	.type	_Z34__device_stub__distanceFieldRefinePiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfjjS3_j,@function
_Z34__device_stub__distanceFieldRefinePiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfjjS3_j: # @_Z34__device_stub__distanceFieldRefinePiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfjjS3_j
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$240, %rsp
	.cfi_def_cfa_offset 288
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	80(%rsp), %rax
	movq	%rdx, (%rax)
	movl	%ecx, 8(%rax)
	leaq	112(%rsp), %rcx
	movsd	%xmm0, (%rcx)
	movsd	%xmm1, 8(%rcx)
	leaq	64(%rsp), %rdx
	movq	%r8, (%rdx)
	movl	%r9d, 8(%rdx)
	leaq	96(%rsp), %r8
	movsd	%xmm2, (%r8)
	movsd	%xmm3, 8(%r8)
	leaq	24(%rsp), %r9
	movq	%rdi, (%r9)
	leaq	16(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	128(%rsp), %rbx
	movq	%r9, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rax, 16(%rbx)
	movq	%rcx, 24(%rbx)
	movq	%rdx, 32(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 40(%rbx)
	movq	%r8, 48(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	328(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 88(%rbx)
	leaq	344(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	360(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19distanceFieldRefinePiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfjjS3_j, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$256, %rsp                      # imm = 0x100
	.cfi_adjust_cfa_offset -256
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end18:
	.size	_Z34__device_stub__distanceFieldRefinePiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfjjS3_j, .Lfunc_end18-_Z34__device_stub__distanceFieldRefinePiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfjjS3_j
	.cfi_endproc
                                        # -- End function
	.globl	_Z35__device_stub__closestAtomPerVertexPiP15HIP_vector_typeIfLj3EEjS0_IiLj3EES0_IfLj4EES4_PS0_IiLj2EEPS4_ # -- Begin function _Z35__device_stub__closestAtomPerVertexPiP15HIP_vector_typeIfLj3EEjS0_IiLj3EES0_IfLj4EES4_PS0_IiLj2EEPS4_
	.type	_Z35__device_stub__closestAtomPerVertexPiP15HIP_vector_typeIfLj3EEjS0_IiLj3EES0_IfLj4EES4_PS0_IiLj2EEPS4_,@function
_Z35__device_stub__closestAtomPerVertexPiP15HIP_vector_typeIfLj3EEjS0_IiLj3EES0_IfLj4EES4_PS0_IiLj2EEPS4_: # @_Z35__device_stub__closestAtomPerVertexPiP15HIP_vector_typeIfLj3EEjS0_IiLj3EES0_IfLj4EES4_PS0_IiLj2EEPS4_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	80(%rsp), %rax
	movq	%rcx, (%rax)
	movl	%r8d, 8(%rax)
	leaq	112(%rsp), %rcx
	movsd	%xmm0, (%rcx)
	movsd	%xmm1, 8(%rcx)
	leaq	96(%rsp), %r8
	movsd	%xmm2, (%r8)
	movsd	%xmm3, 8(%r8)
	leaq	40(%rsp), %r10
	movq	%rdi, (%r10)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	4(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	24(%rsp), %rdx
	movq	%r9, (%rdx)
	leaq	128(%rsp), %rbx
	movq	%r10, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rax, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%rdx, 48(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z20closestAtomPerVertexPiP15HIP_vector_typeIfLj3EEjS0_IiLj3EES0_IfLj4EES4_PS0_IiLj2EEPS4_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end19:
	.size	_Z35__device_stub__closestAtomPerVertexPiP15HIP_vector_typeIfLj3EEjS0_IiLj3EES0_IfLj4EES4_PS0_IiLj2EEPS4_, .Lfunc_end19-_Z35__device_stub__closestAtomPerVertexPiP15HIP_vector_typeIfLj3EEjS0_IiLj3EES0_IfLj4EES4_PS0_IiLj2EEPS4_
	.cfi_endproc
                                        # -- End function
	.globl	_Z35__device_stub__resetGridValuesSlice15HIP_vector_typeIiLj3EEiS0_Pf # -- Begin function _Z35__device_stub__resetGridValuesSlice15HIP_vector_typeIiLj3EEiS0_Pf
	.type	_Z35__device_stub__resetGridValuesSlice15HIP_vector_typeIiLj3EEiS0_Pf,@function
_Z35__device_stub__resetGridValuesSlice15HIP_vector_typeIiLj3EEiS0_Pf: # @_Z35__device_stub__resetGridValuesSlice15HIP_vector_typeIiLj3EEiS0_Pf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	80(%rsp), %rax
	movq	%rdi, (%rax)
	movl	%esi, 8(%rax)
	leaq	64(%rsp), %rsi
	movq	%rcx, (%rsi)
	movl	%r8d, 8(%rsi)
	leaq	4(%rsp), %rcx
	movl	%edx, (%rcx)
	leaq	24(%rsp), %rdx
	movq	%r9, (%rdx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z20resetGridValuesSlice15HIP_vector_typeIiLj3EEiS0_Pf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end20:
	.size	_Z35__device_stub__resetGridValuesSlice15HIP_vector_typeIiLj3EEiS0_Pf, .Lfunc_end20-_Z35__device_stub__resetGridValuesSlice15HIP_vector_typeIiLj3EEiS0_Pf
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB21_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB21_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18countVertexPerCellf15HIP_vector_typeIiLj3EEPKfPS_IjLj2EEiS0_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13compactVoxelsPjPK15HIP_vector_typeIjLj2EEjjjS0_IiLj3EEiS4_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z28generateTriangleVerticesSMEMP15HIP_vector_typeIfLj3EEPKjPKS_IjLj2EEPKfS_IfLj4EEfjjS_IiLj3EESA_, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13groupVerticesP15HIP_vector_typeIfLj3EEjf, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15LaplacianSmoothP15HIP_vector_typeIfLj3EEPijjj, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15memsetCudaFloatPffi, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13memsetCudaIntPiii, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14memsetCudaInt2P15HIP_vector_typeIiLj2EES0_i, %esi
	movl	$.L__unnamed_8, %edx
	movl	$.L__unnamed_8, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15memsetCudaUInt2P15HIP_vector_typeIjLj2EES0_i, %esi
	movl	$.L__unnamed_9, %edx
	movl	$.L__unnamed_9, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9hashAtomsjP15HIP_vector_typeIfLj4EES_IiLj3EES0_PS_IiLj2EEj, %esi
	movl	$.L__unnamed_10, %edx
	movl	$.L__unnamed_10, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19bitonic_pass_kernelP15HIP_vector_typeIiLj2EEiii, %esi
	movl	$.L__unnamed_11, %edx
	movl	$.L__unnamed_11, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11bitonic_512P15HIP_vector_typeIiLj2EEiii, %esi
	movl	$.L__unnamed_12, %edx
	movl	$.L__unnamed_12, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8sortCelljP15HIP_vector_typeIfLj4EEPS_IiLj2EES1_S3_, %esi
	movl	$.L__unnamed_13, %edx
	movl	$.L__unnamed_13, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17probeIntersectionPiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfS3_ji, %esi
	movl	$.L__unnamed_14, %edx
	movl	$.L__unnamed_14, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19distanceFieldRefinePiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfjjS3_j, %esi
	movl	$.L__unnamed_15, %edx
	movl	$.L__unnamed_15, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z20closestAtomPerVertexPiP15HIP_vector_typeIfLj3EEjS0_IiLj3EES0_IfLj4EES4_PS0_IiLj2EEPS4_, %esi
	movl	$.L__unnamed_16, %edx
	movl	$.L__unnamed_16, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z20resetGridValuesSlice15HIP_vector_typeIiLj3EEiS0_Pf, %esi
	movl	$.L__unnamed_17, %edx
	movl	$.L__unnamed_17, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$edgeTable, %esi
	movl	$.L__unnamed_18, %edx
	movl	$.L__unnamed_18, %ecx
	movl	$1024, %r9d                     # imm = 0x400
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$triTable, %esi
	movl	$.L__unnamed_19, %edx
	movl	$.L__unnamed_19, %ecx
	movl	$16384, %r9d                    # imm = 0x4000
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$0, 8(%rsp)
	movl	$1, (%rsp)
	movl	$nbTriTable, %esi
	movl	$.L__unnamed_20, %edx
	movl	$.L__unnamed_20, %ecx
	movl	$1024, %r9d                     # imm = 0x400
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end21:
	.size	__hip_module_ctor, .Lfunc_end21-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB22_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB22_2:
	retq
.Lfunc_end22:
	.size	__hip_module_dtor, .Lfunc_end22-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	edgeTable,@object               # @edgeTable
	.local	edgeTable
	.comm	edgeTable,1024,16
	.type	triTable,@object                # @triTable
	.local	triTable
	.comm	triTable,16384,16
	.type	nbTriTable,@object              # @nbTriTable
	.local	nbTriTable
	.comm	nbTriTable,1024,16
	.type	_Z18countVertexPerCellf15HIP_vector_typeIiLj3EEPKfPS_IjLj2EEiS0_,@object # @_Z18countVertexPerCellf15HIP_vector_typeIiLj3EEPKfPS_IjLj2EEiS0_
	.section	.rodata,"a",@progbits
	.globl	_Z18countVertexPerCellf15HIP_vector_typeIiLj3EEPKfPS_IjLj2EEiS0_
	.p2align	3, 0x0
_Z18countVertexPerCellf15HIP_vector_typeIiLj3EEPKfPS_IjLj2EEiS0_:
	.quad	_Z33__device_stub__countVertexPerCellf15HIP_vector_typeIiLj3EEPKfPS_IjLj2EEiS0_
	.size	_Z18countVertexPerCellf15HIP_vector_typeIiLj3EEPKfPS_IjLj2EEiS0_, 8

	.type	_Z13compactVoxelsPjPK15HIP_vector_typeIjLj2EEjjjS0_IiLj3EEiS4_,@object # @_Z13compactVoxelsPjPK15HIP_vector_typeIjLj2EEjjjS0_IiLj3EEiS4_
	.globl	_Z13compactVoxelsPjPK15HIP_vector_typeIjLj2EEjjjS0_IiLj3EEiS4_
	.p2align	3, 0x0
_Z13compactVoxelsPjPK15HIP_vector_typeIjLj2EEjjjS0_IiLj3EEiS4_:
	.quad	_Z28__device_stub__compactVoxelsPjPK15HIP_vector_typeIjLj2EEjjjS0_IiLj3EEiS4_
	.size	_Z13compactVoxelsPjPK15HIP_vector_typeIjLj2EEjjjS0_IiLj3EEiS4_, 8

	.type	_Z28generateTriangleVerticesSMEMP15HIP_vector_typeIfLj3EEPKjPKS_IjLj2EEPKfS_IfLj4EEfjjS_IiLj3EESA_,@object # @_Z28generateTriangleVerticesSMEMP15HIP_vector_typeIfLj3EEPKjPKS_IjLj2EEPKfS_IfLj4EEfjjS_IiLj3EESA_
	.globl	_Z28generateTriangleVerticesSMEMP15HIP_vector_typeIfLj3EEPKjPKS_IjLj2EEPKfS_IfLj4EEfjjS_IiLj3EESA_
	.p2align	3, 0x0
_Z28generateTriangleVerticesSMEMP15HIP_vector_typeIfLj3EEPKjPKS_IjLj2EEPKfS_IfLj4EEfjjS_IiLj3EESA_:
	.quad	_Z43__device_stub__generateTriangleVerticesSMEMP15HIP_vector_typeIfLj3EEPKjPKS_IjLj2EEPKfS_IfLj4EEfjjS_IiLj3EESA_
	.size	_Z28generateTriangleVerticesSMEMP15HIP_vector_typeIfLj3EEPKjPKS_IjLj2EEPKfS_IfLj4EEfjjS_IiLj3EESA_, 8

	.type	_Z13groupVerticesP15HIP_vector_typeIfLj3EEjf,@object # @_Z13groupVerticesP15HIP_vector_typeIfLj3EEjf
	.globl	_Z13groupVerticesP15HIP_vector_typeIfLj3EEjf
	.p2align	3, 0x0
_Z13groupVerticesP15HIP_vector_typeIfLj3EEjf:
	.quad	_Z28__device_stub__groupVerticesP15HIP_vector_typeIfLj3EEjf
	.size	_Z13groupVerticesP15HIP_vector_typeIfLj3EEjf, 8

	.type	_Z15LaplacianSmoothP15HIP_vector_typeIfLj3EEPijjj,@object # @_Z15LaplacianSmoothP15HIP_vector_typeIfLj3EEPijjj
	.globl	_Z15LaplacianSmoothP15HIP_vector_typeIfLj3EEPijjj
	.p2align	3, 0x0
_Z15LaplacianSmoothP15HIP_vector_typeIfLj3EEPijjj:
	.quad	_Z30__device_stub__LaplacianSmoothP15HIP_vector_typeIfLj3EEPijjj
	.size	_Z15LaplacianSmoothP15HIP_vector_typeIfLj3EEPijjj, 8

	.type	_Z15memsetCudaFloatPffi,@object # @_Z15memsetCudaFloatPffi
	.globl	_Z15memsetCudaFloatPffi
	.p2align	3, 0x0
_Z15memsetCudaFloatPffi:
	.quad	_Z30__device_stub__memsetCudaFloatPffi
	.size	_Z15memsetCudaFloatPffi, 8

	.type	_Z13memsetCudaIntPiii,@object   # @_Z13memsetCudaIntPiii
	.globl	_Z13memsetCudaIntPiii
	.p2align	3, 0x0
_Z13memsetCudaIntPiii:
	.quad	_Z28__device_stub__memsetCudaIntPiii
	.size	_Z13memsetCudaIntPiii, 8

	.type	_Z14memsetCudaInt2P15HIP_vector_typeIiLj2EES0_i,@object # @_Z14memsetCudaInt2P15HIP_vector_typeIiLj2EES0_i
	.globl	_Z14memsetCudaInt2P15HIP_vector_typeIiLj2EES0_i
	.p2align	3, 0x0
_Z14memsetCudaInt2P15HIP_vector_typeIiLj2EES0_i:
	.quad	_Z29__device_stub__memsetCudaInt2P15HIP_vector_typeIiLj2EES0_i
	.size	_Z14memsetCudaInt2P15HIP_vector_typeIiLj2EES0_i, 8

	.type	_Z15memsetCudaUInt2P15HIP_vector_typeIjLj2EES0_i,@object # @_Z15memsetCudaUInt2P15HIP_vector_typeIjLj2EES0_i
	.globl	_Z15memsetCudaUInt2P15HIP_vector_typeIjLj2EES0_i
	.p2align	3, 0x0
_Z15memsetCudaUInt2P15HIP_vector_typeIjLj2EES0_i:
	.quad	_Z30__device_stub__memsetCudaUInt2P15HIP_vector_typeIjLj2EES0_i
	.size	_Z15memsetCudaUInt2P15HIP_vector_typeIjLj2EES0_i, 8

	.type	_Z9hashAtomsjP15HIP_vector_typeIfLj4EES_IiLj3EES0_PS_IiLj2EEj,@object # @_Z9hashAtomsjP15HIP_vector_typeIfLj4EES_IiLj3EES0_PS_IiLj2EEj
	.globl	_Z9hashAtomsjP15HIP_vector_typeIfLj4EES_IiLj3EES0_PS_IiLj2EEj
	.p2align	3, 0x0
_Z9hashAtomsjP15HIP_vector_typeIfLj4EES_IiLj3EES0_PS_IiLj2EEj:
	.quad	_Z24__device_stub__hashAtomsjP15HIP_vector_typeIfLj4EES_IiLj3EES0_PS_IiLj2EEj
	.size	_Z9hashAtomsjP15HIP_vector_typeIfLj4EES_IiLj3EES0_PS_IiLj2EEj, 8

	.type	_Z19bitonic_pass_kernelP15HIP_vector_typeIiLj2EEiii,@object # @_Z19bitonic_pass_kernelP15HIP_vector_typeIiLj2EEiii
	.globl	_Z19bitonic_pass_kernelP15HIP_vector_typeIiLj2EEiii
	.p2align	3, 0x0
_Z19bitonic_pass_kernelP15HIP_vector_typeIiLj2EEiii:
	.quad	_Z34__device_stub__bitonic_pass_kernelP15HIP_vector_typeIiLj2EEiii
	.size	_Z19bitonic_pass_kernelP15HIP_vector_typeIiLj2EEiii, 8

	.type	_Z11bitonic_512P15HIP_vector_typeIiLj2EEiii,@object # @_Z11bitonic_512P15HIP_vector_typeIiLj2EEiii
	.globl	_Z11bitonic_512P15HIP_vector_typeIiLj2EEiii
	.p2align	3, 0x0
_Z11bitonic_512P15HIP_vector_typeIiLj2EEiii:
	.quad	_Z26__device_stub__bitonic_512P15HIP_vector_typeIiLj2EEiii
	.size	_Z11bitonic_512P15HIP_vector_typeIiLj2EEiii, 8

	.type	_Z8sortCelljP15HIP_vector_typeIfLj4EEPS_IiLj2EES1_S3_,@object # @_Z8sortCelljP15HIP_vector_typeIfLj4EEPS_IiLj2EES1_S3_
	.globl	_Z8sortCelljP15HIP_vector_typeIfLj4EEPS_IiLj2EES1_S3_
	.p2align	3, 0x0
_Z8sortCelljP15HIP_vector_typeIfLj4EEPS_IiLj2EES1_S3_:
	.quad	_Z23__device_stub__sortCelljP15HIP_vector_typeIfLj4EEPS_IiLj2EES1_S3_
	.size	_Z8sortCelljP15HIP_vector_typeIfLj4EEPS_IiLj2EES1_S3_, 8

	.type	_Z17probeIntersectionPiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfS3_ji,@object # @_Z17probeIntersectionPiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfS3_ji
	.globl	_Z17probeIntersectionPiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfS3_ji
	.p2align	3, 0x0
_Z17probeIntersectionPiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfS3_ji:
	.quad	_Z32__device_stub__probeIntersectionPiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfS3_ji
	.size	_Z17probeIntersectionPiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfS3_ji, 8

	.type	_Z19distanceFieldRefinePiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfjjS3_j,@object # @_Z19distanceFieldRefinePiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfjjS3_j
	.globl	_Z19distanceFieldRefinePiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfjjS3_j
	.p2align	3, 0x0
_Z19distanceFieldRefinePiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfjjS3_j:
	.quad	_Z34__device_stub__distanceFieldRefinePiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfjjS3_j
	.size	_Z19distanceFieldRefinePiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfjjS3_j, 8

	.type	_Z20closestAtomPerVertexPiP15HIP_vector_typeIfLj3EEjS0_IiLj3EES0_IfLj4EES4_PS0_IiLj2EEPS4_,@object # @_Z20closestAtomPerVertexPiP15HIP_vector_typeIfLj3EEjS0_IiLj3EES0_IfLj4EES4_PS0_IiLj2EEPS4_
	.globl	_Z20closestAtomPerVertexPiP15HIP_vector_typeIfLj3EEjS0_IiLj3EES0_IfLj4EES4_PS0_IiLj2EEPS4_
	.p2align	3, 0x0
_Z20closestAtomPerVertexPiP15HIP_vector_typeIfLj3EEjS0_IiLj3EES0_IfLj4EES4_PS0_IiLj2EEPS4_:
	.quad	_Z35__device_stub__closestAtomPerVertexPiP15HIP_vector_typeIfLj3EEjS0_IiLj3EES0_IfLj4EES4_PS0_IiLj2EEPS4_
	.size	_Z20closestAtomPerVertexPiP15HIP_vector_typeIfLj3EEjS0_IiLj3EES0_IfLj4EES4_PS0_IiLj2EEPS4_, 8

	.type	_Z20resetGridValuesSlice15HIP_vector_typeIiLj3EEiS0_Pf,@object # @_Z20resetGridValuesSlice15HIP_vector_typeIiLj3EEiS0_Pf
	.globl	_Z20resetGridValuesSlice15HIP_vector_typeIiLj3EEiS0_Pf
	.p2align	3, 0x0
_Z20resetGridValuesSlice15HIP_vector_typeIiLj3EEiS0_Pf:
	.quad	_Z35__device_stub__resetGridValuesSlice15HIP_vector_typeIiLj3EEiS0_Pf
	.size	_Z20resetGridValuesSlice15HIP_vector_typeIiLj3EEiS0_Pf, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z18countVertexPerCellf15HIP_vector_typeIiLj3EEPKfPS_IjLj2EEiS0_"
	.size	.L__unnamed_1, 65

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z13compactVoxelsPjPK15HIP_vector_typeIjLj2EEjjjS0_IiLj3EEiS4_"
	.size	.L__unnamed_2, 63

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z28generateTriangleVerticesSMEMP15HIP_vector_typeIfLj3EEPKjPKS_IjLj2EEPKfS_IfLj4EEfjjS_IiLj3EESA_"
	.size	.L__unnamed_3, 99

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z13groupVerticesP15HIP_vector_typeIfLj3EEjf"
	.size	.L__unnamed_4, 45

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z15LaplacianSmoothP15HIP_vector_typeIfLj3EEPijjj"
	.size	.L__unnamed_5, 50

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_Z15memsetCudaFloatPffi"
	.size	.L__unnamed_6, 24

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"_Z13memsetCudaIntPiii"
	.size	.L__unnamed_7, 22

	.type	.L__unnamed_8,@object           # @7
.L__unnamed_8:
	.asciz	"_Z14memsetCudaInt2P15HIP_vector_typeIiLj2EES0_i"
	.size	.L__unnamed_8, 48

	.type	.L__unnamed_9,@object           # @8
.L__unnamed_9:
	.asciz	"_Z15memsetCudaUInt2P15HIP_vector_typeIjLj2EES0_i"
	.size	.L__unnamed_9, 49

	.type	.L__unnamed_10,@object          # @9
.L__unnamed_10:
	.asciz	"_Z9hashAtomsjP15HIP_vector_typeIfLj4EES_IiLj3EES0_PS_IiLj2EEj"
	.size	.L__unnamed_10, 62

	.type	.L__unnamed_11,@object          # @10
.L__unnamed_11:
	.asciz	"_Z19bitonic_pass_kernelP15HIP_vector_typeIiLj2EEiii"
	.size	.L__unnamed_11, 52

	.type	.L__unnamed_12,@object          # @11
.L__unnamed_12:
	.asciz	"_Z11bitonic_512P15HIP_vector_typeIiLj2EEiii"
	.size	.L__unnamed_12, 44

	.type	.L__unnamed_13,@object          # @12
.L__unnamed_13:
	.asciz	"_Z8sortCelljP15HIP_vector_typeIfLj4EEPS_IiLj2EES1_S3_"
	.size	.L__unnamed_13, 54

	.type	.L__unnamed_14,@object          # @13
.L__unnamed_14:
	.asciz	"_Z17probeIntersectionPiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfS3_ji"
	.size	.L__unnamed_14, 92

	.type	.L__unnamed_15,@object          # @14
.L__unnamed_15:
	.asciz	"_Z19distanceFieldRefinePiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfjjS3_j"
	.size	.L__unnamed_15, 95

	.type	.L__unnamed_16,@object          # @15
.L__unnamed_16:
	.asciz	"_Z20closestAtomPerVertexPiP15HIP_vector_typeIfLj3EEjS0_IiLj3EES0_IfLj4EES4_PS0_IiLj2EEPS4_"
	.size	.L__unnamed_16, 91

	.type	.L__unnamed_17,@object          # @16
.L__unnamed_17:
	.asciz	"_Z20resetGridValuesSlice15HIP_vector_typeIiLj3EEiS0_Pf"
	.size	.L__unnamed_17, 55

	.type	.L__unnamed_18,@object          # @17
.L__unnamed_18:
	.asciz	"edgeTable"
	.size	.L__unnamed_18, 10

	.type	.L__unnamed_19,@object          # @18
.L__unnamed_19:
	.asciz	"triTable"
	.size	.L__unnamed_19, 9

	.type	.L__unnamed_20,@object          # @19
.L__unnamed_20:
	.asciz	"nbTriTable"
	.size	.L__unnamed_20, 11

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z33__device_stub__countVertexPerCellf15HIP_vector_typeIiLj3EEPKfPS_IjLj2EEiS0_
	.addrsig_sym _Z28__device_stub__compactVoxelsPjPK15HIP_vector_typeIjLj2EEjjjS0_IiLj3EEiS4_
	.addrsig_sym _Z43__device_stub__generateTriangleVerticesSMEMP15HIP_vector_typeIfLj3EEPKjPKS_IjLj2EEPKfS_IfLj4EEfjjS_IiLj3EESA_
	.addrsig_sym _Z28__device_stub__groupVerticesP15HIP_vector_typeIfLj3EEjf
	.addrsig_sym _Z30__device_stub__LaplacianSmoothP15HIP_vector_typeIfLj3EEPijjj
	.addrsig_sym _Z30__device_stub__memsetCudaFloatPffi
	.addrsig_sym _Z28__device_stub__memsetCudaIntPiii
	.addrsig_sym _Z29__device_stub__memsetCudaInt2P15HIP_vector_typeIiLj2EES0_i
	.addrsig_sym _Z30__device_stub__memsetCudaUInt2P15HIP_vector_typeIjLj2EES0_i
	.addrsig_sym _Z24__device_stub__hashAtomsjP15HIP_vector_typeIfLj4EES_IiLj3EES0_PS_IiLj2EEj
	.addrsig_sym _Z34__device_stub__bitonic_pass_kernelP15HIP_vector_typeIiLj2EEiii
	.addrsig_sym _Z26__device_stub__bitonic_512P15HIP_vector_typeIiLj2EEiii
	.addrsig_sym _Z23__device_stub__sortCelljP15HIP_vector_typeIfLj4EEPS_IiLj2EES1_S3_
	.addrsig_sym _Z32__device_stub__probeIntersectionPiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfS3_ji
	.addrsig_sym _Z34__device_stub__distanceFieldRefinePiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfjjS3_j
	.addrsig_sym _Z35__device_stub__closestAtomPerVertexPiP15HIP_vector_typeIfLj3EEjS0_IiLj3EES0_IfLj4EES4_PS0_IiLj2EEPS4_
	.addrsig_sym _Z35__device_stub__resetGridValuesSlice15HIP_vector_typeIiLj3EEiS0_Pf
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym edgeTable
	.addrsig_sym triTable
	.addrsig_sym nbTriTable
	.addrsig_sym _Z18countVertexPerCellf15HIP_vector_typeIiLj3EEPKfPS_IjLj2EEiS0_
	.addrsig_sym _Z13compactVoxelsPjPK15HIP_vector_typeIjLj2EEjjjS0_IiLj3EEiS4_
	.addrsig_sym _Z28generateTriangleVerticesSMEMP15HIP_vector_typeIfLj3EEPKjPKS_IjLj2EEPKfS_IfLj4EEfjjS_IiLj3EESA_
	.addrsig_sym _Z13groupVerticesP15HIP_vector_typeIfLj3EEjf
	.addrsig_sym _Z15LaplacianSmoothP15HIP_vector_typeIfLj3EEPijjj
	.addrsig_sym _Z15memsetCudaFloatPffi
	.addrsig_sym _Z13memsetCudaIntPiii
	.addrsig_sym _Z14memsetCudaInt2P15HIP_vector_typeIiLj2EES0_i
	.addrsig_sym _Z15memsetCudaUInt2P15HIP_vector_typeIjLj2EES0_i
	.addrsig_sym _Z9hashAtomsjP15HIP_vector_typeIfLj4EES_IiLj3EES0_PS_IiLj2EEj
	.addrsig_sym _Z19bitonic_pass_kernelP15HIP_vector_typeIiLj2EEiii
	.addrsig_sym _Z11bitonic_512P15HIP_vector_typeIiLj2EEiii
	.addrsig_sym _Z8sortCelljP15HIP_vector_typeIfLj4EEPS_IiLj2EES1_S3_
	.addrsig_sym _Z17probeIntersectionPiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfS3_ji
	.addrsig_sym _Z19distanceFieldRefinePiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfjjS3_j
	.addrsig_sym _Z20closestAtomPerVertexPiP15HIP_vector_typeIfLj3EEjS0_IiLj3EES0_IfLj4EES4_PS0_IiLj2EEPS4_
	.addrsig_sym _Z20resetGridValuesSlice15HIP_vector_typeIiLj3EEiS0_Pf
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z18countVertexPerCellf15HIP_vector_typeIiLj3EEPKfPS_IjLj2EEiS0_ ; -- Begin function _Z18countVertexPerCellf15HIP_vector_typeIiLj3EEPKfPS_IjLj2EEiS0_
	.globl	_Z18countVertexPerCellf15HIP_vector_typeIiLj3EEPKfPS_IjLj2EEiS0_
	.p2align	8
	.type	_Z18countVertexPerCellf15HIP_vector_typeIiLj3EEPKfPS_IjLj2EEiS0_,@function
_Z18countVertexPerCellf15HIP_vector_typeIiLj3EEPKfPS_IjLj2EEiS0_: ; @_Z18countVertexPerCellf15HIP_vector_typeIiLj3EEPKfPS_IjLj2EEiS0_
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x3c
	s_load_b128 s[4:7], s[0:1], 0x0
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v6, v0, 10, 10
	v_bfe_u32 v7, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s8, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[4:5], null, s13, s2, v[1:2]
	v_mad_u64_u32 v[2:3], null, s14, s8, v[6:7]
	s_and_b32 s2, s3, 0xffff
	s_add_i32 s3, s6, -2
	v_mad_u64_u32 v[0:1], null, s15, s2, v[7:8]
	s_add_i32 s2, s5, -2
	s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
	v_cmp_ge_u32_e32 vcc_lo, s2, v4
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_ge_u32_e64 s2, s3, v2
	s_add_i32 s3, s7, -2
	s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
	v_cmp_ge_u32_e64 s3, s3, v0
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_15
; %bb.1:
	s_load_b128 s[8:11], s[0:1], 0x20
	s_waitcnt lgkmcnt(0)
	s_cmp_eq_u32 s9, 0
	s_cselect_b32 s3, -1, 0
	s_add_i32 s2, s8, -3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s2, v4
	s_or_b32 s3, s3, vcc_lo
	s_and_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB0_15
; %bb.2:
	v_cmp_le_u32_e32 vcc_lo, s2, v2
	s_cmp_eq_u32 s10, 0
	s_cselect_b32 s3, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s3, s3, vcc_lo
	s_and_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB0_15
; %bb.3:
	v_cmp_le_u32_e32 vcc_lo, s2, v0
	s_cmp_eq_u32 s11, 0
	s_cselect_b32 s2, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, s2, vcc_lo
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB0_15
; %bb.4:
	s_cmp_lg_u32 s9, 0
	s_cselect_b32 s2, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB0_6
; %bb.5:
	s_lshl_b32 s3, s8, 1
	s_and_not1_b32 s2, s2, exec_lo
	s_not_b32 s3, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s3, s5, s3
	v_cmp_gt_u32_e32 vcc_lo, s3, v4
	s_and_b32 s3, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s2, s2, s3
.LBB0_6:                                ; %Flow387
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB0_15
; %bb.7:
	s_cmp_lg_u32 s10, 0
	s_cselect_b32 s2, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB0_9
; %bb.8:
	s_lshl_b32 s3, s8, 1
	s_and_not1_b32 s2, s2, exec_lo
	s_not_b32 s3, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s3, s6, s3
	v_cmp_gt_u32_e32 vcc_lo, s3, v2
	s_and_b32 s3, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s2, s2, s3
.LBB0_9:                                ; %Flow384
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB0_15
; %bb.10:
	s_cmp_lg_u32 s11, 0
	s_cselect_b32 s2, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB0_12
; %bb.11:
	s_lshl_b32 s3, s8, 1
	s_and_not1_b32 s2, s2, exec_lo
	s_not_b32 s3, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s3, s7, s3
	v_cmp_gt_u32_e32 vcc_lo, s3, v0
	s_and_b32 s3, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s2, s2, s3
.LBB0_12:                               ; %Flow381
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB0_15
; %bb.13:
	s_not_b32 s3, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s5, s3
	s_add_i32 s5, s6, s3
	v_cmp_gt_u32_e32 vcc_lo, s2, v4
	v_cmp_gt_u32_e64 s2, s5, v2
	s_add_i32 s3, s7, s3
	v_cmp_gt_u32_e64 s3, s3, v0
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB0_15
; %bb.14:
	v_mul_lo_u32 v1, v4, s6
	v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v4, 1, v2
	s_load_b128 s[0:3], s[0:1], 0x10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v9, v3 :: v_dual_add_nc_u32 v16, 1, v0
	v_add_nc_u32_e32 v5, s6, v1
	v_add_nc_u32_e32 v6, v1, v2
	v_add_nc_u32_e32 v1, v4, v1
	v_mov_b32_e32 v7, v3
	s_delay_alu instid0(VALU_DEP_4)
	v_dual_mov_b32 v13, v3 :: v_dual_add_nc_u32 v2, v5, v2
	v_dual_mov_b32 v5, v3 :: v_dual_add_nc_u32 v4, v5, v4
	v_mul_lo_u32 v8, v6, s7
	v_mul_lo_u32 v17, v1, s7
	v_mov_b32_e32 v1, v3
	v_mul_lo_u32 v12, v2, s7
	v_mul_lo_u32 v14, v4, s7
	v_dual_mov_b32 v15, v3 :: v_dual_add_nc_u32 v2, v8, v0
	v_add_nc_u32_e32 v6, v17, v0
	v_add_nc_u32_e32 v8, v8, v16
	v_add_nc_u32_e32 v4, v12, v0
	v_add_nc_u32_e32 v0, v14, v0
	v_lshlrev_b64 v[10:11], 2, v[2:3]
	v_add_nc_u32_e32 v12, v12, v16
	v_add_nc_u32_e32 v14, v14, v16
	v_dual_mov_b32 v17, v3 :: v_dual_add_nc_u32 v16, v17, v16
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v10, vcc_lo, s0, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s1, v11, vcc_lo
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_add_co_u32 v4, vcc_lo, s0, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	v_add_co_u32 v6, vcc_lo, s0, v6
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
	v_add_co_u32 v8, vcc_lo, s0, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s1, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v12, vcc_lo, s0, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s1, v13, vcc_lo
	s_clause 0x5
	global_load_b32 v10, v[10:11], off
	global_load_b32 v11, v[4:5], off
	global_load_b32 v18, v[0:1], off
	global_load_b32 v6, v[6:7], off
	global_load_b32 v7, v[8:9], off
	global_load_b32 v8, v[12:13], off
	v_lshlrev_b64 v[14:15], 2, v[14:15]
	v_lshlrev_b64 v[0:1], 2, v[16:17]
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v4, vcc_lo, s0, v14
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_clause 0x1
	global_load_b32 v4, v[4:5], off
	global_load_b32 v0, v[0:1], off
	s_waitcnt vmcnt(7)
	v_cmp_gt_f32_e32 vcc_lo, s4, v10
	v_cndmask_b32_e64 v1, 0, 1, vcc_lo
	s_waitcnt vmcnt(6)
	v_cmp_gt_f32_e32 vcc_lo, s4, v11
	v_cndmask_b32_e64 v5, 0, 1, vcc_lo
	s_waitcnt vmcnt(5)
	v_cmp_gt_f32_e32 vcc_lo, s4, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v5, 1, v5
	v_cndmask_b32_e64 v9, 0, 1, vcc_lo
	s_waitcnt vmcnt(4)
	v_cmp_gt_f32_e32 vcc_lo, s4, v6
	v_or_b32_e32 v1, v5, v1
	v_cndmask_b32_e64 v6, 0, 1, vcc_lo
	s_waitcnt vmcnt(3)
	v_cmp_gt_f32_e32 vcc_lo, s4, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshl_or_b32 v1, v9, 2, v1
	v_lshlrev_b32_e32 v5, 3, v6
	v_cndmask_b32_e64 v7, 0, 1, vcc_lo
	s_waitcnt vmcnt(2)
	v_cmp_gt_f32_e32 vcc_lo, s4, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v6, 4, v7
	v_cndmask_b32_e64 v8, 0, 1, vcc_lo
	s_waitcnt vmcnt(1)
	v_cmp_gt_f32_e32 vcc_lo, s4, v4
	v_or3_b32 v1, v1, v5, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v7, 5, v8
	v_cndmask_b32_e64 v4, 0, 1, vcc_lo
	s_waitcnt vmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, s4, v0
	v_lshlrev_b32_e32 v4, 6, v4
	v_cndmask_b32_e64 v0, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or3_b32 v1, v1, v7, v4
	v_lshlrev_b32_e32 v0, 7, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v0, s0, v1, v0
	v_add_co_ci_u32_e64 v1, null, 0, 0, s0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, nbTriTable@rel32@lo+4
	s_addc_u32 s1, s1, nbTriTable@rel32@hi+12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v0, vcc_lo, v0, s0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_load_b32 v0, v[0:1], off
	s_waitcnt vmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, 0, v0
	v_cndmask_b32_e64 v1, 0, 1, vcc_lo
	v_add_co_u32 v2, vcc_lo, s2, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	global_store_b64 v[2:3], v[0:1], off
.LBB0_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18countVertexPerCellf15HIP_vector_typeIiLj3EEPKfPS_IjLj2EEiS0_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 19
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z18countVertexPerCellf15HIP_vector_typeIiLj3EEPKfPS_IjLj2EEiS0_, .Lfunc_end0-_Z18countVertexPerCellf15HIP_vector_typeIiLj3EEPKfPS_IjLj2EEiS0_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1268
; NumSgprs: 18
; NumVgprs: 19
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 19
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	_Z13compactVoxelsPjPK15HIP_vector_typeIjLj2EEjjjS0_IiLj3EEiS4_ ; -- Begin function _Z13compactVoxelsPjPK15HIP_vector_typeIjLj2EEjjjS0_IiLj3EEiS4_
	.globl	_Z13compactVoxelsPjPK15HIP_vector_typeIjLj2EEjjjS0_IiLj3EEiS4_
	.p2align	8
	.type	_Z13compactVoxelsPjPK15HIP_vector_typeIjLj2EEjjjS0_IiLj3EEiS4_,@function
_Z13compactVoxelsPjPK15HIP_vector_typeIjLj2EEjjjS0_IiLj3EEiS4_: ; @_Z13compactVoxelsPjPK15HIP_vector_typeIjLj2EEjjjS0_IiLj3EEiS4_
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x44
	s_load_b256 s[4:11], s[0:1], 0x10
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	v_bfe_u32 v4, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s12, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s13, s2, v[2:3]
	v_mad_u64_u32 v[1:2], null, s14, s12, v[3:4]
	s_and_b32 s2, s3, 0xffff
	s_add_i32 s3, s8, -2
	v_mad_u64_u32 v[2:3], null, s15, s2, v[4:5]
	s_add_i32 s2, s7, -2
	s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
	v_cmp_ge_u32_e32 vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_ge_u32_e64 s2, s3, v1
	s_add_i32 s3, s9, -2
	s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
	v_cmp_ge_u32_e64 s3, s3, v2
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_19
; %bb.1:
	s_load_b64 s[2:3], s[0:1], 0x30
	s_cmp_eq_u32 s11, 0
	s_cselect_b32 s13, -1, 0
	s_add_i32 s12, s10, -3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s12, v0
	s_or_b32 s13, s13, vcc_lo
	s_and_b32 exec_lo, exec_lo, s13
	s_cbranch_execz .LBB1_19
; %bb.2:
	v_cmp_le_u32_e32 vcc_lo, s12, v1
	s_waitcnt lgkmcnt(0)
	s_cmp_eq_u32 s2, 0
	s_cselect_b32 s13, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s13, s13, vcc_lo
	s_and_b32 exec_lo, exec_lo, s13
	s_cbranch_execz .LBB1_19
; %bb.3:
	v_cmp_le_u32_e32 vcc_lo, s12, v2
	s_cmp_eq_u32 s3, 0
	s_cselect_b32 s12, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s12, s12, vcc_lo
	s_and_b32 exec_lo, exec_lo, s12
	s_cbranch_execz .LBB1_19
; %bb.4:
	s_cmp_lg_u32 s11, 0
	s_cselect_b32 s11, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s11
	s_cbranch_vccnz .LBB1_6
; %bb.5:
	s_lshl_b32 s12, s10, 1
	s_and_not1_b32 s11, s11, exec_lo
	s_not_b32 s12, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s12, s7, s12
	v_cmp_gt_u32_e32 vcc_lo, s12, v0
	s_and_b32 s12, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s11, s11, s12
.LBB1_6:                                ; %Flow120
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s11
	s_cbranch_execz .LBB1_19
; %bb.7:
	s_cmp_lg_u32 s2, 0
	s_cselect_b32 s2, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB1_9
; %bb.8:
	s_lshl_b32 s11, s10, 1
	s_and_not1_b32 s2, s2, exec_lo
	s_not_b32 s11, s11
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s11, s8, s11
	v_cmp_gt_u32_e32 vcc_lo, s11, v1
	s_and_b32 s11, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s2, s2, s11
.LBB1_9:                                ; %Flow117
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB1_19
; %bb.10:
	s_cmp_lg_u32 s3, 0
	s_cselect_b32 s2, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB1_12
; %bb.11:
	s_lshl_b32 s3, s10, 1
	s_and_not1_b32 s2, s2, exec_lo
	s_not_b32 s3, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s3, s9, s3
	v_cmp_gt_u32_e32 vcc_lo, s3, v2
	s_and_b32 s3, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s2, s2, s3
.LBB1_12:                               ; %Flow114
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB1_19
; %bb.13:
	s_not_b32 s3, s10
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	s_add_i32 s2, s7, s3
	s_add_i32 s7, s8, s3
	v_cmp_gt_u32_e32 vcc_lo, s2, v0
	v_cmp_gt_u32_e64 s2, s7, v1
	s_add_i32 s3, s9, s3
	v_cmp_gt_u32_e64 s3, s3, v2
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB1_19
; %bb.14:
	v_mad_u64_u32 v[3:4], null, v0, s8, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, v3, s9, v[2:3]
	v_cmp_gt_u32_e32 vcc_lo, s5, v0
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_19
; %bb.15:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_mov_b32_e32 v1, s4
	s_mov_b32 s4, exec_lo
	v_cmpx_gt_u32_e64 s6, v0
	s_cbranch_execz .LBB1_17
; %bb.16:
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v1, vcc_lo, s2, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	s_clause 0x1
	global_load_b32 v3, v[1:2], off offset:4
	global_load_b32 v1, v[1:2], off offset:12
	s_waitcnt vmcnt(0)
	v_cmp_lt_u32_e32 vcc_lo, v3, v1
	v_cndmask_b32_e64 v1, 0, 1, vcc_lo
.LBB1_17:
	s_or_b32 exec_lo, exec_lo, s4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e32 vcc_lo, 0, v1
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_19
; %bb.18:
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 3, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s2, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	global_load_b32 v2, v[2:3], off offset:4
	v_mov_b32_e32 v3, v1
	s_waitcnt vmcnt(0)
	v_lshlrev_b64 v[1:2], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_store_b32 v[1:2], v0, off
.LBB1_19:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13compactVoxelsPjPK15HIP_vector_typeIjLj2EEjjjS0_IiLj3EEiS4_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z13compactVoxelsPjPK15HIP_vector_typeIjLj2EEjjjS0_IiLj3EEiS4_, .Lfunc_end1-_Z13compactVoxelsPjPK15HIP_vector_typeIjLj2EEjjjS0_IiLj3EEiS4_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 788
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	_Z28generateTriangleVerticesSMEMP15HIP_vector_typeIfLj3EEPKjPKS_IjLj2EEPKfS_IfLj4EEfjjS_IiLj3EESA_ ; -- Begin function _Z28generateTriangleVerticesSMEMP15HIP_vector_typeIfLj3EEPKjPKS_IjLj2EEPKfS_IfLj4EEfjjS_IiLj3EESA_
	.globl	_Z28generateTriangleVerticesSMEMP15HIP_vector_typeIfLj3EEPKjPKS_IjLj2EEPKfS_IfLj4EEfjjS_IiLj3EESA_
	.p2align	8
	.type	_Z28generateTriangleVerticesSMEMP15HIP_vector_typeIfLj3EEPKjPKS_IjLj2EEPKfS_IfLj4EEfjjS_IiLj3EESA_,@function
_Z28generateTriangleVerticesSMEMP15HIP_vector_typeIfLj3EEPKjPKS_IjLj2EEPKfS_IfLj4EEfjjS_IiLj3EESA_: ; @_Z28generateTriangleVerticesSMEMP15HIP_vector_typeIfLj3EEPKjPKS_IjLj2EEPKfS_IfLj4EEfjjS_IiLj3EESA_
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x64
	s_load_b128 s[20:23], s[0:1], 0x30
	v_and_b32_e32 v5, 0x3ff, v0
	v_bfe_u32 v2, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s2, 0xffff
	s_lshr_b32 s2, s2, 16
	s_mul_i32 s13, s13, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v1, s13, s14, v5
	v_mul_lo_u32 v1, v1, s2
	s_and_b32 s2, s3, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add3_u32 v3, s15, v2, v1
	v_bfe_u32 v2, v0, 20, 10
	v_mad_u64_u32 v[0:1], null, v3, s2, v[2:3]
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s21, v0
	s_cbranch_execz .LBB2_6
; %bb.1:
	s_load_b256 s[12:19], s[0:1], 0x0
	v_mov_b32_e32 v1, 0
	s_clause 0x1
	s_load_b128 s[24:27], s[0:1], 0x40
	s_load_b128 s[28:31], s[0:1], 0x20
	v_mad_u32_u24 v26, v5, 12, 0x6c00
	v_mad_u32_u24 v27, v5, 12, 0x7800
	v_lshlrev_b64 v[2:3], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s14, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s15, v3, vcc_lo
	s_mul_i32 s2, s24, s25
	s_mov_b32 s14, 0
	s_sub_i32 s3, 0, s2
	global_load_b32 v0, v[2:3], off
	v_cvt_f32_u32_e32 v2, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v2, v2
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v2, 0x4f7ffffe, v2 :: v_dual_mov_b32 v17, v1
	v_cvt_u32_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v3, s3, v2
	s_sub_i32 s3, 0, s25
	v_mul_hi_u32 v3, v2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, v2, v3
	v_cvt_f32_u32_e32 v3, s25
	v_rcp_iflag_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, 0x4f7ffffe, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v3, v3
	s_waitcnt vmcnt(0)
	v_mul_hi_u32 v2, v0, v2
	v_mul_lo_u32 v4, v2, s2
	v_add_nc_u32_e32 v6, 1, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, v0, v4
	v_subrev_nc_u32_e32 v7, s2, v4
	v_cmp_le_u32_e32 vcc_lo, s2, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v2, v2, v6, vcc_lo
	v_cndmask_b32_e32 v4, v4, v7, vcc_lo
	v_mul_lo_u32 v7, s3, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v6, 1, v2
	v_cmp_le_u32_e32 vcc_lo, s2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v6, v2, v6, vcc_lo
	v_mul_hi_u32 v2, v3, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v6, s2
	v_add_nc_u32_e32 v2, v3, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v8, v0, v4
	v_mul_hi_u32 v2, v8, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v2, s25
	v_add_nc_u32_e32 v4, 1, v2
	v_sub_nc_u32_e32 v3, v8, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v7, s25, v3
	v_cmp_le_u32_e32 vcc_lo, s25, v3
	v_dual_cndmask_b32 v2, v2, v4 :: v_dual_cndmask_b32 v3, v3, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, 1, v2
	v_cmp_le_u32_e32 vcc_lo, s25, v3
	v_mov_b32_e32 v3, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v7, v2, v4, vcc_lo
	v_add_nc_u32_e32 v15, 1, v7
	v_mul_lo_u32 v9, v6, s24
	v_cvt_f32_u32_e32 v6, v6
	v_mul_lo_u32 v11, v7, s25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v6, s31, v6, s28
	v_add_nc_u32_e32 v2, s24, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v8, v8, v11
	v_dual_add_f32 v29, 0, v6 :: v_dual_mov_b32 v4, v1
	s_delay_alu instid0(VALU_DEP_3)
	v_add_nc_u32_e32 v13, v2, v7
	v_add_nc_u32_e32 v11, v9, v7
	v_cvt_f32_u32_e32 v7, v7
	v_mov_b32_e32 v10, v1
	v_add_f32_e32 v28, s31, v6
	v_mul_lo_u32 v13, v13, s25
	v_add_nc_u32_e32 v2, v2, v15
	v_fma_f32 v7, s31, v7, s29
	v_add_nc_u32_e32 v18, v15, v9
	v_lshlrev_b64 v[15:16], 2, v[0:1]
	v_sub_f32_e32 v31, v28, v6
	v_mul_lo_u32 v24, v2, s25
	v_add_f32_e32 v37, s31, v7
	v_mul_lo_u32 v25, v18, s25
	v_add_nc_u32_e32 v2, v13, v8
	v_mov_b32_e32 v12, v1
	v_sub_f32_e32 v33, v29, v28
	v_sub_f32_e32 v35, v28, v29
	v_add_co_u32 v18, vcc_lo, s18, v15
	v_add_nc_u32_e32 v15, 1, v8
	v_add_nc_u32_e32 v9, v25, v8
	v_add_co_ci_u32_e32 v19, vcc_lo, s19, v16, vcc_lo
	v_lshlrev_b64 v[20:21], 2, v[2:3]
	v_dual_mov_b32 v14, v1 :: v_dual_add_nc_u32 v3, v24, v8
	v_mad_u64_u32 v[22:23], null, v11, s25, v[15:16]
	v_dual_sub_f32 v32, v28, v28 :: v_dual_add_nc_u32 v11, v13, v15
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v20, vcc_lo, s18, v20
	v_add_co_ci_u32_e32 v21, vcc_lo, s19, v21, vcc_lo
	v_add_nc_u32_e32 v13, v24, v15
	v_add_nc_u32_e32 v16, v25, v15
	v_lshlrev_b64 v[24:25], 2, v[9:10]
	s_clause 0x1
	global_load_b32 v9, v[18:19], off
	global_load_b32 v10, v[20:21], off
	v_lshlrev_b64 v[2:3], 2, v[3:4]
	v_mov_b32_e32 v23, v1
	v_lshlrev_b64 v[11:12], 2, v[11:12]
	v_lshlrev_b64 v[13:14], 2, v[13:14]
	v_cvt_f32_u32_e32 v8, v8
	v_add_f32_e32 v36, 0, v7
	v_add_co_u32 v2, vcc_lo, s18, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s19, v3, vcc_lo
	v_lshlrev_b64 v[22:23], 2, v[22:23]
	v_fma_f32 v8, s31, v8, s30
	v_dual_sub_f32 v41, v37, v36 :: v_dual_sub_f32 v34, v6, v29
	v_sub_f32_e32 v38, v29, v29
	v_sub_f32_e32 v39, v29, v6
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v45, s20, v10
	v_lshlrev_b64 v[15:16], 2, v[16:17]
	v_add_co_u32 v17, vcc_lo, s18, v24
	v_add_co_ci_u32_e32 v18, vcc_lo, s19, v25, vcc_lo
	v_add_co_u32 v19, vcc_lo, s18, v11
	v_add_co_ci_u32_e32 v20, vcc_lo, s19, v12, vcc_lo
	global_load_b32 v11, v[2:3], off
	v_add_co_u32 v21, vcc_lo, s18, v22
	v_add_co_ci_u32_e32 v22, vcc_lo, s19, v23, vcc_lo
	v_add_co_u32 v2, vcc_lo, s18, v13
	v_add_co_ci_u32_e32 v3, vcc_lo, s19, v14, vcc_lo
	s_clause 0x2
	global_load_b32 v12, v[17:18], off
	global_load_b32 v13, v[21:22], off
	global_load_b32 v14, v[19:20], off
	v_add_co_u32 v17, vcc_lo, s18, v15
	v_add_co_ci_u32_e32 v18, vcc_lo, s19, v16, vcc_lo
	s_clause 0x1
	global_load_b32 v15, v[2:3], off
	global_load_b32 v16, v[17:18], off
	v_cmp_gt_f32_e32 vcc_lo, s20, v10
	v_sub_f32_e32 v40, v36, v7
	v_sub_f32_e32 v42, s20, v9
	v_sub_f32_e32 v43, v10, v9
	v_sub_f32_e32 v44, v37, v37
	v_cndmask_b32_e64 v2, 0, 1, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, s20, v9
	v_mad_u32_u24 v20, v5, 12, 0x2400
	v_mad_u32_u24 v21, v5, 12, 0x3000
	v_mad_u32_u24 v22, v5, 12, 0x3c00
	v_lshlrev_b32_e32 v2, 1, v2
	v_cndmask_b32_e64 v3, 0, 1, vcc_lo
	v_mad_u32_u24 v23, v5, 12, 0x4800
	v_mad_u32_u24 v24, v5, 12, 0x5400
	v_mad_u32_u24 v25, v5, 12, 0x6000
	s_delay_alu instid0(VALU_DEP_4)
	v_or_b32_e32 v2, v2, v3
	s_waitcnt vmcnt(5)
	v_cmp_gt_f32_e32 vcc_lo, s20, v11
	v_dual_sub_f32 v49, s20, v11 :: v_dual_sub_f32 v48, v11, v10
	v_cndmask_b32_e64 v4, 0, 1, vcc_lo
	s_waitcnt vmcnt(4)
	v_cmp_gt_f32_e32 vcc_lo, s20, v12
	v_sub_f32_e32 v51, s20, v12
	v_sub_f32_e32 v52, v9, v12
	v_lshl_or_b32 v2, v4, 2, v2
	s_waitcnt vmcnt(3)
	v_dual_sub_f32 v50, v12, v11 :: v_dual_sub_f32 v9, v13, v9
	v_cndmask_b32_e64 v17, 0, 1, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, s20, v13
	s_waitcnt vmcnt(1)
	v_sub_f32_e32 v11, v15, v11
	v_div_scale_f32 v62, null, v52, v52, v51
	v_lshlrev_b32_e32 v17, 3, v17
	v_cndmask_b32_e64 v18, 0, 1, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, s20, v14
	v_sub_f32_e32 v55, s20, v14
	v_div_scale_f32 v71, null, v9, v9, v42
	s_delay_alu instid0(VALU_DEP_4)
	v_lshlrev_b32_e32 v18, 4, v18
	v_cndmask_b32_e64 v19, 0, 1, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, s20, v15
	v_rcp_f32_e32 v77, v62
	v_rcp_f32_e32 v83, v71
	v_or3_b32 v2, v2, v17, v18
	v_lshlrev_b32_e32 v19, 5, v19
	v_cndmask_b32_e64 v3, 0, 1, vcc_lo
	s_waitcnt vmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, s20, v16
	v_div_scale_f32 v46, null, v43, v43, v42
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v60, v13, v16 :: v_dual_lshlrev_b32 v3, 6, v3
	v_cndmask_b32_e64 v4, 0, 1, vcc_lo
	v_fma_f32 v88, -v62, v77, 1.0
	v_dual_sub_f32 v53, s20, v13 :: v_dual_sub_f32 v10, v14, v10
	v_or3_b32 v2, v2, v19, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v77, v88, v77 :: v_dual_lshlrev_b32 v4, 7, v4
	v_fma_f32 v88, -v71, v83, 1.0
	v_sub_f32_e32 v54, v14, v13
	v_rcp_f32_e32 v13, v46
	v_add_co_u32 v2, s2, v2, v4
	s_delay_alu instid0(VALU_DEP_3)
	v_fmac_f32_e32 v83, v88, v83
	v_add_co_ci_u32_e64 v3, null, 0, 0, s2
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, nbTriTable@rel32@lo+4
	s_addc_u32 s3, s3, nbTriTable@rel32@hi+12
	v_mul_u32_u24_e32 v4, 12, v5
	v_sub_f32_e32 v59, s20, v16
	v_lshlrev_b64 v[17:18], 2, v[2:3]
	v_fma_f32 v82, -v46, v13, 1.0
	v_sub_f32_e32 v56, v15, v14
	v_add_nc_u32_e32 v30, 8, v4
	v_div_scale_f32 v14, null, v48, v48, v45
	v_add_co_u32 v17, vcc_lo, v17, s2
	v_add_co_ci_u32_e32 v18, vcc_lo, s3, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_rcp_f32_e32 v75, v14
	v_fmac_f32_e32 v13, v82, v13
	v_div_scale_f32 v66, null, v56, v56, v55
	global_load_b32 v17, v[17:18], off
	v_div_scale_f32 v73, null, v11, v11, v49
	v_rcp_f32_e32 v79, v66
	v_div_scale_f32 v64, null, v54, v54, v53
	v_fma_f32 v82, -v14, v75, 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_rcp_f32_e32 v85, v73
	v_sub_f32_e32 v57, s20, v15
	v_div_scale_f32 v72, null, v10, v10, v45
	v_fmac_f32_e32 v75, v82, v75
	v_div_scale_f32 v70, null, v60, v60, v59
	s_delay_alu instid0(TRANS32_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f32 v90, -v66, v79, 1.0
	v_sub_f32_e32 v12, v16, v12
	v_rcp_f32_e32 v78, v64
	v_rcp_f32_e32 v81, v70
	v_sub_f32_e32 v58, v16, v15
	v_div_scale_f32 v16, null, v50, v50, v49
	v_fmac_f32_e32 v79, v90, v79
	v_fma_f32 v90, -v73, v85, 1.0
	v_div_scale_f32 v74, null, v12, v12, v51
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v76, v16
	v_rcp_f32_e32 v84, v72
	v_fma_f32 v89, -v64, v78, 1.0
	v_rcp_f32_e32 v86, v74
	v_div_scale_f32 v15, s2, v45, v48, v45
	v_div_scale_f32 v47, vcc_lo, v42, v43, v42
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(TRANS32_DEP_3)
	v_fmac_f32_e32 v78, v89, v78
	v_div_scale_f32 v67, s6, v55, v56, v55
	v_fma_f32 v87, -v16, v76, 1.0
	s_delay_alu instid0(TRANS32_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v89, -v72, v84, 1.0
	v_div_scale_f32 v61, s3, v49, v50, v49
	v_dual_fmac_f32 v85, v90, v85 :: v_dual_fmac_f32 v76, v87, v76
	v_fma_f32 v87, -v70, v81, 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v84, v89, v84 :: v_dual_mul_f32 v89, v15, v75
	v_div_scale_f32 v65, s5, v53, v54, v53
	v_fmac_f32_e32 v81, v87, v81
	v_div_scale_f32 v68, null, v58, v58, v57
	v_fma_f32 v87, -v74, v86, 1.0
	v_div_scale_f32 v63, s4, v51, v52, v51
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_rcp_f32_e32 v80, v68
	v_div_scale_f32 v69, s7, v57, v58, v57
	v_fmac_f32_e32 v86, v87, v86
	v_fma_f32 v87, -v14, v89, v15
	v_div_scale_f32 v90, s8, v59, v60, v59
	v_mad_u32_u24 v18, v5, 12, 0xc00
	v_mad_u32_u24 v19, v5, 12, 0x1800
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(TRANS32_DEP_1)
	v_fmac_f32_e32 v89, v87, v75
	v_fma_f32 v82, -v68, v80, 1.0
	v_mul_f32_e32 v87, v61, v76
	v_mad_u32_u24 v5, v5, 12, 0x8400
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v14, -v14, v89, v15
	v_fmac_f32_e32 v80, v82, v80
	v_dual_mul_f32 v82, v47, v13 :: v_dual_mul_f32 v15, v65, v78
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v88, -v46, v82, v47
	v_fmac_f32_e32 v82, v88, v13
	v_div_scale_f32 v88, s9, v42, v9, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v46, -v46, v82, v47
	v_div_scale_f32 v47, s10, v45, v10, v45
	v_div_fmas_f32 v13, v46, v13, v82
	v_fma_f32 v82, -v16, v87, v61
	s_mov_b32 vcc_lo, s2
	v_div_fmas_f32 v14, v14, v75, v89
	s_mov_b32 vcc_lo, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v87, v82, v76
	v_fma_f32 v82, -v64, v15, v65
	v_mul_f32_e32 v46, v63, v77
	v_div_scale_f32 v89, s2, v49, v11, v49
	v_fma_f32 v16, -v16, v87, v61
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v15, v82, v78
	v_fma_f32 v75, -v62, v46, v63
	v_mul_f32_e32 v61, v67, v79
	v_div_fixup_f32 v13, v13, v43, v42
	v_div_fmas_f32 v16, v16, v76, v87
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v87, v88, v83 :: v_dual_fmac_f32 v46, v75, v77
	s_mov_b32 vcc_lo, s4
	v_div_scale_f32 v75, s11, v51, v12, v51
	v_mul_f32_e32 v76, v90, v81
	v_fma_f32 v62, -v62, v46, v63
	v_mul_f32_e32 v63, v47, v84
	v_fma_f32 v64, -v64, v15, v65
	v_mul_f32_e32 v65, v89, v85
	v_div_fixup_f32 v14, v14, v48, v45
	v_div_fmas_f32 v46, v62, v77, v46
	v_fma_f32 v62, -v66, v61, v67
	v_mul_f32_e32 v82, v69, v80
	s_mov_b32 vcc_lo, s5
	v_div_fixup_f32 v16, v16, v50, v49
	v_div_fmas_f32 v15, v64, v78, v15
	v_fmac_f32_e32 v61, v62, v79
	v_fma_f32 v77, -v68, v82, v69
	v_mul_f32_e32 v64, v75, v86
	v_fma_f32 v78, -v70, v76, v90
	v_fma_f32 v62, -v71, v87, v88
	v_fma_f32 v66, -v66, v61, v67
	v_fmac_f32_e32 v82, v77, v80
	v_fma_f32 v77, -v72, v63, v47
	v_fmac_f32_e32 v76, v78, v81
	v_fma_f32 v78, -v73, v65, v89
	v_fmac_f32_e32 v87, v62, v83
	v_fma_f32 v62, -v74, v64, v75
	v_fmac_f32_e32 v63, v77, v84
	v_fma_f32 v68, -v68, v82, v69
	v_fmac_f32_e32 v65, v78, v85
	s_mov_b32 vcc_lo, s6
	v_dual_fmac_f32 v64, v62, v86 :: v_dual_sub_f32 v67, v36, v37
	v_add_f32_e32 v62, 0, v8
	v_fma_f32 v70, -v70, v76, v90
	v_add_f32_e32 v69, s31, v8
	v_fma_f32 v71, -v71, v87, v88
	v_div_fmas_f32 v48, v66, v79, v61
	v_sub_f32_e32 v88, v62, v62
	s_delay_alu instid0(VALU_DEP_4)
	v_dual_sub_f32 v90, v62, v8 :: v_dual_sub_f32 v43, v69, v69
	s_mov_b32 vcc_lo, s7
	v_fma_f32 v47, -v72, v63, v47
	v_div_fmas_f32 v61, v68, v80, v82
	s_mov_b32 vcc_lo, s8
	v_dual_sub_f32 v77, v7, v37 :: v_dual_sub_f32 v78, v36, v36
	v_div_fmas_f32 v66, v70, v81, v76
	s_mov_b32 vcc_lo, s9
	v_sub_f32_e32 v72, v8, v62
	v_fma_f32 v73, -v73, v65, v89
	v_sub_f32_e32 v89, v69, v8
	v_fma_f32 v90, v13, v90, v8
	v_div_fixup_f32 v46, v46, v52, v51
	v_fma_f32 v50, v32, v14, v28
	v_fma_f32 v52, v41, v14, v36
	v_fma_f32 v14, v14, v88, v62
	v_div_fixup_f32 v48, v48, v56, v55
	v_div_fmas_f32 v56, v71, v83, v87
	s_mov_b32 vcc_lo, s10
	v_fma_f32 v74, -v74, v64, v75
	v_div_fixup_f32 v15, v15, v54, v53
	v_div_fmas_f32 v47, v47, v84, v63
	s_mov_b32 vcc_lo, s2
	v_fma_f32 v53, v33, v16, v28
	v_fma_f32 v54, v44, v16, v37
	v_fma_f32 v16, v16, v88, v62
	v_fma_f32 v34, v34, v46, v29
	v_fma_f32 v55, v77, v46, v37
	v_fma_f32 v46, v46, v72, v62
	ds_store_2addr_stride64_b32 v30, v90, v14 offset1:12
	v_div_fixup_f32 v14, v61, v58, v57
	v_div_fixup_f32 v58, v66, v60, v59
	v_div_fmas_f32 v60, v73, v85, v65
	s_mov_b32 vcc_lo, s11
	v_div_fixup_f32 v9, v56, v9, v42
	v_div_fmas_f32 v42, v74, v86, v64
	v_fma_f32 v35, v35, v15, v29
	v_fma_f32 v57, v78, v15, v36
	v_sub_f32_e32 v75, v69, v62
	v_div_fixup_f32 v10, v47, v10, v45
	v_fma_f32 v31, v31, v13, v6
	v_fmac_f32_e32 v6, v39, v9
	v_fma_f32 v13, v13, v40, v7
	v_fma_f32 v15, v43, v15, v69
	v_fma_f32 v59, v32, v48, v28
	v_fma_f32 v41, v41, v48, v36
	v_fma_f32 v48, v43, v48, v69
	ds_store_2addr_stride64_b32 v30, v16, v46 offset0:24 offset1:36
	v_fma_f32 v16, v33, v14, v28
	v_fma_f32 v33, v44, v14, v37
	v_fma_f32 v14, v43, v14, v69
	ds_store_2addr_b32 v18, v50, v52 offset1:1
	ds_store_2addr_b32 v19, v53, v54 offset1:1
	ds_store_2addr_b32 v20, v34, v55 offset1:1
	ds_store_2addr_b32 v21, v35, v57 offset1:1
	v_fma_f32 v20, v43, v58, v69
	v_div_fixup_f32 v11, v60, v11, v49
	v_dual_fmac_f32 v7, v40, v9 :: v_dual_fmac_f32 v36, v78, v10
	v_fmac_f32_e32 v8, v89, v9
	v_div_fixup_f32 v9, v42, v12, v51
	v_fma_f32 v12, v32, v10, v28
	v_fma_f32 v10, v75, v10, v62
	ds_store_2addr_stride64_b32 v30, v14, v20 offset0:72 offset1:84
	v_fmac_f32_e32 v28, v32, v11
	v_fma_f32 v14, v44, v11, v37
	v_fma_f32 v18, v38, v58, v29
	v_fmac_f32_e32 v29, v38, v9
	v_fma_f32 v19, v67, v58, v37
	v_fmac_f32_e32 v37, v44, v9
	v_fma_f32 v11, v75, v11, v62
	v_fmac_f32_e32 v62, v75, v9
	ds_store_2addr_stride64_b32 v30, v15, v48 offset0:48 offset1:60
	ds_store_2addr_b32 v22, v59, v41 offset1:1
	ds_store_2addr_b32 v23, v16, v33 offset1:1
	ds_store_2addr_b32 v24, v18, v19 offset1:1
	ds_store_2addr_b32 v25, v6, v7 offset1:1
	ds_store_2addr_stride64_b32 v30, v8, v10 offset0:96 offset1:108
	ds_store_2addr_b32 v26, v12, v36 offset1:1
	ds_store_2addr_b32 v27, v28, v14 offset1:1
	ds_store_2addr_b32 v4, v31, v13 offset1:1
	ds_store_2addr_b32 v5, v29, v37 offset1:1
	ds_store_2addr_stride64_b32 v30, v11, v62 offset0:120 offset1:132
	s_waitcnt vmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, 0, v17
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB2_6
; %bb.2:                                ; %.lr.ph
	s_load_b32 s2, s[0:1], 0x50
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_lshlrev_b64 v[2:3], 6, v[2:3]
	v_cvt_f32_i32_e32 v5, s26
	v_cvt_f32_i32_e32 v6, s27
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, triTable@rel32@lo+12
	s_addc_u32 s1, s1, triTable@rel32@hi+20
	v_add_co_u32 v0, vcc_lo, s16, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s17, v1, vcc_lo
	v_add_co_u32 v2, vcc_lo, v2, s0
	v_dual_mul_f32 v5, s31, v5 :: v_dual_mul_f32 v6, s31, v6
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	s_mov_b32 s1, 0
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_i32_e32 v7, s2
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v7, s31, v7
.LBB2_3:                                ; =>This Inner Loop Header: Depth=1
	global_load_b32 v8, v[0:1], off
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v8, s1, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s22, v8
	s_cbranch_execz .LBB2_5
; %bb.4:                                ;   in Loop: Header=BB2_3 Depth=1
	global_load_b96 v[9:11], v[2:3], off offset:-8
	v_mad_u64_u32 v[18:19], null, v8, 12, s[12:13]
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[12:13], null, 0xc00, v9, v[4:5]
	v_mad_u64_u32 v[13:14], null, 0xc00, v10, v[4:5]
	v_mad_u64_u32 v[9:10], null, 0xc00, v11, v[4:5]
	ds_load_2addr_b32 v[10:11], v12 offset1:1
	ds_load_b32 v16, v12 offset:8
	ds_load_2addr_b32 v[14:15], v13 offset1:1
	ds_load_b32 v22, v13 offset:8
	ds_load_2addr_b32 v[12:13], v9 offset1:1
	ds_load_b32 v23, v9 offset:8
	s_waitcnt lgkmcnt(5)
	v_dual_add_f32 v8, v5, v10 :: v_dual_add_nc_u32 v9, 2, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[20:21], null, v9, 12, s[12:13]
	s_waitcnt lgkmcnt(4)
	v_dual_add_f32 v9, v6, v11 :: v_dual_add_f32 v10, v7, v16
	s_waitcnt lgkmcnt(0)
	v_dual_add_f32 v11, v5, v14 :: v_dual_add_f32 v14, v7, v23
	v_dual_add_f32 v15, v6, v15 :: v_dual_add_f32 v16, v7, v22
	v_dual_add_f32 v12, v5, v12 :: v_dual_add_f32 v13, v6, v13
	s_clause 0x2
	global_store_b128 v[18:19], v[8:11], off
	global_store_b64 v[18:19], v[15:16], off offset:16
	global_store_b96 v[20:21], v[12:14], off
.LBB2_5:                                ;   in Loop: Header=BB2_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_add_i32 s1, s1, 3
	v_add_co_u32 v2, s0, v2, 12
	v_cmp_ge_u32_e32 vcc_lo, s1, v17
	v_add_co_ci_u32_e64 v3, s0, 0, v3, s0
	s_or_b32 s14, vcc_lo, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s14
	s_cbranch_execnz .LBB2_3
.LBB2_6:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z28generateTriangleVerticesSMEMP15HIP_vector_typeIfLj3EEPKjPKS_IjLj2EEPKfS_IfLj4EEfjjS_IiLj3EESA_
		.amdhsa_group_segment_fixed_size 36864
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 344
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 91
		.amdhsa_next_free_sgpr 32
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z28generateTriangleVerticesSMEMP15HIP_vector_typeIfLj3EEPKjPKS_IjLj2EEPKfS_IfLj4EEfjjS_IiLj3EESA_, .Lfunc_end2-_Z28generateTriangleVerticesSMEMP15HIP_vector_typeIfLj3EEPKjPKS_IjLj2EEPKfS_IfLj4EEfjjS_IiLj3EESA_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3256
; NumSgprs: 34
; NumVgprs: 91
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 36864 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 11
; NumSGPRsForWavesPerEU: 34
; NumVGPRsForWavesPerEU: 91
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	_Z13groupVerticesP15HIP_vector_typeIfLj3EEjf ; -- Begin function _Z13groupVerticesP15HIP_vector_typeIfLj3EEjf
	.globl	_Z13groupVerticesP15HIP_vector_typeIfLj3EEjf
	.p2align	8
	.type	_Z13groupVerticesP15HIP_vector_typeIfLj3EEjf,@function
_Z13groupVerticesP15HIP_vector_typeIfLj3EEjf: ; @_Z13groupVerticesP15HIP_vector_typeIfLj3EEjf
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x1c
	s_load_b64 s[2:3], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_cmp_gt_u32_e32 vcc_lo, s2, v1
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB3_2
; %bb.1:
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[3:4], null, v1, 12, s[0:1]
	global_load_b96 v[0:2], v[3:4], off
	s_waitcnt vmcnt(0)
	v_div_scale_f32 v5, null, s3, s3, v0
	v_div_scale_f32 v6, null, s3, s3, v1
	v_div_scale_f32 v7, null, s3, s3, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v8, v5
	v_rcp_f32_e32 v9, v6
	v_div_scale_f32 v11, vcc_lo, v0, s3, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(TRANS32_DEP_3)
	v_rcp_f32_e32 v10, v7
	v_div_scale_f32 v12, s0, v1, s3, v1
	v_div_scale_f32 v16, s1, v2, s3, v2
	v_fma_f32 v13, -v5, v8, 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v14, -v6, v9, 1.0
	v_fma_f32 v15, -v7, v10, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v8, v13, v8 :: v_dual_fmac_f32 v9, v14, v9
	v_dual_mul_f32 v13, v11, v8 :: v_dual_mul_f32 v14, v12, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v17, -v5, v13, v11
	v_fmac_f32_e32 v10, v15, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v18, -v6, v14, v12
	v_fmac_f32_e32 v13, v17, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v15, v16, v10 :: v_dual_fmac_f32 v14, v18, v9
	v_fma_f32 v5, -v5, v13, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v19, -v7, v15, v16
	v_fma_f32 v6, -v6, v14, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v5, v5, v8, v13
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f32 v6, v6, v9, v14
	s_mov_b32 vcc_lo, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v0, v5, s3, v0
	v_div_fixup_f32 v1, v6, s3, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_trunc_f32_e32 v5, v0
	v_fmac_f32_e32 v15, v19, v10
	v_trunc_f32_e32 v6, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v8, v0, v5
	v_fma_f32 v7, -v7, v15, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ge_f32_e64 s0, |v8|, 0.5
	v_div_fmas_f32 v7, v7, v10, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v8, 0, 1.0, s0
	v_div_fixup_f32 v2, v7, s3, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_bfi_b32 v0, 0x7fffffff, v8, v0
	v_trunc_f32_e32 v7, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v9, v1, v6 :: v_dual_sub_f32 v10, v2, v7
	v_cmp_ge_f32_e64 s0, |v9|, 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v9, 0, 1.0, s0
	v_cmp_ge_f32_e64 s0, |v10|, 0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_bfi_b32 v1, 0x7fffffff, v9, v1
	v_cndmask_b32_e64 v10, 0, 1.0, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v0, v5, v0 :: v_dual_add_f32 v1, v6, v1
	v_bfi_b32 v2, 0x7fffffff, v10, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v0, s3, v0 :: v_dual_mul_f32 v1, s3, v1
	v_add_f32_e32 v2, v7, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v2, s3, v2
	global_store_b96 v[3:4], v[0:2], off
.LBB3_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13groupVerticesP15HIP_vector_typeIfLj3EEjf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 20
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z13groupVerticesP15HIP_vector_typeIfLj3EEjf, .Lfunc_end3-_Z13groupVerticesP15HIP_vector_typeIfLj3EEjf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 548
; NumSgprs: 18
; NumVgprs: 20
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 20
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z15LaplacianSmoothP15HIP_vector_typeIfLj3EEPijjj ; -- Begin function _Z15LaplacianSmoothP15HIP_vector_typeIfLj3EEPijjj
	.globl	_Z15LaplacianSmoothP15HIP_vector_typeIfLj3EEPijjj
	.p2align	8
	.type	_Z15LaplacianSmoothP15HIP_vector_typeIfLj3EEPijjj,@function
_Z15LaplacianSmoothP15HIP_vector_typeIfLj3EEPijjj: ; @_Z15LaplacianSmoothP15HIP_vector_typeIfLj3EEPijjj
; %bb.0:
	s_clause 0x1
	s_load_b32 s8, s[2:3], 0x2c
	s_load_b128 s[4:7], s[2:3], 0x10
	v_and_b32_e32 v1, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s7, s8, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[9:10], null, s15, s7, v[1:2]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_u32_e32 vcc_lo, s4, v9
	s_and_saveexec_b32 s4, vcc_lo
	s_cbranch_execz .LBB4_28
; %bb.1:
	v_mov_b32_e32 v2, -1
	s_mov_b32 s4, 0
.LBB4_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s7, s4, 32
	s_add_i32 s4, s4, 4
	scratch_store_b32 off, v2, s7
	s_cmpk_eq_i32 s4, 0x80
	s_cbranch_scc0 .LBB4_2
; %bb.3:                                ; %.preheader166
	s_load_b128 s[8:11], s[2:3], 0x0
	v_mov_b32_e32 v12, 1
	s_cmp_eq_u32 s5, 0
	s_mov_b32 s4, 0
	s_cbranch_scc1 .LBB4_11
; %bb.4:                                ; %.lr.ph.preheader
	s_waitcnt lgkmcnt(0)
	s_add_u32 s2, s10, 4
	s_addc_u32 s3, s11, 0
	s_mov_b32 s7, 1
                                        ; implicit-def: $sgpr12
.LBB4_5:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_add_u32 s14, s2, -4
	s_addc_u32 s15, s3, -1
	s_or_b32 s12, s12, exec_lo
	s_load_b32 s13, s[14:15], 0x0
	s_waitcnt lgkmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, s13, v9
	s_and_saveexec_b32 s13, vcc_lo
	s_cbranch_execz .LBB4_9
; %bb.6:                                ;   in Loop: Header=BB4_5 Depth=1
	s_load_b32 s14, s[2:3], 0x0
	s_waitcnt lgkmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, s14, v9
	s_mov_b32 s14, -1
	s_and_saveexec_b32 s15, vcc_lo
	s_cbranch_execz .LBB4_8
; %bb.7:                                ;   in Loop: Header=BB4_5 Depth=1
	s_load_b32 s14, s[2:3], 0x4
	s_waitcnt lgkmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, s14, v9
	s_or_not1_b32 s14, vcc_lo, exec_lo
.LBB4_8:                                ; %Flow272
                                        ;   in Loop: Header=BB4_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s12, s12, exec_lo
	s_and_b32 s14, s14, exec_lo
	s_or_b32 s12, s12, s14
.LBB4_9:                                ;   in Loop: Header=BB4_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	v_cndmask_b32_e64 v2, 0, 1, s12
	v_cndmask_b32_e64 v3, 0, v12, s12
	s_add_i32 s13, s7, -1
	s_cmp_ge_u32 s7, s5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v12, v12, v2
	v_mov_b32_e32 v2, s13
	s_cselect_b32 s13, -1, 0
	s_add_i32 s7, s7, 1
	v_lshl_add_u32 v3, v3, 2, 32
	v_cmp_lt_u32_e32 vcc_lo, 31, v12
	scratch_store_b32 v3, v2, off
	s_or_b32 s13, s13, vcc_lo
	s_add_u32 s2, s2, 12
	s_addc_u32 s3, s3, 0
	s_and_b32 s13, exec_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s4, s13, s4
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB4_5
; %bb.10:                               ; %Flow273
	s_or_b32 exec_lo, exec_lo, s4
.LBB4_11:                               ; %.preheader165
	s_cmp_eq_u32 s6, 0
	s_mov_b32 s2, 0
	s_cbranch_scc1 .LBB4_28
; %bb.12:                               ; %.preheader.lr.ph
	s_load_b64 s[0:1], s[0:1], 0x4
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[10:11], null, v9, 12, s[8:9]
	s_lshr_b32 s0, s0, 16
	v_mul_u32_u24_e32 v2, s1, v2
	s_mul_i32 s0, s0, s1
	v_cmp_ne_u32_e64 s1, 1, v12
	v_mul_lo_u32 v1, s0, v1
	v_cmp_lt_u32_e64 s0, 1, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, v1, v2, v0
	v_mul_lo_u32 v13, v0, 12
	v_lshl_add_u32 v0, v12, 1, -2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f32_i32_e32 v18, v0
	v_add_nc_u32_e32 v14, 0xc000, v13
	v_add_nc_u32_e32 v15, 0x9000, v13
	v_add_nc_u32_e32 v16, 0x6000, v13
	v_add_nc_u32_e32 v17, 0x3000, v13
.LBB4_13:                               ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB4_15 Depth 2
                                        ;       Child Loop BB4_16 Depth 3
                                        ;       Child Loop BB4_18 Depth 3
                                        ;       Child Loop BB4_20 Depth 3
                                        ;     Child Loop BB4_25 Depth 2
	v_dual_mov_b32 v19, 0 :: v_dual_mov_b32 v20, 0
	v_mov_b32_e32 v21, 0
	s_and_saveexec_b32 s3, s0
	s_cbranch_execz .LBB4_23
; %bb.14:                               ; %.lr.ph174.preheader
                                        ;   in Loop: Header=BB4_13 Depth=1
	v_dual_mov_b32 v19, 0 :: v_dual_mov_b32 v20, 0
	v_mov_b32_e32 v21, 0
	s_mov_b32 s4, 0
	s_mov_b32 s5, 1
.LBB4_15:                               ; %.lr.ph174
                                        ;   Parent Loop BB4_13 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB4_16 Depth 3
                                        ;       Child Loop BB4_18 Depth 3
                                        ;       Child Loop BB4_20 Depth 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s7, s5, 2
	s_add_i32 s7, s7, 32
	scratch_load_b32 v0, off, s7
	s_mov_b32 s7, 0
	s_waitcnt vmcnt(0)
	v_lshl_add_u32 v0, v0, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
	global_load_b96 v[0:2], v[0:1], off
	s_waitcnt vmcnt(0)
	v_mad_i64_i32 v[3:4], null, v0, 12, s[8:9]
	v_cmp_ne_u32_e32 vcc_lo, v0, v9
	v_cndmask_b32_e64 v6, 0, 1.0, vcc_lo
	global_load_b96 v[3:5], v[3:4], off
	v_mov_b32_e32 v7, v6
	v_mov_b32_e32 v8, v6
	scratch_store_b96 off, v[6:8], off offset:4
	s_waitcnt vmcnt(0)
	s_clause 0x1
	scratch_store_b32 off, v5, off offset:24
	scratch_store_b64 off, v[3:4], off offset:16
.LBB4_16:                               ;   Parent Loop BB4_13 Depth=1
                                        ;     Parent Loop BB4_15 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_add_i32 s12, s7, 4
	s_add_i32 s13, s7, 16
	scratch_load_b32 v0, off, s12
	scratch_load_b32 v3, off, s13
	s_add_i32 s7, s7, 4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s7, 12
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v0, v0, v3
	scratch_store_b32 off, v0, s13
	s_cbranch_scc1 .LBB4_16
; %bb.17:                               ; %_ZmlIfLj3EbE15HIP_vector_typeIT_XT0_EERKS2_T1_.exit
                                        ;   in Loop: Header=BB4_15 Depth=2
	v_mad_i64_i32 v[3:4], null, v1, 12, s[8:9]
	v_cmp_ne_u32_e32 vcc_lo, v1, v9
	s_mov_b32 s7, 0
	global_load_b96 v[6:8], v[3:4], off
	scratch_load_b96 v[3:5], off, off offset:16
	v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo
	ds_store_2addr_b32 v13, v0, v0 offset1:1
	ds_store_b32 v13, v0 offset:8
	s_waitcnt vmcnt(1)
	s_clause 0x1
	scratch_store_b32 off, v8, off offset:12
	scratch_store_b64 off, v[6:7], off offset:4
.LBB4_18:                               ;   Parent Loop BB4_13 Depth=1
                                        ;     Parent Loop BB4_15 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_add_i32 s12, s7, 4
	v_add_nc_u32_e32 v1, s7, v13
	scratch_load_b32 v0, off, s12
	s_add_i32 s7, s7, 4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s7, 12
	ds_load_b32 v1, v1
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_mul_f32_e32 v0, v1, v0
	scratch_store_b32 off, v0, s12
	s_cbranch_scc1 .LBB4_18
; %bb.19:                               ; %_ZmlIfLj3EbE15HIP_vector_typeIT_XT0_EERKS2_T1_.exit119
                                        ;   in Loop: Header=BB4_15 Depth=2
	v_mad_i64_i32 v[0:1], null, v2, 12, s[8:9]
	v_cmp_ne_u32_e32 vcc_lo, v2, v9
	s_mov_b32 s7, 0
	global_load_b96 v[22:24], v[0:1], off
	scratch_load_b96 v[6:8], off, off offset:4
	v_cndmask_b32_e64 v0, 0, 1.0, vcc_lo
	ds_store_2addr_b32 v16, v0, v0 offset1:1
	ds_store_b32 v16, v0 offset:8
	s_waitcnt vmcnt(1)
	ds_store_2addr_b32 v17, v22, v23 offset1:1
	ds_store_b32 v17, v24 offset:8
.LBB4_20:                               ;   Parent Loop BB4_13 Depth=1
                                        ;     Parent Loop BB4_15 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_add_nc_u32_e32 v0, s7, v16
	v_add_nc_u32_e32 v1, s7, v17
	s_add_i32 s7, s7, 4
	ds_load_b32 v0, v0
	ds_load_b32 v2, v1
	s_cmp_lg_u32 s7, 12
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v0, v0, v2
	ds_store_b32 v1, v0
	s_cbranch_scc1 .LBB4_20
; %bb.21:                               ; %_ZmlIfLj3EbE15HIP_vector_typeIT_XT0_EERKS2_T1_.exit133
                                        ;   in Loop: Header=BB4_15 Depth=2
	ds_load_2addr_b32 v[0:1], v17 offset1:1
	ds_load_b32 v2, v17 offset:8
	v_dual_add_f32 v3, v21, v3 :: v_dual_add_f32 v4, v20, v4
	v_add_f32_e32 v5, v19, v5
	s_add_i32 s5, s5, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	v_cmp_eq_u32_e32 vcc_lo, s5, v12
	s_waitcnt vmcnt(0)
	v_dual_add_f32 v4, v4, v7 :: v_dual_add_f32 v3, v3, v6
	v_add_f32_e32 v5, v5, v8
	s_or_b32 s4, vcc_lo, s4
	s_waitcnt lgkmcnt(1)
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_add_f32 v20, v4, v1 :: v_dual_add_f32 v21, v3, v0
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v19, v5, v2
	s_and_not1_b32 exec_lo, exec_lo, s4
	s_cbranch_execnz .LBB4_15
; %bb.22:                               ; %Flow268
                                        ;   in Loop: Header=BB4_13 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
.LBB4_23:                               ; %Flow269
                                        ;   in Loop: Header=BB4_13 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	s_and_saveexec_b32 s3, s1
	s_cbranch_execz .LBB4_27
; %bb.24:                               ;   in Loop: Header=BB4_13 Depth=1
	s_mov_b32 s4, 0
	ds_store_2addr_b32 v14, v18, v18 offset1:1
	ds_store_b32 v14, v18 offset:8
	ds_store_2addr_b32 v15, v21, v20 offset1:1
	ds_store_b32 v15, v19 offset:8
.LBB4_25:                               ;   Parent Loop BB4_13 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_add_nc_u32_e32 v0, s4, v14
	v_add_nc_u32_e32 v1, s4, v15
	s_add_i32 s4, s4, 4
	ds_load_b32 v0, v0
	ds_load_b32 v2, v1
	s_cmp_lg_u32 s4, 12
	s_waitcnt lgkmcnt(0)
	v_div_scale_f32 v3, null, v0, v0, v2
	v_div_scale_f32 v6, vcc_lo, v2, v0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v4, v3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v5, -v3, v4, 1.0
	v_fmac_f32_e32 v4, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v6, v4
	v_fma_f32 v7, -v3, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, v7, v4
	v_fma_f32 v3, -v3, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v3, v3, v4, v5
	v_div_fixup_f32 v0, v3, v0, v2
	ds_store_b32 v1, v0
	s_cbranch_scc1 .LBB4_25
; %bb.26:                               ; %_ZdvIfLj3EiE15HIP_vector_typeIT_XT0_EERKS2_T1_.exit
                                        ;   in Loop: Header=BB4_13 Depth=1
	ds_load_2addr_b32 v[0:1], v15 offset1:1
	ds_load_b32 v2, v15 offset:8
	s_waitcnt lgkmcnt(0)
	global_store_b96 v[10:11], v[0:2], off
.LBB4_27:                               ; %Flow
                                        ;   in Loop: Header=BB4_13 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_add_i32 s2, s2, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s2, s6
	s_cbranch_scc0 .LBB4_13
.LBB4_28:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15LaplacianSmoothP15HIP_vector_typeIfLj3EEPijjj
		.amdhsa_group_segment_fixed_size 61440
		.amdhsa_private_segment_fixed_size 160
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 1
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 25
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z15LaplacianSmoothP15HIP_vector_typeIfLj3EEPijjj, .Lfunc_end4-_Z15LaplacianSmoothP15HIP_vector_typeIfLj3EEPijjj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1352
; NumSgprs: 18
; NumVgprs: 25
; ScratchSize: 160
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 61440 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 25
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	_Z15memsetCudaFloatPffi ; -- Begin function _Z15memsetCudaFloatPffi
	.globl	_Z15memsetCudaFloatPffi
	.p2align	8
	.type	_Z15memsetCudaFloatPffi,@function
_Z15memsetCudaFloatPffi:                ; @_Z15memsetCudaFloatPffi
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x1c
	s_load_b64 s[2:3], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_cmp_gt_u32_e32 vcc_lo, s3, v1
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB5_2
; %bb.1:
	s_load_b64 s[0:1], s[0:1], 0x0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_mov_b32_e32 v2, s2
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB5_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15memsetCudaFloatPffi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 3
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	_Z15memsetCudaFloatPffi, .Lfunc_end5-_Z15memsetCudaFloatPffi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 124
; NumSgprs: 18
; NumVgprs: 3
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 3
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z13memsetCudaIntPiii   ; -- Begin function _Z13memsetCudaIntPiii
	.globl	_Z13memsetCudaIntPiii
	.p2align	8
	.type	_Z13memsetCudaIntPiii,@function
_Z13memsetCudaIntPiii:                  ; @_Z13memsetCudaIntPiii
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x1c
	s_load_b64 s[2:3], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_cmp_gt_u32_e32 vcc_lo, s3, v1
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB6_2
; %bb.1:
	s_load_b64 s[0:1], s[0:1], 0x0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_mov_b32_e32 v2, s2
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB6_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13memsetCudaIntPiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 3
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end6:
	.size	_Z13memsetCudaIntPiii, .Lfunc_end6-_Z13memsetCudaIntPiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 124
; NumSgprs: 18
; NumVgprs: 3
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 3
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z14memsetCudaInt2P15HIP_vector_typeIiLj2EES0_i ; -- Begin function _Z14memsetCudaInt2P15HIP_vector_typeIiLj2EES0_i
	.globl	_Z14memsetCudaInt2P15HIP_vector_typeIiLj2EES0_i
	.p2align	8
	.type	_Z14memsetCudaInt2P15HIP_vector_typeIiLj2EES0_i,@function
_Z14memsetCudaInt2P15HIP_vector_typeIiLj2EES0_i: ; @_Z14memsetCudaInt2P15HIP_vector_typeIiLj2EES0_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b32 s3, s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_u32_e64 s3, v1
	s_cbranch_execz .LBB7_2
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b64 v[0:1], v[2:3], off
.LBB7_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14memsetCudaInt2P15HIP_vector_typeIiLj2EES0_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end7:
	.size	_Z14memsetCudaInt2P15HIP_vector_typeIiLj2EES0_i, .Lfunc_end7-_Z14memsetCudaInt2P15HIP_vector_typeIiLj2EES0_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 132
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z15memsetCudaUInt2P15HIP_vector_typeIjLj2EES0_i ; -- Begin function _Z15memsetCudaUInt2P15HIP_vector_typeIjLj2EES0_i
	.globl	_Z15memsetCudaUInt2P15HIP_vector_typeIjLj2EES0_i
	.p2align	8
	.type	_Z15memsetCudaUInt2P15HIP_vector_typeIjLj2EES0_i,@function
_Z15memsetCudaUInt2P15HIP_vector_typeIjLj2EES0_i: ; @_Z15memsetCudaUInt2P15HIP_vector_typeIjLj2EES0_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b32 s3, s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_u32_e64 s3, v1
	s_cbranch_execz .LBB8_2
; %bb.1:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b64 v[0:1], v[2:3], off
.LBB8_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15memsetCudaUInt2P15HIP_vector_typeIjLj2EES0_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end8:
	.size	_Z15memsetCudaUInt2P15HIP_vector_typeIjLj2EES0_i, .Lfunc_end8-_Z15memsetCudaUInt2P15HIP_vector_typeIjLj2EES0_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 132
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z9hashAtomsjP15HIP_vector_typeIfLj4EES_IiLj3EES0_PS_IiLj2EEj ; -- Begin function _Z9hashAtomsjP15HIP_vector_typeIfLj4EES_IiLj3EES0_PS_IiLj2EEj
	.globl	_Z9hashAtomsjP15HIP_vector_typeIfLj4EES_IiLj3EES0_PS_IiLj2EEj
	.p2align	8
	.type	_Z9hashAtomsjP15HIP_vector_typeIfLj4EES_IiLj3EES0_PS_IiLj2EEj,@function
_Z9hashAtomsjP15HIP_vector_typeIfLj4EES_IiLj3EES0_PS_IiLj2EEj: ; @_Z9hashAtomsjP15HIP_vector_typeIfLj4EES_IiLj3EES0_PS_IiLj2EEj
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x4c
	s_load_b32 s3, s[0:1], 0x38
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_u32_e64 s3, v1
	s_cbranch_execz .LBB9_4
; %bb.1:
	s_load_b32 s2, s[0:1], 0x0
	v_mov_b32_e32 v2, 0
	v_bfrev_b32_e32 v3, -2
	v_bfrev_b32_e32 v4, -2
	s_mov_b32 s8, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_u32_e64 s2, v1
	s_cbranch_execz .LBB9_3
; %bb.2:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x8
	s_load_b64 s[10:11], s[0:1], 0x14
	v_lshlrev_b64 v[3:4], 4, v[1:2]
	s_load_b128 s[4:7], s[0:1], 0x20
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s2, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
	global_load_b96 v[3:5], v[3:4], off
	s_waitcnt vmcnt(0)
	v_dual_subrev_f32 v0, s4, v3 :: v_dual_subrev_f32 v3, s5, v4
	v_subrev_f32_e32 v5, s6, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_scale_f32 v4, null, s7, s7, v0
	v_div_scale_f32 v6, null, s7, s7, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_scale_f32 v8, null, s7, s7, v5
	v_rcp_f32_e32 v7, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v9, v6
	v_div_scale_f32 v12, vcc_lo, v0, s7, v0
	v_rcp_f32_e32 v10, v8
	v_div_scale_f32 v14, s2, v3, s7, v3
	s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_fma_f32 v11, -v4, v7, 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v13, -v6, v9, 1.0
	v_fmac_f32_e32 v7, v11, v7
	v_fma_f32 v11, -v8, v10, 1.0
	v_fmac_f32_e32 v9, v13, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v15, v12, v7 :: v_dual_fmac_f32 v10, v11, v10
	v_mul_f32_e32 v11, v14, v9
	v_div_scale_f32 v13, s3, v5, s7, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v16, -v4, v15, v12
	v_fma_f32 v18, -v6, v11, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v17, v13, v10
	v_fmac_f32_e32 v15, v16, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v11, v18, v9
	v_fma_f32 v16, -v8, v17, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v4, -v4, v15, v12
	v_fma_f32 v6, -v6, v11, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v17, v16, v10
	v_div_fmas_f32 v4, v4, v7, v15
	s_mov_b32 vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v6, v6, v9, v11
	v_fma_f32 v7, -v8, v17, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v0, v4, s7, v0
	s_mov_b32 vcc_lo, s3
	v_div_fixup_f32 v3, v6, s7, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v4, v7, v10, v17
	v_cvt_i32_f32_e32 v7, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_i32_f32_e32 v0, v3
	v_div_fixup_f32 v3, v4, s7, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[5:6], null, s10, v7, v[0:1]
	v_cvt_i32_f32_e32 v0, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, v5, s11, v[0:1]
	v_mov_b32_e32 v4, v1
.LBB9_3:                                ; %.sink.split
	s_or_b32 exec_lo, exec_lo, s8
	s_load_b64 s[0:1], s[0:1], 0x30
	v_lshlrev_b64 v[0:1], 3, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b64 v[0:1], v[3:4], off
.LBB9_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9hashAtomsjP15HIP_vector_typeIfLj4EES_IiLj3EES0_PS_IiLj2EEj
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 19
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end9:
	.size	_Z9hashAtomsjP15HIP_vector_typeIfLj4EES_IiLj3EES0_PS_IiLj2EEj, .Lfunc_end9-_Z9hashAtomsjP15HIP_vector_typeIfLj4EES_IiLj3EES0_PS_IiLj2EEj
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 564
; NumSgprs: 18
; NumVgprs: 19
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 19
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z19bitonic_pass_kernelP15HIP_vector_typeIiLj2EEiii ; -- Begin function _Z19bitonic_pass_kernelP15HIP_vector_typeIiLj2EEiii
	.globl	_Z19bitonic_pass_kernelP15HIP_vector_typeIiLj2EEiii
	.p2align	8
	.type	_Z19bitonic_pass_kernelP15HIP_vector_typeIiLj2EEiii,@function
_Z19bitonic_pass_kernelP15HIP_vector_typeIiLj2EEiii: ; @_Z19bitonic_pass_kernelP15HIP_vector_typeIiLj2EEiii
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x24
	s_load_b128 s[4:7], s[0:1], 0x8
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_bfm_b32 s2, s5, 0
	v_ashrrev_i32_e32 v0, s5, v1
	v_and_b32_e32 v2, s2, v1
	s_add_i32 s2, s5, 1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_lshl_add_u32 v2, v0, s2, v2
	s_lshl_b32 s2, 1, s5
	v_lshrrev_b32_e32 v0, s4, v1
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	s_lshl_b64 s[8:9], s[2:3], 3
	s_and_b32 s3, s6, 1
	v_lshlrev_b64 v[3:4], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, v3, s8
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v4, vcc_lo
	s_clause 0x1
	global_load_b64 v[3:4], v[3:4], off
	global_load_b64 v[5:6], v[5:6], off
	v_add_nc_u32_e32 v1, s2, v2
	v_and_b32_e32 v0, s3, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	v_dual_cndmask_b32 v7, v2, v1 :: v_dual_cndmask_b32 v0, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v8, 31, v7
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[7:8], 3, v[7:8]
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v7, s0, s0, v7
	v_add_co_ci_u32_e64 v8, s0, s1, v8, s0
	s_waitcnt vmcnt(0)
	v_cmp_lt_i32_e32 vcc_lo, v3, v5
	v_dual_cndmask_b32 v10, v6, v4 :: v_dual_cndmask_b32 v9, v5, v3
	v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v4, v4, v6
	s_clause 0x1
	global_store_b64 v[0:1], v[9:10], off
	global_store_b64 v[7:8], v[3:4], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19bitonic_pass_kernelP15HIP_vector_typeIiLj2EEiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end10:
	.size	_Z19bitonic_pass_kernelP15HIP_vector_typeIiLj2EEiii, .Lfunc_end10-_Z19bitonic_pass_kernelP15HIP_vector_typeIiLj2EEiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 316
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z11bitonic_512P15HIP_vector_typeIiLj2EEiii ; -- Begin function _Z11bitonic_512P15HIP_vector_typeIiLj2EEiii
	.globl	_Z11bitonic_512P15HIP_vector_typeIiLj2EEiii
	.p2align	8
	.type	_Z11bitonic_512P15HIP_vector_typeIiLj2EEiii,@function
_Z11bitonic_512P15HIP_vector_typeIiLj2EEiii: ; @_Z11bitonic_512P15HIP_vector_typeIiLj2EEiii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b64 s[4:5], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
	s_load_b128 s[0:3], s[0:1], 0x8
	v_lshlrev_b32_e32 v4, 3, v0
	v_ashrrev_i32_e32 v1, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v1, 24, v1
	v_add_lshl_u32 v1, v3, v1, 1
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v1, 0xfffffe00, v1
	v_add_nc_u32_e32 v1, v1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[1:2], 3, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s4, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
	s_clause 0x1
	global_load_b64 v[5:6], v[1:2], off
	global_load_b64 v[7:8], v[1:2], off offset:2048
	s_waitcnt vmcnt(0)
	ds_store_2addr_stride64_b64 v4, v[5:6], v[7:8] offset1:4
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc1 .LBB11_3
; %bb.1:                                ; %.lr.ph
	v_lshrrev_b32_e32 v3, s0, v3
	s_and_b32 s0, s2, 1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_and_b32_e32 v3, s0, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v3
.LBB11_2:                               ; =>This Inner Loop Header: Depth=1
	s_bfm_b32 s2, s1, 0
	v_lshrrev_b32_e32 v3, s1, v0
	v_and_b32_e32 v5, s2, v0
	s_add_i32 s3, s1, 1
	s_lshl_b32 s0, 1, s1
	s_add_i32 s4, s1, -1
	s_cmp_eq_u32 s1, 0
	v_lshl_add_u32 v3, v3, s3, v5
	s_mov_b32 s1, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v5, 3, v3
	v_add_nc_u32_e32 v9, s0, v3
	v_lshl_add_u32 v7, s0, 3, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_cndmask_b32 v10, v9, v3 :: v_dual_cndmask_b32 v3, v3, v9
	ds_load_b64 v[5:6], v5
	ds_load_b64 v[7:8], v7
	v_lshlrev_b32_e32 v11, 3, v10
	v_lshlrev_b32_e32 v3, 3, v3
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_i32_e64 s0, v5, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v10, v8, v6, s0
	v_cndmask_b32_e64 v9, v7, v5, s0
	v_cndmask_b32_e64 v6, v6, v8, s0
	v_cndmask_b32_e64 v5, v5, v7, s0
	ds_store_b64 v11, v[9:10]
	ds_store_b64 v3, v[5:6]
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB11_2
.LBB11_3:                               ; %._crit_edge
	ds_load_2addr_stride64_b64 v[3:6], v4 offset1:4
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_store_b64 v[1:2], v[3:4], off
	global_store_b64 v[1:2], v[5:6], off offset:2048
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11bitonic_512P15HIP_vector_typeIiLj2EEiii
		.amdhsa_group_segment_fixed_size 4096
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end11:
	.size	_Z11bitonic_512P15HIP_vector_typeIiLj2EEiii, .Lfunc_end11-_Z11bitonic_512P15HIP_vector_typeIiLj2EEiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 432
; NumSgprs: 18
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4096 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z8sortCelljP15HIP_vector_typeIfLj4EEPS_IiLj2EES1_S3_ ; -- Begin function _Z8sortCelljP15HIP_vector_typeIfLj4EEPS_IiLj2EES1_S3_
	.globl	_Z8sortCelljP15HIP_vector_typeIfLj4EEPS_IiLj2EES1_S3_
	.p2align	8
	.type	_Z8sortCelljP15HIP_vector_typeIfLj4EEPS_IiLj2EES1_S3_,@function
_Z8sortCelljP15HIP_vector_typeIfLj4EEPS_IiLj2EES1_S3_: ; @_Z8sortCelljP15HIP_vector_typeIfLj4EEPS_IiLj2EES1_S3_
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x34
	s_load_b32 s2, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
	s_mov_b32 s3, exec_lo
	v_cmpx_gt_u32_e64 s2, v1
	s_cbranch_execz .LBB12_9
; %bb.1:
	s_load_b256 s[4:11], s[0:1], 0x8
	v_mov_b32_e32 v2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 3, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v3, vcc_lo, s6, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v1
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v7, v3
	s_and_saveexec_b32 s1, vcc_lo
	s_cbranch_execz .LBB12_3
; %bb.2:
	v_dual_mov_b32 v6, v2 :: v_dual_add_nc_u32 v5, -1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	v_add_co_u32 v5, s0, s6, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v6, s0, s7, v6, s0
	global_load_b32 v7, v[5:6], off
.LBB12_3:
	s_or_b32 exec_lo, exec_lo, s1
	v_cmp_eq_u32_e64 s0, 0, v1
	s_waitcnt vmcnt(0)
	v_cmp_ne_u32_e64 s1, v3, v7
	v_ashrrev_i32_e32 v6, 31, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, s0, s1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB12_6
; %bb.4:
	v_mov_b32_e32 v5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 3, v[5:6]
	v_add_co_u32 v8, s0, s10, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v9, s0, s11, v9, s0
	global_store_b32 v[8:9], v1, off
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB12_6
; %bb.5:
	v_ashrrev_i32_e32 v8, 31, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 3, v[7:8]
	v_add_co_u32 v7, vcc_lo, s10, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, s11, v8, vcc_lo
	global_store_b32 v[7:8], v1, off offset:4
.LBB12_6:
	s_or_b32 exec_lo, exec_lo, s1
	s_add_i32 s2, s2, -1
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e64 s2, v1
	s_cbranch_execz .LBB12_8
; %bb.7:
	v_dual_mov_b32 v5, v3 :: v_dual_add_nc_u32 v0, 1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	v_add_co_u32 v5, vcc_lo, s10, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s11, v6, vcc_lo
	global_store_b32 v[5:6], v0, off offset:4
.LBB12_8:
	s_or_b32 exec_lo, exec_lo, s0
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[0:1], 4, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 4, v[4:5]
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	v_add_co_u32 v0, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	global_load_b128 v[3:6], v[3:4], off
	s_waitcnt vmcnt(0)
	global_store_b128 v[0:1], v[3:6], off
.LBB12_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8sortCelljP15HIP_vector_typeIfLj4EEPS_IiLj2EES1_S3_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end12:
	.size	_Z8sortCelljP15HIP_vector_typeIfLj4EEPS_IiLj2EES1_S3_, .Lfunc_end12-_Z8sortCelljP15HIP_vector_typeIfLj4EEPS_IiLj2EES1_S3_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 472
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z17probeIntersectionPiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfS3_ji ; -- Begin function _Z17probeIntersectionPiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfS3_ji
	.globl	_Z17probeIntersectionPiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfS3_ji
	.p2align	8
	.type	_Z17probeIntersectionPiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfS3_ji,@function
_Z17probeIntersectionPiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfS3_ji: ; @_Z17probeIntersectionPiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfS3_ji
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x9c
	s_load_b128 s[16:19], s[0:1], 0x3c
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v0, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s4, s2, 16
	s_and_b32 s2, s2, 0xffff
	v_mad_u64_u32 v[7:8], null, s14, s4, v[2:3]
	v_mad_u64_u32 v[4:5], null, s13, s2, v[1:2]
	s_and_b32 s2, s3, 0xffff
	s_add_i32 s3, s17, -1
	v_mad_u64_u32 v[5:6], null, s15, s2, v[0:1]
	s_add_i32 s2, s16, -1
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_cmp_gt_u32_e32 vcc_lo, s2, v4
	s_delay_alu instid0(VALU_DEP_4)
	v_cmp_gt_u32_e64 s2, s3, v7
	s_add_i32 s3, s18, -1
	s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
	v_cmp_gt_u32_e64 s3, s3, v5
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB13_21
; %bb.1:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x78
	s_load_b128 s[8:11], s[0:1], 0x30
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v0, s4, v4
	v_add_nc_u32_e32 v1, s5, v7
	v_add_nc_u32_e32 v2, s6, v5
	s_add_i32 s2, s8, -1
	s_add_i32 s3, s9, -1
	v_cmp_gt_i32_e32 vcc_lo, s2, v0
	v_cmp_gt_i32_e64 s2, s3, v1
	s_add_i32 s3, s10, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e64 s3, s3, v2
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB13_21
; %bb.2:
	s_load_b256 s[4:11], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	s_load_b32 s7, s[0:1], 0x5c
	s_load_b128 s[12:15], s[0:1], 0x60
	v_cvt_f32_i32_e32 v0, v0
	v_cvt_f32_i32_e32 v1, v1
	v_cvt_f32_i32_e32 v2, v2
	s_mov_b32 s19, -1
	s_mov_b32 s23, 0
	s_mov_b32 s22, 0
                                        ; implicit-def: $sgpr16
                                        ; implicit-def: $sgpr21
                                        ; implicit-def: $sgpr20
	s_waitcnt lgkmcnt(0)
	v_fma_f32 v6, s7, v0, s8
	v_fma_f32 v12, s7, v1, s9
	v_fma_f32 v13, s7, v2, s10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_subrev_f32 v0, s8, v6 :: v_dual_subrev_f32 v1, s9, v12
	s_load_b64 s[8:9], s[0:1], 0x70
	v_div_scale_f32 v3, null, s11, s11, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_scale_f32 v8, null, s11, s11, v1
	v_div_scale_f32 v15, vcc_lo, v0, s11, v0
	v_rcp_f32_e32 v10, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_rcp_f32_e32 v11, v8
	v_div_scale_f32 v16, s2, v1, s11, v1
	s_waitcnt_depctr 0xfff
	v_fma_f32 v17, -v3, v10, 1.0
	v_fma_f32 v18, -v8, v11, 1.0
	v_subrev_f32_e32 v2, s10, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v10, v17, v10 :: v_dual_fmac_f32 v11, v18, v11
	v_div_scale_f32 v9, null, s11, s11, v2
	v_div_scale_f32 v20, s3, v2, s11, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v17, v15, v10 :: v_dual_mul_f32 v18, v16, v11
	v_rcp_f32_e32 v14, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v21, -v3, v17, v15
	v_fma_f32 v22, -v8, v18, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v17, v21, v10 :: v_dual_fmac_f32 v18, v22, v11
	s_waitcnt_depctr 0xfff
	v_fma_f32 v19, -v9, v14, 1.0
	v_fma_f32 v3, -v3, v17, v15
	v_fma_f32 v8, -v8, v18, v16
	v_fmac_f32_e32 v14, v19, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v3, v3, v10, v17
	s_mov_b32 vcc_lo, s2
	v_mul_f32_e32 v19, v20, v14
                                        ; implicit-def: $vgpr17
	v_div_fmas_f32 v8, v8, v11, v18
	s_mov_b32 vcc_lo, s3
	v_div_fixup_f32 v0, v3, s11, v0
	s_add_i32 s3, s4, -1
	v_fma_f32 v23, -v9, v19, v20
	s_xor_b32 s4, s7, 0x80000000
	s_add_u32 s10, s14, 8
	s_mov_b32 s14, 0
	v_div_fixup_f32 v1, v8, s11, v1
	v_fmac_f32_e32 v19, v23, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f32_e32 v15, v1
	v_fma_f32 v9, -v9, v19, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v9, v9, v14, v19
	v_cvt_i32_f32_e32 v14, v0
	v_div_fixup_f32 v2, v9, s11, v2
	s_addc_u32 s11, s15, 0
                                        ; implicit-def: $sgpr15
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_i32_f32_e32 v16, v2
.LBB13_3:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB13_4 Depth 2
                                        ;       Child Loop BB13_5 Depth 3
                                        ;         Child Loop BB13_7 Depth 4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, s19, v14
	s_mov_b32 s25, 0
	s_mov_b32 s28, 0
	s_mov_b32 s29, -1
                                        ; implicit-def: $sgpr24
                                        ; implicit-def: $sgpr27
                                        ; implicit-def: $sgpr26
	v_minmax_i32 v0, v0, s3, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_lo_u32 v18, v0, s5
.LBB13_4:                               ;   Parent Loop BB13_3 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB13_5 Depth 3
                                        ;         Child Loop BB13_7 Depth 4
	v_add_nc_u32_e32 v0, s29, v15
	s_mov_b32 s31, 0
	s_mov_b32 s34, -1
	s_mov_b32 s35, 0
                                        ; implicit-def: $sgpr30
                                        ; implicit-def: $sgpr33
                                        ; implicit-def: $sgpr36
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_minmax_i32 v0, v0, s3, 0
	v_add_nc_u32_e32 v0, v0, v18
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_lo_u32 v19, v0, s6
.LBB13_5:                               ;   Parent Loop BB13_3 Depth=1
                                        ;     Parent Loop BB13_4 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB13_7 Depth 4
	v_add_nc_u32_e32 v0, s34, v16
	s_and_not1_b32 s2, s36, exec_lo
	s_and_b32 s36, s23, exec_lo
	s_mov_b32 s37, exec_lo
	s_or_b32 s36, s2, s36
	v_minmax_i32 v0, v0, s3, 0
	s_mov_b32 s2, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v0, v19
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_add_co_u32 v0, vcc_lo, s12, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v1, vcc_lo, s13, v1, vcc_lo
	global_load_b64 v[8:9], v[0:1], off
	s_waitcnt vmcnt(0)
	v_min_i32_e32 v0, 0x7ffffffe, v9
	v_cmpx_gt_i32_e64 v0, v8
	s_cbranch_execz .LBB13_11
; %bb.6:                                ; %.lr.ph.i.preheader
                                        ;   in Loop: Header=BB13_5 Depth=3
	v_ashrrev_i32_e32 v1, 31, v8
	v_mov_b32_e32 v0, v8
	v_add_nc_u32_e32 v8, 1, v8
	s_mov_b32 s38, 0
                                        ; implicit-def: $sgpr39
                                        ; implicit-def: $sgpr41
                                        ; implicit-def: $sgpr40
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 4, v[0:1]
	v_add_co_u32 v10, vcc_lo, s10, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v11, vcc_lo, s11, v1, vcc_lo
.LBB13_7:                               ; %.lr.ph.i
                                        ;   Parent Loop BB13_3 Depth=1
                                        ;     Parent Loop BB13_4 Depth=2
                                        ;       Parent Loop BB13_5 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	global_load_b128 v[0:3], v[10:11], off offset:-8
	s_waitcnt vmcnt(0)
	v_dual_sub_f32 v1, v1, v12 :: v_dual_sub_f32 v0, v0, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v1, v1, v1
	v_dual_sub_f32 v2, v2, v13 :: v_dual_fmac_f32 v1, v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v1, v2, v2
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v1
	v_mul_f32_e32 v0, 0x4f800000, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v1, v0, vcc_lo
	v_sqrt_f32_e32 v1, v0
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v2, -1, v1
	v_add_nc_u32_e32 v20, 1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v21, -v2, v1, v0
	v_fma_f32 v22, -v20, v1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s2, 0, v21
	v_cndmask_b32_e64 v1, v1, v2, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s2, 0, v22
	v_cndmask_b32_e64 v1, v1, v20, s2
	s_and_not1_b32 s2, s40, exec_lo
	s_and_b32 s40, s23, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 s40, s2, s40
	v_mul_f32_e32 v2, 0x37800000, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v1, v2, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v0, 0x260
	v_dual_subrev_f32 v2, s7, v3 :: v_dual_cndmask_b32 v1, v1, v0
	v_mov_b32_e32 v0, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_nlt_f32_e32 vcc_lo, v1, v2
	s_and_saveexec_b32 s42, vcc_lo
; %bb.8:                                ;   in Loop: Header=BB13_7 Depth=4
	v_add_f32_e32 v0, 0x3fb33333, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_lt_f32_e64 s2, v1, v0
	v_mov_b32_e32 v0, v17
	s_or_b32 s2, s2, s23
	s_and_not1_b32 s23, s40, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s40, s23, s2
                                        ; implicit-def: $sgpr23
; %bb.9:                                ;   in Loop: Header=BB13_7 Depth=4
	s_or_b32 exec_lo, exec_lo, s42
	v_cmp_ge_i32_e64 s2, v8, v9
	s_xor_b32 s42, vcc_lo, -1
	v_dual_mov_b32 v17, v0 :: v_dual_add_nc_u32 v8, 1, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, s42, s2
	s_and_b32 s2, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_or_b32 s38, s2, s38
	v_add_co_u32 v10, s2, v10, 16
	v_add_co_ci_u32_e64 v11, s2, 0, v11, s2
	s_and_not1_b32 s23, s23, exec_lo
	s_and_b32 s42, s40, exec_lo
	s_and_not1_b32 s2, s41, exec_lo
	s_and_not1_b32 s39, s39, exec_lo
	s_and_b32 s43, vcc_lo, exec_lo
	s_or_b32 s23, s23, s42
	s_or_b32 s41, s2, s42
	s_or_b32 s39, s39, s43
	s_and_not1_b32 exec_lo, exec_lo, s38
	s_cbranch_execnz .LBB13_7
; %bb.10:                               ; %Flow
                                        ;   in Loop: Header=BB13_5 Depth=3
	s_or_b32 exec_lo, exec_lo, s38
	v_mov_b32_e32 v17, v0
	s_and_not1_b32 s2, s36, exec_lo
	s_and_b32 s23, s41, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s36, s2, s23
	s_or_not1_b32 s2, s39, exec_lo
.LBB13_11:                              ; %Flow221
                                        ;   in Loop: Header=BB13_5 Depth=3
	s_or_b32 exec_lo, exec_lo, s37
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s23, s33, exec_lo
	s_and_b32 s33, s35, exec_lo
	s_mov_b32 s37, -1
	s_or_b32 s33, s23, s33
                                        ; implicit-def: $sgpr23
                                        ; implicit-def: $sgpr35
	s_and_saveexec_b32 s38, s2
; %bb.12:                               ;   in Loop: Header=BB13_5 Depth=3
	s_add_i32 s2, s34, 1
	s_cmp_gt_i32 s34, 0
	s_cselect_b32 s35, -1, 0
	s_cmp_eq_u32 s2, 2
	s_cselect_b32 s34, -1, 0
	s_and_not1_b32 s33, s33, exec_lo
	s_and_b32 s37, s35, exec_lo
	s_and_b32 s23, s36, exec_lo
	s_or_b32 s33, s33, s37
	s_or_not1_b32 s37, s34, exec_lo
	s_mov_b32 s34, s2
; %bb.13:                               ; %Flow222
                                        ;   in Loop: Header=BB13_5 Depth=3
	s_or_b32 exec_lo, exec_lo, s38
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, exec_lo, s37
	s_or_b32 s31, s2, s31
	s_and_not1_b32 s2, s30, exec_lo
	s_and_b32 s30, s33, exec_lo
	s_and_not1_b32 s26, s26, exec_lo
	s_and_b32 s37, s36, exec_lo
	s_or_b32 s30, s2, s30
	s_or_b32 s26, s26, s37
	s_and_not1_b32 exec_lo, exec_lo, s31
	s_cbranch_execnz .LBB13_5
; %bb.14:                               ;   in Loop: Header=BB13_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s23, s27, exec_lo
	s_and_b32 s27, s28, exec_lo
	s_mov_b32 s2, -1
	s_or_b32 s27, s23, s27
                                        ; implicit-def: $sgpr23
                                        ; implicit-def: $sgpr28
	s_and_saveexec_b32 s31, s30
; %bb.15:                               ;   in Loop: Header=BB13_4 Depth=2
	s_add_i32 s30, s29, 1
	s_cmp_gt_i32 s29, 0
	s_cselect_b32 s28, -1, 0
	s_cmp_eq_u32 s30, 2
	s_cselect_b32 s2, -1, 0
	s_and_not1_b32 s27, s27, exec_lo
	s_and_b32 s29, s28, exec_lo
	s_and_b32 s23, s26, exec_lo
	s_or_b32 s27, s27, s29
	s_or_not1_b32 s2, s2, exec_lo
	s_mov_b32 s29, s30
; %bb.16:                               ; %Flow223
                                        ;   in Loop: Header=BB13_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, exec_lo, s2
	s_or_b32 s25, s2, s25
	s_and_not1_b32 s2, s24, exec_lo
	s_and_b32 s24, s27, exec_lo
	s_and_not1_b32 s20, s20, exec_lo
	s_and_b32 s30, s26, exec_lo
	s_or_b32 s24, s2, s24
	s_or_b32 s20, s20, s30
	s_and_not1_b32 exec_lo, exec_lo, s25
	s_cbranch_execnz .LBB13_4
; %bb.17:                               ;   in Loop: Header=BB13_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s25
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s21, s21, exec_lo
	s_and_b32 s22, s22, exec_lo
	s_mov_b32 s2, -1
	s_or_b32 s21, s21, s22
                                        ; implicit-def: $sgpr23
                                        ; implicit-def: $sgpr22
	s_and_saveexec_b32 s25, s24
; %bb.18:                               ;   in Loop: Header=BB13_3 Depth=1
	s_add_i32 s24, s19, 1
	s_cmp_gt_i32 s19, 0
	s_cselect_b32 s22, -1, 0
	s_cmp_eq_u32 s24, 2
	s_cselect_b32 s2, -1, 0
	s_and_not1_b32 s19, s21, exec_lo
	s_and_b32 s21, s22, exec_lo
	s_and_b32 s23, s20, exec_lo
	s_or_b32 s21, s19, s21
	s_or_not1_b32 s2, s2, exec_lo
	s_mov_b32 s19, s24
; %bb.19:                               ; %Flow224
                                        ;   in Loop: Header=BB13_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s25
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, exec_lo, s2
	s_or_b32 s14, s2, s14
	s_and_not1_b32 s2, s15, exec_lo
	s_and_b32 s15, s21, exec_lo
	s_and_not1_b32 s16, s16, exec_lo
	s_and_b32 s24, s20, exec_lo
	s_or_b32 s15, s2, s15
	s_or_b32 s16, s16, s24
	s_and_not1_b32 exec_lo, exec_lo, s14
	s_cbranch_execnz .LBB13_3
; %bb.20:                               ; %_Z14computeInOrOut15HIP_vector_typeIiLj3EEPS_IiLj2EEPS_IfLj4EES_IfLj3EEfS0_.exit
	s_or_b32 exec_lo, exec_lo, s14
	v_mad_u64_u32 v[0:1], null, v4, s17, v[7:8]
	s_load_b64 s[0:1], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, v0, s18, v[5:6]
	v_cndmask_b32_e64 v0, 0x3fb33333, 0, s16
	v_cndmask_b32_e64 v4, v17, v0, s15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v2, 31, v1
	v_cmp_gt_f32_e64 vcc_lo, 0x3a83126f, |v4|
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_cndmask_b32_e32 v5, 0x7ffffffe, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	global_store_b32 v[0:1], v5, off
	global_store_b32 v[2:3], v4, off
.LBB13_21:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17probeIntersectionPiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfS3_ji
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 400
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 24
		.amdhsa_next_free_sgpr 44
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end13:
	.size	_Z17probeIntersectionPiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfS3_ji, .Lfunc_end13-_Z17probeIntersectionPiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfS3_ji
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1804
; NumSgprs: 46
; NumVgprs: 24
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 5
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 46
; NumVGPRsForWavesPerEU: 24
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.protected	_Z19distanceFieldRefinePiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfjjS3_j ; -- Begin function _Z19distanceFieldRefinePiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfjjS3_j
	.globl	_Z19distanceFieldRefinePiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfjjS3_j
	.p2align	8
	.type	_Z19distanceFieldRefinePiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfjjS3_j,@function
_Z19distanceFieldRefinePiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfjjS3_j: ; @_Z19distanceFieldRefinePiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfjjS3_j
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x9c
	s_load_b32 s3, s[0:1], 0x8c
	s_load_b128 s[4:7], s[0:1], 0x7c
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_mul_i32 s15, s15, s2
	s_mov_b32 s2, exec_lo
	v_add3_u32 v0, s15, s3, v0
	v_cmpx_gt_u32_e64 s4, v0
	s_cbranch_execz .LBB14_13
; %bb.1:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x0
	s_load_b32 s4, s[0:1], 0x5c
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_mov_b32 s2, 0x3fb33333
	global_load_b32 v0, v[0:1], off
	v_div_scale_f32 v1, null, s4, s4, 0x3fb33333
	v_rcp_f32_e32 v2, v1
	s_waitcnt_depctr 0xfff
	v_fma_f32 v3, -v1, v2, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v2, v3, v2
	v_div_scale_f32 v3, vcc_lo, s2, s4, s2
	s_load_b64 s[2:3], s[0:1], 0x70
	v_mul_f32_e32 v4, v3, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v5, -v1, v4, v3
	v_fmac_f32_e32 v4, v5, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v1, -v1, v4, v3
	v_div_fmas_f32 v1, v1, v2, v4
	v_mov_b32_e32 v4, 0x47c35000
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v1, v1, s4, 0x3fb33333
	v_ceil_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_i32_f32_e32 v1, v1
	v_cmp_gt_i32_e32 vcc_lo, 0, v1
	v_readfirstlane_b32 s16, v1
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v1, 31, v0
	s_cbranch_vccnz .LBB14_12
; %bb.2:                                ; %.lr.ph216
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x3c
	s_load_b128 s[12:15], s[0:1], 0x50
	v_add_nc_u32_e32 v4, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	v_xor_b32_e32 v4, v4, v1
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s0, s10, s9
	s_add_i32 s8, s8, -1
	s_ashr_i32 s1, s0, 31
	s_add_i32 s11, s0, s1
	v_xor_b32_e32 v6, s1, v1
	s_xor_b32 s11, s11, s1
	s_sub_i32 s1, 0, s16
	v_cvt_f32_u32_e32 v2, s11
	s_sub_i32 s15, 0, s11
	s_mov_b32 s18, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v2, v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	v_cvt_u32_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v3, s15, v2
	s_ashr_i32 s15, s10, 31
	s_add_i32 s17, s10, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_xor_b32 s17, s17, s15
	v_mul_hi_u32 v3, v2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, v2, v3
	v_mul_hi_u32 v2, v4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v3, v2, s11
	v_sub_nc_u32_e32 v3, v4, v3
	v_add_nc_u32_e32 v4, 1, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v5, s11, v3
	v_cmp_le_u32_e32 vcc_lo, s11, v3
	v_cndmask_b32_e32 v3, v3, v5, vcc_lo
	v_cvt_f32_u32_e32 v5, s17
	v_cndmask_b32_e32 v2, v2, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s11, v3
	v_rcp_iflag_f32_e32 v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, 1, v2
	s_add_i32 s11, s9, -1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, 0x4f7ffffe, v3
	v_cvt_u32_f32_e32 v3, v3
	v_cndmask_b32_e32 v2, v2, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v2, v2, v6
	v_sub_nc_u32_e32 v2, v2, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v4, v2, s0
	s_sub_i32 s0, 0, s17
	v_mul_lo_u32 v5, s0, v3
	s_lshl_b32 s0, s16, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v4, v0, v4
	v_mul_hi_u32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v4
	v_add_nc_u32_e32 v7, v4, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v3, v5
	v_xor_b32_e32 v5, v7, v6
	v_xor_b32_e32 v6, s15, v6
	s_add_i32 s15, s10, -1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v5, v3
	v_mul_lo_u32 v7, v3, s17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v5, v5, v7
	v_add_nc_u32_e32 v7, 1, v3
	v_subrev_nc_u32_e32 v8, s17, v5
	v_cmp_le_u32_e32 vcc_lo, s17, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v3, v3, v7, vcc_lo
	v_cndmask_b32_e32 v5, v5, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v7, 1, v3
	v_cmp_le_u32_e32 vcc_lo, s17, v5
	s_or_b32 s17, s0, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v3, v3, v7, vcc_lo
	v_mul_lo_u32 v7, s9, v2
	v_xor_b32_e32 v5, v3, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v3, v5, v6
	v_sub_nc_u32_e32 v6, v6, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v8, v3, s10
	v_sub_nc_u32_e32 v6, v6, v5
	v_add_nc_u32_e32 v9, s6, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v7, v4, v8
	v_mad_u64_u32 v[4:5], null, s10, v6, v[0:1]
	v_add_nc_u32_e32 v8, s5, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v5, s7, v7
	v_cvt_f32_i32_e32 v7, v9
	v_cvt_f32_i32_e32 v6, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f32_i32_e32 v8, v5
	v_fma_f32 v7, s4, v7, s13
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f32 v5, s4, v6, s12
	v_subrev_nc_u32_e32 v6, s16, v4
	v_mov_b32_e32 v4, 0x47c35000
	v_fma_f32 v8, s4, v8, s14
.LBB14_3:                               ; %.lr.ph209
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB14_4 Depth 2
                                        ;       Child Loop BB14_5 Depth 3
	v_add_nc_u32_e32 v9, s18, v2
	s_mov_b32 s19, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_minmax_i32 v9, v9, s8, 0
	v_add_nc_u32_e32 v10, s5, v9
	v_mul_lo_u32 v9, v9, s9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v10, v10
	v_fma_f32 v10, s4, v10, s12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v10, v10, v5
	v_mul_f32_e32 v10, v10, v10
.LBB14_4:                               ; %.lr.ph
                                        ;   Parent Loop BB14_3 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB14_5 Depth 3
	v_add_nc_u32_e32 v11, s19, v3
	s_mov_b32 s20, s17
	v_mov_b32_e32 v13, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_minmax_i32 v11, v11, s11, 0
	v_add_nc_u32_e32 v12, s6, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v12, v12
	v_fma_f32 v12, s4, v12, s13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v12, v12, v7 :: v_dual_add_nc_u32 v11, v11, v9
	v_mul_lo_u32 v11, v11, s10
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f32 v12, v12, v12, v10
.LBB14_5:                               ;   Parent Loop BB14_3 Depth=1
                                        ;     Parent Loop BB14_4 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_minmax_i32 v14, v13, s15, 0
	s_mov_b32 s21, exec_lo
	v_add_nc_u32_e32 v15, v14, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v16, 31, v15
	v_lshlrev_b64 v[15:16], 2, v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v15, vcc_lo, s2, v15
	v_add_co_ci_u32_e32 v16, vcc_lo, s3, v16, vcc_lo
	global_load_b32 v15, v[15:16], off
	s_waitcnt vmcnt(0)
	v_cmpx_lt_f32_e32 0x3fb3126e, v15
	s_cbranch_execz .LBB14_7
; %bb.6:                                ;   in Loop: Header=BB14_5 Depth=3
	v_add_nc_u32_e32 v14, s7, v14
	v_max_f32_e32 v4, v4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v14, v14
	v_fma_f32 v14, s4, v14, s14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v14, v14, v8
	v_fma_f32 v14, v14, v14, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v15, 0x4f800000, v14
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v14
	v_cndmask_b32_e32 v14, v14, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v15, v14
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v16, -1, v15
	v_add_nc_u32_e32 v17, 1, v15
	v_fma_f32 v18, -v16, v15, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v19, -v17, v15, v14
	v_cmp_ge_f32_e64 s0, 0, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v15, v15, v16, s0
	v_cmp_lt_f32_e64 s0, 0, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v15, v15, v17, s0
	v_mul_f32_e32 v16, 0x37800000, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v15, v15, v16, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v14, 0x260
	v_cndmask_b32_e32 v14, v15, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_min_f32_e32 v4, v14, v4
.LBB14_7:                               ;   in Loop: Header=BB14_5 Depth=3
	s_or_b32 exec_lo, exec_lo, s21
	v_add_nc_u32_e32 v13, 1, v13
	s_add_i32 s20, s20, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s20, 0
	s_cbranch_scc0 .LBB14_5
; %bb.8:                                ; %._crit_edge
                                        ;   in Loop: Header=BB14_4 Depth=2
	s_add_i32 s0, s19, 1
	s_cmp_eq_u32 s19, s16
	s_cbranch_scc1 .LBB14_10
; %bb.9:                                ;   in Loop: Header=BB14_4 Depth=2
	s_mov_b32 s19, s0
	s_branch .LBB14_4
.LBB14_10:                              ; %._crit_edge210
                                        ;   in Loop: Header=BB14_3 Depth=1
	s_add_i32 s0, s18, 1
	s_cmp_eq_u32 s18, s16
	s_cbranch_scc1 .LBB14_12
; %bb.11:                               ;   in Loop: Header=BB14_3 Depth=1
	s_mov_b32 s18, s0
	s_branch .LBB14_3
.LBB14_12:                              ; %Flow245
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_sub_f32_e32 v2, 0x3fb33333, v4
	v_cmp_gt_f32_e32 vcc_lo, 0x4479c000, v4
	v_cndmask_b32_e64 v2, -s4, v2, vcc_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB14_13:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19distanceFieldRefinePiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfjjS3_j
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 400
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 20
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end14:
	.size	_Z19distanceFieldRefinePiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfjjS3_j, .Lfunc_end14-_Z19distanceFieldRefinePiP15HIP_vector_typeIiLj2EES0_IiLj3EES0_IfLj4EES3_S3_S4_S2_PS4_PfjjS3_j
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1360
; NumSgprs: 24
; NumVgprs: 20
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 20
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z20closestAtomPerVertexPiP15HIP_vector_typeIfLj3EEjS0_IiLj3EES0_IfLj4EES4_PS0_IiLj2EEPS4_ ; -- Begin function _Z20closestAtomPerVertexPiP15HIP_vector_typeIfLj3EEjS0_IiLj3EES0_IfLj4EES4_PS0_IiLj2EEPS4_
	.globl	_Z20closestAtomPerVertexPiP15HIP_vector_typeIfLj3EEjS0_IiLj3EES0_IfLj4EES4_PS0_IiLj2EEPS4_
	.p2align	8
	.type	_Z20closestAtomPerVertexPiP15HIP_vector_typeIfLj3EEjS0_IiLj3EES0_IfLj4EES4_PS0_IiLj2EEPS4_,@function
_Z20closestAtomPerVertexPiP15HIP_vector_typeIfLj3EEjS0_IiLj3EES0_IfLj4EES4_PS0_IiLj2EEPS4_: ; @_Z20closestAtomPerVertexPiP15HIP_vector_typeIfLj3EEjS0_IiLj3EES0_IfLj4EES4_PS0_IiLj2EEPS4_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x5c
	s_load_b32 s3, s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_u32_e64 s3, v3
	s_cbranch_execz .LBB15_12
; %bb.1:
	s_clause 0x2
	s_load_b128 s[12:15], s[0:1], 0x0
	s_load_b256 s[4:11], s[0:1], 0x14
	s_load_b128 s[16:19], s[0:1], 0x40
	s_mov_b32 s1, -1
	s_waitcnt lgkmcnt(0)
	v_mad_i64_i32 v[0:1], null, v3, 12, s[14:15]
	global_load_b96 v[0:2], v[0:1], off
	s_waitcnt vmcnt(0)
	v_dual_subrev_f32 v5, s7, v0 :: v_dual_subrev_f32 v6, s8, v1
	v_subrev_f32_e32 v7, s9, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_scale_f32 v4, null, s10, s10, v5
	v_div_scale_f32 v8, null, s10, s10, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_scale_f32 v9, null, s10, s10, v7
	v_rcp_f32_e32 v10, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v11, v8
	v_div_scale_f32 v13, vcc_lo, v5, s10, v5
	v_rcp_f32_e32 v12, v9
	v_div_scale_f32 v14, s2, v6, s10, v6
	s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_fma_f32 v15, -v4, v10, 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v16, -v8, v11, 1.0
	v_fma_f32 v17, -v9, v12, 1.0
	v_dual_fmac_f32 v10, v15, v10 :: v_dual_fmac_f32 v11, v16, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v12, v17, v12
	v_div_scale_f32 v18, s3, v7, s10, v7
	v_dual_mul_f32 v15, v13, v10 :: v_dual_mul_f32 v16, v14, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v19, -v4, v15, v13
	v_fma_f32 v20, -v8, v16, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v17, v18, v12
	v_dual_fmac_f32 v15, v19, v10 :: v_dual_fmac_f32 v16, v20, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v21, -v9, v17, v18
	v_fma_f32 v4, -v4, v15, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v8, -v8, v16, v14
	v_fmac_f32_e32 v17, v21, v12
	v_mov_b32_e32 v13, 0x497423f0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v10, v4, v10, v15
	s_mov_b32 vcc_lo, s2
	v_fma_f32 v9, -v9, v17, v18
	v_div_fmas_f32 v8, v8, v11, v16
	s_mov_b32 vcc_lo, s3
	v_div_fixup_f32 v5, v10, s10, v5
	v_ashrrev_i32_e32 v4, 31, v3
	v_div_fmas_f32 v9, v9, v12, v17
	v_div_fixup_f32 v6, v8, s10, v6
	s_add_i32 s2, s4, -1
	v_cvt_i32_f32_e32 v10, v5
	s_add_u32 s3, s18, 4
	v_div_fixup_f32 v7, v9, s10, v7
	v_mov_b32_e32 v9, -1
	v_cvt_i32_f32_e32 v11, v6
	s_addc_u32 s4, s19, 0
	s_delay_alu instid0(VALU_DEP_3)
	v_cvt_i32_f32_e32 v12, v7
.LBB15_2:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB15_3 Depth 2
                                        ;       Child Loop BB15_4 Depth 3
                                        ;         Child Loop BB15_6 Depth 4
	v_add_nc_u32_e32 v5, s1, v10
	s_mov_b32 s7, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_minmax_i32 v5, v5, s2, 0
	v_mul_lo_u32 v14, v5, s5
.LBB15_3:                               ;   Parent Loop BB15_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB15_4 Depth 3
                                        ;         Child Loop BB15_6 Depth 4
	v_add_nc_u32_e32 v5, s7, v11
	s_mov_b32 s8, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_minmax_i32 v5, v5, s2, 0
	v_add_nc_u32_e32 v5, v5, v14
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_lo_u32 v15, v5, s6
.LBB15_4:                               ;   Parent Loop BB15_2 Depth=1
                                        ;     Parent Loop BB15_3 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB15_6 Depth 4
	v_add_nc_u32_e32 v5, s8, v12
	s_mov_b32 s9, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_minmax_i32 v5, v5, s2, 0
	v_add_nc_u32_e32 v5, v5, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s16, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s17, v6, vcc_lo
	global_load_b64 v[5:6], v[5:6], off
	s_waitcnt vmcnt(0)
	v_min_i32_e32 v7, 0x7ffffffe, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 v7, v5
	s_cbranch_execz .LBB15_8
; %bb.5:                                ; %.lr.ph.i.preheader
                                        ;   in Loop: Header=BB15_4 Depth=3
	v_ashrrev_i32_e32 v8, 31, v5
	v_mov_b32_e32 v7, v5
	s_mov_b32 s10, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 4, v[7:8]
	v_add_co_u32 v7, vcc_lo, s3, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, s4, v8, vcc_lo
.LBB15_6:                               ; %.lr.ph.i
                                        ;   Parent Loop BB15_2 Depth=1
                                        ;     Parent Loop BB15_3 Depth=2
                                        ;       Parent Loop BB15_4 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	global_load_b96 v[16:18], v[7:8], off offset:-4
	s_waitcnt vmcnt(0)
	v_dual_sub_f32 v17, v17, v1 :: v_dual_sub_f32 v16, v16, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v18, v18, v2 :: v_dual_mul_f32 v17, v17, v17
	v_fmac_f32_e32 v17, v16, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v17, v18, v18
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v17
	v_mul_f32_e32 v16, 0x4f800000, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v16, v17, v16, vcc_lo
	v_sqrt_f32_e32 v17, v16
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v19, 1, v17
	v_add_nc_u32_e32 v18, -1, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v21, -v19, v17, v16
	v_fma_f32 v20, -v18, v17, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s0, 0, v20
	v_cndmask_b32_e64 v17, v17, v18, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s0, 0, v21
	v_cndmask_b32_e64 v17, v17, v19, s0
	v_add_co_u32 v7, s0, v7, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v8, s0, 0, v8, s0
	v_mul_f32_e32 v18, 0x37800000, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v17, v17, v18, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v16, 0x260
	v_cndmask_b32_e32 v16, v17, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_cmp_lt_f32_e32 vcc_lo, v16, v13
	v_cndmask_b32_e32 v9, v9, v5, vcc_lo
	v_add_nc_u32_e32 v5, 1, v5
	v_cndmask_b32_e32 v13, v13, v16, vcc_lo
	v_cmp_ge_i32_e32 vcc_lo, v5, v6
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB15_6
; %bb.7:                                ; %Flow
                                        ;   in Loop: Header=BB15_4 Depth=3
	s_or_b32 exec_lo, exec_lo, s10
.LBB15_8:                               ; %Flow93
                                        ;   in Loop: Header=BB15_4 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
	s_add_i32 s8, s8, 1
	s_cmp_eq_u32 s8, 2
	s_cbranch_scc0 .LBB15_4
; %bb.9:                                ;   in Loop: Header=BB15_3 Depth=2
	s_add_i32 s7, s7, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s7, 2
	s_cbranch_scc0 .LBB15_3
; %bb.10:                               ;   in Loop: Header=BB15_2 Depth=1
	s_add_i32 s1, s1, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s1, 2
	s_cbranch_scc0 .LBB15_2
; %bb.11:                               ; %_Z18computeClosestAtom15HIP_vector_typeIfLj3EES_IiLj3EEPS_IiLj2EEPS_IfLj4EES1_.exit
	v_lshlrev_b64 v[0:1], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s12, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s13, v1, vcc_lo
	global_store_b32 v[0:1], v9, off
.LBB15_12:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z20closestAtomPerVertexPiP15HIP_vector_typeIfLj3EEjS0_IiLj3EES0_IfLj4EES4_PS0_IiLj2EEPS4_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 336
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 22
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end15:
	.size	_Z20closestAtomPerVertexPiP15HIP_vector_typeIfLj3EEjS0_IiLj3EES0_IfLj4EES4_PS0_IiLj2EEPS4_, .Lfunc_end15-_Z20closestAtomPerVertexPiP15HIP_vector_typeIfLj3EEjS0_IiLj3EES0_IfLj4EES4_PS0_IiLj2EEPS4_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 972
; NumSgprs: 22
; NumVgprs: 22
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 22
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z20resetGridValuesSlice15HIP_vector_typeIiLj3EEiS0_Pf ; -- Begin function _Z20resetGridValuesSlice15HIP_vector_typeIiLj3EEiS0_Pf
	.globl	_Z20resetGridValuesSlice15HIP_vector_typeIiLj3EEiS0_Pf
	.p2align	8
	.type	_Z20resetGridValuesSlice15HIP_vector_typeIiLj3EEiS0_Pf,@function
_Z20resetGridValuesSlice15HIP_vector_typeIiLj3EEiS0_Pf: ; @_Z20resetGridValuesSlice15HIP_vector_typeIiLj3EEiS0_Pf
; %bb.0:
	s_clause 0x1
	s_load_b64 s[2:3], s[0:1], 0x34
	s_load_b128 s[4:7], s[0:1], 0x10
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v2, v0, 10, 10
	v_bfe_u32 v7, v0, 20, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s7, s2, 16
	s_and_b32 s2, s2, 0xffff
	v_mad_u64_u32 v[3:4], null, s14, s7, v[2:3]
	v_mad_u64_u32 v[5:6], null, s13, s2, v[1:2]
	s_and_b32 s2, s3, 0xffff
	s_add_i32 s3, s5, -1
	v_mad_u64_u32 v[0:1], null, s15, s2, v[7:8]
	s_add_i32 s2, s4, -1
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_cmp_gt_u32_e32 vcc_lo, s2, v5
	s_delay_alu instid0(VALU_DEP_4)
	v_cmp_gt_u32_e64 s2, s3, v3
	s_add_i32 s3, s6, -1
	s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
	v_cmp_gt_u32_e64 s3, s3, v0
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB16_28
; %bb.1:
	s_load_b128 s[8:11], s[0:1], 0x0
	v_mad_u64_u32 v[6:7], null, v5, s5, v[3:4]
	s_load_b64 s[0:1], s[0:1], 0x20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, v6, s6, v[0:1]
	v_ashrrev_i32_e32 v2, 31, v1
	s_waitcnt lgkmcnt(0)
	s_sub_i32 s2, s4, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s2, v5
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB16_3
; %bb.2:
	v_lshlrev_b64 v[6:7], 2, v[1:2]
	v_mov_b32_e32 v4, 0x3fb33333
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, s0, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
	global_store_b32 v[6:7], v4, off
.LBB16_3:
	s_or_b32 exec_lo, exec_lo, s2
	s_sub_i32 s2, s5, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s2, v3
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB16_5
; %bb.4:
	v_lshlrev_b64 v[6:7], 2, v[1:2]
	v_mov_b32_e32 v4, 0x3fb33333
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, s0, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
	global_store_b32 v[6:7], v4, off
.LBB16_5:
	s_or_b32 exec_lo, exec_lo, s2
	s_sub_i32 s2, s6, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s2, v0
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB16_7
; %bb.6:
	v_lshlrev_b64 v[6:7], 2, v[1:2]
	v_mov_b32_e32 v4, 0x3fb33333
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, s0, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
	global_store_b32 v[6:7], v4, off
.LBB16_7:
	s_or_b32 exec_lo, exec_lo, s2
	s_cmp_eq_u32 s8, 0
	s_mov_b32 s3, 0
	s_cbranch_scc1 .LBB16_9
; %bb.8:
	v_cmp_gt_u32_e32 vcc_lo, s11, v5
	s_and_b32 s2, vcc_lo, exec_lo
	s_branch .LBB16_10
.LBB16_9:
	s_mov_b32 s3, -1
	s_mov_b32 s2, 0
.LBB16_10:                              ; %Flow99
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB16_12
; %bb.11:
	s_lshl_b32 s3, s11, 1
	s_and_not1_b32 s2, s2, exec_lo
	s_sub_i32 s3, s4, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s3, v5
	s_and_b32 s3, vcc_lo, exec_lo
	s_or_b32 s2, s2, s3
.LBB16_12:                              ; %Flow100
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB16_14
; %bb.13:                               ; %.sink.split
	v_lshlrev_b64 v[4:5], 2, v[1:2]
	v_mov_b32_e32 v6, 0x3fb33333
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, s0, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	global_store_b32 v[4:5], v6, off
.LBB16_14:
	s_or_b32 exec_lo, exec_lo, s3
	s_cmp_eq_u32 s9, 0
	s_mov_b32 s3, 0
	s_cbranch_scc1 .LBB16_16
; %bb.15:
	v_cmp_gt_u32_e32 vcc_lo, s11, v3
	s_and_b32 s2, vcc_lo, exec_lo
	s_branch .LBB16_17
.LBB16_16:
	s_mov_b32 s3, -1
	s_mov_b32 s2, 0
.LBB16_17:                              ; %Flow97
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB16_19
; %bb.18:
	s_lshl_b32 s3, s11, 1
	s_and_not1_b32 s2, s2, exec_lo
	s_sub_i32 s3, s5, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s3, v3
	s_and_b32 s3, vcc_lo, exec_lo
	s_or_b32 s2, s2, s3
.LBB16_19:                              ; %Flow98
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB16_21
; %bb.20:                               ; %.sink.split77
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_mov_b32_e32 v5, 0x3fb33333
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	global_store_b32 v[3:4], v5, off
.LBB16_21:
	s_or_b32 exec_lo, exec_lo, s3
	s_cmp_eq_u32 s10, 0
	s_mov_b32 s3, 0
	s_cbranch_scc1 .LBB16_23
; %bb.22:
	v_cmp_gt_u32_e32 vcc_lo, s11, v0
	s_and_b32 s2, vcc_lo, exec_lo
	s_branch .LBB16_24
.LBB16_23:
	s_mov_b32 s3, -1
	s_mov_b32 s2, 0
.LBB16_24:                              ; %Flow
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB16_26
; %bb.25:
	s_lshl_b32 s3, s11, 1
	s_and_not1_b32 s2, s2, exec_lo
	s_sub_i32 s3, s6, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_u32_e32 vcc_lo, s3, v0
	s_and_b32 s3, vcc_lo, exec_lo
	s_or_b32 s2, s2, s3
.LBB16_26:                              ; %Flow95
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB16_28
; %bb.27:                               ; %.sink.split79
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_mov_b32_e32 v2, 0x3fb33333
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB16_28:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z20resetGridValuesSlice15HIP_vector_typeIiLj3EEiS0_Pf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 2
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end16:
	.size	_Z20resetGridValuesSlice15HIP_vector_typeIiLj3EEiS0_Pf, .Lfunc_end16-_Z20resetGridValuesSlice15HIP_vector_typeIiLj3EEiS0_Pf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 780
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 2
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	edgeTable               ; @edgeTable
	.type	edgeTable,@object
	.data
	.globl	edgeTable
	.p2align	4, 0x0
edgeTable:
	.long	0                               ; 0x0
	.long	265                             ; 0x109
	.long	515                             ; 0x203
	.long	778                             ; 0x30a
	.long	1030                            ; 0x406
	.long	1295                            ; 0x50f
	.long	1541                            ; 0x605
	.long	1804                            ; 0x70c
	.long	2060                            ; 0x80c
	.long	2309                            ; 0x905
	.long	2575                            ; 0xa0f
	.long	2822                            ; 0xb06
	.long	3082                            ; 0xc0a
	.long	3331                            ; 0xd03
	.long	3593                            ; 0xe09
	.long	3840                            ; 0xf00
	.long	400                             ; 0x190
	.long	153                             ; 0x99
	.long	915                             ; 0x393
	.long	666                             ; 0x29a
	.long	1430                            ; 0x596
	.long	1183                            ; 0x49f
	.long	1941                            ; 0x795
	.long	1692                            ; 0x69c
	.long	2460                            ; 0x99c
	.long	2197                            ; 0x895
	.long	2975                            ; 0xb9f
	.long	2710                            ; 0xa96
	.long	3482                            ; 0xd9a
	.long	3219                            ; 0xc93
	.long	3993                            ; 0xf99
	.long	3728                            ; 0xe90
	.long	560                             ; 0x230
	.long	825                             ; 0x339
	.long	51                              ; 0x33
	.long	314                             ; 0x13a
	.long	1590                            ; 0x636
	.long	1855                            ; 0x73f
	.long	1077                            ; 0x435
	.long	1340                            ; 0x53c
	.long	2620                            ; 0xa3c
	.long	2869                            ; 0xb35
	.long	2111                            ; 0x83f
	.long	2358                            ; 0x936
	.long	3642                            ; 0xe3a
	.long	3891                            ; 0xf33
	.long	3129                            ; 0xc39
	.long	3376                            ; 0xd30
	.long	928                             ; 0x3a0
	.long	681                             ; 0x2a9
	.long	419                             ; 0x1a3
	.long	170                             ; 0xaa
	.long	1958                            ; 0x7a6
	.long	1711                            ; 0x6af
	.long	1445                            ; 0x5a5
	.long	1196                            ; 0x4ac
	.long	2988                            ; 0xbac
	.long	2725                            ; 0xaa5
	.long	2479                            ; 0x9af
	.long	2214                            ; 0x8a6
	.long	4010                            ; 0xfaa
	.long	3747                            ; 0xea3
	.long	3497                            ; 0xda9
	.long	3232                            ; 0xca0
	.long	1120                            ; 0x460
	.long	1385                            ; 0x569
	.long	1635                            ; 0x663
	.long	1898                            ; 0x76a
	.long	102                             ; 0x66
	.long	367                             ; 0x16f
	.long	613                             ; 0x265
	.long	876                             ; 0x36c
	.long	3180                            ; 0xc6c
	.long	3429                            ; 0xd65
	.long	3695                            ; 0xe6f
	.long	3942                            ; 0xf66
	.long	2154                            ; 0x86a
	.long	2403                            ; 0x963
	.long	2665                            ; 0xa69
	.long	2912                            ; 0xb60
	.long	1520                            ; 0x5f0
	.long	1273                            ; 0x4f9
	.long	2035                            ; 0x7f3
	.long	1786                            ; 0x6fa
	.long	502                             ; 0x1f6
	.long	255                             ; 0xff
	.long	1013                            ; 0x3f5
	.long	764                             ; 0x2fc
	.long	3580                            ; 0xdfc
	.long	3317                            ; 0xcf5
	.long	4095                            ; 0xfff
	.long	3830                            ; 0xef6
	.long	2554                            ; 0x9fa
	.long	2291                            ; 0x8f3
	.long	3065                            ; 0xbf9
	.long	2800                            ; 0xaf0
	.long	1616                            ; 0x650
	.long	1881                            ; 0x759
	.long	1107                            ; 0x453
	.long	1370                            ; 0x55a
	.long	598                             ; 0x256
	.long	863                             ; 0x35f
	.long	85                              ; 0x55
	.long	348                             ; 0x15c
	.long	3676                            ; 0xe5c
	.long	3925                            ; 0xf55
	.long	3167                            ; 0xc5f
	.long	3414                            ; 0xd56
	.long	2650                            ; 0xa5a
	.long	2899                            ; 0xb53
	.long	2137                            ; 0x859
	.long	2384                            ; 0x950
	.long	1984                            ; 0x7c0
	.long	1737                            ; 0x6c9
	.long	1475                            ; 0x5c3
	.long	1226                            ; 0x4ca
	.long	966                             ; 0x3c6
	.long	719                             ; 0x2cf
	.long	453                             ; 0x1c5
	.long	204                             ; 0xcc
	.long	4044                            ; 0xfcc
	.long	3781                            ; 0xec5
	.long	3535                            ; 0xdcf
	.long	3270                            ; 0xcc6
	.long	3018                            ; 0xbca
	.long	2755                            ; 0xac3
	.long	2505                            ; 0x9c9
	.long	2240                            ; 0x8c0
	.long	2240                            ; 0x8c0
	.long	2505                            ; 0x9c9
	.long	2755                            ; 0xac3
	.long	3018                            ; 0xbca
	.long	3270                            ; 0xcc6
	.long	3535                            ; 0xdcf
	.long	3781                            ; 0xec5
	.long	4044                            ; 0xfcc
	.long	204                             ; 0xcc
	.long	453                             ; 0x1c5
	.long	719                             ; 0x2cf
	.long	966                             ; 0x3c6
	.long	1226                            ; 0x4ca
	.long	1475                            ; 0x5c3
	.long	1737                            ; 0x6c9
	.long	1984                            ; 0x7c0
	.long	2384                            ; 0x950
	.long	2137                            ; 0x859
	.long	2899                            ; 0xb53
	.long	2650                            ; 0xa5a
	.long	3414                            ; 0xd56
	.long	3167                            ; 0xc5f
	.long	3925                            ; 0xf55
	.long	3676                            ; 0xe5c
	.long	348                             ; 0x15c
	.long	85                              ; 0x55
	.long	863                             ; 0x35f
	.long	598                             ; 0x256
	.long	1370                            ; 0x55a
	.long	1107                            ; 0x453
	.long	1881                            ; 0x759
	.long	1616                            ; 0x650
	.long	2800                            ; 0xaf0
	.long	3065                            ; 0xbf9
	.long	2291                            ; 0x8f3
	.long	2554                            ; 0x9fa
	.long	3830                            ; 0xef6
	.long	4095                            ; 0xfff
	.long	3317                            ; 0xcf5
	.long	3580                            ; 0xdfc
	.long	764                             ; 0x2fc
	.long	1013                            ; 0x3f5
	.long	255                             ; 0xff
	.long	502                             ; 0x1f6
	.long	1786                            ; 0x6fa
	.long	2035                            ; 0x7f3
	.long	1273                            ; 0x4f9
	.long	1520                            ; 0x5f0
	.long	2912                            ; 0xb60
	.long	2665                            ; 0xa69
	.long	2403                            ; 0x963
	.long	2154                            ; 0x86a
	.long	3942                            ; 0xf66
	.long	3695                            ; 0xe6f
	.long	3429                            ; 0xd65
	.long	3180                            ; 0xc6c
	.long	876                             ; 0x36c
	.long	613                             ; 0x265
	.long	367                             ; 0x16f
	.long	102                             ; 0x66
	.long	1898                            ; 0x76a
	.long	1635                            ; 0x663
	.long	1385                            ; 0x569
	.long	1120                            ; 0x460
	.long	3232                            ; 0xca0
	.long	3497                            ; 0xda9
	.long	3747                            ; 0xea3
	.long	4010                            ; 0xfaa
	.long	2214                            ; 0x8a6
	.long	2479                            ; 0x9af
	.long	2725                            ; 0xaa5
	.long	2988                            ; 0xbac
	.long	1196                            ; 0x4ac
	.long	1445                            ; 0x5a5
	.long	1711                            ; 0x6af
	.long	1958                            ; 0x7a6
	.long	170                             ; 0xaa
	.long	419                             ; 0x1a3
	.long	681                             ; 0x2a9
	.long	928                             ; 0x3a0
	.long	3376                            ; 0xd30
	.long	3129                            ; 0xc39
	.long	3891                            ; 0xf33
	.long	3642                            ; 0xe3a
	.long	2358                            ; 0x936
	.long	2111                            ; 0x83f
	.long	2869                            ; 0xb35
	.long	2620                            ; 0xa3c
	.long	1340                            ; 0x53c
	.long	1077                            ; 0x435
	.long	1855                            ; 0x73f
	.long	1590                            ; 0x636
	.long	314                             ; 0x13a
	.long	51                              ; 0x33
	.long	825                             ; 0x339
	.long	560                             ; 0x230
	.long	3728                            ; 0xe90
	.long	3993                            ; 0xf99
	.long	3219                            ; 0xc93
	.long	3482                            ; 0xd9a
	.long	2710                            ; 0xa96
	.long	2975                            ; 0xb9f
	.long	2197                            ; 0x895
	.long	2460                            ; 0x99c
	.long	1692                            ; 0x69c
	.long	1941                            ; 0x795
	.long	1183                            ; 0x49f
	.long	1430                            ; 0x596
	.long	666                             ; 0x29a
	.long	915                             ; 0x393
	.long	153                             ; 0x99
	.long	400                             ; 0x190
	.long	3840                            ; 0xf00
	.long	3593                            ; 0xe09
	.long	3331                            ; 0xd03
	.long	3082                            ; 0xc0a
	.long	2822                            ; 0xb06
	.long	2575                            ; 0xa0f
	.long	2309                            ; 0x905
	.long	2060                            ; 0x80c
	.long	1804                            ; 0x70c
	.long	1541                            ; 0x605
	.long	1295                            ; 0x50f
	.long	1030                            ; 0x406
	.long	778                             ; 0x30a
	.long	515                             ; 0x203
	.long	265                             ; 0x109
	.long	0                               ; 0x0
	.size	edgeTable, 1024

	.protected	triTable                ; @triTable
	.type	triTable,@object
	.globl	triTable
	.p2align	4, 0x0
triTable:
	.zero	64,255
	.long	0                               ; 0x0
	.long	8                               ; 0x8
	.long	3                               ; 0x3
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	9                               ; 0x9
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	8                               ; 0x8
	.long	3                               ; 0x3
	.long	9                               ; 0x9
	.long	8                               ; 0x8
	.long	1                               ; 0x1
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	2                               ; 0x2
	.long	10                              ; 0xa
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	0                               ; 0x0
	.long	8                               ; 0x8
	.long	3                               ; 0x3
	.long	1                               ; 0x1
	.long	2                               ; 0x2
	.long	10                              ; 0xa
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	9                               ; 0x9
	.long	2                               ; 0x2
	.long	10                              ; 0xa
	.long	0                               ; 0x0
	.long	2                               ; 0x2
	.long	9                               ; 0x9
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	2                               ; 0x2
	.long	8                               ; 0x8
	.long	3                               ; 0x3
	.long	2                               ; 0x2
	.long	10                              ; 0xa
	.long	8                               ; 0x8
	.long	10                              ; 0xa
	.long	9                               ; 0x9
	.long	8                               ; 0x8
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	3                               ; 0x3
	.long	11                              ; 0xb
	.long	2                               ; 0x2
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	0                               ; 0x0
	.long	11                              ; 0xb
	.long	2                               ; 0x2
	.long	8                               ; 0x8
	.long	11                              ; 0xb
	.long	0                               ; 0x0
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	9                               ; 0x9
	.long	0                               ; 0x0
	.long	2                               ; 0x2
	.long	3                               ; 0x3
	.long	11                              ; 0xb
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	11                              ; 0xb
	.long	2                               ; 0x2
	.long	1                               ; 0x1
	.long	9                               ; 0x9
	.long	11                              ; 0xb
	.long	9                               ; 0x9
	.long	8                               ; 0x8
	.long	11                              ; 0xb
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	3                               ; 0x3
	.long	10                              ; 0xa
	.long	1                               ; 0x1
	.long	11                              ; 0xb
	.long	10                              ; 0xa
	.long	3                               ; 0x3
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	0                               ; 0x0
	.long	10                              ; 0xa
	.long	1                               ; 0x1
	.long	0                               ; 0x0
	.long	8                               ; 0x8
	.long	10                              ; 0xa
	.long	8                               ; 0x8
	.long	11                              ; 0xb
	.long	10                              ; 0xa
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	3                               ; 0x3
	.long	9                               ; 0x9
	.long	0                               ; 0x0
	.long	3                               ; 0x3
	.long	11                              ; 0xb
	.long	9                               ; 0x9
	.long	11                              ; 0xb
	.long	10                              ; 0xa
	.long	9                               ; 0x9
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	9                               ; 0x9
	.long	8                               ; 0x8
	.long	10                              ; 0xa
	.long	10                              ; 0xa
	.long	8                               ; 0x8
	.long	11                              ; 0xb
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4                               ; 0x4
	.long	7                               ; 0x7
	.long	8                               ; 0x8
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4                               ; 0x4
	.long	3                               ; 0x3
	.long	0                               ; 0x0
	.long	7                               ; 0x7
	.long	3                               ; 0x3
	.long	4                               ; 0x4
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	9                               ; 0x9
	.long	8                               ; 0x8
	.long	4                               ; 0x4
	.long	7                               ; 0x7
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4                               ; 0x4
	.long	1                               ; 0x1
	.long	9                               ; 0x9
	.long	4                               ; 0x4
	.long	7                               ; 0x7
	.long	1                               ; 0x1
	.long	7                               ; 0x7
	.long	3                               ; 0x3
	.long	1                               ; 0x1
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	2                               ; 0x2
	.long	10                              ; 0xa
	.long	8                               ; 0x8
	.long	4                               ; 0x4
	.long	7                               ; 0x7
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	3                               ; 0x3
	.long	4                               ; 0x4
	.long	7                               ; 0x7
	.long	3                               ; 0x3
	.long	0                               ; 0x0
	.long	4                               ; 0x4
	.long	1                               ; 0x1
	.long	2                               ; 0x2
	.long	10                              ; 0xa
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	9                               ; 0x9
	.long	2                               ; 0x2
	.long	10                              ; 0xa
	.long	9                               ; 0x9
	.long	0                               ; 0x0
	.long	2                               ; 0x2
	.long	8                               ; 0x8
	.long	4                               ; 0x4
	.long	7                               ; 0x7
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	2                               ; 0x2
	.long	10                              ; 0xa
	.long	9                               ; 0x9
	.long	2                               ; 0x2
	.long	9                               ; 0x9
	.long	7                               ; 0x7
	.long	2                               ; 0x2
	.long	7                               ; 0x7
	.long	3                               ; 0x3
	.long	7                               ; 0x7
	.long	9                               ; 0x9
	.long	4                               ; 0x4
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	8                               ; 0x8
	.long	4                               ; 0x4
	.long	7                               ; 0x7
	.long	3                               ; 0x3
	.long	11                              ; 0xb
	.long	2                               ; 0x2
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	11                              ; 0xb
	.long	4                               ; 0x4
	.long	7                               ; 0x7
	.long	11                              ; 0xb
	.long	2                               ; 0x2
	.long	4                               ; 0x4
	.long	2                               ; 0x2
	.long	0                               ; 0x0
	.long	4                               ; 0x4
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	9                               ; 0x9
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	8                               ; 0x8
	.long	4                               ; 0x4
	.long	7                               ; 0x7
	.long	2                               ; 0x2
	.long	3                               ; 0x3
	.long	11                              ; 0xb
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4                               ; 0x4
	.long	7                               ; 0x7
	.long	11                              ; 0xb
	.long	9                               ; 0x9
	.long	4                               ; 0x4
	.long	11                              ; 0xb
	.long	9                               ; 0x9
	.long	11                              ; 0xb
	.long	2                               ; 0x2
	.long	9                               ; 0x9
	.long	2                               ; 0x2
	.long	1                               ; 0x1
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	3                               ; 0x3
	.long	10                              ; 0xa
	.long	1                               ; 0x1
	.long	3                               ; 0x3
	.long	11                              ; 0xb
	.long	10                              ; 0xa
	.long	7                               ; 0x7
	.long	8                               ; 0x8
	.long	4                               ; 0x4
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	11                              ; 0xb
	.long	10                              ; 0xa
	.long	1                               ; 0x1
	.long	4                               ; 0x4
	.long	11                              ; 0xb
	.long	1                               ; 0x1
	.long	0                               ; 0x0
	.long	4                               ; 0x4
	.long	7                               ; 0x7
	.long	11                              ; 0xb
	.long	4                               ; 0x4
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4                               ; 0x4
	.long	7                               ; 0x7
	.long	8                               ; 0x8
	.long	9                               ; 0x9
	.long	0                               ; 0x0
	.long	11                              ; 0xb
	.long	9                               ; 0x9
	.long	11                              ; 0xb
	.long	10                              ; 0xa
	.long	11                              ; 0xb
	.long	0                               ; 0x0
	.long	3                               ; 0x3
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4                               ; 0x4
	.long	7                               ; 0x7
	.long	11                              ; 0xb
	.long	4                               ; 0x4
	.long	11                              ; 0xb
	.long	9                               ; 0x9
	.long	9                               ; 0x9
	.long	11                              ; 0xb
	.long	10                              ; 0xa
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	9                               ; 0x9
	.long	5                               ; 0x5
	.long	4                               ; 0x4
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	9                               ; 0x9
	.long	5                               ; 0x5
	.long	4                               ; 0x4
	.long	0                               ; 0x0
	.long	8                               ; 0x8
	.long	3                               ; 0x3
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	0                               ; 0x0
	.long	5                               ; 0x5
	.long	4                               ; 0x4
	.long	1                               ; 0x1
	.long	5                               ; 0x5
	.long	0                               ; 0x0
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	8                               ; 0x8
	.long	5                               ; 0x5
	.long	4                               ; 0x4
	.long	8                               ; 0x8
	.long	3                               ; 0x3
	.long	5                               ; 0x5
	.long	3                               ; 0x3
	.long	1                               ; 0x1
	.long	5                               ; 0x5
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	2                               ; 0x2
	.long	10                              ; 0xa
	.long	9                               ; 0x9
	.long	5                               ; 0x5
	.long	4                               ; 0x4
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	3                               ; 0x3
	.long	0                               ; 0x0
	.long	8                               ; 0x8
	.long	1                               ; 0x1
	.long	2                               ; 0x2
	.long	10                              ; 0xa
	.long	4                               ; 0x4
	.long	9                               ; 0x9
	.long	5                               ; 0x5
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	5                               ; 0x5
	.long	2                               ; 0x2
	.long	10                              ; 0xa
	.long	5                               ; 0x5
	.long	4                               ; 0x4
	.long	2                               ; 0x2
	.long	4                               ; 0x4
	.long	0                               ; 0x0
	.long	2                               ; 0x2
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	2                               ; 0x2
	.long	10                              ; 0xa
	.long	5                               ; 0x5
	.long	3                               ; 0x3
	.long	2                               ; 0x2
	.long	5                               ; 0x5
	.long	3                               ; 0x3
	.long	5                               ; 0x5
	.long	4                               ; 0x4
	.long	3                               ; 0x3
	.long	4                               ; 0x4
	.long	8                               ; 0x8
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	9                               ; 0x9
	.long	5                               ; 0x5
	.long	4                               ; 0x4
	.long	2                               ; 0x2
	.long	3                               ; 0x3
	.long	11                              ; 0xb
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	0                               ; 0x0
	.long	11                              ; 0xb
	.long	2                               ; 0x2
	.long	0                               ; 0x0
	.long	8                               ; 0x8
	.long	11                              ; 0xb
	.long	4                               ; 0x4
	.long	9                               ; 0x9
	.long	5                               ; 0x5
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	0                               ; 0x0
	.long	5                               ; 0x5
	.long	4                               ; 0x4
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	5                               ; 0x5
	.long	2                               ; 0x2
	.long	3                               ; 0x3
	.long	11                              ; 0xb
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	2                               ; 0x2
	.long	1                               ; 0x1
	.long	5                               ; 0x5
	.long	2                               ; 0x2
	.long	5                               ; 0x5
	.long	8                               ; 0x8
	.long	2                               ; 0x2
	.long	8                               ; 0x8
	.long	11                              ; 0xb
	.long	4                               ; 0x4
	.long	8                               ; 0x8
	.long	5                               ; 0x5
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	10                              ; 0xa
	.long	3                               ; 0x3
	.long	11                              ; 0xb
	.long	10                              ; 0xa
	.long	1                               ; 0x1
	.long	3                               ; 0x3
	.long	9                               ; 0x9
	.long	5                               ; 0x5
	.long	4                               ; 0x4
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4                               ; 0x4
	.long	9                               ; 0x9
	.long	5                               ; 0x5
	.long	0                               ; 0x0
	.long	8                               ; 0x8
	.long	1                               ; 0x1
	.long	8                               ; 0x8
	.long	10                              ; 0xa
	.long	1                               ; 0x1
	.long	8                               ; 0x8
	.long	11                              ; 0xb
	.long	10                              ; 0xa
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	5                               ; 0x5
	.long	4                               ; 0x4
	.long	0                               ; 0x0
	.long	5                               ; 0x5
	.long	0                               ; 0x0
	.long	11                              ; 0xb
	.long	5                               ; 0x5
	.long	11                              ; 0xb
	.long	10                              ; 0xa
	.long	11                              ; 0xb
	.long	0                               ; 0x0
	.long	3                               ; 0x3
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	5                               ; 0x5
	.long	4                               ; 0x4
	.long	8                               ; 0x8
	.long	5                               ; 0x5
	.long	8                               ; 0x8
	.long	10                              ; 0xa
	.long	10                              ; 0xa
	.long	8                               ; 0x8
	.long	11                              ; 0xb
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	9                               ; 0x9
	.long	7                               ; 0x7
	.long	8                               ; 0x8
	.long	5                               ; 0x5
	.long	7                               ; 0x7
	.long	9                               ; 0x9
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	9                               ; 0x9
	.long	3                               ; 0x3
	.long	0                               ; 0x0
	.long	9                               ; 0x9
	.long	5                               ; 0x5
	.long	3                               ; 0x3
	.long	5                               ; 0x5
	.long	7                               ; 0x7
	.long	3                               ; 0x3
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	0                               ; 0x0
	.long	7                               ; 0x7
	.long	8                               ; 0x8
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	7                               ; 0x7
	.long	1                               ; 0x1
	.long	5                               ; 0x5
	.long	7                               ; 0x7
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	5                               ; 0x5
	.long	3                               ; 0x3
	.long	3                               ; 0x3
	.long	5                               ; 0x5
	.long	7                               ; 0x7
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	9                               ; 0x9
	.long	7                               ; 0x7
	.long	8                               ; 0x8
	.long	9                               ; 0x9
	.long	5                               ; 0x5
	.long	7                               ; 0x7
	.long	10                              ; 0xa
	.long	1                               ; 0x1
	.long	2                               ; 0x2
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	10                              ; 0xa
	.long	1                               ; 0x1
	.long	2                               ; 0x2
	.long	9                               ; 0x9
	.long	5                               ; 0x5
	.long	0                               ; 0x0
	.long	5                               ; 0x5
	.long	3                               ; 0x3
	.long	0                               ; 0x0
	.long	5                               ; 0x5
	.long	7                               ; 0x7
	.long	3                               ; 0x3
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	8                               ; 0x8
	.long	0                               ; 0x0
	.long	2                               ; 0x2
	.long	8                               ; 0x8
	.long	2                               ; 0x2
	.long	5                               ; 0x5
	.long	8                               ; 0x8
	.long	5                               ; 0x5
	.long	7                               ; 0x7
	.long	10                              ; 0xa
	.long	5                               ; 0x5
	.long	2                               ; 0x2
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	2                               ; 0x2
	.long	10                              ; 0xa
	.long	5                               ; 0x5
	.long	2                               ; 0x2
	.long	5                               ; 0x5
	.long	3                               ; 0x3
	.long	3                               ; 0x3
	.long	5                               ; 0x5
	.long	7                               ; 0x7
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	7                               ; 0x7
	.long	9                               ; 0x9
	.long	5                               ; 0x5
	.long	7                               ; 0x7
	.long	8                               ; 0x8
	.long	9                               ; 0x9
	.long	3                               ; 0x3
	.long	11                              ; 0xb
	.long	2                               ; 0x2
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	9                               ; 0x9
	.long	5                               ; 0x5
	.long	7                               ; 0x7
	.long	9                               ; 0x9
	.long	7                               ; 0x7
	.long	2                               ; 0x2
	.long	9                               ; 0x9
	.long	2                               ; 0x2
	.long	0                               ; 0x0
	.long	2                               ; 0x2
	.long	7                               ; 0x7
	.long	11                              ; 0xb
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	2                               ; 0x2
	.long	3                               ; 0x3
	.long	11                              ; 0xb
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	8                               ; 0x8
	.long	1                               ; 0x1
	.long	7                               ; 0x7
	.long	8                               ; 0x8
	.long	1                               ; 0x1
	.long	5                               ; 0x5
	.long	7                               ; 0x7
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	11                              ; 0xb
	.long	2                               ; 0x2
	.long	1                               ; 0x1
	.long	11                              ; 0xb
	.long	1                               ; 0x1
	.long	7                               ; 0x7
	.long	7                               ; 0x7
	.long	1                               ; 0x1
	.long	5                               ; 0x5
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	9                               ; 0x9
	.long	5                               ; 0x5
	.long	8                               ; 0x8
	.long	8                               ; 0x8
	.long	5                               ; 0x5
	.long	7                               ; 0x7
	.long	10                              ; 0xa
	.long	1                               ; 0x1
	.long	3                               ; 0x3
	.long	10                              ; 0xa
	.long	3                               ; 0x3
	.long	11                              ; 0xb
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	5                               ; 0x5
	.long	7                               ; 0x7
	.long	0                               ; 0x0
	.long	5                               ; 0x5
	.long	0                               ; 0x0
	.long	9                               ; 0x9
	.long	7                               ; 0x7
	.long	11                              ; 0xb
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	0                               ; 0x0
	.long	10                              ; 0xa
	.long	11                              ; 0xb
	.long	10                              ; 0xa
	.long	0                               ; 0x0
	.long	4294967295                      ; 0xffffffff
	.long	11                              ; 0xb
	.long	10                              ; 0xa
	.long	0                               ; 0x0
	.long	11                              ; 0xb
	.long	0                               ; 0x0
	.long	3                               ; 0x3
	.long	10                              ; 0xa
	.long	5                               ; 0x5
	.long	0                               ; 0x0
	.long	8                               ; 0x8
	.long	0                               ; 0x0
	.long	7                               ; 0x7
	.long	5                               ; 0x5
	.long	7                               ; 0x7
	.long	0                               ; 0x0
	.long	4294967295                      ; 0xffffffff
	.long	11                              ; 0xb
	.long	10                              ; 0xa
	.long	5                               ; 0x5
	.long	7                               ; 0x7
	.long	11                              ; 0xb
	.long	5                               ; 0x5
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	10                              ; 0xa
	.long	6                               ; 0x6
	.long	5                               ; 0x5
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	0                               ; 0x0
	.long	8                               ; 0x8
	.long	3                               ; 0x3
	.long	5                               ; 0x5
	.long	10                              ; 0xa
	.long	6                               ; 0x6
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	9                               ; 0x9
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	5                               ; 0x5
	.long	10                              ; 0xa
	.long	6                               ; 0x6
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	8                               ; 0x8
	.long	3                               ; 0x3
	.long	1                               ; 0x1
	.long	9                               ; 0x9
	.long	8                               ; 0x8
	.long	5                               ; 0x5
	.long	10                              ; 0xa
	.long	6                               ; 0x6
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	6                               ; 0x6
	.long	5                               ; 0x5
	.long	2                               ; 0x2
	.long	6                               ; 0x6
	.long	1                               ; 0x1
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	6                               ; 0x6
	.long	5                               ; 0x5
	.long	1                               ; 0x1
	.long	2                               ; 0x2
	.long	6                               ; 0x6
	.long	3                               ; 0x3
	.long	0                               ; 0x0
	.long	8                               ; 0x8
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	9                               ; 0x9
	.long	6                               ; 0x6
	.long	5                               ; 0x5
	.long	9                               ; 0x9
	.long	0                               ; 0x0
	.long	6                               ; 0x6
	.long	0                               ; 0x0
	.long	2                               ; 0x2
	.long	6                               ; 0x6
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	5                               ; 0x5
	.long	9                               ; 0x9
	.long	8                               ; 0x8
	.long	5                               ; 0x5
	.long	8                               ; 0x8
	.long	2                               ; 0x2
	.long	5                               ; 0x5
	.long	2                               ; 0x2
	.long	6                               ; 0x6
	.long	3                               ; 0x3
	.long	2                               ; 0x2
	.long	8                               ; 0x8
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	2                               ; 0x2
	.long	3                               ; 0x3
	.long	11                              ; 0xb
	.long	10                              ; 0xa
	.long	6                               ; 0x6
	.long	5                               ; 0x5
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	11                              ; 0xb
	.long	0                               ; 0x0
	.long	8                               ; 0x8
	.long	11                              ; 0xb
	.long	2                               ; 0x2
	.long	0                               ; 0x0
	.long	10                              ; 0xa
	.long	6                               ; 0x6
	.long	5                               ; 0x5
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	9                               ; 0x9
	.long	2                               ; 0x2
	.long	3                               ; 0x3
	.long	11                              ; 0xb
	.long	5                               ; 0x5
	.long	10                              ; 0xa
	.long	6                               ; 0x6
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	5                               ; 0x5
	.long	10                              ; 0xa
	.long	6                               ; 0x6
	.long	1                               ; 0x1
	.long	9                               ; 0x9
	.long	2                               ; 0x2
	.long	9                               ; 0x9
	.long	11                              ; 0xb
	.long	2                               ; 0x2
	.long	9                               ; 0x9
	.long	8                               ; 0x8
	.long	11                              ; 0xb
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	6                               ; 0x6
	.long	3                               ; 0x3
	.long	11                              ; 0xb
	.long	6                               ; 0x6
	.long	5                               ; 0x5
	.long	3                               ; 0x3
	.long	5                               ; 0x5
	.long	1                               ; 0x1
	.long	3                               ; 0x3
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	0                               ; 0x0
	.long	8                               ; 0x8
	.long	11                              ; 0xb
	.long	0                               ; 0x0
	.long	11                              ; 0xb
	.long	5                               ; 0x5
	.long	0                               ; 0x0
	.long	5                               ; 0x5
	.long	1                               ; 0x1
	.long	5                               ; 0x5
	.long	11                              ; 0xb
	.long	6                               ; 0x6
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	3                               ; 0x3
	.long	11                              ; 0xb
	.long	6                               ; 0x6
	.long	0                               ; 0x0
	.long	3                               ; 0x3
	.long	6                               ; 0x6
	.long	0                               ; 0x0
	.long	6                               ; 0x6
	.long	5                               ; 0x5
	.long	0                               ; 0x0
	.long	5                               ; 0x5
	.long	9                               ; 0x9
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	6                               ; 0x6
	.long	5                               ; 0x5
	.long	9                               ; 0x9
	.long	6                               ; 0x6
	.long	9                               ; 0x9
	.long	11                              ; 0xb
	.long	11                              ; 0xb
	.long	9                               ; 0x9
	.long	8                               ; 0x8
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	5                               ; 0x5
	.long	10                              ; 0xa
	.long	6                               ; 0x6
	.long	4                               ; 0x4
	.long	7                               ; 0x7
	.long	8                               ; 0x8
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4                               ; 0x4
	.long	3                               ; 0x3
	.long	0                               ; 0x0
	.long	4                               ; 0x4
	.long	7                               ; 0x7
	.long	3                               ; 0x3
	.long	6                               ; 0x6
	.long	5                               ; 0x5
	.long	10                              ; 0xa
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	9                               ; 0x9
	.long	0                               ; 0x0
	.long	5                               ; 0x5
	.long	10                              ; 0xa
	.long	6                               ; 0x6
	.long	8                               ; 0x8
	.long	4                               ; 0x4
	.long	7                               ; 0x7
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	10                              ; 0xa
	.long	6                               ; 0x6
	.long	5                               ; 0x5
	.long	1                               ; 0x1
	.long	9                               ; 0x9
	.long	7                               ; 0x7
	.long	1                               ; 0x1
	.long	7                               ; 0x7
	.long	3                               ; 0x3
	.long	7                               ; 0x7
	.long	9                               ; 0x9
	.long	4                               ; 0x4
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	6                               ; 0x6
	.long	1                               ; 0x1
	.long	2                               ; 0x2
	.long	6                               ; 0x6
	.long	5                               ; 0x5
	.long	1                               ; 0x1
	.long	4                               ; 0x4
	.long	7                               ; 0x7
	.long	8                               ; 0x8
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	2                               ; 0x2
	.long	5                               ; 0x5
	.long	5                               ; 0x5
	.long	2                               ; 0x2
	.long	6                               ; 0x6
	.long	3                               ; 0x3
	.long	0                               ; 0x0
	.long	4                               ; 0x4
	.long	3                               ; 0x3
	.long	4                               ; 0x4
	.long	7                               ; 0x7
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	8                               ; 0x8
	.long	4                               ; 0x4
	.long	7                               ; 0x7
	.long	9                               ; 0x9
	.long	0                               ; 0x0
	.long	5                               ; 0x5
	.long	0                               ; 0x0
	.long	6                               ; 0x6
	.long	5                               ; 0x5
	.long	0                               ; 0x0
	.long	2                               ; 0x2
	.long	6                               ; 0x6
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	7                               ; 0x7
	.long	3                               ; 0x3
	.long	9                               ; 0x9
	.long	7                               ; 0x7
	.long	9                               ; 0x9
	.long	4                               ; 0x4
	.long	3                               ; 0x3
	.long	2                               ; 0x2
	.long	9                               ; 0x9
	.long	5                               ; 0x5
	.long	9                               ; 0x9
	.long	6                               ; 0x6
	.long	2                               ; 0x2
	.long	6                               ; 0x6
	.long	9                               ; 0x9
	.long	4294967295                      ; 0xffffffff
	.long	3                               ; 0x3
	.long	11                              ; 0xb
	.long	2                               ; 0x2
	.long	7                               ; 0x7
	.long	8                               ; 0x8
	.long	4                               ; 0x4
	.long	10                              ; 0xa
	.long	6                               ; 0x6
	.long	5                               ; 0x5
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	5                               ; 0x5
	.long	10                              ; 0xa
	.long	6                               ; 0x6
	.long	4                               ; 0x4
	.long	7                               ; 0x7
	.long	2                               ; 0x2
	.long	4                               ; 0x4
	.long	2                               ; 0x2
	.long	0                               ; 0x0
	.long	2                               ; 0x2
	.long	7                               ; 0x7
	.long	11                              ; 0xb
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	9                               ; 0x9
	.long	4                               ; 0x4
	.long	7                               ; 0x7
	.long	8                               ; 0x8
	.long	2                               ; 0x2
	.long	3                               ; 0x3
	.long	11                              ; 0xb
	.long	5                               ; 0x5
	.long	10                              ; 0xa
	.long	6                               ; 0x6
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	9                               ; 0x9
	.long	2                               ; 0x2
	.long	1                               ; 0x1
	.long	9                               ; 0x9
	.long	11                              ; 0xb
	.long	2                               ; 0x2
	.long	9                               ; 0x9
	.long	4                               ; 0x4
	.long	11                              ; 0xb
	.long	7                               ; 0x7
	.long	11                              ; 0xb
	.long	4                               ; 0x4
	.long	5                               ; 0x5
	.long	10                              ; 0xa
	.long	6                               ; 0x6
	.long	4294967295                      ; 0xffffffff
	.long	8                               ; 0x8
	.long	4                               ; 0x4
	.long	7                               ; 0x7
	.long	3                               ; 0x3
	.long	11                              ; 0xb
	.long	5                               ; 0x5
	.long	3                               ; 0x3
	.long	5                               ; 0x5
	.long	1                               ; 0x1
	.long	5                               ; 0x5
	.long	11                              ; 0xb
	.long	6                               ; 0x6
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	5                               ; 0x5
	.long	1                               ; 0x1
	.long	11                              ; 0xb
	.long	5                               ; 0x5
	.long	11                              ; 0xb
	.long	6                               ; 0x6
	.long	1                               ; 0x1
	.long	0                               ; 0x0
	.long	11                              ; 0xb
	.long	7                               ; 0x7
	.long	11                              ; 0xb
	.long	4                               ; 0x4
	.long	0                               ; 0x0
	.long	4                               ; 0x4
	.long	11                              ; 0xb
	.long	4294967295                      ; 0xffffffff
	.long	0                               ; 0x0
	.long	5                               ; 0x5
	.long	9                               ; 0x9
	.long	0                               ; 0x0
	.long	6                               ; 0x6
	.long	5                               ; 0x5
	.long	0                               ; 0x0
	.long	3                               ; 0x3
	.long	6                               ; 0x6
	.long	11                              ; 0xb
	.long	6                               ; 0x6
	.long	3                               ; 0x3
	.long	8                               ; 0x8
	.long	4                               ; 0x4
	.long	7                               ; 0x7
	.long	4294967295                      ; 0xffffffff
	.long	6                               ; 0x6
	.long	5                               ; 0x5
	.long	9                               ; 0x9
	.long	6                               ; 0x6
	.long	9                               ; 0x9
	.long	11                              ; 0xb
	.long	4                               ; 0x4
	.long	7                               ; 0x7
	.long	9                               ; 0x9
	.long	7                               ; 0x7
	.long	11                              ; 0xb
	.long	9                               ; 0x9
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	10                              ; 0xa
	.long	4                               ; 0x4
	.long	9                               ; 0x9
	.long	6                               ; 0x6
	.long	4                               ; 0x4
	.long	10                              ; 0xa
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4                               ; 0x4
	.long	10                              ; 0xa
	.long	6                               ; 0x6
	.long	4                               ; 0x4
	.long	9                               ; 0x9
	.long	10                              ; 0xa
	.long	0                               ; 0x0
	.long	8                               ; 0x8
	.long	3                               ; 0x3
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	10                              ; 0xa
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	10                              ; 0xa
	.long	6                               ; 0x6
	.long	0                               ; 0x0
	.long	6                               ; 0x6
	.long	4                               ; 0x4
	.long	0                               ; 0x0
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	8                               ; 0x8
	.long	3                               ; 0x3
	.long	1                               ; 0x1
	.long	8                               ; 0x8
	.long	1                               ; 0x1
	.long	6                               ; 0x6
	.long	8                               ; 0x8
	.long	6                               ; 0x6
	.long	4                               ; 0x4
	.long	6                               ; 0x6
	.long	1                               ; 0x1
	.long	10                              ; 0xa
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	4                               ; 0x4
	.long	9                               ; 0x9
	.long	1                               ; 0x1
	.long	2                               ; 0x2
	.long	4                               ; 0x4
	.long	2                               ; 0x2
	.long	6                               ; 0x6
	.long	4                               ; 0x4
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	3                               ; 0x3
	.long	0                               ; 0x0
	.long	8                               ; 0x8
	.long	1                               ; 0x1
	.long	2                               ; 0x2
	.long	9                               ; 0x9
	.long	2                               ; 0x2
	.long	4                               ; 0x4
	.long	9                               ; 0x9
	.long	2                               ; 0x2
	.long	6                               ; 0x6
	.long	4                               ; 0x4
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	0                               ; 0x0
	.long	2                               ; 0x2
	.long	4                               ; 0x4
	.long	4                               ; 0x4
	.long	2                               ; 0x2
	.long	6                               ; 0x6
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	8                               ; 0x8
	.long	3                               ; 0x3
	.long	2                               ; 0x2
	.long	8                               ; 0x8
	.long	2                               ; 0x2
	.long	4                               ; 0x4
	.long	4                               ; 0x4
	.long	2                               ; 0x2
	.long	6                               ; 0x6
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	10                              ; 0xa
	.long	4                               ; 0x4
	.long	9                               ; 0x9
	.long	10                              ; 0xa
	.long	6                               ; 0x6
	.long	4                               ; 0x4
	.long	11                              ; 0xb
	.long	2                               ; 0x2
	.long	3                               ; 0x3
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	0                               ; 0x0
	.long	8                               ; 0x8
	.long	2                               ; 0x2
	.long	2                               ; 0x2
	.long	8                               ; 0x8
	.long	11                              ; 0xb
	.long	4                               ; 0x4
	.long	9                               ; 0x9
	.long	10                              ; 0xa
	.long	4                               ; 0x4
	.long	10                              ; 0xa
	.long	6                               ; 0x6
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	3                               ; 0x3
	.long	11                              ; 0xb
	.long	2                               ; 0x2
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	6                               ; 0x6
	.long	0                               ; 0x0
	.long	6                               ; 0x6
	.long	4                               ; 0x4
	.long	6                               ; 0x6
	.long	1                               ; 0x1
	.long	10                              ; 0xa
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	6                               ; 0x6
	.long	4                               ; 0x4
	.long	1                               ; 0x1
	.long	6                               ; 0x6
	.long	1                               ; 0x1
	.long	10                              ; 0xa
	.long	4                               ; 0x4
	.long	8                               ; 0x8
	.long	1                               ; 0x1
	.long	2                               ; 0x2
	.long	1                               ; 0x1
	.long	11                              ; 0xb
	.long	8                               ; 0x8
	.long	11                              ; 0xb
	.long	1                               ; 0x1
	.long	4294967295                      ; 0xffffffff
	.long	9                               ; 0x9
	.long	6                               ; 0x6
	.long	4                               ; 0x4
	.long	9                               ; 0x9
	.long	3                               ; 0x3
	.long	6                               ; 0x6
	.long	9                               ; 0x9
	.long	1                               ; 0x1
	.long	3                               ; 0x3
	.long	11                              ; 0xb
	.long	6                               ; 0x6
	.long	3                               ; 0x3
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	8                               ; 0x8
	.long	11                              ; 0xb
	.long	1                               ; 0x1
	.long	8                               ; 0x8
	.long	1                               ; 0x1
	.long	0                               ; 0x0
	.long	11                              ; 0xb
	.long	6                               ; 0x6
	.long	1                               ; 0x1
	.long	9                               ; 0x9
	.long	1                               ; 0x1
	.long	4                               ; 0x4
	.long	6                               ; 0x6
	.long	4                               ; 0x4
	.long	1                               ; 0x1
	.long	4294967295                      ; 0xffffffff
	.long	3                               ; 0x3
	.long	11                              ; 0xb
	.long	6                               ; 0x6
	.long	3                               ; 0x3
	.long	6                               ; 0x6
	.long	0                               ; 0x0
	.long	0                               ; 0x0
	.long	6                               ; 0x6
	.long	4                               ; 0x4
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	6                               ; 0x6
	.long	4                               ; 0x4
	.long	8                               ; 0x8
	.long	11                              ; 0xb
	.long	6                               ; 0x6
	.long	8                               ; 0x8
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	7                               ; 0x7
	.long	10                              ; 0xa
	.long	6                               ; 0x6
	.long	7                               ; 0x7
	.long	8                               ; 0x8
	.long	10                              ; 0xa
	.long	8                               ; 0x8
	.long	9                               ; 0x9
	.long	10                              ; 0xa
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	0                               ; 0x0
	.long	7                               ; 0x7
	.long	3                               ; 0x3
	.long	0                               ; 0x0
	.long	10                              ; 0xa
	.long	7                               ; 0x7
	.long	0                               ; 0x0
	.long	9                               ; 0x9
	.long	10                              ; 0xa
	.long	6                               ; 0x6
	.long	7                               ; 0x7
	.long	10                              ; 0xa
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	10                              ; 0xa
	.long	6                               ; 0x6
	.long	7                               ; 0x7
	.long	1                               ; 0x1
	.long	10                              ; 0xa
	.long	7                               ; 0x7
	.long	1                               ; 0x1
	.long	7                               ; 0x7
	.long	8                               ; 0x8
	.long	1                               ; 0x1
	.long	8                               ; 0x8
	.long	0                               ; 0x0
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	10                              ; 0xa
	.long	6                               ; 0x6
	.long	7                               ; 0x7
	.long	10                              ; 0xa
	.long	7                               ; 0x7
	.long	1                               ; 0x1
	.long	1                               ; 0x1
	.long	7                               ; 0x7
	.long	3                               ; 0x3
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	2                               ; 0x2
	.long	6                               ; 0x6
	.long	1                               ; 0x1
	.long	6                               ; 0x6
	.long	8                               ; 0x8
	.long	1                               ; 0x1
	.long	8                               ; 0x8
	.long	9                               ; 0x9
	.long	8                               ; 0x8
	.long	6                               ; 0x6
	.long	7                               ; 0x7
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	2                               ; 0x2
	.long	6                               ; 0x6
	.long	9                               ; 0x9
	.long	2                               ; 0x2
	.long	9                               ; 0x9
	.long	1                               ; 0x1
	.long	6                               ; 0x6
	.long	7                               ; 0x7
	.long	9                               ; 0x9
	.long	0                               ; 0x0
	.long	9                               ; 0x9
	.long	3                               ; 0x3
	.long	7                               ; 0x7
	.long	3                               ; 0x3
	.long	9                               ; 0x9
	.long	4294967295                      ; 0xffffffff
	.long	7                               ; 0x7
	.long	8                               ; 0x8
	.long	0                               ; 0x0
	.long	7                               ; 0x7
	.long	0                               ; 0x0
	.long	6                               ; 0x6
	.long	6                               ; 0x6
	.long	0                               ; 0x0
	.long	2                               ; 0x2
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	7                               ; 0x7
	.long	3                               ; 0x3
	.long	2                               ; 0x2
	.long	6                               ; 0x6
	.long	7                               ; 0x7
	.long	2                               ; 0x2
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	2                               ; 0x2
	.long	3                               ; 0x3
	.long	11                              ; 0xb
	.long	10                              ; 0xa
	.long	6                               ; 0x6
	.long	8                               ; 0x8
	.long	10                              ; 0xa
	.long	8                               ; 0x8
	.long	9                               ; 0x9
	.long	8                               ; 0x8
	.long	6                               ; 0x6
	.long	7                               ; 0x7
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	2                               ; 0x2
	.long	0                               ; 0x0
	.long	7                               ; 0x7
	.long	2                               ; 0x2
	.long	7                               ; 0x7
	.long	11                              ; 0xb
	.long	0                               ; 0x0
	.long	9                               ; 0x9
	.long	7                               ; 0x7
	.long	6                               ; 0x6
	.long	7                               ; 0x7
	.long	10                              ; 0xa
	.long	9                               ; 0x9
	.long	10                              ; 0xa
	.long	7                               ; 0x7
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	8                               ; 0x8
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	7                               ; 0x7
	.long	8                               ; 0x8
	.long	1                               ; 0x1
	.long	10                              ; 0xa
	.long	7                               ; 0x7
	.long	6                               ; 0x6
	.long	7                               ; 0x7
	.long	10                              ; 0xa
	.long	2                               ; 0x2
	.long	3                               ; 0x3
	.long	11                              ; 0xb
	.long	4294967295                      ; 0xffffffff
	.long	11                              ; 0xb
	.long	2                               ; 0x2
	.long	1                               ; 0x1
	.long	11                              ; 0xb
	.long	1                               ; 0x1
	.long	7                               ; 0x7
	.long	10                              ; 0xa
	.long	6                               ; 0x6
	.long	1                               ; 0x1
	.long	6                               ; 0x6
	.long	7                               ; 0x7
	.long	1                               ; 0x1
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	8                               ; 0x8
	.long	9                               ; 0x9
	.long	6                               ; 0x6
	.long	8                               ; 0x8
	.long	6                               ; 0x6
	.long	7                               ; 0x7
	.long	9                               ; 0x9
	.long	1                               ; 0x1
	.long	6                               ; 0x6
	.long	11                              ; 0xb
	.long	6                               ; 0x6
	.long	3                               ; 0x3
	.long	1                               ; 0x1
	.long	3                               ; 0x3
	.long	6                               ; 0x6
	.long	4294967295                      ; 0xffffffff
	.long	0                               ; 0x0
	.long	9                               ; 0x9
	.long	1                               ; 0x1
	.long	11                              ; 0xb
	.long	6                               ; 0x6
	.long	7                               ; 0x7
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	7                               ; 0x7
	.long	8                               ; 0x8
	.long	0                               ; 0x0
	.long	7                               ; 0x7
	.long	0                               ; 0x0
	.long	6                               ; 0x6
	.long	3                               ; 0x3
	.long	11                              ; 0xb
	.long	0                               ; 0x0
	.long	11                              ; 0xb
	.long	6                               ; 0x6
	.long	0                               ; 0x0
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	7                               ; 0x7
	.long	11                              ; 0xb
	.long	6                               ; 0x6
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	7                               ; 0x7
	.long	6                               ; 0x6
	.long	11                              ; 0xb
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	3                               ; 0x3
	.long	0                               ; 0x0
	.long	8                               ; 0x8
	.long	11                              ; 0xb
	.long	7                               ; 0x7
	.long	6                               ; 0x6
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	9                               ; 0x9
	.long	11                              ; 0xb
	.long	7                               ; 0x7
	.long	6                               ; 0x6
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	8                               ; 0x8
	.long	1                               ; 0x1
	.long	9                               ; 0x9
	.long	8                               ; 0x8
	.long	3                               ; 0x3
	.long	1                               ; 0x1
	.long	11                              ; 0xb
	.long	7                               ; 0x7
	.long	6                               ; 0x6
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	10                              ; 0xa
	.long	1                               ; 0x1
	.long	2                               ; 0x2
	.long	6                               ; 0x6
	.long	11                              ; 0xb
	.long	7                               ; 0x7
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	2                               ; 0x2
	.long	10                              ; 0xa
	.long	3                               ; 0x3
	.long	0                               ; 0x0
	.long	8                               ; 0x8
	.long	6                               ; 0x6
	.long	11                              ; 0xb
	.long	7                               ; 0x7
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	2                               ; 0x2
	.long	9                               ; 0x9
	.long	0                               ; 0x0
	.long	2                               ; 0x2
	.long	10                              ; 0xa
	.long	9                               ; 0x9
	.long	6                               ; 0x6
	.long	11                              ; 0xb
	.long	7                               ; 0x7
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	6                               ; 0x6
	.long	11                              ; 0xb
	.long	7                               ; 0x7
	.long	2                               ; 0x2
	.long	10                              ; 0xa
	.long	3                               ; 0x3
	.long	10                              ; 0xa
	.long	8                               ; 0x8
	.long	3                               ; 0x3
	.long	10                              ; 0xa
	.long	9                               ; 0x9
	.long	8                               ; 0x8
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	7                               ; 0x7
	.long	2                               ; 0x2
	.long	3                               ; 0x3
	.long	6                               ; 0x6
	.long	2                               ; 0x2
	.long	7                               ; 0x7
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	7                               ; 0x7
	.long	0                               ; 0x0
	.long	8                               ; 0x8
	.long	7                               ; 0x7
	.long	6                               ; 0x6
	.long	0                               ; 0x0
	.long	6                               ; 0x6
	.long	2                               ; 0x2
	.long	0                               ; 0x0
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	2                               ; 0x2
	.long	7                               ; 0x7
	.long	6                               ; 0x6
	.long	2                               ; 0x2
	.long	3                               ; 0x3
	.long	7                               ; 0x7
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	9                               ; 0x9
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	6                               ; 0x6
	.long	2                               ; 0x2
	.long	1                               ; 0x1
	.long	8                               ; 0x8
	.long	6                               ; 0x6
	.long	1                               ; 0x1
	.long	9                               ; 0x9
	.long	8                               ; 0x8
	.long	8                               ; 0x8
	.long	7                               ; 0x7
	.long	6                               ; 0x6
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	10                              ; 0xa
	.long	7                               ; 0x7
	.long	6                               ; 0x6
	.long	10                              ; 0xa
	.long	1                               ; 0x1
	.long	7                               ; 0x7
	.long	1                               ; 0x1
	.long	3                               ; 0x3
	.long	7                               ; 0x7
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	10                              ; 0xa
	.long	7                               ; 0x7
	.long	6                               ; 0x6
	.long	1                               ; 0x1
	.long	7                               ; 0x7
	.long	10                              ; 0xa
	.long	1                               ; 0x1
	.long	8                               ; 0x8
	.long	7                               ; 0x7
	.long	1                               ; 0x1
	.long	0                               ; 0x0
	.long	8                               ; 0x8
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	0                               ; 0x0
	.long	3                               ; 0x3
	.long	7                               ; 0x7
	.long	0                               ; 0x0
	.long	7                               ; 0x7
	.long	10                              ; 0xa
	.long	0                               ; 0x0
	.long	10                              ; 0xa
	.long	9                               ; 0x9
	.long	6                               ; 0x6
	.long	10                              ; 0xa
	.long	7                               ; 0x7
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	7                               ; 0x7
	.long	6                               ; 0x6
	.long	10                              ; 0xa
	.long	7                               ; 0x7
	.long	10                              ; 0xa
	.long	8                               ; 0x8
	.long	8                               ; 0x8
	.long	10                              ; 0xa
	.long	9                               ; 0x9
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	6                               ; 0x6
	.long	8                               ; 0x8
	.long	4                               ; 0x4
	.long	11                              ; 0xb
	.long	8                               ; 0x8
	.long	6                               ; 0x6
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	3                               ; 0x3
	.long	6                               ; 0x6
	.long	11                              ; 0xb
	.long	3                               ; 0x3
	.long	0                               ; 0x0
	.long	6                               ; 0x6
	.long	0                               ; 0x0
	.long	4                               ; 0x4
	.long	6                               ; 0x6
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	8                               ; 0x8
	.long	6                               ; 0x6
	.long	11                              ; 0xb
	.long	8                               ; 0x8
	.long	4                               ; 0x4
	.long	6                               ; 0x6
	.long	9                               ; 0x9
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	9                               ; 0x9
	.long	4                               ; 0x4
	.long	6                               ; 0x6
	.long	9                               ; 0x9
	.long	6                               ; 0x6
	.long	3                               ; 0x3
	.long	9                               ; 0x9
	.long	3                               ; 0x3
	.long	1                               ; 0x1
	.long	11                              ; 0xb
	.long	3                               ; 0x3
	.long	6                               ; 0x6
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	6                               ; 0x6
	.long	8                               ; 0x8
	.long	4                               ; 0x4
	.long	6                               ; 0x6
	.long	11                              ; 0xb
	.long	8                               ; 0x8
	.long	2                               ; 0x2
	.long	10                              ; 0xa
	.long	1                               ; 0x1
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	2                               ; 0x2
	.long	10                              ; 0xa
	.long	3                               ; 0x3
	.long	0                               ; 0x0
	.long	11                              ; 0xb
	.long	0                               ; 0x0
	.long	6                               ; 0x6
	.long	11                              ; 0xb
	.long	0                               ; 0x0
	.long	4                               ; 0x4
	.long	6                               ; 0x6
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4                               ; 0x4
	.long	11                              ; 0xb
	.long	8                               ; 0x8
	.long	4                               ; 0x4
	.long	6                               ; 0x6
	.long	11                              ; 0xb
	.long	0                               ; 0x0
	.long	2                               ; 0x2
	.long	9                               ; 0x9
	.long	2                               ; 0x2
	.long	10                              ; 0xa
	.long	9                               ; 0x9
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	10                              ; 0xa
	.long	9                               ; 0x9
	.long	3                               ; 0x3
	.long	10                              ; 0xa
	.long	3                               ; 0x3
	.long	2                               ; 0x2
	.long	9                               ; 0x9
	.long	4                               ; 0x4
	.long	3                               ; 0x3
	.long	11                              ; 0xb
	.long	3                               ; 0x3
	.long	6                               ; 0x6
	.long	4                               ; 0x4
	.long	6                               ; 0x6
	.long	3                               ; 0x3
	.long	4294967295                      ; 0xffffffff
	.long	8                               ; 0x8
	.long	2                               ; 0x2
	.long	3                               ; 0x3
	.long	8                               ; 0x8
	.long	4                               ; 0x4
	.long	2                               ; 0x2
	.long	4                               ; 0x4
	.long	6                               ; 0x6
	.long	2                               ; 0x2
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	0                               ; 0x0
	.long	4                               ; 0x4
	.long	2                               ; 0x2
	.long	4                               ; 0x4
	.long	6                               ; 0x6
	.long	2                               ; 0x2
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	9                               ; 0x9
	.long	0                               ; 0x0
	.long	2                               ; 0x2
	.long	3                               ; 0x3
	.long	4                               ; 0x4
	.long	2                               ; 0x2
	.long	4                               ; 0x4
	.long	6                               ; 0x6
	.long	4                               ; 0x4
	.long	3                               ; 0x3
	.long	8                               ; 0x8
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	9                               ; 0x9
	.long	4                               ; 0x4
	.long	1                               ; 0x1
	.long	4                               ; 0x4
	.long	2                               ; 0x2
	.long	2                               ; 0x2
	.long	4                               ; 0x4
	.long	6                               ; 0x6
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	8                               ; 0x8
	.long	1                               ; 0x1
	.long	3                               ; 0x3
	.long	8                               ; 0x8
	.long	6                               ; 0x6
	.long	1                               ; 0x1
	.long	8                               ; 0x8
	.long	4                               ; 0x4
	.long	6                               ; 0x6
	.long	6                               ; 0x6
	.long	10                              ; 0xa
	.long	1                               ; 0x1
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	10                              ; 0xa
	.long	1                               ; 0x1
	.long	0                               ; 0x0
	.long	10                              ; 0xa
	.long	0                               ; 0x0
	.long	6                               ; 0x6
	.long	6                               ; 0x6
	.long	0                               ; 0x0
	.long	4                               ; 0x4
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4                               ; 0x4
	.long	6                               ; 0x6
	.long	3                               ; 0x3
	.long	4                               ; 0x4
	.long	3                               ; 0x3
	.long	8                               ; 0x8
	.long	6                               ; 0x6
	.long	10                              ; 0xa
	.long	3                               ; 0x3
	.long	0                               ; 0x0
	.long	3                               ; 0x3
	.long	9                               ; 0x9
	.long	10                              ; 0xa
	.long	9                               ; 0x9
	.long	3                               ; 0x3
	.long	4294967295                      ; 0xffffffff
	.long	10                              ; 0xa
	.long	9                               ; 0x9
	.long	4                               ; 0x4
	.long	6                               ; 0x6
	.long	10                              ; 0xa
	.long	4                               ; 0x4
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4                               ; 0x4
	.long	9                               ; 0x9
	.long	5                               ; 0x5
	.long	7                               ; 0x7
	.long	6                               ; 0x6
	.long	11                              ; 0xb
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	0                               ; 0x0
	.long	8                               ; 0x8
	.long	3                               ; 0x3
	.long	4                               ; 0x4
	.long	9                               ; 0x9
	.long	5                               ; 0x5
	.long	11                              ; 0xb
	.long	7                               ; 0x7
	.long	6                               ; 0x6
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	5                               ; 0x5
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	5                               ; 0x5
	.long	4                               ; 0x4
	.long	0                               ; 0x0
	.long	7                               ; 0x7
	.long	6                               ; 0x6
	.long	11                              ; 0xb
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	11                              ; 0xb
	.long	7                               ; 0x7
	.long	6                               ; 0x6
	.long	8                               ; 0x8
	.long	3                               ; 0x3
	.long	4                               ; 0x4
	.long	3                               ; 0x3
	.long	5                               ; 0x5
	.long	4                               ; 0x4
	.long	3                               ; 0x3
	.long	1                               ; 0x1
	.long	5                               ; 0x5
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	9                               ; 0x9
	.long	5                               ; 0x5
	.long	4                               ; 0x4
	.long	10                              ; 0xa
	.long	1                               ; 0x1
	.long	2                               ; 0x2
	.long	7                               ; 0x7
	.long	6                               ; 0x6
	.long	11                              ; 0xb
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	6                               ; 0x6
	.long	11                              ; 0xb
	.long	7                               ; 0x7
	.long	1                               ; 0x1
	.long	2                               ; 0x2
	.long	10                              ; 0xa
	.long	0                               ; 0x0
	.long	8                               ; 0x8
	.long	3                               ; 0x3
	.long	4                               ; 0x4
	.long	9                               ; 0x9
	.long	5                               ; 0x5
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	7                               ; 0x7
	.long	6                               ; 0x6
	.long	11                              ; 0xb
	.long	5                               ; 0x5
	.long	4                               ; 0x4
	.long	10                              ; 0xa
	.long	4                               ; 0x4
	.long	2                               ; 0x2
	.long	10                              ; 0xa
	.long	4                               ; 0x4
	.long	0                               ; 0x0
	.long	2                               ; 0x2
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	3                               ; 0x3
	.long	4                               ; 0x4
	.long	8                               ; 0x8
	.long	3                               ; 0x3
	.long	5                               ; 0x5
	.long	4                               ; 0x4
	.long	3                               ; 0x3
	.long	2                               ; 0x2
	.long	5                               ; 0x5
	.long	10                              ; 0xa
	.long	5                               ; 0x5
	.long	2                               ; 0x2
	.long	11                              ; 0xb
	.long	7                               ; 0x7
	.long	6                               ; 0x6
	.long	4294967295                      ; 0xffffffff
	.long	7                               ; 0x7
	.long	2                               ; 0x2
	.long	3                               ; 0x3
	.long	7                               ; 0x7
	.long	6                               ; 0x6
	.long	2                               ; 0x2
	.long	5                               ; 0x5
	.long	4                               ; 0x4
	.long	9                               ; 0x9
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	9                               ; 0x9
	.long	5                               ; 0x5
	.long	4                               ; 0x4
	.long	0                               ; 0x0
	.long	8                               ; 0x8
	.long	6                               ; 0x6
	.long	0                               ; 0x0
	.long	6                               ; 0x6
	.long	2                               ; 0x2
	.long	6                               ; 0x6
	.long	8                               ; 0x8
	.long	7                               ; 0x7
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	3                               ; 0x3
	.long	6                               ; 0x6
	.long	2                               ; 0x2
	.long	3                               ; 0x3
	.long	7                               ; 0x7
	.long	6                               ; 0x6
	.long	1                               ; 0x1
	.long	5                               ; 0x5
	.long	0                               ; 0x0
	.long	5                               ; 0x5
	.long	4                               ; 0x4
	.long	0                               ; 0x0
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	6                               ; 0x6
	.long	2                               ; 0x2
	.long	8                               ; 0x8
	.long	6                               ; 0x6
	.long	8                               ; 0x8
	.long	7                               ; 0x7
	.long	2                               ; 0x2
	.long	1                               ; 0x1
	.long	8                               ; 0x8
	.long	4                               ; 0x4
	.long	8                               ; 0x8
	.long	5                               ; 0x5
	.long	1                               ; 0x1
	.long	5                               ; 0x5
	.long	8                               ; 0x8
	.long	4294967295                      ; 0xffffffff
	.long	9                               ; 0x9
	.long	5                               ; 0x5
	.long	4                               ; 0x4
	.long	10                              ; 0xa
	.long	1                               ; 0x1
	.long	6                               ; 0x6
	.long	1                               ; 0x1
	.long	7                               ; 0x7
	.long	6                               ; 0x6
	.long	1                               ; 0x1
	.long	3                               ; 0x3
	.long	7                               ; 0x7
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	6                               ; 0x6
	.long	10                              ; 0xa
	.long	1                               ; 0x1
	.long	7                               ; 0x7
	.long	6                               ; 0x6
	.long	1                               ; 0x1
	.long	0                               ; 0x0
	.long	7                               ; 0x7
	.long	8                               ; 0x8
	.long	7                               ; 0x7
	.long	0                               ; 0x0
	.long	9                               ; 0x9
	.long	5                               ; 0x5
	.long	4                               ; 0x4
	.long	4294967295                      ; 0xffffffff
	.long	4                               ; 0x4
	.long	0                               ; 0x0
	.long	10                              ; 0xa
	.long	4                               ; 0x4
	.long	10                              ; 0xa
	.long	5                               ; 0x5
	.long	0                               ; 0x0
	.long	3                               ; 0x3
	.long	10                              ; 0xa
	.long	6                               ; 0x6
	.long	10                              ; 0xa
	.long	7                               ; 0x7
	.long	3                               ; 0x3
	.long	7                               ; 0x7
	.long	10                              ; 0xa
	.long	4294967295                      ; 0xffffffff
	.long	7                               ; 0x7
	.long	6                               ; 0x6
	.long	10                              ; 0xa
	.long	7                               ; 0x7
	.long	10                              ; 0xa
	.long	8                               ; 0x8
	.long	5                               ; 0x5
	.long	4                               ; 0x4
	.long	10                              ; 0xa
	.long	4                               ; 0x4
	.long	8                               ; 0x8
	.long	10                              ; 0xa
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	6                               ; 0x6
	.long	9                               ; 0x9
	.long	5                               ; 0x5
	.long	6                               ; 0x6
	.long	11                              ; 0xb
	.long	9                               ; 0x9
	.long	11                              ; 0xb
	.long	8                               ; 0x8
	.long	9                               ; 0x9
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	3                               ; 0x3
	.long	6                               ; 0x6
	.long	11                              ; 0xb
	.long	0                               ; 0x0
	.long	6                               ; 0x6
	.long	3                               ; 0x3
	.long	0                               ; 0x0
	.long	5                               ; 0x5
	.long	6                               ; 0x6
	.long	0                               ; 0x0
	.long	9                               ; 0x9
	.long	5                               ; 0x5
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	0                               ; 0x0
	.long	11                              ; 0xb
	.long	8                               ; 0x8
	.long	0                               ; 0x0
	.long	5                               ; 0x5
	.long	11                              ; 0xb
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	5                               ; 0x5
	.long	5                               ; 0x5
	.long	6                               ; 0x6
	.long	11                              ; 0xb
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	6                               ; 0x6
	.long	11                              ; 0xb
	.long	3                               ; 0x3
	.long	6                               ; 0x6
	.long	3                               ; 0x3
	.long	5                               ; 0x5
	.long	5                               ; 0x5
	.long	3                               ; 0x3
	.long	1                               ; 0x1
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	2                               ; 0x2
	.long	10                              ; 0xa
	.long	9                               ; 0x9
	.long	5                               ; 0x5
	.long	11                              ; 0xb
	.long	9                               ; 0x9
	.long	11                              ; 0xb
	.long	8                               ; 0x8
	.long	11                              ; 0xb
	.long	5                               ; 0x5
	.long	6                               ; 0x6
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	0                               ; 0x0
	.long	11                              ; 0xb
	.long	3                               ; 0x3
	.long	0                               ; 0x0
	.long	6                               ; 0x6
	.long	11                              ; 0xb
	.long	0                               ; 0x0
	.long	9                               ; 0x9
	.long	6                               ; 0x6
	.long	5                               ; 0x5
	.long	6                               ; 0x6
	.long	9                               ; 0x9
	.long	1                               ; 0x1
	.long	2                               ; 0x2
	.long	10                              ; 0xa
	.long	4294967295                      ; 0xffffffff
	.long	11                              ; 0xb
	.long	8                               ; 0x8
	.long	5                               ; 0x5
	.long	11                              ; 0xb
	.long	5                               ; 0x5
	.long	6                               ; 0x6
	.long	8                               ; 0x8
	.long	0                               ; 0x0
	.long	5                               ; 0x5
	.long	10                              ; 0xa
	.long	5                               ; 0x5
	.long	2                               ; 0x2
	.long	0                               ; 0x0
	.long	2                               ; 0x2
	.long	5                               ; 0x5
	.long	4294967295                      ; 0xffffffff
	.long	6                               ; 0x6
	.long	11                              ; 0xb
	.long	3                               ; 0x3
	.long	6                               ; 0x6
	.long	3                               ; 0x3
	.long	5                               ; 0x5
	.long	2                               ; 0x2
	.long	10                              ; 0xa
	.long	3                               ; 0x3
	.long	10                              ; 0xa
	.long	5                               ; 0x5
	.long	3                               ; 0x3
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	5                               ; 0x5
	.long	8                               ; 0x8
	.long	9                               ; 0x9
	.long	5                               ; 0x5
	.long	2                               ; 0x2
	.long	8                               ; 0x8
	.long	5                               ; 0x5
	.long	6                               ; 0x6
	.long	2                               ; 0x2
	.long	3                               ; 0x3
	.long	8                               ; 0x8
	.long	2                               ; 0x2
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	9                               ; 0x9
	.long	5                               ; 0x5
	.long	6                               ; 0x6
	.long	9                               ; 0x9
	.long	6                               ; 0x6
	.long	0                               ; 0x0
	.long	0                               ; 0x0
	.long	6                               ; 0x6
	.long	2                               ; 0x2
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	5                               ; 0x5
	.long	8                               ; 0x8
	.long	1                               ; 0x1
	.long	8                               ; 0x8
	.long	0                               ; 0x0
	.long	5                               ; 0x5
	.long	6                               ; 0x6
	.long	8                               ; 0x8
	.long	3                               ; 0x3
	.long	8                               ; 0x8
	.long	2                               ; 0x2
	.long	6                               ; 0x6
	.long	2                               ; 0x2
	.long	8                               ; 0x8
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	5                               ; 0x5
	.long	6                               ; 0x6
	.long	2                               ; 0x2
	.long	1                               ; 0x1
	.long	6                               ; 0x6
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	3                               ; 0x3
	.long	6                               ; 0x6
	.long	1                               ; 0x1
	.long	6                               ; 0x6
	.long	10                              ; 0xa
	.long	3                               ; 0x3
	.long	8                               ; 0x8
	.long	6                               ; 0x6
	.long	5                               ; 0x5
	.long	6                               ; 0x6
	.long	9                               ; 0x9
	.long	8                               ; 0x8
	.long	9                               ; 0x9
	.long	6                               ; 0x6
	.long	4294967295                      ; 0xffffffff
	.long	10                              ; 0xa
	.long	1                               ; 0x1
	.long	0                               ; 0x0
	.long	10                              ; 0xa
	.long	0                               ; 0x0
	.long	6                               ; 0x6
	.long	9                               ; 0x9
	.long	5                               ; 0x5
	.long	0                               ; 0x0
	.long	5                               ; 0x5
	.long	6                               ; 0x6
	.long	0                               ; 0x0
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	0                               ; 0x0
	.long	3                               ; 0x3
	.long	8                               ; 0x8
	.long	5                               ; 0x5
	.long	6                               ; 0x6
	.long	10                              ; 0xa
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	10                              ; 0xa
	.long	5                               ; 0x5
	.long	6                               ; 0x6
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	11                              ; 0xb
	.long	5                               ; 0x5
	.long	10                              ; 0xa
	.long	7                               ; 0x7
	.long	5                               ; 0x5
	.long	11                              ; 0xb
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	11                              ; 0xb
	.long	5                               ; 0x5
	.long	10                              ; 0xa
	.long	11                              ; 0xb
	.long	7                               ; 0x7
	.long	5                               ; 0x5
	.long	8                               ; 0x8
	.long	3                               ; 0x3
	.long	0                               ; 0x0
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	5                               ; 0x5
	.long	11                              ; 0xb
	.long	7                               ; 0x7
	.long	5                               ; 0x5
	.long	10                              ; 0xa
	.long	11                              ; 0xb
	.long	1                               ; 0x1
	.long	9                               ; 0x9
	.long	0                               ; 0x0
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	10                              ; 0xa
	.long	7                               ; 0x7
	.long	5                               ; 0x5
	.long	10                              ; 0xa
	.long	11                              ; 0xb
	.long	7                               ; 0x7
	.long	9                               ; 0x9
	.long	8                               ; 0x8
	.long	1                               ; 0x1
	.long	8                               ; 0x8
	.long	3                               ; 0x3
	.long	1                               ; 0x1
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	11                              ; 0xb
	.long	1                               ; 0x1
	.long	2                               ; 0x2
	.long	11                              ; 0xb
	.long	7                               ; 0x7
	.long	1                               ; 0x1
	.long	7                               ; 0x7
	.long	5                               ; 0x5
	.long	1                               ; 0x1
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	0                               ; 0x0
	.long	8                               ; 0x8
	.long	3                               ; 0x3
	.long	1                               ; 0x1
	.long	2                               ; 0x2
	.long	7                               ; 0x7
	.long	1                               ; 0x1
	.long	7                               ; 0x7
	.long	5                               ; 0x5
	.long	7                               ; 0x7
	.long	2                               ; 0x2
	.long	11                              ; 0xb
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	9                               ; 0x9
	.long	7                               ; 0x7
	.long	5                               ; 0x5
	.long	9                               ; 0x9
	.long	2                               ; 0x2
	.long	7                               ; 0x7
	.long	9                               ; 0x9
	.long	0                               ; 0x0
	.long	2                               ; 0x2
	.long	2                               ; 0x2
	.long	11                              ; 0xb
	.long	7                               ; 0x7
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	7                               ; 0x7
	.long	5                               ; 0x5
	.long	2                               ; 0x2
	.long	7                               ; 0x7
	.long	2                               ; 0x2
	.long	11                              ; 0xb
	.long	5                               ; 0x5
	.long	9                               ; 0x9
	.long	2                               ; 0x2
	.long	3                               ; 0x3
	.long	2                               ; 0x2
	.long	8                               ; 0x8
	.long	9                               ; 0x9
	.long	8                               ; 0x8
	.long	2                               ; 0x2
	.long	4294967295                      ; 0xffffffff
	.long	2                               ; 0x2
	.long	5                               ; 0x5
	.long	10                              ; 0xa
	.long	2                               ; 0x2
	.long	3                               ; 0x3
	.long	5                               ; 0x5
	.long	3                               ; 0x3
	.long	7                               ; 0x7
	.long	5                               ; 0x5
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	8                               ; 0x8
	.long	2                               ; 0x2
	.long	0                               ; 0x0
	.long	8                               ; 0x8
	.long	5                               ; 0x5
	.long	2                               ; 0x2
	.long	8                               ; 0x8
	.long	7                               ; 0x7
	.long	5                               ; 0x5
	.long	10                              ; 0xa
	.long	2                               ; 0x2
	.long	5                               ; 0x5
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	9                               ; 0x9
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	5                               ; 0x5
	.long	10                              ; 0xa
	.long	3                               ; 0x3
	.long	5                               ; 0x5
	.long	3                               ; 0x3
	.long	7                               ; 0x7
	.long	3                               ; 0x3
	.long	10                              ; 0xa
	.long	2                               ; 0x2
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	9                               ; 0x9
	.long	8                               ; 0x8
	.long	2                               ; 0x2
	.long	9                               ; 0x9
	.long	2                               ; 0x2
	.long	1                               ; 0x1
	.long	8                               ; 0x8
	.long	7                               ; 0x7
	.long	2                               ; 0x2
	.long	10                              ; 0xa
	.long	2                               ; 0x2
	.long	5                               ; 0x5
	.long	7                               ; 0x7
	.long	5                               ; 0x5
	.long	2                               ; 0x2
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	3                               ; 0x3
	.long	5                               ; 0x5
	.long	3                               ; 0x3
	.long	7                               ; 0x7
	.long	5                               ; 0x5
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	0                               ; 0x0
	.long	8                               ; 0x8
	.long	7                               ; 0x7
	.long	0                               ; 0x0
	.long	7                               ; 0x7
	.long	1                               ; 0x1
	.long	1                               ; 0x1
	.long	7                               ; 0x7
	.long	5                               ; 0x5
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	9                               ; 0x9
	.long	0                               ; 0x0
	.long	3                               ; 0x3
	.long	9                               ; 0x9
	.long	3                               ; 0x3
	.long	5                               ; 0x5
	.long	5                               ; 0x5
	.long	3                               ; 0x3
	.long	7                               ; 0x7
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	9                               ; 0x9
	.long	8                               ; 0x8
	.long	7                               ; 0x7
	.long	5                               ; 0x5
	.long	9                               ; 0x9
	.long	7                               ; 0x7
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	5                               ; 0x5
	.long	8                               ; 0x8
	.long	4                               ; 0x4
	.long	5                               ; 0x5
	.long	10                              ; 0xa
	.long	8                               ; 0x8
	.long	10                              ; 0xa
	.long	11                              ; 0xb
	.long	8                               ; 0x8
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	5                               ; 0x5
	.long	0                               ; 0x0
	.long	4                               ; 0x4
	.long	5                               ; 0x5
	.long	11                              ; 0xb
	.long	0                               ; 0x0
	.long	5                               ; 0x5
	.long	10                              ; 0xa
	.long	11                              ; 0xb
	.long	11                              ; 0xb
	.long	3                               ; 0x3
	.long	0                               ; 0x0
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	9                               ; 0x9
	.long	8                               ; 0x8
	.long	4                               ; 0x4
	.long	10                              ; 0xa
	.long	8                               ; 0x8
	.long	10                              ; 0xa
	.long	11                              ; 0xb
	.long	10                              ; 0xa
	.long	4                               ; 0x4
	.long	5                               ; 0x5
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	10                              ; 0xa
	.long	11                              ; 0xb
	.long	4                               ; 0x4
	.long	10                              ; 0xa
	.long	4                               ; 0x4
	.long	5                               ; 0x5
	.long	11                              ; 0xb
	.long	3                               ; 0x3
	.long	4                               ; 0x4
	.long	9                               ; 0x9
	.long	4                               ; 0x4
	.long	1                               ; 0x1
	.long	3                               ; 0x3
	.long	1                               ; 0x1
	.long	4                               ; 0x4
	.long	4294967295                      ; 0xffffffff
	.long	2                               ; 0x2
	.long	5                               ; 0x5
	.long	1                               ; 0x1
	.long	2                               ; 0x2
	.long	8                               ; 0x8
	.long	5                               ; 0x5
	.long	2                               ; 0x2
	.long	11                              ; 0xb
	.long	8                               ; 0x8
	.long	4                               ; 0x4
	.long	5                               ; 0x5
	.long	8                               ; 0x8
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	0                               ; 0x0
	.long	4                               ; 0x4
	.long	11                              ; 0xb
	.long	0                               ; 0x0
	.long	11                              ; 0xb
	.long	3                               ; 0x3
	.long	4                               ; 0x4
	.long	5                               ; 0x5
	.long	11                              ; 0xb
	.long	2                               ; 0x2
	.long	11                              ; 0xb
	.long	1                               ; 0x1
	.long	5                               ; 0x5
	.long	1                               ; 0x1
	.long	11                              ; 0xb
	.long	4294967295                      ; 0xffffffff
	.long	0                               ; 0x0
	.long	2                               ; 0x2
	.long	5                               ; 0x5
	.long	0                               ; 0x0
	.long	5                               ; 0x5
	.long	9                               ; 0x9
	.long	2                               ; 0x2
	.long	11                              ; 0xb
	.long	5                               ; 0x5
	.long	4                               ; 0x4
	.long	5                               ; 0x5
	.long	8                               ; 0x8
	.long	11                              ; 0xb
	.long	8                               ; 0x8
	.long	5                               ; 0x5
	.long	4294967295                      ; 0xffffffff
	.long	9                               ; 0x9
	.long	4                               ; 0x4
	.long	5                               ; 0x5
	.long	2                               ; 0x2
	.long	11                              ; 0xb
	.long	3                               ; 0x3
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	2                               ; 0x2
	.long	5                               ; 0x5
	.long	10                              ; 0xa
	.long	3                               ; 0x3
	.long	5                               ; 0x5
	.long	2                               ; 0x2
	.long	3                               ; 0x3
	.long	4                               ; 0x4
	.long	5                               ; 0x5
	.long	3                               ; 0x3
	.long	8                               ; 0x8
	.long	4                               ; 0x4
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	5                               ; 0x5
	.long	10                              ; 0xa
	.long	2                               ; 0x2
	.long	5                               ; 0x5
	.long	2                               ; 0x2
	.long	4                               ; 0x4
	.long	4                               ; 0x4
	.long	2                               ; 0x2
	.long	0                               ; 0x0
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	3                               ; 0x3
	.long	10                              ; 0xa
	.long	2                               ; 0x2
	.long	3                               ; 0x3
	.long	5                               ; 0x5
	.long	10                              ; 0xa
	.long	3                               ; 0x3
	.long	8                               ; 0x8
	.long	5                               ; 0x5
	.long	4                               ; 0x4
	.long	5                               ; 0x5
	.long	8                               ; 0x8
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	9                               ; 0x9
	.long	4294967295                      ; 0xffffffff
	.long	5                               ; 0x5
	.long	10                              ; 0xa
	.long	2                               ; 0x2
	.long	5                               ; 0x5
	.long	2                               ; 0x2
	.long	4                               ; 0x4
	.long	1                               ; 0x1
	.long	9                               ; 0x9
	.long	2                               ; 0x2
	.long	9                               ; 0x9
	.long	4                               ; 0x4
	.long	2                               ; 0x2
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	8                               ; 0x8
	.long	4                               ; 0x4
	.long	5                               ; 0x5
	.long	8                               ; 0x8
	.long	5                               ; 0x5
	.long	3                               ; 0x3
	.long	3                               ; 0x3
	.long	5                               ; 0x5
	.long	1                               ; 0x1
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	0                               ; 0x0
	.long	4                               ; 0x4
	.long	5                               ; 0x5
	.long	1                               ; 0x1
	.long	0                               ; 0x0
	.long	5                               ; 0x5
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	8                               ; 0x8
	.long	4                               ; 0x4
	.long	5                               ; 0x5
	.long	8                               ; 0x8
	.long	5                               ; 0x5
	.long	3                               ; 0x3
	.long	9                               ; 0x9
	.long	0                               ; 0x0
	.long	5                               ; 0x5
	.long	0                               ; 0x0
	.long	3                               ; 0x3
	.long	5                               ; 0x5
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	9                               ; 0x9
	.long	4                               ; 0x4
	.long	5                               ; 0x5
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4                               ; 0x4
	.long	11                              ; 0xb
	.long	7                               ; 0x7
	.long	4                               ; 0x4
	.long	9                               ; 0x9
	.long	11                              ; 0xb
	.long	9                               ; 0x9
	.long	10                              ; 0xa
	.long	11                              ; 0xb
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	0                               ; 0x0
	.long	8                               ; 0x8
	.long	3                               ; 0x3
	.long	4                               ; 0x4
	.long	9                               ; 0x9
	.long	7                               ; 0x7
	.long	9                               ; 0x9
	.long	11                              ; 0xb
	.long	7                               ; 0x7
	.long	9                               ; 0x9
	.long	10                              ; 0xa
	.long	11                              ; 0xb
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	10                              ; 0xa
	.long	11                              ; 0xb
	.long	1                               ; 0x1
	.long	11                              ; 0xb
	.long	4                               ; 0x4
	.long	1                               ; 0x1
	.long	4                               ; 0x4
	.long	0                               ; 0x0
	.long	7                               ; 0x7
	.long	4                               ; 0x4
	.long	11                              ; 0xb
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	3                               ; 0x3
	.long	1                               ; 0x1
	.long	4                               ; 0x4
	.long	3                               ; 0x3
	.long	4                               ; 0x4
	.long	8                               ; 0x8
	.long	1                               ; 0x1
	.long	10                              ; 0xa
	.long	4                               ; 0x4
	.long	7                               ; 0x7
	.long	4                               ; 0x4
	.long	11                              ; 0xb
	.long	10                              ; 0xa
	.long	11                              ; 0xb
	.long	4                               ; 0x4
	.long	4294967295                      ; 0xffffffff
	.long	4                               ; 0x4
	.long	11                              ; 0xb
	.long	7                               ; 0x7
	.long	9                               ; 0x9
	.long	11                              ; 0xb
	.long	4                               ; 0x4
	.long	9                               ; 0x9
	.long	2                               ; 0x2
	.long	11                              ; 0xb
	.long	9                               ; 0x9
	.long	1                               ; 0x1
	.long	2                               ; 0x2
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	9                               ; 0x9
	.long	7                               ; 0x7
	.long	4                               ; 0x4
	.long	9                               ; 0x9
	.long	11                              ; 0xb
	.long	7                               ; 0x7
	.long	9                               ; 0x9
	.long	1                               ; 0x1
	.long	11                              ; 0xb
	.long	2                               ; 0x2
	.long	11                              ; 0xb
	.long	1                               ; 0x1
	.long	0                               ; 0x0
	.long	8                               ; 0x8
	.long	3                               ; 0x3
	.long	4294967295                      ; 0xffffffff
	.long	11                              ; 0xb
	.long	7                               ; 0x7
	.long	4                               ; 0x4
	.long	11                              ; 0xb
	.long	4                               ; 0x4
	.long	2                               ; 0x2
	.long	2                               ; 0x2
	.long	4                               ; 0x4
	.long	0                               ; 0x0
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	11                              ; 0xb
	.long	7                               ; 0x7
	.long	4                               ; 0x4
	.long	11                              ; 0xb
	.long	4                               ; 0x4
	.long	2                               ; 0x2
	.long	8                               ; 0x8
	.long	3                               ; 0x3
	.long	4                               ; 0x4
	.long	3                               ; 0x3
	.long	2                               ; 0x2
	.long	4                               ; 0x4
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	2                               ; 0x2
	.long	9                               ; 0x9
	.long	10                              ; 0xa
	.long	2                               ; 0x2
	.long	7                               ; 0x7
	.long	9                               ; 0x9
	.long	2                               ; 0x2
	.long	3                               ; 0x3
	.long	7                               ; 0x7
	.long	7                               ; 0x7
	.long	4                               ; 0x4
	.long	9                               ; 0x9
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	9                               ; 0x9
	.long	10                              ; 0xa
	.long	7                               ; 0x7
	.long	9                               ; 0x9
	.long	7                               ; 0x7
	.long	4                               ; 0x4
	.long	10                              ; 0xa
	.long	2                               ; 0x2
	.long	7                               ; 0x7
	.long	8                               ; 0x8
	.long	7                               ; 0x7
	.long	0                               ; 0x0
	.long	2                               ; 0x2
	.long	0                               ; 0x0
	.long	7                               ; 0x7
	.long	4294967295                      ; 0xffffffff
	.long	3                               ; 0x3
	.long	7                               ; 0x7
	.long	10                              ; 0xa
	.long	3                               ; 0x3
	.long	10                              ; 0xa
	.long	2                               ; 0x2
	.long	7                               ; 0x7
	.long	4                               ; 0x4
	.long	10                              ; 0xa
	.long	1                               ; 0x1
	.long	10                              ; 0xa
	.long	0                               ; 0x0
	.long	4                               ; 0x4
	.long	0                               ; 0x0
	.long	10                              ; 0xa
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	10                              ; 0xa
	.long	2                               ; 0x2
	.long	8                               ; 0x8
	.long	7                               ; 0x7
	.long	4                               ; 0x4
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4                               ; 0x4
	.long	9                               ; 0x9
	.long	1                               ; 0x1
	.long	4                               ; 0x4
	.long	1                               ; 0x1
	.long	7                               ; 0x7
	.long	7                               ; 0x7
	.long	1                               ; 0x1
	.long	3                               ; 0x3
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4                               ; 0x4
	.long	9                               ; 0x9
	.long	1                               ; 0x1
	.long	4                               ; 0x4
	.long	1                               ; 0x1
	.long	7                               ; 0x7
	.long	0                               ; 0x0
	.long	8                               ; 0x8
	.long	1                               ; 0x1
	.long	8                               ; 0x8
	.long	7                               ; 0x7
	.long	1                               ; 0x1
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4                               ; 0x4
	.long	0                               ; 0x0
	.long	3                               ; 0x3
	.long	7                               ; 0x7
	.long	4                               ; 0x4
	.long	3                               ; 0x3
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4                               ; 0x4
	.long	8                               ; 0x8
	.long	7                               ; 0x7
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	9                               ; 0x9
	.long	10                              ; 0xa
	.long	8                               ; 0x8
	.long	10                              ; 0xa
	.long	11                              ; 0xb
	.long	8                               ; 0x8
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	3                               ; 0x3
	.long	0                               ; 0x0
	.long	9                               ; 0x9
	.long	3                               ; 0x3
	.long	9                               ; 0x9
	.long	11                              ; 0xb
	.long	11                              ; 0xb
	.long	9                               ; 0x9
	.long	10                              ; 0xa
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	10                              ; 0xa
	.long	0                               ; 0x0
	.long	10                              ; 0xa
	.long	8                               ; 0x8
	.long	8                               ; 0x8
	.long	10                              ; 0xa
	.long	11                              ; 0xb
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	3                               ; 0x3
	.long	1                               ; 0x1
	.long	10                              ; 0xa
	.long	11                              ; 0xb
	.long	3                               ; 0x3
	.long	10                              ; 0xa
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	2                               ; 0x2
	.long	11                              ; 0xb
	.long	1                               ; 0x1
	.long	11                              ; 0xb
	.long	9                               ; 0x9
	.long	9                               ; 0x9
	.long	11                              ; 0xb
	.long	8                               ; 0x8
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	3                               ; 0x3
	.long	0                               ; 0x0
	.long	9                               ; 0x9
	.long	3                               ; 0x3
	.long	9                               ; 0x9
	.long	11                              ; 0xb
	.long	1                               ; 0x1
	.long	2                               ; 0x2
	.long	9                               ; 0x9
	.long	2                               ; 0x2
	.long	11                              ; 0xb
	.long	9                               ; 0x9
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	0                               ; 0x0
	.long	2                               ; 0x2
	.long	11                              ; 0xb
	.long	8                               ; 0x8
	.long	0                               ; 0x0
	.long	11                              ; 0xb
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	3                               ; 0x3
	.long	2                               ; 0x2
	.long	11                              ; 0xb
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	2                               ; 0x2
	.long	3                               ; 0x3
	.long	8                               ; 0x8
	.long	2                               ; 0x2
	.long	8                               ; 0x8
	.long	10                              ; 0xa
	.long	10                              ; 0xa
	.long	8                               ; 0x8
	.long	9                               ; 0x9
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	9                               ; 0x9
	.long	10                              ; 0xa
	.long	2                               ; 0x2
	.long	0                               ; 0x0
	.long	9                               ; 0x9
	.long	2                               ; 0x2
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	2                               ; 0x2
	.long	3                               ; 0x3
	.long	8                               ; 0x8
	.long	2                               ; 0x2
	.long	8                               ; 0x8
	.long	10                              ; 0xa
	.long	0                               ; 0x0
	.long	1                               ; 0x1
	.long	8                               ; 0x8
	.long	1                               ; 0x1
	.long	10                              ; 0xa
	.long	8                               ; 0x8
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	10                              ; 0xa
	.long	2                               ; 0x2
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	1                               ; 0x1
	.long	3                               ; 0x3
	.long	8                               ; 0x8
	.long	9                               ; 0x9
	.long	1                               ; 0x1
	.long	8                               ; 0x8
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	0                               ; 0x0
	.long	9                               ; 0x9
	.long	1                               ; 0x1
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	0                               ; 0x0
	.long	3                               ; 0x3
	.long	8                               ; 0x8
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.long	4294967295                      ; 0xffffffff
	.zero	64,255
	.size	triTable, 16384

	.protected	nbTriTable              ; @nbTriTable
	.type	nbTriTable,@object
	.globl	nbTriTable
	.p2align	4, 0x0
nbTriTable:
	.long	0                               ; 0x0
	.long	3                               ; 0x3
	.long	3                               ; 0x3
	.long	6                               ; 0x6
	.long	3                               ; 0x3
	.long	6                               ; 0x6
	.long	6                               ; 0x6
	.long	9                               ; 0x9
	.long	3                               ; 0x3
	.long	6                               ; 0x6
	.long	6                               ; 0x6
	.long	9                               ; 0x9
	.long	6                               ; 0x6
	.long	9                               ; 0x9
	.long	9                               ; 0x9
	.long	6                               ; 0x6
	.long	3                               ; 0x3
	.long	6                               ; 0x6
	.long	6                               ; 0x6
	.long	9                               ; 0x9
	.long	6                               ; 0x6
	.long	9                               ; 0x9
	.long	9                               ; 0x9
	.long	12                              ; 0xc
	.long	6                               ; 0x6
	.long	9                               ; 0x9
	.long	9                               ; 0x9
	.long	12                              ; 0xc
	.long	9                               ; 0x9
	.long	12                              ; 0xc
	.long	12                              ; 0xc
	.long	9                               ; 0x9
	.long	3                               ; 0x3
	.long	6                               ; 0x6
	.long	6                               ; 0x6
	.long	9                               ; 0x9
	.long	6                               ; 0x6
	.long	9                               ; 0x9
	.long	9                               ; 0x9
	.long	12                              ; 0xc
	.long	6                               ; 0x6
	.long	9                               ; 0x9
	.long	9                               ; 0x9
	.long	12                              ; 0xc
	.long	9                               ; 0x9
	.long	12                              ; 0xc
	.long	12                              ; 0xc
	.long	9                               ; 0x9
	.long	6                               ; 0x6
	.long	9                               ; 0x9
	.long	9                               ; 0x9
	.long	6                               ; 0x6
	.long	9                               ; 0x9
	.long	12                              ; 0xc
	.long	12                              ; 0xc
	.long	9                               ; 0x9
	.long	9                               ; 0x9
	.long	12                              ; 0xc
	.long	12                              ; 0xc
	.long	9                               ; 0x9
	.long	12                              ; 0xc
	.long	15                              ; 0xf
	.long	15                              ; 0xf
	.long	6                               ; 0x6
	.long	3                               ; 0x3
	.long	6                               ; 0x6
	.long	6                               ; 0x6
	.long	9                               ; 0x9
	.long	6                               ; 0x6
	.long	9                               ; 0x9
	.long	9                               ; 0x9
	.long	12                              ; 0xc
	.long	6                               ; 0x6
	.long	9                               ; 0x9
	.long	9                               ; 0x9
	.long	12                              ; 0xc
	.long	9                               ; 0x9
	.long	12                              ; 0xc
	.long	12                              ; 0xc
	.long	9                               ; 0x9
	.long	6                               ; 0x6
	.long	9                               ; 0x9
	.long	9                               ; 0x9
	.long	12                              ; 0xc
	.long	9                               ; 0x9
	.long	12                              ; 0xc
	.long	12                              ; 0xc
	.long	15                              ; 0xf
	.long	9                               ; 0x9
	.long	12                              ; 0xc
	.long	12                              ; 0xc
	.long	15                              ; 0xf
	.long	12                              ; 0xc
	.long	15                              ; 0xf
	.long	15                              ; 0xf
	.long	12                              ; 0xc
	.long	6                               ; 0x6
	.long	9                               ; 0x9
	.long	9                               ; 0x9
	.long	12                              ; 0xc
	.long	9                               ; 0x9
	.long	12                              ; 0xc
	.long	6                               ; 0x6
	.long	9                               ; 0x9
	.long	9                               ; 0x9
	.long	12                              ; 0xc
	.long	12                              ; 0xc
	.long	15                              ; 0xf
	.long	12                              ; 0xc
	.long	15                              ; 0xf
	.long	9                               ; 0x9
	.long	6                               ; 0x6
	.long	9                               ; 0x9
	.long	12                              ; 0xc
	.long	12                              ; 0xc
	.long	9                               ; 0x9
	.long	12                              ; 0xc
	.long	15                              ; 0xf
	.long	9                               ; 0x9
	.long	6                               ; 0x6
	.long	12                              ; 0xc
	.long	15                              ; 0xf
	.long	15                              ; 0xf
	.long	12                              ; 0xc
	.long	15                              ; 0xf
	.long	6                               ; 0x6
	.long	12                              ; 0xc
	.long	3                               ; 0x3
	.long	3                               ; 0x3
	.long	6                               ; 0x6
	.long	6                               ; 0x6
	.long	9                               ; 0x9
	.long	6                               ; 0x6
	.long	9                               ; 0x9
	.long	9                               ; 0x9
	.long	12                              ; 0xc
	.long	6                               ; 0x6
	.long	9                               ; 0x9
	.long	9                               ; 0x9
	.long	12                              ; 0xc
	.long	9                               ; 0x9
	.long	12                              ; 0xc
	.long	12                              ; 0xc
	.long	9                               ; 0x9
	.long	6                               ; 0x6
	.long	9                               ; 0x9
	.long	9                               ; 0x9
	.long	12                              ; 0xc
	.long	9                               ; 0x9
	.long	12                              ; 0xc
	.long	12                              ; 0xc
	.long	15                              ; 0xf
	.long	9                               ; 0x9
	.long	6                               ; 0x6
	.long	12                              ; 0xc
	.long	9                               ; 0x9
	.long	12                              ; 0xc
	.long	9                               ; 0x9
	.long	15                              ; 0xf
	.long	6                               ; 0x6
	.long	6                               ; 0x6
	.long	9                               ; 0x9
	.long	9                               ; 0x9
	.long	12                              ; 0xc
	.long	9                               ; 0x9
	.long	12                              ; 0xc
	.long	12                              ; 0xc
	.long	15                              ; 0xf
	.long	9                               ; 0x9
	.long	12                              ; 0xc
	.long	12                              ; 0xc
	.long	15                              ; 0xf
	.long	12                              ; 0xc
	.long	15                              ; 0xf
	.long	15                              ; 0xf
	.long	12                              ; 0xc
	.long	9                               ; 0x9
	.long	12                              ; 0xc
	.long	12                              ; 0xc
	.long	9                               ; 0x9
	.long	12                              ; 0xc
	.long	15                              ; 0xf
	.long	15                              ; 0xf
	.long	12                              ; 0xc
	.long	12                              ; 0xc
	.long	9                               ; 0x9
	.long	15                              ; 0xf
	.long	6                               ; 0x6
	.long	15                              ; 0xf
	.long	12                              ; 0xc
	.long	6                               ; 0x6
	.long	3                               ; 0x3
	.long	6                               ; 0x6
	.long	9                               ; 0x9
	.long	9                               ; 0x9
	.long	12                              ; 0xc
	.long	9                               ; 0x9
	.long	12                              ; 0xc
	.long	12                              ; 0xc
	.long	15                              ; 0xf
	.long	9                               ; 0x9
	.long	12                              ; 0xc
	.long	12                              ; 0xc
	.long	15                              ; 0xf
	.long	6                               ; 0x6
	.long	9                               ; 0x9
	.long	9                               ; 0x9
	.long	6                               ; 0x6
	.long	9                               ; 0x9
	.long	12                              ; 0xc
	.long	12                              ; 0xc
	.long	15                              ; 0xf
	.long	12                              ; 0xc
	.long	15                              ; 0xf
	.long	15                              ; 0xf
	.long	6                               ; 0x6
	.long	12                              ; 0xc
	.long	9                               ; 0x9
	.long	15                              ; 0xf
	.long	12                              ; 0xc
	.long	9                               ; 0x9
	.long	6                               ; 0x6
	.long	12                              ; 0xc
	.long	3                               ; 0x3
	.long	9                               ; 0x9
	.long	12                              ; 0xc
	.long	12                              ; 0xc
	.long	15                              ; 0xf
	.long	12                              ; 0xc
	.long	15                              ; 0xf
	.long	9                               ; 0x9
	.long	12                              ; 0xc
	.long	12                              ; 0xc
	.long	15                              ; 0xf
	.long	15                              ; 0xf
	.long	6                               ; 0x6
	.long	9                               ; 0x9
	.long	12                              ; 0xc
	.long	6                               ; 0x6
	.long	3                               ; 0x3
	.long	6                               ; 0x6
	.long	9                               ; 0x9
	.long	9                               ; 0x9
	.long	6                               ; 0x6
	.long	9                               ; 0x9
	.long	12                              ; 0xc
	.long	6                               ; 0x6
	.long	3                               ; 0x3
	.long	9                               ; 0x9
	.long	6                               ; 0x6
	.long	12                              ; 0xc
	.long	3                               ; 0x3
	.long	6                               ; 0x6
	.long	3                               ; 0x3
	.long	3                               ; 0x3
	.long	0                               ; 0x0
	.size	nbTriTable, 1024

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym triTable
	.addrsig_sym nbTriTable
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           12
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           12
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18countVertexPerCellf15HIP_vector_typeIiLj3EEPKfPS_IjLj2EEiS0_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z18countVertexPerCellf15HIP_vector_typeIiLj3EEPKfPS_IjLj2EEiS0_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     19
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           12
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           12
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
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...

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