#include "includes.h"
__global__ void Compute_psi_phi_Kernel(float* psi, float* phi, const float* gAbsIx, const float* gAbsIy, const float* gIx, const float* gIy, int nPixels, float norm_for_contrast_num, float norm_for_contrast_denom, float eps)
{
int bx = blockIdx.x;
int tx = threadIdx.x;

int x = bx*blockDim.x + tx;
if (x >= nPixels)
return;


float psi_num = 0, psi_denom = 0;
float phi_num = 0, phi_denom = 0;
if (norm_for_contrast_num == 0)
{
psi_num = 1;
phi_num = 1;
}
else if (norm_for_contrast_num == 1)
{
psi_num = gAbsIx[x];
phi_num = gAbsIy[x];
}
else if (norm_for_contrast_num == 2)
{
psi_num = gAbsIx[x] * gAbsIx[x];
phi_num = gAbsIy[x] * gAbsIy[x];
}
else
{
psi_num = pow(gAbsIx[x], norm_for_contrast_num);
phi_num = pow(gAbsIy[x], norm_for_contrast_num);
}

if (norm_for_contrast_denom == 0)
{
psi_denom = 1;
phi_denom = 1;
}
else if (norm_for_contrast_denom == 1)
{
psi_denom = fabs(gIx[x]) + eps;
phi_denom = fabs(gIy[x]) + eps;
}
else if (norm_for_contrast_denom == 2)
{
psi_denom = gIx[x] * gIx[x] + eps;
phi_denom = gIy[x] * gIy[x] + eps;
}
else
{
psi_denom = pow(fabs(gIx[x]), norm_for_contrast_denom) + eps;
phi_denom = pow(fabs(gIy[x]), norm_for_contrast_denom) + eps;
}
psi[x] = psi_num / psi_denom;
phi[x] = phi_num / phi_denom;

}
	.file	"tmpxft_0030d99e_00000000-6_Compute_psi_phi_Kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z60__device_stub__Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifffPfS_PKfS1_S1_S1_ifff
	.type	_Z60__device_stub__Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifffPfS_PKfS1_S1_S1_ifff, @function
_Z60__device_stub__Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifffPfS_PKfS1_S1_S1_ifff:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$232, %rsp
	.cfi_def_cfa_offset 240
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movss	%xmm0, 12(%rsp)
	movss	%xmm1, 8(%rsp)
	movss	%xmm2, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 216(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 208(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	80(%rsp)
	.cfi_def_cfa_offset 248
	leaq	_Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 256
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 248
	popq	%rdx
	.cfi_def_cfa_offset 240
.L2:
	movq	216(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$232, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z60__device_stub__Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifffPfS_PKfS1_S1_S1_ifff, .-_Z60__device_stub__Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifffPfS_PKfS1_S1_S1_ifff
	.globl	_Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff
	.type	_Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff, @function
_Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z60__device_stub__Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifffPfS_PKfS1_S1_S1_ifff
	.cfi_endproc
.LFE2033:
	.size	_Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff, .-_Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void Compute_psi_phi_Kernel(float* psi, float* phi, const float* gAbsIx, const float* gAbsIy, const float* gIx, const float* gIy, int nPixels, float norm_for_contrast_num, float norm_for_contrast_denom, float eps)
{
int bx = blockIdx.x;
int tx = threadIdx.x;

int x = bx*blockDim.x + tx;
if (x >= nPixels)
return;


float psi_num = 0, psi_denom = 0;
float phi_num = 0, phi_denom = 0;
if (norm_for_contrast_num == 0)
{
psi_num = 1;
phi_num = 1;
}
else if (norm_for_contrast_num == 1)
{
psi_num = gAbsIx[x];
phi_num = gAbsIy[x];
}
else if (norm_for_contrast_num == 2)
{
psi_num = gAbsIx[x] * gAbsIx[x];
phi_num = gAbsIy[x] * gAbsIy[x];
}
else
{
psi_num = pow(gAbsIx[x], norm_for_contrast_num);
phi_num = pow(gAbsIy[x], norm_for_contrast_num);
}

if (norm_for_contrast_denom == 0)
{
psi_denom = 1;
phi_denom = 1;
}
else if (norm_for_contrast_denom == 1)
{
psi_denom = fabs(gIx[x]) + eps;
phi_denom = fabs(gIy[x]) + eps;
}
else if (norm_for_contrast_denom == 2)
{
psi_denom = gIx[x] * gIx[x] + eps;
phi_denom = gIy[x] * gIy[x] + eps;
}
else
{
psi_denom = pow(fabs(gIx[x]), norm_for_contrast_denom) + eps;
phi_denom = pow(fabs(gIy[x]), norm_for_contrast_denom) + eps;
}
psi[x] = psi_num / psi_denom;
phi[x] = phi_num / phi_denom;

}
	.text
	.file	"Compute_psi_phi_Kernel.hip"
	.globl	_Z37__device_stub__Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff # -- Begin function _Z37__device_stub__Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff
	.type	_Z37__device_stub__Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff,@function
_Z37__device_stub__Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff: # @_Z37__device_stub__Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	12(%rsp), %r9
	movss	%xmm0, (%r9)
	leaq	8(%rsp), %r10
	movss	%xmm1, (%r10)
	leaq	4(%rsp), %r11
	movss	%xmm2, (%r11)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	movq	%r9, 56(%rbx)
	movq	%r10, 64(%rbx)
	movq	%r11, 72(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z37__device_stub__Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff, .Lfunc_end0-_Z37__device_stub__Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff,@object # @_Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff
	.section	.rodata,"a",@progbits
	.globl	_Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff
	.p2align	3, 0x0
_Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff:
	.quad	_Z37__device_stub__Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff
	.size	_Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff"
	.size	.L__unnamed_1, 47

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z37__device_stub__Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff ; -- Begin function _Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff
	.globl	_Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff
	.p2align	8
	.type	_Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff,@function
_Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff: ; @_Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x4c
	s_load_b128 s[4:7], s[0:1], 0x30
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s4, v1
	s_cbranch_execz .LBB0_28
; %bb.1:
	s_clause 0x1
	s_load_b256 s[8:15], s[0:1], 0x0
	s_load_b128 s[16:19], s[0:1], 0x20
	v_cmp_eq_f32_e64 s0, s5, 0
	v_dual_mov_b32 v0, 1.0 :: v_dual_mov_b32 v5, 1.0
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_12
; %bb.2:
	v_cmp_neq_f32_e64 s0, s5, 1.0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB0_5
; %bb.3:
	v_ashrrev_i32_e32 v2, 31, v1
	v_cmp_neq_f32_e64 s0, s5, 2.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s12, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s13, v3, vcc_lo
	s_and_b32 vcc_lo, exec_lo, s0
	global_load_b32 v4, v[4:5], off
	s_cbranch_vccz .LBB0_6
; %bb.4:
	v_add_co_u32 v5, vcc_lo, s14, v2
	v_add_co_ci_u32_e32 v6, vcc_lo, s15, v3, vcc_lo
	s_waitcnt vmcnt(0)
	v_cmp_neq_f32_e32 vcc_lo, 1.0, v4
	s_mov_b32 s1, 0x3e76c4e1
	global_load_b32 v7, v[5:6], off
	v_cndmask_b32_e64 v0, 1.0, s5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_neq_f32_e32 vcc_lo, 0, v0
	v_cmp_neq_f32_e64 s3, v0, |v0|
	v_cndmask_b32_e32 v5, 1.0, v4, vcc_lo
	v_frexp_mant_f32_e64 v8, |v5|
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v8
	v_cndmask_b32_e64 v9, 0, 1, vcc_lo
	v_ldexp_f32 v8, v8, v9
	s_waitcnt vmcnt(0)
	v_cmp_neq_f32_e64 s0, 1.0, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v6, 1.0, s5, s0
	v_cmp_neq_f32_e64 s0, 0, v6
	v_cmp_neq_f32_e64 s20, v6, |v6|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v7, 1.0, v7, s0
	v_frexp_mant_f32_e64 v10, |v7|
	v_cmp_lt_f32_e64 s21, |v7|, 1.0
	v_cmp_class_f32_e64 s22, v7, 0x204
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_gt_f32_e64 s0, 0x3f2aaaab, v10
	s_xor_b32 s20, s20, s21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v12, 0, 1, s0
	v_ldexp_f32 v10, v10, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v9, 1.0, v8 :: v_dual_add_f32 v14, 1.0, v10
	v_rcp_f32_e32 v11, v9
	v_add_f32_e32 v15, -1.0, v9
	v_add_f32_e32 v13, -1.0, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v17, v14
	v_sub_f32_e32 v8, v8, v15
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v12, v13, v11
	v_frexp_exp_i32_f32_e32 v24, v5
	v_cmp_lt_f32_e64 s4, |v5|, 1.0
	v_cmp_class_f32_e64 s5, v5, 0x204
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v16, v9, v12
	s_xor_b32 s3, s3, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v9, v12, v9, -v16
	v_fmac_f32_e32 v9, v12, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v15, -1.0, v10 :: v_dual_add_f32 v18, v16, v9
	v_dual_mul_f32 v8, v15, v17 :: v_dual_add_f32 v19, -1.0, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v20, v14, v8 :: v_dual_sub_f32 v21, v13, v18
	v_sub_f32_e32 v10, v10, v19
	v_sub_f32_e32 v16, v18, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v14, v8, v14, -v20
	v_sub_f32_e32 v13, v13, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v9, v16, v9
	v_fmac_f32_e32 v14, v8, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v10, v13, v18
	v_add_f32_e32 v9, v9, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v9, v21, v9
	v_add_f32_e32 v13, v20, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v9, v11, v9 :: v_dual_sub_f32 v16, v13, v20
	v_sub_f32_e32 v11, v16, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v14, v12, v9
	v_sub_f32_e32 v12, v14, v12
	v_sub_f32_e32 v10, v15, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v15, v15, v10
	v_sub_f32_e32 v13, v15, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v11, v11, v13
	v_dual_add_f32 v10, v10, v11 :: v_dual_sub_f32 v9, v9, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v10, v17, v10
	v_add_f32_e32 v15, v8, v10
	v_mul_f32_e32 v11, v14, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_add_f32 v13, v9, v9 :: v_dual_mul_f32 v16, v15, v15
	v_sub_f32_e32 v8, v15, v8
	v_fma_f32 v12, v14, v14, -v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v8, v10, v8
	v_fmac_f32_e32 v12, v14, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v13, v11, v12
	v_add_f32_e32 v18, v8, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmaak_f32 v10, s1, v13, 0x3e91f4c4
	v_fma_f32 v17, v15, v15, -v16
	v_fmac_f32_e32 v17, v15, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v19, v16, v17
	v_fmaak_f32 v20, s1, v19, 0x3e91f4c4
	v_sub_f32_e32 v11, v13, v11
	v_dual_fmaak_f32 v10, v13, v10, 0x3ecccdef :: v_dual_mul_f32 v23, v14, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v11, v12, v11 :: v_dual_mul_f32 v18, v13, v10
	v_fma_f32 v12, v13, v10, -v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v12, v11, v10
	v_fmaak_f32 v10, v19, v20, 0x3ecccdef
	v_sub_f32_e32 v16, v19, v16
	v_dual_add_f32 v20, v18, v12 :: v_dual_mul_f32 v21, v19, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v16, v17, v16
	v_add_f32_e32 v22, 0x3f2aaaaa, v20
	v_sub_f32_e32 v18, v20, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v17, v19, v10, -v21
	v_sub_f32_e32 v12, v12, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v17, v16, v10
	v_fma_f32 v10, v13, v14, -v23
	v_add_f32_e32 v18, 0xbf2aaaaa, v22
	v_fmac_f32_e32 v10, v13, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v18, v20, v18
	v_ldexp_f32 v9, v9, 1
	v_fmac_f32_e32 v10, v11, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v26, v23, v10
	v_add_f32_e32 v20, v21, v17
	v_sub_f32_e32 v13, v20, v21
	v_mul_f32_e32 v21, v15, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v13, v17, v13
	v_fma_f32 v25, v19, v15, -v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v13, 0x31739010, v13 :: v_dual_add_f32 v12, 0x31739010, v12
	v_fmac_f32_e32 v25, v19, v8
	v_ldexp_f32 v8, v8, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v12, v12, v18
	v_add_f32_e32 v11, v22, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v19, v26, v11 :: v_dual_add_f32 v18, 0x3f2aaaaa, v20
	v_add_f32_e32 v17, 0xbf2aaaaa, v18
	v_fmac_f32_e32 v25, v16, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f32 v16, v26, v11, -v19
	v_ldexp_f32 v15, v15, 1
	v_dual_sub_f32 v17, v20, v17 :: v_dual_sub_f32 v20, v26, v23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v23, v21, v25
	v_add_f32_e32 v13, v13, v17
	v_subrev_co_ci_u32_e32 v17, vcc_lo, 0, v24, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v10, v10, v20
	v_cvt_f32_i32_e32 v17, v17
	v_sub_f32_e32 v22, v22, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v12, v12, v22
	v_fmac_f32_e32 v16, v26, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v16, v10, v11
	v_add_f32_e32 v20, v19, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v22, v18, v13 :: v_dual_sub_f32 v19, v20, v19
	v_sub_f32_e32 v16, v16, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v12, v18, v22
	v_dual_mul_f32 v18, v23, v22 :: v_dual_add_f32 v9, v9, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v10, v23, v21 :: v_dual_add_f32 v11, v13, v12
	v_fma_f32 v12, v23, v22, -v18
	v_mul_f32_e32 v13, 0x3f317218, v17
	v_frexp_exp_i32_f32_e32 v21, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v10, v25, v10
	v_fmac_f32_e32 v12, v23, v11
	v_ldexp_f32 v11, v14, 1
	v_fma_f32 v14, 0x3f317218, v17, -v13
	v_subrev_co_ci_u32_e64 v21, vcc_lo, 0, v21, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v12, v10, v22
	v_cmp_gt_f32_e32 vcc_lo, 0, v0
	v_fmac_f32_e32 v14, 0xb102e308, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_f32_i32_e32 v21, v21
	v_add_f32_e32 v22, v18, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v19, v15, v22
	v_sub_f32_e32 v15, v19, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v15, v22, v15
	v_sub_f32_e32 v18, v22, v18
	v_sub_f32_e32 v12, v12, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v8, v8, v12
	v_add_f32_e32 v8, v8, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v17, v19, v8
	v_dual_add_f32 v10, v11, v20 :: v_dual_sub_f32 v19, v17, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v11, v10, v11
	v_sub_f32_e32 v8, v8, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v11, v20, v11
	v_add_f32_e32 v9, v9, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v11, v13, v14 :: v_dual_add_f32 v12, v10, v9
	v_sub_f32_e32 v13, v11, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v13, v14, v13 :: v_dual_add_f32 v18, v11, v12
	v_sub_f32_e32 v10, v12, v10
	v_dual_sub_f32 v22, v18, v11 :: v_dual_sub_f32 v9, v9, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v14, v18, v22
	v_mul_f32_e32 v20, 0x3f317218, v21
	v_sub_f32_e32 v12, v12, v22
	v_sub_f32_e32 v11, v11, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v16, 0x3f317218, v21, -v20
	v_dual_add_f32 v11, v12, v11 :: v_dual_fmac_f32 v16, 0xb102e308, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v15, v20, v16
	v_sub_f32_e32 v20, v15, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_add_f32 v21, v15, v17 :: v_dual_sub_f32 v14, v16, v20
	v_add_f32_e32 v16, v13, v9
	v_dual_add_f32 v12, v14, v8 :: v_dual_add_f32 v11, v16, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v10, v21, v15
	v_sub_f32_e32 v22, v21, v10
	v_sub_f32_e32 v10, v17, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v17, v12, v14
	v_dual_sub_f32 v15, v15, v22 :: v_dual_sub_f32 v8, v8, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v10, v10, v15 :: v_dual_sub_f32 v15, v16, v13
	v_dual_add_f32 v19, v18, v11 :: v_dual_add_f32 v10, v12, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v16, v16, v15
	v_dual_sub_f32 v9, v9, v15 :: v_dual_sub_f32 v12, v12, v17
	v_add_f32_e32 v15, v21, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v13, v13, v16 :: v_dual_sub_f32 v16, v19, v18
	v_sub_f32_e32 v12, v14, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v14, v15, v21
	v_add_f32_e32 v9, v9, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v11, v11, v16
	v_add_f32_e32 v8, v8, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v10, v10, v14 :: v_dual_add_f32 v9, v9, v11
	v_add_f32_e32 v8, v8, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v10, v19, v9
	v_dual_add_f32 v11, v15, v8 :: v_dual_sub_f32 v12, v10, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v13, v0, v10 :: v_dual_sub_f32 v14, v11, v15
	v_mul_f32_e32 v15, v6, v11
	v_sub_f32_e32 v9, v9, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fma_f32 v10, v0, v10, -v13
	v_cmp_class_f32_e64 s1, v13, 0x204
	v_sub_f32_e32 v8, v8, v14
	v_fma_f32 v11, v6, v11, -v15
	v_fmac_f32_e32 v10, v0, v9
	v_trunc_f32_e32 v9, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v11, v6, v8
	v_mul_f32_e32 v8, 0.5, v0
	v_add_f32_e32 v12, v13, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_eq_f32_e64 s0, v9, v0
	v_add_f32_e32 v14, v15, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_trunc_f32_e32 v17, v8
	v_cndmask_b32_e64 v9, v12, v13, s1
	v_cmp_class_f32_e64 s1, v15, 0x204
	v_sub_f32_e32 v12, v12, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cmp_neq_f32_e64 s2, v17, v8
	v_cndmask_b32_e64 v17, |v0|, 0, s3
	v_cndmask_b32_e64 v16, v14, v15, s1
	v_cmp_eq_f32_e64 s1, 0x42b17218, v9
	v_sub_f32_e32 v10, v10, v12
	v_sub_f32_e32 v14, v14, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v18, 0, 0x37000000, s1
	v_cmp_eq_f32_e64 s1, 0x42b17218, v16
	v_sub_f32_e32 v11, v11, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v20, v9, v18
	v_cndmask_b32_e64 v19, 0, 0x37000000, s1
	v_cmp_eq_f32_e64 s1, 0, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v21, 0x3fb8aa3b, v20 :: v_dual_sub_f32 v8, v16, v19
	s_xor_b32 s3, vcc_lo, s1
	s_and_b32 vcc_lo, s0, s2
	v_cmp_eq_f32_e64 s2, |v5|, 1.0
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f32 v25, 0x3fb8aa3b, v20, -v21
	v_mul_f32_e32 v23, 0x3fb8aa3b, v8
	v_rndne_f32_e32 v26, v21
	v_cndmask_b32_e32 v24, 1.0, v5, vcc_lo
	v_cndmask_b32_e64 v22, 0x7f800000, 0, s3
	v_fmac_f32_e32 v25, 0x32a5705f, v20
	v_fma_f32 v13, 0x3fb8aa3b, v8, -v23
	v_rndne_f32_e32 v27, v23
	v_sub_f32_e32 v21, v21, v26
	v_cmp_gt_f32_e64 s3, 0, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v13, 0x32a5705f, v8 :: v_dual_sub_f32 v12, v23, v27
	v_cndmask_b32_e32 v23, 0, v5, vcc_lo
	v_add_f32_e32 v21, v21, v25
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v9|
	v_cvt_i32_f32_e32 v15, v27
	v_dual_cndmask_b32 v9, 0, v10 :: v_dual_add_f32 v10, v12, v13
	s_delay_alu instid0(VALU_DEP_4)
	v_exp_f32_e32 v13, v21
	v_cvt_i32_f32_e32 v21, v26
	v_cndmask_b32_e64 v12, v17, |v5|, s2
	v_cmp_ngt_f32_e64 s2, 0xc2ce8ed0, v20
	v_exp_f32_e32 v10, v10
	v_bfi_b32 v17, 0x7fffffff, v22, v23
	v_add_f32_e32 v9, v18, v9
	v_trunc_f32_e32 v18, v6
	v_mul_f32_e32 v22, 0.5, v6
	s_delay_alu instid0(TRANS32_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ldexp_f32 v13, v13, v21
	v_cmp_eq_f32_e32 vcc_lo, v18, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(TRANS32_DEP_1)
	v_trunc_f32_e32 v18, v22
	v_ldexp_f32 v10, v10, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v13, 0, v13, s2
	v_cmp_neq_f32_e64 s2, 0x7f800000, |v16|
	v_cndmask_b32_e64 v11, 0, v11, s2
	v_cmp_ngt_f32_e64 s2, 0xc2ce8ed0, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v11, v19, v11
	v_cndmask_b32_e64 v10, 0, v10, s2
	v_cmp_nlt_f32_e64 s2, 0x42b17218, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v13, 0x7f800000, v13, s2
	v_cmp_nlt_f32_e64 s2, 0x42b17218, v8
	v_fma_f32 v9, v13, v9, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v8, 0x7f800000, v10, s2
	v_cmp_eq_f32_e64 s4, 0x7f800000, v13
	v_cmp_neq_f32_e64 s2, v18, v22
	v_fma_f32 v10, v8, v11, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v9, v9, v13, s4
	v_cmp_eq_f32_e64 s4, 0x7f800000, v8
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v11, 1.0, v7, s2
	v_bfi_b32 v9, 0x7fffffff, v9, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v8, v10, v8, s4
	v_cmp_eq_f32_e64 s4, 0, v7
	v_cndmask_b32_e64 v10, |v6|, 0, s20
	v_cndmask_b32_e64 v13, 0x7fc00000, v9, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_bfi_b32 v8, 0x7fffffff, v8, v11
	v_cmp_eq_f32_e64 s0, |v7|, 1.0
	s_xor_b32 s3, s3, s4
	v_cndmask_b32_e64 v11, 0x7f800000, 0, s3
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e32 v14, 0x7fc00000, v8, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0, v5
	v_cndmask_b32_e64 v10, v10, |v7|, s0
	s_mov_b32 s0, 0
	v_cndmask_b32_e32 v9, v9, v13, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0, v7
	v_cndmask_b32_e64 v13, 0, v7, s2
	v_cndmask_b32_e32 v8, v8, v14, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v0, 0x204
	v_cndmask_b32_e32 v9, v9, v12, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v6, 0x204
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v8, v8, v10, vcc_lo
	v_bfi_b32 v10, 0x7fffffff, v11, v13
	s_or_b32 vcc_lo, s1, s5
	v_cndmask_b32_e32 v9, v9, v17, vcc_lo
	s_or_b32 vcc_lo, s4, s22
	v_cndmask_b32_e32 v8, v8, v10, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v5, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v0, 0x7fc00000, v9, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v7, v6
	v_cndmask_b32_e32 v5, 0x7fc00000, v8, vcc_lo
	s_branch .LBB0_7
.LBB0_5:
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr0
	s_branch .LBB0_10
.LBB0_6:
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr0
.LBB0_7:                                ; %Flow104
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_9
; %bb.8:
	v_add_co_u32 v2, vcc_lo, s14, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s15, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_dual_mul_f32 v0, v4, v4 :: v_dual_mul_f32 v5, v2, v2
.LBB0_9:                                ; %Flow105
	s_mov_b32 s0, 0
.LBB0_10:                               ; %Flow106
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_12
; %bb.11:
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s12, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s13, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, s14, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s15, v3, vcc_lo
	global_load_b32 v0, v[4:5], off
	global_load_b32 v5, v[2:3], off
.LBB0_12:
	v_cmp_neq_f32_e64 s0, s6, 0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB0_16
; %bb.13:
	v_cmp_neq_f32_e64 s0, s6, 1.0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB0_17
; %bb.14:
	v_ashrrev_i32_e32 v2, 31, v1
	v_cmp_neq_f32_e64 s0, s6, 2.0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v6, vcc_lo, s16, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s17, v4, vcc_lo
	s_and_b32 vcc_lo, exec_lo, s0
	global_load_b32 v6, v[6:7], off
	s_cbranch_vccz .LBB0_18
; %bb.15:
	v_add_co_u32 v7, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v8, vcc_lo, s19, v4, vcc_lo
	s_waitcnt vmcnt(0)
	v_cmp_neq_f32_e64 s0, |v6|, 1.0
	s_mov_b32 s1, 0x3e76c4e1
	global_load_b32 v7, v[7:8], off
	v_cndmask_b32_e64 v8, 1.0, s6, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_neq_f32_e32 vcc_lo, 0, v8
	v_cmp_neq_f32_e64 s3, v8, |v8|
	v_cndmask_b32_e64 v9, 1.0, |v6|, vcc_lo
	v_frexp_mant_f32_e32 v10, v9
	v_cmp_eq_f32_e64 s2, 0, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v10
	v_cndmask_b32_e64 v11, 0, 1, vcc_lo
	v_ldexp_f32 v10, v10, v11
	s_waitcnt vmcnt(0)
	v_cmp_neq_f32_e64 s0, |v7|, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v12, 1.0, s6, s0
	v_cmp_neq_f32_e64 s0, 0, v12
	v_cmp_neq_f32_e64 s4, v12, |v12|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v7, 1.0, |v7|, s0
	v_frexp_mant_f32_e32 v13, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_f32_e64 s0, 0x3f2aaaab, v13
	v_cndmask_b32_e64 v15, 0, 1, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ldexp_f32 v13, v13, v15
	v_add_f32_e32 v11, 1.0, v10
	v_dual_add_f32 v16, -1.0, v10 :: v_dual_add_f32 v17, 1.0, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v18, -1.0, v11
	v_rcp_f32_e32 v20, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v10, v10, v18
	v_add_f32_e32 v18, -1.0, v13
	v_rcp_f32_e32 v14, v11
	s_waitcnt_depctr 0xfff
	v_dual_add_f32 v22, -1.0, v17 :: v_dual_mul_f32 v15, v16, v14
	v_mul_f32_e32 v19, v11, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v11, v15, v11, -v19
	v_dual_fmac_f32 v11, v15, v10 :: v_dual_mul_f32 v10, v18, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v21, v19, v11
	v_dual_mul_f32 v23, v17, v10 :: v_dual_sub_f32 v24, v16, v21
	v_sub_f32_e32 v13, v13, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v17, v10, v17, -v23
	v_dual_sub_f32 v16, v16, v24 :: v_dual_fmac_f32 v17, v10, v13
	v_sub_f32_e32 v19, v21, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v13, v16, v21
	v_add_f32_e32 v16, v23, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v11, v19, v11
	v_sub_f32_e32 v19, v16, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v11, v11, v13
	v_sub_f32_e32 v13, v18, v16
	v_add_f32_e32 v11, v24, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v11, v14, v11 :: v_dual_sub_f32 v14, v19, v17
	v_sub_f32_e32 v18, v18, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v16, v18, v16
	v_add_f32_e32 v14, v14, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v13, v13, v14
	v_mul_f32_e32 v13, v20, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v18, v10, v13
	v_sub_f32_e32 v10, v18, v10
	v_mul_f32_e32 v19, v18, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v10, v13, v10
	v_fma_f32 v20, v18, v18, -v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v21, v10, v10
	v_dual_add_f32 v17, v15, v11 :: v_dual_fmac_f32 v20, v18, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v14, v17, v17
	v_dual_sub_f32 v15, v17, v15 :: v_dual_add_f32 v22, v19, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v11, v11, v15
	v_fma_f32 v15, v17, v17, -v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v19, v22, v19
	v_dual_fmaak_f32 v23, s1, v22, 0x3e91f4c4 :: v_dual_add_f32 v16, v11, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v19, v20, v19
	v_fmac_f32_e32 v15, v17, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v16, v14, v15
	v_dual_sub_f32 v14, v16, v14 :: v_dual_fmaak_f32 v13, s1, v16, 0x3e91f4c4
	v_mul_f32_e32 v26, v17, v16
	v_cmp_eq_f32_e64 s1, 0x7f800000, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v14, v15, v14 :: v_dual_fmaak_f32 v13, v16, v13, 0x3ecccdef
	v_fma_f32 v27, v16, v17, -v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v21, v16, v13
	v_fma_f32 v15, v16, v13, -v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v15, v14, v13
	v_fmaak_f32 v13, v22, v23, 0x3ecccdef
	v_dual_add_f32 v23, v21, v15 :: v_dual_mul_f32 v24, v22, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v25, 0x3f2aaaaa, v23
	v_fma_f32 v20, v22, v13, -v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v20, v19, v13
	v_frexp_exp_i32_f32_e32 v13, v9
	v_subrev_co_ci_u32_e32 v13, vcc_lo, 0, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v13, v13
	v_fmac_f32_e32 v27, v16, v11
	v_ldexp_f32 v11, v11, 1
	v_fmac_f32_e32 v27, v14, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v29, v26, v27
	v_sub_f32_e32 v21, v23, v21
	v_sub_f32_e32 v15, v15, v21
	v_add_f32_e32 v21, 0xbf2aaaaa, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v15, 0x31739010, v15
	v_sub_f32_e32 v21, v23, v21
	v_add_f32_e32 v23, v24, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v15, v15, v21
	v_sub_f32_e32 v16, v23, v24
	v_dual_mul_f32 v24, v18, v22 :: v_dual_add_f32 v21, 0x3f2aaaaa, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v16, v20, v16
	v_fma_f32 v28, v22, v18, -v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v20, 0xbf2aaaaa, v21
	v_add_f32_e32 v16, 0x31739010, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v28, v22, v10
	v_add_f32_e32 v14, v25, v15
	v_dual_sub_f32 v20, v23, v20 :: v_dual_sub_f32 v23, v29, v26
	v_ldexp_f32 v10, v10, 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v28, v19, v18
	v_sub_f32_e32 v25, v25, v14
	v_mul_f32_e32 v22, v29, v14
	v_add_f32_e32 v16, v16, v20
	v_sub_f32_e32 v20, v27, v23
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v15, v15, v25
	v_fma_f32 v19, v29, v14, -v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f32_e32 v23, v21, v16
	v_add_f32_e32 v25, v24, v28
	v_fmac_f32_e32 v19, v29, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v21, v21, v23
	v_dual_mul_f32 v26, v25, v23 :: v_dual_fmac_f32 v19, v20, v14
	v_ldexp_f32 v14, v17, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v16, v16, v21
	v_fma_f32 v20, v25, v23, -v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v21, v22, v19 :: v_dual_fmac_f32 v20, v25, v16
	v_add_f32_e32 v16, v14, v21
	v_sub_f32_e32 v22, v21, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v14, v16, v14
	v_sub_f32_e32 v19, v19, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v14, v21, v14 :: v_dual_add_f32 v11, v11, v19
	v_add_f32_e32 v11, v11, v14
	v_sub_f32_e32 v17, v25, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v17, v28, v17
	v_fmac_f32_e32 v20, v17, v23
	v_ldexp_f32 v17, v18, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v18, v26, v20
	v_sub_f32_e32 v22, v18, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v21, v17, v18
	v_dual_sub_f32 v20, v20, v22 :: v_dual_mul_f32 v15, 0x3f317218, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v17, v21, v17 :: v_dual_add_f32 v10, v10, v20
	v_fma_f32 v24, 0x3f317218, v13, -v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v17, v18, v17 :: v_dual_add_f32 v18, v16, v11
	v_fmac_f32_e32 v24, 0xb102e308, v13
	v_frexp_exp_i32_f32_e32 v13, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v10, v10, v17
	v_sub_f32_e32 v16, v18, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v14, v15, v24
	v_subrev_co_ci_u32_e64 v13, vcc_lo, 0, v13, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v11, v11, v16
	v_cmp_gt_f32_e64 s0, 1.0, v9
	v_sub_f32_e32 v15, v14, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f32_i32_e32 v13, v13
	s_xor_b32 s0, s3, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v19, 0x3f317218, v13
	v_cndmask_b32_e64 v28, |v8|, 0, s0
	v_fma_f32 v22, 0x3f317218, v13, -v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v22, 0xb102e308, v13 :: v_dual_add_f32 v13, v14, v18
	v_sub_f32_e32 v23, v13, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v16, v18, v23
	v_add_f32_e32 v20, v21, v10
	v_dual_sub_f32 v26, v13, v23 :: v_dual_sub_f32 v21, v20, v21
	v_add_f32_e32 v17, v19, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v14, v14, v26
	v_dual_sub_f32 v10, v10, v21 :: v_dual_add_f32 v25, v17, v20
	v_sub_f32_e32 v15, v24, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v14, v16, v14
	v_dual_sub_f32 v18, v25, v17 :: v_dual_add_f32 v23, v15, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v24, v25, v18
	v_dual_sub_f32 v19, v17, v19 :: v_dual_sub_f32 v18, v20, v18
	v_dual_add_f32 v14, v23, v14 :: v_dual_sub_f32 v17, v17, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v16, v22, v19
	v_sub_f32_e32 v19, v23, v15
	v_dual_add_f32 v17, v18, v17 :: v_dual_add_f32 v20, v16, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v18, v23, v19 :: v_dual_add_f32 v21, v13, v14
	v_sub_f32_e32 v11, v11, v19
	v_sub_f32_e32 v19, v20, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v15, v15, v18
	v_dual_sub_f32 v13, v21, v13 :: v_dual_sub_f32 v18, v20, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v11, v11, v15
	v_sub_f32_e32 v13, v14, v13
	v_sub_f32_e32 v10, v10, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v14, v16, v18 :: v_dual_add_f32 v11, v11, v13
	v_add_f32_e32 v10, v10, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v14, v21, v11 :: v_dual_add_f32 v17, v20, v17
	v_add_f32_e32 v20, v25, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v15, v20, v25
	v_sub_f32_e32 v13, v17, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v15, v8, v14 :: v_dual_add_f32 v10, v10, v13
	v_sub_f32_e32 v13, v14, v21
	v_cmp_class_f32_e64 vcc_lo, v15, 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_add_f32 v16, v20, v10 :: v_dual_sub_f32 v11, v11, v13
	v_fma_f32 v13, v8, v14, -v15
	v_sub_f32_e32 v14, v16, v20
	v_mul_f32_e32 v17, v12, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v13, v8, v11 :: v_dual_sub_f32 v10, v10, v14
	v_fma_f32 v11, v12, v16, -v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v14, v15, v13 :: v_dual_fmac_f32 v11, v12, v10
	v_cndmask_b32_e32 v10, v14, v15, vcc_lo
	v_sub_f32_e32 v14, v14, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v16, v17, v11
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v13, v13, v14
	v_cndmask_b32_e64 v18, 0, 0x37000000, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v17, 0x204
	v_dual_sub_f32 v20, v10, v18 :: v_dual_cndmask_b32 v19, v16, v17
	v_sub_f32_e32 v16, v16, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v22, 0x3fb8aa3b, v20
	v_cmp_eq_f32_e32 vcc_lo, 0x42b17218, v19
	v_cmp_ngt_f32_e64 s3, 0xc2ce8ed0, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v11, v11, v16
	v_fma_f32 v24, 0x3fb8aa3b, v20, -v22
	v_cndmask_b32_e64 v21, 0, 0x37000000, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0, v8
	v_rndne_f32_e32 v26, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v24, 0x32a5705f, v20 :: v_dual_sub_f32 v23, v19, v21
	s_xor_b32 s0, vcc_lo, s2
	v_sub_f32_e32 v22, v22, v26
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v10|
	s_delay_alu instid0(VALU_DEP_2)
	v_add_f32_e32 v14, v22, v24
	v_cndmask_b32_e32 v10, 0, v13, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 1.0, v9
	v_mul_f32_e32 v25, 0x3fb8aa3b, v23
	v_cndmask_b32_e64 v22, 0x7f800000, 0, s0
	v_exp_f32_e32 v13, v14
	v_add_f32_e32 v10, v18, v10
	v_cndmask_b32_e32 v14, v28, v9, vcc_lo
	v_fma_f32 v15, 0x3fb8aa3b, v23, -v25
	v_rndne_f32_e32 v27, v25
	v_cvt_i32_f32_e32 v18, v26
	v_cmp_gt_f32_e64 s0, 1.0, v7
	v_cmp_gt_f32_e32 vcc_lo, 0, v12
	v_fmac_f32_e32 v15, 0x32a5705f, v23
	v_sub_f32_e32 v25, v25, v27
	v_ldexp_f32 v13, v13, v18
	v_cvt_i32_f32_e32 v17, v27
	s_xor_b32 s0, s4, s0
	v_cmp_class_f32_e64 s4, v8, 0x204
	v_add_f32_e32 v15, v25, v15
	v_cndmask_b32_e64 v13, 0, v13, s3
	v_cmp_neq_f32_e64 s3, 0x7f800000, |v19|
	v_cndmask_b32_e64 v16, |v12|, 0, s0
	v_cmp_eq_f32_e64 s0, 0x7f800000, v7
	v_exp_f32_e32 v15, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v11, 0, v11, s3
	v_cmp_ngt_f32_e64 s3, 0xc2ce8ed0, v23
	v_add_f32_e32 v11, v21, v11
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v15, v15, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v15, 0, v15, s3
	v_cmp_nlt_f32_e64 s3, 0x42b17218, v20
	v_cndmask_b32_e64 v13, 0x7f800000, v13, s3
	v_cmp_nlt_f32_e64 s3, 0x42b17218, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v10, v13, v10, v13
	v_cndmask_b32_e64 v15, 0x7f800000, v15, s3
	v_cmp_eq_f32_e64 s3, 1.0, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v11, v15, v11, v15
	v_cndmask_b32_e64 v16, v16, v7, s3
	v_cmp_eq_f32_e64 s3, 0x7f800000, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v10, v10, v13, s3
	v_cmp_eq_f32_e64 s3, 0x7f800000, v15
	v_cndmask_b32_e64 v10, |v10|, v14, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v11, v11, v15, s3
	v_cmp_eq_f32_e64 s3, 0, v7
	v_cmp_class_f32_e64 s4, v12, 0x204
	v_cndmask_b32_e64 v11, |v11|, v16, s4
	s_delay_alu instid0(VALU_DEP_3)
	s_xor_b32 s4, vcc_lo, s3
	s_or_b32 vcc_lo, s2, s1
	v_cndmask_b32_e64 v13, 0x7f800000, 0, s4
	v_cndmask_b32_e32 v10, v10, v22, vcc_lo
	s_or_b32 vcc_lo, s3, s0
	s_mov_b32 s0, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v11, v11, v13, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v9, v8
	v_cndmask_b32_e32 v8, 0x7fc00000, v10, vcc_lo
	v_cmp_o_f32_e32 vcc_lo, v7, v12
	v_add_f32_e32 v7, s7, v8
	v_cndmask_b32_e32 v9, 0x7fc00000, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v8, s7, v9
	s_branch .LBB0_19
.LBB0_16:
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr8
                                        ; implicit-def: $vgpr7
	s_branch .LBB0_25
.LBB0_17:
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr8
                                        ; implicit-def: $vgpr7
	s_branch .LBB0_22
.LBB0_18:
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr8
                                        ; implicit-def: $vgpr7
.LBB0_19:                               ; %Flow
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_21
; %bb.20:
	v_add_co_u32 v3, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s19, v4, vcc_lo
	s_waitcnt vmcnt(0)
	v_fma_f32 v7, v6, v6, s7
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(0)
	v_fma_f32 v8, v3, v3, s7
.LBB0_21:                               ; %Flow100
	s_mov_b32 s0, 0
.LBB0_22:                               ; %Flow101
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_24
; %bb.23:
	v_ashrrev_i32_e32 v2, 31, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v6, vcc_lo, s16, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s17, v4, vcc_lo
	v_add_co_u32 v3, vcc_lo, s18, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s19, v4, vcc_lo
	global_load_b32 v6, v[6:7], off
	global_load_b32 v3, v[3:4], off
	s_waitcnt vmcnt(1)
	v_add_f32_e64 v7, |v6|, s7
	s_waitcnt vmcnt(0)
	v_add_f32_e64 v8, |v3|, s7
.LBB0_24:                               ; %Flow102
	s_mov_b32 s0, 0
.LBB0_25:                               ; %Flow103
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_27
; %bb.26:                               ; %._crit_edge
	v_ashrrev_i32_e32 v2, 31, v1
	v_dual_mov_b32 v7, 1.0 :: v_dual_mov_b32 v8, 1.0
.LBB0_27:
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v3, null, v7, v7, v0
	s_waitcnt vmcnt(0)
	v_div_scale_f32 v4, null, v8, v8, v5
	v_div_scale_f32 v12, vcc_lo, v0, v7, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v6, v3
	v_rcp_f32_e32 v9, v4
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_waitcnt_depctr 0xfff
	v_fma_f32 v10, -v3, v6, 1.0
	v_fma_f32 v11, -v4, v9, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v6, v10, v6 :: v_dual_fmac_f32 v9, v11, v9
	v_div_scale_f32 v10, s0, v5, v8, v5
	v_mul_f32_e32 v11, v12, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v13, v10, v9
	v_fma_f32 v14, -v3, v11, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v15, -v4, v13, v10
	v_fmac_f32_e32 v11, v14, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v13, v15, v9
	v_fma_f32 v3, -v3, v11, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v4, -v4, v13, v10
	v_div_fmas_f32 v6, v3, v6, v11
	s_mov_b32 vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_2)
	v_div_fmas_f32 v9, v4, v9, v13
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v3, vcc_lo, s8, v1
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v2, vcc_lo
	v_div_fixup_f32 v6, v6, v7, v0
	v_add_co_u32 v0, vcc_lo, s10, v1
	v_div_fixup_f32 v5, v9, v8, v5
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v2, vcc_lo
	global_store_b32 v[3:4], v6, off
	global_store_b32 v[0:1], v5, off
.LBB0_28:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 30
		.amdhsa_next_free_sgpr 23
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff, .Lfunc_end0-_Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 5316
; NumSgprs: 25
; NumVgprs: 30
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 25
; NumVGPRsForWavesPerEU: 30
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         60
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         68
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         76
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         78
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         80
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         82
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         84
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         86
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         128
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 320
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff
    .private_segment_fixed_size: 0
    .sgpr_count:     25
    .sgpr_spill_count: 0
    .symbol:         _Z22Compute_psi_phi_KernelPfS_PKfS1_S1_S1_ifff.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     30
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
