#include<stdio.h>
#include<stdlib.h>
#include<sys/time.h>


#define CUDA_ERROR_EXIT(str) do{\
                                    cudaError err = cudaGetLastError();\
                                    if( err != cudaSuccess){\
                                             printf("Cuda Error: '%s' for %s\n", cudaGetErrorString(err), str);\
                                             exit(-1);\
                                    }\
                             }while(0);
#define TDIFF(start, end) ((end.tv_sec - start.tv_sec) * 1000000UL + (end.tv_usec - start.tv_usec))

__global__ void reduce(int* input, int n){
  unsigned int tid=threadIdx.x;
  unsigned int i=blockDim.x * blockIdx.x + threadIdx.x;
  unsigned int offset = blockDim.x * blockIdx.x;
  __syncthreads();
    for(unsigned int s=1; s<blockDim.x; s*=2){
      if(tid % (2*s)==0){
        input[i] = (i + s < offset + blockDim.x && i+s < n)? input[i] ^ input[i + s] : input[i];
        printf("input[%d]= %d offset= %ld\n",i,input[i],offset);
      }
      __syncthreads();
    }
}

int main(int argc, char** argv){
  struct timeval start, end, t_start, t_end;
  int i,n = atoi(argv[1]);
  int seed= atoi(argv[2]);
  int * array;
  int blocks;
  int result=0;
  int threads=10;
  array=(int*)malloc(n * sizeof(int));

  srand(seed);
  for(i=0;i<n;i++){
    array[i]=random();
    printf("a[%d]= %d\n",i,array[i]);
  }

  int *gpu_array;

  gettimeofday(&t_start, NULL);

  cudaMalloc(&gpu_array, n*sizeof(int));
  CUDA_ERROR_EXIT("cudaMalloc");

  cudaMemcpy(gpu_array, array, n*sizeof(int), cudaMemcpyHostToDevice);
  CUDA_ERROR_EXIT("cudaMemcpy");

  gettimeofday(&start, NULL);

  blocks= (n + threads -1)/threads;

  reduce<<<blocks,threads>>>(gpu_array,n);
  CUDA_ERROR_EXIT("kernel invocation");
  gettimeofday(&end, NULL);

  cudaMemcpy(array, gpu_array, n*sizeof(int), cudaMemcpyDeviceToHost);
  CUDA_ERROR_EXIT("memcpy");

  for(i=0;i<n;i+=threads){
    result = result ^ array[i];
    printf("result= %d\n",result);
  }
  gettimeofday(&t_end, NULL);
  printf("Total time = %ld microsecs Processsing =%ld microsecs\n", TDIFF(t_start, t_end), TDIFF(start, end));
  cudaFree(gpu_array);

}

	.file	"tmpxft_00397540_00000000-6_q2.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z26__device_stub__Z6reducePiiPii
	.type	_Z26__device_stub__Z6reducePiiPii, @function
_Z26__device_stub__Z6reducePiiPii:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movl	%esi, 4(%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z6reducePii(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L2:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z26__device_stub__Z6reducePiiPii, .-_Z26__device_stub__Z6reducePiiPii
	.globl	_Z6reducePii
	.type	_Z6reducePii, @function
_Z6reducePii:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z26__device_stub__Z6reducePiiPii
	.cfi_endproc
.LFE2053:
	.size	_Z6reducePii, .-_Z6reducePii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"a[%d]= %d\n"
.LC1:
	.string	"cudaMalloc"
.LC2:
	.string	"Cuda Error: '%s' for %s\n"
.LC3:
	.string	"cudaMemcpy"
.LC4:
	.string	"kernel invocation"
.LC5:
	.string	"memcpy"
.LC6:
	.string	"result= %d\n"
.LC7:
	.string	"Total time = %ld microsecs Processsing =%ld microsecs\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	leaq	.LC0(%rip), %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rsi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	8(%rsi), %rdi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	call	atoi@PLT
	movq	16(%rbp), %rdi
	movslq	%eax, %r12
	call	atoi@PLT
	movq	%r12, %rbx
	salq	$2, %r12
	movl	%eax, %r13d
	movq	%r12, %rdi
	call	malloc@PLT
	movl	%r13d, %edi
	xorl	%r13d, %r13d
	movq	%rax, %rbp
	call	srand@PLT
.L9:
	movl	%r13d, %r15d
	cmpl	%r13d, %ebx
	jle	.L22
	call	random@PLT
	movl	%r15d, %edx
	movq	%r14, %rsi
	movl	$2, %edi
	movl	%eax, 0(%rbp,%r13,4)
	movl	%eax, %ecx
	xorl	%eax, %eax
	incq	%r13
	call	__printf_chk@PLT
	jmp	.L9
.L22:
	leaq	40(%rsp), %rdi
	xorl	%esi, %esi
	call	gettimeofday@PLT
	movq	%rsp, %rdi
	movq	%r12, %rsi
	call	cudaMalloc@PLT
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L11
	call	cudaGetErrorString@PLT
	leaq	.LC1(%rip), %rcx
	movq	%rax, %rdx
	jmp	.L21
.L11:
	movq	(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rdx
	movq	%rbp, %rsi
	call	cudaMemcpy@PLT
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L12
	call	cudaGetErrorString@PLT
	leaq	.LC3(%rip), %rcx
	movq	%rax, %rdx
.L21:
	movl	$2, %edi
	leaq	.LC2(%rip), %rsi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	orl	$-1, %edi
	call	exit@PLT
.L12:
	xorl	%esi, %esi
	leaq	8(%rsp), %rdi
	call	gettimeofday@PLT
	leal	9(%rbx), %eax
	movl	$10, %esi
	xorl	%r9d, %r9d
	cltd
	movl	$2147483653, %ecx
	xorl	%r8d, %r8d
	movl	$1, 64(%rsp)
	idivl	%esi
	addq	%rcx, %rcx
	movq	%rcx, 56(%rsp)
	movq	%rcx, %rdx
	movl	$1, %ecx
	movl	%eax, 24(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 28(%rsp)
	movq	24(%rsp), %rdi
	movl	32(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	movq	(%rsp), %rdi
	movl	%ebx, %esi
	call	_Z26__device_stub__Z6reducePiiPii
.L13:
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L14
	call	cudaGetErrorString@PLT
	leaq	.LC4(%rip), %rcx
	movq	%rax, %rdx
	jmp	.L21
.L14:
	leaq	24(%rsp), %rdi
	xorl	%esi, %esi
	xorl	%r13d, %r13d
	call	gettimeofday@PLT
	movq	(%rsp), %rsi
	movq	%r12, %rdx
	movq	%rbp, %rdi
	movl	$2, %ecx
	xorl	%r12d, %r12d
	leaq	.LC6(%rip), %r14
	call	cudaMemcpy@PLT
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L15
	call	cudaGetErrorString@PLT
	leaq	.LC5(%rip), %rcx
	movq	%rax, %rdx
	jmp	.L21
.L15:
	cmpl	%r12d, %ebx
	jle	.L23
	xorl	0(%rbp,%r12,4), %r13d
	movq	%r14, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	movl	%r13d, %edx
	addq	$10, %r12
	call	__printf_chk@PLT
	jmp	.L15
.L23:
	xorl	%esi, %esi
	leaq	56(%rsp), %rdi
	call	gettimeofday@PLT
	movq	24(%rsp), %rcx
	movq	56(%rsp), %rdx
	xorl	%eax, %eax
	subq	8(%rsp), %rcx
	subq	40(%rsp), %rdx
	movl	$2, %edi
	imulq	$1000000, %rcx, %rcx
	leaq	.LC7(%rip), %rsi
	addq	32(%rsp), %rcx
	subq	16(%rsp), %rcx
	imulq	$1000000, %rdx, %rdx
	addq	64(%rsp), %rdx
	subq	48(%rsp), %rdx
	call	__printf_chk@PLT
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC8:
	.string	"_Z6reducePii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC8(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z6reducePii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include<stdio.h>
#include<stdlib.h>
#include<sys/time.h>


#define CUDA_ERROR_EXIT(str) do{\
                                    hipError_t err = hipGetLastError();\
                                    if( err != hipSuccess){\
                                             printf("Cuda Error: '%s' for %s\n", hipGetErrorString(err), str);\
                                             exit(-1);\
                                    }\
                             }while(0);
#define TDIFF(start, end) ((end.tv_sec - start.tv_sec) * 1000000UL + (end.tv_usec - start.tv_usec))

__global__ void reduce(int* input, int n){
  unsigned int tid=threadIdx.x;
  unsigned int i=blockDim.x * blockIdx.x + threadIdx.x;
  unsigned int offset = blockDim.x * blockIdx.x;
  __syncthreads();
    for(unsigned int s=1; s<blockDim.x; s*=2){
      if(tid % (2*s)==0){
        input[i] = (i + s < offset + blockDim.x && i+s < n)? input[i] ^ input[i + s] : input[i];
        printf("input[%d]= %d offset= %ld\n",i,input[i],offset);
      }
      __syncthreads();
    }
}

int main(int argc, char** argv){
  struct timeval start, end, t_start, t_end;
  int i,n = atoi(argv[1]);
  int seed= atoi(argv[2]);
  int * array;
  int blocks;
  int result=0;
  int threads=10;
  array=(int*)malloc(n * sizeof(int));

  srand(seed);
  for(i=0;i<n;i++){
    array[i]=random();
    printf("a[%d]= %d\n",i,array[i]);
  }

  int *gpu_array;

  gettimeofday(&t_start, NULL);

  hipMalloc(&gpu_array, n*sizeof(int));
  CUDA_ERROR_EXIT("hipMalloc");

  hipMemcpy(gpu_array, array, n*sizeof(int), hipMemcpyHostToDevice);
  CUDA_ERROR_EXIT("hipMemcpy");

  gettimeofday(&start, NULL);

  blocks= (n + threads -1)/threads;

  reduce<<<blocks,threads>>>(gpu_array,n);
  CUDA_ERROR_EXIT("kernel invocation");
  gettimeofday(&end, NULL);

  hipMemcpy(array, gpu_array, n*sizeof(int), hipMemcpyDeviceToHost);
  CUDA_ERROR_EXIT("memcpy");

  for(i=0;i<n;i+=threads){
    result = result ^ array[i];
    printf("result= %d\n",result);
  }
  gettimeofday(&t_end, NULL);
  printf("Total time = %ld microsecs Processsing =%ld microsecs\n", TDIFF(t_start, t_end), TDIFF(start, end));
  hipFree(gpu_array);

}

	.text
	.file	"q2.hip"
	.globl	_Z21__device_stub__reducePii    # -- Begin function _Z21__device_stub__reducePii
	.type	_Z21__device_stub__reducePii,@function
_Z21__device_stub__reducePii:           # @_Z21__device_stub__reducePii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6reducePii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z21__device_stub__reducePii, .Lfunc_end0-_Z21__device_stub__reducePii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsi, %r14
	movq	8(%rsi), %rdi
	callq	atoi
	movl	%eax, %ebx
	movq	16(%r14), %rdi
	callq	atoi
	movl	%eax, %ebp
	movslq	%ebx, %r15
	shlq	$2, %r15
	movq	%r15, %rdi
	callq	malloc
	movq	%rax, %r14
	movl	%ebp, %edi
	callq	srand
	testl	%ebx, %ebx
	jle	.LBB1_3
# %bb.1:                                # %.lr.ph.preheader
	movl	%ebx, %r13d
	xorl	%r12d, %r12d
.LBB1_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	callq	random
	movl	%eax, (%r14,%r12,4)
	movl	$.L.str, %edi
	movl	%r12d, %esi
	movl	%eax, %edx
	xorl	%eax, %eax
	callq	printf
	incq	%r12
	cmpq	%r12, %r13
	jne	.LBB1_2
.LBB1_3:                                # %._crit_edge
	leaq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movq	%rsp, %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB1_4
# %bb.6:
	movq	(%rsp), %rdi
	movq	%r14, %rsi
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB1_7
# %bb.8:
	leaq	40(%rsp), %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	leal	9(%rbx), %eax
	cltq
	imulq	$1717986919, %rax, %rdi         # imm = 0x66666667
	movq	%rdi, %rax
	shrq	$63, %rax
	sarq	$34, %rdi
	addl	%eax, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$10, %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_10
# %bb.9:
	movq	(%rsp), %rdi
	movl	%ebx, %esi
	callq	_Z21__device_stub__reducePii
.LBB1_10:
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB1_11
# %bb.12:
	leaq	24(%rsp), %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movq	(%rsp), %rsi
	movq	%r14, %rdi
	movq	%r15, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB1_17
# %bb.13:                               # %.preheader
	testl	%ebx, %ebx
	jle	.LBB1_16
# %bb.14:                               # %.lr.ph58.preheader
	xorl	%r15d, %r15d
	xorl	%ebp, %ebp
.LBB1_15:                               # %.lr.ph58
                                        # =>This Inner Loop Header: Depth=1
	xorl	(%r14,%r15,4), %ebp
	movl	$.L.str.6, %edi
	movl	%ebp, %esi
	xorl	%eax, %eax
	callq	printf
	addq	$10, %r15
	cmpl	%r15d, %ebx
	jg	.LBB1_15
.LBB1_16:                               # %._crit_edge59
	leaq	56(%rsp), %rbx
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	gettimeofday
	movq	(%rbx), %rax
	movq	8(%rbx), %rsi
	subq	8(%rsp), %rax
	imulq	$1000000, %rax, %rax            # imm = 0xF4240
	subq	16(%rsp), %rsi
	addq	%rax, %rsi
	movq	24(%rsp), %rax
	movq	32(%rsp), %rdx
	subq	40(%rsp), %rax
	imulq	$1000000, %rax, %rax            # imm = 0xF4240
	subq	48(%rsp), %rdx
	addq	%rax, %rdx
	movl	$.L.str.7, %edi
	xorl	%eax, %eax
	callq	printf
	movq	(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB1_4:
	.cfi_def_cfa_offset 128
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %edi
	movl	$.L.str.2, %edx
	jmp	.LBB1_5
.LBB1_7:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %edi
	movl	$.L.str.3, %edx
	jmp	.LBB1_5
.LBB1_11:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %edi
	movl	$.L.str.4, %edx
	jmp	.LBB1_5
.LBB1_17:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.1, %edi
	movl	$.L.str.5, %edx
.LBB1_5:
	movq	%rax, %rsi
	xorl	%eax, %eax
	callq	printf
	movl	$-1, %edi
	callq	exit
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6reducePii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z6reducePii,@object            # @_Z6reducePii
	.section	.rodata,"a",@progbits
	.globl	_Z6reducePii
	.p2align	3, 0x0
_Z6reducePii:
	.quad	_Z21__device_stub__reducePii
	.size	_Z6reducePii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"a[%d]= %d\n"
	.size	.L.str, 11

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Cuda Error: '%s' for %s\n"
	.size	.L.str.1, 25

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"hipMalloc"
	.size	.L.str.2, 10

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"hipMemcpy"
	.size	.L.str.3, 10

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"kernel invocation"
	.size	.L.str.4, 18

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"memcpy"
	.size	.L.str.5, 7

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"result= %d\n"
	.size	.L.str.6, 12

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"Total time = %ld microsecs Processsing =%ld microsecs\n"
	.size	.L.str.7, 55

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z6reducePii"
	.size	.L__unnamed_1, 13

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z21__device_stub__reducePii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z6reducePii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z6reducePii            ; -- Begin function _Z6reducePii
	.globl	_Z6reducePii
	.p2align	8
	.type	_Z6reducePii,@function
_Z6reducePii:                           ; @_Z6reducePii
; %bb.0:
	s_load_b32 s4, s[0:1], 0x1c
	s_add_u32 s2, s0, 16
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_b32 s20, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lt_u32 s20, 2
	s_cbranch_scc1 .LBB0_231
; %bb.1:                                ; %.lr.ph
	s_clause 0x1
	s_load_b64 s[8:9], s[0:1], 0x0
	s_load_b32 s0, s[0:1], 0x8
	v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v6, 2
	s_mul_i32 s21, s15, s20
	v_mbcnt_lo_u32_b32 v37, -1, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_mov_b32 v34, v3 :: v_dual_add_nc_u32 v33, s21, v0
	v_mov_b32_e32 v7, 1
	s_mov_b32 s4, 0
	s_add_i32 s1, s21, s20
	s_mov_b32 s23, s4
	v_lshlrev_b64 v[1:2], 2, v[33:34]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v35, vcc_lo, s8, v1
	v_add_co_ci_u32_e32 v36, vcc_lo, s9, v2, vcc_lo
	v_mov_b32_e32 v1, 33
	s_min_u32 s22, s1, s0
	s_mov_b32 s0, 1
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_8 Depth 2
                                        ;     Child Loop BB0_16 Depth 2
                                        ;     Child Loop BB0_22 Depth 2
                                        ;     Child Loop BB0_31 Depth 2
                                        ;     Child Loop BB0_34 Depth 2
                                        ;       Child Loop BB0_37 Depth 3
                                        ;       Child Loop BB0_45 Depth 3
                                        ;       Child Loop BB0_53 Depth 3
                                        ;       Child Loop BB0_61 Depth 3
                                        ;       Child Loop BB0_69 Depth 3
                                        ;       Child Loop BB0_77 Depth 3
                                        ;       Child Loop BB0_85 Depth 3
                                        ;       Child Loop BB0_93 Depth 3
                                        ;       Child Loop BB0_101 Depth 3
                                        ;       Child Loop BB0_107 Depth 3
                                        ;       Child Loop BB0_116 Depth 3
                                        ;     Child Loop BB0_124 Depth 2
                                        ;     Child Loop BB0_132 Depth 2
                                        ;     Child Loop BB0_138 Depth 2
                                        ;     Child Loop BB0_147 Depth 2
                                        ;     Child Loop BB0_152 Depth 2
                                        ;     Child Loop BB0_160 Depth 2
                                        ;     Child Loop BB0_166 Depth 2
                                        ;     Child Loop BB0_175 Depth 2
                                        ;     Child Loop BB0_179 Depth 2
                                        ;     Child Loop BB0_187 Depth 2
                                        ;     Child Loop BB0_193 Depth 2
                                        ;     Child Loop BB0_202 Depth 2
                                        ;     Child Loop BB0_206 Depth 2
                                        ;     Child Loop BB0_214 Depth 2
                                        ;     Child Loop BB0_220 Depth 2
                                        ;     Child Loop BB0_229 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s24, s0, 1
	s_mov_b32 s25, exec_lo
	s_add_i32 s1, s24, -1
	v_and_b32_e32 v2, s1, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB0_230
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	global_load_b32 v10, v[35:36], off
	v_add_nc_u32_e32 v2, s0, v33
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 s22, v2
	s_cbranch_execz .LBB0_5
; %bb.4:                                ;   in Loop: Header=BB0_2 Depth=1
	v_lshlrev_b64 v[4:5], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s8, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
	global_load_b32 v2, v[4:5], off
	s_waitcnt vmcnt(0)
	v_xor_b32_e32 v10, v2, v10
.LBB0_5:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt vmcnt(0)
	global_store_b32 v[35:36], v10, off
	s_load_b64 s[10:11], s[2:3], 0x50
	v_mov_b32_e32 v2, v37
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v2
	v_cmp_eq_u32_e64 s0, s0, v2
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_11
; %bb.6:                                ;   in Loop: Header=BB0_2 Depth=1
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[13:14], v3, s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[10:11] offset:40
	global_load_b64 v[8:9], v3, s[10:11]
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v5, v5, v14
	v_and_b32_e32 v4, v4, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v5, v5, 24
	v_mul_hi_u32 v11, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v11, v5
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v8, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v9, v5, vcc_lo
	global_load_b64 v[11:12], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v3, v[11:14], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[4:5], v[13:14]
	s_cbranch_execz .LBB0_10
; %bb.7:                                ; %.preheader3.i.i.i.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s6, 0
.LBB0_8:                                ; %.preheader3.i.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[8:9], v3, s[10:11] offset:40
	global_load_b64 v[11:12], v3, s[10:11]
	v_dual_mov_b32 v14, v5 :: v_dual_mov_b32 v13, v4
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v8, v8, v13
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[4:5], null, v8, 24, v[11:12]
	v_and_b32_e32 v11, v9, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v11, 24, v[5:6]
	v_mov_b32_e32 v5, v8
	global_load_b64 v[11:12], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v3, v[11:14], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[13:14]
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB0_8
; %bb.9:                                ; %Flow442
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_10:                               ; %Flow444
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_11:                               ; %.loopexit4.i.i.i
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[8:9], v3, s[10:11] offset:40
	global_load_b128 v[11:14], v3, s[10:11]
	v_readfirstlane_b32 s12, v4
	v_readfirstlane_b32 s13, v5
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v8
	v_readfirstlane_b32 s7, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[12:13], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s14, s6, 24
	s_mul_i32 s15, s6, 24
	s_and_saveexec_b32 s16, s0
	s_cbranch_execz .LBB0_13
; %bb.12:                               ;   in Loop: Header=BB0_2 Depth=1
	v_dual_mov_b32 v4, s5 :: v_dual_mov_b32 v5, v3
	s_add_i32 s5, s14, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v8, vcc_lo, v11, s15
	v_add_co_ci_u32_e32 v9, vcc_lo, s5, v12, vcc_lo
	global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_13:                               ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s16
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[4:5], 6, v[2:3]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v13, s6
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v14, vcc_lo
	s_mov_b32 s7, s4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v2, v4
	s_mov_b32 s5, s4
	s_mov_b32 s6, s4
	v_add_co_ci_u32_e32 v9, vcc_lo, v9, v5, vcc_lo
	v_mov_b32_e32 v2, v3
	v_mov_b32_e32 v4, v3
	v_dual_mov_b32 v16, s7 :: v_dual_mov_b32 v13, s4
	v_dual_mov_b32 v15, s6 :: v_dual_mov_b32 v14, s5
	s_clause 0x3
	global_store_b128 v[8:9], v[1:4], off
	global_store_b128 v[8:9], v[13:16], off offset:16
	global_store_b128 v[8:9], v[13:16], off offset:32
	global_store_b128 v[8:9], v[13:16], off offset:48
	s_and_saveexec_b32 s5, s0
	s_cbranch_execz .LBB0_21
; %bb.14:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x1
	global_load_b64 v[17:18], v3, s[10:11] offset:32 glc
	global_load_b64 v[4:5], v3, s[10:11] offset:40
	v_mov_b32_e32 v16, s13
	s_mov_b32 s6, exec_lo
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v15, s12 :: v_dual_and_b32 v2, s13, v5
	v_and_b32_e32 v4, s12, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v2, v2, 24
	v_mul_hi_u32 v5, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v5, v2
	v_add_co_u32 v4, vcc_lo, v11, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v12, v2, vcc_lo
	global_store_b64 v[4:5], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v3, v[15:18], s[10:11] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[15:16], v[17:18]
	s_cbranch_execz .LBB0_17
; %bb.15:                               ; %.preheader1.i.i.i.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s7, 0
.LBB0_16:                               ; %.preheader1.i.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v13, s12 :: v_dual_mov_b32 v14, s13
	s_sleep 1
	global_store_b64 v[4:5], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v3, v[13:16], s[10:11] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[13:14], v[15:16]
	v_dual_mov_b32 v16, v14 :: v_dual_mov_b32 v15, v13
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_16
.LBB0_17:                               ; %Flow440
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	global_load_b64 v[4:5], v3, s[10:11] offset:16
	s_mov_b32 s7, exec_lo
	s_mov_b32 s6, exec_lo
	v_mbcnt_lo_u32_b32 v2, s7, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB0_19
; %bb.18:                               ;   in Loop: Header=BB0_2 Depth=1
	s_bcnt1_i32_b32 s7, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s7
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[4:5], v[2:3], off offset:8
.LBB0_19:                               ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt vmcnt(0)
	global_load_b64 v[13:14], v[4:5], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[13:14]
	s_cbranch_vccnz .LBB0_21
; %bb.20:                               ;   in Loop: Header=BB0_2 Depth=1
	global_load_b32 v2, v[4:5], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v2
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[13:14], v[2:3], off
	s_and_b32 m0, s6, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_21:                               ; %Flow441
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_add_i32 s14, s14, s1
	v_add_co_u32 v2, vcc_lo, v11, s15
	v_add_co_ci_u32_e32 v5, vcc_lo, s14, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v2, 20
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
.LBB0_22:                               ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_24
; %bb.23:                               ;   in Loop: Header=BB0_22 Depth=2
	global_load_b32 v2, v[4:5], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB0_24:                               ;   in Loop: Header=BB0_22 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_26
; %bb.25:                               ;   in Loop: Header=BB0_22 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_27
.LBB0_26:                               ;   in Loop: Header=BB0_22 Depth=2
	s_mov_b32 s1, -1
.LBB0_27:                               ; %Flow435
                                        ;   in Loop: Header=BB0_22 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_22
; %bb.28:                               ;   in Loop: Header=BB0_2 Depth=1
	global_load_b64 v[11:12], v[8:9], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_32
; %bb.29:                               ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x2
	global_load_b64 v[4:5], v3, s[10:11] offset:40
	global_load_b64 v[8:9], v3, s[10:11] offset:24 glc
	global_load_b64 v[15:16], v3, s[10:11]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v2, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v13, vcc_lo, v2, s12
	v_add_co_ci_u32_e32 v14, vcc_lo, s13, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[13:14]
	v_dual_cndmask_b32 v14, v14, v17 :: v_dual_cndmask_b32 v13, v13, v2
	v_and_b32_e32 v2, v14, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, v13, v4
	v_mul_hi_u32 v5, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v4, vcc_lo, v15, v4
	v_mov_b32_e32 v15, v8
	v_mul_lo_u32 v2, v2, 24
	v_add_nc_u32_e32 v2, v5, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, v16, v2, vcc_lo
	v_mov_b32_e32 v16, v9
	global_store_b64 v[4:5], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v3, v[13:16], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[15:16], v[8:9]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_32
; %bb.30:                               ; %.preheader.i.i.i.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s0, 0
.LBB0_31:                               ; %.preheader.i.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[4:5], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v3, v[13:16], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[15:16]
	v_dual_mov_b32 v16, v9 :: v_dual_mov_b32 v15, v8
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_31
.LBB0_32:                               ; %__ockl_printf_begin.exit
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_getpc_b64 s[6:7]
	s_add_u32 s6, s6, .str@rel32@lo+4
	s_addc_u32 s7, s7, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u64 s[6:7], 0
	s_cbranch_scc0 .LBB0_119
; %bb.33:                               ;   in Loop: Header=BB0_2 Depth=1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v38, 2, v11
	v_dual_mov_b32 v14, v12 :: v_dual_and_b32 v13, -3, v11
	s_mov_b64 s[12:13], 27
.LBB0_34:                               ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_37 Depth 3
                                        ;       Child Loop BB0_45 Depth 3
                                        ;       Child Loop BB0_53 Depth 3
                                        ;       Child Loop BB0_61 Depth 3
                                        ;       Child Loop BB0_69 Depth 3
                                        ;       Child Loop BB0_77 Depth 3
                                        ;       Child Loop BB0_85 Depth 3
                                        ;       Child Loop BB0_93 Depth 3
                                        ;       Child Loop BB0_101 Depth 3
                                        ;       Child Loop BB0_107 Depth 3
                                        ;       Child Loop BB0_116 Depth 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s0, s[12:13], 56
	s_and_b32 s0, s0, exec_lo
	s_cselect_b32 s14, s12, 56
	s_cselect_b32 s15, s13, 0
	s_cmp_gt_u32 s14, 7
	s_cbranch_scc1 .LBB0_39
; %bb.35:                               ;   in Loop: Header=BB0_34 Depth=2
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v15, 0
	v_mov_b32_e32 v16, 0
	s_cmp_eq_u32 s14, 0
	s_cbranch_scc1 .LBB0_38
; %bb.36:                               ; %.preheader31.i.preheader
                                        ;   in Loop: Header=BB0_34 Depth=2
	s_lshl_b64 s[0:1], s[14:15], 3
	s_mov_b64 s[16:17], 0
	s_mov_b64 s[18:19], s[6:7]
.LBB0_37:                               ; %.preheader31.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_34 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	global_load_u8 v2, v3, s[18:19]
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v2, 0xffff, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s16, v[2:3]
	s_add_u32 s16, s16, 8
	s_addc_u32 s17, s17, 0
	s_add_u32 s18, s18, 1
	s_addc_u32 s19, s19, 0
	s_cmp_lg_u32 s0, s16
	v_or_b32_e32 v15, v4, v15
	v_or_b32_e32 v16, v5, v16
	s_cbranch_scc1 .LBB0_37
.LBB0_38:                               ; %Flow411
                                        ;   in Loop: Header=BB0_34 Depth=2
	s_mov_b32 s0, 0
	s_mov_b32 s5, 0
	s_branch .LBB0_40
.LBB0_39:                               ;   in Loop: Header=BB0_34 Depth=2
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr15_vgpr16
                                        ; implicit-def: $sgpr5
.LBB0_40:                               ; %Flow413
                                        ;   in Loop: Header=BB0_34 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_mov_b64 s[0:1], s[6:7]
	s_cbranch_vccnz .LBB0_42
; %bb.41:                               ;   in Loop: Header=BB0_34 Depth=2
	global_load_b64 v[15:16], v3, s[6:7]
	s_add_i32 s5, s14, -8
	s_add_u32 s0, s6, 8
	s_addc_u32 s1, s7, 0
.LBB0_42:                               ; %.loopexit32.i
                                        ;   in Loop: Header=BB0_34 Depth=2
	s_cmp_gt_u32 s5, 7
	s_cbranch_scc1 .LBB0_47
; %bb.43:                               ;   in Loop: Header=BB0_34 Depth=2
	v_mov_b32_e32 v17, 0
	v_mov_b32_e32 v18, 0
	s_cmp_eq_u32 s5, 0
	s_cbranch_scc1 .LBB0_46
; %bb.44:                               ; %.preheader29.i.preheader
                                        ;   in Loop: Header=BB0_34 Depth=2
	s_mov_b64 s[16:17], 0
	s_mov_b64 s[18:19], 0
.LBB0_45:                               ; %.preheader29.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_34 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s26, s0, s18
	s_addc_u32 s27, s1, s19
	s_add_u32 s18, s18, 1
	global_load_u8 v2, v3, s[26:27]
	s_addc_u32 s19, s19, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v2, 0xffff, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s16, v[2:3]
	s_add_u32 s16, s16, 8
	s_addc_u32 s17, s17, 0
	s_cmp_lg_u32 s5, s18
	v_or_b32_e32 v17, v4, v17
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v18, v5, v18
	s_cbranch_scc1 .LBB0_45
.LBB0_46:                               ; %Flow406
                                        ;   in Loop: Header=BB0_34 Depth=2
	s_mov_b32 s16, 0
	s_mov_b32 s26, 0
	s_branch .LBB0_48
.LBB0_47:                               ;   in Loop: Header=BB0_34 Depth=2
	s_mov_b32 s16, -1
                                        ; implicit-def: $vgpr17_vgpr18
                                        ; implicit-def: $sgpr26
.LBB0_48:                               ; %Flow408
                                        ;   in Loop: Header=BB0_34 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB0_50
; %bb.49:                               ;   in Loop: Header=BB0_34 Depth=2
	global_load_b64 v[17:18], v3, s[0:1]
	s_add_i32 s26, s5, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_50:                               ; %.loopexit30.i
                                        ;   in Loop: Header=BB0_34 Depth=2
	s_cmp_gt_u32 s26, 7
	s_cbranch_scc1 .LBB0_55
; %bb.51:                               ;   in Loop: Header=BB0_34 Depth=2
	v_mov_b32_e32 v19, 0
	v_mov_b32_e32 v20, 0
	s_cmp_eq_u32 s26, 0
	s_cbranch_scc1 .LBB0_54
; %bb.52:                               ; %.preheader27.i.preheader
                                        ;   in Loop: Header=BB0_34 Depth=2
	s_mov_b64 s[16:17], 0
	s_mov_b64 s[18:19], 0
.LBB0_53:                               ; %.preheader27.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_34 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s28, s0, s18
	s_addc_u32 s29, s1, s19
	s_add_u32 s18, s18, 1
	global_load_u8 v2, v3, s[28:29]
	s_addc_u32 s19, s19, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v2, 0xffff, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s16, v[2:3]
	s_add_u32 s16, s16, 8
	s_addc_u32 s17, s17, 0
	s_cmp_lg_u32 s26, s18
	v_or_b32_e32 v19, v4, v19
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v20, v5, v20
	s_cbranch_scc1 .LBB0_53
.LBB0_54:                               ; %Flow401
                                        ;   in Loop: Header=BB0_34 Depth=2
	s_mov_b32 s16, 0
	s_mov_b32 s5, 0
	s_branch .LBB0_56
.LBB0_55:                               ;   in Loop: Header=BB0_34 Depth=2
	s_mov_b32 s16, -1
                                        ; implicit-def: $sgpr5
.LBB0_56:                               ; %Flow403
                                        ;   in Loop: Header=BB0_34 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB0_58
; %bb.57:                               ;   in Loop: Header=BB0_34 Depth=2
	global_load_b64 v[19:20], v3, s[0:1]
	s_add_i32 s5, s26, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_58:                               ; %.loopexit28.i
                                        ;   in Loop: Header=BB0_34 Depth=2
	s_cmp_gt_u32 s5, 7
	s_cbranch_scc1 .LBB0_63
; %bb.59:                               ;   in Loop: Header=BB0_34 Depth=2
	v_mov_b32_e32 v21, 0
	v_mov_b32_e32 v22, 0
	s_cmp_eq_u32 s5, 0
	s_cbranch_scc1 .LBB0_62
; %bb.60:                               ; %.preheader25.i.preheader
                                        ;   in Loop: Header=BB0_34 Depth=2
	s_mov_b64 s[16:17], 0
	s_mov_b64 s[18:19], 0
.LBB0_61:                               ; %.preheader25.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_34 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s26, s0, s18
	s_addc_u32 s27, s1, s19
	s_add_u32 s18, s18, 1
	global_load_u8 v2, v3, s[26:27]
	s_addc_u32 s19, s19, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v2, 0xffff, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s16, v[2:3]
	s_add_u32 s16, s16, 8
	s_addc_u32 s17, s17, 0
	s_cmp_lg_u32 s5, s18
	v_or_b32_e32 v21, v4, v21
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v22, v5, v22
	s_cbranch_scc1 .LBB0_61
.LBB0_62:                               ; %Flow396
                                        ;   in Loop: Header=BB0_34 Depth=2
	s_mov_b32 s16, 0
	s_mov_b32 s26, 0
	s_branch .LBB0_64
.LBB0_63:                               ;   in Loop: Header=BB0_34 Depth=2
	s_mov_b32 s16, -1
                                        ; implicit-def: $vgpr21_vgpr22
                                        ; implicit-def: $sgpr26
.LBB0_64:                               ; %Flow398
                                        ;   in Loop: Header=BB0_34 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB0_66
; %bb.65:                               ;   in Loop: Header=BB0_34 Depth=2
	global_load_b64 v[21:22], v3, s[0:1]
	s_add_i32 s26, s5, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_66:                               ; %.loopexit26.i
                                        ;   in Loop: Header=BB0_34 Depth=2
	s_cmp_gt_u32 s26, 7
	s_cbranch_scc1 .LBB0_71
; %bb.67:                               ;   in Loop: Header=BB0_34 Depth=2
	v_mov_b32_e32 v23, 0
	v_mov_b32_e32 v24, 0
	s_cmp_eq_u32 s26, 0
	s_cbranch_scc1 .LBB0_70
; %bb.68:                               ; %.preheader23.i.preheader
                                        ;   in Loop: Header=BB0_34 Depth=2
	s_mov_b64 s[16:17], 0
	s_mov_b64 s[18:19], 0
.LBB0_69:                               ; %.preheader23.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_34 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s28, s0, s18
	s_addc_u32 s29, s1, s19
	s_add_u32 s18, s18, 1
	global_load_u8 v2, v3, s[28:29]
	s_addc_u32 s19, s19, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v2, 0xffff, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s16, v[2:3]
	s_add_u32 s16, s16, 8
	s_addc_u32 s17, s17, 0
	s_cmp_lg_u32 s26, s18
	v_or_b32_e32 v23, v4, v23
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v24, v5, v24
	s_cbranch_scc1 .LBB0_69
.LBB0_70:                               ; %Flow391
                                        ;   in Loop: Header=BB0_34 Depth=2
	s_mov_b32 s16, 0
	s_mov_b32 s5, 0
	s_branch .LBB0_72
.LBB0_71:                               ;   in Loop: Header=BB0_34 Depth=2
	s_mov_b32 s16, -1
                                        ; implicit-def: $sgpr5
.LBB0_72:                               ; %Flow393
                                        ;   in Loop: Header=BB0_34 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB0_74
; %bb.73:                               ;   in Loop: Header=BB0_34 Depth=2
	global_load_b64 v[23:24], v3, s[0:1]
	s_add_i32 s5, s26, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_74:                               ; %.loopexit24.i
                                        ;   in Loop: Header=BB0_34 Depth=2
	s_cmp_gt_u32 s5, 7
	s_cbranch_scc1 .LBB0_79
; %bb.75:                               ;   in Loop: Header=BB0_34 Depth=2
	v_mov_b32_e32 v25, 0
	v_mov_b32_e32 v26, 0
	s_cmp_eq_u32 s5, 0
	s_cbranch_scc1 .LBB0_78
; %bb.76:                               ; %.preheader21.i.preheader
                                        ;   in Loop: Header=BB0_34 Depth=2
	s_mov_b64 s[16:17], 0
	s_mov_b64 s[18:19], 0
.LBB0_77:                               ; %.preheader21.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_34 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s26, s0, s18
	s_addc_u32 s27, s1, s19
	s_add_u32 s18, s18, 1
	global_load_u8 v2, v3, s[26:27]
	s_addc_u32 s19, s19, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v2, 0xffff, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s16, v[2:3]
	s_add_u32 s16, s16, 8
	s_addc_u32 s17, s17, 0
	s_cmp_lg_u32 s5, s18
	v_or_b32_e32 v25, v4, v25
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v26, v5, v26
	s_cbranch_scc1 .LBB0_77
.LBB0_78:                               ; %Flow386
                                        ;   in Loop: Header=BB0_34 Depth=2
	s_mov_b32 s16, 0
	s_mov_b32 s26, 0
	s_branch .LBB0_80
.LBB0_79:                               ;   in Loop: Header=BB0_34 Depth=2
	s_mov_b32 s16, -1
                                        ; implicit-def: $vgpr25_vgpr26
                                        ; implicit-def: $sgpr26
.LBB0_80:                               ; %Flow388
                                        ;   in Loop: Header=BB0_34 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB0_82
; %bb.81:                               ;   in Loop: Header=BB0_34 Depth=2
	global_load_b64 v[25:26], v3, s[0:1]
	s_add_i32 s26, s5, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_82:                               ; %.loopexit22.i
                                        ;   in Loop: Header=BB0_34 Depth=2
	s_cmp_gt_u32 s26, 7
	s_cbranch_scc1 .LBB0_87
; %bb.83:                               ;   in Loop: Header=BB0_34 Depth=2
	v_mov_b32_e32 v27, 0
	v_mov_b32_e32 v28, 0
	s_cmp_eq_u32 s26, 0
	s_cbranch_scc1 .LBB0_86
; %bb.84:                               ; %.preheader.i.preheader
                                        ;   in Loop: Header=BB0_34 Depth=2
	s_mov_b64 s[16:17], 0
	s_mov_b64 s[18:19], s[0:1]
.LBB0_85:                               ; %.preheader.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_34 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	global_load_u8 v2, v3, s[18:19]
	s_add_i32 s26, s26, -1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v2, 0xffff, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s16, v[2:3]
	s_add_u32 s16, s16, 8
	s_addc_u32 s17, s17, 0
	s_add_u32 s18, s18, 1
	s_addc_u32 s19, s19, 0
	s_cmp_lg_u32 s26, 0
	v_or_b32_e32 v27, v4, v27
	v_or_b32_e32 v28, v5, v28
	s_cbranch_scc1 .LBB0_85
.LBB0_86:                               ; %Flow381
                                        ;   in Loop: Header=BB0_34 Depth=2
	s_mov_b32 s5, 0
	s_branch .LBB0_88
.LBB0_87:                               ;   in Loop: Header=BB0_34 Depth=2
	s_mov_b32 s5, -1
.LBB0_88:                               ; %Flow383
                                        ;   in Loop: Header=BB0_34 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s5
	s_cbranch_vccnz .LBB0_90
; %bb.89:                               ;   in Loop: Header=BB0_34 Depth=2
	global_load_b64 v[27:28], v3, s[0:1]
.LBB0_90:                               ; %.loopexit.i
                                        ;   in Loop: Header=BB0_34 Depth=2
	v_mov_b32_e32 v2, v37
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v2
	v_cmp_eq_u32_e64 s0, s0, v2
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_96
; %bb.91:                               ;   in Loop: Header=BB0_34 Depth=2
	global_load_b64 v[31:32], v3, s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[10:11] offset:40
	global_load_b64 v[8:9], v3, s[10:11]
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v5, v5, v32
	v_and_b32_e32 v4, v4, v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v5, v5, 24
	v_mul_hi_u32 v29, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v29, v5
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v8, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v9, v5, vcc_lo
	global_load_b64 v[29:30], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v3, v[29:32], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[4:5], v[31:32]
	s_cbranch_execz .LBB0_95
; %bb.92:                               ; %.preheader3.i.i19.i.preheader
                                        ;   in Loop: Header=BB0_34 Depth=2
	s_mov_b32 s16, 0
.LBB0_93:                               ; %.preheader3.i.i19.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_34 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[8:9], v3, s[10:11] offset:40
	global_load_b64 v[29:30], v3, s[10:11]
	v_dual_mov_b32 v32, v5 :: v_dual_mov_b32 v31, v4
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v8, v8, v31
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[4:5], null, v8, 24, v[29:30]
	v_and_b32_e32 v29, v9, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v29, 24, v[5:6]
	v_mov_b32_e32 v5, v8
	global_load_b64 v[29:30], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v3, v[29:32], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[31:32]
	s_or_b32 s16, vcc_lo, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s16
	s_cbranch_execnz .LBB0_93
; %bb.94:                               ; %Flow376
                                        ;   in Loop: Header=BB0_34 Depth=2
	s_or_b32 exec_lo, exec_lo, s16
.LBB0_95:                               ; %Flow378
                                        ;   in Loop: Header=BB0_34 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_96:                               ; %.loopexit4.i.i14.i
                                        ;   in Loop: Header=BB0_34 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[8:9], v3, s[10:11] offset:40
	global_load_b128 v[29:32], v3, s[10:11]
	v_readfirstlane_b32 s16, v4
	v_readfirstlane_b32 s17, v5
	s_mov_b32 s27, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s18, v8
	v_readfirstlane_b32 s19, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[18:19], s[16:17], s[18:19]
	s_mul_i32 s1, s19, 24
	s_mul_hi_u32 s5, s18, 24
	s_mul_i32 s26, s18, 24
	s_and_saveexec_b32 s28, s0
	s_cbranch_execz .LBB0_98
; %bb.97:                               ;   in Loop: Header=BB0_34 Depth=2
	v_dual_mov_b32 v4, s27 :: v_dual_mov_b32 v5, v3
	s_add_i32 s27, s5, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v8, vcc_lo, v29, s26
	v_add_co_ci_u32_e32 v9, vcc_lo, s27, v30, vcc_lo
	global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_98:                               ;   in Loop: Header=BB0_34 Depth=2
	s_or_b32 exec_lo, exec_lo, s28
	v_cmp_gt_u64_e64 vcc_lo, s[12:13], 56
	v_or_b32_e32 v4, 0, v14
	v_or_b32_e32 v5, v13, v38
	s_lshl_b64 s[18:19], s[18:19], 12
	s_lshl_b32 s27, s14, 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s27, s27, 28
	v_cndmask_b32_e32 v14, v4, v14, vcc_lo
	v_cndmask_b32_e32 v8, v5, v13, vcc_lo
	v_lshlrev_b64 v[4:5], 6, v[2:3]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v31, s18
	v_add_co_ci_u32_e32 v9, vcc_lo, s19, v32, vcc_lo
	s_and_b32 s27, s27, 0x1e0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, v2, v4
	v_and_or_b32 v13, 0xffffff1f, v8, s27
	v_add_co_ci_u32_e32 v5, vcc_lo, v9, v5, vcc_lo
	s_clause 0x3
	global_store_b128 v[4:5], v[13:16], off
	global_store_b128 v[4:5], v[17:20], off offset:16
	global_store_b128 v[4:5], v[21:24], off offset:32
	global_store_b128 v[4:5], v[25:28], off offset:48
	s_and_saveexec_b32 s18, s0
	s_cbranch_execz .LBB0_106
; %bb.99:                               ;   in Loop: Header=BB0_34 Depth=2
	s_clause 0x1
	global_load_b64 v[17:18], v3, s[10:11] offset:32 glc
	global_load_b64 v[8:9], v3, s[10:11] offset:40
	v_dual_mov_b32 v15, s16 :: v_dual_mov_b32 v16, s17
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s28, v8
	v_readfirstlane_b32 s29, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[28:29], s[28:29], s[16:17]
	s_mul_i32 s19, s29, 24
	s_mul_hi_u32 s27, s28, 24
	s_mul_i32 s28, s28, 24
	s_add_i32 s27, s27, s19
	v_add_co_u32 v8, vcc_lo, v29, s28
	v_add_co_ci_u32_e32 v9, vcc_lo, s27, v30, vcc_lo
	s_mov_b32 s19, exec_lo
	global_store_b64 v[8:9], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v3, v[15:18], s[10:11] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[15:16], v[17:18]
	s_cbranch_execz .LBB0_102
; %bb.100:                              ; %.preheader1.i.i17.i.preheader
                                        ;   in Loop: Header=BB0_34 Depth=2
	s_mov_b32 s27, 0
.LBB0_101:                              ; %.preheader1.i.i17.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_34 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_dual_mov_b32 v13, s16 :: v_dual_mov_b32 v14, s17
	s_sleep 1
	global_store_b64 v[8:9], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v3, v[13:16], s[10:11] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[13:14], v[15:16]
	v_dual_mov_b32 v16, v14 :: v_dual_mov_b32 v15, v13
	s_or_b32 s27, vcc_lo, s27
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s27
	s_cbranch_execnz .LBB0_101
.LBB0_102:                              ; %Flow374
                                        ;   in Loop: Header=BB0_34 Depth=2
	s_or_b32 exec_lo, exec_lo, s19
	global_load_b64 v[8:9], v3, s[10:11] offset:16
	s_mov_b32 s27, exec_lo
	s_mov_b32 s19, exec_lo
	v_mbcnt_lo_u32_b32 v2, s27, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB0_104
; %bb.103:                              ;   in Loop: Header=BB0_34 Depth=2
	s_bcnt1_i32_b32 s27, s27
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s27
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[8:9], v[2:3], off offset:8
.LBB0_104:                              ;   in Loop: Header=BB0_34 Depth=2
	s_or_b32 exec_lo, exec_lo, s19
	s_waitcnt vmcnt(0)
	global_load_b64 v[13:14], v[8:9], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[13:14]
	s_cbranch_vccnz .LBB0_106
; %bb.105:                              ;   in Loop: Header=BB0_34 Depth=2
	global_load_b32 v2, v[8:9], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s19, v2
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[13:14], v[2:3], off
	s_and_b32 m0, s19, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_106:                              ; %Flow375
                                        ;   in Loop: Header=BB0_34 Depth=2
	s_or_b32 exec_lo, exec_lo, s18
	s_add_i32 s5, s5, s1
	v_add_co_u32 v2, vcc_lo, v29, s26
	v_add_co_ci_u32_e32 v9, vcc_lo, s5, v30, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v2, 20
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
.LBB0_107:                              ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_34 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_109
; %bb.108:                              ;   in Loop: Header=BB0_107 Depth=3
	global_load_b32 v2, v[8:9], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB0_109:                              ;   in Loop: Header=BB0_107 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_111
; %bb.110:                              ;   in Loop: Header=BB0_107 Depth=3
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_112
.LBB0_111:                              ;   in Loop: Header=BB0_107 Depth=3
	s_mov_b32 s1, -1
.LBB0_112:                              ; %Flow369
                                        ;   in Loop: Header=BB0_107 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_107
; %bb.113:                              ;   in Loop: Header=BB0_34 Depth=2
	global_load_b128 v[13:16], v[4:5], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_117
; %bb.114:                              ;   in Loop: Header=BB0_34 Depth=2
	s_clause 0x2
	global_load_b64 v[4:5], v3, s[10:11] offset:40
	global_load_b64 v[8:9], v3, s[10:11] offset:24 glc
	global_load_b64 v[17:18], v3, s[10:11]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v2, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v19, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v15, vcc_lo, v2, s16
	v_add_co_ci_u32_e32 v16, vcc_lo, s17, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[15:16]
	v_dual_cndmask_b32 v16, v16, v19 :: v_dual_cndmask_b32 v15, v15, v2
	v_and_b32_e32 v2, v16, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v15, v4
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v5, v4, 24
	v_mul_lo_u32 v4, v4, 24
	v_add_nc_u32_e32 v2, v5, v2
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, v17, v4
	v_mov_b32_e32 v17, v8
	v_add_co_ci_u32_e32 v5, vcc_lo, v18, v2, vcc_lo
	v_mov_b32_e32 v18, v9
	global_store_b64 v[4:5], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[17:18], v3, v[15:18], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[17:18], v[8:9]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_117
; %bb.115:                              ; %.preheader.i.i16.i.preheader
                                        ;   in Loop: Header=BB0_34 Depth=2
	s_mov_b32 s0, 0
.LBB0_116:                              ; %.preheader.i.i16.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_34 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	global_store_b64 v[4:5], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v3, v[15:18], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[17:18]
	v_dual_mov_b32 v18, v9 :: v_dual_mov_b32 v17, v8
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_116
.LBB0_117:                              ; %__ockl_hostcall_preview.exit20.i
                                        ;   in Loop: Header=BB0_34 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_sub_u32 s12, s12, s14
	s_subb_u32 s13, s13, s15
	s_add_u32 s6, s6, s14
	s_addc_u32 s7, s7, s15
	s_cmp_lg_u64 s[12:13], 0
	s_cbranch_scc1 .LBB0_34
; %bb.118:                              ; %Flow414
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s0, 0
	s_branch .LBB0_120
.LBB0_119:                              ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr13_vgpr14
.LBB0_120:                              ; %Flow429
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB0_149
; %bb.121:                              ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v2, v37
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v2
	v_cmp_eq_u32_e64 s0, s0, v2
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_127
; %bb.122:                              ;   in Loop: Header=BB0_2 Depth=1
	global_load_b64 v[15:16], v3, s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[10:11] offset:40
	global_load_b64 v[8:9], v3, s[10:11]
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v5, v5, v16
	v_and_b32_e32 v4, v4, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v5, v5, 24
	v_mul_hi_u32 v13, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v13, v5
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v8, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v9, v5, vcc_lo
	global_load_b64 v[13:14], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v3, v[13:16], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[4:5], v[15:16]
	s_cbranch_execz .LBB0_126
; %bb.123:                              ; %.preheader3.i.i.i29.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s6, 0
.LBB0_124:                              ; %.preheader3.i.i.i29
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[8:9], v3, s[10:11] offset:40
	global_load_b64 v[13:14], v3, s[10:11]
	v_dual_mov_b32 v16, v5 :: v_dual_mov_b32 v15, v4
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v8, v8, v15
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[4:5], null, v8, 24, v[13:14]
	v_and_b32_e32 v13, v9, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v13, 24, v[5:6]
	v_mov_b32_e32 v5, v8
	global_load_b64 v[13:14], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v3, v[13:16], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[15:16]
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB0_124
; %bb.125:                              ; %Flow426
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_126:                              ; %Flow428
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_127:                              ; %.loopexit4.i.i.i24
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[8:9], v3, s[10:11] offset:40
	global_load_b128 v[15:18], v3, s[10:11]
	v_readfirstlane_b32 s12, v4
	v_readfirstlane_b32 s13, v5
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v8
	v_readfirstlane_b32 s7, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[12:13], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s14, s6, 24
	s_mul_i32 s15, s6, 24
	s_and_saveexec_b32 s16, s0
	s_cbranch_execz .LBB0_129
; %bb.128:                              ;   in Loop: Header=BB0_2 Depth=1
	v_dual_mov_b32 v4, s5 :: v_dual_mov_b32 v5, v3
	s_add_i32 s5, s14, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v8, vcc_lo, v15, s15
	v_add_co_ci_u32_e32 v9, vcc_lo, s5, v16, vcc_lo
	global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_129:                              ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s16
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[4:5], 6, v[2:3]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v17, s6
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v18, vcc_lo
	s_mov_b32 s7, s4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v2, v4
	s_mov_b32 s5, s4
	s_mov_b32 s6, s4
	v_and_or_b32 v11, 0xffffff1f, v11, 32
	v_add_co_ci_u32_e32 v5, vcc_lo, v8, v5, vcc_lo
	v_dual_mov_b32 v13, v3 :: v_dual_mov_b32 v20, s7
	v_dual_mov_b32 v14, v3 :: v_dual_mov_b32 v19, s6
	v_dual_mov_b32 v18, s5 :: v_dual_mov_b32 v17, s4
	s_clause 0x3
	global_store_b128 v[4:5], v[11:14], off
	global_store_b128 v[4:5], v[17:20], off offset:16
	global_store_b128 v[4:5], v[17:20], off offset:32
	global_store_b128 v[4:5], v[17:20], off offset:48
	s_and_saveexec_b32 s5, s0
	s_cbranch_execz .LBB0_137
; %bb.130:                              ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x1
	global_load_b64 v[19:20], v3, s[10:11] offset:32 glc
	global_load_b64 v[8:9], v3, s[10:11] offset:40
	v_dual_mov_b32 v17, s12 :: v_dual_mov_b32 v18, s13
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v8
	v_readfirstlane_b32 s7, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[6:7], s[12:13]
	s_mul_i32 s7, s7, 24
	s_mul_hi_u32 s16, s6, 24
	s_mul_i32 s6, s6, 24
	s_add_i32 s16, s16, s7
	v_add_co_u32 v8, vcc_lo, v15, s6
	v_add_co_ci_u32_e32 v9, vcc_lo, s16, v16, vcc_lo
	s_mov_b32 s6, exec_lo
	global_store_b64 v[8:9], v[19:20], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v3, v[17:20], s[10:11] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[13:14], v[19:20]
	s_cbranch_execz .LBB0_133
; %bb.131:                              ; %.preheader1.i.i.i27.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s7, 0
.LBB0_132:                              ; %.preheader1.i.i.i27
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v11, s12 :: v_dual_mov_b32 v12, s13
	s_sleep 1
	global_store_b64 v[8:9], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v3, v[11:14], s[10:11] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[13:14]
	v_dual_mov_b32 v14, v12 :: v_dual_mov_b32 v13, v11
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_132
.LBB0_133:                              ; %Flow424
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	global_load_b64 v[8:9], v3, s[10:11] offset:16
	s_mov_b32 s7, exec_lo
	s_mov_b32 s6, exec_lo
	v_mbcnt_lo_u32_b32 v2, s7, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB0_135
; %bb.134:                              ;   in Loop: Header=BB0_2 Depth=1
	s_bcnt1_i32_b32 s7, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s7
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[8:9], v[2:3], off offset:8
.LBB0_135:                              ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt vmcnt(0)
	global_load_b64 v[11:12], v[8:9], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	s_cbranch_vccnz .LBB0_137
; %bb.136:                              ;   in Loop: Header=BB0_2 Depth=1
	global_load_b32 v2, v[8:9], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v2
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[11:12], v[2:3], off
	s_and_b32 m0, s6, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_137:                              ; %Flow425
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_add_i32 s14, s14, s1
	v_add_co_u32 v2, vcc_lo, v15, s15
	v_add_co_ci_u32_e32 v9, vcc_lo, s14, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v2, 20
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
.LBB0_138:                              ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_140
; %bb.139:                              ;   in Loop: Header=BB0_138 Depth=2
	global_load_b32 v2, v[8:9], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB0_140:                              ;   in Loop: Header=BB0_138 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_142
; %bb.141:                              ;   in Loop: Header=BB0_138 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_143
.LBB0_142:                              ;   in Loop: Header=BB0_138 Depth=2
	s_mov_b32 s1, -1
.LBB0_143:                              ; %Flow419
                                        ;   in Loop: Header=BB0_138 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_138
; %bb.144:                              ;   in Loop: Header=BB0_2 Depth=1
	global_load_b128 v[13:16], v[4:5], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_148
; %bb.145:                              ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x2
	global_load_b64 v[4:5], v3, s[10:11] offset:40
	global_load_b64 v[8:9], v3, s[10:11] offset:24 glc
	global_load_b64 v[11:12], v3, s[10:11]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v2, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v5, vcc_lo
	s_waitcnt vmcnt(1)
	v_mov_b32_e32 v18, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v15, vcc_lo, v2, s12
	v_add_co_ci_u32_e32 v16, vcc_lo, s13, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[15:16]
	v_dual_cndmask_b32 v16, v16, v17 :: v_dual_cndmask_b32 v15, v15, v2
	v_mov_b32_e32 v17, v8
	v_and_b32_e32 v2, v16, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v15, v4
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v5, v4, 24
	v_mul_lo_u32 v4, v4, 24
	v_add_nc_u32_e32 v2, v5, v2
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v11, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, v12, v2, vcc_lo
	global_store_b64 v[4:5], v[8:9], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[17:18], v3, v[15:18], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[17:18], v[8:9]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_148
; %bb.146:                              ; %.preheader.i.i.i26.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s0, 0
.LBB0_147:                              ; %.preheader.i.i.i26
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[4:5], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v3, v[15:18], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[17:18]
	v_dual_mov_b32 v18, v9 :: v_dual_mov_b32 v17, v8
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_147
.LBB0_148:                              ; %__ockl_hostcall_preview.exit.i
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_149:                              ; %__ockl_printf_append_string_n.exit
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v2, v37
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v2
	v_cmp_eq_u32_e64 s0, s0, v2
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_155
; %bb.150:                              ;   in Loop: Header=BB0_2 Depth=1
	global_load_b64 v[17:18], v3, s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[10:11] offset:40
	global_load_b64 v[8:9], v3, s[10:11]
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v5, v5, v18
	v_and_b32_e32 v4, v4, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v5, v5, 24
	v_mul_hi_u32 v11, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v11, v5
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v8, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v9, v5, vcc_lo
	global_load_b64 v[15:16], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v3, v[15:18], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[4:5], v[17:18]
	s_cbranch_execz .LBB0_154
; %bb.151:                              ; %.preheader3.i.i.i36.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s6, 0
.LBB0_152:                              ; %.preheader3.i.i.i36
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[8:9], v3, s[10:11] offset:40
	global_load_b64 v[11:12], v3, s[10:11]
	v_dual_mov_b32 v18, v5 :: v_dual_mov_b32 v17, v4
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v8, v8, v17
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[4:5], null, v8, 24, v[11:12]
	v_and_b32_e32 v11, v9, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v11, 24, v[5:6]
	v_mov_b32_e32 v5, v8
	global_load_b64 v[15:16], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v3, v[15:18], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[17:18]
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB0_152
; %bb.153:                              ; %Flow362
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_154:                              ; %Flow364
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_155:                              ; %.loopexit4.i.i.i30
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[8:9], v3, s[10:11] offset:40
	global_load_b128 v[17:20], v3, s[10:11]
	v_readfirstlane_b32 s12, v4
	v_readfirstlane_b32 s13, v5
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v8
	v_readfirstlane_b32 s7, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[12:13], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s14, s6, 24
	s_mul_i32 s15, s6, 24
	s_and_saveexec_b32 s16, s0
	s_cbranch_execz .LBB0_157
; %bb.156:                              ;   in Loop: Header=BB0_2 Depth=1
	v_dual_mov_b32 v4, s5 :: v_dual_mov_b32 v5, v3
	s_add_i32 s5, s14, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v8, vcc_lo, v17, s15
	v_add_co_ci_u32_e32 v9, vcc_lo, s5, v18, vcc_lo
	global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_157:                              ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s16
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[4:5], 6, v[2:3]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v19, s6
	v_add_co_ci_u32_e32 v8, vcc_lo, s7, v20, vcc_lo
	s_mov_b32 s7, s4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v2, v4
	s_mov_b32 s5, s4
	s_mov_b32 s6, s4
	v_and_or_b32 v13, 0xffffff1f, v13, 32
	v_add_co_ci_u32_e32 v5, vcc_lo, v8, v5, vcc_lo
	v_dual_mov_b32 v15, v33 :: v_dual_mov_b32 v16, v34
	v_dual_mov_b32 v22, s7 :: v_dual_mov_b32 v21, s6
	v_dual_mov_b32 v20, s5 :: v_dual_mov_b32 v19, s4
	s_clause 0x3
	global_store_b128 v[4:5], v[13:16], off
	global_store_b128 v[4:5], v[19:22], off offset:16
	global_store_b128 v[4:5], v[19:22], off offset:32
	global_store_b128 v[4:5], v[19:22], off offset:48
	s_and_saveexec_b32 s5, s0
	s_cbranch_execz .LBB0_165
; %bb.158:                              ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x1
	global_load_b64 v[15:16], v3, s[10:11] offset:32 glc
	global_load_b64 v[8:9], v3, s[10:11] offset:40
	v_dual_mov_b32 v13, s12 :: v_dual_mov_b32 v14, s13
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v8
	v_readfirstlane_b32 s7, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[6:7], s[12:13]
	s_mul_i32 s7, s7, 24
	s_mul_hi_u32 s16, s6, 24
	s_mul_i32 s6, s6, 24
	s_add_i32 s16, s16, s7
	v_add_co_u32 v8, vcc_lo, v17, s6
	v_add_co_ci_u32_e32 v9, vcc_lo, s16, v18, vcc_lo
	s_mov_b32 s6, exec_lo
	global_store_b64 v[8:9], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v3, v[13:16], s[10:11] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[13:14], v[15:16]
	s_cbranch_execz .LBB0_161
; %bb.159:                              ; %.preheader1.i.i.i34.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s7, 0
.LBB0_160:                              ; %.preheader1.i.i.i34
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v11, s12 :: v_dual_mov_b32 v12, s13
	s_sleep 1
	global_store_b64 v[8:9], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v3, v[11:14], s[10:11] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[13:14]
	v_dual_mov_b32 v14, v12 :: v_dual_mov_b32 v13, v11
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_160
.LBB0_161:                              ; %Flow360
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	global_load_b64 v[8:9], v3, s[10:11] offset:16
	s_mov_b32 s7, exec_lo
	s_mov_b32 s6, exec_lo
	v_mbcnt_lo_u32_b32 v2, s7, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB0_163
; %bb.162:                              ;   in Loop: Header=BB0_2 Depth=1
	s_bcnt1_i32_b32 s7, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s7
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[8:9], v[2:3], off offset:8
.LBB0_163:                              ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt vmcnt(0)
	global_load_b64 v[11:12], v[8:9], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	s_cbranch_vccnz .LBB0_165
; %bb.164:                              ;   in Loop: Header=BB0_2 Depth=1
	global_load_b32 v2, v[8:9], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v2
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[11:12], v[2:3], off
	s_and_b32 m0, s6, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_165:                              ; %Flow361
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_add_i32 s14, s14, s1
	v_add_co_u32 v2, vcc_lo, v17, s15
	v_add_co_ci_u32_e32 v9, vcc_lo, s14, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v2, 20
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
.LBB0_166:                              ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_168
; %bb.167:                              ;   in Loop: Header=BB0_166 Depth=2
	global_load_b32 v2, v[8:9], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB0_168:                              ;   in Loop: Header=BB0_166 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_170
; %bb.169:                              ;   in Loop: Header=BB0_166 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_171
.LBB0_170:                              ;   in Loop: Header=BB0_166 Depth=2
	s_mov_b32 s1, -1
.LBB0_171:                              ; %Flow355
                                        ;   in Loop: Header=BB0_166 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_166
; %bb.172:                              ;   in Loop: Header=BB0_2 Depth=1
	global_load_b64 v[8:9], v[4:5], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_176
; %bb.173:                              ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x2
	global_load_b64 v[4:5], v3, s[10:11] offset:40
	global_load_b64 v[15:16], v3, s[10:11] offset:24 glc
	global_load_b64 v[13:14], v3, s[10:11]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v2, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v2, s12
	v_add_co_ci_u32_e32 v12, vcc_lo, s13, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	v_dual_cndmask_b32 v12, v12, v17 :: v_dual_cndmask_b32 v11, v11, v2
	v_and_b32_e32 v2, v12, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, v11, v4
	v_mul_hi_u32 v5, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v4, vcc_lo, v13, v4
	v_mov_b32_e32 v13, v15
	v_mul_lo_u32 v2, v2, 24
	v_add_nc_u32_e32 v2, v5, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, v14, v2, vcc_lo
	v_mov_b32_e32 v14, v16
	global_store_b64 v[4:5], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v3, v[11:14], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[13:14], v[15:16]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_176
; %bb.174:                              ; %.preheader.i.i.i33.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s0, 0
.LBB0_175:                              ; %.preheader.i.i.i33
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[4:5], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v3, v[11:14], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[15:16], v[13:14]
	v_dual_mov_b32 v13, v15 :: v_dual_mov_b32 v14, v16
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_175
.LBB0_176:                              ; %__ockl_printf_append_args.exit
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v2, v37
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v2
	v_cmp_eq_u32_e64 s0, s0, v2
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_182
; %bb.177:                              ;   in Loop: Header=BB0_2 Depth=1
	global_load_b64 v[13:14], v3, s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[10:11] offset:40
	global_load_b64 v[11:12], v3, s[10:11]
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v5, v5, v14
	v_and_b32_e32 v4, v4, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v5, v5, 24
	v_mul_hi_u32 v15, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v15, v5
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v11, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v12, v5, vcc_lo
	global_load_b64 v[11:12], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v3, v[11:14], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[4:5], v[13:14]
	s_cbranch_execz .LBB0_181
; %bb.178:                              ; %.preheader3.i.i.i43.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s6, 0
.LBB0_179:                              ; %.preheader3.i.i.i43
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[11:12], v3, s[10:11] offset:40
	global_load_b64 v[15:16], v3, s[10:11]
	v_dual_mov_b32 v14, v5 :: v_dual_mov_b32 v13, v4
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v11, v11, v13
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[4:5], null, v11, 24, v[15:16]
	v_and_b32_e32 v15, v12, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[11:12], null, v15, 24, v[5:6]
	v_mov_b32_e32 v5, v11
	global_load_b64 v[11:12], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v3, v[11:14], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[13:14]
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB0_179
; %bb.180:                              ; %Flow348
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_181:                              ; %Flow350
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_182:                              ; %.loopexit4.i.i.i37
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[16:17], v3, s[10:11] offset:40
	global_load_b128 v[12:15], v3, s[10:11]
	v_readfirstlane_b32 s12, v4
	v_readfirstlane_b32 s13, v5
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v16
	v_readfirstlane_b32 s7, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[12:13], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s14, s6, 24
	s_mul_i32 s15, s6, 24
	s_and_saveexec_b32 s16, s0
	s_cbranch_execz .LBB0_184
; %bb.183:                              ;   in Loop: Header=BB0_2 Depth=1
	v_dual_mov_b32 v4, s5 :: v_dual_mov_b32 v5, v3
	s_add_i32 s5, s14, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v16, vcc_lo, v12, s15
	v_add_co_ci_u32_e32 v17, vcc_lo, s5, v13, vcc_lo
	global_store_b128 v[16:17], v[4:7], off offset:8
.LBB0_184:                              ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s16
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[4:5], 6, v[2:3]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v14, s6
	v_add_co_ci_u32_e32 v11, vcc_lo, s7, v15, vcc_lo
	s_mov_b32 s7, s4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v2, v4
	s_mov_b32 s5, s4
	s_mov_b32 s6, s4
	v_and_or_b32 v8, 0xffffff1f, v8, 32
	v_add_co_ci_u32_e32 v5, vcc_lo, v11, v5, vcc_lo
	v_mov_b32_e32 v11, v3
	v_dual_mov_b32 v17, s7 :: v_dual_mov_b32 v14, s4
	v_dual_mov_b32 v16, s6 :: v_dual_mov_b32 v15, s5
	s_clause 0x3
	global_store_b128 v[4:5], v[8:11], off
	global_store_b128 v[4:5], v[14:17], off offset:16
	global_store_b128 v[4:5], v[14:17], off offset:32
	global_store_b128 v[4:5], v[14:17], off offset:48
	s_and_saveexec_b32 s5, s0
	s_cbranch_execz .LBB0_192
; %bb.185:                              ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x1
	global_load_b64 v[18:19], v3, s[10:11] offset:32 glc
	global_load_b64 v[8:9], v3, s[10:11] offset:40
	v_dual_mov_b32 v16, s12 :: v_dual_mov_b32 v17, s13
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v8
	v_readfirstlane_b32 s7, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[6:7], s[12:13]
	s_mul_i32 s7, s7, 24
	s_mul_hi_u32 s16, s6, 24
	s_mul_i32 s6, s6, 24
	s_add_i32 s16, s16, s7
	v_add_co_u32 v14, vcc_lo, v12, s6
	v_add_co_ci_u32_e32 v15, vcc_lo, s16, v13, vcc_lo
	s_mov_b32 s6, exec_lo
	global_store_b64 v[14:15], v[18:19], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v3, v[16:19], s[10:11] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[10:11], v[18:19]
	s_cbranch_execz .LBB0_188
; %bb.186:                              ; %.preheader1.i.i.i41.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s7, 0
.LBB0_187:                              ; %.preheader1.i.i.i41
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v9, s13
	s_sleep 1
	global_store_b64 v[14:15], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v3, v[8:11], s[10:11] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[10:11]
	v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v10, v8
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_187
.LBB0_188:                              ; %Flow346
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	global_load_b64 v[8:9], v3, s[10:11] offset:16
	s_mov_b32 s7, exec_lo
	s_mov_b32 s6, exec_lo
	v_mbcnt_lo_u32_b32 v2, s7, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB0_190
; %bb.189:                              ;   in Loop: Header=BB0_2 Depth=1
	s_bcnt1_i32_b32 s7, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s7
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[8:9], v[2:3], off offset:8
.LBB0_190:                              ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt vmcnt(0)
	global_load_b64 v[10:11], v[8:9], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11]
	s_cbranch_vccnz .LBB0_192
; %bb.191:                              ;   in Loop: Header=BB0_2 Depth=1
	global_load_b32 v2, v[8:9], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v2
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[10:11], v[2:3], off
	s_and_b32 m0, s6, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_192:                              ; %Flow347
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_add_i32 s14, s14, s1
	v_add_co_u32 v2, vcc_lo, v12, s15
	v_add_co_ci_u32_e32 v9, vcc_lo, s14, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v2, 20
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
.LBB0_193:                              ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_195
; %bb.194:                              ;   in Loop: Header=BB0_193 Depth=2
	global_load_b32 v2, v[8:9], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB0_195:                              ;   in Loop: Header=BB0_193 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_197
; %bb.196:                              ;   in Loop: Header=BB0_193 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_198
.LBB0_197:                              ;   in Loop: Header=BB0_193 Depth=2
	s_mov_b32 s1, -1
.LBB0_198:                              ; %Flow341
                                        ;   in Loop: Header=BB0_193 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_193
; %bb.199:                              ;   in Loop: Header=BB0_2 Depth=1
	global_load_b64 v[8:9], v[4:5], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_203
; %bb.200:                              ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x2
	global_load_b64 v[4:5], v3, s[10:11] offset:40
	global_load_b64 v[14:15], v3, s[10:11] offset:24 glc
	global_load_b64 v[12:13], v3, s[10:11]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v2, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v16, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v2, s12
	v_add_co_ci_u32_e32 v11, vcc_lo, s13, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11]
	v_dual_cndmask_b32 v11, v11, v16 :: v_dual_cndmask_b32 v10, v10, v2
	v_and_b32_e32 v2, v11, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v10, v4
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v5, v4, 24
	v_mul_lo_u32 v4, v4, 24
	v_add_nc_u32_e32 v2, v5, v2
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, v12, v4
	v_mov_b32_e32 v12, v14
	v_add_co_ci_u32_e32 v5, vcc_lo, v13, v2, vcc_lo
	v_mov_b32_e32 v13, v15
	global_store_b64 v[4:5], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[12:13], v3, v[10:13], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[12:13], v[14:15]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_203
; %bb.201:                              ; %.preheader.i.i.i40.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s0, 0
.LBB0_202:                              ; %.preheader.i.i.i40
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[4:5], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[14:15], v3, v[10:13], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[14:15], v[12:13]
	v_dual_mov_b32 v12, v14 :: v_dual_mov_b32 v13, v15
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_202
.LBB0_203:                              ; %__ockl_printf_append_args.exit44
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v2, v37
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v2
	v_cmp_eq_u32_e64 s0, s0, v2
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_209
; %bb.204:                              ;   in Loop: Header=BB0_2 Depth=1
	global_load_b64 v[12:13], v3, s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[10:11] offset:40
	global_load_b64 v[10:11], v3, s[10:11]
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v5, v5, v13
	v_and_b32_e32 v4, v4, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v5, v5, 24
	v_mul_hi_u32 v14, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v14, v5
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v10, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v11, v5, vcc_lo
	global_load_b64 v[10:11], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v3, v[10:13], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[4:5], v[12:13]
	s_cbranch_execz .LBB0_208
; %bb.205:                              ; %.preheader3.i.i.i51.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s6, 0
.LBB0_206:                              ; %.preheader3.i.i.i51
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[10:11], v3, s[10:11] offset:40
	global_load_b64 v[14:15], v3, s[10:11]
	v_dual_mov_b32 v13, v5 :: v_dual_mov_b32 v12, v4
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v10, v10, v12
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[4:5], null, v10, 24, v[14:15]
	v_and_b32_e32 v14, v11, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[10:11], null, v14, 24, v[5:6]
	v_mov_b32_e32 v5, v10
	global_load_b64 v[10:11], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v3, v[10:13], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[12:13]
	s_or_b32 s6, vcc_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB0_206
; %bb.207:                              ; %Flow334
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_208:                              ; %Flow336
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_209:                              ; %.loopexit4.i.i.i45
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[10:11], v3, s[10:11] offset:40
	global_load_b128 v[12:15], v3, s[10:11]
	v_readfirstlane_b32 s12, v4
	v_readfirstlane_b32 s13, v5
	s_mov_b32 s5, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v10
	v_readfirstlane_b32 s7, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[12:13], s[6:7]
	s_mul_i32 s1, s7, 24
	s_mul_hi_u32 s14, s6, 24
	s_mul_i32 s15, s6, 24
	s_and_saveexec_b32 s16, s0
	s_cbranch_execz .LBB0_211
; %bb.210:                              ;   in Loop: Header=BB0_2 Depth=1
	v_dual_mov_b32 v4, s5 :: v_dual_mov_b32 v5, v3
	s_add_i32 s5, s14, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v10, vcc_lo, v12, s15
	v_add_co_ci_u32_e32 v11, vcc_lo, s5, v13, vcc_lo
	global_store_b128 v[10:11], v[4:7], off offset:8
.LBB0_211:                              ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s16
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[4:5], 6, v[2:3]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v14, s6
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v15, vcc_lo
	s_mov_b32 s7, s4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v2, v4
	s_mov_b32 s5, s4
	s_mov_b32 s6, s4
	v_and_or_b32 v8, 0xffffff1d, v8, 34
	v_add_co_ci_u32_e32 v5, vcc_lo, v10, v5, vcc_lo
	v_dual_mov_b32 v10, s21 :: v_dual_mov_b32 v11, s23
	v_dual_mov_b32 v17, s7 :: v_dual_mov_b32 v16, s6
	v_dual_mov_b32 v15, s5 :: v_dual_mov_b32 v14, s4
	s_clause 0x3
	global_store_b128 v[4:5], v[8:11], off
	global_store_b128 v[4:5], v[14:17], off offset:16
	global_store_b128 v[4:5], v[14:17], off offset:32
	global_store_b128 v[4:5], v[14:17], off offset:48
	s_and_saveexec_b32 s5, s0
	s_cbranch_execz .LBB0_219
; %bb.212:                              ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x1
	global_load_b64 v[16:17], v3, s[10:11] offset:32 glc
	global_load_b64 v[4:5], v3, s[10:11] offset:40
	v_dual_mov_b32 v14, s12 :: v_dual_mov_b32 v15, s13
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v4
	v_readfirstlane_b32 s7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[6:7], s[12:13]
	s_mul_i32 s7, s7, 24
	s_mul_hi_u32 s16, s6, 24
	s_mul_i32 s6, s6, 24
	s_add_i32 s16, s16, s7
	v_add_co_u32 v4, vcc_lo, v12, s6
	v_add_co_ci_u32_e32 v5, vcc_lo, s16, v13, vcc_lo
	s_mov_b32 s6, exec_lo
	global_store_b64 v[4:5], v[16:17], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v3, v[14:17], s[10:11] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[10:11], v[16:17]
	s_cbranch_execz .LBB0_215
; %bb.213:                              ; %.preheader1.i.i.i49.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s7, 0
.LBB0_214:                              ; %.preheader1.i.i.i49
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v9, s13
	s_sleep 1
	global_store_b64 v[4:5], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[8:9], v3, v[8:11], s[10:11] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[10:11]
	v_dual_mov_b32 v11, v9 :: v_dual_mov_b32 v10, v8
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_214
.LBB0_215:                              ; %Flow332
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	global_load_b64 v[4:5], v3, s[10:11] offset:16
	s_mov_b32 s7, exec_lo
	s_mov_b32 s6, exec_lo
	v_mbcnt_lo_u32_b32 v2, s7, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB0_217
; %bb.216:                              ;   in Loop: Header=BB0_2 Depth=1
	s_bcnt1_i32_b32 s7, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s7
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[4:5], v[2:3], off offset:8
.LBB0_217:                              ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_waitcnt vmcnt(0)
	global_load_b64 v[8:9], v[4:5], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[8:9]
	s_cbranch_vccnz .LBB0_219
; %bb.218:                              ;   in Loop: Header=BB0_2 Depth=1
	global_load_b32 v2, v[4:5], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s6, v2
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[8:9], v[2:3], off
	s_and_b32 m0, s6, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_219:                              ; %Flow333
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_add_i32 s14, s14, s1
	v_add_co_u32 v2, vcc_lo, v12, s15
	v_add_co_ci_u32_e32 v5, vcc_lo, s14, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v2, 20
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
.LBB0_220:                              ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_222
; %bb.221:                              ;   in Loop: Header=BB0_220 Depth=2
	global_load_b32 v2, v[4:5], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB0_222:                              ;   in Loop: Header=BB0_220 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_224
; %bb.223:                              ;   in Loop: Header=BB0_220 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_225
.LBB0_224:                              ;   in Loop: Header=BB0_220 Depth=2
	s_mov_b32 s1, -1
.LBB0_225:                              ; %Flow327
                                        ;   in Loop: Header=BB0_220 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_220
; %bb.226:                              ;   in Loop: Header=BB0_2 Depth=1
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_230
; %bb.227:                              ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x2
	global_load_b64 v[4:5], v3, s[10:11] offset:40
	global_load_b64 v[12:13], v3, s[10:11] offset:24 glc
	global_load_b64 v[10:11], v3, s[10:11]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v2, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v2, s12
	v_add_co_ci_u32_e32 v9, vcc_lo, s13, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[8:9]
	v_cndmask_b32_e32 v8, v8, v2, vcc_lo
	v_dual_cndmask_b32 v9, v9, v14 :: v_dual_and_b32 v4, v8, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v2, v9, v5
	v_mul_hi_u32 v5, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v2, v2, 24
	v_mul_lo_u32 v4, v4, 24
	v_add_nc_u32_e32 v2, v5, v2
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, v10, v4
	v_mov_b32_e32 v10, v12
	v_add_co_ci_u32_e32 v5, vcc_lo, v11, v2, vcc_lo
	v_mov_b32_e32 v11, v13
	global_store_b64 v[4:5], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v3, v[8:11], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[10:11], v[12:13]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_230
; %bb.228:                              ; %.preheader.i.i.i48.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s0, 0
.LBB0_229:                              ; %.preheader.i.i.i48
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[4:5], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[12:13], v3, v[8:11], s[10:11] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[12:13], v[10:11]
	v_dual_mov_b32 v10, v12 :: v_dual_mov_b32 v11, v13
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_229
.LBB0_230:                              ; %Flow445
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s25
	s_cmp_ge_u32 s24, s20
	s_mov_b32 s0, s24
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_2
.LBB0_231:                              ; %._crit_edge
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6reducePii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 39
		.amdhsa_next_free_sgpr 30
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z6reducePii, .Lfunc_end0-_Z6reducePii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 9516
; NumSgprs: 32
; NumVgprs: 39
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 32
; NumVGPRsForWavesPerEU: 39
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	.str,@object                    ; @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.str:
	.asciz	"input[%d]= %d offset= %ld\n"
	.size	.str, 27

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         96
        .size:           8
        .value_kind:     hidden_hostcall_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6reducePii
    .private_segment_fixed_size: 0
    .sgpr_count:     32
    .sgpr_spill_count: 0
    .symbol:         _Z6reducePii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     39
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
