#include <stdio.h>
#include <cmath>
#include "Cuda/PBKDF2.cu"

#define ERRCHECK(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true,bool wait=true) {
   if (code != cudaSuccess) {
      fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
      if (abort) exit(code);
   }
}

#define SHA256_DIGESTSIZE 32
#define SHA256_BLOCKSIZE 64

__global__ void PBKDF2Kernel(int n, unsigned char *out) {
  unsigned char passwd[22] = "governor washout beak";
  int pwd_len = sizeof(passwd) - 1;
  for (int i = blockIdx.x * blockDim.x + threadIdx.x; i<n; i += blockDim.x * gridDim.x) {
    cuda_derive_key_sha256(passwd, pwd_len, &out[SHA256_DIGESTSIZE*i]);
  }
}

int main() {
  cudaError_t err;
  int device = 0;
  int numSMs;
  const int N = 1;

  cudaDeviceProp props;
  err = cudaGetDeviceProperties(&props, device);

  if(err) { return -1; }

  printf("%s (%2d)\n", props.name, props.multiProcessorCount);
  cudaSetDevice(device);
  cudaDeviceGetAttribute(&numSMs, cudaDevAttrMultiProcessorCount, device);

  cudaError_t error;
  /* Stop eating CPU while waiting for results! */
  error = cudaSetDeviceFlags(cudaDeviceScheduleBlockingSync);
  if (error != cudaSuccess) { 
    fprintf(stderr, "Could not set blocking sync (error %d)\n", error);
  }


  int blockSize;      // The launch configurator returned block size 
  int minGridSize;    // The minimum grid size needed to achieve the maximum occupancy for a full device launch 
  int gridSize;       // The actual grid size needed, based on input size 

  float time;
  cudaEvent_t start, stop;
  cudaEventCreate(&start);
  cudaEventCreate(&stop);
  cudaEventRecord(start, 0);

  cudaOccupancyMaxPotentialBlockSize(&minGridSize, &blockSize, PBKDF2Kernel, 0, N); 

  // Round up according to array size 
  gridSize = (N + blockSize - 1) / blockSize; 

  cudaEventRecord(stop, 0);
  cudaEventSynchronize(stop);
  cudaEventElapsedTime(&time, start, stop);
  printf("Occupancy calculator elapsed time:  %3.3f ms \n", time);

  unsigned char *finalDestination;
  cudaMallocManaged((void **)&finalDestination, N*SHA256_DIGESTSIZE);
  ERRCHECK(cudaGetLastError());
  printf("SMs: %d, X: %d, Y: %d\n", numSMs, 32*numSMs, 512);
  printf("grid: %d, min grid: %d, block: %d\n", gridSize, minGridSize, blockSize);
  //PBKDF2Kernel<<<1,1>>>(N, 100000, d_hash);
  PBKDF2Kernel<<<gridSize,blockSize>>>(N, finalDestination);
  ERRCHECK(cudaDeviceSynchronize());
  ERRCHECK(cudaGetLastError());

  for(int i = 0; i < N; i++) {
    for(int j = 0; j < SHA256_DIGESTSIZE; j++) {
      printf("%02x ", finalDestination[i*SHA256_DIGESTSIZE+j]);
    }
    printf("\n");
  }
  cudaFree(finalDestination);
  cudaDeviceReset();
  return 0;
}

	.file	"tmpxft_002469d1_00000000-6_main.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2042:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2042:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"GPUassert: %s %s %d\n"
	.text
	.type	_Z9gpuAssert9cudaErrorPKcibb.isra.0, @function
_Z9gpuAssert9cudaErrorPKcibb.isra.0:
.LFB2192:
	.cfi_startproc
	testl	%edi, %edi
	je	.L8
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	%ecx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movl	%edi, %ebx
	subq	$24, %rsp
	.cfi_def_cfa_offset 48
	movl	%edx, 12(%rsp)
	movq	%rsi, (%rsp)
	call	cudaGetErrorString@PLT
	movl	12(%rsp), %r9d
	movq	(%rsp), %r8
	leaq	.LC0(%rip), %rdx
	movq	stderr(%rip), %rdi
	movq	%rax, %rcx
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	testb	%bpl, %bpl
	je	.L2
	movl	%ebx, %edi
	call	exit@PLT
.L2:
	addq	$24, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
.L8:
	.cfi_restore 3
	.cfi_restore 6
	ret
	.cfi_endproc
.LFE2192:
	.size	_Z9gpuAssert9cudaErrorPKcibb.isra.0, .-_Z9gpuAssert9cudaErrorPKcibb.isra.0
	.globl	m_cycle
	.type	m_cycle, @function
m_cycle:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2027:
	.size	m_cycle, .-m_cycle
	.globl	sha256_compile
	.type	sha256_compile, @function
sha256_compile:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2028:
	.size	sha256_compile, .-sha256_compile
	.globl	sha256_hash
	.type	sha256_hash, @function
sha256_hash:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2029:
	.size	sha256_hash, .-sha256_hash
	.globl	sha256_setstate_c
	.type	sha256_setstate_c, @function
sha256_setstate_c:
.LFB2030:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2030:
	.size	sha256_setstate_c, .-sha256_setstate_c
	.globl	sha256_begin
	.type	sha256_begin, @function
sha256_begin:
.LFB2189:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	pushq	%rax
	.cfi_def_cfa_offset 16
	call	sha256_compile
	.cfi_endproc
.LFE2189:
	.size	sha256_begin, .-sha256_begin
	.globl	sha256_end
	.type	sha256_end, @function
sha256_end:
.LFB2033:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2033:
	.size	sha256_end, .-sha256_end
	.globl	s_sha256_end
	.type	s_sha256_end, @function
s_sha256_end:
.LFB2191:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	pushq	%rax
	.cfi_def_cfa_offset 16
	call	sha256_end
	.cfi_endproc
.LFE2191:
	.size	s_sha256_end, .-s_sha256_end
	.globl	sha256
	.type	sha256, @function
sha256:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2035:
	.size	sha256, .-sha256
	.globl	_Z13hmac_sha256_c10sha256_ctxS_PhiS0_
	.type	_Z13hmac_sha256_c10sha256_ctxS_PhiS0_, @function
_Z13hmac_sha256_c10sha256_ctxS_PhiS0_:
.LFB2036:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2036:
	.size	_Z13hmac_sha256_c10sha256_ctxS_PhiS0_, .-_Z13hmac_sha256_c10sha256_ctxS_PhiS0_
	.globl	_Z22cuda_derive_key_sha256PhiS_
	.type	_Z22cuda_derive_key_sha256PhiS_, @function
_Z22cuda_derive_key_sha256PhiS_:
.LFB2037:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2037:
	.size	_Z22cuda_derive_key_sha256PhiS_, .-_Z22cuda_derive_key_sha256PhiS_
	.globl	_Z33__device_stub__Z12PBKDF2KerneliPhiPh
	.type	_Z33__device_stub__Z12PBKDF2KerneliPhiPh, @function
_Z33__device_stub__Z12PBKDF2KerneliPhiPh:
.LFB2064:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movl	%edi, 12(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L32
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z12PBKDF2KerneliPh(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L32:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L34
	call	__stack_chk_fail@PLT
.L34:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2064:
	.size	_Z33__device_stub__Z12PBKDF2KerneliPhiPh, .-_Z33__device_stub__Z12PBKDF2KerneliPhiPh
	.globl	_Z12PBKDF2KerneliPh
	.type	_Z12PBKDF2KerneliPh, @function
_Z12PBKDF2KerneliPh:
.LFB2065:
	.cfi_startproc
	endbr64
	jmp	_Z33__device_stub__Z12PBKDF2KerneliPhiPh
	.cfi_endproc
.LFE2065:
	.size	_Z12PBKDF2KerneliPh, .-_Z12PBKDF2KerneliPh
	.section	.rodata.str1.1
.LC1:
	.string	"%s (%2d)\n"
.LC2:
	.string	"Could not set blocking sync (error %d)\n"
.LC3:
	.string	"Occupancy calculator elapsed time:  %3.3f ms \n"
.LC4:
	.string	"/home/ubuntu/Datasets/stackv2/train-structured/mpreziuso/crunch/master/main.cu"
.LC5:
	.string	"SMs: %d, X: %d, Y: %d\n"
.LC6:
	.string	"grid: %d, min grid: %d, block: %d\n"
.LC7:
	.string	"%02x "
.LC8:
	.string	"\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2039:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	xorl	%esi, %esi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$1288, %rsp
	.cfi_def_cfa_offset 1344
	movq	%fs:40, %rax
	movq	%rax, 1272(%rsp)
	xorl	%eax, %eax
	leaq	240(%rsp), %rbx
	movq	%rbx, %rdi
	call	cudaGetDeviceProperties_v2@PLT
	movl	%eax, %edx
	orl	$-1, %eax
	testl	%edx, %edx
	jne	.L37
	movl	628(%rsp), %ecx
	movq	%rbx, %rdx
	movl	$2, %edi
	xorl	%eax, %eax
	leaq	.LC1(%rip), %rsi
	call	__printf_chk@PLT
	xorl	%edi, %edi
	call	cudaSetDevice@PLT
	leaq	32(%rsp), %rdi
	xorl	%edx, %edx
	movl	$16, %esi
	call	cudaDeviceGetAttribute@PLT
	movl	$4, %edi
	call	cudaSetDeviceFlags@PLT
	movl	%eax, %ecx
	testl	%eax, %eax
	je	.L39
	movq	stderr(%rip), %rdi
	leaq	.LC2(%rip), %rdx
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
.L39:
	leaq	48(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	56(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	48(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	leaq	36(%rsp), %rdi
	call	cudaGetDevice@PLT
	testl	%eax, %eax
	leaq	44(%rsp), %rax
	movq	%rax, (%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 8(%rsp)
	jne	.L41
	movl	36(%rsp), %edx
	leaq	40(%rsp), %rdi
	movl	$39, %esi
	call	cudaDeviceGetAttribute@PLT
	testl	%eax, %eax
	jne	.L41
	movl	36(%rsp), %edx
	movq	(%rsp), %rdi
	movl	$10, %esi
	call	cudaDeviceGetAttribute@PLT
	testl	%eax, %eax
	jne	.L41
	movl	36(%rsp), %edx
	movq	8(%rsp), %rdi
	movl	$1, %esi
	call	cudaDeviceGetAttribute@PLT
	testl	%eax, %eax
	jne	.L41
	movl	36(%rsp), %edx
	leaq	72(%rsp), %rdi
	movl	$16, %esi
	call	cudaDeviceGetAttribute@PLT
	testl	%eax, %eax
	jne	.L41
	leaq	96(%rsp), %rdi
	leaq	_Z12PBKDF2KerneliPh(%rip), %rsi
	call	cudaFuncGetAttributes@PLT
	testl	%eax, %eax
	jne	.L41
	movl	40(%rsp), %eax
	movl	120(%rsp), %ebx
	movl	44(%rsp), %r15d
	movl	%eax, 16(%rsp)
	movl	64(%rsp), %eax
	cmpl	%eax, %ebx
	cmovg	%eax, %ebx
	movl	$1, %eax
	testl	%ebx, %ebx
	cmovg	%eax, %ebx
	xorl	%r14d, %r14d
	xorl	%r13d, %r13d
	xorl	%r12d, %r12d
	leal	-1(%r15,%rbx), %ebp
	movl	%ebp, %eax
	cltd
	idivl	%r15d
	leaq	84(%rsp), %rax
	movq	%rax, 24(%rsp)
	subl	%edx, %ebp
.L43:
	testl	%ebp, %ebp
	jle	.L45
	movq	24(%rsp), %rdi
	xorl	%r8d, %r8d
	xorl	%ecx, %ecx
	movl	%ebx, %edx
	leaq	_Z12PBKDF2KerneliPh(%rip), %rsi
	call	cudaOccupancyMaxActiveBlocksPerMultiprocessorWithFlags@PLT
	testl	%eax, %eax
	jne	.L41
	movl	84(%rsp), %eax
	movl	%ebx, %edx
	imull	%eax, %edx
	cmpl	%r14d, %edx
	jle	.L44
	movl	%edx, %r14d
	movl	%eax, %r13d
	movl	%ebx, %r12d
.L44:
	cmpl	%r14d, 16(%rsp)
	je	.L45
	subl	%r15d, %ebp
	jmp	.L43
.L45:
	imull	72(%rsp), %r13d
	movl	%r13d, 20(%rsp)
.L41:
	movq	56(%rsp), %rdi
	xorl	%esi, %esi
	leaq	.LC4(%rip), %rbx
	call	cudaEventRecord@PLT
	movq	56(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	56(%rsp), %rdx
	movq	48(%rsp), %rsi
	movq	(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	44(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	8(%rsp), %rdi
	movl	$1, %edx
	movl	$32, %esi
	call	cudaMallocManaged@PLT
	call	cudaGetLastError@PLT
	movl	$1, %ecx
	movl	$69, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcibb.isra.0
	movl	32(%rsp), %edx
	movl	$2, %edi
	xorl	%eax, %eax
	movl	$512, %r8d
	leaq	.LC5(%rip), %rsi
	movl	%edx, %ecx
	sall	$5, %ecx
	call	__printf_chk@PLT
	movl	20(%rsp), %ecx
	movl	%r12d, %r8d
	xorl	%eax, %eax
	movl	$1, %edx
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	movl	%r12d, 84(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rdi
	movl	$1, %esi
	movl	$1, 80(%rsp)
	movq	%rdi, 88(%rsp)
	movl	92(%rsp), %ecx
	movq	84(%rsp), %rdx
	movq	%rdi, 72(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L47
	movq	64(%rsp), %rsi
	movl	$1, %edi
	call	_Z33__device_stub__Z12PBKDF2KerneliPhiPh
.L47:
	call	cudaDeviceSynchronize@PLT
	movq	%rbx, %rsi
	movl	$1, %ecx
	movl	$74, %edx
	movl	%eax, %edi
	leaq	.LC7(%rip), %rbp
	call	_Z9gpuAssert9cudaErrorPKcibb.isra.0
	call	cudaGetLastError@PLT
	movq	%rbx, %rsi
	movl	$1, %ecx
	xorl	%ebx, %ebx
	movl	%eax, %edi
	movl	$75, %edx
	call	_Z9gpuAssert9cudaErrorPKcibb.isra.0
.L48:
	movq	64(%rsp), %rax
	movq	%rbp, %rsi
	movl	$2, %edi
	movzbl	(%rax,%rbx), %edx
	xorl	%eax, %eax
	incq	%rbx
	call	__printf_chk@PLT
	cmpq	$32, %rbx
	jne	.L48
	leaq	.LC8(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	call	cudaDeviceReset@PLT
	xorl	%eax, %eax
.L37:
	movq	1272(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L49
	call	__stack_chk_fail@PLT
.L49:
	addq	$1288, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2039:
	.size	main, .-main
	.section	.rodata.str1.1
.LC9:
	.string	"_Z12PBKDF2KerneliPh"
.LC10:
	.string	"k256"
.LC11:
	.string	"ITERATIONS"
.LC12:
	.string	"SHA256_IPAD_CONST"
.LC13:
	.string	"SHA256_OPAD_CONST"
.LC14:
	.string	"cuda_init_derive"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2067:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC9(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z12PBKDF2KerneliPh(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC10(%rip), %rdx
	movl	$256, %r9d
	leaq	_ZL4k256(%rip), %rsi
	pushq	$1
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC11(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$4, %r9d
	leaq	_ZL10ITERATIONS(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC12(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZL17SHA256_IPAD_CONST(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC13(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZL17SHA256_OPAD_CONST(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC14(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$32, %r9d
	movq	%rdx, %rcx
	leaq	_ZL16cuda_init_derive(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2067:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL16cuda_init_derive
	.comm	_ZL16cuda_init_derive,32,32
	.local	_ZL17SHA256_OPAD_CONST
	.comm	_ZL17SHA256_OPAD_CONST,1,1
	.local	_ZL17SHA256_IPAD_CONST
	.comm	_ZL17SHA256_IPAD_CONST,1,1
	.local	_ZL10ITERATIONS
	.comm	_ZL10ITERATIONS,4,4
	.section	.rodata
	.align 32
	.type	_ZL4k256, @object
	.size	_ZL4k256, 256
_ZL4k256:
	.long	1116352408
	.long	1899447441
	.long	-1245643825
	.long	-373957723
	.long	961987163
	.long	1508970993
	.long	-1841331548
	.long	-1424204075
	.long	-670586216
	.long	310598401
	.long	607225278
	.long	1426881987
	.long	1925078388
	.long	-2132889090
	.long	-1680079193
	.long	-1046744716
	.long	-459576895
	.long	-272742522
	.long	264347078
	.long	604807628
	.long	770255983
	.long	1249150122
	.long	1555081692
	.long	1996064986
	.long	-1740746414
	.long	-1473132947
	.long	-1341970488
	.long	-1084653625
	.long	-958395405
	.long	-710438585
	.long	113926993
	.long	338241895
	.long	666307205
	.long	773529912
	.long	1294757372
	.long	1396182291
	.long	1695183700
	.long	1986661051
	.long	-2117940946
	.long	-1838011259
	.long	-1564481375
	.long	-1474664885
	.long	-1035236496
	.long	-949202525
	.long	-778901479
	.long	-694614492
	.long	-200395387
	.long	275423344
	.long	430227734
	.long	506948616
	.long	659060556
	.long	883997877
	.long	958139571
	.long	1322822218
	.long	1537002063
	.long	1747873779
	.long	1955562222
	.long	2024104815
	.long	-2067236844
	.long	-1933114872
	.long	-1866530822
	.long	-1538233109
	.long	-1090935817
	.long	-965641998
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <cmath>
#include "Cuda/PBKDF2.cu"

#define ERRCHECK(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true,bool wait=true) {
   if (code != hipSuccess) {
      fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
      if (abort) exit(code);
   }
}

#define SHA256_DIGESTSIZE 32
#define SHA256_BLOCKSIZE 64

__global__ void PBKDF2Kernel(int n, unsigned char *out) {
  unsigned char passwd[22] = "governor washout beak";
  int pwd_len = sizeof(passwd) - 1;
  for (int i = blockIdx.x * blockDim.x + threadIdx.x; i<n; i += blockDim.x * gridDim.x) {
    cuda_derive_key_sha256(passwd, pwd_len, &out[SHA256_DIGESTSIZE*i]);
  }
}

int main() {
  hipError_t err;
  int device = 0;
  int numSMs;
  const int N = 1;

  hipDeviceProp_t props;
  err = hipGetDeviceProperties(&props, device);

  if(err) { return -1; }

  printf("%s (%2d)\n", props.name, props.multiProcessorCount);
  hipSetDevice(device);
  hipDeviceGetAttribute(&numSMs, hipDeviceAttributeMultiprocessorCount, device);

  hipError_t error;
  /* Stop eating CPU while waiting for results! */
  error = hipSetDeviceFlags(hipDeviceScheduleBlockingSync);
  if (error != hipSuccess) { 
    fprintf(stderr, "Could not set blocking sync (error %d)\n", error);
  }


  int blockSize;      // The launch configurator returned block size 
  int minGridSize;    // The minimum grid size needed to achieve the maximum occupancy for a full device launch 
  int gridSize;       // The actual grid size needed, based on input size 

  float time;
  hipEvent_t start, stop;
  hipEventCreate(&start);
  hipEventCreate(&stop);
  hipEventRecord(start, 0);

  hipOccupancyMaxPotentialBlockSize(&minGridSize, &blockSize, PBKDF2Kernel, 0, N); 

  // Round up according to array size 
  gridSize = (N + blockSize - 1) / blockSize; 

  hipEventRecord(stop, 0);
  hipEventSynchronize(stop);
  hipEventElapsedTime(&time, start, stop);
  printf("Occupancy calculator elapsed time:  %3.3f ms \n", time);

  unsigned char *finalDestination;
  hipMallocManaged((void **)&finalDestination, N*SHA256_DIGESTSIZE);
  ERRCHECK(hipGetLastError());
  printf("SMs: %d, X: %d, Y: %d\n", numSMs, 32*numSMs, 512);
  printf("grid: %d, min grid: %d, block: %d\n", gridSize, minGridSize, blockSize);
  //PBKDF2Kernel<<<1,1>>>(N, 100000, d_hash);
  PBKDF2Kernel<<<gridSize,blockSize>>>(N, finalDestination);
  ERRCHECK(hipDeviceSynchronize());
  ERRCHECK(hipGetLastError());

  for(int i = 0; i < N; i++) {
    for(int j = 0; j < SHA256_DIGESTSIZE; j++) {
      printf("%02x ", finalDestination[i*SHA256_DIGESTSIZE+j]);
    }
    printf("\n");
  }
  hipFree(finalDestination);
  hipDeviceReset();
  return 0;
}

	.text
	.file	"main.hip"
	.globl	_Z27__device_stub__PBKDF2KerneliPh # -- Begin function _Z27__device_stub__PBKDF2KerneliPh
	.type	_Z27__device_stub__PBKDF2KerneliPh,@function
_Z27__device_stub__PBKDF2KerneliPh:     # @_Z27__device_stub__PBKDF2KerneliPh
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	leaq	24(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12PBKDF2KerneliPh, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z27__device_stub__PBKDF2KerneliPh, .Lfunc_end0-_Z27__device_stub__PBKDF2KerneliPh
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	subq	$1528, %rsp                     # imm = 0x5F8
	.cfi_def_cfa_offset 1552
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	leaq	56(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipGetDevicePropertiesR0600
	movl	%eax, %ecx
	movl	$-1, %eax
	testl	%ecx, %ecx
	jne	.LBB1_14
# %bb.1:
	leaq	56(%rsp), %rsi
	movl	388(%rsi), %edx
	movl	$.L.str, %edi
	xorl	%eax, %eax
	callq	printf
	xorl	%edi, %edi
	callq	hipSetDevice
	leaq	32(%rsp), %rdi
	movl	$63, %esi
	xorl	%edx, %edx
	callq	hipDeviceGetAttribute
	movl	$4, %edi
	callq	hipSetDeviceFlags
	testl	%eax, %eax
	jne	.LBB1_2
.LBB1_3:
	leaq	48(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventCreate
	leaq	40(%rsp), %r14
	movq	%r14, %rdi
	callq	hipEventCreate
	movq	(%rbx), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	leaq	28(%rsp), %rdi
	leaq	12(%rsp), %rsi
	movl	$_Z12PBKDF2KerneliPh, %edx
	xorl	%ecx, %ecx
	movl	$1, %r8d
	callq	hipOccupancyMaxPotentialBlockSize
	movq	(%r14), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	(%r14), %rdi
	callq	hipEventSynchronize
	movq	(%rbx), %rsi
	movq	(%r14), %rdx
	leaq	36(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	cvtss2sd	(%rbx), %xmm0
	movl	$.L.str.2, %edi
	movb	$1, %al
	callq	printf
	leaq	16(%rsp), %rdi
	movl	$32, %esi
	movl	$1, %edx
	callq	hipMallocManaged
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB1_4
# %bb.6:                                # %_Z9gpuAssert10hipError_tPKcibb.exit
	movl	32(%rsp), %esi
	movl	%esi, %edx
	shll	$5, %edx
	movl	$.L.str.4, %edi
	movl	$512, %ecx                      # imm = 0x200
	xorl	%eax, %eax
	callq	printf
	movl	28(%rsp), %edx
	movl	12(%rsp), %ecx
	movl	$.L.str.5, %edi
	movl	$1, %esi
	xorl	%eax, %eax
	callq	printf
	movl	12(%rsp), %edx
	btsq	$32, %rdx
	movabsq	$4294967296, %rdi               # imm = 0x100000000
	orq	$1, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_8
# %bb.7:
	movq	16(%rsp), %rsi
	movl	$1, %edi
	callq	_Z27__device_stub__PBKDF2KerneliPh
.LBB1_8:                                # %.critedge
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB1_9
# %bb.10:                               # %_Z9gpuAssert10hipError_tPKcibb.exit23
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB1_15
# %bb.11:                               # %_Z9gpuAssert10hipError_tPKcibb.exit25.preheader
	xorl	%ebx, %ebx
.LBB1_12:                               # %_Z9gpuAssert10hipError_tPKcibb.exit25
                                        # =>This Inner Loop Header: Depth=1
	movq	16(%rsp), %rax
	movzbl	(%rax,%rbx), %esi
	movl	$.L.str.6, %edi
	xorl	%eax, %eax
	callq	printf
	incq	%rbx
	cmpq	$32, %rbx
	jne	.LBB1_12
# %bb.13:
	movl	$10, %edi
	callq	putchar@PLT
	movq	16(%rsp), %rdi
	callq	hipFree
	callq	hipDeviceReset
	xorl	%eax, %eax
.LBB1_14:
	addq	$1528, %rsp                     # imm = 0x5F8
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.LBB1_2:
	.cfi_def_cfa_offset 1552
	movq	stderr(%rip), %rdi
	movl	$.L.str.1, %esi
	movl	%eax, %edx
	xorl	%eax, %eax
	callq	fprintf
	jmp	.LBB1_3
.LBB1_4:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.8, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$71, %r8d
	jmp	.LBB1_5
.LBB1_9:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.8, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$76, %r8d
	jmp	.LBB1_5
.LBB1_15:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.8, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$77, %r8d
.LBB1_5:
	xorl	%eax, %eax
	callq	fprintf
	movl	%ebx, %edi
	callq	exit
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	subq	$32, %rsp
	.cfi_adjust_cfa_offset 32
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12PBKDF2KerneliPh, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
	movl	$ITERATIONS, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movl	$4, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$SHA256_IPAD_CONST, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movl	$1, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$SHA256_OPAD_CONST, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movl	$1, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$cuda_init_derive, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movl	$32, %r9d
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$__hip_module_dtor, %edi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	ITERATIONS,@object              # @ITERATIONS
	.local	ITERATIONS
	.comm	ITERATIONS,4,4
	.type	SHA256_IPAD_CONST,@object       # @SHA256_IPAD_CONST
	.local	SHA256_IPAD_CONST
	.comm	SHA256_IPAD_CONST,1,1
	.type	SHA256_OPAD_CONST,@object       # @SHA256_OPAD_CONST
	.local	SHA256_OPAD_CONST
	.comm	SHA256_OPAD_CONST,1,1
	.type	cuda_init_derive,@object        # @cuda_init_derive
	.local	cuda_init_derive
	.comm	cuda_init_derive,32,16
	.type	_Z12PBKDF2KerneliPh,@object     # @_Z12PBKDF2KerneliPh
	.section	.rodata,"a",@progbits
	.globl	_Z12PBKDF2KerneliPh
	.p2align	3, 0x0
_Z12PBKDF2KerneliPh:
	.quad	_Z27__device_stub__PBKDF2KerneliPh
	.size	_Z12PBKDF2KerneliPh, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"%s (%2d)\n"
	.size	.L.str, 10

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Could not set blocking sync (error %d)\n"
	.size	.L.str.1, 40

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Occupancy calculator elapsed time:  %3.3f ms \n"
	.size	.L.str.2, 47

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"/home/ubuntu/Datasets/stackv2/train-structured-repos-hip-sm89/mpreziuso/crunch/master/main.hip"
	.size	.L.str.3, 95

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"SMs: %d, X: %d, Y: %d\n"
	.size	.L.str.4, 23

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"grid: %d, min grid: %d, block: %d\n"
	.size	.L.str.5, 35

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"%02x "
	.size	.L.str.6, 6

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"GPUassert: %s %s %d\n"
	.size	.L.str.8, 21

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z12PBKDF2KerneliPh"
	.size	.L__unnamed_1, 20

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"ITERATIONS"
	.size	.L__unnamed_2, 11

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"SHA256_IPAD_CONST"
	.size	.L__unnamed_3, 18

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"SHA256_OPAD_CONST"
	.size	.L__unnamed_4, 18

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"cuda_init_derive"
	.size	.L__unnamed_5, 17

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z27__device_stub__PBKDF2KerneliPh
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym ITERATIONS
	.addrsig_sym SHA256_IPAD_CONST
	.addrsig_sym SHA256_OPAD_CONST
	.addrsig_sym cuda_init_derive
	.addrsig_sym _Z12PBKDF2KerneliPh
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z12PBKDF2KerneliPh     ; -- Begin function _Z12PBKDF2KerneliPh
	.globl	_Z12PBKDF2KerneliPh
	.p2align	8
	.type	_Z12PBKDF2KerneliPh,@function
_Z12PBKDF2KerneliPh:                    ; @_Z12PBKDF2KerneliPh
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x1c
	s_load_b32 s12, s[0:1], 0x0
	s_add_u32 s2, s0, 16
	s_addc_u32 s3, s1, 0
	v_mov_b32_e32 v2, 0x73617720
	v_mov_b32_e32 v3, 0x74756f68
	v_mov_b32_e32 v4, 0x6b
	v_mov_b32_e32 v5, 0x61656220
	s_mov_b32 s5, exec_lo
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[8:9], null, s15, s4, v[0:1]
	v_mov_b32_e32 v0, 0x65766f67
	v_mov_b32_e32 v1, 0x726f6e72
	s_clause 0x2
	scratch_store_b128 off, v[0:3], off offset:624
	scratch_store_b16 off, v4, off offset:644
	scratch_store_b32 off, v5, off offset:640
	v_cmpx_gt_i32_e64 s12, v8
	s_cbranch_execz .LBB0_422
; %bb.1:                                ; %.lr.ph
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v20, 0x208
	s_getpc_b64 s[6:7]
	s_add_u32 s6, s6, SHA256_IPAD_CONST@rel32@lo+4
	s_addc_u32 s7, s7, SHA256_IPAD_CONST@rel32@hi+12
	s_getpc_b64 s[8:9]
	s_add_u32 s8, s8, SHA256_OPAD_CONST@rel32@lo+4
	s_addc_u32 s9, s9, SHA256_OPAD_CONST@rel32@hi+12
	v_dual_mov_b32 v19, 0x1a0 :: v_dual_mov_b32 v4, 64
	s_clause 0x1
	global_load_u8 v17, v1, s[6:7]
	global_load_u8 v18, v1, s[8:9]
	s_getpc_b64 s[6:7]
	s_add_u32 s6, s6, ITERATIONS@rel32@lo+4
	s_addc_u32 s7, s7, ITERATIONS@rel32@hi+12
	s_load_b32 s13, s[6:7], 0x0
	s_load_b32 s19, s[2:3], 0x0
	s_load_b64 s[2:3], s[0:1], 0x8
	s_add_i32 s14, 0x1a0, 40
	s_add_i32 s15, 0x208, 40
	s_add_i32 s16, 48, 40
	s_add_i32 s17, 48, 8
	v_dual_mov_b32 v21, 48 :: v_dual_mov_b32 v24, 0x120
	v_add_nc_u32_e64 v22, 48, 36
	v_dual_mov_b32 v2, 0x6a09e667 :: v_dual_lshlrev_b32 v23, 5, v8
	v_dual_mov_b32 v25, 0x160 :: v_dual_mov_b32 v26, 16
	v_mov_b32_e32 v3, 0xbb67ae85
	v_mov_b32_e32 v27, 0x98
	s_mov_b32 s8, 0x1f83d9ab
	s_mov_b32 s1, 0
	s_mov_b32 s7, 0x9b05688c
	s_mov_b32 s6, 0x510e527f
	s_waitcnt lgkmcnt(0)
	s_cmp_gt_i32 s13, 1
	s_mul_i32 s19, s19, s4
	s_cselect_b32 s18, -1, 0
	s_lshl_b32 s20, s19, 5
	s_mov_b32 s9, 0x5be0cd19
	s_mov_b32 s5, 0xa54ff53a
	s_mov_b32 s4, 0x3c6ef372
	s_mov_b32 s21, 0
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_3 Depth 2
                                        ;     Child Loop BB0_5 Depth 2
                                        ;     Child Loop BB0_7 Depth 2
                                        ;     Child Loop BB0_9 Depth 2
                                        ;     Child Loop BB0_11 Depth 2
                                        ;     Child Loop BB0_13 Depth 2
                                        ;     Child Loop BB0_15 Depth 2
                                        ;       Child Loop BB0_16 Depth 3
                                        ;     Child Loop BB0_24 Depth 2
                                        ;     Child Loop BB0_26 Depth 2
                                        ;     Child Loop BB0_28 Depth 2
                                        ;     Child Loop BB0_30 Depth 2
                                        ;     Child Loop BB0_32 Depth 2
                                        ;       Child Loop BB0_33 Depth 3
                                        ;     Child Loop BB0_41 Depth 2
                                        ;     Child Loop BB0_46 Depth 2
                                        ;       Child Loop BB0_48 Depth 3
                                        ;       Child Loop BB0_59 Depth 3
                                        ;       Child Loop BB0_61 Depth 3
                                        ;       Child Loop BB0_63 Depth 3
                                        ;         Child Loop BB0_64 Depth 4
                                        ;       Child Loop BB0_72 Depth 3
                                        ;     Child Loop BB0_77 Depth 2
                                        ;     Child Loop BB0_89 Depth 2
                                        ;     Child Loop BB0_96 Depth 2
                                        ;     Child Loop BB0_98 Depth 2
                                        ;       Child Loop BB0_99 Depth 3
                                        ;     Child Loop BB0_107 Depth 2
                                        ;     Child Loop BB0_110 Depth 2
                                        ;     Child Loop BB0_120 Depth 2
                                        ;     Child Loop BB0_122 Depth 2
                                        ;       Child Loop BB0_123 Depth 3
                                        ;     Child Loop BB0_131 Depth 2
                                        ;     Child Loop BB0_133 Depth 2
                                        ;     Child Loop BB0_135 Depth 2
                                        ;     Child Loop BB0_140 Depth 2
                                        ;       Child Loop BB0_142 Depth 3
                                        ;       Child Loop BB0_153 Depth 3
                                        ;       Child Loop BB0_155 Depth 3
                                        ;       Child Loop BB0_157 Depth 3
                                        ;         Child Loop BB0_158 Depth 4
                                        ;       Child Loop BB0_166 Depth 3
                                        ;     Child Loop BB0_171 Depth 2
                                        ;     Child Loop BB0_183 Depth 2
                                        ;     Child Loop BB0_190 Depth 2
                                        ;     Child Loop BB0_192 Depth 2
                                        ;       Child Loop BB0_193 Depth 3
                                        ;     Child Loop BB0_201 Depth 2
                                        ;     Child Loop BB0_204 Depth 2
                                        ;     Child Loop BB0_214 Depth 2
                                        ;     Child Loop BB0_216 Depth 2
                                        ;       Child Loop BB0_217 Depth 3
                                        ;     Child Loop BB0_225 Depth 2
                                        ;     Child Loop BB0_227 Depth 2
                                        ;     Child Loop BB0_229 Depth 2
                                        ;     Child Loop BB0_232 Depth 2
                                        ;       Child Loop BB0_236 Depth 3
                                        ;         Child Loop BB0_238 Depth 4
                                        ;         Child Loop BB0_249 Depth 4
                                        ;         Child Loop BB0_251 Depth 4
                                        ;         Child Loop BB0_253 Depth 4
                                        ;           Child Loop BB0_254 Depth 5
                                        ;         Child Loop BB0_262 Depth 4
                                        ;       Child Loop BB0_267 Depth 3
                                        ;       Child Loop BB0_279 Depth 3
                                        ;       Child Loop BB0_286 Depth 3
                                        ;       Child Loop BB0_288 Depth 3
                                        ;         Child Loop BB0_289 Depth 4
                                        ;       Child Loop BB0_297 Depth 3
                                        ;       Child Loop BB0_300 Depth 3
                                        ;       Child Loop BB0_310 Depth 3
                                        ;       Child Loop BB0_312 Depth 3
                                        ;         Child Loop BB0_313 Depth 4
                                        ;       Child Loop BB0_321 Depth 3
                                        ;       Child Loop BB0_323 Depth 3
                                        ;       Child Loop BB0_325 Depth 3
                                        ;       Child Loop BB0_330 Depth 3
                                        ;         Child Loop BB0_332 Depth 4
                                        ;         Child Loop BB0_343 Depth 4
                                        ;         Child Loop BB0_345 Depth 4
                                        ;         Child Loop BB0_347 Depth 4
                                        ;           Child Loop BB0_348 Depth 5
                                        ;         Child Loop BB0_356 Depth 4
                                        ;       Child Loop BB0_361 Depth 3
                                        ;       Child Loop BB0_373 Depth 3
                                        ;       Child Loop BB0_380 Depth 3
                                        ;       Child Loop BB0_382 Depth 3
                                        ;         Child Loop BB0_383 Depth 4
                                        ;       Child Loop BB0_391 Depth 3
                                        ;       Child Loop BB0_394 Depth 3
                                        ;       Child Loop BB0_404 Depth 3
                                        ;       Child Loop BB0_406 Depth 3
                                        ;         Child Loop BB0_407 Depth 4
                                        ;       Child Loop BB0_415 Depth 3
                                        ;       Child Loop BB0_417 Depth 3
                                        ;       Child Loop BB0_419 Depth 3
	s_mov_b64 s[10:11], 43
	s_mov_b32 s0, s1
.LBB0_3:                                ; %.lr.ph.i.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_readfirstlane_b32 s22, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s22, s22, s0
	s_add_i32 s23, s22, 21
	s_add_i32 s24, s22, 22
	s_add_i32 s25, s22, 23
	s_add_i32 s22, s22, 24
	s_add_u32 s10, s10, -4
	s_addc_u32 s11, s11, -1
	s_add_i32 s0, s0, 4
	v_cmp_gt_u64_e64 s26, s[10:11], 3
	s_waitcnt vmcnt(1)
	s_clause 0x3
	scratch_store_b8 off, v17, s23
	scratch_store_b8 off, v17, s24
	scratch_store_b8 off, v17, s25
	scratch_store_b8 off, v17, s22
	s_and_b32 vcc_lo, exec_lo, s26
	s_cbranch_vccnz .LBB0_3
; %bb.4:                                ; %._crit_edge.i.i.i
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_readfirstlane_b32 s22, v24
	s_mov_b64 s[10:11], 43
	s_delay_alu instid0(VALU_DEP_1)
	s_add_i32 s22, s22, s0
	s_mov_b32 s0, 0
	s_add_i32 s23, s22, 23
	s_add_i32 s24, s22, 22
	s_add_i32 s22, s22, 21
	s_clause 0x2
	scratch_store_b8 off, v17, s23
	scratch_store_b8 off, v17, s24
	scratch_store_b8 off, v17, s22
.LBB0_5:                                ; %.lr.ph.i.i21.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_readfirstlane_b32 s22, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s22, s22, s0
	s_add_i32 s23, s22, 21
	s_add_i32 s24, s22, 22
	s_add_i32 s25, s22, 23
	s_add_i32 s22, s22, 24
	s_add_u32 s10, s10, -4
	s_addc_u32 s11, s11, -1
	s_add_i32 s0, s0, 4
	v_cmp_gt_u64_e64 s26, s[10:11], 3
	s_waitcnt vmcnt(0)
	s_clause 0x3
	scratch_store_b8 off, v18, s23
	scratch_store_b8 off, v18, s24
	scratch_store_b8 off, v18, s25
	scratch_store_b8 off, v18, s22
	s_and_b32 vcc_lo, exec_lo, s26
	s_cbranch_vccnz .LBB0_5
; %bb.6:                                ; %._crit_edge.i.i24.i
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_readfirstlane_b32 s10, v25
	s_delay_alu instid0(VALU_DEP_1)
	s_add_i32 s10, s10, s0
	s_mov_b32 s0, 0
	s_add_i32 s11, s10, 23
	s_add_i32 s22, s10, 22
	s_add_i32 s10, s10, 21
	s_clause 0x2
	scratch_store_b8 off, v18, s11
	scratch_store_b8 off, v18, s22
	scratch_store_b8 off, v18, s10
.LBB0_7:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_add_i32 s10, s0, 0x270
	s_add_i32 s11, s0, 0x160
	scratch_load_u8 v0, off, s10
	s_add_i32 s10, s0, 0x120
	s_add_i32 s0, s0, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s0, 21
	s_waitcnt vmcnt(0)
	v_xor_b32_e32 v5, v0, v17
	v_xor_b32_e32 v0, v0, v18
	scratch_store_b8 off, v5, s10
	scratch_store_b8 off, v0, s11
	s_cbranch_scc1 .LBB0_7
; %bb.8:                                ; %.lr.ph.i.i
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_dual_mov_b32 v14, s9 :: v_dual_mov_b32 v13, s8
	v_dual_mov_b32 v12, s7 :: v_dual_mov_b32 v11, s6
	v_dual_mov_b32 v0, v1 :: v_dual_mov_b32 v7, v3
	v_dual_mov_b32 v10, s5 :: v_dual_mov_b32 v9, s4
	s_movk_i32 s10, 0xffc0
	s_mov_b32 s0, 0
	s_mov_b32 s11, -1
	v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v6, v2
	s_clause 0x5
	scratch_store_b64 off, v[13:14], off offset:448
	scratch_store_b128 off, v[0:3], off offset:520
	scratch_store_b128 off, v[9:12], off offset:536
	scratch_store_b64 off, v[13:14], off offset:552
	scratch_store_b128 off, v[9:12], off offset:432
	scratch_store_b128 off, v[4:7], off offset:416
.LBB0_9:                                ; %.lr.ph.i.i.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_readfirstlane_b32 s22, v24
	s_add_i32 s23, s0, 0x120
	scratch_load_u8 v0, off, s23
	s_add_i32 s22, s22, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s23, s22, 1
	s_add_i32 s24, s22, 2
	s_add_i32 s22, s22, 3
	s_clause 0x2
	scratch_load_u8 v5, off, s23
	scratch_load_u8 v6, off, s24
	scratch_load_u8 v7, off, s22
	v_readfirstlane_b32 s22, v19
	s_delay_alu instid0(VALU_DEP_1)
	s_add_i32 s22, s22, s0
	s_add_i32 s0, s0, 4
	s_add_i32 s23, s22, 40
	s_add_i32 s24, s22, 41
	s_add_i32 s25, s22, 42
	s_add_i32 s22, s22, 43
	s_add_u32 s10, s10, 4
	s_addc_u32 s11, s11, 0
	s_waitcnt vmcnt(3)
	scratch_store_b8 off, v0, s23
	s_waitcnt vmcnt(2)
	scratch_store_b8 off, v5, s24
	s_waitcnt vmcnt(1)
	scratch_store_b8 off, v6, s25
	s_waitcnt vmcnt(0)
	scratch_store_b8 off, v7, s22
	s_cmp_lg_u64 s[10:11], 0
	s_cbranch_scc1 .LBB0_9
; %bb.10:                               ; %_ZL6memcpyPvPKvm.exit.i.i.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_movk_i32 s0, 0x64
.LBB0_11:                               ; %_ZL6memcpyPvPKvm.exit.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s10, s0, 0x1a0
	s_add_i32 s0, s0, -4
	scratch_load_b32 v0, off, s10
	s_cmp_lg_u32 s0, 36
	s_waitcnt vmcnt(0)
	v_perm_b32 v0, 0, v0, 0x10203
	scratch_store_b32 off, v0, s10
	s_cbranch_scc1 .LBB0_11
; %bb.12:                               ;   in Loop: Header=BB0_2 Depth=1
	s_movk_i32 s10, 0xffe0
	s_mov_b32 s11, -1
	s_mov_b32 s0, 0
.LBB0_13:                               ; %.lr.ph.i.i.i275.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_readfirstlane_b32 s22, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s22, s22, s0
	s_add_i32 s23, s22, 8
	s_add_i32 s24, s22, 9
	s_add_i32 s25, s22, 10
	s_add_i32 s22, s22, 11
	s_clause 0x3
	scratch_load_u8 v0, off, s23
	scratch_load_u8 v5, off, s24
	scratch_load_u8 v6, off, s25
	scratch_load_u8 v7, off, s22
	v_readfirstlane_b32 s22, v21
	s_add_i32 s23, s0, 48
	s_delay_alu instid0(VALU_DEP_1)
	s_add_i32 s22, s22, s0
	s_add_i32 s0, s0, 4
	s_add_i32 s24, s22, 1
	s_add_i32 s25, s22, 2
	s_add_i32 s22, s22, 3
	s_add_u32 s10, s10, 4
	s_addc_u32 s11, s11, 0
	s_waitcnt vmcnt(3)
	scratch_store_b8 off, v0, s23
	s_waitcnt vmcnt(2)
	scratch_store_b8 off, v5, s24
	s_waitcnt vmcnt(1)
	scratch_store_b8 off, v6, s25
	s_waitcnt vmcnt(0)
	scratch_store_b8 off, v7, s22
	s_cmp_lg_u64 s[10:11], 0
	s_cbranch_scc1 .LBB0_13
; %bb.14:                               ; %.preheader14.i.i.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s10, 0
.LBB0_15:                               ; %.preheader14.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_16 Depth 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s10, 0
	s_mov_b32 s22, 0
	s_cselect_b32 s11, -1, 0
.LBB0_16:                               ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_15 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sub_i32 s0, 4, s22
	s_sub_i32 s23, 0, s22
	s_and_b32 s0, s0, 7
	s_and_b32 s23, s23, 7
	s_lshl_b32 s0, s0, 2
	s_lshl_b32 s23, s23, 2
	s_add_i32 s0, s0, 48
	s_add_i32 s23, s23, 48
	s_clause 0x1
	scratch_load_b32 v5, off, s0
	scratch_load_b32 v0, off, s23
	s_and_not1_b32 vcc_lo, exec_lo, s11
	s_cbranch_vccnz .LBB0_18
; %bb.17:                               ;   in Loop: Header=BB0_16 Depth=3
	s_add_i32 s0, s22, 14
	s_add_i32 s23, s22, 1
	s_and_b32 s0, s0, 15
	s_and_b32 s24, s23, 15
	s_lshl_b32 s0, s0, 2
	s_lshl_b32 s24, s24, 2
	s_add_i32 s0, s14, s0
	scratch_load_b32 v6, off, s0
	s_add_i32 s0, s14, s24
	s_add_i32 s24, s22, 9
	scratch_load_b32 v7, off, s0
	s_and_b32 s0, s24, 15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s0, s0, 2
	s_add_i32 s0, s14, s0
	scratch_load_b32 v9, off, s0
	s_lshl_b32 s0, s22, 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s24, s14, s0
	s_mov_b32 s0, 0
	scratch_load_b32 v10, off, s24
	s_waitcnt vmcnt(3)
	v_alignbit_b32 v11, v6, v6, 17
	v_alignbit_b32 v12, v6, v6, 19
	v_lshrrev_b32_e32 v6, 10, v6
	s_waitcnt vmcnt(2)
	v_alignbit_b32 v13, v7, v7, 7
	v_alignbit_b32 v14, v7, v7, 18
	v_lshrrev_b32_e32 v7, 3, v7
	v_xor_b32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor3_b32 v7, v13, v14, v7
	s_waitcnt vmcnt(1)
	v_xad_u32 v6, v11, v6, v9
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v6, v6, v10, v7
	scratch_store_b32 off, v6, s24
	s_branch .LBB0_19
.LBB0_18:                               ;   in Loop: Header=BB0_16 Depth=3
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr6
                                        ; implicit-def: $sgpr23
.LBB0_19:                               ; %Flow953
                                        ;   in Loop: Header=BB0_16 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_21
; %bb.20:                               ;   in Loop: Header=BB0_16 Depth=3
	s_lshl_b32 s0, s22, 2
	s_add_i32 s23, s22, 1
	s_add_i32 s0, s14, s0
	scratch_load_b32 v6, off, s0
.LBB0_21:                               ; %m_cycle.exit.i.i
                                        ;   in Loop: Header=BB0_16 Depth=3
	s_getpc_b64 s[24:25]
	s_add_u32 s24, s24, _ZL4k256@rel32@lo+4
	s_addc_u32 s25, s25, _ZL4k256@rel32@hi+12
	s_or_b32 s0, s22, s10
	s_waitcnt vmcnt(1)
	v_alignbit_b32 v11, v5, v5, 6
	s_lshl_b64 s[26:27], s[0:1], 2
	v_alignbit_b32 v12, v5, v5, 11
	s_add_u32 s24, s26, s24
	s_addc_u32 s25, s27, s25
	s_sub_i32 s0, 6, s22
	s_sub_i32 s26, 5, s22
	s_and_b32 s0, s0, 7
	s_and_b32 s26, s26, 7
	s_lshl_b32 s0, s0, 2
	s_sub_i32 s27, 7, s22
	s_lshl_b32 s26, s26, 2
	s_add_i32 s0, s0, 48
	s_add_i32 s26, s26, 48
	s_and_b32 s27, s27, 7
	s_clause 0x1
	scratch_load_b32 v7, off, s0
	scratch_load_b32 v9, off, s26
	s_lshl_b32 s0, s27, 2
	s_load_b32 s24, s[24:25], 0x0
	s_add_i32 s0, s0, 48
	v_alignbit_b32 v13, v5, v5, 25
	scratch_load_b32 v10, off, s0
	s_sub_i32 s25, 1, s22
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s25, s25, 7
	v_xor3_b32 v11, v11, v12, v13
	s_lshl_b32 s25, s25, 2
	s_add_i32 s25, s25, 48
	s_waitcnt vmcnt(3) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v6, v6, v11, s24
	s_sub_i32 s24, 3, s22
	s_sub_i32 s22, 2, s22
	s_and_b32 s24, s24, 7
	s_and_b32 s22, s22, 7
	s_lshl_b32 s24, s24, 2
	s_lshl_b32 s22, s22, 2
	s_add_i32 s24, s24, 48
	s_add_i32 s22, s22, 48
	v_alignbit_b32 v11, v0, v0, 22
	s_cmp_lg_u32 s23, 16
	s_waitcnt vmcnt(1)
	v_bfi_b32 v5, v5, v9, v7
	v_alignbit_b32 v9, v0, v0, 2
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2)
	v_add3_u32 v5, v6, v10, v5
	v_alignbit_b32 v10, v0, v0, 13
	scratch_store_b32 off, v5, s0
	scratch_load_b32 v6, off, s24
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v5, v5, v6
	scratch_store_b32 off, v5, s24
	s_clause 0x2
	scratch_load_b32 v5, off, s25
	scratch_load_b32 v6, off, s22
	scratch_load_b32 v7, off, s0
	s_mov_b32 s22, s23
	s_waitcnt vmcnt(2)
	v_and_b32_e32 v12, v5, v0
	v_xor_b32_e32 v0, v5, v0
	v_xor3_b32 v5, v9, v10, v11
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_or_b32 v0, v6, v0, v12
	s_waitcnt vmcnt(0)
	v_add3_u32 v0, v7, v5, v0
	scratch_store_b32 off, v0, s0
	s_cbranch_scc1 .LBB0_16
; %bb.22:                               ; %_ZL6memcpyPvPKvm.exit.i281.i
                                        ;   in Loop: Header=BB0_15 Depth=2
	s_add_i32 s0, s10, 16
	s_cmp_lt_u32 s10, 48
	s_mov_b32 s10, s0
	s_cbranch_scc1 .LBB0_15
; %bb.23:                               ; %.preheader.i.i.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s0, 0
.LBB0_24:                               ; %.preheader.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e64 v0, 0x1a0, s0
	s_add_i32 s10, s0, 48
	s_add_i32 s0, s0, 4
	s_cmp_lg_u32 s0, 32
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v0, 8, v0
	scratch_load_b32 v5, off, s10
	scratch_load_b32 v6, v0, off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v5, v6, v5
	scratch_store_b32 v0, v5, off
	s_cbranch_scc1 .LBB0_24
; %bb.25:                               ; %sha256_compile.exit.i
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_movk_i32 s10, 0xffc0
	s_mov_b32 s11, -1
	s_mov_b32 s0, 0
	scratch_store_b32 off, v4, off offset:520
.LBB0_26:                               ; %.lr.ph.i.i.i52.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_readfirstlane_b32 s22, v25
	s_add_i32 s23, s0, 0x160
	scratch_load_u8 v0, off, s23
	s_add_i32 s22, s22, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s23, s22, 1
	s_add_i32 s24, s22, 2
	s_add_i32 s22, s22, 3
	s_clause 0x2
	scratch_load_u8 v5, off, s23
	scratch_load_u8 v6, off, s24
	scratch_load_u8 v7, off, s22
	v_readfirstlane_b32 s22, v20
	s_delay_alu instid0(VALU_DEP_1)
	s_add_i32 s22, s22, s0
	s_add_i32 s0, s0, 4
	s_add_i32 s23, s22, 40
	s_add_i32 s24, s22, 41
	s_add_i32 s25, s22, 42
	s_add_i32 s22, s22, 43
	s_add_u32 s10, s10, 4
	s_addc_u32 s11, s11, 0
	s_waitcnt vmcnt(3)
	scratch_store_b8 off, v0, s23
	s_waitcnt vmcnt(2)
	scratch_store_b8 off, v5, s24
	s_waitcnt vmcnt(1)
	scratch_store_b8 off, v6, s25
	s_waitcnt vmcnt(0)
	scratch_store_b8 off, v7, s22
	s_cmp_lg_u64 s[10:11], 0
	s_cbranch_scc1 .LBB0_26
; %bb.27:                               ; %_ZL6memcpyPvPKvm.exit.i36.i.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_movk_i32 s0, 0x64
.LBB0_28:                               ; %_ZL6memcpyPvPKvm.exit.i36.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s10, s0, 0x208
	s_add_i32 s0, s0, -4
	scratch_load_b32 v0, off, s10
	s_cmp_lg_u32 s0, 36
	s_waitcnt vmcnt(0)
	v_perm_b32 v0, 0, v0, 0x10203
	scratch_store_b32 off, v0, s10
	s_cbranch_scc1 .LBB0_28
; %bb.29:                               ;   in Loop: Header=BB0_2 Depth=1
	s_movk_i32 s10, 0xffe0
	s_mov_b32 s11, -1
	s_mov_b32 s0, 0
.LBB0_30:                               ; %.lr.ph.i.i.i282.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_readfirstlane_b32 s22, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s22, s22, s0
	s_add_i32 s23, s22, 8
	s_add_i32 s24, s22, 9
	s_add_i32 s25, s22, 10
	s_add_i32 s22, s22, 11
	s_clause 0x3
	scratch_load_u8 v0, off, s23
	scratch_load_u8 v5, off, s24
	scratch_load_u8 v6, off, s25
	scratch_load_u8 v7, off, s22
	v_readfirstlane_b32 s22, v21
	s_add_i32 s23, s0, 48
	s_delay_alu instid0(VALU_DEP_1)
	s_add_i32 s22, s22, s0
	s_add_i32 s0, s0, 4
	s_add_i32 s24, s22, 1
	s_add_i32 s25, s22, 2
	s_add_i32 s22, s22, 3
	s_add_u32 s10, s10, 4
	s_addc_u32 s11, s11, 0
	s_waitcnt vmcnt(3)
	scratch_store_b8 off, v0, s23
	s_waitcnt vmcnt(2)
	scratch_store_b8 off, v5, s24
	s_waitcnt vmcnt(1)
	scratch_store_b8 off, v6, s25
	s_waitcnt vmcnt(0)
	scratch_store_b8 off, v7, s22
	s_cmp_lg_u64 s[10:11], 0
	s_cbranch_scc1 .LBB0_30
; %bb.31:                               ; %.preheader14.i288.i.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s10, 0
.LBB0_32:                               ; %.preheader14.i288.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_33 Depth 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s10, 0
	s_mov_b32 s22, 0
	s_cselect_b32 s11, -1, 0
.LBB0_33:                               ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_32 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sub_i32 s0, 4, s22
	s_sub_i32 s23, 0, s22
	s_and_b32 s0, s0, 7
	s_and_b32 s23, s23, 7
	s_lshl_b32 s0, s0, 2
	s_lshl_b32 s23, s23, 2
	s_add_i32 s0, s0, 48
	s_add_i32 s23, s23, 48
	s_clause 0x1
	scratch_load_b32 v5, off, s0
	scratch_load_b32 v0, off, s23
	s_and_not1_b32 vcc_lo, exec_lo, s11
	s_cbranch_vccnz .LBB0_35
; %bb.34:                               ;   in Loop: Header=BB0_33 Depth=3
	s_add_i32 s0, s22, 14
	s_add_i32 s23, s22, 1
	s_and_b32 s0, s0, 15
	s_and_b32 s24, s23, 15
	s_lshl_b32 s0, s0, 2
	s_lshl_b32 s24, s24, 2
	s_add_i32 s0, s15, s0
	scratch_load_b32 v6, off, s0
	s_add_i32 s0, s15, s24
	s_add_i32 s24, s22, 9
	scratch_load_b32 v7, off, s0
	s_and_b32 s0, s24, 15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s0, s0, 2
	s_add_i32 s0, s15, s0
	scratch_load_b32 v9, off, s0
	s_lshl_b32 s0, s22, 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s24, s15, s0
	s_mov_b32 s0, 0
	scratch_load_b32 v10, off, s24
	s_waitcnt vmcnt(3)
	v_alignbit_b32 v11, v6, v6, 17
	v_alignbit_b32 v12, v6, v6, 19
	v_lshrrev_b32_e32 v6, 10, v6
	s_waitcnt vmcnt(2)
	v_alignbit_b32 v13, v7, v7, 7
	v_alignbit_b32 v14, v7, v7, 18
	v_lshrrev_b32_e32 v7, 3, v7
	v_xor_b32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor3_b32 v7, v13, v14, v7
	s_waitcnt vmcnt(1)
	v_xad_u32 v6, v11, v6, v9
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v6, v6, v10, v7
	scratch_store_b32 off, v6, s24
	s_branch .LBB0_36
.LBB0_35:                               ;   in Loop: Header=BB0_33 Depth=3
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr6
                                        ; implicit-def: $sgpr23
.LBB0_36:                               ; %Flow952
                                        ;   in Loop: Header=BB0_33 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_38
; %bb.37:                               ;   in Loop: Header=BB0_33 Depth=3
	s_lshl_b32 s0, s22, 2
	s_add_i32 s23, s22, 1
	s_add_i32 s0, s15, s0
	scratch_load_b32 v6, off, s0
.LBB0_38:                               ; %m_cycle.exit.i292.i
                                        ;   in Loop: Header=BB0_33 Depth=3
	s_getpc_b64 s[24:25]
	s_add_u32 s24, s24, _ZL4k256@rel32@lo+4
	s_addc_u32 s25, s25, _ZL4k256@rel32@hi+12
	s_or_b32 s0, s22, s10
	s_waitcnt vmcnt(1)
	v_alignbit_b32 v11, v5, v5, 6
	s_lshl_b64 s[26:27], s[0:1], 2
	v_alignbit_b32 v12, v5, v5, 11
	s_add_u32 s24, s26, s24
	s_addc_u32 s25, s27, s25
	s_sub_i32 s0, 6, s22
	s_sub_i32 s26, 5, s22
	s_and_b32 s0, s0, 7
	s_and_b32 s26, s26, 7
	s_lshl_b32 s0, s0, 2
	s_sub_i32 s27, 7, s22
	s_lshl_b32 s26, s26, 2
	s_add_i32 s0, s0, 48
	s_add_i32 s26, s26, 48
	s_and_b32 s27, s27, 7
	s_clause 0x1
	scratch_load_b32 v7, off, s0
	scratch_load_b32 v9, off, s26
	s_lshl_b32 s0, s27, 2
	s_load_b32 s24, s[24:25], 0x0
	s_add_i32 s0, s0, 48
	v_alignbit_b32 v13, v5, v5, 25
	scratch_load_b32 v10, off, s0
	s_sub_i32 s25, 1, s22
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s25, s25, 7
	v_xor3_b32 v11, v11, v12, v13
	s_lshl_b32 s25, s25, 2
	s_add_i32 s25, s25, 48
	s_waitcnt vmcnt(3) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v6, v6, v11, s24
	s_sub_i32 s24, 3, s22
	s_sub_i32 s22, 2, s22
	s_and_b32 s24, s24, 7
	s_and_b32 s22, s22, 7
	s_lshl_b32 s24, s24, 2
	s_lshl_b32 s22, s22, 2
	s_add_i32 s24, s24, 48
	s_add_i32 s22, s22, 48
	v_alignbit_b32 v11, v0, v0, 22
	s_cmp_lg_u32 s23, 16
	s_waitcnt vmcnt(1)
	v_bfi_b32 v5, v5, v9, v7
	v_alignbit_b32 v9, v0, v0, 2
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2)
	v_add3_u32 v5, v6, v10, v5
	v_alignbit_b32 v10, v0, v0, 13
	scratch_store_b32 off, v5, s0
	scratch_load_b32 v6, off, s24
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v5, v5, v6
	scratch_store_b32 off, v5, s24
	s_clause 0x2
	scratch_load_b32 v5, off, s25
	scratch_load_b32 v6, off, s22
	scratch_load_b32 v7, off, s0
	s_mov_b32 s22, s23
	s_waitcnt vmcnt(2)
	v_and_b32_e32 v12, v5, v0
	v_xor_b32_e32 v0, v5, v0
	v_xor3_b32 v5, v9, v10, v11
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_or_b32 v0, v6, v0, v12
	s_waitcnt vmcnt(0)
	v_add3_u32 v0, v7, v5, v0
	scratch_store_b32 off, v0, s0
	s_cbranch_scc1 .LBB0_33
; %bb.39:                               ; %_ZL6memcpyPvPKvm.exit.i295.i
                                        ;   in Loop: Header=BB0_32 Depth=2
	s_add_i32 s0, s10, 16
	s_cmp_lt_u32 s10, 48
	s_mov_b32 s10, s0
	s_cbranch_scc1 .LBB0_32
; %bb.40:                               ; %.preheader.i296.i.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s0, 0
.LBB0_41:                               ; %.preheader.i296.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e64 v0, 0x208, s0
	s_add_i32 s10, s0, 48
	s_add_i32 s0, s0, 4
	s_cmp_lg_u32 s0, 32
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v0, 8, v0
	scratch_load_b32 v5, off, s10
	scratch_load_b32 v6, v0, off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v5, v6, v5
	scratch_store_b32 v0, v5, off
	s_cbranch_scc1 .LBB0_41
; %bb.42:                               ; %sha256_compile.exit300.i
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_clause 0x8
	scratch_load_b128 v[9:12], off, off offset:416
	scratch_load_b128 v[13:16], off, off offset:432
	scratch_load_b64 v[5:6], off, off offset:512
	scratch_load_b128 v[28:31], off, off offset:496
	scratch_load_b128 v[32:35], off, off offset:480
	scratch_load_b128 v[36:39], off, off offset:464
	scratch_load_b64 v[64:65], off, off offset:616
	scratch_load_b128 v[40:43], off, off offset:600
	scratch_load_b128 v[44:47], off, off offset:584
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(8)
	scratch_store_b128 off, v[9:12], off offset:48
	s_clause 0x5
	scratch_load_b128 v[9:12], off, off offset:568
	scratch_load_b128 v[48:51], off, off offset:552
	scratch_load_b32 v0, off, off offset:48
	scratch_load_b128 v[52:55], off, off offset:536
	scratch_load_b128 v[56:59], off, off offset:520
	scratch_load_b128 v[60:63], off, off offset:448
	s_waitcnt vmcnt(13)
	scratch_store_b128 off, v[13:16], off offset:64
	s_waitcnt vmcnt(12)
	scratch_store_b64 off, v[5:6], off offset:144
	s_waitcnt vmcnt(11)
	scratch_store_b128 off, v[28:31], off offset:128
	s_waitcnt vmcnt(10)
	scratch_store_b128 off, v[32:35], off offset:112
	s_waitcnt vmcnt(9)
	scratch_store_b128 off, v[36:39], off offset:96
	s_waitcnt vmcnt(8)
	scratch_store_b64 off, v[64:65], off offset:248
	s_waitcnt vmcnt(7)
	scratch_store_b128 off, v[40:43], off offset:232
	s_waitcnt vmcnt(6)
	scratch_store_b128 off, v[44:47], off offset:216
	s_waitcnt vmcnt(5)
	scratch_store_b128 off, v[9:12], off offset:200
	s_waitcnt vmcnt(4)
	scratch_store_b128 off, v[48:51], off offset:184
	s_waitcnt vmcnt(3)
	v_add_nc_u32_e32 v5, 20, v0
	s_waitcnt vmcnt(2)
	scratch_store_b128 off, v[52:55], off offset:168
	s_waitcnt vmcnt(1)
	scratch_store_b128 off, v[56:59], off offset:152
	s_waitcnt vmcnt(0)
	s_clause 0x1
	scratch_store_b128 off, v[60:63], off offset:80
	scratch_store_b32 off, v5, off offset:48
	v_cmpx_lt_u32_e32 0xffffffeb, v0
	s_cbranch_execz .LBB0_44
; %bb.43:                               ;   in Loop: Header=BB0_2 Depth=1
	scratch_load_b32 v5, off, off offset:52
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v5, 1, v5
	scratch_store_b32 off, v5, off offset:52
.LBB0_44:                               ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, cuda_init_derive@rel32@lo+4
	s_addc_u32 s11, s11, cuda_init_derive@rel32@hi+12
	v_mov_b32_e32 v9, 20
	v_dual_mov_b32 v5, s10 :: v_dual_mov_b32 v6, s11
	v_dual_mov_b32 v10, 0 :: v_dual_and_b32 v7, 63, v0
	s_mov_b32 s22, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_u32_e32 43, v7
	s_cbranch_execz .LBB0_75
; %bb.45:                               ; %.lr.ph.i.i57.i
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_sub_nc_u32_e32 v0, 64, v7
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, cuda_init_derive@rel32@lo+4
	s_addc_u32 s11, s11, cuda_init_derive@rel32@hi+12
	v_mov_b32_e32 v9, 20
	v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v5, s10
	v_mov_b32_e32 v6, s11
	v_dual_mov_b32 v12, v1 :: v_dual_mov_b32 v11, v0
	s_mov_b32 s23, 0
.LBB0_46:                               ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_48 Depth 3
                                        ;       Child Loop BB0_59 Depth 3
                                        ;       Child Loop BB0_61 Depth 3
                                        ;       Child Loop BB0_63 Depth 3
                                        ;         Child Loop BB0_64 Depth 4
                                        ;       Child Loop BB0_72 Depth 3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v14, v6
	v_dual_mov_b32 v16, v12 :: v_dual_mov_b32 v15, v11
	v_dual_mov_b32 v13, v5 :: v_dual_add_nc_u32 v0, s16, v7
	s_mov_b32 s0, exec_lo
	v_cmpx_lt_u64_e32 3, v[11:12]
	s_cbranch_execz .LBB0_50
; %bb.47:                               ; %.lr.ph.i.i.i.i.i.preheader
                                        ;   in Loop: Header=BB0_46 Depth=2
	v_dual_mov_b32 v14, v6 :: v_dual_mov_b32 v13, v5
	v_dual_mov_b32 v16, v12 :: v_dual_mov_b32 v15, v11
	s_mov_b32 s10, 0
.LBB0_48:                               ; %.lr.ph.i.i.i.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_46 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	global_load_b32 v7, v[13:14], off
	v_add_co_u32 v15, vcc_lo, v15, -4
	v_add_co_ci_u32_e32 v16, vcc_lo, -1, v16, vcc_lo
	v_add_co_u32 v13, vcc_lo, v13, 4
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_gt_u64_e32 vcc_lo, 4, v[15:16]
	s_or_b32 s10, vcc_lo, s10
	s_waitcnt vmcnt(0)
	v_lshrrev_b32_e32 v28, 8, v7
	v_lshrrev_b32_e32 v29, 24, v7
	s_clause 0x3
	scratch_store_b8 v0, v7, off
	scratch_store_b8 v0, v28, off offset:1
	scratch_store_d16_hi_b8 v0, v7, off offset:2
	scratch_store_b8 v0, v29, off offset:3
	v_add_nc_u32_e32 v0, 4, v0
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_48
; %bb.49:                               ; %Flow948
                                        ;   in Loop: Header=BB0_46 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_50:                               ; %Flow949
                                        ;   in Loop: Header=BB0_46 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s0, 0
	s_mov_b32 s10, exec_lo
	v_cmpx_lt_i64_e32 1, v[15:16]
	s_xor_b32 s10, exec_lo, s10
	s_cbranch_execz .LBB0_54
; %bb.51:                               ; %NodeBlock
                                        ;   in Loop: Header=BB0_46 Depth=2
	s_mov_b32 s0, exec_lo
	v_cmpx_lt_i64_e32 2, v[15:16]
	s_cbranch_execz .LBB0_53
; %bb.52:                               ;   in Loop: Header=BB0_46 Depth=2
	global_load_u8 v7, v[13:14], off offset:2
	s_waitcnt vmcnt(0)
	scratch_store_b8 v0, v7, off offset:2
.LBB0_53:                               ;   in Loop: Header=BB0_46 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	global_load_u8 v7, v[13:14], off offset:1
	s_mov_b32 s0, exec_lo
                                        ; implicit-def: $vgpr15_vgpr16
	s_waitcnt vmcnt(0)
	scratch_store_b8 v0, v7, off offset:1
.LBB0_54:                               ; %Flow946
                                        ;   in Loop: Header=BB0_46 Depth=2
	s_and_not1_saveexec_b32 s10, s10
; %bb.55:                               ; %LeafBlock
                                        ;   in Loop: Header=BB0_46 Depth=2
	v_cmp_eq_u64_e32 vcc_lo, 1, v[15:16]
	s_and_not1_b32 s0, s0, exec_lo
	s_and_b32 s11, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s0, s0, s11
; %bb.56:                               ; %Flow947
                                        ;   in Loop: Header=BB0_46 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
	s_and_saveexec_b32 s10, s0
	s_cbranch_execz .LBB0_58
; %bb.57:                               ;   in Loop: Header=BB0_46 Depth=2
	global_load_u8 v7, v[13:14], off
	s_waitcnt vmcnt(0)
	scratch_store_b8 v0, v7, off
.LBB0_58:                               ; %_ZL6memcpyPvPKvm.exit.i.i.i.preheader
                                        ;   in Loop: Header=BB0_46 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
	s_movk_i32 s0, 0x64
.LBB0_59:                               ; %_ZL6memcpyPvPKvm.exit.i.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_46 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s10, s0, 48
	s_add_i32 s0, s0, -4
	scratch_load_b32 v0, off, s10
	s_cmp_lg_u32 s0, 36
	s_waitcnt vmcnt(0)
	v_perm_b32 v0, 0, v0, 0x10203
	scratch_store_b32 off, v0, s10
	s_cbranch_scc1 .LBB0_59
; %bb.60:                               ;   in Loop: Header=BB0_46 Depth=2
	s_movk_i32 s10, 0xffe0
	s_mov_b32 s11, -1
	s_mov_b32 s0, 0
.LBB0_61:                               ; %.lr.ph.i.i.i52.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_46 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s24, s17, s0
	s_add_i32 s25, s24, 1
	s_add_i32 s26, s24, 2
	s_add_i32 s27, s24, 3
	s_clause 0x3
	scratch_load_u8 v0, off, s24
	scratch_load_u8 v7, off, s25
	scratch_load_u8 v13, off, s26
	scratch_load_u8 v14, off, s27
	v_readfirstlane_b32 s24, v26
	s_add_i32 s25, s0, 16
	s_delay_alu instid0(VALU_DEP_1)
	s_add_i32 s24, s24, s0
	s_add_i32 s0, s0, 4
	s_add_i32 s26, s24, 1
	s_add_i32 s27, s24, 2
	s_add_i32 s24, s24, 3
	s_add_u32 s10, s10, 4
	s_addc_u32 s11, s11, 0
	s_waitcnt vmcnt(3)
	scratch_store_b8 off, v0, s25
	s_waitcnt vmcnt(2)
	scratch_store_b8 off, v7, s26
	s_waitcnt vmcnt(1)
	scratch_store_b8 off, v13, s27
	s_waitcnt vmcnt(0)
	scratch_store_b8 off, v14, s24
	s_cmp_lg_u64 s[10:11], 0
	s_cbranch_scc1 .LBB0_61
; %bb.62:                               ; %.preheader14.i.i.i.preheader
                                        ;   in Loop: Header=BB0_46 Depth=2
	s_mov_b32 s10, 0
.LBB0_63:                               ; %.preheader14.i.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_46 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_64 Depth 4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s10, 0
	s_mov_b32 s24, 0
	s_cselect_b32 s11, -1, 0
.LBB0_64:                               ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_46 Depth=2
                                        ;       Parent Loop BB0_63 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_sub_i32 s0, 4, s24
	s_sub_i32 s25, 0, s24
	s_and_b32 s0, s0, 7
	s_and_b32 s25, s25, 7
	s_lshl_b32 s0, s0, 2
	s_lshl_b32 s25, s25, 2
	s_add_i32 s0, s0, 16
	s_add_i32 s25, s25, 16
	s_clause 0x1
	scratch_load_b32 v7, off, s0
	scratch_load_b32 v0, off, s25
	s_and_not1_b32 vcc_lo, exec_lo, s11
	s_cbranch_vccnz .LBB0_66
; %bb.65:                               ;   in Loop: Header=BB0_64 Depth=4
	s_add_i32 s0, s24, 14
	s_add_i32 s25, s24, 1
	s_and_b32 s0, s0, 15
	s_and_b32 s26, s25, 15
	s_lshl_b32 s0, s0, 2
	s_lshl_b32 s26, s26, 2
	s_add_i32 s0, s16, s0
	scratch_load_b32 v13, off, s0
	s_add_i32 s0, s16, s26
	s_add_i32 s26, s24, 9
	scratch_load_b32 v14, off, s0
	s_and_b32 s0, s26, 15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s0, s0, 2
	s_add_i32 s0, s16, s0
	scratch_load_b32 v15, off, s0
	s_lshl_b32 s0, s24, 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s26, s16, s0
	s_mov_b32 s0, 0
	scratch_load_b32 v16, off, s26
	s_waitcnt vmcnt(3)
	v_alignbit_b32 v28, v13, v13, 17
	v_alignbit_b32 v29, v13, v13, 19
	v_lshrrev_b32_e32 v13, 10, v13
	s_waitcnt vmcnt(2)
	v_alignbit_b32 v30, v14, v14, 7
	v_alignbit_b32 v31, v14, v14, 18
	v_lshrrev_b32_e32 v14, 3, v14
	v_xor_b32_e32 v28, v28, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor3_b32 v14, v30, v31, v14
	s_waitcnt vmcnt(1)
	v_xad_u32 v13, v28, v13, v15
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v13, v13, v16, v14
	scratch_store_b32 off, v13, s26
	s_branch .LBB0_67
.LBB0_66:                               ;   in Loop: Header=BB0_64 Depth=4
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr13
                                        ; implicit-def: $sgpr25
.LBB0_67:                               ; %Flow945
                                        ;   in Loop: Header=BB0_64 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_69
; %bb.68:                               ;   in Loop: Header=BB0_64 Depth=4
	s_lshl_b32 s0, s24, 2
	s_add_i32 s25, s24, 1
	s_add_i32 s0, s16, s0
	scratch_load_b32 v13, off, s0
.LBB0_69:                               ; %m_cycle.exit.i.i.i
                                        ;   in Loop: Header=BB0_64 Depth=4
	s_getpc_b64 s[26:27]
	s_add_u32 s26, s26, _ZL4k256@rel32@lo+4
	s_addc_u32 s27, s27, _ZL4k256@rel32@hi+12
	s_or_b32 s0, s24, s10
	s_waitcnt vmcnt(1)
	v_alignbit_b32 v28, v7, v7, 6
	s_lshl_b64 s[28:29], s[0:1], 2
	v_alignbit_b32 v29, v7, v7, 11
	s_add_u32 s26, s28, s26
	s_addc_u32 s27, s29, s27
	s_sub_i32 s0, 6, s24
	s_sub_i32 s28, 5, s24
	s_and_b32 s0, s0, 7
	s_and_b32 s28, s28, 7
	s_lshl_b32 s0, s0, 2
	s_sub_i32 s29, 7, s24
	s_lshl_b32 s28, s28, 2
	s_add_i32 s0, s0, 16
	s_add_i32 s28, s28, 16
	s_and_b32 s29, s29, 7
	s_clause 0x1
	scratch_load_b32 v14, off, s0
	scratch_load_b32 v15, off, s28
	s_lshl_b32 s0, s29, 2
	s_load_b32 s26, s[26:27], 0x0
	s_add_i32 s0, s0, 16
	v_alignbit_b32 v30, v7, v7, 25
	scratch_load_b32 v16, off, s0
	s_sub_i32 s27, 1, s24
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s27, s27, 7
	v_xor3_b32 v28, v28, v29, v30
	s_lshl_b32 s27, s27, 2
	s_add_i32 s27, s27, 16
	s_waitcnt vmcnt(3) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v13, v13, v28, s26
	s_sub_i32 s26, 3, s24
	s_sub_i32 s24, 2, s24
	s_and_b32 s26, s26, 7
	s_and_b32 s24, s24, 7
	s_lshl_b32 s26, s26, 2
	s_lshl_b32 s24, s24, 2
	s_add_i32 s26, s26, 16
	s_add_i32 s24, s24, 16
	v_alignbit_b32 v28, v0, v0, 22
	s_cmp_lg_u32 s25, 16
	s_waitcnt vmcnt(1)
	v_bfi_b32 v7, v7, v15, v14
	v_alignbit_b32 v15, v0, v0, 2
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2)
	v_add3_u32 v7, v13, v16, v7
	v_alignbit_b32 v16, v0, v0, 13
	scratch_store_b32 off, v7, s0
	scratch_load_b32 v13, off, s26
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v7, v7, v13
	scratch_store_b32 off, v7, s26
	s_clause 0x2
	scratch_load_b32 v7, off, s27
	scratch_load_b32 v13, off, s24
	scratch_load_b32 v14, off, s0
	s_mov_b32 s24, s25
	s_waitcnt vmcnt(2)
	v_and_b32_e32 v29, v7, v0
	v_xor_b32_e32 v0, v7, v0
	v_xor3_b32 v7, v15, v16, v28
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_or_b32 v0, v13, v0, v29
	s_waitcnt vmcnt(0)
	v_add3_u32 v0, v14, v7, v0
	scratch_store_b32 off, v0, s0
	s_cbranch_scc1 .LBB0_64
; %bb.70:                               ; %_ZL6memcpyPvPKvm.exit.i58.i.i
                                        ;   in Loop: Header=BB0_63 Depth=3
	s_add_i32 s0, s10, 16
	s_cmp_lt_u32 s10, 48
	s_mov_b32 s10, s0
	s_cbranch_scc1 .LBB0_63
; %bb.71:                               ; %.preheader.i.i.i.preheader
                                        ;   in Loop: Header=BB0_46 Depth=2
	s_mov_b32 s0, 0
.LBB0_72:                               ; %.preheader.i.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_46 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	s_add_i32 s10, s0, 16
	s_add_i32 s11, s17, s0
	scratch_load_b32 v0, off, s10
	scratch_load_b32 v7, off, s11
	s_add_i32 s0, s0, 4
	s_cmp_lg_u32 s0, 32
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v0, v7, v0
	scratch_store_b32 off, v0, s11
	s_cbranch_scc1 .LBB0_72
; %bb.73:                               ; %sha256_compile.exit.i.i
                                        ;   in Loop: Header=BB0_46 Depth=2
	v_sub_co_u32 v9, vcc_lo, v9, v11
	v_sub_co_ci_u32_e32 v10, vcc_lo, v10, v12, vcc_lo
	v_add_co_u32 v5, s0, v5, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v6, s0, v6, v12, s0
	v_cmp_gt_u64_e32 vcc_lo, 64, v[9:10]
	v_mov_b32_e32 v11, 64
	v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v7, 0
	s_or_b32 s23, vcc_lo, s23
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s23
	s_cbranch_execnz .LBB0_46
; %bb.74:                               ; %Flow950
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s23
	v_mov_b32_e32 v7, 0
.LBB0_75:                               ; %Flow951
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v0, s16, v7
	s_mov_b32 s0, exec_lo
	v_cmpx_lt_u64_e32 3, v[9:10]
	s_cbranch_execz .LBB0_79
; %bb.76:                               ; %.lr.ph.i.i38.i.i.i.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s10, 0
.LBB0_77:                               ; %.lr.ph.i.i38.i.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v7, v[5:6], off
	v_add_co_u32 v9, vcc_lo, v9, -4
	v_add_co_ci_u32_e32 v10, vcc_lo, -1, v10, vcc_lo
	v_add_co_u32 v5, vcc_lo, v5, 4
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_gt_u64_e32 vcc_lo, 4, v[9:10]
	s_or_b32 s10, vcc_lo, s10
	s_waitcnt vmcnt(0)
	v_lshrrev_b32_e32 v11, 8, v7
	v_lshrrev_b32_e32 v12, 24, v7
	s_clause 0x3
	scratch_store_b8 v0, v7, off
	scratch_store_b8 v0, v11, off offset:1
	scratch_store_d16_hi_b8 v0, v7, off offset:2
	scratch_store_b8 v0, v12, off offset:3
	v_add_nc_u32_e32 v0, 4, v0
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_77
; %bb.78:                               ; %Flow943
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_79:                               ; %Flow944
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s0, 0
	s_mov_b32 s10, exec_lo
	v_cmpx_lt_i64_e32 1, v[9:10]
	s_xor_b32 s10, exec_lo, s10
	s_cbranch_execz .LBB0_83
; %bb.80:                               ; %NodeBlock811
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s0, exec_lo
	v_cmpx_lt_i64_e32 2, v[9:10]
	s_cbranch_execz .LBB0_82
; %bb.81:                               ;   in Loop: Header=BB0_2 Depth=1
	global_load_u8 v7, v[5:6], off offset:2
	s_waitcnt vmcnt(0)
	scratch_store_b8 v0, v7, off offset:2
.LBB0_82:                               ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	global_load_u8 v7, v[5:6], off offset:1
	s_mov_b32 s0, exec_lo
                                        ; implicit-def: $vgpr9_vgpr10
	s_waitcnt vmcnt(0)
	scratch_store_b8 v0, v7, off offset:1
.LBB0_83:                               ; %Flow941
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s10, s10
; %bb.84:                               ; %LeafBlock809
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_cmp_eq_u64_e32 vcc_lo, 1, v[9:10]
	s_and_not1_b32 s0, s0, exec_lo
	s_and_b32 s11, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s0, s0, s11
; %bb.85:                               ; %Flow942
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_and_saveexec_b32 s10, s0
	s_cbranch_execz .LBB0_87
; %bb.86:                               ;   in Loop: Header=BB0_2 Depth=1
	global_load_u8 v5, v[5:6], off
	s_waitcnt vmcnt(0)
	scratch_store_b8 v0, v5, off
.LBB0_87:                               ; %sha256_hash.exit.i.i
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	scratch_load_b32 v5, off, off offset:48
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v0, 63, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ne_u32_e32 0, v0
	s_cbranch_execz .LBB0_90
; %bb.88:                               ; %.lr.ph.i.i.i59.i
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v6, 3, v0
	s_mov_b32 s10, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_and_b32_e32 v6, 0x7c, v6
.LBB0_89:                               ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v7, v22, v6
	v_add_nc_u32_e32 v6, -4, v6
	scratch_load_b32 v9, v7, off
	v_cmp_eq_u32_e32 vcc_lo, 0, v6
	s_or_b32 s10, vcc_lo, s10
	s_waitcnt vmcnt(0)
	v_perm_b32 v9, 0, v9, 0x10203
	scratch_store_b32 v7, v9, off
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_89
.LBB0_90:                               ; %Flow940
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_and_b32_e32 v6, 60, v0
	v_not_b32_e32 v5, v5
	s_mov_b32 s0, exec_lo
	scratch_load_b32 v7, v6, off offset:88
	v_lshlrev_b32_e32 v5, 3, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e64 v9, v5, 0xffffff80
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v7, v7, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_or_b32 v5, 0x80, v5, v7
	scratch_store_b32 v6, v5, off offset:88
                                        ; implicit-def: $vgpr5_vgpr6
	v_cmpx_gt_u32_e32 56, v0
	s_xor_b32 s0, exec_lo, s0
; %bb.91:                               ;   in Loop: Header=BB0_2 Depth=1
	v_lshrrev_b32_e32 v0, 2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, 1, v0
	v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v5, v0
                                        ; implicit-def: $vgpr0
; %bb.92:                               ; %Flow937
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s22, s0
	s_cbranch_execz .LBB0_109
; %bb.93:                               ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 60, v0
	s_cbranch_execz .LBB0_95
; %bb.94:                               ;   in Loop: Header=BB0_2 Depth=1
	scratch_store_b32 off, v1, off offset:148
.LBB0_95:                               ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_movk_i32 s10, 0xffe0
	s_mov_b32 s11, -1
	s_mov_b32 s0, 0
.LBB0_96:                               ; %.lr.ph.i.i.i78.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s23, s17, s0
	s_add_i32 s24, s23, 1
	s_add_i32 s25, s23, 2
	s_add_i32 s26, s23, 3
	s_clause 0x3
	scratch_load_u8 v0, off, s23
	scratch_load_u8 v5, off, s24
	scratch_load_u8 v6, off, s25
	scratch_load_u8 v7, off, s26
	v_readfirstlane_b32 s23, v26
	s_add_i32 s24, s0, 16
	s_delay_alu instid0(VALU_DEP_1)
	s_add_i32 s23, s23, s0
	s_add_i32 s0, s0, 4
	s_add_i32 s25, s23, 1
	s_add_i32 s26, s23, 2
	s_add_i32 s23, s23, 3
	s_add_u32 s10, s10, 4
	s_addc_u32 s11, s11, 0
	s_waitcnt vmcnt(3)
	scratch_store_b8 off, v0, s24
	s_waitcnt vmcnt(2)
	scratch_store_b8 off, v5, s25
	s_waitcnt vmcnt(1)
	scratch_store_b8 off, v6, s26
	s_waitcnt vmcnt(0)
	scratch_store_b8 off, v7, s23
	s_cmp_lg_u64 s[10:11], 0
	s_cbranch_scc1 .LBB0_96
; %bb.97:                               ; %.preheader14.i84.i.i.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s10, 0
.LBB0_98:                               ; %.preheader14.i84.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_99 Depth 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s10, 0
	s_mov_b32 s23, 0
	s_cselect_b32 s11, -1, 0
.LBB0_99:                               ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_98 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sub_i32 s0, 4, s23
	s_sub_i32 s24, 0, s23
	s_and_b32 s0, s0, 7
	s_and_b32 s24, s24, 7
	s_lshl_b32 s0, s0, 2
	s_lshl_b32 s24, s24, 2
	s_add_i32 s0, s0, 16
	s_add_i32 s24, s24, 16
	s_clause 0x1
	scratch_load_b32 v5, off, s0
	scratch_load_b32 v0, off, s24
	s_and_not1_b32 vcc_lo, exec_lo, s11
	s_cbranch_vccnz .LBB0_101
; %bb.100:                              ;   in Loop: Header=BB0_99 Depth=3
	s_add_i32 s0, s23, 14
	s_add_i32 s24, s23, 1
	s_and_b32 s0, s0, 15
	s_and_b32 s25, s24, 15
	s_lshl_b32 s0, s0, 2
	s_lshl_b32 s25, s25, 2
	s_add_i32 s0, s16, s0
	scratch_load_b32 v6, off, s0
	s_add_i32 s0, s16, s25
	s_add_i32 s25, s23, 9
	scratch_load_b32 v7, off, s0
	s_and_b32 s0, s25, 15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s0, s0, 2
	s_add_i32 s0, s16, s0
	scratch_load_b32 v9, off, s0
	s_lshl_b32 s0, s23, 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s25, s16, s0
	s_mov_b32 s0, 0
	scratch_load_b32 v10, off, s25
	s_waitcnt vmcnt(3)
	v_alignbit_b32 v11, v6, v6, 17
	v_alignbit_b32 v12, v6, v6, 19
	v_lshrrev_b32_e32 v6, 10, v6
	s_waitcnt vmcnt(2)
	v_alignbit_b32 v13, v7, v7, 7
	v_alignbit_b32 v14, v7, v7, 18
	v_lshrrev_b32_e32 v7, 3, v7
	v_xor_b32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor3_b32 v7, v13, v14, v7
	s_waitcnt vmcnt(1)
	v_xad_u32 v6, v11, v6, v9
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v6, v6, v10, v7
	scratch_store_b32 off, v6, s25
	s_branch .LBB0_102
.LBB0_101:                              ;   in Loop: Header=BB0_99 Depth=3
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr6
                                        ; implicit-def: $sgpr24
.LBB0_102:                              ; %Flow936
                                        ;   in Loop: Header=BB0_99 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_104
; %bb.103:                              ;   in Loop: Header=BB0_99 Depth=3
	s_lshl_b32 s0, s23, 2
	s_add_i32 s24, s23, 1
	s_add_i32 s0, s16, s0
	scratch_load_b32 v6, off, s0
.LBB0_104:                              ; %m_cycle.exit.i88.i.i
                                        ;   in Loop: Header=BB0_99 Depth=3
	s_getpc_b64 s[26:27]
	s_add_u32 s26, s26, _ZL4k256@rel32@lo+4
	s_addc_u32 s27, s27, _ZL4k256@rel32@hi+12
	s_or_b32 s0, s23, s10
	s_waitcnt vmcnt(1)
	v_alignbit_b32 v11, v5, v5, 6
	s_lshl_b64 s[28:29], s[0:1], 2
	v_alignbit_b32 v12, v5, v5, 11
	s_add_u32 s26, s28, s26
	s_addc_u32 s27, s29, s27
	s_sub_i32 s0, 6, s23
	s_sub_i32 s25, 5, s23
	s_and_b32 s0, s0, 7
	s_and_b32 s25, s25, 7
	s_lshl_b32 s0, s0, 2
	s_sub_i32 s28, 7, s23
	s_lshl_b32 s25, s25, 2
	s_add_i32 s0, s0, 16
	s_add_i32 s25, s25, 16
	s_and_b32 s28, s28, 7
	s_clause 0x1
	scratch_load_b32 v7, off, s0
	scratch_load_b32 v9, off, s25
	s_lshl_b32 s0, s28, 2
	s_load_b32 s25, s[26:27], 0x0
	s_add_i32 s0, s0, 16
	v_alignbit_b32 v13, v5, v5, 25
	scratch_load_b32 v10, off, s0
	s_sub_i32 s26, 1, s23
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s26, s26, 7
	v_xor3_b32 v11, v11, v12, v13
	s_lshl_b32 s26, s26, 2
	s_add_i32 s26, s26, 16
	s_waitcnt vmcnt(3) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v6, v6, v11, s25
	s_sub_i32 s25, 3, s23
	s_sub_i32 s23, 2, s23
	s_and_b32 s25, s25, 7
	s_and_b32 s23, s23, 7
	s_lshl_b32 s25, s25, 2
	s_lshl_b32 s23, s23, 2
	s_add_i32 s25, s25, 16
	s_add_i32 s23, s23, 16
	v_alignbit_b32 v11, v0, v0, 22
	s_cmp_lg_u32 s24, 16
	s_waitcnt vmcnt(1)
	v_bfi_b32 v5, v5, v9, v7
	v_alignbit_b32 v9, v0, v0, 2
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2)
	v_add3_u32 v5, v6, v10, v5
	v_alignbit_b32 v10, v0, v0, 13
	scratch_store_b32 off, v5, s0
	scratch_load_b32 v6, off, s25
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v5, v5, v6
	scratch_store_b32 off, v5, s25
	s_clause 0x2
	scratch_load_b32 v5, off, s26
	scratch_load_b32 v6, off, s23
	scratch_load_b32 v7, off, s0
	s_mov_b32 s23, s24
	s_waitcnt vmcnt(2)
	v_and_b32_e32 v12, v5, v0
	v_xor_b32_e32 v0, v5, v0
	v_xor3_b32 v5, v9, v10, v11
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_or_b32 v0, v6, v0, v12
	s_waitcnt vmcnt(0)
	v_add3_u32 v0, v7, v5, v0
	scratch_store_b32 off, v0, s0
	s_cbranch_scc1 .LBB0_99
; %bb.105:                              ; %_ZL6memcpyPvPKvm.exit.i91.i.i
                                        ;   in Loop: Header=BB0_98 Depth=2
	s_add_i32 s0, s10, 16
	s_cmp_lt_u32 s10, 48
	s_mov_b32 s10, s0
	s_cbranch_scc1 .LBB0_98
; %bb.106:                              ; %.preheader.i92.i.i.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s0, 0
.LBB0_107:                              ; %.preheader.i92.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	s_add_i32 s10, s0, 16
	s_add_i32 s11, s17, s0
	scratch_load_b32 v0, off, s10
	scratch_load_b32 v5, off, s11
	s_add_i32 s0, s0, 4
	s_cmp_lg_u32 s0, 32
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v0, v5, v0
	scratch_store_b32 off, v0, s11
	s_cbranch_scc1 .LBB0_107
; %bb.108:                              ; %sha256_compile.exit96.i.i
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v5, 0
	v_mov_b32_e32 v6, 0
.LBB0_109:                              ; %Flow938
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v0, 2, v5
	v_sub_co_u32 v5, vcc_lo, 0x42, v5
	v_sub_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	s_mov_b32 s10, 0
.LBB0_110:                              ; %.lr.ph.i.i.i.i.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v5, -8
	v_add_co_ci_u32_e32 v10, vcc_lo, -1, v6, vcc_lo
	v_add_nc_u32_e32 v7, 48, v0
	v_add_co_u32 v5, s0, v5, -4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cmp_gt_u64_e32 vcc_lo, 4, v[9:10]
	v_add_nc_u32_e32 v0, 4, v0
	v_add_nc_u32_e32 v11, 40, v7
	v_add_nc_u32_e32 v13, 42, v7
	v_add_co_ci_u32_e64 v6, s0, -1, v6, s0
	v_add_nc_u32_e32 v12, 41, v7
	v_add_nc_u32_e32 v7, 43, v7
	s_or_b32 s10, vcc_lo, s10
	s_clause 0x3
	scratch_store_b8 v11, v1, off
	scratch_store_b8 v12, v1, off
	scratch_store_b8 v13, v1, off
	scratch_store_b8 v7, v1, off
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_110
; %bb.111:                              ; %._crit_edge.i.i.i.i.i.i
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v0, 48, v0
	s_mov_b32 s0, 0
	s_mov_b32 s10, exec_lo
	v_cmpx_lt_i64_e32 5, v[5:6]
	s_xor_b32 s10, exec_lo, s10
	s_cbranch_execz .LBB0_115
; %bb.112:                              ; %NodeBlock817
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s0, exec_lo
	v_cmpx_lt_i64_e32 6, v[5:6]
	s_cbranch_execz .LBB0_114
; %bb.113:                              ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v7, 42, v0
	scratch_store_b8 v7, v1, off
.LBB0_114:                              ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v7, 41, v0
	s_mov_b32 s0, exec_lo
	scratch_store_b8 v7, v1, off
.LBB0_115:                              ; %Flow934
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s10, s10
; %bb.116:                              ; %LeafBlock815
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_cmp_eq_u64_e32 vcc_lo, 5, v[5:6]
	s_and_not1_b32 s0, s0, exec_lo
	s_and_b32 s11, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s0, s0, s11
; %bb.117:                              ; %Flow935
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_and_saveexec_b32 s10, s0
	s_cbranch_execz .LBB0_119
; %bb.118:                              ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v0, 40, v0
	scratch_store_b8 v0, v1, off
.LBB0_119:                              ; %_ZL6memsetPvim.exit.i.i.i.i
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	scratch_load_b64 v[5:6], off, off offset:48
	s_movk_i32 s10, 0xffe0
	s_mov_b32 s11, -1
	s_mov_b32 s0, 0
	s_waitcnt vmcnt(0)
	v_alignbit_b32 v6, v6, v5, 29
	v_lshlrev_b32_e32 v7, 3, v5
	scratch_store_b64 off, v[6:7], off offset:144
.LBB0_120:                              ; %.lr.ph.i.i.i59.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_readfirstlane_b32 s22, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s22, s22, s0
	s_add_i32 s23, s22, 8
	s_add_i32 s24, s22, 9
	s_add_i32 s25, s22, 10
	s_add_i32 s22, s22, 11
	s_clause 0x3
	scratch_load_u8 v0, off, s23
	scratch_load_u8 v5, off, s24
	scratch_load_u8 v6, off, s25
	scratch_load_u8 v7, off, s22
	v_readfirstlane_b32 s22, v26
	s_add_i32 s23, s0, 16
	s_delay_alu instid0(VALU_DEP_1)
	s_add_i32 s22, s22, s0
	s_add_i32 s0, s0, 4
	s_add_i32 s24, s22, 1
	s_add_i32 s25, s22, 2
	s_add_i32 s22, s22, 3
	s_add_u32 s10, s10, 4
	s_addc_u32 s11, s11, 0
	s_waitcnt vmcnt(3)
	scratch_store_b8 off, v0, s23
	s_waitcnt vmcnt(2)
	scratch_store_b8 off, v5, s24
	s_waitcnt vmcnt(1)
	scratch_store_b8 off, v6, s25
	s_waitcnt vmcnt(0)
	scratch_store_b8 off, v7, s22
	s_cmp_lg_u64 s[10:11], 0
	s_cbranch_scc1 .LBB0_120
; %bb.121:                              ; %.preheader14.i65.i.i.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s10, 0
.LBB0_122:                              ; %.preheader14.i65.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_123 Depth 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s10, 0
	s_mov_b32 s22, 0
	s_cselect_b32 s11, -1, 0
.LBB0_123:                              ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_122 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sub_i32 s0, 4, s22
	s_sub_i32 s23, 0, s22
	s_and_b32 s0, s0, 7
	s_and_b32 s23, s23, 7
	s_lshl_b32 s0, s0, 2
	s_lshl_b32 s23, s23, 2
	s_add_i32 s0, s0, 16
	s_add_i32 s23, s23, 16
	s_clause 0x1
	scratch_load_b32 v5, off, s0
	scratch_load_b32 v0, off, s23
	s_and_not1_b32 vcc_lo, exec_lo, s11
	s_cbranch_vccnz .LBB0_125
; %bb.124:                              ;   in Loop: Header=BB0_123 Depth=3
	s_add_i32 s0, s22, 14
	s_add_i32 s23, s22, 1
	s_and_b32 s0, s0, 15
	s_and_b32 s24, s23, 15
	s_lshl_b32 s0, s0, 2
	s_lshl_b32 s24, s24, 2
	s_add_i32 s0, s16, s0
	scratch_load_b32 v6, off, s0
	s_add_i32 s0, s16, s24
	s_add_i32 s24, s22, 9
	scratch_load_b32 v7, off, s0
	s_and_b32 s0, s24, 15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s0, s0, 2
	s_add_i32 s0, s16, s0
	scratch_load_b32 v9, off, s0
	s_lshl_b32 s0, s22, 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s24, s16, s0
	s_mov_b32 s0, 0
	scratch_load_b32 v10, off, s24
	s_waitcnt vmcnt(3)
	v_alignbit_b32 v11, v6, v6, 17
	v_alignbit_b32 v12, v6, v6, 19
	v_lshrrev_b32_e32 v6, 10, v6
	s_waitcnt vmcnt(2)
	v_alignbit_b32 v13, v7, v7, 7
	v_alignbit_b32 v14, v7, v7, 18
	v_lshrrev_b32_e32 v7, 3, v7
	v_xor_b32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor3_b32 v7, v13, v14, v7
	s_waitcnt vmcnt(1)
	v_xad_u32 v6, v11, v6, v9
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v6, v6, v10, v7
	scratch_store_b32 off, v6, s24
	s_branch .LBB0_126
.LBB0_125:                              ;   in Loop: Header=BB0_123 Depth=3
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr6
                                        ; implicit-def: $sgpr23
.LBB0_126:                              ; %Flow933
                                        ;   in Loop: Header=BB0_123 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_128
; %bb.127:                              ;   in Loop: Header=BB0_123 Depth=3
	s_lshl_b32 s0, s22, 2
	s_add_i32 s23, s22, 1
	s_add_i32 s0, s16, s0
	scratch_load_b32 v6, off, s0
.LBB0_128:                              ; %m_cycle.exit.i69.i.i
                                        ;   in Loop: Header=BB0_123 Depth=3
	s_getpc_b64 s[24:25]
	s_add_u32 s24, s24, _ZL4k256@rel32@lo+4
	s_addc_u32 s25, s25, _ZL4k256@rel32@hi+12
	s_or_b32 s0, s22, s10
	s_waitcnt vmcnt(1)
	v_alignbit_b32 v11, v5, v5, 6
	s_lshl_b64 s[26:27], s[0:1], 2
	v_alignbit_b32 v12, v5, v5, 11
	s_add_u32 s24, s26, s24
	s_addc_u32 s25, s27, s25
	s_sub_i32 s0, 6, s22
	s_sub_i32 s26, 5, s22
	s_and_b32 s0, s0, 7
	s_and_b32 s26, s26, 7
	s_lshl_b32 s0, s0, 2
	s_sub_i32 s27, 7, s22
	s_lshl_b32 s26, s26, 2
	s_add_i32 s0, s0, 16
	s_add_i32 s26, s26, 16
	s_and_b32 s27, s27, 7
	s_clause 0x1
	scratch_load_b32 v7, off, s0
	scratch_load_b32 v9, off, s26
	s_lshl_b32 s0, s27, 2
	s_load_b32 s24, s[24:25], 0x0
	s_add_i32 s0, s0, 16
	v_alignbit_b32 v13, v5, v5, 25
	scratch_load_b32 v10, off, s0
	s_sub_i32 s25, 1, s22
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s25, s25, 7
	v_xor3_b32 v11, v11, v12, v13
	s_lshl_b32 s25, s25, 2
	s_add_i32 s25, s25, 16
	s_waitcnt vmcnt(3) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v6, v6, v11, s24
	s_sub_i32 s24, 3, s22
	s_sub_i32 s22, 2, s22
	s_and_b32 s24, s24, 7
	s_and_b32 s22, s22, 7
	s_lshl_b32 s24, s24, 2
	s_lshl_b32 s22, s22, 2
	s_add_i32 s24, s24, 16
	s_add_i32 s22, s22, 16
	v_alignbit_b32 v11, v0, v0, 22
	s_cmp_lg_u32 s23, 16
	s_waitcnt vmcnt(1)
	v_bfi_b32 v5, v5, v9, v7
	v_alignbit_b32 v9, v0, v0, 2
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2)
	v_add3_u32 v5, v6, v10, v5
	v_alignbit_b32 v10, v0, v0, 13
	scratch_store_b32 off, v5, s0
	scratch_load_b32 v6, off, s24
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v5, v5, v6
	scratch_store_b32 off, v5, s24
	s_clause 0x2
	scratch_load_b32 v5, off, s25
	scratch_load_b32 v6, off, s22
	scratch_load_b32 v7, off, s0
	s_mov_b32 s22, s23
	s_waitcnt vmcnt(2)
	v_and_b32_e32 v12, v5, v0
	v_xor_b32_e32 v0, v5, v0
	v_xor3_b32 v5, v9, v10, v11
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_or_b32 v0, v6, v0, v12
	s_waitcnt vmcnt(0)
	v_add3_u32 v0, v7, v5, v0
	scratch_store_b32 off, v0, s0
	s_cbranch_scc1 .LBB0_123
; %bb.129:                              ; %_ZL6memcpyPvPKvm.exit.i72.i.i
                                        ;   in Loop: Header=BB0_122 Depth=2
	s_add_i32 s0, s10, 16
	s_cmp_lt_u32 s10, 48
	s_mov_b32 s10, s0
	s_cbranch_scc1 .LBB0_122
; %bb.130:                              ; %.preheader.i73.i.i.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s0, 0
.LBB0_131:                              ; %.preheader.i73.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e64 v0, s0, 48
	s_add_i32 s10, s0, 16
	s_add_i32 s0, s0, 4
	s_cmp_lg_u32 s0, 32
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v0, 8, v0
	scratch_load_b32 v5, off, s10
	scratch_load_b32 v6, v0, off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v5, v6, v5
	scratch_store_b32 v0, v5, off
	s_cbranch_scc1 .LBB0_131
; %bb.132:                              ; %sha256_compile.exit77.i.i
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s0, 0
	s_mov_b32 s10, 0
.LBB0_133:                              ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s11, s10, -4
	s_add_i32 s22, s10, 0x100
	v_add_nc_u32_e64 v0, s11, 48
	s_and_not1_b32 s11, 24, s0
	s_add_i32 s10, s10, 1
	s_add_i32 s0, s0, 8
	s_cmp_lg_u32 s10, 32
	v_add_nc_u32_e32 v0, 8, v0
	scratch_load_b32 v0, v0, off
	s_waitcnt vmcnt(0)
	v_lshrrev_b32_e32 v0, s11, v0
	scratch_store_b8 off, v0, s22
	s_cbranch_scc1 .LBB0_133
; %bb.134:                              ; %.lr.ph.i.i4.i.i.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_movk_i32 s10, 0xff98
	s_mov_b32 s11, -1
	s_mov_b32 s0, 0
.LBB0_135:                              ; %.lr.ph.i.i4.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_readfirstlane_b32 s22, v27
	s_add_i32 s23, s0, 0x98
	scratch_load_u8 v0, off, s23
	s_add_i32 s22, s22, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s23, s22, 1
	s_add_i32 s24, s22, 2
	s_add_i32 s22, s22, 3
	s_clause 0x2
	scratch_load_u8 v5, off, s23
	scratch_load_u8 v6, off, s24
	scratch_load_u8 v7, off, s22
	v_readfirstlane_b32 s22, v21
	s_add_i32 s23, s0, 48
	s_delay_alu instid0(VALU_DEP_1)
	s_add_i32 s22, s22, s0
	s_add_i32 s0, s0, 4
	s_add_i32 s24, s22, 1
	s_add_i32 s25, s22, 2
	s_add_i32 s22, s22, 3
	s_add_u32 s10, s10, 4
	s_addc_u32 s11, s11, 0
	s_waitcnt vmcnt(3)
	scratch_store_b8 off, v0, s23
	s_waitcnt vmcnt(2)
	scratch_store_b8 off, v5, s24
	s_waitcnt vmcnt(1)
	scratch_store_b8 off, v6, s25
	s_waitcnt vmcnt(0)
	scratch_store_b8 off, v7, s22
	s_cmp_lg_u64 s[10:11], 0
	s_cbranch_scc1 .LBB0_135
; %bb.136:                              ; %_ZL6memcpyPvPKvm.exit.i65.i
                                        ;   in Loop: Header=BB0_2 Depth=1
	scratch_load_b32 v0, off, off offset:48
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v5, 32, v0
	scratch_store_b32 off, v5, off offset:48
	v_cmpx_lt_u32_e32 0xffffffdf, v0
	s_cbranch_execz .LBB0_138
; %bb.137:                              ;   in Loop: Header=BB0_2 Depth=1
	scratch_load_b32 v5, off, off offset:52
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v5, 1, v5
	scratch_store_b32 off, v5, off offset:52
.LBB0_138:                              ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_mov_b32_e32 v5, 32
	v_dual_mov_b32 v6, 0 :: v_dual_and_b32 v11, 63, v0
	v_mov_b32_e32 v7, 0x100
	s_mov_b32 s22, exec_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_lt_u32_e32 31, v11
	s_cbranch_execz .LBB0_169
; %bb.139:                              ; %.lr.ph.i7.preheader.i.i
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_sub_nc_u32_e32 v0, 64, v11
	v_dual_mov_b32 v5, 32 :: v_dual_mov_b32 v10, v1
	v_dual_mov_b32 v7, 0x100 :: v_dual_mov_b32 v6, 0
	s_delay_alu instid0(VALU_DEP_3)
	v_mov_b32_e32 v9, v0
	s_mov_b32 s23, 0
.LBB0_140:                              ; %.lr.ph.i7.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_142 Depth 3
                                        ;       Child Loop BB0_153 Depth 3
                                        ;       Child Loop BB0_155 Depth 3
                                        ;       Child Loop BB0_157 Depth 3
                                        ;         Child Loop BB0_158 Depth 4
                                        ;       Child Loop BB0_166 Depth 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v13, v7 :: v_dual_add_nc_u32 v0, s16, v11
	v_dual_mov_b32 v12, v10 :: v_dual_mov_b32 v11, v9
	s_mov_b32 s0, exec_lo
	v_cmpx_lt_u64_e32 3, v[9:10]
	s_cbranch_execz .LBB0_144
; %bb.141:                              ; %.lr.ph.i.i.i32.i.i.preheader
                                        ;   in Loop: Header=BB0_140 Depth=2
	v_dual_mov_b32 v13, v7 :: v_dual_mov_b32 v12, v10
	v_mov_b32_e32 v11, v9
	s_mov_b32 s10, 0
.LBB0_142:                              ; %.lr.ph.i.i.i32.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_140 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_clause 0x3
	scratch_load_u8 v14, v13, off
	scratch_load_u8 v15, v13, off offset:1
	scratch_load_u8 v16, v13, off offset:2
	scratch_load_u8 v28, v13, off offset:3
	v_add_co_u32 v11, vcc_lo, v11, -4
	v_add_co_ci_u32_e32 v12, vcc_lo, -1, v12, vcc_lo
	v_add_nc_u32_e32 v13, 4, v13
	s_waitcnt vmcnt(3)
	scratch_store_b8 v0, v14, off
	s_waitcnt vmcnt(2)
	scratch_store_b8 v0, v15, off offset:1
	s_waitcnt vmcnt(1)
	scratch_store_b8 v0, v16, off offset:2
	s_waitcnt vmcnt(0)
	scratch_store_b8 v0, v28, off offset:3
	v_cmp_gt_u64_e32 vcc_lo, 4, v[11:12]
	v_add_nc_u32_e32 v0, 4, v0
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_142
; %bb.143:                              ; %Flow929
                                        ;   in Loop: Header=BB0_140 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_144:                              ; %Flow930
                                        ;   in Loop: Header=BB0_140 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s0, 0
	s_mov_b32 s10, exec_lo
	v_cmpx_lt_i64_e32 1, v[11:12]
	s_xor_b32 s10, exec_lo, s10
	s_cbranch_execz .LBB0_148
; %bb.145:                              ; %NodeBlock823
                                        ;   in Loop: Header=BB0_140 Depth=2
	s_mov_b32 s0, exec_lo
	v_cmpx_lt_i64_e32 2, v[11:12]
	s_cbranch_execz .LBB0_147
; %bb.146:                              ;   in Loop: Header=BB0_140 Depth=2
	scratch_load_u8 v11, v13, off offset:2
	s_waitcnt vmcnt(0)
	scratch_store_b8 v0, v11, off offset:2
.LBB0_147:                              ;   in Loop: Header=BB0_140 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	scratch_load_u8 v11, v13, off offset:1
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	scratch_store_b8 v0, v11, off offset:1
                                        ; implicit-def: $vgpr11_vgpr12
.LBB0_148:                              ; %Flow927
                                        ;   in Loop: Header=BB0_140 Depth=2
	s_and_not1_saveexec_b32 s10, s10
; %bb.149:                              ; %LeafBlock821
                                        ;   in Loop: Header=BB0_140 Depth=2
	v_cmp_eq_u64_e32 vcc_lo, 1, v[11:12]
	s_and_not1_b32 s0, s0, exec_lo
	s_and_b32 s11, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s0, s0, s11
; %bb.150:                              ; %Flow928
                                        ;   in Loop: Header=BB0_140 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
	s_and_saveexec_b32 s10, s0
	s_cbranch_execz .LBB0_152
; %bb.151:                              ;   in Loop: Header=BB0_140 Depth=2
	scratch_load_u8 v11, v13, off
	s_waitcnt vmcnt(0)
	scratch_store_b8 v0, v11, off
.LBB0_152:                              ; %_ZL6memcpyPvPKvm.exit.i16.i.i.preheader
                                        ;   in Loop: Header=BB0_140 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
	s_movk_i32 s0, 0x64
.LBB0_153:                              ; %_ZL6memcpyPvPKvm.exit.i16.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_140 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s10, s0, 48
	s_add_i32 s0, s0, -4
	scratch_load_b32 v0, off, s10
	s_cmp_lg_u32 s0, 36
	s_waitcnt vmcnt(0)
	v_perm_b32 v0, 0, v0, 0x10203
	scratch_store_b32 off, v0, s10
	s_cbranch_scc1 .LBB0_153
; %bb.154:                              ;   in Loop: Header=BB0_140 Depth=2
	s_movk_i32 s10, 0xffe0
	s_mov_b32 s11, -1
	s_mov_b32 s0, 0
.LBB0_155:                              ; %.lr.ph.i.i.i97.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_140 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s24, s17, s0
	s_add_i32 s25, s24, 1
	s_add_i32 s26, s24, 2
	s_add_i32 s27, s24, 3
	s_clause 0x3
	scratch_load_u8 v0, off, s24
	scratch_load_u8 v11, off, s25
	scratch_load_u8 v12, off, s26
	scratch_load_u8 v13, off, s27
	v_readfirstlane_b32 s24, v26
	s_add_i32 s25, s0, 16
	s_delay_alu instid0(VALU_DEP_1)
	s_add_i32 s24, s24, s0
	s_add_i32 s0, s0, 4
	s_add_i32 s26, s24, 1
	s_add_i32 s27, s24, 2
	s_add_i32 s24, s24, 3
	s_add_u32 s10, s10, 4
	s_addc_u32 s11, s11, 0
	s_waitcnt vmcnt(3)
	scratch_store_b8 off, v0, s25
	s_waitcnt vmcnt(2)
	scratch_store_b8 off, v11, s26
	s_waitcnt vmcnt(1)
	scratch_store_b8 off, v12, s27
	s_waitcnt vmcnt(0)
	scratch_store_b8 off, v13, s24
	s_cmp_lg_u64 s[10:11], 0
	s_cbranch_scc1 .LBB0_155
; %bb.156:                              ; %.preheader14.i103.i.i.preheader
                                        ;   in Loop: Header=BB0_140 Depth=2
	s_mov_b32 s10, 0
.LBB0_157:                              ; %.preheader14.i103.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_140 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_158 Depth 4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s10, 0
	s_mov_b32 s24, 0
	s_cselect_b32 s11, -1, 0
.LBB0_158:                              ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_140 Depth=2
                                        ;       Parent Loop BB0_157 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_sub_i32 s0, 4, s24
	s_sub_i32 s25, 0, s24
	s_and_b32 s0, s0, 7
	s_and_b32 s25, s25, 7
	s_lshl_b32 s0, s0, 2
	s_lshl_b32 s25, s25, 2
	s_add_i32 s0, s0, 16
	s_add_i32 s25, s25, 16
	s_clause 0x1
	scratch_load_b32 v11, off, s0
	scratch_load_b32 v0, off, s25
	s_and_not1_b32 vcc_lo, exec_lo, s11
	s_cbranch_vccnz .LBB0_160
; %bb.159:                              ;   in Loop: Header=BB0_158 Depth=4
	s_add_i32 s0, s24, 14
	s_add_i32 s25, s24, 1
	s_and_b32 s0, s0, 15
	s_and_b32 s26, s25, 15
	s_lshl_b32 s0, s0, 2
	s_lshl_b32 s26, s26, 2
	s_add_i32 s0, s16, s0
	scratch_load_b32 v12, off, s0
	s_add_i32 s0, s16, s26
	s_add_i32 s26, s24, 9
	scratch_load_b32 v13, off, s0
	s_and_b32 s0, s26, 15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s0, s0, 2
	s_add_i32 s0, s16, s0
	scratch_load_b32 v14, off, s0
	s_lshl_b32 s0, s24, 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s26, s16, s0
	s_mov_b32 s0, 0
	scratch_load_b32 v15, off, s26
	s_waitcnt vmcnt(3)
	v_alignbit_b32 v16, v12, v12, 17
	v_alignbit_b32 v28, v12, v12, 19
	v_lshrrev_b32_e32 v12, 10, v12
	s_waitcnt vmcnt(2)
	v_alignbit_b32 v29, v13, v13, 7
	v_alignbit_b32 v30, v13, v13, 18
	v_lshrrev_b32_e32 v13, 3, v13
	v_xor_b32_e32 v16, v16, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor3_b32 v13, v29, v30, v13
	s_waitcnt vmcnt(1)
	v_xad_u32 v12, v16, v12, v14
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v12, v12, v15, v13
	scratch_store_b32 off, v12, s26
	s_branch .LBB0_161
.LBB0_160:                              ;   in Loop: Header=BB0_158 Depth=4
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr12
                                        ; implicit-def: $sgpr25
.LBB0_161:                              ; %Flow926
                                        ;   in Loop: Header=BB0_158 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_163
; %bb.162:                              ;   in Loop: Header=BB0_158 Depth=4
	s_lshl_b32 s0, s24, 2
	s_add_i32 s25, s24, 1
	s_add_i32 s0, s16, s0
	scratch_load_b32 v12, off, s0
.LBB0_163:                              ; %m_cycle.exit.i107.i.i
                                        ;   in Loop: Header=BB0_158 Depth=4
	s_getpc_b64 s[26:27]
	s_add_u32 s26, s26, _ZL4k256@rel32@lo+4
	s_addc_u32 s27, s27, _ZL4k256@rel32@hi+12
	s_or_b32 s0, s24, s10
	s_waitcnt vmcnt(1)
	v_alignbit_b32 v16, v11, v11, 6
	s_lshl_b64 s[28:29], s[0:1], 2
	v_alignbit_b32 v28, v11, v11, 11
	s_add_u32 s26, s28, s26
	s_addc_u32 s27, s29, s27
	s_sub_i32 s0, 6, s24
	s_sub_i32 s28, 5, s24
	s_and_b32 s0, s0, 7
	s_and_b32 s28, s28, 7
	s_lshl_b32 s0, s0, 2
	s_sub_i32 s29, 7, s24
	s_lshl_b32 s28, s28, 2
	s_add_i32 s0, s0, 16
	s_add_i32 s28, s28, 16
	s_and_b32 s29, s29, 7
	s_clause 0x1
	scratch_load_b32 v13, off, s0
	scratch_load_b32 v14, off, s28
	s_lshl_b32 s0, s29, 2
	s_load_b32 s26, s[26:27], 0x0
	s_add_i32 s0, s0, 16
	v_alignbit_b32 v29, v11, v11, 25
	scratch_load_b32 v15, off, s0
	s_sub_i32 s27, 1, s24
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s27, s27, 7
	v_xor3_b32 v16, v16, v28, v29
	s_lshl_b32 s27, s27, 2
	s_add_i32 s27, s27, 16
	s_waitcnt vmcnt(3) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v12, v12, v16, s26
	s_sub_i32 s26, 3, s24
	s_sub_i32 s24, 2, s24
	s_and_b32 s26, s26, 7
	s_and_b32 s24, s24, 7
	s_lshl_b32 s26, s26, 2
	s_lshl_b32 s24, s24, 2
	s_add_i32 s26, s26, 16
	s_add_i32 s24, s24, 16
	v_alignbit_b32 v16, v0, v0, 22
	s_cmp_lg_u32 s25, 16
	s_waitcnt vmcnt(1)
	v_bfi_b32 v11, v11, v14, v13
	v_alignbit_b32 v14, v0, v0, 2
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2)
	v_add3_u32 v11, v12, v15, v11
	v_alignbit_b32 v15, v0, v0, 13
	scratch_store_b32 off, v11, s0
	scratch_load_b32 v12, off, s26
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	scratch_store_b32 off, v11, s26
	s_clause 0x2
	scratch_load_b32 v11, off, s27
	scratch_load_b32 v12, off, s24
	scratch_load_b32 v13, off, s0
	s_mov_b32 s24, s25
	s_waitcnt vmcnt(2)
	v_and_b32_e32 v28, v11, v0
	v_xor_b32_e32 v0, v11, v0
	v_xor3_b32 v11, v14, v15, v16
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_or_b32 v0, v12, v0, v28
	s_waitcnt vmcnt(0)
	v_add3_u32 v0, v13, v11, v0
	scratch_store_b32 off, v0, s0
	s_cbranch_scc1 .LBB0_158
; %bb.164:                              ; %_ZL6memcpyPvPKvm.exit.i110.i.i
                                        ;   in Loop: Header=BB0_157 Depth=3
	s_add_i32 s0, s10, 16
	s_cmp_lt_u32 s10, 48
	s_mov_b32 s10, s0
	s_cbranch_scc1 .LBB0_157
; %bb.165:                              ; %.preheader.i111.i.i.preheader
                                        ;   in Loop: Header=BB0_140 Depth=2
	s_mov_b32 s0, 0
.LBB0_166:                              ; %.preheader.i111.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_140 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	s_add_i32 s10, s0, 16
	s_add_i32 s11, s17, s0
	scratch_load_b32 v0, off, s10
	scratch_load_b32 v11, off, s11
	s_add_i32 s0, s0, 4
	s_cmp_lg_u32 s0, 32
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v0, v11, v0
	scratch_store_b32 off, v0, s11
	s_cbranch_scc1 .LBB0_166
; %bb.167:                              ; %sha256_compile.exit115.i.i
                                        ;   in Loop: Header=BB0_140 Depth=2
	v_sub_co_u32 v5, vcc_lo, v5, v9
	v_sub_co_ci_u32_e32 v6, vcc_lo, v6, v10, vcc_lo
	v_add_nc_u32_e32 v7, v7, v9
	v_mov_b32_e32 v9, 64
	v_mov_b32_e32 v10, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_cmp_gt_u64_e32 vcc_lo, 64, v[5:6]
	v_mov_b32_e32 v11, 0
	s_or_b32 s23, vcc_lo, s23
	s_and_not1_b32 exec_lo, exec_lo, s23
	s_cbranch_execnz .LBB0_140
; %bb.168:                              ; %Flow931
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s23
	v_mov_b32_e32 v11, 0
.LBB0_169:                              ; %Flow932
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v0, s16, v11
	s_mov_b32 s0, exec_lo
	v_cmpx_lt_u64_e32 3, v[5:6]
	s_cbranch_execz .LBB0_173
; %bb.170:                              ; %.lr.ph.i.i38.i28.i.i.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s10, 0
.LBB0_171:                              ; %.lr.ph.i.i38.i28.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_clause 0x3
	scratch_load_u8 v9, v7, off
	scratch_load_u8 v10, v7, off offset:1
	scratch_load_u8 v11, v7, off offset:2
	scratch_load_u8 v12, v7, off offset:3
	v_add_co_u32 v5, vcc_lo, v5, -4
	v_add_co_ci_u32_e32 v6, vcc_lo, -1, v6, vcc_lo
	v_add_nc_u32_e32 v7, 4, v7
	s_waitcnt vmcnt(3)
	scratch_store_b8 v0, v9, off
	s_waitcnt vmcnt(2)
	scratch_store_b8 v0, v10, off offset:1
	s_waitcnt vmcnt(1)
	scratch_store_b8 v0, v11, off offset:2
	s_waitcnt vmcnt(0)
	scratch_store_b8 v0, v12, off offset:3
	v_cmp_gt_u64_e32 vcc_lo, 4, v[5:6]
	v_add_nc_u32_e32 v0, 4, v0
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_171
; %bb.172:                              ; %Flow924
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_173:                              ; %Flow925
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s0, 0
	s_mov_b32 s10, exec_lo
	v_cmpx_lt_i64_e32 1, v[5:6]
	s_xor_b32 s10, exec_lo, s10
	s_cbranch_execz .LBB0_177
; %bb.174:                              ; %NodeBlock829
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s0, exec_lo
	v_cmpx_lt_i64_e32 2, v[5:6]
	s_cbranch_execz .LBB0_176
; %bb.175:                              ;   in Loop: Header=BB0_2 Depth=1
	scratch_load_u8 v5, v7, off offset:2
	s_waitcnt vmcnt(0)
	scratch_store_b8 v0, v5, off offset:2
.LBB0_176:                              ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	scratch_load_u8 v5, v7, off offset:1
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	scratch_store_b8 v0, v5, off offset:1
                                        ; implicit-def: $vgpr5_vgpr6
.LBB0_177:                              ; %Flow922
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s10, s10
; %bb.178:                              ; %LeafBlock827
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_cmp_eq_u64_e32 vcc_lo, 1, v[5:6]
	s_and_not1_b32 s0, s0, exec_lo
	s_and_b32 s11, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s0, s0, s11
; %bb.179:                              ; %Flow923
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_and_saveexec_b32 s10, s0
	s_cbranch_execz .LBB0_181
; %bb.180:                              ;   in Loop: Header=BB0_2 Depth=1
	scratch_load_u8 v5, v7, off
	s_waitcnt vmcnt(0)
	scratch_store_b8 v0, v5, off
.LBB0_181:                              ; %sha256_hash.exit36.i.i
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	scratch_load_b32 v5, off, off offset:48
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v0, 63, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ne_u32_e32 0, v0
	s_cbranch_execz .LBB0_184
; %bb.182:                              ; %.lr.ph.i.i38.i66.i
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v6, 3, v0
	s_mov_b32 s10, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_and_b32_e32 v6, 0x7c, v6
.LBB0_183:                              ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v7, v22, v6
	v_add_nc_u32_e32 v6, -4, v6
	scratch_load_b32 v9, v7, off
	v_cmp_eq_u32_e32 vcc_lo, 0, v6
	s_or_b32 s10, vcc_lo, s10
	s_waitcnt vmcnt(0)
	v_perm_b32 v9, 0, v9, 0x10203
	scratch_store_b32 v7, v9, off
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_183
.LBB0_184:                              ; %Flow921
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_and_b32_e32 v6, 60, v0
	v_not_b32_e32 v5, v5
	s_mov_b32 s0, exec_lo
	scratch_load_b32 v7, v6, off offset:88
	v_lshlrev_b32_e32 v5, 3, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e64 v9, v5, 0xffffff80
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v7, v7, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_or_b32 v5, 0x80, v5, v7
	scratch_store_b32 v6, v5, off offset:88
                                        ; implicit-def: $vgpr5_vgpr6
	v_cmpx_gt_u32_e32 56, v0
	s_xor_b32 s0, exec_lo, s0
; %bb.185:                              ;   in Loop: Header=BB0_2 Depth=1
	v_lshrrev_b32_e32 v0, 2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, 1, v0
	v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v5, v0
                                        ; implicit-def: $vgpr0
; %bb.186:                              ; %Flow918
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s22, s0
	s_cbranch_execz .LBB0_203
; %bb.187:                              ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 60, v0
	s_cbranch_execz .LBB0_189
; %bb.188:                              ;   in Loop: Header=BB0_2 Depth=1
	scratch_store_b32 off, v1, off offset:148
.LBB0_189:                              ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_movk_i32 s10, 0xffe0
	s_mov_b32 s11, -1
	s_mov_b32 s0, 0
.LBB0_190:                              ; %.lr.ph.i.i.i135.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s23, s17, s0
	s_add_i32 s24, s23, 1
	s_add_i32 s25, s23, 2
	s_add_i32 s26, s23, 3
	s_clause 0x3
	scratch_load_u8 v0, off, s23
	scratch_load_u8 v5, off, s24
	scratch_load_u8 v6, off, s25
	scratch_load_u8 v7, off, s26
	v_readfirstlane_b32 s23, v26
	s_add_i32 s24, s0, 16
	s_delay_alu instid0(VALU_DEP_1)
	s_add_i32 s23, s23, s0
	s_add_i32 s0, s0, 4
	s_add_i32 s25, s23, 1
	s_add_i32 s26, s23, 2
	s_add_i32 s23, s23, 3
	s_add_u32 s10, s10, 4
	s_addc_u32 s11, s11, 0
	s_waitcnt vmcnt(3)
	scratch_store_b8 off, v0, s24
	s_waitcnt vmcnt(2)
	scratch_store_b8 off, v5, s25
	s_waitcnt vmcnt(1)
	scratch_store_b8 off, v6, s26
	s_waitcnt vmcnt(0)
	scratch_store_b8 off, v7, s23
	s_cmp_lg_u64 s[10:11], 0
	s_cbranch_scc1 .LBB0_190
; %bb.191:                              ; %.preheader14.i141.i.i.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s10, 0
.LBB0_192:                              ; %.preheader14.i141.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_193 Depth 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s10, 0
	s_mov_b32 s23, 0
	s_cselect_b32 s11, -1, 0
.LBB0_193:                              ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_192 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sub_i32 s0, 4, s23
	s_sub_i32 s24, 0, s23
	s_and_b32 s0, s0, 7
	s_and_b32 s24, s24, 7
	s_lshl_b32 s0, s0, 2
	s_lshl_b32 s24, s24, 2
	s_add_i32 s0, s0, 16
	s_add_i32 s24, s24, 16
	s_clause 0x1
	scratch_load_b32 v5, off, s0
	scratch_load_b32 v0, off, s24
	s_and_not1_b32 vcc_lo, exec_lo, s11
	s_cbranch_vccnz .LBB0_195
; %bb.194:                              ;   in Loop: Header=BB0_193 Depth=3
	s_add_i32 s0, s23, 14
	s_add_i32 s24, s23, 1
	s_and_b32 s0, s0, 15
	s_and_b32 s25, s24, 15
	s_lshl_b32 s0, s0, 2
	s_lshl_b32 s25, s25, 2
	s_add_i32 s0, s16, s0
	scratch_load_b32 v6, off, s0
	s_add_i32 s0, s16, s25
	s_add_i32 s25, s23, 9
	scratch_load_b32 v7, off, s0
	s_and_b32 s0, s25, 15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s0, s0, 2
	s_add_i32 s0, s16, s0
	scratch_load_b32 v9, off, s0
	s_lshl_b32 s0, s23, 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s25, s16, s0
	s_mov_b32 s0, 0
	scratch_load_b32 v10, off, s25
	s_waitcnt vmcnt(3)
	v_alignbit_b32 v11, v6, v6, 17
	v_alignbit_b32 v12, v6, v6, 19
	v_lshrrev_b32_e32 v6, 10, v6
	s_waitcnt vmcnt(2)
	v_alignbit_b32 v13, v7, v7, 7
	v_alignbit_b32 v14, v7, v7, 18
	v_lshrrev_b32_e32 v7, 3, v7
	v_xor_b32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor3_b32 v7, v13, v14, v7
	s_waitcnt vmcnt(1)
	v_xad_u32 v6, v11, v6, v9
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v6, v6, v10, v7
	scratch_store_b32 off, v6, s25
	s_branch .LBB0_196
.LBB0_195:                              ;   in Loop: Header=BB0_193 Depth=3
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr6
                                        ; implicit-def: $sgpr24
.LBB0_196:                              ; %Flow917
                                        ;   in Loop: Header=BB0_193 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_198
; %bb.197:                              ;   in Loop: Header=BB0_193 Depth=3
	s_lshl_b32 s0, s23, 2
	s_add_i32 s24, s23, 1
	s_add_i32 s0, s16, s0
	scratch_load_b32 v6, off, s0
.LBB0_198:                              ; %m_cycle.exit.i145.i.i
                                        ;   in Loop: Header=BB0_193 Depth=3
	s_getpc_b64 s[26:27]
	s_add_u32 s26, s26, _ZL4k256@rel32@lo+4
	s_addc_u32 s27, s27, _ZL4k256@rel32@hi+12
	s_or_b32 s0, s23, s10
	s_waitcnt vmcnt(1)
	v_alignbit_b32 v11, v5, v5, 6
	s_lshl_b64 s[28:29], s[0:1], 2
	v_alignbit_b32 v12, v5, v5, 11
	s_add_u32 s26, s28, s26
	s_addc_u32 s27, s29, s27
	s_sub_i32 s0, 6, s23
	s_sub_i32 s25, 5, s23
	s_and_b32 s0, s0, 7
	s_and_b32 s25, s25, 7
	s_lshl_b32 s0, s0, 2
	s_sub_i32 s28, 7, s23
	s_lshl_b32 s25, s25, 2
	s_add_i32 s0, s0, 16
	s_add_i32 s25, s25, 16
	s_and_b32 s28, s28, 7
	s_clause 0x1
	scratch_load_b32 v7, off, s0
	scratch_load_b32 v9, off, s25
	s_lshl_b32 s0, s28, 2
	s_load_b32 s25, s[26:27], 0x0
	s_add_i32 s0, s0, 16
	v_alignbit_b32 v13, v5, v5, 25
	scratch_load_b32 v10, off, s0
	s_sub_i32 s26, 1, s23
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s26, s26, 7
	v_xor3_b32 v11, v11, v12, v13
	s_lshl_b32 s26, s26, 2
	s_add_i32 s26, s26, 16
	s_waitcnt vmcnt(3) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v6, v6, v11, s25
	s_sub_i32 s25, 3, s23
	s_sub_i32 s23, 2, s23
	s_and_b32 s25, s25, 7
	s_and_b32 s23, s23, 7
	s_lshl_b32 s25, s25, 2
	s_lshl_b32 s23, s23, 2
	s_add_i32 s25, s25, 16
	s_add_i32 s23, s23, 16
	v_alignbit_b32 v11, v0, v0, 22
	s_cmp_lg_u32 s24, 16
	s_waitcnt vmcnt(1)
	v_bfi_b32 v5, v5, v9, v7
	v_alignbit_b32 v9, v0, v0, 2
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2)
	v_add3_u32 v5, v6, v10, v5
	v_alignbit_b32 v10, v0, v0, 13
	scratch_store_b32 off, v5, s0
	scratch_load_b32 v6, off, s25
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v5, v5, v6
	scratch_store_b32 off, v5, s25
	s_clause 0x2
	scratch_load_b32 v5, off, s26
	scratch_load_b32 v6, off, s23
	scratch_load_b32 v7, off, s0
	s_mov_b32 s23, s24
	s_waitcnt vmcnt(2)
	v_and_b32_e32 v12, v5, v0
	v_xor_b32_e32 v0, v5, v0
	v_xor3_b32 v5, v9, v10, v11
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_or_b32 v0, v6, v0, v12
	s_waitcnt vmcnt(0)
	v_add3_u32 v0, v7, v5, v0
	scratch_store_b32 off, v0, s0
	s_cbranch_scc1 .LBB0_193
; %bb.199:                              ; %_ZL6memcpyPvPKvm.exit.i148.i.i
                                        ;   in Loop: Header=BB0_192 Depth=2
	s_add_i32 s0, s10, 16
	s_cmp_lt_u32 s10, 48
	s_mov_b32 s10, s0
	s_cbranch_scc1 .LBB0_192
; %bb.200:                              ; %.preheader.i149.i.i.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s0, 0
.LBB0_201:                              ; %.preheader.i149.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	s_add_i32 s10, s0, 16
	s_add_i32 s11, s17, s0
	scratch_load_b32 v0, off, s10
	scratch_load_b32 v5, off, s11
	s_add_i32 s0, s0, 4
	s_cmp_lg_u32 s0, 32
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v0, v5, v0
	scratch_store_b32 off, v0, s11
	s_cbranch_scc1 .LBB0_201
; %bb.202:                              ; %sha256_compile.exit153.i.i
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v5, 0
	v_mov_b32_e32 v6, 0
.LBB0_203:                              ; %Flow919
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v0, 2, v5
	v_sub_co_u32 v5, vcc_lo, 0x42, v5
	v_sub_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	s_mov_b32 s10, 0
.LBB0_204:                              ; %.lr.ph.i.i.i.i44.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, v5, -8
	v_add_co_ci_u32_e32 v10, vcc_lo, -1, v6, vcc_lo
	v_add_nc_u32_e32 v7, 48, v0
	v_add_co_u32 v5, s0, v5, -4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cmp_gt_u64_e32 vcc_lo, 4, v[9:10]
	v_add_nc_u32_e32 v0, 4, v0
	v_add_nc_u32_e32 v11, 40, v7
	v_add_nc_u32_e32 v13, 42, v7
	v_add_co_ci_u32_e64 v6, s0, -1, v6, s0
	v_add_nc_u32_e32 v12, 41, v7
	v_add_nc_u32_e32 v7, 43, v7
	s_or_b32 s10, vcc_lo, s10
	s_clause 0x3
	scratch_store_b8 v11, v1, off
	scratch_store_b8 v12, v1, off
	scratch_store_b8 v13, v1, off
	scratch_store_b8 v7, v1, off
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_204
; %bb.205:                              ; %._crit_edge.i.i.i.i47.i.i
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v0, 48, v0
	s_mov_b32 s0, 0
	s_mov_b32 s10, exec_lo
	v_cmpx_lt_i64_e32 5, v[5:6]
	s_xor_b32 s10, exec_lo, s10
	s_cbranch_execz .LBB0_209
; %bb.206:                              ; %NodeBlock835
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s0, exec_lo
	v_cmpx_lt_i64_e32 6, v[5:6]
	s_cbranch_execz .LBB0_208
; %bb.207:                              ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v7, 42, v0
	scratch_store_b8 v7, v1, off
.LBB0_208:                              ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v7, 41, v0
	s_mov_b32 s0, exec_lo
	scratch_store_b8 v7, v1, off
.LBB0_209:                              ; %Flow915
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s10, s10
; %bb.210:                              ; %LeafBlock833
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_cmp_eq_u64_e32 vcc_lo, 5, v[5:6]
	s_and_not1_b32 s0, s0, exec_lo
	s_and_b32 s11, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s0, s0, s11
; %bb.211:                              ; %Flow916
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_and_saveexec_b32 s10, s0
	s_cbranch_execz .LBB0_213
; %bb.212:                              ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v0, 40, v0
	scratch_store_b8 v0, v1, off
.LBB0_213:                              ; %_ZL6memsetPvim.exit.i.i48.i.i
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	scratch_load_b64 v[5:6], off, off offset:48
	s_movk_i32 s10, 0xffe0
	s_mov_b32 s11, -1
	s_mov_b32 s0, 0
	s_waitcnt vmcnt(0)
	v_alignbit_b32 v6, v6, v5, 29
	v_lshlrev_b32_e32 v7, 3, v5
	scratch_store_b64 off, v[6:7], off offset:144
.LBB0_214:                              ; %.lr.ph.i.i.i116.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_readfirstlane_b32 s22, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s22, s22, s0
	s_add_i32 s23, s22, 8
	s_add_i32 s24, s22, 9
	s_add_i32 s25, s22, 10
	s_add_i32 s22, s22, 11
	s_clause 0x3
	scratch_load_u8 v0, off, s23
	scratch_load_u8 v5, off, s24
	scratch_load_u8 v6, off, s25
	scratch_load_u8 v7, off, s22
	v_readfirstlane_b32 s22, v26
	s_add_i32 s23, s0, 16
	s_delay_alu instid0(VALU_DEP_1)
	s_add_i32 s22, s22, s0
	s_add_i32 s0, s0, 4
	s_add_i32 s24, s22, 1
	s_add_i32 s25, s22, 2
	s_add_i32 s22, s22, 3
	s_add_u32 s10, s10, 4
	s_addc_u32 s11, s11, 0
	s_waitcnt vmcnt(3)
	scratch_store_b8 off, v0, s23
	s_waitcnt vmcnt(2)
	scratch_store_b8 off, v5, s24
	s_waitcnt vmcnt(1)
	scratch_store_b8 off, v6, s25
	s_waitcnt vmcnt(0)
	scratch_store_b8 off, v7, s22
	s_cmp_lg_u64 s[10:11], 0
	s_cbranch_scc1 .LBB0_214
; %bb.215:                              ; %.preheader14.i122.i.i.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s10, 0
.LBB0_216:                              ; %.preheader14.i122.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_217 Depth 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s10, 0
	s_mov_b32 s22, 0
	s_cselect_b32 s11, -1, 0
.LBB0_217:                              ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_216 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sub_i32 s0, 4, s22
	s_sub_i32 s23, 0, s22
	s_and_b32 s0, s0, 7
	s_and_b32 s23, s23, 7
	s_lshl_b32 s0, s0, 2
	s_lshl_b32 s23, s23, 2
	s_add_i32 s0, s0, 16
	s_add_i32 s23, s23, 16
	s_clause 0x1
	scratch_load_b32 v5, off, s0
	scratch_load_b32 v0, off, s23
	s_and_not1_b32 vcc_lo, exec_lo, s11
	s_cbranch_vccnz .LBB0_219
; %bb.218:                              ;   in Loop: Header=BB0_217 Depth=3
	s_add_i32 s0, s22, 14
	s_add_i32 s23, s22, 1
	s_and_b32 s0, s0, 15
	s_and_b32 s24, s23, 15
	s_lshl_b32 s0, s0, 2
	s_lshl_b32 s24, s24, 2
	s_add_i32 s0, s16, s0
	scratch_load_b32 v6, off, s0
	s_add_i32 s0, s16, s24
	s_add_i32 s24, s22, 9
	scratch_load_b32 v7, off, s0
	s_and_b32 s0, s24, 15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s0, s0, 2
	s_add_i32 s0, s16, s0
	scratch_load_b32 v9, off, s0
	s_lshl_b32 s0, s22, 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s24, s16, s0
	s_mov_b32 s0, 0
	scratch_load_b32 v10, off, s24
	s_waitcnt vmcnt(3)
	v_alignbit_b32 v11, v6, v6, 17
	v_alignbit_b32 v12, v6, v6, 19
	v_lshrrev_b32_e32 v6, 10, v6
	s_waitcnt vmcnt(2)
	v_alignbit_b32 v13, v7, v7, 7
	v_alignbit_b32 v14, v7, v7, 18
	v_lshrrev_b32_e32 v7, 3, v7
	v_xor_b32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor3_b32 v7, v13, v14, v7
	s_waitcnt vmcnt(1)
	v_xad_u32 v6, v11, v6, v9
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v6, v6, v10, v7
	scratch_store_b32 off, v6, s24
	s_branch .LBB0_220
.LBB0_219:                              ;   in Loop: Header=BB0_217 Depth=3
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr6
                                        ; implicit-def: $sgpr23
.LBB0_220:                              ; %Flow914
                                        ;   in Loop: Header=BB0_217 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_222
; %bb.221:                              ;   in Loop: Header=BB0_217 Depth=3
	s_lshl_b32 s0, s22, 2
	s_add_i32 s23, s22, 1
	s_add_i32 s0, s16, s0
	scratch_load_b32 v6, off, s0
.LBB0_222:                              ; %m_cycle.exit.i126.i.i
                                        ;   in Loop: Header=BB0_217 Depth=3
	s_getpc_b64 s[24:25]
	s_add_u32 s24, s24, _ZL4k256@rel32@lo+4
	s_addc_u32 s25, s25, _ZL4k256@rel32@hi+12
	s_or_b32 s0, s22, s10
	s_waitcnt vmcnt(1)
	v_alignbit_b32 v11, v5, v5, 6
	s_lshl_b64 s[26:27], s[0:1], 2
	v_alignbit_b32 v12, v5, v5, 11
	s_add_u32 s24, s26, s24
	s_addc_u32 s25, s27, s25
	s_sub_i32 s0, 6, s22
	s_sub_i32 s26, 5, s22
	s_and_b32 s0, s0, 7
	s_and_b32 s26, s26, 7
	s_lshl_b32 s0, s0, 2
	s_sub_i32 s27, 7, s22
	s_lshl_b32 s26, s26, 2
	s_add_i32 s0, s0, 16
	s_add_i32 s26, s26, 16
	s_and_b32 s27, s27, 7
	s_clause 0x1
	scratch_load_b32 v7, off, s0
	scratch_load_b32 v9, off, s26
	s_lshl_b32 s0, s27, 2
	s_load_b32 s24, s[24:25], 0x0
	s_add_i32 s0, s0, 16
	v_alignbit_b32 v13, v5, v5, 25
	scratch_load_b32 v10, off, s0
	s_sub_i32 s25, 1, s22
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s25, s25, 7
	v_xor3_b32 v11, v11, v12, v13
	s_lshl_b32 s25, s25, 2
	s_add_i32 s25, s25, 16
	s_waitcnt vmcnt(3) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v6, v6, v11, s24
	s_sub_i32 s24, 3, s22
	s_sub_i32 s22, 2, s22
	s_and_b32 s24, s24, 7
	s_and_b32 s22, s22, 7
	s_lshl_b32 s24, s24, 2
	s_lshl_b32 s22, s22, 2
	s_add_i32 s24, s24, 16
	s_add_i32 s22, s22, 16
	v_alignbit_b32 v11, v0, v0, 22
	s_cmp_lg_u32 s23, 16
	s_waitcnt vmcnt(1)
	v_bfi_b32 v5, v5, v9, v7
	v_alignbit_b32 v9, v0, v0, 2
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2)
	v_add3_u32 v5, v6, v10, v5
	v_alignbit_b32 v10, v0, v0, 13
	scratch_store_b32 off, v5, s0
	scratch_load_b32 v6, off, s24
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v5, v5, v6
	scratch_store_b32 off, v5, s24
	s_clause 0x2
	scratch_load_b32 v5, off, s25
	scratch_load_b32 v6, off, s22
	scratch_load_b32 v7, off, s0
	s_mov_b32 s22, s23
	s_waitcnt vmcnt(2)
	v_and_b32_e32 v12, v5, v0
	v_xor_b32_e32 v0, v5, v0
	v_xor3_b32 v5, v9, v10, v11
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_or_b32 v0, v6, v0, v12
	s_waitcnt vmcnt(0)
	v_add3_u32 v0, v7, v5, v0
	scratch_store_b32 off, v0, s0
	s_cbranch_scc1 .LBB0_217
; %bb.223:                              ; %_ZL6memcpyPvPKvm.exit.i129.i.i
                                        ;   in Loop: Header=BB0_216 Depth=2
	s_add_i32 s0, s10, 16
	s_cmp_lt_u32 s10, 48
	s_mov_b32 s10, s0
	s_cbranch_scc1 .LBB0_216
; %bb.224:                              ; %.preheader.i130.i.i.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s0, 0
.LBB0_225:                              ; %.preheader.i130.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e64 v0, s0, 48
	s_add_i32 s10, s0, 16
	s_add_i32 s0, s0, 4
	s_cmp_lg_u32 s0, 32
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v0, 8, v0
	scratch_load_b32 v5, off, s10
	scratch_load_b32 v6, v0, off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v5, v6, v5
	scratch_store_b32 v0, v5, off
	s_cbranch_scc1 .LBB0_225
; %bb.226:                              ; %sha256_compile.exit134.i.i
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s0, 0
	s_mov_b32 s10, 0
.LBB0_227:                              ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s11, s10, -4
	s_add_i32 s22, s10, 0x100
	v_add_nc_u32_e64 v0, s11, 48
	s_and_not1_b32 s11, 24, s0
	s_add_i32 s10, s10, 1
	s_add_i32 s0, s0, 8
	s_cmp_lg_u32 s10, 32
	v_add_nc_u32_e32 v0, 8, v0
	scratch_load_b32 v0, v0, off
	s_waitcnt vmcnt(0)
	v_lshrrev_b32_e32 v0, s11, v0
	scratch_store_b8 off, v0, s22
	s_cbranch_scc1 .LBB0_227
; %bb.228:                              ; %_Z13hmac_sha256_c10sha256_ctxS_PhiS0_.exit.i
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_ashrrev_i32_e32 v0, 31, v23
	v_add_co_u32 v5, vcc_lo, s2, v23
	s_mov_b64 s[10:11], 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s3, v0, vcc_lo
	v_mov_b32_e32 v0, 0x100
.LBB0_229:                              ; %.lr.ph.i.i67.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_clause 0x3
	scratch_load_u8 v7, v0, off offset:1
	scratch_load_u8 v9, v0, off offset:3
	scratch_load_u8 v10, v0, off
	scratch_load_u8 v11, v0, off offset:2
	v_add_nc_u32_e32 v0, 4, v0
	s_waitcnt vmcnt(3)
	v_lshlrev_b16 v7, 8, v7
	s_waitcnt vmcnt(2)
	v_lshlrev_b16 v9, 8, v9
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_or_b32_e32 v7, v10, v7
	s_waitcnt vmcnt(0)
	v_or_b32_e32 v10, v11, v9
	v_add_co_u32 v9, vcc_lo, v5, s10
	s_add_u32 s10, s10, 4
	v_and_b32_e32 v7, 0xffff, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_lshlrev_b32_e32 v11, 16, v10
	v_add_co_ci_u32_e32 v10, vcc_lo, s11, v6, vcc_lo
	s_addc_u32 s11, s11, 0
	s_cmp_lg_u64 s[10:11], 32
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v7, v7, v11
	global_store_b32 v[9:10], v7, off
	s_cbranch_scc1 .LBB0_229
; %bb.230:                              ; %_ZL6memcpyPvPKvm.exit.preheader.i
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccnz .LBB0_421
; %bb.231:                              ; %.lr.ph.i.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_mov_b32 s22, 1
.LBB0_232:                              ; %.lr.ph.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_236 Depth 3
                                        ;         Child Loop BB0_238 Depth 4
                                        ;         Child Loop BB0_249 Depth 4
                                        ;         Child Loop BB0_251 Depth 4
                                        ;         Child Loop BB0_253 Depth 4
                                        ;           Child Loop BB0_254 Depth 5
                                        ;         Child Loop BB0_262 Depth 4
                                        ;       Child Loop BB0_267 Depth 3
                                        ;       Child Loop BB0_279 Depth 3
                                        ;       Child Loop BB0_286 Depth 3
                                        ;       Child Loop BB0_288 Depth 3
                                        ;         Child Loop BB0_289 Depth 4
                                        ;       Child Loop BB0_297 Depth 3
                                        ;       Child Loop BB0_300 Depth 3
                                        ;       Child Loop BB0_310 Depth 3
                                        ;       Child Loop BB0_312 Depth 3
                                        ;         Child Loop BB0_313 Depth 4
                                        ;       Child Loop BB0_321 Depth 3
                                        ;       Child Loop BB0_323 Depth 3
                                        ;       Child Loop BB0_325 Depth 3
                                        ;       Child Loop BB0_330 Depth 3
                                        ;         Child Loop BB0_332 Depth 4
                                        ;         Child Loop BB0_343 Depth 4
                                        ;         Child Loop BB0_345 Depth 4
                                        ;         Child Loop BB0_347 Depth 4
                                        ;           Child Loop BB0_348 Depth 5
                                        ;         Child Loop BB0_356 Depth 4
                                        ;       Child Loop BB0_361 Depth 3
                                        ;       Child Loop BB0_373 Depth 3
                                        ;       Child Loop BB0_380 Depth 3
                                        ;       Child Loop BB0_382 Depth 3
                                        ;         Child Loop BB0_383 Depth 4
                                        ;       Child Loop BB0_391 Depth 3
                                        ;       Child Loop BB0_394 Depth 3
                                        ;       Child Loop BB0_404 Depth 3
                                        ;       Child Loop BB0_406 Depth 3
                                        ;         Child Loop BB0_407 Depth 4
                                        ;       Child Loop BB0_415 Depth 3
                                        ;       Child Loop BB0_417 Depth 3
                                        ;       Child Loop BB0_419 Depth 3
	s_clause 0x8
	scratch_load_b128 v[9:12], off, off offset:416
	scratch_load_b128 v[13:16], off, off offset:432
	scratch_load_b64 v[64:65], off, off offset:512
	scratch_load_b128 v[28:31], off, off offset:496
	scratch_load_b128 v[32:35], off, off offset:480
	scratch_load_b128 v[36:39], off, off offset:464
	scratch_load_b64 v[66:67], off, off offset:616
	scratch_load_b128 v[40:43], off, off offset:600
	scratch_load_b128 v[44:47], off, off offset:584
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(8)
	scratch_store_b128 off, v[9:12], off offset:48
	s_clause 0x5
	scratch_load_b128 v[9:12], off, off offset:568
	scratch_load_b128 v[48:51], off, off offset:552
	scratch_load_b32 v0, off, off offset:48
	scratch_load_b128 v[52:55], off, off offset:536
	scratch_load_b128 v[56:59], off, off offset:520
	scratch_load_b128 v[60:63], off, off offset:448
	s_waitcnt vmcnt(13)
	scratch_store_b128 off, v[13:16], off offset:64
	s_waitcnt vmcnt(12)
	scratch_store_b64 off, v[64:65], off offset:144
	s_waitcnt vmcnt(11)
	scratch_store_b128 off, v[28:31], off offset:128
	s_waitcnt vmcnt(10)
	scratch_store_b128 off, v[32:35], off offset:112
	s_waitcnt vmcnt(9)
	scratch_store_b128 off, v[36:39], off offset:96
	s_waitcnt vmcnt(8)
	scratch_store_b64 off, v[66:67], off offset:248
	s_waitcnt vmcnt(7)
	scratch_store_b128 off, v[40:43], off offset:232
	s_waitcnt vmcnt(6)
	scratch_store_b128 off, v[44:47], off offset:216
	s_waitcnt vmcnt(5)
	scratch_store_b128 off, v[9:12], off offset:200
	s_waitcnt vmcnt(4)
	scratch_store_b128 off, v[48:51], off offset:184
	s_waitcnt vmcnt(3)
	v_add_nc_u32_e32 v7, 32, v0
	s_waitcnt vmcnt(2)
	scratch_store_b128 off, v[52:55], off offset:168
	s_waitcnt vmcnt(1)
	scratch_store_b128 off, v[56:59], off offset:152
	s_waitcnt vmcnt(0)
	s_clause 0x1
	scratch_store_b128 off, v[60:63], off offset:80
	scratch_store_b32 off, v7, off offset:48
	v_cmpx_lt_u32_e32 0xffffffdf, v0
	s_cbranch_execz .LBB0_234
; %bb.233:                              ;   in Loop: Header=BB0_232 Depth=2
	scratch_load_b32 v7, off, off offset:52
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v7, 1, v7
	scratch_store_b32 off, v7, off offset:52
.LBB0_234:                              ;   in Loop: Header=BB0_232 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	v_mov_b32_e32 v9, 32
	v_dual_mov_b32 v10, 0 :: v_dual_and_b32 v13, 63, v0
	v_mov_b32_e32 v7, 0x100
	s_mov_b32 s23, exec_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_lt_u32_e32 31, v13
	s_cbranch_execz .LBB0_265
; %bb.235:                              ; %.lr.ph.i.i70.i
                                        ;   in Loop: Header=BB0_232 Depth=2
	v_sub_nc_u32_e32 v0, 64, v13
	v_dual_mov_b32 v9, 32 :: v_dual_mov_b32 v12, v1
	v_dual_mov_b32 v7, 0x100 :: v_dual_mov_b32 v10, 0
	s_delay_alu instid0(VALU_DEP_3)
	v_mov_b32_e32 v11, v0
	s_mov_b32 s24, 0
.LBB0_236:                              ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_232 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_238 Depth 4
                                        ;         Child Loop BB0_249 Depth 4
                                        ;         Child Loop BB0_251 Depth 4
                                        ;         Child Loop BB0_253 Depth 4
                                        ;           Child Loop BB0_254 Depth 5
                                        ;         Child Loop BB0_262 Depth 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v15, v7 :: v_dual_add_nc_u32 v0, s16, v13
	v_dual_mov_b32 v14, v12 :: v_dual_mov_b32 v13, v11
	s_mov_b32 s0, exec_lo
	v_cmpx_lt_u64_e32 3, v[11:12]
	s_cbranch_execz .LBB0_240
; %bb.237:                              ; %.lr.ph.i.i.i.i270.i.preheader
                                        ;   in Loop: Header=BB0_236 Depth=3
	v_dual_mov_b32 v15, v7 :: v_dual_mov_b32 v14, v12
	v_mov_b32_e32 v13, v11
	s_mov_b32 s10, 0
.LBB0_238:                              ; %.lr.ph.i.i.i.i270.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_232 Depth=2
                                        ;       Parent Loop BB0_236 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_clause 0x3
	scratch_load_u8 v16, v15, off
	scratch_load_u8 v28, v15, off offset:1
	scratch_load_u8 v29, v15, off offset:2
	scratch_load_u8 v30, v15, off offset:3
	v_add_co_u32 v13, vcc_lo, v13, -4
	v_add_co_ci_u32_e32 v14, vcc_lo, -1, v14, vcc_lo
	v_add_nc_u32_e32 v15, 4, v15
	s_waitcnt vmcnt(3)
	scratch_store_b8 v0, v16, off
	s_waitcnt vmcnt(2)
	scratch_store_b8 v0, v28, off offset:1
	s_waitcnt vmcnt(1)
	scratch_store_b8 v0, v29, off offset:2
	s_waitcnt vmcnt(0)
	scratch_store_b8 v0, v30, off offset:3
	v_cmp_gt_u64_e32 vcc_lo, 4, v[13:14]
	v_add_nc_u32_e32 v0, 4, v0
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_238
; %bb.239:                              ; %Flow908
                                        ;   in Loop: Header=BB0_236 Depth=3
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_240:                              ; %Flow909
                                        ;   in Loop: Header=BB0_236 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s0, 0
	s_mov_b32 s10, exec_lo
	v_cmpx_lt_i64_e32 1, v[13:14]
	s_xor_b32 s10, exec_lo, s10
	s_cbranch_execz .LBB0_244
; %bb.241:                              ; %NodeBlock841
                                        ;   in Loop: Header=BB0_236 Depth=3
	s_mov_b32 s0, exec_lo
	v_cmpx_lt_i64_e32 2, v[13:14]
	s_cbranch_execz .LBB0_243
; %bb.242:                              ;   in Loop: Header=BB0_236 Depth=3
	scratch_load_u8 v13, v15, off offset:2
	s_waitcnt vmcnt(0)
	scratch_store_b8 v0, v13, off offset:2
.LBB0_243:                              ;   in Loop: Header=BB0_236 Depth=3
	s_or_b32 exec_lo, exec_lo, s0
	scratch_load_u8 v13, v15, off offset:1
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	scratch_store_b8 v0, v13, off offset:1
                                        ; implicit-def: $vgpr13_vgpr14
.LBB0_244:                              ; %Flow906
                                        ;   in Loop: Header=BB0_236 Depth=3
	s_and_not1_saveexec_b32 s10, s10
; %bb.245:                              ; %LeafBlock839
                                        ;   in Loop: Header=BB0_236 Depth=3
	v_cmp_eq_u64_e32 vcc_lo, 1, v[13:14]
	s_and_not1_b32 s0, s0, exec_lo
	s_and_b32 s11, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s0, s0, s11
; %bb.246:                              ; %Flow907
                                        ;   in Loop: Header=BB0_236 Depth=3
	s_or_b32 exec_lo, exec_lo, s10
	s_and_saveexec_b32 s10, s0
	s_cbranch_execz .LBB0_248
; %bb.247:                              ;   in Loop: Header=BB0_236 Depth=3
	scratch_load_u8 v13, v15, off
	s_waitcnt vmcnt(0)
	scratch_store_b8 v0, v13, off
.LBB0_248:                              ; %_ZL6memcpyPvPKvm.exit.i.i79.i.preheader
                                        ;   in Loop: Header=BB0_236 Depth=3
	s_or_b32 exec_lo, exec_lo, s10
	s_movk_i32 s0, 0x64
.LBB0_249:                              ; %_ZL6memcpyPvPKvm.exit.i.i79.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_232 Depth=2
                                        ;       Parent Loop BB0_236 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s10, s0, 48
	s_add_i32 s0, s0, -4
	scratch_load_b32 v0, off, s10
	s_cmp_lg_u32 s0, 36
	s_waitcnt vmcnt(0)
	v_perm_b32 v0, 0, v0, 0x10203
	scratch_store_b32 off, v0, s10
	s_cbranch_scc1 .LBB0_249
; %bb.250:                              ;   in Loop: Header=BB0_236 Depth=3
	s_movk_i32 s10, 0xffe0
	s_mov_b32 s11, -1
	s_mov_b32 s0, 0
.LBB0_251:                              ; %.lr.ph.i.i.i52.i82.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_232 Depth=2
                                        ;       Parent Loop BB0_236 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s25, s17, s0
	s_add_i32 s26, s25, 1
	s_add_i32 s27, s25, 2
	s_add_i32 s28, s25, 3
	s_clause 0x3
	scratch_load_u8 v0, off, s25
	scratch_load_u8 v13, off, s26
	scratch_load_u8 v14, off, s27
	scratch_load_u8 v15, off, s28
	v_readfirstlane_b32 s25, v26
	s_add_i32 s26, s0, 16
	s_delay_alu instid0(VALU_DEP_1)
	s_add_i32 s25, s25, s0
	s_add_i32 s0, s0, 4
	s_add_i32 s27, s25, 1
	s_add_i32 s28, s25, 2
	s_add_i32 s25, s25, 3
	s_add_u32 s10, s10, 4
	s_addc_u32 s11, s11, 0
	s_waitcnt vmcnt(3)
	scratch_store_b8 off, v0, s26
	s_waitcnt vmcnt(2)
	scratch_store_b8 off, v13, s27
	s_waitcnt vmcnt(1)
	scratch_store_b8 off, v14, s28
	s_waitcnt vmcnt(0)
	scratch_store_b8 off, v15, s25
	s_cmp_lg_u64 s[10:11], 0
	s_cbranch_scc1 .LBB0_251
; %bb.252:                              ; %.preheader14.i.i87.i.preheader
                                        ;   in Loop: Header=BB0_236 Depth=3
	s_mov_b32 s10, 0
.LBB0_253:                              ; %.preheader14.i.i87.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_232 Depth=2
                                        ;       Parent Loop BB0_236 Depth=3
                                        ; =>      This Loop Header: Depth=4
                                        ;           Child Loop BB0_254 Depth 5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s10, 0
	s_mov_b32 s25, 0
	s_cselect_b32 s11, -1, 0
.LBB0_254:                              ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_232 Depth=2
                                        ;       Parent Loop BB0_236 Depth=3
                                        ;         Parent Loop BB0_253 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_sub_i32 s0, 4, s25
	s_sub_i32 s26, 0, s25
	s_and_b32 s0, s0, 7
	s_and_b32 s26, s26, 7
	s_lshl_b32 s0, s0, 2
	s_lshl_b32 s26, s26, 2
	s_add_i32 s0, s0, 16
	s_add_i32 s26, s26, 16
	s_clause 0x1
	scratch_load_b32 v13, off, s0
	scratch_load_b32 v0, off, s26
	s_and_not1_b32 vcc_lo, exec_lo, s11
	s_cbranch_vccnz .LBB0_256
; %bb.255:                              ;   in Loop: Header=BB0_254 Depth=5
	s_add_i32 s0, s25, 14
	s_add_i32 s26, s25, 1
	s_and_b32 s0, s0, 15
	s_and_b32 s27, s26, 15
	s_lshl_b32 s0, s0, 2
	s_lshl_b32 s27, s27, 2
	s_add_i32 s0, s16, s0
	scratch_load_b32 v14, off, s0
	s_add_i32 s0, s16, s27
	s_add_i32 s27, s25, 9
	scratch_load_b32 v15, off, s0
	s_and_b32 s0, s27, 15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s0, s0, 2
	s_add_i32 s0, s16, s0
	scratch_load_b32 v16, off, s0
	s_lshl_b32 s0, s25, 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s27, s16, s0
	s_mov_b32 s0, 0
	scratch_load_b32 v28, off, s27
	s_waitcnt vmcnt(3)
	v_alignbit_b32 v29, v14, v14, 17
	v_alignbit_b32 v30, v14, v14, 19
	v_lshrrev_b32_e32 v14, 10, v14
	s_waitcnt vmcnt(2)
	v_alignbit_b32 v31, v15, v15, 7
	v_alignbit_b32 v32, v15, v15, 18
	v_lshrrev_b32_e32 v15, 3, v15
	v_xor_b32_e32 v29, v29, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor3_b32 v15, v31, v32, v15
	s_waitcnt vmcnt(1)
	v_xad_u32 v14, v29, v14, v16
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v14, v14, v28, v15
	scratch_store_b32 off, v14, s27
	s_branch .LBB0_257
.LBB0_256:                              ;   in Loop: Header=BB0_254 Depth=5
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr14
                                        ; implicit-def: $sgpr26
.LBB0_257:                              ; %Flow905
                                        ;   in Loop: Header=BB0_254 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_259
; %bb.258:                              ;   in Loop: Header=BB0_254 Depth=5
	s_lshl_b32 s0, s25, 2
	s_add_i32 s26, s25, 1
	s_add_i32 s0, s16, s0
	scratch_load_b32 v14, off, s0
.LBB0_259:                              ; %m_cycle.exit.i.i91.i
                                        ;   in Loop: Header=BB0_254 Depth=5
	s_getpc_b64 s[28:29]
	s_add_u32 s28, s28, _ZL4k256@rel32@lo+4
	s_addc_u32 s29, s29, _ZL4k256@rel32@hi+12
	s_or_b32 s0, s25, s10
	s_waitcnt vmcnt(1)
	v_alignbit_b32 v29, v13, v13, 6
	s_lshl_b64 s[30:31], s[0:1], 2
	v_alignbit_b32 v30, v13, v13, 11
	s_add_u32 s28, s30, s28
	s_addc_u32 s29, s31, s29
	s_sub_i32 s0, 6, s25
	s_sub_i32 s27, 5, s25
	s_and_b32 s0, s0, 7
	s_and_b32 s27, s27, 7
	s_lshl_b32 s0, s0, 2
	s_sub_i32 s30, 7, s25
	s_lshl_b32 s27, s27, 2
	s_add_i32 s0, s0, 16
	s_add_i32 s27, s27, 16
	s_and_b32 s30, s30, 7
	s_clause 0x1
	scratch_load_b32 v15, off, s0
	scratch_load_b32 v16, off, s27
	s_lshl_b32 s0, s30, 2
	s_load_b32 s27, s[28:29], 0x0
	s_add_i32 s0, s0, 16
	v_alignbit_b32 v31, v13, v13, 25
	scratch_load_b32 v28, off, s0
	s_sub_i32 s28, 1, s25
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s28, s28, 7
	v_xor3_b32 v29, v29, v30, v31
	s_lshl_b32 s28, s28, 2
	s_add_i32 s28, s28, 16
	s_waitcnt vmcnt(3) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v14, v14, v29, s27
	s_sub_i32 s27, 3, s25
	s_sub_i32 s25, 2, s25
	s_and_b32 s27, s27, 7
	s_and_b32 s25, s25, 7
	s_lshl_b32 s27, s27, 2
	s_lshl_b32 s25, s25, 2
	s_add_i32 s27, s27, 16
	s_add_i32 s25, s25, 16
	v_alignbit_b32 v29, v0, v0, 22
	s_cmp_lg_u32 s26, 16
	s_waitcnt vmcnt(1)
	v_bfi_b32 v13, v13, v16, v15
	v_alignbit_b32 v16, v0, v0, 2
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2)
	v_add3_u32 v13, v14, v28, v13
	v_alignbit_b32 v28, v0, v0, 13
	scratch_store_b32 off, v13, s0
	scratch_load_b32 v14, off, s27
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v13, v13, v14
	scratch_store_b32 off, v13, s27
	s_clause 0x2
	scratch_load_b32 v13, off, s28
	scratch_load_b32 v14, off, s25
	scratch_load_b32 v15, off, s0
	s_mov_b32 s25, s26
	s_waitcnt vmcnt(2)
	v_and_b32_e32 v30, v13, v0
	v_xor_b32_e32 v0, v13, v0
	v_xor3_b32 v13, v16, v28, v29
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_or_b32 v0, v14, v0, v30
	s_waitcnt vmcnt(0)
	v_add3_u32 v0, v15, v13, v0
	scratch_store_b32 off, v0, s0
	s_cbranch_scc1 .LBB0_254
; %bb.260:                              ; %_ZL6memcpyPvPKvm.exit.i58.i94.i
                                        ;   in Loop: Header=BB0_253 Depth=4
	s_add_i32 s0, s10, 16
	s_cmp_lt_u32 s10, 48
	s_mov_b32 s10, s0
	s_cbranch_scc1 .LBB0_253
; %bb.261:                              ; %.preheader.i.i95.i.preheader
                                        ;   in Loop: Header=BB0_236 Depth=3
	s_mov_b32 s0, 0
.LBB0_262:                              ; %.preheader.i.i95.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_232 Depth=2
                                        ;       Parent Loop BB0_236 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	s_add_i32 s10, s0, 16
	s_add_i32 s11, s17, s0
	scratch_load_b32 v0, off, s10
	scratch_load_b32 v13, off, s11
	s_add_i32 s0, s0, 4
	s_cmp_lg_u32 s0, 32
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v0, v13, v0
	scratch_store_b32 off, v0, s11
	s_cbranch_scc1 .LBB0_262
; %bb.263:                              ; %sha256_compile.exit.i98.i
                                        ;   in Loop: Header=BB0_236 Depth=3
	v_sub_co_u32 v9, vcc_lo, v9, v11
	v_sub_co_ci_u32_e32 v10, vcc_lo, v10, v12, vcc_lo
	v_add_nc_u32_e32 v7, v7, v11
	v_mov_b32_e32 v11, 64
	v_mov_b32_e32 v12, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_cmp_gt_u64_e32 vcc_lo, 64, v[9:10]
	v_mov_b32_e32 v13, 0
	s_or_b32 s24, vcc_lo, s24
	s_and_not1_b32 exec_lo, exec_lo, s24
	s_cbranch_execnz .LBB0_236
; %bb.264:                              ; %Flow910
                                        ;   in Loop: Header=BB0_232 Depth=2
	s_or_b32 exec_lo, exec_lo, s24
	v_mov_b32_e32 v13, 0
.LBB0_265:                              ; %Flow911
                                        ;   in Loop: Header=BB0_232 Depth=2
	s_or_b32 exec_lo, exec_lo, s23
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v0, s16, v13
	s_mov_b32 s0, exec_lo
	v_cmpx_lt_u64_e32 3, v[9:10]
	s_cbranch_execz .LBB0_269
; %bb.266:                              ; %.lr.ph.i.i38.i.i265.i.preheader
                                        ;   in Loop: Header=BB0_232 Depth=2
	s_mov_b32 s10, 0
.LBB0_267:                              ; %.lr.ph.i.i38.i.i265.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_232 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_clause 0x3
	scratch_load_u8 v11, v7, off
	scratch_load_u8 v12, v7, off offset:1
	scratch_load_u8 v13, v7, off offset:2
	scratch_load_u8 v14, v7, off offset:3
	v_add_co_u32 v9, vcc_lo, v9, -4
	v_add_co_ci_u32_e32 v10, vcc_lo, -1, v10, vcc_lo
	v_add_nc_u32_e32 v7, 4, v7
	s_waitcnt vmcnt(3)
	scratch_store_b8 v0, v11, off
	s_waitcnt vmcnt(2)
	scratch_store_b8 v0, v12, off offset:1
	s_waitcnt vmcnt(1)
	scratch_store_b8 v0, v13, off offset:2
	s_waitcnt vmcnt(0)
	scratch_store_b8 v0, v14, off offset:3
	v_cmp_gt_u64_e32 vcc_lo, 4, v[9:10]
	v_add_nc_u32_e32 v0, 4, v0
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_267
; %bb.268:                              ; %Flow903
                                        ;   in Loop: Header=BB0_232 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_269:                              ; %Flow904
                                        ;   in Loop: Header=BB0_232 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s0, 0
	s_mov_b32 s10, exec_lo
	v_cmpx_lt_i64_e32 1, v[9:10]
	s_xor_b32 s10, exec_lo, s10
	s_cbranch_execz .LBB0_273
; %bb.270:                              ; %NodeBlock847
                                        ;   in Loop: Header=BB0_232 Depth=2
	s_mov_b32 s0, exec_lo
	v_cmpx_lt_i64_e32 2, v[9:10]
	s_cbranch_execz .LBB0_272
; %bb.271:                              ;   in Loop: Header=BB0_232 Depth=2
	scratch_load_u8 v9, v7, off offset:2
	s_waitcnt vmcnt(0)
	scratch_store_b8 v0, v9, off offset:2
.LBB0_272:                              ;   in Loop: Header=BB0_232 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	scratch_load_u8 v9, v7, off offset:1
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	scratch_store_b8 v0, v9, off offset:1
                                        ; implicit-def: $vgpr9_vgpr10
.LBB0_273:                              ; %Flow901
                                        ;   in Loop: Header=BB0_232 Depth=2
	s_and_not1_saveexec_b32 s10, s10
; %bb.274:                              ; %LeafBlock845
                                        ;   in Loop: Header=BB0_232 Depth=2
	v_cmp_eq_u64_e32 vcc_lo, 1, v[9:10]
	s_and_not1_b32 s0, s0, exec_lo
	s_and_b32 s11, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s0, s0, s11
; %bb.275:                              ; %Flow902
                                        ;   in Loop: Header=BB0_232 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
	s_and_saveexec_b32 s10, s0
	s_cbranch_execz .LBB0_277
; %bb.276:                              ;   in Loop: Header=BB0_232 Depth=2
	scratch_load_u8 v7, v7, off
	s_waitcnt vmcnt(0)
	scratch_store_b8 v0, v7, off
.LBB0_277:                              ; %sha256_hash.exit.i108.i
                                        ;   in Loop: Header=BB0_232 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
	scratch_load_b32 v7, off, off offset:48
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v0, 63, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ne_u32_e32 0, v0
	s_cbranch_execz .LBB0_280
; %bb.278:                              ; %.lr.ph.i.i.i110.i
                                        ;   in Loop: Header=BB0_232 Depth=2
	v_add_nc_u32_e32 v9, 3, v0
	s_mov_b32 s10, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_and_b32_e32 v9, 0x7c, v9
.LBB0_279:                              ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_232 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v10, v22, v9
	v_add_nc_u32_e32 v9, -4, v9
	scratch_load_b32 v11, v10, off
	v_cmp_eq_u32_e32 vcc_lo, 0, v9
	s_or_b32 s10, vcc_lo, s10
	s_waitcnt vmcnt(0)
	v_perm_b32 v11, 0, v11, 0x10203
	scratch_store_b32 v10, v11, off
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_279
.LBB0_280:                              ; %Flow900
                                        ;   in Loop: Header=BB0_232 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	v_and_b32_e32 v9, 60, v0
	v_not_b32_e32 v7, v7
	s_mov_b32 s0, exec_lo
	scratch_load_b32 v10, v9, off offset:88
	v_lshlrev_b32_e32 v7, 3, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e64 v11, v7, 0xffffff80
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v10, v10, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_or_b32 v7, 0x80, v7, v10
	scratch_store_b32 v9, v7, off offset:88
                                        ; implicit-def: $vgpr9_vgpr10
	v_cmpx_gt_u32_e32 56, v0
	s_xor_b32 s0, exec_lo, s0
; %bb.281:                              ;   in Loop: Header=BB0_232 Depth=2
	v_lshrrev_b32_e32 v0, 2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, 1, v0
	v_dual_mov_b32 v10, v1 :: v_dual_mov_b32 v9, v0
                                        ; implicit-def: $vgpr0
; %bb.282:                              ; %Flow897
                                        ;   in Loop: Header=BB0_232 Depth=2
	s_and_not1_saveexec_b32 s23, s0
	s_cbranch_execz .LBB0_299
; %bb.283:                              ;   in Loop: Header=BB0_232 Depth=2
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 60, v0
	s_cbranch_execz .LBB0_285
; %bb.284:                              ;   in Loop: Header=BB0_232 Depth=2
	scratch_store_b32 off, v1, off offset:148
.LBB0_285:                              ;   in Loop: Header=BB0_232 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	s_movk_i32 s10, 0xffe0
	s_mov_b32 s11, -1
	s_mov_b32 s0, 0
.LBB0_286:                              ; %.lr.ph.i.i.i78.i247.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_232 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s24, s17, s0
	s_add_i32 s25, s24, 1
	s_add_i32 s26, s24, 2
	s_add_i32 s27, s24, 3
	s_clause 0x3
	scratch_load_u8 v0, off, s24
	scratch_load_u8 v7, off, s25
	scratch_load_u8 v9, off, s26
	scratch_load_u8 v10, off, s27
	v_readfirstlane_b32 s24, v26
	s_add_i32 s25, s0, 16
	s_delay_alu instid0(VALU_DEP_1)
	s_add_i32 s24, s24, s0
	s_add_i32 s0, s0, 4
	s_add_i32 s26, s24, 1
	s_add_i32 s27, s24, 2
	s_add_i32 s24, s24, 3
	s_add_u32 s10, s10, 4
	s_addc_u32 s11, s11, 0
	s_waitcnt vmcnt(3)
	scratch_store_b8 off, v0, s25
	s_waitcnt vmcnt(2)
	scratch_store_b8 off, v7, s26
	s_waitcnt vmcnt(1)
	scratch_store_b8 off, v9, s27
	s_waitcnt vmcnt(0)
	scratch_store_b8 off, v10, s24
	s_cmp_lg_u64 s[10:11], 0
	s_cbranch_scc1 .LBB0_286
; %bb.287:                              ; %.preheader14.i84.i252.i.preheader
                                        ;   in Loop: Header=BB0_232 Depth=2
	s_mov_b32 s10, 0
.LBB0_288:                              ; %.preheader14.i84.i252.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_232 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_289 Depth 4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s10, 0
	s_mov_b32 s24, 0
	s_cselect_b32 s11, -1, 0
.LBB0_289:                              ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_232 Depth=2
                                        ;       Parent Loop BB0_288 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_sub_i32 s0, 4, s24
	s_sub_i32 s25, 0, s24
	s_and_b32 s0, s0, 7
	s_and_b32 s25, s25, 7
	s_lshl_b32 s0, s0, 2
	s_lshl_b32 s25, s25, 2
	s_add_i32 s0, s0, 16
	s_add_i32 s25, s25, 16
	s_clause 0x1
	scratch_load_b32 v7, off, s0
	scratch_load_b32 v0, off, s25
	s_and_not1_b32 vcc_lo, exec_lo, s11
	s_cbranch_vccnz .LBB0_291
; %bb.290:                              ;   in Loop: Header=BB0_289 Depth=4
	s_add_i32 s0, s24, 14
	s_add_i32 s25, s24, 1
	s_and_b32 s0, s0, 15
	s_and_b32 s26, s25, 15
	s_lshl_b32 s0, s0, 2
	s_lshl_b32 s26, s26, 2
	s_add_i32 s0, s16, s0
	scratch_load_b32 v9, off, s0
	s_add_i32 s0, s16, s26
	s_add_i32 s26, s24, 9
	scratch_load_b32 v10, off, s0
	s_and_b32 s0, s26, 15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s0, s0, 2
	s_add_i32 s0, s16, s0
	scratch_load_b32 v11, off, s0
	s_lshl_b32 s0, s24, 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s26, s16, s0
	s_mov_b32 s0, 0
	scratch_load_b32 v12, off, s26
	s_waitcnt vmcnt(3)
	v_alignbit_b32 v13, v9, v9, 17
	v_alignbit_b32 v14, v9, v9, 19
	v_lshrrev_b32_e32 v9, 10, v9
	s_waitcnt vmcnt(2)
	v_alignbit_b32 v15, v10, v10, 7
	v_alignbit_b32 v16, v10, v10, 18
	v_lshrrev_b32_e32 v10, 3, v10
	v_xor_b32_e32 v13, v13, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor3_b32 v10, v15, v16, v10
	s_waitcnt vmcnt(1)
	v_xad_u32 v9, v13, v9, v11
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v9, v9, v12, v10
	scratch_store_b32 off, v9, s26
	s_branch .LBB0_292
.LBB0_291:                              ;   in Loop: Header=BB0_289 Depth=4
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $sgpr25
.LBB0_292:                              ; %Flow896
                                        ;   in Loop: Header=BB0_289 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_294
; %bb.293:                              ;   in Loop: Header=BB0_289 Depth=4
	s_lshl_b32 s0, s24, 2
	s_add_i32 s25, s24, 1
	s_add_i32 s0, s16, s0
	scratch_load_b32 v9, off, s0
.LBB0_294:                              ; %m_cycle.exit.i88.i256.i
                                        ;   in Loop: Header=BB0_289 Depth=4
	s_getpc_b64 s[26:27]
	s_add_u32 s26, s26, _ZL4k256@rel32@lo+4
	s_addc_u32 s27, s27, _ZL4k256@rel32@hi+12
	s_or_b32 s0, s24, s10
	s_waitcnt vmcnt(1)
	v_alignbit_b32 v13, v7, v7, 6
	s_lshl_b64 s[28:29], s[0:1], 2
	v_alignbit_b32 v14, v7, v7, 11
	s_add_u32 s26, s28, s26
	s_addc_u32 s27, s29, s27
	s_sub_i32 s0, 6, s24
	s_sub_i32 s28, 5, s24
	s_and_b32 s0, s0, 7
	s_and_b32 s28, s28, 7
	s_lshl_b32 s0, s0, 2
	s_sub_i32 s29, 7, s24
	s_lshl_b32 s28, s28, 2
	s_add_i32 s0, s0, 16
	s_add_i32 s28, s28, 16
	s_and_b32 s29, s29, 7
	s_clause 0x1
	scratch_load_b32 v10, off, s0
	scratch_load_b32 v11, off, s28
	s_lshl_b32 s0, s29, 2
	s_load_b32 s26, s[26:27], 0x0
	s_add_i32 s0, s0, 16
	v_alignbit_b32 v15, v7, v7, 25
	scratch_load_b32 v12, off, s0
	s_sub_i32 s27, 1, s24
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s27, s27, 7
	v_xor3_b32 v13, v13, v14, v15
	s_lshl_b32 s27, s27, 2
	s_add_i32 s27, s27, 16
	s_waitcnt vmcnt(3) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v9, v9, v13, s26
	s_sub_i32 s26, 3, s24
	s_sub_i32 s24, 2, s24
	s_and_b32 s26, s26, 7
	s_and_b32 s24, s24, 7
	s_lshl_b32 s26, s26, 2
	s_lshl_b32 s24, s24, 2
	s_add_i32 s26, s26, 16
	s_add_i32 s24, s24, 16
	v_alignbit_b32 v13, v0, v0, 22
	s_cmp_lg_u32 s25, 16
	s_waitcnt vmcnt(1)
	v_bfi_b32 v7, v7, v11, v10
	v_alignbit_b32 v11, v0, v0, 2
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2)
	v_add3_u32 v7, v9, v12, v7
	v_alignbit_b32 v12, v0, v0, 13
	scratch_store_b32 off, v7, s0
	scratch_load_b32 v9, off, s26
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v7, v7, v9
	scratch_store_b32 off, v7, s26
	s_clause 0x2
	scratch_load_b32 v7, off, s27
	scratch_load_b32 v9, off, s24
	scratch_load_b32 v10, off, s0
	s_mov_b32 s24, s25
	s_waitcnt vmcnt(2)
	v_and_b32_e32 v14, v7, v0
	v_xor_b32_e32 v0, v7, v0
	v_xor3_b32 v7, v11, v12, v13
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_or_b32 v0, v9, v0, v14
	s_waitcnt vmcnt(0)
	v_add3_u32 v0, v10, v7, v0
	scratch_store_b32 off, v0, s0
	s_cbranch_scc1 .LBB0_289
; %bb.295:                              ; %_ZL6memcpyPvPKvm.exit.i91.i259.i
                                        ;   in Loop: Header=BB0_288 Depth=3
	s_add_i32 s0, s10, 16
	s_cmp_lt_u32 s10, 48
	s_mov_b32 s10, s0
	s_cbranch_scc1 .LBB0_288
; %bb.296:                              ; %.preheader.i92.i260.i.preheader
                                        ;   in Loop: Header=BB0_232 Depth=2
	s_mov_b32 s0, 0
.LBB0_297:                              ; %.preheader.i92.i260.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_232 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	s_add_i32 s10, s0, 16
	s_add_i32 s11, s17, s0
	scratch_load_b32 v0, off, s10
	scratch_load_b32 v7, off, s11
	s_add_i32 s0, s0, 4
	s_cmp_lg_u32 s0, 32
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v0, v7, v0
	scratch_store_b32 off, v0, s11
	s_cbranch_scc1 .LBB0_297
; %bb.298:                              ; %sha256_compile.exit96.i263.i
                                        ;   in Loop: Header=BB0_232 Depth=2
	v_mov_b32_e32 v9, 0
	v_mov_b32_e32 v10, 0
.LBB0_299:                              ; %Flow898
                                        ;   in Loop: Header=BB0_232 Depth=2
	s_or_b32 exec_lo, exec_lo, s23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v0, 2, v9
	v_sub_co_u32 v9, vcc_lo, 0x42, v9
	v_sub_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_mov_b32 s10, 0
.LBB0_300:                              ; %.lr.ph.i.i.i.i.i116.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_232 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v9, -8
	v_add_co_ci_u32_e32 v12, vcc_lo, -1, v10, vcc_lo
	v_add_nc_u32_e32 v7, 48, v0
	v_add_co_u32 v9, s0, v9, -4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cmp_gt_u64_e32 vcc_lo, 4, v[11:12]
	v_add_nc_u32_e32 v0, 4, v0
	v_add_nc_u32_e32 v13, 40, v7
	v_add_nc_u32_e32 v15, 42, v7
	v_add_co_ci_u32_e64 v10, s0, -1, v10, s0
	v_add_nc_u32_e32 v14, 41, v7
	v_add_nc_u32_e32 v7, 43, v7
	s_or_b32 s10, vcc_lo, s10
	s_clause 0x3
	scratch_store_b8 v13, v1, off
	scratch_store_b8 v14, v1, off
	scratch_store_b8 v15, v1, off
	scratch_store_b8 v7, v1, off
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_300
; %bb.301:                              ; %._crit_edge.i.i.i.i.i119.i
                                        ;   in Loop: Header=BB0_232 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v0, 48, v0
	s_mov_b32 s0, 0
	s_mov_b32 s10, exec_lo
	v_cmpx_lt_i64_e32 5, v[9:10]
	s_xor_b32 s10, exec_lo, s10
	s_cbranch_execz .LBB0_305
; %bb.302:                              ; %NodeBlock853
                                        ;   in Loop: Header=BB0_232 Depth=2
	s_mov_b32 s0, exec_lo
	v_cmpx_lt_i64_e32 6, v[9:10]
	s_cbranch_execz .LBB0_304
; %bb.303:                              ;   in Loop: Header=BB0_232 Depth=2
	v_add_nc_u32_e32 v7, 42, v0
	scratch_store_b8 v7, v1, off
.LBB0_304:                              ;   in Loop: Header=BB0_232 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v7, 41, v0
	s_mov_b32 s0, exec_lo
	scratch_store_b8 v7, v1, off
.LBB0_305:                              ; %Flow894
                                        ;   in Loop: Header=BB0_232 Depth=2
	s_and_not1_saveexec_b32 s10, s10
; %bb.306:                              ; %LeafBlock851
                                        ;   in Loop: Header=BB0_232 Depth=2
	v_cmp_eq_u64_e32 vcc_lo, 5, v[9:10]
	s_and_not1_b32 s0, s0, exec_lo
	s_and_b32 s11, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s0, s0, s11
; %bb.307:                              ; %Flow895
                                        ;   in Loop: Header=BB0_232 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
	s_and_saveexec_b32 s10, s0
	s_cbranch_execz .LBB0_309
; %bb.308:                              ;   in Loop: Header=BB0_232 Depth=2
	v_add_nc_u32_e32 v0, 40, v0
	scratch_store_b8 v0, v1, off
.LBB0_309:                              ; %_ZL6memsetPvim.exit.i.i.i120.i
                                        ;   in Loop: Header=BB0_232 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
	scratch_load_b64 v[9:10], off, off offset:48
	s_movk_i32 s10, 0xffe0
	s_mov_b32 s11, -1
	s_mov_b32 s0, 0
	s_waitcnt vmcnt(0)
	v_alignbit_b32 v10, v10, v9, 29
	v_lshlrev_b32_e32 v11, 3, v9
	scratch_store_b64 off, v[10:11], off offset:144
.LBB0_310:                              ; %.lr.ph.i.i.i59.i121.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_232 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_readfirstlane_b32 s23, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s23, s23, s0
	s_add_i32 s24, s23, 8
	s_add_i32 s25, s23, 9
	s_add_i32 s26, s23, 10
	s_add_i32 s23, s23, 11
	s_clause 0x3
	scratch_load_u8 v0, off, s24
	scratch_load_u8 v7, off, s25
	scratch_load_u8 v9, off, s26
	scratch_load_u8 v10, off, s23
	v_readfirstlane_b32 s23, v26
	s_add_i32 s24, s0, 16
	s_delay_alu instid0(VALU_DEP_1)
	s_add_i32 s23, s23, s0
	s_add_i32 s0, s0, 4
	s_add_i32 s25, s23, 1
	s_add_i32 s26, s23, 2
	s_add_i32 s23, s23, 3
	s_add_u32 s10, s10, 4
	s_addc_u32 s11, s11, 0
	s_waitcnt vmcnt(3)
	scratch_store_b8 off, v0, s24
	s_waitcnt vmcnt(2)
	scratch_store_b8 off, v7, s25
	s_waitcnt vmcnt(1)
	scratch_store_b8 off, v9, s26
	s_waitcnt vmcnt(0)
	scratch_store_b8 off, v10, s23
	s_cmp_lg_u64 s[10:11], 0
	s_cbranch_scc1 .LBB0_310
; %bb.311:                              ; %.preheader14.i65.i126.i.preheader
                                        ;   in Loop: Header=BB0_232 Depth=2
	s_mov_b32 s10, 0
.LBB0_312:                              ; %.preheader14.i65.i126.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_232 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_313 Depth 4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s10, 0
	s_mov_b32 s23, 0
	s_cselect_b32 s11, -1, 0
.LBB0_313:                              ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_232 Depth=2
                                        ;       Parent Loop BB0_312 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_sub_i32 s0, 4, s23
	s_sub_i32 s24, 0, s23
	s_and_b32 s0, s0, 7
	s_and_b32 s24, s24, 7
	s_lshl_b32 s0, s0, 2
	s_lshl_b32 s24, s24, 2
	s_add_i32 s0, s0, 16
	s_add_i32 s24, s24, 16
	s_clause 0x1
	scratch_load_b32 v7, off, s0
	scratch_load_b32 v0, off, s24
	s_and_not1_b32 vcc_lo, exec_lo, s11
	s_cbranch_vccnz .LBB0_315
; %bb.314:                              ;   in Loop: Header=BB0_313 Depth=4
	s_add_i32 s0, s23, 14
	s_add_i32 s24, s23, 1
	s_and_b32 s0, s0, 15
	s_and_b32 s25, s24, 15
	s_lshl_b32 s0, s0, 2
	s_lshl_b32 s25, s25, 2
	s_add_i32 s0, s16, s0
	scratch_load_b32 v9, off, s0
	s_add_i32 s0, s16, s25
	s_add_i32 s25, s23, 9
	scratch_load_b32 v10, off, s0
	s_and_b32 s0, s25, 15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s0, s0, 2
	s_add_i32 s0, s16, s0
	scratch_load_b32 v11, off, s0
	s_lshl_b32 s0, s23, 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s25, s16, s0
	s_mov_b32 s0, 0
	scratch_load_b32 v12, off, s25
	s_waitcnt vmcnt(3)
	v_alignbit_b32 v13, v9, v9, 17
	v_alignbit_b32 v14, v9, v9, 19
	v_lshrrev_b32_e32 v9, 10, v9
	s_waitcnt vmcnt(2)
	v_alignbit_b32 v15, v10, v10, 7
	v_alignbit_b32 v16, v10, v10, 18
	v_lshrrev_b32_e32 v10, 3, v10
	v_xor_b32_e32 v13, v13, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor3_b32 v10, v15, v16, v10
	s_waitcnt vmcnt(1)
	v_xad_u32 v9, v13, v9, v11
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v9, v9, v12, v10
	scratch_store_b32 off, v9, s25
	s_branch .LBB0_316
.LBB0_315:                              ;   in Loop: Header=BB0_313 Depth=4
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $sgpr24
.LBB0_316:                              ; %Flow893
                                        ;   in Loop: Header=BB0_313 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_318
; %bb.317:                              ;   in Loop: Header=BB0_313 Depth=4
	s_lshl_b32 s0, s23, 2
	s_add_i32 s24, s23, 1
	s_add_i32 s0, s16, s0
	scratch_load_b32 v9, off, s0
.LBB0_318:                              ; %m_cycle.exit.i69.i130.i
                                        ;   in Loop: Header=BB0_313 Depth=4
	s_getpc_b64 s[26:27]
	s_add_u32 s26, s26, _ZL4k256@rel32@lo+4
	s_addc_u32 s27, s27, _ZL4k256@rel32@hi+12
	s_or_b32 s0, s23, s10
	s_waitcnt vmcnt(1)
	v_alignbit_b32 v13, v7, v7, 6
	s_lshl_b64 s[28:29], s[0:1], 2
	v_alignbit_b32 v14, v7, v7, 11
	s_add_u32 s26, s28, s26
	s_addc_u32 s27, s29, s27
	s_sub_i32 s0, 6, s23
	s_sub_i32 s25, 5, s23
	s_and_b32 s0, s0, 7
	s_and_b32 s25, s25, 7
	s_lshl_b32 s0, s0, 2
	s_sub_i32 s28, 7, s23
	s_lshl_b32 s25, s25, 2
	s_add_i32 s0, s0, 16
	s_add_i32 s25, s25, 16
	s_and_b32 s28, s28, 7
	s_clause 0x1
	scratch_load_b32 v10, off, s0
	scratch_load_b32 v11, off, s25
	s_lshl_b32 s0, s28, 2
	s_load_b32 s25, s[26:27], 0x0
	s_add_i32 s0, s0, 16
	v_alignbit_b32 v15, v7, v7, 25
	scratch_load_b32 v12, off, s0
	s_sub_i32 s26, 1, s23
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s26, s26, 7
	v_xor3_b32 v13, v13, v14, v15
	s_lshl_b32 s26, s26, 2
	s_add_i32 s26, s26, 16
	s_waitcnt vmcnt(3) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v9, v9, v13, s25
	s_sub_i32 s25, 3, s23
	s_sub_i32 s23, 2, s23
	s_and_b32 s25, s25, 7
	s_and_b32 s23, s23, 7
	s_lshl_b32 s25, s25, 2
	s_lshl_b32 s23, s23, 2
	s_add_i32 s25, s25, 16
	s_add_i32 s23, s23, 16
	v_alignbit_b32 v13, v0, v0, 22
	s_cmp_lg_u32 s24, 16
	s_waitcnt vmcnt(1)
	v_bfi_b32 v7, v7, v11, v10
	v_alignbit_b32 v11, v0, v0, 2
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2)
	v_add3_u32 v7, v9, v12, v7
	v_alignbit_b32 v12, v0, v0, 13
	scratch_store_b32 off, v7, s0
	scratch_load_b32 v9, off, s25
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v7, v7, v9
	scratch_store_b32 off, v7, s25
	s_clause 0x2
	scratch_load_b32 v7, off, s26
	scratch_load_b32 v9, off, s23
	scratch_load_b32 v10, off, s0
	s_mov_b32 s23, s24
	s_waitcnt vmcnt(2)
	v_and_b32_e32 v14, v7, v0
	v_xor_b32_e32 v0, v7, v0
	v_xor3_b32 v7, v11, v12, v13
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_or_b32 v0, v9, v0, v14
	s_waitcnt vmcnt(0)
	v_add3_u32 v0, v10, v7, v0
	scratch_store_b32 off, v0, s0
	s_cbranch_scc1 .LBB0_313
; %bb.319:                              ; %_ZL6memcpyPvPKvm.exit.i72.i133.i
                                        ;   in Loop: Header=BB0_312 Depth=3
	s_add_i32 s0, s10, 16
	s_cmp_lt_u32 s10, 48
	s_mov_b32 s10, s0
	s_cbranch_scc1 .LBB0_312
; %bb.320:                              ; %.preheader.i73.i134.i.preheader
                                        ;   in Loop: Header=BB0_232 Depth=2
	s_mov_b32 s0, 0
.LBB0_321:                              ; %.preheader.i73.i134.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_232 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e64 v0, s0, 48
	s_add_i32 s10, s0, 16
	s_add_i32 s0, s0, 4
	s_cmp_lg_u32 s0, 32
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v0, 8, v0
	scratch_load_b32 v7, off, s10
	scratch_load_b32 v9, v0, off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v7, v9, v7
	scratch_store_b32 v0, v7, off
	s_cbranch_scc1 .LBB0_321
; %bb.322:                              ; %sha256_compile.exit77.i137.i
                                        ;   in Loop: Header=BB0_232 Depth=2
	s_mov_b32 s0, 0
	s_mov_b32 s10, 0
.LBB0_323:                              ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_232 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s11, s10, -4
	s_add_i32 s23, s10, 0x100
	v_add_nc_u32_e64 v0, s11, 48
	s_and_not1_b32 s11, 24, s0
	s_add_i32 s10, s10, 1
	s_add_i32 s0, s0, 8
	s_cmp_lg_u32 s10, 32
	v_add_nc_u32_e32 v0, 8, v0
	scratch_load_b32 v0, v0, off
	s_waitcnt vmcnt(0)
	v_lshrrev_b32_e32 v0, s11, v0
	scratch_store_b8 off, v0, s23
	s_cbranch_scc1 .LBB0_323
; %bb.324:                              ; %.lr.ph.i.i4.i140.i.preheader
                                        ;   in Loop: Header=BB0_232 Depth=2
	s_movk_i32 s10, 0xff98
	s_mov_b32 s11, -1
	s_mov_b32 s0, 0
.LBB0_325:                              ; %.lr.ph.i.i4.i140.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_232 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_readfirstlane_b32 s23, v27
	s_add_i32 s24, s0, 0x98
	scratch_load_u8 v0, off, s24
	s_add_i32 s23, s23, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s24, s23, 1
	s_add_i32 s25, s23, 2
	s_add_i32 s23, s23, 3
	s_clause 0x2
	scratch_load_u8 v7, off, s24
	scratch_load_u8 v9, off, s25
	scratch_load_u8 v10, off, s23
	v_readfirstlane_b32 s23, v21
	s_add_i32 s24, s0, 48
	s_delay_alu instid0(VALU_DEP_1)
	s_add_i32 s23, s23, s0
	s_add_i32 s0, s0, 4
	s_add_i32 s25, s23, 1
	s_add_i32 s26, s23, 2
	s_add_i32 s23, s23, 3
	s_add_u32 s10, s10, 4
	s_addc_u32 s11, s11, 0
	s_waitcnt vmcnt(3)
	scratch_store_b8 off, v0, s24
	s_waitcnt vmcnt(2)
	scratch_store_b8 off, v7, s25
	s_waitcnt vmcnt(1)
	scratch_store_b8 off, v9, s26
	s_waitcnt vmcnt(0)
	scratch_store_b8 off, v10, s23
	s_cmp_lg_u64 s[10:11], 0
	s_cbranch_scc1 .LBB0_325
; %bb.326:                              ; %_ZL6memcpyPvPKvm.exit.i145.i
                                        ;   in Loop: Header=BB0_232 Depth=2
	scratch_load_b32 v0, off, off offset:48
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v7, 32, v0
	scratch_store_b32 off, v7, off offset:48
	v_cmpx_lt_u32_e32 0xffffffdf, v0
	s_cbranch_execz .LBB0_328
; %bb.327:                              ;   in Loop: Header=BB0_232 Depth=2
	scratch_load_b32 v7, off, off offset:52
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v7, 1, v7
	scratch_store_b32 off, v7, off offset:52
.LBB0_328:                              ;   in Loop: Header=BB0_232 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	v_mov_b32_e32 v9, 32
	v_dual_mov_b32 v10, 0 :: v_dual_and_b32 v13, 63, v0
	v_mov_b32_e32 v7, 0x100
	s_mov_b32 s23, exec_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_lt_u32_e32 31, v13
	s_cbranch_execz .LBB0_359
; %bb.329:                              ; %.lr.ph.i7.preheader.i147.i
                                        ;   in Loop: Header=BB0_232 Depth=2
	v_sub_nc_u32_e32 v0, 64, v13
	v_dual_mov_b32 v9, 32 :: v_dual_mov_b32 v12, v1
	v_dual_mov_b32 v7, 0x100 :: v_dual_mov_b32 v10, 0
	s_delay_alu instid0(VALU_DEP_3)
	v_mov_b32_e32 v11, v0
	s_mov_b32 s24, 0
.LBB0_330:                              ; %.lr.ph.i7.i148.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_232 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_332 Depth 4
                                        ;         Child Loop BB0_343 Depth 4
                                        ;         Child Loop BB0_345 Depth 4
                                        ;         Child Loop BB0_347 Depth 4
                                        ;           Child Loop BB0_348 Depth 5
                                        ;         Child Loop BB0_356 Depth 4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v15, v7 :: v_dual_add_nc_u32 v0, s16, v13
	v_dual_mov_b32 v14, v12 :: v_dual_mov_b32 v13, v11
	s_mov_b32 s0, exec_lo
	v_cmpx_lt_u64_e32 3, v[11:12]
	s_cbranch_execz .LBB0_334
; %bb.331:                              ; %.lr.ph.i.i.i32.i242.i.preheader
                                        ;   in Loop: Header=BB0_330 Depth=3
	v_dual_mov_b32 v15, v7 :: v_dual_mov_b32 v14, v12
	v_mov_b32_e32 v13, v11
	s_mov_b32 s10, 0
.LBB0_332:                              ; %.lr.ph.i.i.i32.i242.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_232 Depth=2
                                        ;       Parent Loop BB0_330 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_clause 0x3
	scratch_load_u8 v16, v15, off
	scratch_load_u8 v28, v15, off offset:1
	scratch_load_u8 v29, v15, off offset:2
	scratch_load_u8 v30, v15, off offset:3
	v_add_co_u32 v13, vcc_lo, v13, -4
	v_add_co_ci_u32_e32 v14, vcc_lo, -1, v14, vcc_lo
	v_add_nc_u32_e32 v15, 4, v15
	s_waitcnt vmcnt(3)
	scratch_store_b8 v0, v16, off
	s_waitcnt vmcnt(2)
	scratch_store_b8 v0, v28, off offset:1
	s_waitcnt vmcnt(1)
	scratch_store_b8 v0, v29, off offset:2
	s_waitcnt vmcnt(0)
	scratch_store_b8 v0, v30, off offset:3
	v_cmp_gt_u64_e32 vcc_lo, 4, v[13:14]
	v_add_nc_u32_e32 v0, 4, v0
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_332
; %bb.333:                              ; %Flow889
                                        ;   in Loop: Header=BB0_330 Depth=3
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_334:                              ; %Flow890
                                        ;   in Loop: Header=BB0_330 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s0, 0
	s_mov_b32 s10, exec_lo
	v_cmpx_lt_i64_e32 1, v[13:14]
	s_xor_b32 s10, exec_lo, s10
	s_cbranch_execz .LBB0_338
; %bb.335:                              ; %NodeBlock859
                                        ;   in Loop: Header=BB0_330 Depth=3
	s_mov_b32 s0, exec_lo
	v_cmpx_lt_i64_e32 2, v[13:14]
	s_cbranch_execz .LBB0_337
; %bb.336:                              ;   in Loop: Header=BB0_330 Depth=3
	scratch_load_u8 v13, v15, off offset:2
	s_waitcnt vmcnt(0)
	scratch_store_b8 v0, v13, off offset:2
.LBB0_337:                              ;   in Loop: Header=BB0_330 Depth=3
	s_or_b32 exec_lo, exec_lo, s0
	scratch_load_u8 v13, v15, off offset:1
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	scratch_store_b8 v0, v13, off offset:1
                                        ; implicit-def: $vgpr13_vgpr14
.LBB0_338:                              ; %Flow887
                                        ;   in Loop: Header=BB0_330 Depth=3
	s_and_not1_saveexec_b32 s10, s10
; %bb.339:                              ; %LeafBlock857
                                        ;   in Loop: Header=BB0_330 Depth=3
	v_cmp_eq_u64_e32 vcc_lo, 1, v[13:14]
	s_and_not1_b32 s0, s0, exec_lo
	s_and_b32 s11, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s0, s0, s11
; %bb.340:                              ; %Flow888
                                        ;   in Loop: Header=BB0_330 Depth=3
	s_or_b32 exec_lo, exec_lo, s10
	s_and_saveexec_b32 s10, s0
	s_cbranch_execz .LBB0_342
; %bb.341:                              ;   in Loop: Header=BB0_330 Depth=3
	scratch_load_u8 v13, v15, off
	s_waitcnt vmcnt(0)
	scratch_store_b8 v0, v13, off
.LBB0_342:                              ; %_ZL6memcpyPvPKvm.exit.i16.i157.i.preheader
                                        ;   in Loop: Header=BB0_330 Depth=3
	s_or_b32 exec_lo, exec_lo, s10
	s_movk_i32 s0, 0x64
.LBB0_343:                              ; %_ZL6memcpyPvPKvm.exit.i16.i157.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_232 Depth=2
                                        ;       Parent Loop BB0_330 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s10, s0, 48
	s_add_i32 s0, s0, -4
	scratch_load_b32 v0, off, s10
	s_cmp_lg_u32 s0, 36
	s_waitcnt vmcnt(0)
	v_perm_b32 v0, 0, v0, 0x10203
	scratch_store_b32 off, v0, s10
	s_cbranch_scc1 .LBB0_343
; %bb.344:                              ;   in Loop: Header=BB0_330 Depth=3
	s_movk_i32 s10, 0xffe0
	s_mov_b32 s11, -1
	s_mov_b32 s0, 0
.LBB0_345:                              ; %.lr.ph.i.i.i97.i160.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_232 Depth=2
                                        ;       Parent Loop BB0_330 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s25, s17, s0
	s_add_i32 s26, s25, 1
	s_add_i32 s27, s25, 2
	s_add_i32 s28, s25, 3
	s_clause 0x3
	scratch_load_u8 v0, off, s25
	scratch_load_u8 v13, off, s26
	scratch_load_u8 v14, off, s27
	scratch_load_u8 v15, off, s28
	v_readfirstlane_b32 s25, v26
	s_add_i32 s26, s0, 16
	s_delay_alu instid0(VALU_DEP_1)
	s_add_i32 s25, s25, s0
	s_add_i32 s0, s0, 4
	s_add_i32 s27, s25, 1
	s_add_i32 s28, s25, 2
	s_add_i32 s25, s25, 3
	s_add_u32 s10, s10, 4
	s_addc_u32 s11, s11, 0
	s_waitcnt vmcnt(3)
	scratch_store_b8 off, v0, s26
	s_waitcnt vmcnt(2)
	scratch_store_b8 off, v13, s27
	s_waitcnt vmcnt(1)
	scratch_store_b8 off, v14, s28
	s_waitcnt vmcnt(0)
	scratch_store_b8 off, v15, s25
	s_cmp_lg_u64 s[10:11], 0
	s_cbranch_scc1 .LBB0_345
; %bb.346:                              ; %.preheader14.i103.i165.i.preheader
                                        ;   in Loop: Header=BB0_330 Depth=3
	s_mov_b32 s10, 0
.LBB0_347:                              ; %.preheader14.i103.i165.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_232 Depth=2
                                        ;       Parent Loop BB0_330 Depth=3
                                        ; =>      This Loop Header: Depth=4
                                        ;           Child Loop BB0_348 Depth 5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s10, 0
	s_mov_b32 s25, 0
	s_cselect_b32 s11, -1, 0
.LBB0_348:                              ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_232 Depth=2
                                        ;       Parent Loop BB0_330 Depth=3
                                        ;         Parent Loop BB0_347 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_sub_i32 s0, 4, s25
	s_sub_i32 s26, 0, s25
	s_and_b32 s0, s0, 7
	s_and_b32 s26, s26, 7
	s_lshl_b32 s0, s0, 2
	s_lshl_b32 s26, s26, 2
	s_add_i32 s0, s0, 16
	s_add_i32 s26, s26, 16
	s_clause 0x1
	scratch_load_b32 v13, off, s0
	scratch_load_b32 v0, off, s26
	s_and_not1_b32 vcc_lo, exec_lo, s11
	s_cbranch_vccnz .LBB0_350
; %bb.349:                              ;   in Loop: Header=BB0_348 Depth=5
	s_add_i32 s0, s25, 14
	s_add_i32 s26, s25, 1
	s_and_b32 s0, s0, 15
	s_and_b32 s27, s26, 15
	s_lshl_b32 s0, s0, 2
	s_lshl_b32 s27, s27, 2
	s_add_i32 s0, s16, s0
	scratch_load_b32 v14, off, s0
	s_add_i32 s0, s16, s27
	s_add_i32 s27, s25, 9
	scratch_load_b32 v15, off, s0
	s_and_b32 s0, s27, 15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s0, s0, 2
	s_add_i32 s0, s16, s0
	scratch_load_b32 v16, off, s0
	s_lshl_b32 s0, s25, 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s27, s16, s0
	s_mov_b32 s0, 0
	scratch_load_b32 v28, off, s27
	s_waitcnt vmcnt(3)
	v_alignbit_b32 v29, v14, v14, 17
	v_alignbit_b32 v30, v14, v14, 19
	v_lshrrev_b32_e32 v14, 10, v14
	s_waitcnt vmcnt(2)
	v_alignbit_b32 v31, v15, v15, 7
	v_alignbit_b32 v32, v15, v15, 18
	v_lshrrev_b32_e32 v15, 3, v15
	v_xor_b32_e32 v29, v29, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor3_b32 v15, v31, v32, v15
	s_waitcnt vmcnt(1)
	v_xad_u32 v14, v29, v14, v16
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v14, v14, v28, v15
	scratch_store_b32 off, v14, s27
	s_branch .LBB0_351
.LBB0_350:                              ;   in Loop: Header=BB0_348 Depth=5
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr14
                                        ; implicit-def: $sgpr26
.LBB0_351:                              ; %Flow886
                                        ;   in Loop: Header=BB0_348 Depth=5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_353
; %bb.352:                              ;   in Loop: Header=BB0_348 Depth=5
	s_lshl_b32 s0, s25, 2
	s_add_i32 s26, s25, 1
	s_add_i32 s0, s16, s0
	scratch_load_b32 v14, off, s0
.LBB0_353:                              ; %m_cycle.exit.i107.i169.i
                                        ;   in Loop: Header=BB0_348 Depth=5
	s_getpc_b64 s[28:29]
	s_add_u32 s28, s28, _ZL4k256@rel32@lo+4
	s_addc_u32 s29, s29, _ZL4k256@rel32@hi+12
	s_or_b32 s0, s25, s10
	s_waitcnt vmcnt(1)
	v_alignbit_b32 v29, v13, v13, 6
	s_lshl_b64 s[30:31], s[0:1], 2
	v_alignbit_b32 v30, v13, v13, 11
	s_add_u32 s28, s30, s28
	s_addc_u32 s29, s31, s29
	s_sub_i32 s0, 6, s25
	s_sub_i32 s27, 5, s25
	s_and_b32 s0, s0, 7
	s_and_b32 s27, s27, 7
	s_lshl_b32 s0, s0, 2
	s_sub_i32 s30, 7, s25
	s_lshl_b32 s27, s27, 2
	s_add_i32 s0, s0, 16
	s_add_i32 s27, s27, 16
	s_and_b32 s30, s30, 7
	s_clause 0x1
	scratch_load_b32 v15, off, s0
	scratch_load_b32 v16, off, s27
	s_lshl_b32 s0, s30, 2
	s_load_b32 s27, s[28:29], 0x0
	s_add_i32 s0, s0, 16
	v_alignbit_b32 v31, v13, v13, 25
	scratch_load_b32 v28, off, s0
	s_sub_i32 s28, 1, s25
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s28, s28, 7
	v_xor3_b32 v29, v29, v30, v31
	s_lshl_b32 s28, s28, 2
	s_add_i32 s28, s28, 16
	s_waitcnt vmcnt(3) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v14, v14, v29, s27
	s_sub_i32 s27, 3, s25
	s_sub_i32 s25, 2, s25
	s_and_b32 s27, s27, 7
	s_and_b32 s25, s25, 7
	s_lshl_b32 s27, s27, 2
	s_lshl_b32 s25, s25, 2
	s_add_i32 s27, s27, 16
	s_add_i32 s25, s25, 16
	v_alignbit_b32 v29, v0, v0, 22
	s_cmp_lg_u32 s26, 16
	s_waitcnt vmcnt(1)
	v_bfi_b32 v13, v13, v16, v15
	v_alignbit_b32 v16, v0, v0, 2
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2)
	v_add3_u32 v13, v14, v28, v13
	v_alignbit_b32 v28, v0, v0, 13
	scratch_store_b32 off, v13, s0
	scratch_load_b32 v14, off, s27
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v13, v13, v14
	scratch_store_b32 off, v13, s27
	s_clause 0x2
	scratch_load_b32 v13, off, s28
	scratch_load_b32 v14, off, s25
	scratch_load_b32 v15, off, s0
	s_mov_b32 s25, s26
	s_waitcnt vmcnt(2)
	v_and_b32_e32 v30, v13, v0
	v_xor_b32_e32 v0, v13, v0
	v_xor3_b32 v13, v16, v28, v29
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_or_b32 v0, v14, v0, v30
	s_waitcnt vmcnt(0)
	v_add3_u32 v0, v15, v13, v0
	scratch_store_b32 off, v0, s0
	s_cbranch_scc1 .LBB0_348
; %bb.354:                              ; %_ZL6memcpyPvPKvm.exit.i110.i172.i
                                        ;   in Loop: Header=BB0_347 Depth=4
	s_add_i32 s0, s10, 16
	s_cmp_lt_u32 s10, 48
	s_mov_b32 s10, s0
	s_cbranch_scc1 .LBB0_347
; %bb.355:                              ; %.preheader.i111.i173.i.preheader
                                        ;   in Loop: Header=BB0_330 Depth=3
	s_mov_b32 s0, 0
.LBB0_356:                              ; %.preheader.i111.i173.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_232 Depth=2
                                        ;       Parent Loop BB0_330 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	s_add_i32 s10, s0, 16
	s_add_i32 s11, s17, s0
	scratch_load_b32 v0, off, s10
	scratch_load_b32 v13, off, s11
	s_add_i32 s0, s0, 4
	s_cmp_lg_u32 s0, 32
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v0, v13, v0
	scratch_store_b32 off, v0, s11
	s_cbranch_scc1 .LBB0_356
; %bb.357:                              ; %sha256_compile.exit115.i176.i
                                        ;   in Loop: Header=BB0_330 Depth=3
	v_sub_co_u32 v9, vcc_lo, v9, v11
	v_sub_co_ci_u32_e32 v10, vcc_lo, v10, v12, vcc_lo
	v_add_nc_u32_e32 v7, v7, v11
	v_mov_b32_e32 v11, 64
	v_mov_b32_e32 v12, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_cmp_gt_u64_e32 vcc_lo, 64, v[9:10]
	v_mov_b32_e32 v13, 0
	s_or_b32 s24, vcc_lo, s24
	s_and_not1_b32 exec_lo, exec_lo, s24
	s_cbranch_execnz .LBB0_330
; %bb.358:                              ; %Flow891
                                        ;   in Loop: Header=BB0_232 Depth=2
	s_or_b32 exec_lo, exec_lo, s24
	v_mov_b32_e32 v13, 0
.LBB0_359:                              ; %Flow892
                                        ;   in Loop: Header=BB0_232 Depth=2
	s_or_b32 exec_lo, exec_lo, s23
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v0, s16, v13
	s_mov_b32 s0, exec_lo
	v_cmpx_lt_u64_e32 3, v[9:10]
	s_cbranch_execz .LBB0_363
; %bb.360:                              ; %.lr.ph.i.i38.i28.i237.i.preheader
                                        ;   in Loop: Header=BB0_232 Depth=2
	s_mov_b32 s10, 0
.LBB0_361:                              ; %.lr.ph.i.i38.i28.i237.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_232 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_clause 0x3
	scratch_load_u8 v11, v7, off
	scratch_load_u8 v12, v7, off offset:1
	scratch_load_u8 v13, v7, off offset:2
	scratch_load_u8 v14, v7, off offset:3
	v_add_co_u32 v9, vcc_lo, v9, -4
	v_add_co_ci_u32_e32 v10, vcc_lo, -1, v10, vcc_lo
	v_add_nc_u32_e32 v7, 4, v7
	s_waitcnt vmcnt(3)
	scratch_store_b8 v0, v11, off
	s_waitcnt vmcnt(2)
	scratch_store_b8 v0, v12, off offset:1
	s_waitcnt vmcnt(1)
	scratch_store_b8 v0, v13, off offset:2
	s_waitcnt vmcnt(0)
	scratch_store_b8 v0, v14, off offset:3
	v_cmp_gt_u64_e32 vcc_lo, 4, v[9:10]
	v_add_nc_u32_e32 v0, 4, v0
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_361
; %bb.362:                              ; %Flow884
                                        ;   in Loop: Header=BB0_232 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_363:                              ; %Flow885
                                        ;   in Loop: Header=BB0_232 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s0, 0
	s_mov_b32 s10, exec_lo
	v_cmpx_lt_i64_e32 1, v[9:10]
	s_xor_b32 s10, exec_lo, s10
	s_cbranch_execz .LBB0_367
; %bb.364:                              ; %NodeBlock865
                                        ;   in Loop: Header=BB0_232 Depth=2
	s_mov_b32 s0, exec_lo
	v_cmpx_lt_i64_e32 2, v[9:10]
	s_cbranch_execz .LBB0_366
; %bb.365:                              ;   in Loop: Header=BB0_232 Depth=2
	scratch_load_u8 v9, v7, off offset:2
	s_waitcnt vmcnt(0)
	scratch_store_b8 v0, v9, off offset:2
.LBB0_366:                              ;   in Loop: Header=BB0_232 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	scratch_load_u8 v9, v7, off offset:1
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	scratch_store_b8 v0, v9, off offset:1
                                        ; implicit-def: $vgpr9_vgpr10
.LBB0_367:                              ; %Flow882
                                        ;   in Loop: Header=BB0_232 Depth=2
	s_and_not1_saveexec_b32 s10, s10
; %bb.368:                              ; %LeafBlock863
                                        ;   in Loop: Header=BB0_232 Depth=2
	v_cmp_eq_u64_e32 vcc_lo, 1, v[9:10]
	s_and_not1_b32 s0, s0, exec_lo
	s_and_b32 s11, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s0, s0, s11
; %bb.369:                              ; %Flow883
                                        ;   in Loop: Header=BB0_232 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
	s_and_saveexec_b32 s10, s0
	s_cbranch_execz .LBB0_371
; %bb.370:                              ;   in Loop: Header=BB0_232 Depth=2
	scratch_load_u8 v7, v7, off
	s_waitcnt vmcnt(0)
	scratch_store_b8 v0, v7, off
.LBB0_371:                              ; %sha256_hash.exit36.i186.i
                                        ;   in Loop: Header=BB0_232 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
	scratch_load_b32 v7, off, off offset:48
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v0, 63, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ne_u32_e32 0, v0
	s_cbranch_execz .LBB0_374
; %bb.372:                              ; %.lr.ph.i.i38.i188.i
                                        ;   in Loop: Header=BB0_232 Depth=2
	v_add_nc_u32_e32 v9, 3, v0
	s_mov_b32 s10, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_and_b32_e32 v9, 0x7c, v9
.LBB0_373:                              ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_232 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v10, v22, v9
	v_add_nc_u32_e32 v9, -4, v9
	scratch_load_b32 v11, v10, off
	v_cmp_eq_u32_e32 vcc_lo, 0, v9
	s_or_b32 s10, vcc_lo, s10
	s_waitcnt vmcnt(0)
	v_perm_b32 v11, 0, v11, 0x10203
	scratch_store_b32 v10, v11, off
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_373
.LBB0_374:                              ; %Flow881
                                        ;   in Loop: Header=BB0_232 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	v_and_b32_e32 v9, 60, v0
	v_not_b32_e32 v7, v7
	s_mov_b32 s0, exec_lo
	scratch_load_b32 v10, v9, off offset:88
	v_lshlrev_b32_e32 v7, 3, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e64 v11, v7, 0xffffff80
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v10, v10, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_or_b32 v7, 0x80, v7, v10
	scratch_store_b32 v9, v7, off offset:88
                                        ; implicit-def: $vgpr9_vgpr10
	v_cmpx_gt_u32_e32 56, v0
	s_xor_b32 s0, exec_lo, s0
; %bb.375:                              ;   in Loop: Header=BB0_232 Depth=2
	v_lshrrev_b32_e32 v0, 2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, 1, v0
	v_dual_mov_b32 v10, v1 :: v_dual_mov_b32 v9, v0
                                        ; implicit-def: $vgpr0
; %bb.376:                              ; %Flow878
                                        ;   in Loop: Header=BB0_232 Depth=2
	s_and_not1_saveexec_b32 s23, s0
	s_cbranch_execz .LBB0_393
; %bb.377:                              ;   in Loop: Header=BB0_232 Depth=2
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 60, v0
	s_cbranch_execz .LBB0_379
; %bb.378:                              ;   in Loop: Header=BB0_232 Depth=2
	scratch_store_b32 off, v1, off offset:148
.LBB0_379:                              ;   in Loop: Header=BB0_232 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	s_movk_i32 s10, 0xffe0
	s_mov_b32 s11, -1
	s_mov_b32 s0, 0
.LBB0_380:                              ; %.lr.ph.i.i.i135.i219.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_232 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s24, s17, s0
	s_add_i32 s25, s24, 1
	s_add_i32 s26, s24, 2
	s_add_i32 s27, s24, 3
	s_clause 0x3
	scratch_load_u8 v0, off, s24
	scratch_load_u8 v7, off, s25
	scratch_load_u8 v9, off, s26
	scratch_load_u8 v10, off, s27
	v_readfirstlane_b32 s24, v26
	s_add_i32 s25, s0, 16
	s_delay_alu instid0(VALU_DEP_1)
	s_add_i32 s24, s24, s0
	s_add_i32 s0, s0, 4
	s_add_i32 s26, s24, 1
	s_add_i32 s27, s24, 2
	s_add_i32 s24, s24, 3
	s_add_u32 s10, s10, 4
	s_addc_u32 s11, s11, 0
	s_waitcnt vmcnt(3)
	scratch_store_b8 off, v0, s25
	s_waitcnt vmcnt(2)
	scratch_store_b8 off, v7, s26
	s_waitcnt vmcnt(1)
	scratch_store_b8 off, v9, s27
	s_waitcnt vmcnt(0)
	scratch_store_b8 off, v10, s24
	s_cmp_lg_u64 s[10:11], 0
	s_cbranch_scc1 .LBB0_380
; %bb.381:                              ; %.preheader14.i141.i224.i.preheader
                                        ;   in Loop: Header=BB0_232 Depth=2
	s_mov_b32 s10, 0
.LBB0_382:                              ; %.preheader14.i141.i224.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_232 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_383 Depth 4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s10, 0
	s_mov_b32 s24, 0
	s_cselect_b32 s11, -1, 0
.LBB0_383:                              ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_232 Depth=2
                                        ;       Parent Loop BB0_382 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_sub_i32 s0, 4, s24
	s_sub_i32 s25, 0, s24
	s_and_b32 s0, s0, 7
	s_and_b32 s25, s25, 7
	s_lshl_b32 s0, s0, 2
	s_lshl_b32 s25, s25, 2
	s_add_i32 s0, s0, 16
	s_add_i32 s25, s25, 16
	s_clause 0x1
	scratch_load_b32 v7, off, s0
	scratch_load_b32 v0, off, s25
	s_and_not1_b32 vcc_lo, exec_lo, s11
	s_cbranch_vccnz .LBB0_385
; %bb.384:                              ;   in Loop: Header=BB0_383 Depth=4
	s_add_i32 s0, s24, 14
	s_add_i32 s25, s24, 1
	s_and_b32 s0, s0, 15
	s_and_b32 s26, s25, 15
	s_lshl_b32 s0, s0, 2
	s_lshl_b32 s26, s26, 2
	s_add_i32 s0, s16, s0
	scratch_load_b32 v9, off, s0
	s_add_i32 s0, s16, s26
	s_add_i32 s26, s24, 9
	scratch_load_b32 v10, off, s0
	s_and_b32 s0, s26, 15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s0, s0, 2
	s_add_i32 s0, s16, s0
	scratch_load_b32 v11, off, s0
	s_lshl_b32 s0, s24, 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s26, s16, s0
	s_mov_b32 s0, 0
	scratch_load_b32 v12, off, s26
	s_waitcnt vmcnt(3)
	v_alignbit_b32 v13, v9, v9, 17
	v_alignbit_b32 v14, v9, v9, 19
	v_lshrrev_b32_e32 v9, 10, v9
	s_waitcnt vmcnt(2)
	v_alignbit_b32 v15, v10, v10, 7
	v_alignbit_b32 v16, v10, v10, 18
	v_lshrrev_b32_e32 v10, 3, v10
	v_xor_b32_e32 v13, v13, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor3_b32 v10, v15, v16, v10
	s_waitcnt vmcnt(1)
	v_xad_u32 v9, v13, v9, v11
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v9, v9, v12, v10
	scratch_store_b32 off, v9, s26
	s_branch .LBB0_386
.LBB0_385:                              ;   in Loop: Header=BB0_383 Depth=4
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $sgpr25
.LBB0_386:                              ; %Flow877
                                        ;   in Loop: Header=BB0_383 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_388
; %bb.387:                              ;   in Loop: Header=BB0_383 Depth=4
	s_lshl_b32 s0, s24, 2
	s_add_i32 s25, s24, 1
	s_add_i32 s0, s16, s0
	scratch_load_b32 v9, off, s0
.LBB0_388:                              ; %m_cycle.exit.i145.i228.i
                                        ;   in Loop: Header=BB0_383 Depth=4
	s_getpc_b64 s[26:27]
	s_add_u32 s26, s26, _ZL4k256@rel32@lo+4
	s_addc_u32 s27, s27, _ZL4k256@rel32@hi+12
	s_or_b32 s0, s24, s10
	s_waitcnt vmcnt(1)
	v_alignbit_b32 v13, v7, v7, 6
	s_lshl_b64 s[28:29], s[0:1], 2
	v_alignbit_b32 v14, v7, v7, 11
	s_add_u32 s26, s28, s26
	s_addc_u32 s27, s29, s27
	s_sub_i32 s0, 6, s24
	s_sub_i32 s28, 5, s24
	s_and_b32 s0, s0, 7
	s_and_b32 s28, s28, 7
	s_lshl_b32 s0, s0, 2
	s_sub_i32 s29, 7, s24
	s_lshl_b32 s28, s28, 2
	s_add_i32 s0, s0, 16
	s_add_i32 s28, s28, 16
	s_and_b32 s29, s29, 7
	s_clause 0x1
	scratch_load_b32 v10, off, s0
	scratch_load_b32 v11, off, s28
	s_lshl_b32 s0, s29, 2
	s_load_b32 s26, s[26:27], 0x0
	s_add_i32 s0, s0, 16
	v_alignbit_b32 v15, v7, v7, 25
	scratch_load_b32 v12, off, s0
	s_sub_i32 s27, 1, s24
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s27, s27, 7
	v_xor3_b32 v13, v13, v14, v15
	s_lshl_b32 s27, s27, 2
	s_add_i32 s27, s27, 16
	s_waitcnt vmcnt(3) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v9, v9, v13, s26
	s_sub_i32 s26, 3, s24
	s_sub_i32 s24, 2, s24
	s_and_b32 s26, s26, 7
	s_and_b32 s24, s24, 7
	s_lshl_b32 s26, s26, 2
	s_lshl_b32 s24, s24, 2
	s_add_i32 s26, s26, 16
	s_add_i32 s24, s24, 16
	v_alignbit_b32 v13, v0, v0, 22
	s_cmp_lg_u32 s25, 16
	s_waitcnt vmcnt(1)
	v_bfi_b32 v7, v7, v11, v10
	v_alignbit_b32 v11, v0, v0, 2
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2)
	v_add3_u32 v7, v9, v12, v7
	v_alignbit_b32 v12, v0, v0, 13
	scratch_store_b32 off, v7, s0
	scratch_load_b32 v9, off, s26
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v7, v7, v9
	scratch_store_b32 off, v7, s26
	s_clause 0x2
	scratch_load_b32 v7, off, s27
	scratch_load_b32 v9, off, s24
	scratch_load_b32 v10, off, s0
	s_mov_b32 s24, s25
	s_waitcnt vmcnt(2)
	v_and_b32_e32 v14, v7, v0
	v_xor_b32_e32 v0, v7, v0
	v_xor3_b32 v7, v11, v12, v13
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_or_b32 v0, v9, v0, v14
	s_waitcnt vmcnt(0)
	v_add3_u32 v0, v10, v7, v0
	scratch_store_b32 off, v0, s0
	s_cbranch_scc1 .LBB0_383
; %bb.389:                              ; %_ZL6memcpyPvPKvm.exit.i148.i231.i
                                        ;   in Loop: Header=BB0_382 Depth=3
	s_add_i32 s0, s10, 16
	s_cmp_lt_u32 s10, 48
	s_mov_b32 s10, s0
	s_cbranch_scc1 .LBB0_382
; %bb.390:                              ; %.preheader.i149.i232.i.preheader
                                        ;   in Loop: Header=BB0_232 Depth=2
	s_mov_b32 s0, 0
.LBB0_391:                              ; %.preheader.i149.i232.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_232 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	s_add_i32 s10, s0, 16
	s_add_i32 s11, s17, s0
	scratch_load_b32 v0, off, s10
	scratch_load_b32 v7, off, s11
	s_add_i32 s0, s0, 4
	s_cmp_lg_u32 s0, 32
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v0, v7, v0
	scratch_store_b32 off, v0, s11
	s_cbranch_scc1 .LBB0_391
; %bb.392:                              ; %sha256_compile.exit153.i235.i
                                        ;   in Loop: Header=BB0_232 Depth=2
	v_mov_b32_e32 v9, 0
	v_mov_b32_e32 v10, 0
.LBB0_393:                              ; %Flow879
                                        ;   in Loop: Header=BB0_232 Depth=2
	s_or_b32 exec_lo, exec_lo, s23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v0, 2, v9
	v_sub_co_u32 v9, vcc_lo, 0x42, v9
	v_sub_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_mov_b32 s10, 0
.LBB0_394:                              ; %.lr.ph.i.i.i.i44.i194.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_232 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v9, -8
	v_add_co_ci_u32_e32 v12, vcc_lo, -1, v10, vcc_lo
	v_add_nc_u32_e32 v7, 48, v0
	v_add_co_u32 v9, s0, v9, -4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cmp_gt_u64_e32 vcc_lo, 4, v[11:12]
	v_add_nc_u32_e32 v0, 4, v0
	v_add_nc_u32_e32 v13, 40, v7
	v_add_nc_u32_e32 v15, 42, v7
	v_add_co_ci_u32_e64 v10, s0, -1, v10, s0
	v_add_nc_u32_e32 v14, 41, v7
	v_add_nc_u32_e32 v7, 43, v7
	s_or_b32 s10, vcc_lo, s10
	s_clause 0x3
	scratch_store_b8 v13, v1, off
	scratch_store_b8 v14, v1, off
	scratch_store_b8 v15, v1, off
	scratch_store_b8 v7, v1, off
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_394
; %bb.395:                              ; %._crit_edge.i.i.i.i47.i197.i
                                        ;   in Loop: Header=BB0_232 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
	v_add_nc_u32_e32 v0, 48, v0
	s_mov_b32 s0, 0
	s_mov_b32 s10, exec_lo
	v_cmpx_lt_i64_e32 5, v[9:10]
	s_xor_b32 s10, exec_lo, s10
	s_cbranch_execz .LBB0_399
; %bb.396:                              ; %NodeBlock871
                                        ;   in Loop: Header=BB0_232 Depth=2
	s_mov_b32 s0, exec_lo
	v_cmpx_lt_i64_e32 6, v[9:10]
	s_cbranch_execz .LBB0_398
; %bb.397:                              ;   in Loop: Header=BB0_232 Depth=2
	v_add_nc_u32_e32 v7, 42, v0
	scratch_store_b8 v7, v1, off
.LBB0_398:                              ;   in Loop: Header=BB0_232 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v7, 41, v0
	s_mov_b32 s0, exec_lo
	scratch_store_b8 v7, v1, off
.LBB0_399:                              ; %Flow875
                                        ;   in Loop: Header=BB0_232 Depth=2
	s_and_not1_saveexec_b32 s10, s10
; %bb.400:                              ; %LeafBlock869
                                        ;   in Loop: Header=BB0_232 Depth=2
	v_cmp_eq_u64_e32 vcc_lo, 5, v[9:10]
	s_and_not1_b32 s0, s0, exec_lo
	s_and_b32 s11, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s0, s0, s11
; %bb.401:                              ; %Flow876
                                        ;   in Loop: Header=BB0_232 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
	s_and_saveexec_b32 s10, s0
	s_cbranch_execz .LBB0_403
; %bb.402:                              ;   in Loop: Header=BB0_232 Depth=2
	v_add_nc_u32_e32 v0, 40, v0
	scratch_store_b8 v0, v1, off
.LBB0_403:                              ; %_ZL6memsetPvim.exit.i.i48.i198.i
                                        ;   in Loop: Header=BB0_232 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
	scratch_load_b64 v[9:10], off, off offset:48
	s_movk_i32 s10, 0xffe0
	s_mov_b32 s11, -1
	s_mov_b32 s0, 0
	s_waitcnt vmcnt(0)
	v_alignbit_b32 v10, v10, v9, 29
	v_lshlrev_b32_e32 v11, 3, v9
	scratch_store_b64 off, v[10:11], off offset:144
.LBB0_404:                              ; %.lr.ph.i.i.i116.i199.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_232 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_readfirstlane_b32 s23, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s23, s23, s0
	s_add_i32 s24, s23, 8
	s_add_i32 s25, s23, 9
	s_add_i32 s26, s23, 10
	s_add_i32 s23, s23, 11
	s_clause 0x3
	scratch_load_u8 v0, off, s24
	scratch_load_u8 v7, off, s25
	scratch_load_u8 v9, off, s26
	scratch_load_u8 v10, off, s23
	v_readfirstlane_b32 s23, v26
	s_add_i32 s24, s0, 16
	s_delay_alu instid0(VALU_DEP_1)
	s_add_i32 s23, s23, s0
	s_add_i32 s0, s0, 4
	s_add_i32 s25, s23, 1
	s_add_i32 s26, s23, 2
	s_add_i32 s23, s23, 3
	s_add_u32 s10, s10, 4
	s_addc_u32 s11, s11, 0
	s_waitcnt vmcnt(3)
	scratch_store_b8 off, v0, s24
	s_waitcnt vmcnt(2)
	scratch_store_b8 off, v7, s25
	s_waitcnt vmcnt(1)
	scratch_store_b8 off, v9, s26
	s_waitcnt vmcnt(0)
	scratch_store_b8 off, v10, s23
	s_cmp_lg_u64 s[10:11], 0
	s_cbranch_scc1 .LBB0_404
; %bb.405:                              ; %.preheader14.i122.i204.i.preheader
                                        ;   in Loop: Header=BB0_232 Depth=2
	s_mov_b32 s10, 0
.LBB0_406:                              ; %.preheader14.i122.i204.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_232 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_407 Depth 4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s10, 0
	s_mov_b32 s23, 0
	s_cselect_b32 s11, -1, 0
.LBB0_407:                              ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_232 Depth=2
                                        ;       Parent Loop BB0_406 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_sub_i32 s0, 4, s23
	s_sub_i32 s24, 0, s23
	s_and_b32 s0, s0, 7
	s_and_b32 s24, s24, 7
	s_lshl_b32 s0, s0, 2
	s_lshl_b32 s24, s24, 2
	s_add_i32 s0, s0, 16
	s_add_i32 s24, s24, 16
	s_clause 0x1
	scratch_load_b32 v7, off, s0
	scratch_load_b32 v0, off, s24
	s_and_not1_b32 vcc_lo, exec_lo, s11
	s_cbranch_vccnz .LBB0_409
; %bb.408:                              ;   in Loop: Header=BB0_407 Depth=4
	s_add_i32 s0, s23, 14
	s_add_i32 s24, s23, 1
	s_and_b32 s0, s0, 15
	s_and_b32 s25, s24, 15
	s_lshl_b32 s0, s0, 2
	s_lshl_b32 s25, s25, 2
	s_add_i32 s0, s16, s0
	scratch_load_b32 v9, off, s0
	s_add_i32 s0, s16, s25
	s_add_i32 s25, s23, 9
	scratch_load_b32 v10, off, s0
	s_and_b32 s0, s25, 15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b32 s0, s0, 2
	s_add_i32 s0, s16, s0
	scratch_load_b32 v11, off, s0
	s_lshl_b32 s0, s23, 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s25, s16, s0
	s_mov_b32 s0, 0
	scratch_load_b32 v12, off, s25
	s_waitcnt vmcnt(3)
	v_alignbit_b32 v13, v9, v9, 17
	v_alignbit_b32 v14, v9, v9, 19
	v_lshrrev_b32_e32 v9, 10, v9
	s_waitcnt vmcnt(2)
	v_alignbit_b32 v15, v10, v10, 7
	v_alignbit_b32 v16, v10, v10, 18
	v_lshrrev_b32_e32 v10, 3, v10
	v_xor_b32_e32 v13, v13, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor3_b32 v10, v15, v16, v10
	s_waitcnt vmcnt(1)
	v_xad_u32 v9, v13, v9, v11
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v9, v9, v12, v10
	scratch_store_b32 off, v9, s25
	s_branch .LBB0_410
.LBB0_409:                              ;   in Loop: Header=BB0_407 Depth=4
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $sgpr24
.LBB0_410:                              ; %Flow
                                        ;   in Loop: Header=BB0_407 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_412
; %bb.411:                              ;   in Loop: Header=BB0_407 Depth=4
	s_lshl_b32 s0, s23, 2
	s_add_i32 s24, s23, 1
	s_add_i32 s0, s16, s0
	scratch_load_b32 v9, off, s0
.LBB0_412:                              ; %m_cycle.exit.i126.i208.i
                                        ;   in Loop: Header=BB0_407 Depth=4
	s_getpc_b64 s[26:27]
	s_add_u32 s26, s26, _ZL4k256@rel32@lo+4
	s_addc_u32 s27, s27, _ZL4k256@rel32@hi+12
	s_or_b32 s0, s23, s10
	s_waitcnt vmcnt(1)
	v_alignbit_b32 v13, v7, v7, 6
	s_lshl_b64 s[28:29], s[0:1], 2
	v_alignbit_b32 v14, v7, v7, 11
	s_add_u32 s26, s28, s26
	s_addc_u32 s27, s29, s27
	s_sub_i32 s0, 6, s23
	s_sub_i32 s25, 5, s23
	s_and_b32 s0, s0, 7
	s_and_b32 s25, s25, 7
	s_lshl_b32 s0, s0, 2
	s_sub_i32 s28, 7, s23
	s_lshl_b32 s25, s25, 2
	s_add_i32 s0, s0, 16
	s_add_i32 s25, s25, 16
	s_and_b32 s28, s28, 7
	s_clause 0x1
	scratch_load_b32 v10, off, s0
	scratch_load_b32 v11, off, s25
	s_lshl_b32 s0, s28, 2
	s_load_b32 s25, s[26:27], 0x0
	s_add_i32 s0, s0, 16
	v_alignbit_b32 v15, v7, v7, 25
	scratch_load_b32 v12, off, s0
	s_sub_i32 s26, 1, s23
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s26, s26, 7
	v_xor3_b32 v13, v13, v14, v15
	s_lshl_b32 s26, s26, 2
	s_add_i32 s26, s26, 16
	s_waitcnt vmcnt(3) lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v9, v9, v13, s25
	s_sub_i32 s25, 3, s23
	s_sub_i32 s23, 2, s23
	s_and_b32 s25, s25, 7
	s_and_b32 s23, s23, 7
	s_lshl_b32 s25, s25, 2
	s_lshl_b32 s23, s23, 2
	s_add_i32 s25, s25, 16
	s_add_i32 s23, s23, 16
	v_alignbit_b32 v13, v0, v0, 22
	s_cmp_lg_u32 s24, 16
	s_waitcnt vmcnt(1)
	v_bfi_b32 v7, v7, v11, v10
	v_alignbit_b32 v11, v0, v0, 2
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2)
	v_add3_u32 v7, v9, v12, v7
	v_alignbit_b32 v12, v0, v0, 13
	scratch_store_b32 off, v7, s0
	scratch_load_b32 v9, off, s25
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v7, v7, v9
	scratch_store_b32 off, v7, s25
	s_clause 0x2
	scratch_load_b32 v7, off, s26
	scratch_load_b32 v9, off, s23
	scratch_load_b32 v10, off, s0
	s_mov_b32 s23, s24
	s_waitcnt vmcnt(2)
	v_and_b32_e32 v14, v7, v0
	v_xor_b32_e32 v0, v7, v0
	v_xor3_b32 v7, v11, v12, v13
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_or_b32 v0, v9, v0, v14
	s_waitcnt vmcnt(0)
	v_add3_u32 v0, v10, v7, v0
	scratch_store_b32 off, v0, s0
	s_cbranch_scc1 .LBB0_407
; %bb.413:                              ; %_ZL6memcpyPvPKvm.exit.i129.i211.i
                                        ;   in Loop: Header=BB0_406 Depth=3
	s_add_i32 s0, s10, 16
	s_cmp_lt_u32 s10, 48
	s_mov_b32 s10, s0
	s_cbranch_scc1 .LBB0_406
; %bb.414:                              ; %.preheader.i130.i212.i.preheader
                                        ;   in Loop: Header=BB0_232 Depth=2
	s_mov_b32 s0, 0
.LBB0_415:                              ; %.preheader.i130.i212.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_232 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e64 v0, s0, 48
	s_add_i32 s10, s0, 16
	s_add_i32 s0, s0, 4
	s_cmp_lg_u32 s0, 32
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v0, 8, v0
	scratch_load_b32 v7, off, s10
	scratch_load_b32 v9, v0, off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v7, v9, v7
	scratch_store_b32 v0, v7, off
	s_cbranch_scc1 .LBB0_415
; %bb.416:                              ; %sha256_compile.exit134.i215.i
                                        ;   in Loop: Header=BB0_232 Depth=2
	s_mov_b32 s0, 0
	s_mov_b32 s10, 0
.LBB0_417:                              ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_232 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s11, s10, -4
	s_add_i32 s23, s10, 0x100
	v_add_nc_u32_e64 v0, s11, 48
	s_and_not1_b32 s11, 24, s0
	s_add_i32 s10, s10, 1
	s_add_i32 s0, s0, 8
	s_cmp_lg_u32 s10, 32
	v_add_nc_u32_e32 v0, 8, v0
	scratch_load_b32 v0, v0, off
	s_waitcnt vmcnt(0)
	v_lshrrev_b32_e32 v0, s11, v0
	scratch_store_b8 off, v0, s23
	s_cbranch_scc1 .LBB0_417
; %bb.418:                              ; %_Z13hmac_sha256_c10sha256_ctxS_PhiS0_.exit274.i
                                        ;   in Loop: Header=BB0_232 Depth=2
	v_dual_mov_b32 v10, v6 :: v_dual_mov_b32 v9, v5
	s_mov_b32 s0, 0
.LBB0_419:                              ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_232 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	s_add_i32 s10, s0, 0x100
	global_load_u8 v0, v[9:10], off
	scratch_load_u8 v7, off, s10
	s_add_i32 s0, s0, 1
	s_cmp_lg_u32 s0, 32
	s_waitcnt vmcnt(0)
	v_xor_b32_e32 v0, v0, v7
	global_store_b8 v[9:10], v0, off
	v_add_co_u32 v9, vcc_lo, v9, 1
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_cbranch_scc1 .LBB0_419
; %bb.420:                              ; %_ZL6memcpyPvPKvm.exit.i
                                        ;   in Loop: Header=BB0_232 Depth=2
	s_add_i32 s22, s22, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s22, s13
	s_cbranch_scc1 .LBB0_232
.LBB0_421:                              ; %_Z22cuda_derive_key_sha256PhiS_.exit
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v8, s19, v8
	v_add_nc_u32_e32 v23, s20, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s12, v8
	s_or_b32 s21, vcc_lo, s21
	s_and_not1_b32 exec_lo, exec_lo, s21
	s_cbranch_execnz .LBB0_2
.LBB0_422:                              ; %Flow955
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12PBKDF2KerneliPh
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 656
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 68
		.amdhsa_next_free_sgpr 32
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z12PBKDF2KerneliPh, .Lfunc_end0-_Z12PBKDF2KerneliPh
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 22356
; NumSgprs: 34
; NumVgprs: 68
; ScratchSize: 656
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 8
; NumSGPRsForWavesPerEU: 34
; NumVGPRsForWavesPerEU: 68
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	_ZL4k256,@object                ; @_ZL4k256
	.section	.rodata,"a",@progbits
	.p2align	4, 0x0
_ZL4k256:
	.long	1116352408                      ; 0x428a2f98
	.long	1899447441                      ; 0x71374491
	.long	3049323471                      ; 0xb5c0fbcf
	.long	3921009573                      ; 0xe9b5dba5
	.long	961987163                       ; 0x3956c25b
	.long	1508970993                      ; 0x59f111f1
	.long	2453635748                      ; 0x923f82a4
	.long	2870763221                      ; 0xab1c5ed5
	.long	3624381080                      ; 0xd807aa98
	.long	310598401                       ; 0x12835b01
	.long	607225278                       ; 0x243185be
	.long	1426881987                      ; 0x550c7dc3
	.long	1925078388                      ; 0x72be5d74
	.long	2162078206                      ; 0x80deb1fe
	.long	2614888103                      ; 0x9bdc06a7
	.long	3248222580                      ; 0xc19bf174
	.long	3835390401                      ; 0xe49b69c1
	.long	4022224774                      ; 0xefbe4786
	.long	264347078                       ; 0xfc19dc6
	.long	604807628                       ; 0x240ca1cc
	.long	770255983                       ; 0x2de92c6f
	.long	1249150122                      ; 0x4a7484aa
	.long	1555081692                      ; 0x5cb0a9dc
	.long	1996064986                      ; 0x76f988da
	.long	2554220882                      ; 0x983e5152
	.long	2821834349                      ; 0xa831c66d
	.long	2952996808                      ; 0xb00327c8
	.long	3210313671                      ; 0xbf597fc7
	.long	3336571891                      ; 0xc6e00bf3
	.long	3584528711                      ; 0xd5a79147
	.long	113926993                       ; 0x6ca6351
	.long	338241895                       ; 0x14292967
	.long	666307205                       ; 0x27b70a85
	.long	773529912                       ; 0x2e1b2138
	.long	1294757372                      ; 0x4d2c6dfc
	.long	1396182291                      ; 0x53380d13
	.long	1695183700                      ; 0x650a7354
	.long	1986661051                      ; 0x766a0abb
	.long	2177026350                      ; 0x81c2c92e
	.long	2456956037                      ; 0x92722c85
	.long	2730485921                      ; 0xa2bfe8a1
	.long	2820302411                      ; 0xa81a664b
	.long	3259730800                      ; 0xc24b8b70
	.long	3345764771                      ; 0xc76c51a3
	.long	3516065817                      ; 0xd192e819
	.long	3600352804                      ; 0xd6990624
	.long	4094571909                      ; 0xf40e3585
	.long	275423344                       ; 0x106aa070
	.long	430227734                       ; 0x19a4c116
	.long	506948616                       ; 0x1e376c08
	.long	659060556                       ; 0x2748774c
	.long	883997877                       ; 0x34b0bcb5
	.long	958139571                       ; 0x391c0cb3
	.long	1322822218                      ; 0x4ed8aa4a
	.long	1537002063                      ; 0x5b9cca4f
	.long	1747873779                      ; 0x682e6ff3
	.long	1955562222                      ; 0x748f82ee
	.long	2024104815                      ; 0x78a5636f
	.long	2227730452                      ; 0x84c87814
	.long	2361852424                      ; 0x8cc70208
	.long	2428436474                      ; 0x90befffa
	.long	2756734187                      ; 0xa4506ceb
	.long	3204031479                      ; 0xbef9a3f7
	.long	3329325298                      ; 0xc67178f2
	.size	_ZL4k256, 256

	.protected	ITERATIONS              ; @ITERATIONS
	.type	ITERATIONS,@object
	.data
	.globl	ITERATIONS
	.p2align	2, 0x0
ITERATIONS:
	.long	100000                          ; 0x186a0
	.size	ITERATIONS, 4

	.protected	SHA256_IPAD_CONST       ; @SHA256_IPAD_CONST
	.type	SHA256_IPAD_CONST,@object
	.globl	SHA256_IPAD_CONST
SHA256_IPAD_CONST:
	.byte	54                              ; 0x36
	.size	SHA256_IPAD_CONST, 1

	.protected	SHA256_OPAD_CONST       ; @SHA256_OPAD_CONST
	.type	SHA256_OPAD_CONST,@object
	.globl	SHA256_OPAD_CONST
SHA256_OPAD_CONST:
	.byte	92                              ; 0x5c
	.size	SHA256_OPAD_CONST, 1

	.protected	cuda_init_derive        ; @cuda_init_derive
	.type	cuda_init_derive,@object
	.globl	cuda_init_derive
	.p2align	4, 0x0
cuda_init_derive:
	.ascii	"\346X\024\3448'Y\370UP\002\236r=\307\347\000\000\000\001"
	.zero	12
	.size	cuda_init_derive, 32

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym ITERATIONS
	.addrsig_sym SHA256_IPAD_CONST
	.addrsig_sym SHA256_OPAD_CONST
	.addrsig_sym cuda_init_derive
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12PBKDF2KerneliPh
    .private_segment_fixed_size: 656
    .sgpr_count:     34
    .sgpr_spill_count: 0
    .symbol:         _Z12PBKDF2KerneliPh.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     68
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
