#include <stdio.h>

/*  ************************************************** FIRST LAYER START ********************************************************* */
/*
    Layer 1: Normal 3D Convolution Layer
    Input: 225 * 225 * 3 (Padding of 1)
    Weight: 3 * 3 * 3 with a Stride of 2
    Output: 112 * 112 * 32
    Next Layer is a padding layer, so padding operation is handled in this layer itself & hence
    Final Output = 114 * 114 * 32
*/
__global__ void executeFirstLayer_CONV3D_partA(double *Layer1_Neurons_GPU,
                            double *Layer1_Weights_GPU,
                            double *Layer2_Neurons_GPU,
                            double *Layer1_Mean_GPU,
                            double *Layer1_StanDev_GPU,
                            double *Layer1_Gamma_GPU,
                            double *Layer1_Beta_GPU
                        )
{
	double product = 0.0;
    int outputOffset = 115;
    int stride = 2;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 114 * 114)   // channel to work with
                        + (blockIdx.y * 32 * 114)    // Position in the grid row-wise
                        + (blockIdx.z * 32)          // Position in the grid column-wise
                        + (threadIdx.x * 114)
                        + (threadIdx.y);

    int weight_Position = filter_number * 27;

    int input_Position = ((blockIdx.y * 32 * 225) * stride) // Position in the grid row-wise
                       + (blockIdx.z * 32 * stride)         // Position in the grid column-wise
                       + (threadIdx.x * 225 * stride )
                       + (threadIdx.y * stride);

    /* RGB weights and input 3*3*3 */
    for(int channel = 0; channel < 3; channel++) // This is the Channel loop
    {
        for(int row = 0; row < 3; row++)       // This is the Row Loop
        {
            product += ((Layer1_Neurons_GPU[(channel * 225 * 225) + input_Position + (row * 225)] * Layer1_Weights_GPU[weight_Position + (channel * 3 * 3) + (row * 3)])
                    + (Layer1_Neurons_GPU[(channel * 225 * 225) + input_Position + (row * 225) + 1] * Layer1_Weights_GPU[weight_Position + (channel * 3 * 3) + (row * 3) + 1])
                    + (Layer1_Neurons_GPU[(channel * 225 * 225) + input_Position + (row * 225) + 2] * Layer1_Weights_GPU[weight_Position + (channel * 3 * 3) + (row * 3) + 2]));
        }
    }

    double Z = (product - Layer1_Mean_GPU[filter_number]) / Layer1_StanDev_GPU[filter_number];
    Z = (Z * Layer1_Gamma_GPU[filter_number]) + Layer1_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer2_Neurons_GPU[output_Position + outputOffset] = Z;
}

__global__ void executeFirstLayer_CONV3D_partB(double *Layer1_Neurons_GPU,
                            double *Layer1_Weights_GPU,
                            double *Layer2_Neurons_GPU,
                            double *Layer1_Mean_GPU,
                            double *Layer1_StanDev_GPU,
                            double *Layer1_Gamma_GPU,
                            double *Layer1_Beta_GPU
                        )
{
	double product = 0.0;
    int outputOffset = 115;
    int stride = 2;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 114 * 114)   // channel to work with
                        + (blockIdx.y * 16 * 114 + 96)  // Position in the grid row-wise and there is no column-wise position
                        + (threadIdx.x * 114)           // Position inside the 256 (16 * 16) block
                        + (threadIdx.y);

    int weight_Position = filter_number * 27;

    int input_Position = ((blockIdx.y * 16 * 225) * stride) + (96 * stride) // Position in the grid row-wise and column-wise
                       + (threadIdx.x * 225 * stride)
                       + (threadIdx.y * stride);

    /* RGB weights and input 3*3*3 */
    for(int channel = 0; channel < 3; channel++) // This is the Channel loop
    {
        for(int row = 0; row < 3; row++)       // This is the Row Loop
        {
            product += ((Layer1_Neurons_GPU[(channel * 225 * 225) + input_Position + (row * 225)] * Layer1_Weights_GPU[weight_Position + (channel * 3 * 3) + (row * 3)])
                    + (Layer1_Neurons_GPU[(channel * 225 * 225) + input_Position + (row * 225) + 1] * Layer1_Weights_GPU[weight_Position + (channel * 3 * 3) + (row * 3) + 1])
                    + (Layer1_Neurons_GPU[(channel * 225 * 225) + input_Position + (row * 225) + 2] * Layer1_Weights_GPU[weight_Position + (channel * 3 * 3) + (row * 3) + 2]));
        }
    }

    double Z = (product - Layer1_Mean_GPU[filter_number]) / Layer1_StanDev_GPU[filter_number];
    Z = (Z * Layer1_Gamma_GPU[filter_number]) + Layer1_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer2_Neurons_GPU[output_Position + outputOffset] = Z;
}

__global__ void executeFirstLayer_CONV3D_partC(double *Layer1_Neurons_GPU,
                            double *Layer1_Weights_GPU,
                            double *Layer2_Neurons_GPU,
                            double *Layer1_Mean_GPU,
                            double *Layer1_StanDev_GPU,
                            double *Layer1_Gamma_GPU,
                            double *Layer1_Beta_GPU
                        )
{
	double product = 0.0;
    int outputOffset = 115;
    int stride = 2;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 114 * 114)   // channel to work with
                        + (96 * 114)                    // Position in the grid row-wise as row is last
                        + (blockIdx.y * 16)             // Position in the grid column-wise
                        + (threadIdx.x * 114)           // Position inside the 256 (16 * 16) block
                        + (threadIdx.y);

    int weight_Position = filter_number * 27;

    int input_Position = ((96 * 225) * stride)
                       + (blockIdx.y * 16 * stride)     // Position in the grid row-wise and column-wise
                       + (threadIdx.x * 225 * stride)
                       + (threadIdx.y * stride);

    /* RGB weights and input 3*3*3 */
    for(int channel = 0; channel < 3; channel++) // This is the Channel loop
    {
        for(int row = 0; row < 3; row++)       // This is the Row Loop
        {
            product += ((Layer1_Neurons_GPU[(channel * 225 * 225) + input_Position + (row * 225)] * Layer1_Weights_GPU[weight_Position + (channel * 3 * 3) + (row * 3)])
                    + (Layer1_Neurons_GPU[(channel * 225 * 225) + input_Position + (row * 225) + 1] * Layer1_Weights_GPU[weight_Position + (channel * 3 * 3) + (row * 3) + 1])
                    + (Layer1_Neurons_GPU[(channel * 225 * 225) + input_Position + (row * 225) + 2] * Layer1_Weights_GPU[weight_Position + (channel * 3 * 3) + (row * 3) + 2]));
        }
    }

    double Z = (product - Layer1_Mean_GPU[filter_number]) / Layer1_StanDev_GPU[filter_number];
    Z = (Z * Layer1_Gamma_GPU[filter_number]) + Layer1_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer2_Neurons_GPU[output_Position + outputOffset] = Z;
}
/*  ************************************************** FIRST LAYER END ************************************************************ */

/*  ************************************************** SECOND LAYER START ********************************************************* */
/*
    Layer 2: Depthwise Separable Convolution Layer
    Input: 114 * 114 * 3 (After padding)
    Weight: 3 * 3 * 32 with a Stride of 1
    Output: 112 * 112 * 32
*/
__global__ void executeSecondLayer_DSC_partA(double *Layer2_Neurons_GPU,
                            double *Layer2_Weights_GPU,
                            double *Layer3_Neurons_GPU,
                            double *Layer2_Mean_GPU,
                            double *Layer2_StanDev_GPU,
                            double *Layer2_Gamma_GPU,
                            double *Layer2_Beta_GPU
                        )
{
	double product = 0.0;

    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 112 * 112)   // channel to work with
                        + (blockIdx.y * 32 * 112)    // Position in the grid row-wise
                        + (blockIdx.z * 32)          // Position in the grid column-wise
                        + (threadIdx.x * 112)
                        + (threadIdx.y);

    int weight_Position = filter_number * 9;

    int input_Position = (blockIdx.y * 32 * 114) // Position in the grid row-wise
                       + (blockIdx.z * 32)         // Position in the grid column-wise
                       + (threadIdx.x * 114)
                       + (threadIdx.y);

    for(int row = 0; row < 3; row++)       // This is the Row Loop
    {
        product += ((Layer2_Neurons_GPU[(filter_number * 114 * 114) + input_Position + (row * 114)] * Layer2_Weights_GPU[weight_Position + (row * 3)])
                + (Layer2_Neurons_GPU[(filter_number * 114 * 114) + input_Position + (row * 114) + 1] * Layer2_Weights_GPU[weight_Position + (row * 3) + 1])
                + (Layer2_Neurons_GPU[(filter_number * 114 * 114) + input_Position + (row * 114) + 2] * Layer2_Weights_GPU[weight_Position + (row * 3) + 2]));
    }

    double Z = (product - Layer2_Mean_GPU[filter_number]) / Layer2_StanDev_GPU[filter_number];
    Z = (Z * Layer2_Gamma_GPU[filter_number]) + Layer2_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer3_Neurons_GPU[output_Position] = Z;
}

__global__ void executeSecondLayer_DSC_partB(double *Layer2_Neurons_GPU,
                                    double *Layer2_Weights_GPU,
                                    double *Layer3_Neurons_GPU,
                                    double *Layer2_Mean_GPU,
                                    double *Layer2_StanDev_GPU,
                                    double *Layer2_Gamma_GPU,
                                    double *Layer2_Beta_GPU
                                )
{
    double product = 0.0;

    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 112 * 112)   // channel to work with
                        + (blockIdx.y * 16 * 112 + 96)  // Position in the grid row-wise and there is no column-wise position
                        + (threadIdx.x * 112)           // Position inside the 256 (16 * 16) block
                        + (threadIdx.y);

    int weight_Position = filter_number * 9;

    int input_Position  = (blockIdx.y * 16 * 114)
                        + (96) // Position in the grid row-wise and column-wise
                        + (threadIdx.x * 114)
                        + (threadIdx.y);

    for(int row = 0; row < 3; row++)       // This is the Row Loop
    {
        product += ((Layer2_Neurons_GPU[(filter_number * 114 * 114) + input_Position + (row * 114)] * Layer2_Weights_GPU[weight_Position + (row * 3)])
                + (Layer2_Neurons_GPU[(filter_number * 114 * 114) + input_Position + (row * 114) + 1] * Layer2_Weights_GPU[weight_Position + (row * 3) + 1])
                + (Layer2_Neurons_GPU[(filter_number * 114 * 114) + input_Position + (row * 114) + 2] * Layer2_Weights_GPU[weight_Position + (row * 3) + 2]));
    }

    double Z = (product - Layer2_Mean_GPU[filter_number]) / Layer2_StanDev_GPU[filter_number];
    Z = (Z * Layer2_Gamma_GPU[filter_number]) + Layer2_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer3_Neurons_GPU[output_Position] = Z;
}

__global__ void executeSecondLayer_DSC_partC(double *Layer2_Neurons_GPU,
                                    double *Layer2_Weights_GPU,
                                    double *Layer3_Neurons_GPU,
                                    double *Layer2_Mean_GPU,
                                    double *Layer2_StanDev_GPU,
                                    double *Layer2_Gamma_GPU,
                                    double *Layer2_Beta_GPU
                                )
{
    double product = 0.0;

    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 112 * 112)   // channel to work with
                        + (96 * 112)                    // Position in the grid row-wise as row is last
                        + (blockIdx.y * 16)             // Position in the grid column-wise
                        + (threadIdx.x * 112)           // Position inside the 256 (16 * 16) block
                        + (threadIdx.y);

    int weight_Position = filter_number * 9;

    int input_Position = (96 * 114)
                        + (blockIdx.y * 16)     // Position in the grid row-wise and column-wise
                        + (threadIdx.x * 114)
                        + (threadIdx.y);

    for(int row = 0; row < 3; row++)       // This is the Row Loop
    {
        product += ((Layer2_Neurons_GPU[(filter_number * 114 * 114) + input_Position + (row * 114)] * Layer2_Weights_GPU[weight_Position + (row * 3)])
                + (Layer2_Neurons_GPU[(filter_number * 114 * 114) + input_Position + (row * 114) + 1] * Layer2_Weights_GPU[weight_Position + (row * 3) + 1])
                + (Layer2_Neurons_GPU[(filter_number * 114 * 114) + input_Position + (row * 114) + 2] * Layer2_Weights_GPU[weight_Position + (row * 3) + 2]));
    }

    double Z = (product - Layer2_Mean_GPU[filter_number]) / Layer2_StanDev_GPU[filter_number];
    Z = (Z * Layer2_Gamma_GPU[filter_number]) + Layer2_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer3_Neurons_GPU[output_Position] = Z;
}
/*  ************************************************** SECOND LAYER END ********************************************************* */

/*  ************************************************** THIRD LAYER START ******************************************************** */
/*
    Layer 3: Pointwise Separable Convolution Layer
    Input: 112 * 112 * 32 (After padding)
    Weight: 1 * 1 * 32 * 64 with a Stride of 1
    Output: 113 * 113 * 64 (Padding of 1 is handled in this layer execution itself)
*/
__global__ void executeThirdLayer_PSC_partA(double *Layer3_Neurons_GPU,
    double *Layer3_Weights_GPU,
    double *Layer4_Neurons_GPU,
    double *Layer3_Mean_GPU,
    double *Layer3_StanDev_GPU,
    double *Layer3_Gamma_GPU,
    double *Layer3_Beta_GPU
)
{
    double product = 0.0;

    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 113 * 113)   // channel to work with
                        + (blockIdx.y * 32 * 113)    // Position in the grid row-wise
                        + (blockIdx.z * 32)          // Position in the grid column-wise
                        + (threadIdx.x * 113)
                        + (threadIdx.y);

    int weight_Position = filter_number * 32;

    int input_Position = (blockIdx.y * 32 * 112) // Position in the grid row-wise
                       + (blockIdx.z * 32)         // Position in the grid column-wise
                       + (threadIdx.x * 112)
                       + (threadIdx.y);

    for(int channel = 0; channel < 32; channel++)       // This is the channel loop as we have 32 channels to work with
    {
        product += (Layer3_Neurons_GPU[(channel * 112 * 112) + input_Position] * Layer3_Weights_GPU[weight_Position + channel]);
    }

    double Z = (product - Layer3_Mean_GPU[filter_number]) / Layer3_StanDev_GPU[filter_number];
    Z = (Z * Layer3_Gamma_GPU[filter_number]) + Layer3_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer4_Neurons_GPU[output_Position] = Z;
}

__global__ void executeThirdLayer_PSC_partB(double *Layer3_Neurons_GPU,
    double *Layer3_Weights_GPU,
    double *Layer4_Neurons_GPU,
    double *Layer3_Mean_GPU,
    double *Layer3_StanDev_GPU,
    double *Layer3_Gamma_GPU,
    double *Layer3_Beta_GPU
)
{
    double product = 0.0;

    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 113 * 113)   // channel to work with
                        + (blockIdx.y * 16 * 113 + 96)  // Position in the grid row-wise and there is no column-wise position
                        + (threadIdx.x * 113)           // Position inside the 256 (16 * 16) block
                        + (threadIdx.y);

    int weight_Position = filter_number * 32;

    int input_Position = (blockIdx.y * 16 * 112)         // Position in the grid row-wise
                       + (96)                   // Position in the grid column-wise
                       + (threadIdx.x * 112)
                       + (threadIdx.y);

    for(int channel = 0 ; channel < 32 ; channel++) // Channel loop as we have 32 input channels to work with
    {
        product += (Layer3_Neurons_GPU[(channel * 112 * 112) + input_Position] * Layer3_Weights_GPU[weight_Position + channel]);
    }

    double Z = (product - Layer3_Mean_GPU[filter_number]) / Layer3_StanDev_GPU[filter_number];
    Z = (Z * Layer3_Gamma_GPU[filter_number]) + Layer3_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer4_Neurons_GPU[output_Position] = Z;
}

__global__ void executeThirdLayer_PSC_partC(double *Layer3_Neurons_GPU,
    double *Layer3_Weights_GPU,
    double *Layer4_Neurons_GPU,
    double *Layer3_Mean_GPU,
    double *Layer3_StanDev_GPU,
    double *Layer3_Gamma_GPU,
    double *Layer3_Beta_GPU
)
{
    double product = 0.0;

    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 113 * 113)   // channel to work with
                        + (96 * 113)                    // Position in the grid row-wise as row is last
                        + (blockIdx.y * 16)             // Position in the grid column-wise
                        + (threadIdx.x * 113)           // Position inside the 256 (16 * 16) block
                        + (threadIdx.y);

    int weight_Position = filter_number * 32;

    int input_Position = (96 * 112)            // row-wise: the bottom part of the grid after 96th row
                       + (blockIdx.y * 16)     // column-wise: block number in the 6 blocks of 16 * 16 threads
                       + (threadIdx.x * 112)   // Position inside one the above block row-wise
                       + (threadIdx.y);        // Position inside one the above block column-wise

    for(int channel = 0 ; channel < 32 ; channel++) // Channel loop as we have 32 input channels to work with
    {
        product += (Layer3_Neurons_GPU[(channel * 112 * 112) + input_Position] * Layer3_Weights_GPU[weight_Position + channel]);
    }

    double Z = (product - Layer3_Mean_GPU[filter_number]) / Layer3_StanDev_GPU[filter_number];
    Z = (Z * Layer3_Gamma_GPU[filter_number]) + Layer3_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer4_Neurons_GPU[output_Position] = Z;
}
/*  ************************************************** THIRD LAYER END ********************************************************* */

/*  ************************************************** FOURTH LAYER START ****************************************************** */
/*
    Layer 4: Depthwise Separable Convolution Layer
    Input: 113 * 113 * 64
    Weight: 3 * 3 * 64 with a Stride of 2
    Output: 56 * 56 * 64
*/
__global__ void executeFourthLayer_DSC_partA(double *Layer4_Neurons_GPU,
    double *Layer4_Weights_GPU,
    double *Layer5_Neurons_GPU,
    double *Layer4_Mean_GPU,
    double *Layer4_StanDev_GPU,
    double *Layer4_Gamma_GPU,
    double *Layer4_Beta_GPU
)
{
    double product = 0.0;
    int stride = 2;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 56 * 56)   // channel to work with
                        + (threadIdx.x * 56)
                        + (threadIdx.y);

    int weight_Position = filter_number * 9;

    int input_Position = (threadIdx.x * 113 * stride )
                       + (threadIdx.y * stride);

    for(int row = 0; row < 3; row++)       // This is the Row Loop
    {
        product += ((Layer4_Neurons_GPU[(filter_number * 113 * 113) + input_Position + (row * 113)] * Layer4_Weights_GPU[weight_Position + (row * 3)])
                + (Layer4_Neurons_GPU[(filter_number * 113 * 113) + input_Position + (row * 113) + 1] * Layer4_Weights_GPU[weight_Position + (row * 3) + 1])
                + (Layer4_Neurons_GPU[(filter_number * 113 * 113) + input_Position + (row * 113) + 2] * Layer4_Weights_GPU[weight_Position + (row * 3) + 2]));
    }

    double Z = (product - Layer4_Mean_GPU[filter_number]) / Layer4_StanDev_GPU[filter_number];
    Z = (Z * Layer4_Gamma_GPU[filter_number]) + Layer4_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer5_Neurons_GPU[output_Position] = Z;
}

__global__ void executeFourthLayer_DSC_partB(double *Layer4_Neurons_GPU,
    double *Layer4_Weights_GPU,
    double *Layer5_Neurons_GPU,
    double *Layer4_Mean_GPU,
    double *Layer4_StanDev_GPU,
    double *Layer4_Gamma_GPU,
    double *Layer4_Beta_GPU
)
{
    double product = 0.0;
    int stride = 2;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 56 * 56)   // channel to work with
                        + (threadIdx.x * 56)
                        + (threadIdx.y + 32);

    int weight_Position = filter_number * 9;

    int input_Position = (threadIdx.x * 113 * stride)
                       + (threadIdx.y * stride)
                       + (32 * stride);

    for(int row = 0; row < 3; row++)       // This is the Row Loop
    {
        product += ((Layer4_Neurons_GPU[(filter_number * 113 * 113) + input_Position + (row * 113)] * Layer4_Weights_GPU[weight_Position + (row * 3)])
                + (Layer4_Neurons_GPU[(filter_number * 113 * 113) + input_Position + (row * 113) + 1] * Layer4_Weights_GPU[weight_Position + (row * 3) + 1])
                + (Layer4_Neurons_GPU[(filter_number * 113 * 113) + input_Position + (row * 113) + 2] * Layer4_Weights_GPU[weight_Position + (row * 3) + 2]));
    }

    double Z = (product - Layer4_Mean_GPU[filter_number]) / Layer4_StanDev_GPU[filter_number];
    Z = (Z * Layer4_Gamma_GPU[filter_number]) + Layer4_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer5_Neurons_GPU[output_Position] = Z;
}

__global__ void executeFourthLayer_DSC_partC(double *Layer4_Neurons_GPU,
    double *Layer4_Weights_GPU,
    double *Layer5_Neurons_GPU,
    double *Layer4_Mean_GPU,
    double *Layer4_StanDev_GPU,
    double *Layer4_Gamma_GPU,
    double *Layer4_Beta_GPU
)
{
    double product = 0.0;
    int stride = 2;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 56 * 56)   // channel to work with
                        + (56 * 32)
                        + (threadIdx.x * 56)
                        + (threadIdx.y);

    int weight_Position = filter_number * 9;

    int input_Position = (113 * 32 * stride)
                       + (threadIdx.x * 113 * stride)
                       + (threadIdx.y * stride);

    for(int row = 0; row < 3; row++)       // This is the Row Loop
    {
        product += ((Layer4_Neurons_GPU[(filter_number * 113 * 113) + input_Position + (row * 113)] * Layer4_Weights_GPU[weight_Position + (row * 3)])
                + (Layer4_Neurons_GPU[(filter_number * 113 * 113) + input_Position + (row * 113) + 1] * Layer4_Weights_GPU[weight_Position + (row * 3) + 1])
                + (Layer4_Neurons_GPU[(filter_number * 113 * 113) + input_Position + (row * 113) + 2] * Layer4_Weights_GPU[weight_Position + (row * 3) + 2]));
    }

    double Z = (product - Layer4_Mean_GPU[filter_number]) / Layer4_StanDev_GPU[filter_number];
    Z = (Z * Layer4_Gamma_GPU[filter_number]) + Layer4_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer5_Neurons_GPU[output_Position] = Z;
}

__global__ void executeFourthLayer_DSC_partD(double *Layer4_Neurons_GPU,
    double *Layer4_Weights_GPU,
    double *Layer5_Neurons_GPU,
    double *Layer4_Mean_GPU,
    double *Layer4_StanDev_GPU,
    double *Layer4_Gamma_GPU,
    double *Layer4_Beta_GPU
)
{
    double product = 0.0;
    int stride = 2;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 56 * 56)   // channel to work with
                        + (56 * 32)
                        + 32
                        + (threadIdx.x * 56)
                        + (threadIdx.y);

    int weight_Position = filter_number * 9;

    int input_Position = (113 * 32 * stride)
                       + (32 * stride)
                       + (threadIdx.x * 113 * stride)
                       + (threadIdx.y * stride);

    for(int row = 0; row < 3; row++) // This is the Row Loop
    {
        product += ((Layer4_Neurons_GPU[(filter_number * 113 * 113) + input_Position + (row * 113)] * Layer4_Weights_GPU[weight_Position + (row * 3)])
                + (Layer4_Neurons_GPU[(filter_number * 113 * 113) + input_Position + (row * 113) + 1] * Layer4_Weights_GPU[weight_Position + (row * 3) + 1])
                + (Layer4_Neurons_GPU[(filter_number * 113 * 113) + input_Position + (row * 113) + 2] * Layer4_Weights_GPU[weight_Position + (row * 3) + 2]));
    }

    double Z = (product - Layer4_Mean_GPU[filter_number]) / Layer4_StanDev_GPU[filter_number];
    Z = (Z * Layer4_Gamma_GPU[filter_number]) + Layer4_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer5_Neurons_GPU[output_Position] = Z;
}
/*  ************************************************** FOURTH LAYER END ****************************************************** */

/*  *************************************************** FIFTH LAYER START **************************************************** */
/*
    Layer 5: Pointwise Separable Convolution Layer
    Input: 56 * 56 * 64
    Weight: 1 * 1 * 64 * 128 with a Stride of 1
    Output: 58 * 58 * 128 (Padding for the next layer is handled here itself)
*/
__global__ void executeFifthLayer_PSC_partA(double *Layer5_Neurons_GPU,
    double *Layer5_Weights_GPU,
    double *Layer6_Neurons_GPU,
    double *Layer5_Mean_GPU,
    double *Layer5_StanDev_GPU,
    double *Layer5_Gamma_GPU,
    double *Layer5_Beta_GPU
)
{
    double product = 0.0;
    int offset = 59;

    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 58 * 58)   // channel to work with
                        + (threadIdx.x * 58)
                        + (threadIdx.y);

    int weight_Position = filter_number * 64;

    int input_Position = (threadIdx.x * 56)
                       + (threadIdx.y);

    for(int channel = 0; channel < 64; channel++)       // This is the channel loop as we have 32 channels to work with
    {
        product += (Layer5_Neurons_GPU[(channel * 56 * 56) + input_Position] * Layer5_Weights_GPU[weight_Position + channel]);
    }

    double Z = (product - Layer5_Mean_GPU[filter_number]) / Layer5_StanDev_GPU[filter_number];
    Z = (Z * Layer5_Gamma_GPU[filter_number]) + Layer5_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer6_Neurons_GPU[output_Position + offset] = Z;
}

__global__ void executeFifthLayer_PSC_partB(double *Layer5_Neurons_GPU,
    double *Layer5_Weights_GPU,
    double *Layer6_Neurons_GPU,
    double *Layer5_Mean_GPU,
    double *Layer5_StanDev_GPU,
    double *Layer5_Gamma_GPU,
    double *Layer5_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;
    int offset = 59;

    // Output position
    int output_Position = (filter_number * 58 * 58)   // channel to work with
                        + (threadIdx.x * 58)
                        + (threadIdx.y + 32);

    int weight_Position = filter_number * 64;

    int input_Position = (threadIdx.x * 56)
                       + (threadIdx.y)
                       + (32);

    for(int channel = 0; channel < 64; channel++)       // This is the channel loop as we have 32 channels to work with
    {
        product += (Layer5_Neurons_GPU[(channel * 56 * 56) + input_Position] * Layer5_Weights_GPU[weight_Position + channel]);
    }

    double Z = (product - Layer5_Mean_GPU[filter_number]) / Layer5_StanDev_GPU[filter_number];
    Z = (Z * Layer5_Gamma_GPU[filter_number]) + Layer5_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer6_Neurons_GPU[output_Position + offset] = Z;
}

__global__ void executeFifthLayer_PSC_partC(double *Layer5_Neurons_GPU,
    double *Layer5_Weights_GPU,
    double *Layer6_Neurons_GPU,
    double *Layer5_Mean_GPU,
    double *Layer5_StanDev_GPU,
    double *Layer5_Gamma_GPU,
    double *Layer5_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;
    int offset = 59;

    // Output position
    int output_Position = (filter_number * 58 * 58)   // channel to work with
                        + (58 * 32)
                        + (threadIdx.x * 58)
                        + (threadIdx.y);

    int weight_Position = filter_number * 64;

    int input_Position = (56 * 32)
                       + (threadIdx.x * 56)
                       + (threadIdx.y);

    for(int channel = 0; channel < 64; channel++)       // This is the channel loop as we have 32 channels to work with
    {
        product += (Layer5_Neurons_GPU[(channel * 56 * 56) + input_Position] * Layer5_Weights_GPU[weight_Position + channel]);
    }

    double Z = (product - Layer5_Mean_GPU[filter_number]) / Layer5_StanDev_GPU[filter_number];
    Z = (Z * Layer5_Gamma_GPU[filter_number]) + Layer5_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer6_Neurons_GPU[output_Position + offset] = Z;
}

__global__ void executeFifthLayer_PSC_partD(double *Layer5_Neurons_GPU,
    double *Layer5_Weights_GPU,
    double *Layer6_Neurons_GPU,
    double *Layer5_Mean_GPU,
    double *Layer5_StanDev_GPU,
    double *Layer5_Gamma_GPU,
    double *Layer5_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;
    int offset = 59;

    // Output position
    int output_Position = (filter_number * 58 * 58)   // channel to work with
                        + (58 * 32)
                        + 32
                        + (threadIdx.x * 58)
                        + (threadIdx.y);

    int weight_Position = filter_number * 64;

    int input_Position = (56 * 32)
                       + (32)
                       + (threadIdx.x * 56)
                       + (threadIdx.y);

    for(int channel = 0; channel < 64; channel++)       // This is the channel loop as we have 32 channels to work with
    {
        product += (Layer5_Neurons_GPU[(channel * 56 * 56) + input_Position] * Layer5_Weights_GPU[weight_Position + channel]);
    }

    double Z = (product - Layer5_Mean_GPU[filter_number]) / Layer5_StanDev_GPU[filter_number];
    Z = (Z * Layer5_Gamma_GPU[filter_number]) + Layer5_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer6_Neurons_GPU[output_Position + offset] = Z;
}
/*  *************************************************** FIFTH LAYER END **************************************************** */

/*  *************************************************** SIXTH LAYER START ************************************************** */
/*
    Layer 6: Depthwise Separable Convolution Layer
    Input: 58 * 58 * 128
    Weight: 3 * 3 * 128 with a Stride of 1
    Output: 56 * 56 * 128
*/
__global__ void executeSixthLayer_DSC_partA(double *Layer6_Neurons_GPU,
    double *Layer6_Weights_GPU,
    double *Layer7_Neurons_GPU,
    double *Layer6_Mean_GPU,
    double *Layer6_StanDev_GPU,
    double *Layer6_Gamma_GPU,
    double *Layer6_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 56 * 56)   // channel to work with
                        + (threadIdx.x * 56)
                        + (threadIdx.y);

    int weight_Position = filter_number * 9;

    int input_Position = (threadIdx.x * 58)
                       + (threadIdx.y);

    for(int row = 0; row < 3; row++)       // This is the Row Loop
    {
        product += ((Layer6_Neurons_GPU[(filter_number * 58 * 58) + input_Position + (row * 58)] * Layer6_Weights_GPU[weight_Position + (row * 3)])
                + (Layer6_Neurons_GPU[(filter_number * 58 * 58) + input_Position + (row * 58) + 1] * Layer6_Weights_GPU[weight_Position + (row * 3) + 1])
                + (Layer6_Neurons_GPU[(filter_number * 58 * 58) + input_Position + (row * 58) + 2] * Layer6_Weights_GPU[weight_Position + (row * 3) + 2]));
    }

    double Z = (product - Layer6_Mean_GPU[filter_number]) / Layer6_StanDev_GPU[filter_number];
    Z = (Z * Layer6_Gamma_GPU[filter_number]) + Layer6_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer7_Neurons_GPU[output_Position] = Z;
}

__global__ void executeSixthLayer_DSC_partB(double *Layer6_Neurons_GPU,
    double *Layer6_Weights_GPU,
    double *Layer7_Neurons_GPU,
    double *Layer6_Mean_GPU,
    double *Layer6_StanDev_GPU,
    double *Layer6_Gamma_GPU,
    double *Layer6_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 56 * 56)   // channel to work with
                        + (threadIdx.x * 56)
                        + (threadIdx.y + 32);

    int weight_Position = filter_number * 9;

    int input_Position = (threadIdx.x * 58)
                       + (threadIdx.y)
                       + (32);

    for(int row = 0; row < 3; row++)       // This is the Row Loop
    {
        product += ((Layer6_Neurons_GPU[(filter_number * 58 * 58) + input_Position + (row * 58)] * Layer6_Weights_GPU[weight_Position + (row * 3)])
                + (Layer6_Neurons_GPU[(filter_number * 58 * 58) + input_Position + (row * 58) + 1] * Layer6_Weights_GPU[weight_Position + (row * 3) + 1])
                + (Layer6_Neurons_GPU[(filter_number * 58 * 58) + input_Position + (row * 58) + 2] * Layer6_Weights_GPU[weight_Position + (row * 3) + 2]));
    }

    double Z = (product - Layer6_Mean_GPU[filter_number]) / Layer6_StanDev_GPU[filter_number];
    Z = (Z * Layer6_Gamma_GPU[filter_number]) + Layer6_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer7_Neurons_GPU[output_Position] = Z;
}

__global__ void executeSixthLayer_DSC_partC(double *Layer6_Neurons_GPU,
    double *Layer6_Weights_GPU,
    double *Layer7_Neurons_GPU,
    double *Layer6_Mean_GPU,
    double *Layer6_StanDev_GPU,
    double *Layer6_Gamma_GPU,
    double *Layer6_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 56 * 56)   // channel to work with
                        + (56 * 32)
                        + (threadIdx.x * 56)
                        + (threadIdx.y);

    int weight_Position = filter_number * 9;

    int input_Position = (58 * 32)
                       + (threadIdx.x * 58)
                       + (threadIdx.y);

    for(int row = 0; row < 3; row++)       // This is the Row Loop
    {
        product += ((Layer6_Neurons_GPU[(filter_number * 58 * 58) + input_Position + (row * 58)] * Layer6_Weights_GPU[weight_Position + (row * 3)])
                + (Layer6_Neurons_GPU[(filter_number * 58 * 58) + input_Position + (row * 58) + 1] * Layer6_Weights_GPU[weight_Position + (row * 3) + 1])
                + (Layer6_Neurons_GPU[(filter_number * 58 * 58) + input_Position + (row * 58) + 2] * Layer6_Weights_GPU[weight_Position + (row * 3) + 2]));
    }

    double Z = (product - Layer6_Mean_GPU[filter_number]) / Layer6_StanDev_GPU[filter_number];
    Z = (Z * Layer6_Gamma_GPU[filter_number]) + Layer6_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer7_Neurons_GPU[output_Position] = Z;
}

__global__ void executeSixthLayer_DSC_partD(double *Layer6_Neurons_GPU,
    double *Layer6_Weights_GPU,
    double *Layer7_Neurons_GPU,
    double *Layer6_Mean_GPU,
    double *Layer6_StanDev_GPU,
    double *Layer6_Gamma_GPU,
    double *Layer6_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 56 * 56)   // channel to work with
                        + (56 * 32)
                        + 32
                        + (threadIdx.x * 56)
                        + (threadIdx.y);

    int weight_Position = filter_number * 9;

    int input_Position = (58 * 32)
                       + (32)
                       + (threadIdx.x * 58)
                       + (threadIdx.y);

    for(int row = 0; row < 3; row++)       // This is the Row Loop
    {
        product += ((Layer6_Neurons_GPU[(filter_number * 58 * 58) + input_Position + (row * 58)] * Layer6_Weights_GPU[weight_Position + (row * 3)])
                + (Layer6_Neurons_GPU[(filter_number * 58 * 58) + input_Position + (row * 58) + 1] * Layer6_Weights_GPU[weight_Position + (row * 3) + 1])
                + (Layer6_Neurons_GPU[(filter_number * 58 * 58) + input_Position + (row * 58) + 2] * Layer6_Weights_GPU[weight_Position + (row * 3) + 2]));
    }

    double Z = (product - Layer6_Mean_GPU[filter_number]) / Layer6_StanDev_GPU[filter_number];
    Z = (Z * Layer6_Gamma_GPU[filter_number]) + Layer6_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer7_Neurons_GPU[output_Position] = Z;
}

/*  *************************************************** SIXTH LAYER END **************************************************** */

/*  *************************************************** SEVENTH LAYER START ************************************************ */
/*
    Layer 7: Pointwise Separable Convolution Layer
    Input: 56 * 56 * 128
    Weight: 1 * 1 * 128 * 128 with a Stride of 1
    Output: 57 * 57 * 128  (Padding for the next layer is handled in this layer itself)
*/
__global__ void executeSeventhLayer_PSC_partA(double *Layer7_Neurons_GPU,
    double *Layer7_Weights_GPU,
    double *Layer8_Neurons_GPU,
    double *Layer7_Mean_GPU,
    double *Layer7_StanDev_GPU,
    double *Layer7_Gamma_GPU,
    double *Layer7_Beta_GPU
)
{
    double product = 0.0;

    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 57 * 57)   // channel to work with
                        + (threadIdx.x * 57)
                        + (threadIdx.y);

    int weight_Position = filter_number * 128;

    int input_Position = (threadIdx.x * 56)
                       + (threadIdx.y);

    for(int channel = 0; channel < 128; channel++)       // This is the channel loop as we have 32 channels to work with
    {
        product += (Layer7_Neurons_GPU[(channel * 56 * 56) + input_Position] * Layer7_Weights_GPU[weight_Position + channel]);
    }

    double Z = (product - Layer7_Mean_GPU[filter_number]) / Layer7_StanDev_GPU[filter_number];
    Z = (Z * Layer7_Gamma_GPU[filter_number]) + Layer7_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer8_Neurons_GPU[output_Position] = Z;
}

__global__ void executeSeventhLayer_PSC_partB(double *Layer7_Neurons_GPU,
    double *Layer7_Weights_GPU,
    double *Layer8_Neurons_GPU,
    double *Layer7_Mean_GPU,
    double *Layer7_StanDev_GPU,
    double *Layer7_Gamma_GPU,
    double *Layer7_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 57 * 57)   // channel to work with
                        + (threadIdx.x * 57)
                        + (threadIdx.y + 32);

    int weight_Position = filter_number * 128;

    int input_Position = (threadIdx.x * 56)
                       + (threadIdx.y)
                       + (32);

    for(int channel = 0; channel < 128 ; channel++)       // This is the channel loop as we have 32 channels to work with
    {
        product += (Layer7_Neurons_GPU[(channel * 56 * 56) + input_Position] * Layer7_Weights_GPU[weight_Position + channel]);
    }

    double Z = (product - Layer7_Mean_GPU[filter_number]) / Layer7_StanDev_GPU[filter_number];
    Z = (Z * Layer7_Gamma_GPU[filter_number]) + Layer7_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer8_Neurons_GPU[output_Position] = Z;
}

__global__ void executeSeventhLayer_PSC_partC(double *Layer7_Neurons_GPU,
    double *Layer7_Weights_GPU,
    double *Layer8_Neurons_GPU,
    double *Layer7_Mean_GPU,
    double *Layer7_StanDev_GPU,
    double *Layer7_Gamma_GPU,
    double *Layer7_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 57 * 57)   // channel to work with
                        + (57 * 32)
                        + (threadIdx.x * 57)
                        + (threadIdx.y);

    int weight_Position = filter_number * 128;

    int input_Position = (56 * 32)
                       + (threadIdx.x * 56)
                       + (threadIdx.y);

    for(int channel = 0; channel < 128 ; channel++)       // This is the channel loop as we have 32 channels to work with
    {
        product += (Layer7_Neurons_GPU[(channel * 56 * 56) + input_Position] * Layer7_Weights_GPU[weight_Position + channel]);
    }

    double Z = (product - Layer7_Mean_GPU[filter_number]) / Layer7_StanDev_GPU[filter_number];
    Z = (Z * Layer7_Gamma_GPU[filter_number]) + Layer7_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer8_Neurons_GPU[output_Position] = Z;
}

__global__ void executeSeventhLayer_PSC_partD(double *Layer7_Neurons_GPU,
    double *Layer7_Weights_GPU,
    double *Layer8_Neurons_GPU,
    double *Layer7_Mean_GPU,
    double *Layer7_StanDev_GPU,
    double *Layer7_Gamma_GPU,
    double *Layer7_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 57 * 57)   // channel to work with
                        + (57 * 32)
                        + 32
                        + (threadIdx.x * 57)
                        + (threadIdx.y);

    int weight_Position = filter_number * 128;

    int input_Position = (56 * 32)
                       + (32)
                       + (threadIdx.x * 56)
                       + (threadIdx.y);

    for(int channel = 0; channel < 128 ; channel++)       // This is the channel loop as we have 32 channels to work with
    {
        product += (Layer7_Neurons_GPU[(channel * 56 * 56) + input_Position] * Layer7_Weights_GPU[weight_Position + channel]);
    }

    double Z = (product - Layer7_Mean_GPU[filter_number]) / Layer7_StanDev_GPU[filter_number];
    Z = (Z * Layer7_Gamma_GPU[filter_number]) + Layer7_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer8_Neurons_GPU[output_Position] = Z;
}

/*  *************************************************** SEVENTH LAYER END **************************************************** */

/*  *************************************************** EIGHTH LAYER START ************************************************** */
/*
    Layer 8: Depthwise Separable Convolution Layer
    Input: 57 * 57 * 128
    Weight: 3 * 3 * 128  with a Stride of 2
    Output: 28 * 28 * 128
*/
__global__ void executeEighthLayer_DSC(double *Layer8_Neurons_GPU,
    double *Layer8_Weights_GPU,
    double *Layer9_Neurons_GPU,
    double *Layer8_Mean_GPU,
    double *Layer8_StanDev_GPU,
    double *Layer8_Gamma_GPU,
    double *Layer8_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;
    int stride = 2;

    // Output position
    int output_Position = (filter_number * 28 * 28)   // channel to work with
                        + (threadIdx.x * 28)
                        + (threadIdx.y);

    int weight_Position = filter_number * 9;

    int input_Position = (threadIdx.x * 57 * stride)
                       + (threadIdx.y * stride);

    for(int row = 0; row < 3; row++)       // This is the Row Loop
    {
        product += ((Layer8_Neurons_GPU[(filter_number * 57 * 57) + input_Position + (row * 57)] * Layer8_Weights_GPU[weight_Position + (row * 3)])
                + (Layer8_Neurons_GPU[(filter_number * 57 * 57) + input_Position + (row * 57) + 1] * Layer8_Weights_GPU[weight_Position + (row * 3) + 1])
                + (Layer8_Neurons_GPU[(filter_number * 57 * 57) + input_Position + (row * 57) + 2] * Layer8_Weights_GPU[weight_Position + (row * 3) + 2]));
    }

    double Z = (product - Layer8_Mean_GPU[filter_number]) / Layer8_StanDev_GPU[filter_number];
    Z = (Z * Layer8_Gamma_GPU[filter_number]) + Layer8_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer9_Neurons_GPU[output_Position] = Z;
}

/*  *************************************************** EIGHTH LAYER END **************************************************** */

/*  *************************************************** NINTH LAYER START ************************************************** */
/*
    Layer 9: Pointwise Separable Convolution Layer
    Input: 28 * 28 * 128
    Weight: 1 * 1 * 128 * 256  with a Stride of 1
    Output: 30 * 30 * 256 (Handling the padding for the next layer)
*/
__global__ void executeNinthLayer_PSC(double *Layer9_Neurons_GPU,
    double *Layer9_Weights_GPU,
    double *Layer10_Neurons_GPU,
    double *Layer9_Mean_GPU,
    double *Layer9_StanDev_GPU,
    double *Layer9_Gamma_GPU,
    double *Layer9_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;
    int offset = 31;

    // Output position
    int output_Position = (filter_number * 30 * 30)   // channel to work with
                        + (threadIdx.x * 30)
                        + (threadIdx.y);

    int weight_Position = filter_number * 128;

    int input_Position = (threadIdx.x * 28)
                        + (threadIdx.y);

    for(int channel = 0; channel < 128; channel++)       // This is the channel loop as we have 32 channels to work with
    {
        product += (Layer9_Neurons_GPU[(channel * 28 * 28) + input_Position] * Layer9_Weights_GPU[weight_Position + channel]);
    }

    double Z = (product - Layer9_Mean_GPU[filter_number]) / Layer9_StanDev_GPU[filter_number];
    Z = (Z * Layer9_Gamma_GPU[filter_number]) + Layer9_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer10_Neurons_GPU[output_Position + offset] = Z;
}

/*  *************************************************** NINTH LAYER END **************************************************** */

/*  *************************************************** TENTH LAYER START ************************************************** */
/*
    Layer 10: Depthwise Separable Convolution Layer
    Input: 30 * 30 * 256
    Weight: 3 * 3 * 256  with a Stride of 1
    Output: 28 * 28 * 256
*/
__global__ void executeTenthLayer_DSC(double *Layer10_Neurons_GPU,
    double *Layer10_Weights_GPU,
    double *Layer11_Neurons_GPU,
    double *Layer10_Mean_GPU,
    double *Layer10_StanDev_GPU,
    double *Layer10_Gamma_GPU,
    double *Layer10_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 28 * 28)   // channel to work with
                        + (threadIdx.x * 28)
                        + (threadIdx.y);

    int weight_Position = filter_number * 9;

    int input_Position = (threadIdx.x * 30)
                       + (threadIdx.y);

    for(int row = 0; row < 3; row++)       // This is the Row Loop
    {
        product += ((Layer10_Neurons_GPU[(filter_number * 30 * 30) + input_Position + (row * 30)] * Layer10_Weights_GPU[weight_Position + (row * 3)])
                + (Layer10_Neurons_GPU[(filter_number * 30 * 30) + input_Position + (row * 30) + 1] * Layer10_Weights_GPU[weight_Position + (row * 3) + 1])
                + (Layer10_Neurons_GPU[(filter_number * 30 * 30) + input_Position + (row * 30) + 2] * Layer10_Weights_GPU[weight_Position + (row * 3) + 2]));
    }

    double Z = (product - Layer10_Mean_GPU[filter_number]) / Layer10_StanDev_GPU[filter_number];
    Z = (Z * Layer10_Gamma_GPU[filter_number]) + Layer10_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer11_Neurons_GPU[output_Position] = Z;
}

/*  *************************************************** TENTH LAYER END **************************************************** */

/*  *************************************************** ELEVENTH LAYER START ************************************************** */
/*
    Layer 11: Pointwise Separable Convolution Layer
    Input: 28 * 28 * 256
    Weight: 1 * 1 * 256 * 256  with a Stride of 1
    Output: 29 * 29 * 256  (Padding for the next layer is handled in this layer itself)
*/
__global__ void executeEleventhLayer_PSC(double *Layer11_Neurons_GPU,
    double *Layer11_Weights_GPU,
    double *Layer12_Neurons_GPU,
    double *Layer11_Mean_GPU,
    double *Layer11_StanDev_GPU,
    double *Layer11_Gamma_GPU,
    double *Layer11_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 29 * 29)   // channel to work with
                        + (threadIdx.x * 29)
                        + (threadIdx.y);

    int weight_Position = filter_number * 256;

    int input_Position = (threadIdx.x * 28)
                        + (threadIdx.y);

    for(int channel = 0; channel < 256; channel++)       // This is the channel loop as we have 32 channels to work with
    {
        product += (Layer11_Neurons_GPU[(channel * 28 * 28) + input_Position] * Layer11_Weights_GPU[weight_Position + channel]);
    }

    double Z = (product - Layer11_Mean_GPU[filter_number]) / Layer11_StanDev_GPU[filter_number];
    Z = (Z * Layer11_Gamma_GPU[filter_number]) + Layer11_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer12_Neurons_GPU[output_Position] = Z;
}

/*  *************************************************** ELEVENTH LAYER END **************************************************** */

/*  *************************************************** TWELFTH LAYER START ************************************************** */
/*
    Layer 12: Depthwise Separable Convolution Layer
    Input: 29 * 29 * 256
    Weight: 3 * 3 * 256 with a Stride of 2
    Output: 14 * 14 * 256
*/
__global__ void executeTwelfthLayer_DSC(double *Layer12_Neurons_GPU,
    double *Layer12_Weights_GPU,
    double *Layer13_Neurons_GPU,
    double *Layer12_Mean_GPU,
    double *Layer12_StanDev_GPU,
    double *Layer12_Gamma_GPU,
    double *Layer12_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;
    int stride = 2;

    // Output position
    int output_Position = (filter_number * 14 * 14)   // channel to work with
                        + (threadIdx.x * 14)
                        + (threadIdx.y);

    int weight_Position = filter_number * 9;

    int input_Position = (threadIdx.x * 29 * stride)
                       + (threadIdx.y * stride);

    for(int row = 0; row < 3; row++)       // This is the Row Loop
    {
        product += ((Layer12_Neurons_GPU[(filter_number * 29 * 29) + input_Position + (row * 29)] * Layer12_Weights_GPU[weight_Position + (row * 3)])
                + (Layer12_Neurons_GPU[(filter_number * 29 * 29) + input_Position + (row * 29) + 1] * Layer12_Weights_GPU[weight_Position + (row * 3) + 1])
                + (Layer12_Neurons_GPU[(filter_number * 29 * 29) + input_Position + (row * 29) + 2] * Layer12_Weights_GPU[weight_Position + (row * 3) + 2]));
    }

    double Z = (product - Layer12_Mean_GPU[filter_number]) / Layer12_StanDev_GPU[filter_number];
    Z = (Z * Layer12_Gamma_GPU[filter_number]) + Layer12_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer13_Neurons_GPU[output_Position] = Z;
}

/*  *************************************************** TWELFTH LAYER END **************************************************** */

/*  *************************************************** THIRTEENTH LAYER START ************************************************** */
/*
    Layer 13: Pointwise Separable Convolution Layer
    Input: 14 * 14 * 256
    Weight: 1 * 1 * 256 * 512 with a Stride of 1
    Output: 16 * 16 * 512  (Handling padding for next layer)
*/
__global__ void executeThirteenthLayer_PSC(double *Layer13_Neurons_GPU,
    double *Layer13_Weights_GPU,
    double *Layer14_Neurons_GPU,
    double *Layer13_Mean_GPU,
    double *Layer13_StanDev_GPU,
    double *Layer13_Gamma_GPU,
    double *Layer13_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;
    int offset = 17;

    // Output position
    int output_Position = (filter_number * 16 * 16)   // channel to work with
                        + (threadIdx.x * 16)
                        + (threadIdx.y);

    int weight_Position = filter_number * 256;

    int input_Position = (threadIdx.x * 14)
                        + (threadIdx.y);

    for(int channel = 0; channel < 256; channel++)       // This is the channel loop as we have 32 channels to work with
    {
        product += (Layer13_Neurons_GPU[(channel * 14 * 14) + input_Position] * Layer13_Weights_GPU[weight_Position + channel]);
    }

    double Z = (product - Layer13_Mean_GPU[filter_number]) / Layer13_StanDev_GPU[filter_number];
    Z = (Z * Layer13_Gamma_GPU[filter_number]) + Layer13_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer14_Neurons_GPU[output_Position + offset] = Z;
}

/*  *************************************************** THIRTEENTH LAYER END **************************************************** */

/*  *************************************************** FOURTEENTH LAYER START ************************************************** */
/*
    Layer 14: Depthwise Separable Convolution Layer
    Input: 16 * 16 * 512
    Weight: 3 * 3 * 512 with a Stride of 1
    Output: 14 * 14 * 512  (Handling padding for next layer)
*/
__global__ void executeFourteenthLayer_DSC(double *Layer14_Neurons_GPU,
    double *Layer14_Weights_GPU,
    double *Layer15_Neurons_GPU,
    double *Layer14_Mean_GPU,
    double *Layer14_StanDev_GPU,
    double *Layer14_Gamma_GPU,
    double *Layer14_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 14 * 14)   // channel to work with
                        + (threadIdx.x * 14)
                        + (threadIdx.y);

    int weight_Position = filter_number * 9;

    int input_Position = (threadIdx.x * 16)
                       + (threadIdx.y);

    for(int row = 0; row < 3; row++)       // This is the Row Loop
    {
        product += ((Layer14_Neurons_GPU[(filter_number * 16 * 16) + input_Position + (row * 16)] * Layer14_Weights_GPU[weight_Position + (row * 3)])
                + (Layer14_Neurons_GPU[(filter_number * 16 * 16) + input_Position + (row * 16) + 1] * Layer14_Weights_GPU[weight_Position + (row * 3) + 1])
                + (Layer14_Neurons_GPU[(filter_number * 16 * 16) + input_Position + (row * 16) + 2] * Layer14_Weights_GPU[weight_Position + (row * 3) + 2]));
    }

    double Z = (product - Layer14_Mean_GPU[filter_number]) / Layer14_StanDev_GPU[filter_number];
    Z = (Z * Layer14_Gamma_GPU[filter_number]) + Layer14_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer15_Neurons_GPU[output_Position] = Z;
}

/*  *************************************************** FOURTEENTH LAYER END **************************************************** */

/*  *************************************************** FIFTEENTH LAYER START ************************************************** */
/*
    Layer 15: Pointwise Separable Convolution Layer
    Input: 14 * 14 * 512
    Weight: 1 * 1 * 512 * 512 with a Stride of 1
    Output: 16 * 16 * 512  (Handling padding for next layer)
*/
__global__ void executeFifteenthLayer_PSC(double *Layer15_Neurons_GPU,
    double *Layer15_Weights_GPU,
    double *Layer16_Neurons_GPU,
    double *Layer15_Mean_GPU,
    double *Layer15_StanDev_GPU,
    double *Layer15_Gamma_GPU,
    double *Layer15_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;
    int offset = 17;

    // Output position
    int output_Position = (filter_number * 16 * 16)   // channel to work with
                        + (threadIdx.x * 16)
                        + (threadIdx.y);

    int weight_Position = filter_number * 512;

    int input_Position = (threadIdx.x * 14)
                        + (threadIdx.y);

    for(int channel = 0; channel < 512 ; channel++)       // This is the channel loop as we have 32 channels to work with
    {
        product += (Layer15_Neurons_GPU[(channel * 14 * 14) + input_Position] * Layer15_Weights_GPU[weight_Position + channel]);
    }

    double Z = (product - Layer15_Mean_GPU[filter_number]) / Layer15_StanDev_GPU[filter_number];
    Z = (Z * Layer15_Gamma_GPU[filter_number]) + Layer15_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer16_Neurons_GPU[output_Position + offset] = Z;
}

/*  *************************************************** FIFTEENTH LAYER END **************************************************** */

/*  *************************************************** SIXTEENTH LAYER START ************************************************** */
/*
    Layer 16: Depthwise Separable Convolution Layer
    Input: 16 * 16 * 512
    Weight: 3 * 3 * 512 with a Stride of 1
    Output: 14 * 14 * 512  (Handling padding for next layer)
*/
__global__ void executeSixteenthLayer_DSC(double *Layer16_Neurons_GPU,
    double *Layer16_Weights_GPU,
    double *Layer17_Neurons_GPU,
    double *Layer16_Mean_GPU,
    double *Layer16_StanDev_GPU,
    double *Layer16_Gamma_GPU,
    double *Layer16_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 14 * 14)   // channel to work with
                        + (threadIdx.x * 14)
                        + (threadIdx.y);

    int weight_Position = filter_number * 9;

    int input_Position = (threadIdx.x * 16)
                       + (threadIdx.y);

    for(int row = 0; row < 3; row++)       // This is the Row Loop
    {
        product += ((Layer16_Neurons_GPU[(filter_number * 16 * 16) + input_Position + (row * 16)] * Layer16_Weights_GPU[weight_Position + (row * 3)])
                + (Layer16_Neurons_GPU[(filter_number * 16 * 16) + input_Position + (row * 16) + 1] * Layer16_Weights_GPU[weight_Position + (row * 3) + 1])
                + (Layer16_Neurons_GPU[(filter_number * 16 * 16) + input_Position + (row * 16) + 2] * Layer16_Weights_GPU[weight_Position + (row * 3) + 2]));
    }

    double Z = (product - Layer16_Mean_GPU[filter_number]) / Layer16_StanDev_GPU[filter_number];
    Z = (Z * Layer16_Gamma_GPU[filter_number]) + Layer16_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer17_Neurons_GPU[output_Position] = Z;
}

/*  *************************************************** SIXTEENTH LAYER END **************************************************** */

/*  *************************************************** SEVENTEENTH LAYER START ************************************************** */
/*
    Layer 17: Pointwise Separable Convolution Layer
    Input: 14 * 14 * 512
    Weight: 1 * 1 * 512 * 512 with a Stride of 1
    Output: 16 * 16 * 512  (Handling padding for next layer)
*/
__global__ void executeSeventeenthLayer_PSC(double *Layer17_Neurons_GPU,
    double *Layer17_Weights_GPU,
    double *Layer18_Neurons_GPU,
    double *Layer17_Mean_GPU,
    double *Layer17_StanDev_GPU,
    double *Layer17_Gamma_GPU,
    double *Layer17_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;
    int offset = 17;

    // Output position
    int output_Position = (filter_number * 16 * 16)   // channel to work with
                        + (threadIdx.x * 16)
                        + (threadIdx.y);

    int weight_Position = filter_number * 512;

    int input_Position = (threadIdx.x * 14)
                        + (threadIdx.y);

    for(int channel = 0; channel < 512 ; channel++)       // This is the channel loop as we have 32 channels to work with
    {
        product += (Layer17_Neurons_GPU[(channel * 14 * 14) + input_Position] * Layer17_Weights_GPU[weight_Position + channel]);
    }

    double Z = (product - Layer17_Mean_GPU[filter_number]) / Layer17_StanDev_GPU[filter_number];
    Z = (Z * Layer17_Gamma_GPU[filter_number]) + Layer17_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer18_Neurons_GPU[output_Position + offset] = Z;
}

/*  *************************************************** SEVENTEENTH LAYER END **************************************************** */

/*  *************************************************** EIGHTEENTH LAYER START ************************************************** */
/*
    Layer 18: Depthwise Separable Convolution Layer
    Input: 16 * 16 * 512
    Weight: 3 * 3 * 512 with a Stride of 1
    Output: 14 * 14 * 512
*/
__global__ void executeEighteenthLayer_DSC(double *Layer18_Neurons_GPU,
    double *Layer18_Weights_GPU,
    double *Layer19_Neurons_GPU,
    double *Layer18_Mean_GPU,
    double *Layer18_StanDev_GPU,
    double *Layer18_Gamma_GPU,
    double *Layer18_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 14 * 14)   // channel to work with
                        + (threadIdx.x * 14)
                        + (threadIdx.y);

    int weight_Position = filter_number * 9;

    int input_Position = (threadIdx.x * 16)
                       + (threadIdx.y);

    for(int row = 0; row < 3; row++)       // This is the Row Loop
    {
        product += ((Layer18_Neurons_GPU[(filter_number * 16 * 16) + input_Position + (row * 16)] * Layer18_Weights_GPU[weight_Position + (row * 3)])
                + (Layer18_Neurons_GPU[(filter_number * 16 * 16) + input_Position + (row * 16) + 1] * Layer18_Weights_GPU[weight_Position + (row * 3) + 1])
                + (Layer18_Neurons_GPU[(filter_number * 16 * 16) + input_Position + (row * 16) + 2] * Layer18_Weights_GPU[weight_Position + (row * 3) + 2]));
    }

    double Z = (product - Layer18_Mean_GPU[filter_number]) / Layer18_StanDev_GPU[filter_number];
    Z = (Z * Layer18_Gamma_GPU[filter_number]) + Layer18_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer19_Neurons_GPU[output_Position] = Z;
}

/*  *************************************************** EIGHTEENTH LAYER END **************************************************** */

/*  *************************************************** NINETEENTH LAYER START ************************************************** */
/*
    Layer 19: Pointwise Separable Convolution Layer
    Input: 14 * 14 * 512
    Weight: 1 * 1 * 512 * 512 with a Stride of 1
    Output: 16 * 16 * 512  (Handling padding for next layer)
*/
__global__ void executeNineteenthLayer_PSC(double *Layer19_Neurons_GPU,
    double *Layer19_Weights_GPU,
    double *Layer20_Neurons_GPU,
    double *Layer19_Mean_GPU,
    double *Layer19_StanDev_GPU,
    double *Layer19_Gamma_GPU,
    double *Layer19_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;
    int offset = 17;

    // Output position
    int output_Position = (filter_number * 16 * 16)   // channel to work with
                        + (threadIdx.x * 16)
                        + (threadIdx.y);

    int weight_Position = filter_number * 512;

    int input_Position = (threadIdx.x * 14)
                        + (threadIdx.y);

    for(int channel = 0; channel < 512 ; channel++)       // This is the channel loop as we have 32 channels to work with
    {
        product += (Layer19_Neurons_GPU[(channel * 14 * 14) + input_Position] * Layer19_Weights_GPU[weight_Position + channel]);
    }

    double Z = (product - Layer19_Mean_GPU[filter_number]) / Layer19_StanDev_GPU[filter_number];
    Z = (Z * Layer19_Gamma_GPU[filter_number]) + Layer19_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer20_Neurons_GPU[output_Position + offset] = Z;
}

/*  *************************************************** NINETEENTH LAYER END **************************************************** */

/*  *************************************************** TWENTY LAYER START ************************************************** */
/*
    Layer 20: Depthwise Separable Convolution Layer
    Input: 16 * 16 * 512
    Weight: 3 * 3 * 512 with a Stride of 1
    Output: 14 * 14 * 512
*/
__global__ void executeTwentyLayer_DSC(double *Layer20_Neurons_GPU,
    double *Layer20_Weights_GPU,
    double *Layer21_Neurons_GPU,
    double *Layer20_Mean_GPU,
    double *Layer20_StanDev_GPU,
    double *Layer20_Gamma_GPU,
    double *Layer20_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 14 * 14)   // channel to work with
                        + (threadIdx.x * 14)
                        + (threadIdx.y);

    int weight_Position = filter_number * 9;

    int input_Position = (threadIdx.x * 16)
                       + (threadIdx.y);

    for(int row = 0; row < 3; row++)       // This is the Row Loop
    {
        product += ((Layer20_Neurons_GPU[(filter_number * 16 * 16) + input_Position + (row * 16)] * Layer20_Weights_GPU[weight_Position + (row * 3)])
                + (Layer20_Neurons_GPU[(filter_number * 16 * 16) + input_Position + (row * 16) + 1] * Layer20_Weights_GPU[weight_Position + (row * 3) + 1])
                + (Layer20_Neurons_GPU[(filter_number * 16 * 16) + input_Position + (row * 16) + 2] * Layer20_Weights_GPU[weight_Position + (row * 3) + 2]));
    }

    double Z = (product - Layer20_Mean_GPU[filter_number]) / Layer20_StanDev_GPU[filter_number];
    Z = (Z * Layer20_Gamma_GPU[filter_number]) + Layer20_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer21_Neurons_GPU[output_Position] = Z;
}
/*  *************************************************** TWENTY LAYER END **************************************************** */

/*  *************************************************** TWENTYONE LAYER START ************************************************** */
/*
    Layer 21: Pointwise Separable Convolution Layer
    Input: 14 * 14 * 512
    Weight: 1 * 1 * 512 * 512 with a Stride of 1
    Output: 16 * 16 * 512  (Handling padding for next layer)
*/
__global__ void executeTwentyOneLayer_PSC(double *Layer21_Neurons_GPU,
    double *Layer21_Weights_GPU,
    double *Layer22_Neurons_GPU,
    double *Layer21_Mean_GPU,
    double *Layer21_StanDev_GPU,
    double *Layer21_Gamma_GPU,
    double *Layer21_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;
    int offset = 17;

    // Output position
    int output_Position = (filter_number * 16 * 16)   // channel to work with
                        + (threadIdx.x * 16)
                        + (threadIdx.y);

    int weight_Position = filter_number * 512;

    int input_Position = (threadIdx.x * 14)
                        + (threadIdx.y);

    for(int channel = 0; channel < 512 ; channel++)       // This is the channel loop as we have 32 channels to work with
    {
        product += (Layer21_Neurons_GPU[(channel * 14 * 14) + input_Position] * Layer21_Weights_GPU[weight_Position + channel]);
    }

    double Z = (product - Layer21_Mean_GPU[filter_number]) / Layer21_StanDev_GPU[filter_number];
    Z = (Z * Layer21_Gamma_GPU[filter_number]) + Layer21_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer22_Neurons_GPU[output_Position + offset] = Z;
}

/*  *************************************************** TWENTYONE LAYER END **************************************************** */

/*  *************************************************** TWENTYTWO LAYER START ************************************************** */
/*
    Layer 22: Depthwise Separable Convolution Layer
    Input: 16 * 16 * 512
    Weight: 3 * 3 * 512 with a Stride of 1
    Output: 14 * 14 * 512
*/
__global__ void executeTwentyTwoLayer_DSC(double *Layer22_Neurons_GPU,
    double *Layer22_Weights_GPU,
    double *Layer23_Neurons_GPU,
    double *Layer22_Mean_GPU,
    double *Layer22_StanDev_GPU,
    double *Layer22_Gamma_GPU,
    double *Layer22_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 14 * 14)   // channel to work with
                        + (threadIdx.x * 14)
                        + (threadIdx.y);

    int weight_Position = filter_number * 9;

    int input_Position = (threadIdx.x * 16)
                       + (threadIdx.y);

    for(int row = 0; row < 3; row++)       // This is the Row Loop
    {
        product += ((Layer22_Neurons_GPU[(filter_number * 16 * 16) + input_Position + (row * 16)] * Layer22_Weights_GPU[weight_Position + (row * 3)])
                + (Layer22_Neurons_GPU[(filter_number * 16 * 16) + input_Position + (row * 16) + 1] * Layer22_Weights_GPU[weight_Position + (row * 3) + 1])
                + (Layer22_Neurons_GPU[(filter_number * 16 * 16) + input_Position + (row * 16) + 2] * Layer22_Weights_GPU[weight_Position + (row * 3) + 2]));
    }

    double Z = (product - Layer22_Mean_GPU[filter_number]) / Layer22_StanDev_GPU[filter_number];
    Z = (Z * Layer22_Gamma_GPU[filter_number]) + Layer22_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer23_Neurons_GPU[output_Position] = Z;
}
/*  *************************************************** TWENTYTWO LAYER END **************************************************** */

/*  *************************************************** TWENTYTHREE LAYER START ************************************************** */
/*
    Layer 23: Pointwise Separable Convolution Layer
    Input: 14 * 14 * 512
    Weight: 1 * 1 * 512 * 512 with a Stride of 1
    Output: 14 * 14 * 512  (Handling padding for next layer)
*/
__global__ void executeTwentyThreeLayer_PSC(double *Layer23_Neurons_GPU,
    double *Layer23_Weights_GPU,
    double *Layer24_Neurons_GPU,
    double *Layer23_Mean_GPU,
    double *Layer23_StanDev_GPU,
    double *Layer23_Gamma_GPU,
    double *Layer23_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 15 * 15)   // channel to work with
                        + (threadIdx.x * 15)
                        + (threadIdx.y);

    int weight_Position = filter_number * 512;

    int input_Position = (threadIdx.x * 14)
                        + (threadIdx.y);

    for(int channel = 0; channel < 512 ; channel++)       // This is the channel loop as we have 32 channels to work with
    {
        product += (Layer23_Neurons_GPU[(channel * 14 * 14) + input_Position] * Layer23_Weights_GPU[weight_Position + channel]);
    }

    double Z = (product - Layer23_Mean_GPU[filter_number]) / Layer23_StanDev_GPU[filter_number];
    Z = (Z * Layer23_Gamma_GPU[filter_number]) + Layer23_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer24_Neurons_GPU[output_Position] = Z;
}
/*  *************************************************** TWENTYTHREE LAYER END **************************************************** */

/*  *************************************************** TWENTYFOUR LAYER START ************************************************** */
/*
    Layer 24: Depthwise Separable Convolution Layer
    Input: 15 * 15 * 512
    Weight: 3 * 3 * 512 with a Stride of 2
    Output: 14 * 14 * 512  (Handling padding for next layer)
*/
__global__ void executeTwentyFourLayer_DSC(double *Layer24_Neurons_GPU,
    double *Layer24_Weights_GPU,
    double *Layer25_Neurons_GPU,
    double *Layer24_Mean_GPU,
    double *Layer24_StanDev_GPU,
    double *Layer24_Gamma_GPU,
    double *Layer24_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;
    int stride = 2;

    // Output position
    int output_Position = (filter_number * 7 * 7)   // channel to work with
                        + (threadIdx.x * 7)
                        + (threadIdx.y);

    int weight_Position = filter_number * 9;

    int input_Position = (threadIdx.x * 15 * stride)
                       + (threadIdx.y * stride);

    for(int row = 0; row < 3; row++)       // This is the Row Loop
    {
        product += ((Layer24_Neurons_GPU[(filter_number * 15 * 15) + input_Position + (row * 15)] * Layer24_Weights_GPU[weight_Position + (row * 3)])
                + (Layer24_Neurons_GPU[(filter_number * 15 * 15) + input_Position + (row * 15) + 1] * Layer24_Weights_GPU[weight_Position + (row * 3) + 1])
                + (Layer24_Neurons_GPU[(filter_number * 15 * 15) + input_Position + (row * 15) + 2] * Layer24_Weights_GPU[weight_Position + (row * 3) + 2]));
    }

    double Z = (product - Layer24_Mean_GPU[filter_number]) / Layer24_StanDev_GPU[filter_number];
    Z = (Z * Layer24_Gamma_GPU[filter_number]) + Layer24_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer25_Neurons_GPU[output_Position] = Z;
}
/*  *************************************************** TWENTYFOUR LAYER END **************************************************** */

/*  *************************************************** TWENTYFIVE LAYER START ************************************************** */
/*
    Layer 25: Pointwise Separable Convolution Layer
    Input: 7 * 7 * 512
    Weight: 1 * 1 * 512 * 1024 with a Stride of 1
    Output: 9 * 9 * 1024 (Handling padding for next layer)
*/
__global__ void executeTwentyFiveLayer_PSC(double *Layer25_Neurons_GPU,
    double *Layer25_Weights_GPU,
    double *Layer26_Neurons_GPU,
    double *Layer25_Mean_GPU,
    double *Layer25_StanDev_GPU,
    double *Layer25_Gamma_GPU,
    double *Layer25_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;
    int offset = 10;

    // Output position
    int output_Position = (filter_number * 9 * 9)   // channel to work with
                        + (threadIdx.x * 9)
                        + (threadIdx.y);

    int weight_Position = filter_number * 512;

    int input_Position = (threadIdx.x * 7)
                        + (threadIdx.y);

    for(int channel = 0; channel < 512 ; channel++)
    {
        product += (Layer25_Neurons_GPU[(channel * 7 * 7) + input_Position] * Layer25_Weights_GPU[weight_Position + channel]);
    }

    double Z = (product - Layer25_Mean_GPU[filter_number]) / Layer25_StanDev_GPU[filter_number];
    Z = (Z * Layer25_Gamma_GPU[filter_number]) + Layer25_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer26_Neurons_GPU[output_Position + offset] = Z;
}
/*  *************************************************** TWENTYFIVE LAYER END **************************************************** */

/*  *************************************************** TWENTYSIX LAYER START ************************************************** */
/*
    Layer 26: Depthwise Separable Convolution Layer
    Input: 9 * 9 * 1024
    Weight: 3 * 3 * 1024 with a Stride of 1
    Output: 7 * 7 * 1024  (Handling padding for next layer)
*/
__global__ void executeTwentySixLayer_DSC(double *Layer26_Neurons_GPU,
    double *Layer26_Weights_GPU,
    double *Layer27_Neurons_GPU,
    double *Layer26_Mean_GPU,
    double *Layer26_StanDev_GPU,
    double *Layer26_Gamma_GPU,
    double *Layer26_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 7 * 7)   // channel to work with
                        + (threadIdx.x * 7)
                        + (threadIdx.y);

    int weight_Position = filter_number * 9;

    int input_Position = (threadIdx.x * 9)
                       + (threadIdx.y);

    for(int row = 0; row < 3; row++)       // This is the Row Loop
    {
        product += ((Layer26_Neurons_GPU[(filter_number * 9 * 9) + input_Position + (row * 9)] * Layer26_Weights_GPU[weight_Position + (row * 3)])
                + (Layer26_Neurons_GPU[(filter_number * 9 * 9) + input_Position + (row * 9) + 1] * Layer26_Weights_GPU[weight_Position + (row * 3) + 1])
                + (Layer26_Neurons_GPU[(filter_number * 9 * 9) + input_Position + (row * 9) + 2] * Layer26_Weights_GPU[weight_Position + (row * 3) + 2]));
    }

    double Z = (product - Layer26_Mean_GPU[filter_number]) / Layer26_StanDev_GPU[filter_number];
    Z = (Z * Layer26_Gamma_GPU[filter_number]) + Layer26_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer27_Neurons_GPU[output_Position] = Z;
}
/*  *************************************************** TWENTYSIX LAYER END **************************************************** */

/*  *************************************************** TWENTYSEVEN LAYER START ************************************************** */
/*
    Layer 27: Pointwise Separable Convolution Layer
    Input: 7 * 7 * 1024
    Weight: 1 * 1 * 1024 * 1024 with a Stride of 1
    Output: 7 * 7 * 1024
*/
__global__ void executeTwentySevenLayer_PSC(double *Layer27_Neurons_GPU,
    double *Layer27_Weights_GPU,
    double *Layer28_Neurons_GPU,
    double *Layer27_Mean_GPU,
    double *Layer27_StanDev_GPU,
    double *Layer27_Gamma_GPU,
    double *Layer27_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 7 * 7)   // channel to work with
                        + (threadIdx.x * 7)
                        + (threadIdx.y);

    int weight_Position = filter_number * 1024;

    int input_Position = (threadIdx.x * 7)
                        + (threadIdx.y);

    for(int channel = 0; channel < 1024 ; channel++)
    {
        product += (Layer27_Neurons_GPU[(channel * 7 * 7) + input_Position] * Layer27_Weights_GPU[weight_Position + channel]);
    }

    double Z = (product - Layer27_Mean_GPU[filter_number]) / Layer27_StanDev_GPU[filter_number];
    Z = (Z * Layer27_Gamma_GPU[filter_number]) + Layer27_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer28_Neurons_GPU[output_Position] = Z;
}
/*  *************************************************** TWENTYSEVEN LAYER END **************************************************** */

/*  *************************************************** TWENTYEIGHT LAYER START ************************************************** */
/*
    Layer 28: Global Average Pooling Layer
    Input: 7 * 7 * 1024
    Weight: None
    Output: 1 * 1 * 1024
*/
__global__ void executeTwentyEightLayer_AvgPooling(double *Layer28_Neurons_GPU,
    double *Layer29_Neurons_GPU
)
{
    double sum = 0.0;
    int filter_number = threadIdx.x * 32 + threadIdx.y;

    // Output position
    int output_Position = filter_number;

    int input_Position_start = filter_number * 49;
    for(int row = 0 ; row < 7 ; row++)
        for(int col = 0 ; col < 7 ; col++)
            sum += Layer28_Neurons_GPU[input_Position_start + row * 7 + col];

    sum = sum / 49;
    Layer29_Neurons_GPU[output_Position] = sum;
}
/*  *************************************************** TWENTYEIGHT LAYER END **************************************************** */

/*  *************************************************** TWENTYNINE LAYER START ************************************************** */
/*
    Layer 29: Fully Connected Layer
    Input: 1 * 1 * 1024
    Weight: 1000 * 1024
    Bias: 1000
    Output: 1000
*/
__global__ void executeTwentyNineLayer_FullyConnected(double *Layer29_Neurons_GPU,
    double *Layer30_Neurons_GPU,
    double *Layer29_Weights_GPU,
    double *Layer29_Bias_GPU
)
{
    double product = 0.0;
    int filter_number = threadIdx.x;

    // Output position
    int output_Position = filter_number;

    int weight_Position = filter_number * 1024;

    for(int channel = 0; channel < 1024 ; channel++)
    {
        product += (Layer29_Neurons_GPU[channel] * Layer29_Weights_GPU[weight_Position + channel]);
    }

    //Adding Bias to the output
    product += Layer29_Bias_GPU[filter_number];

    Layer30_Neurons_GPU[output_Position] = product;
}
/*  *************************************************** TWENTYNINE LAYER END **************************************************** */

	.file	"tmpxft_002fbe80_00000000-6_MobileNets_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2029:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0, @function
_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0:
.LFB2262:
	.cfi_startproc
	jmp	cudaLaunchKernel@PLT
	.cfi_endproc
.LFE2262:
	.size	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0, .-_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	.globl	_Z62__device_stub__Z30executeFirstLayer_CONV3D_partAPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.type	_Z62__device_stub__Z30executeFirstLayer_CONV3D_partAPdS_S_S_S_S_S_PdS_S_S_S_S_S_, @function
_Z62__device_stub__Z30executeFirstLayer_CONV3D_partAPdS_S_S_S_S_S_PdS_S_S_S_S_S_:
.LFB2051:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L3
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z30executeFirstLayer_CONV3D_partAPdS_S_S_S_S_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L3:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L5
	call	__stack_chk_fail@PLT
.L5:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2051:
	.size	_Z62__device_stub__Z30executeFirstLayer_CONV3D_partAPdS_S_S_S_S_S_PdS_S_S_S_S_S_, .-_Z62__device_stub__Z30executeFirstLayer_CONV3D_partAPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.globl	_Z30executeFirstLayer_CONV3D_partAPdS_S_S_S_S_S_
	.type	_Z30executeFirstLayer_CONV3D_partAPdS_S_S_S_S_S_, @function
_Z30executeFirstLayer_CONV3D_partAPdS_S_S_S_S_S_:
.LFB2052:
	.cfi_startproc
	endbr64
	jmp	_Z62__device_stub__Z30executeFirstLayer_CONV3D_partAPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.cfi_endproc
.LFE2052:
	.size	_Z30executeFirstLayer_CONV3D_partAPdS_S_S_S_S_S_, .-_Z30executeFirstLayer_CONV3D_partAPdS_S_S_S_S_S_
	.globl	_Z62__device_stub__Z30executeFirstLayer_CONV3D_partBPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.type	_Z62__device_stub__Z30executeFirstLayer_CONV3D_partBPdS_S_S_S_S_S_PdS_S_S_S_S_S_, @function
_Z62__device_stub__Z30executeFirstLayer_CONV3D_partBPdS_S_S_S_S_S_PdS_S_S_S_S_S_:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z30executeFirstLayer_CONV3D_partBPdS_S_S_S_S_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L9:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L11
	call	__stack_chk_fail@PLT
.L11:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z62__device_stub__Z30executeFirstLayer_CONV3D_partBPdS_S_S_S_S_S_PdS_S_S_S_S_S_, .-_Z62__device_stub__Z30executeFirstLayer_CONV3D_partBPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.globl	_Z30executeFirstLayer_CONV3D_partBPdS_S_S_S_S_S_
	.type	_Z30executeFirstLayer_CONV3D_partBPdS_S_S_S_S_S_, @function
_Z30executeFirstLayer_CONV3D_partBPdS_S_S_S_S_S_:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z62__device_stub__Z30executeFirstLayer_CONV3D_partBPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.cfi_endproc
.LFE2054:
	.size	_Z30executeFirstLayer_CONV3D_partBPdS_S_S_S_S_S_, .-_Z30executeFirstLayer_CONV3D_partBPdS_S_S_S_S_S_
	.globl	_Z62__device_stub__Z30executeFirstLayer_CONV3D_partCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.type	_Z62__device_stub__Z30executeFirstLayer_CONV3D_partCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, @function
_Z62__device_stub__Z30executeFirstLayer_CONV3D_partCPdS_S_S_S_S_S_PdS_S_S_S_S_S_:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z30executeFirstLayer_CONV3D_partCPdS_S_S_S_S_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L14:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L16
	call	__stack_chk_fail@PLT
.L16:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z62__device_stub__Z30executeFirstLayer_CONV3D_partCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, .-_Z62__device_stub__Z30executeFirstLayer_CONV3D_partCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.globl	_Z30executeFirstLayer_CONV3D_partCPdS_S_S_S_S_S_
	.type	_Z30executeFirstLayer_CONV3D_partCPdS_S_S_S_S_S_, @function
_Z30executeFirstLayer_CONV3D_partCPdS_S_S_S_S_S_:
.LFB2056:
	.cfi_startproc
	endbr64
	jmp	_Z62__device_stub__Z30executeFirstLayer_CONV3D_partCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.cfi_endproc
.LFE2056:
	.size	_Z30executeFirstLayer_CONV3D_partCPdS_S_S_S_S_S_, .-_Z30executeFirstLayer_CONV3D_partCPdS_S_S_S_S_S_
	.globl	_Z60__device_stub__Z28executeSecondLayer_DSC_partAPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.type	_Z60__device_stub__Z28executeSecondLayer_DSC_partAPdS_S_S_S_S_S_PdS_S_S_S_S_S_, @function
_Z60__device_stub__Z28executeSecondLayer_DSC_partAPdS_S_S_S_S_S_PdS_S_S_S_S_S_:
.LFB2057:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z28executeSecondLayer_DSC_partAPdS_S_S_S_S_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L19:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L21
	call	__stack_chk_fail@PLT
.L21:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2057:
	.size	_Z60__device_stub__Z28executeSecondLayer_DSC_partAPdS_S_S_S_S_S_PdS_S_S_S_S_S_, .-_Z60__device_stub__Z28executeSecondLayer_DSC_partAPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.globl	_Z28executeSecondLayer_DSC_partAPdS_S_S_S_S_S_
	.type	_Z28executeSecondLayer_DSC_partAPdS_S_S_S_S_S_, @function
_Z28executeSecondLayer_DSC_partAPdS_S_S_S_S_S_:
.LFB2058:
	.cfi_startproc
	endbr64
	jmp	_Z60__device_stub__Z28executeSecondLayer_DSC_partAPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.cfi_endproc
.LFE2058:
	.size	_Z28executeSecondLayer_DSC_partAPdS_S_S_S_S_S_, .-_Z28executeSecondLayer_DSC_partAPdS_S_S_S_S_S_
	.globl	_Z60__device_stub__Z28executeSecondLayer_DSC_partBPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.type	_Z60__device_stub__Z28executeSecondLayer_DSC_partBPdS_S_S_S_S_S_PdS_S_S_S_S_S_, @function
_Z60__device_stub__Z28executeSecondLayer_DSC_partBPdS_S_S_S_S_S_PdS_S_S_S_S_S_:
.LFB2059:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z28executeSecondLayer_DSC_partBPdS_S_S_S_S_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L24:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L26
	call	__stack_chk_fail@PLT
.L26:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2059:
	.size	_Z60__device_stub__Z28executeSecondLayer_DSC_partBPdS_S_S_S_S_S_PdS_S_S_S_S_S_, .-_Z60__device_stub__Z28executeSecondLayer_DSC_partBPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.globl	_Z28executeSecondLayer_DSC_partBPdS_S_S_S_S_S_
	.type	_Z28executeSecondLayer_DSC_partBPdS_S_S_S_S_S_, @function
_Z28executeSecondLayer_DSC_partBPdS_S_S_S_S_S_:
.LFB2060:
	.cfi_startproc
	endbr64
	jmp	_Z60__device_stub__Z28executeSecondLayer_DSC_partBPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.cfi_endproc
.LFE2060:
	.size	_Z28executeSecondLayer_DSC_partBPdS_S_S_S_S_S_, .-_Z28executeSecondLayer_DSC_partBPdS_S_S_S_S_S_
	.globl	_Z60__device_stub__Z28executeSecondLayer_DSC_partCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.type	_Z60__device_stub__Z28executeSecondLayer_DSC_partCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, @function
_Z60__device_stub__Z28executeSecondLayer_DSC_partCPdS_S_S_S_S_S_PdS_S_S_S_S_S_:
.LFB2061:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L29
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z28executeSecondLayer_DSC_partCPdS_S_S_S_S_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L29:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L31
	call	__stack_chk_fail@PLT
.L31:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2061:
	.size	_Z60__device_stub__Z28executeSecondLayer_DSC_partCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, .-_Z60__device_stub__Z28executeSecondLayer_DSC_partCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.globl	_Z28executeSecondLayer_DSC_partCPdS_S_S_S_S_S_
	.type	_Z28executeSecondLayer_DSC_partCPdS_S_S_S_S_S_, @function
_Z28executeSecondLayer_DSC_partCPdS_S_S_S_S_S_:
.LFB2062:
	.cfi_startproc
	endbr64
	jmp	_Z60__device_stub__Z28executeSecondLayer_DSC_partCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.cfi_endproc
.LFE2062:
	.size	_Z28executeSecondLayer_DSC_partCPdS_S_S_S_S_S_, .-_Z28executeSecondLayer_DSC_partCPdS_S_S_S_S_S_
	.globl	_Z59__device_stub__Z27executeThirdLayer_PSC_partAPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.type	_Z59__device_stub__Z27executeThirdLayer_PSC_partAPdS_S_S_S_S_S_PdS_S_S_S_S_S_, @function
_Z59__device_stub__Z27executeThirdLayer_PSC_partAPdS_S_S_S_S_S_PdS_S_S_S_S_S_:
.LFB2063:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L34
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z27executeThirdLayer_PSC_partAPdS_S_S_S_S_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L34:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L36
	call	__stack_chk_fail@PLT
.L36:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2063:
	.size	_Z59__device_stub__Z27executeThirdLayer_PSC_partAPdS_S_S_S_S_S_PdS_S_S_S_S_S_, .-_Z59__device_stub__Z27executeThirdLayer_PSC_partAPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.globl	_Z27executeThirdLayer_PSC_partAPdS_S_S_S_S_S_
	.type	_Z27executeThirdLayer_PSC_partAPdS_S_S_S_S_S_, @function
_Z27executeThirdLayer_PSC_partAPdS_S_S_S_S_S_:
.LFB2064:
	.cfi_startproc
	endbr64
	jmp	_Z59__device_stub__Z27executeThirdLayer_PSC_partAPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.cfi_endproc
.LFE2064:
	.size	_Z27executeThirdLayer_PSC_partAPdS_S_S_S_S_S_, .-_Z27executeThirdLayer_PSC_partAPdS_S_S_S_S_S_
	.globl	_Z59__device_stub__Z27executeThirdLayer_PSC_partBPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.type	_Z59__device_stub__Z27executeThirdLayer_PSC_partBPdS_S_S_S_S_S_PdS_S_S_S_S_S_, @function
_Z59__device_stub__Z27executeThirdLayer_PSC_partBPdS_S_S_S_S_S_PdS_S_S_S_S_S_:
.LFB2065:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L39
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z27executeThirdLayer_PSC_partBPdS_S_S_S_S_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L39:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L41
	call	__stack_chk_fail@PLT
.L41:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2065:
	.size	_Z59__device_stub__Z27executeThirdLayer_PSC_partBPdS_S_S_S_S_S_PdS_S_S_S_S_S_, .-_Z59__device_stub__Z27executeThirdLayer_PSC_partBPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.globl	_Z27executeThirdLayer_PSC_partBPdS_S_S_S_S_S_
	.type	_Z27executeThirdLayer_PSC_partBPdS_S_S_S_S_S_, @function
_Z27executeThirdLayer_PSC_partBPdS_S_S_S_S_S_:
.LFB2066:
	.cfi_startproc
	endbr64
	jmp	_Z59__device_stub__Z27executeThirdLayer_PSC_partBPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.cfi_endproc
.LFE2066:
	.size	_Z27executeThirdLayer_PSC_partBPdS_S_S_S_S_S_, .-_Z27executeThirdLayer_PSC_partBPdS_S_S_S_S_S_
	.globl	_Z59__device_stub__Z27executeThirdLayer_PSC_partCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.type	_Z59__device_stub__Z27executeThirdLayer_PSC_partCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, @function
_Z59__device_stub__Z27executeThirdLayer_PSC_partCPdS_S_S_S_S_S_PdS_S_S_S_S_S_:
.LFB2067:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L44
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z27executeThirdLayer_PSC_partCPdS_S_S_S_S_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L44:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L46
	call	__stack_chk_fail@PLT
.L46:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2067:
	.size	_Z59__device_stub__Z27executeThirdLayer_PSC_partCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, .-_Z59__device_stub__Z27executeThirdLayer_PSC_partCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.globl	_Z27executeThirdLayer_PSC_partCPdS_S_S_S_S_S_
	.type	_Z27executeThirdLayer_PSC_partCPdS_S_S_S_S_S_, @function
_Z27executeThirdLayer_PSC_partCPdS_S_S_S_S_S_:
.LFB2068:
	.cfi_startproc
	endbr64
	jmp	_Z59__device_stub__Z27executeThirdLayer_PSC_partCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.cfi_endproc
.LFE2068:
	.size	_Z27executeThirdLayer_PSC_partCPdS_S_S_S_S_S_, .-_Z27executeThirdLayer_PSC_partCPdS_S_S_S_S_S_
	.globl	_Z60__device_stub__Z28executeFourthLayer_DSC_partAPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.type	_Z60__device_stub__Z28executeFourthLayer_DSC_partAPdS_S_S_S_S_S_PdS_S_S_S_S_S_, @function
_Z60__device_stub__Z28executeFourthLayer_DSC_partAPdS_S_S_S_S_S_PdS_S_S_S_S_S_:
.LFB2069:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L49
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z28executeFourthLayer_DSC_partAPdS_S_S_S_S_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L49:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L51
	call	__stack_chk_fail@PLT
.L51:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2069:
	.size	_Z60__device_stub__Z28executeFourthLayer_DSC_partAPdS_S_S_S_S_S_PdS_S_S_S_S_S_, .-_Z60__device_stub__Z28executeFourthLayer_DSC_partAPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.globl	_Z28executeFourthLayer_DSC_partAPdS_S_S_S_S_S_
	.type	_Z28executeFourthLayer_DSC_partAPdS_S_S_S_S_S_, @function
_Z28executeFourthLayer_DSC_partAPdS_S_S_S_S_S_:
.LFB2070:
	.cfi_startproc
	endbr64
	jmp	_Z60__device_stub__Z28executeFourthLayer_DSC_partAPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.cfi_endproc
.LFE2070:
	.size	_Z28executeFourthLayer_DSC_partAPdS_S_S_S_S_S_, .-_Z28executeFourthLayer_DSC_partAPdS_S_S_S_S_S_
	.globl	_Z60__device_stub__Z28executeFourthLayer_DSC_partBPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.type	_Z60__device_stub__Z28executeFourthLayer_DSC_partBPdS_S_S_S_S_S_PdS_S_S_S_S_S_, @function
_Z60__device_stub__Z28executeFourthLayer_DSC_partBPdS_S_S_S_S_S_PdS_S_S_S_S_S_:
.LFB2071:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L54
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z28executeFourthLayer_DSC_partBPdS_S_S_S_S_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L54:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L56
	call	__stack_chk_fail@PLT
.L56:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2071:
	.size	_Z60__device_stub__Z28executeFourthLayer_DSC_partBPdS_S_S_S_S_S_PdS_S_S_S_S_S_, .-_Z60__device_stub__Z28executeFourthLayer_DSC_partBPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.globl	_Z28executeFourthLayer_DSC_partBPdS_S_S_S_S_S_
	.type	_Z28executeFourthLayer_DSC_partBPdS_S_S_S_S_S_, @function
_Z28executeFourthLayer_DSC_partBPdS_S_S_S_S_S_:
.LFB2072:
	.cfi_startproc
	endbr64
	jmp	_Z60__device_stub__Z28executeFourthLayer_DSC_partBPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.cfi_endproc
.LFE2072:
	.size	_Z28executeFourthLayer_DSC_partBPdS_S_S_S_S_S_, .-_Z28executeFourthLayer_DSC_partBPdS_S_S_S_S_S_
	.globl	_Z60__device_stub__Z28executeFourthLayer_DSC_partCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.type	_Z60__device_stub__Z28executeFourthLayer_DSC_partCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, @function
_Z60__device_stub__Z28executeFourthLayer_DSC_partCPdS_S_S_S_S_S_PdS_S_S_S_S_S_:
.LFB2073:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L59
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z28executeFourthLayer_DSC_partCPdS_S_S_S_S_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L59:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L61
	call	__stack_chk_fail@PLT
.L61:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2073:
	.size	_Z60__device_stub__Z28executeFourthLayer_DSC_partCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, .-_Z60__device_stub__Z28executeFourthLayer_DSC_partCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.globl	_Z28executeFourthLayer_DSC_partCPdS_S_S_S_S_S_
	.type	_Z28executeFourthLayer_DSC_partCPdS_S_S_S_S_S_, @function
_Z28executeFourthLayer_DSC_partCPdS_S_S_S_S_S_:
.LFB2074:
	.cfi_startproc
	endbr64
	jmp	_Z60__device_stub__Z28executeFourthLayer_DSC_partCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.cfi_endproc
.LFE2074:
	.size	_Z28executeFourthLayer_DSC_partCPdS_S_S_S_S_S_, .-_Z28executeFourthLayer_DSC_partCPdS_S_S_S_S_S_
	.globl	_Z60__device_stub__Z28executeFourthLayer_DSC_partDPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.type	_Z60__device_stub__Z28executeFourthLayer_DSC_partDPdS_S_S_S_S_S_PdS_S_S_S_S_S_, @function
_Z60__device_stub__Z28executeFourthLayer_DSC_partDPdS_S_S_S_S_S_PdS_S_S_S_S_S_:
.LFB2075:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L64
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z28executeFourthLayer_DSC_partDPdS_S_S_S_S_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L64:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L66
	call	__stack_chk_fail@PLT
.L66:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2075:
	.size	_Z60__device_stub__Z28executeFourthLayer_DSC_partDPdS_S_S_S_S_S_PdS_S_S_S_S_S_, .-_Z60__device_stub__Z28executeFourthLayer_DSC_partDPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.globl	_Z28executeFourthLayer_DSC_partDPdS_S_S_S_S_S_
	.type	_Z28executeFourthLayer_DSC_partDPdS_S_S_S_S_S_, @function
_Z28executeFourthLayer_DSC_partDPdS_S_S_S_S_S_:
.LFB2076:
	.cfi_startproc
	endbr64
	jmp	_Z60__device_stub__Z28executeFourthLayer_DSC_partDPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.cfi_endproc
.LFE2076:
	.size	_Z28executeFourthLayer_DSC_partDPdS_S_S_S_S_S_, .-_Z28executeFourthLayer_DSC_partDPdS_S_S_S_S_S_
	.globl	_Z59__device_stub__Z27executeFifthLayer_PSC_partAPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.type	_Z59__device_stub__Z27executeFifthLayer_PSC_partAPdS_S_S_S_S_S_PdS_S_S_S_S_S_, @function
_Z59__device_stub__Z27executeFifthLayer_PSC_partAPdS_S_S_S_S_S_PdS_S_S_S_S_S_:
.LFB2077:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L69
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z27executeFifthLayer_PSC_partAPdS_S_S_S_S_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L69:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L71
	call	__stack_chk_fail@PLT
.L71:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2077:
	.size	_Z59__device_stub__Z27executeFifthLayer_PSC_partAPdS_S_S_S_S_S_PdS_S_S_S_S_S_, .-_Z59__device_stub__Z27executeFifthLayer_PSC_partAPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.globl	_Z27executeFifthLayer_PSC_partAPdS_S_S_S_S_S_
	.type	_Z27executeFifthLayer_PSC_partAPdS_S_S_S_S_S_, @function
_Z27executeFifthLayer_PSC_partAPdS_S_S_S_S_S_:
.LFB2078:
	.cfi_startproc
	endbr64
	jmp	_Z59__device_stub__Z27executeFifthLayer_PSC_partAPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.cfi_endproc
.LFE2078:
	.size	_Z27executeFifthLayer_PSC_partAPdS_S_S_S_S_S_, .-_Z27executeFifthLayer_PSC_partAPdS_S_S_S_S_S_
	.globl	_Z59__device_stub__Z27executeFifthLayer_PSC_partBPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.type	_Z59__device_stub__Z27executeFifthLayer_PSC_partBPdS_S_S_S_S_S_PdS_S_S_S_S_S_, @function
_Z59__device_stub__Z27executeFifthLayer_PSC_partBPdS_S_S_S_S_S_PdS_S_S_S_S_S_:
.LFB2079:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L74
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z27executeFifthLayer_PSC_partBPdS_S_S_S_S_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L74:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L76
	call	__stack_chk_fail@PLT
.L76:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2079:
	.size	_Z59__device_stub__Z27executeFifthLayer_PSC_partBPdS_S_S_S_S_S_PdS_S_S_S_S_S_, .-_Z59__device_stub__Z27executeFifthLayer_PSC_partBPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.globl	_Z27executeFifthLayer_PSC_partBPdS_S_S_S_S_S_
	.type	_Z27executeFifthLayer_PSC_partBPdS_S_S_S_S_S_, @function
_Z27executeFifthLayer_PSC_partBPdS_S_S_S_S_S_:
.LFB2080:
	.cfi_startproc
	endbr64
	jmp	_Z59__device_stub__Z27executeFifthLayer_PSC_partBPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.cfi_endproc
.LFE2080:
	.size	_Z27executeFifthLayer_PSC_partBPdS_S_S_S_S_S_, .-_Z27executeFifthLayer_PSC_partBPdS_S_S_S_S_S_
	.globl	_Z59__device_stub__Z27executeFifthLayer_PSC_partCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.type	_Z59__device_stub__Z27executeFifthLayer_PSC_partCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, @function
_Z59__device_stub__Z27executeFifthLayer_PSC_partCPdS_S_S_S_S_S_PdS_S_S_S_S_S_:
.LFB2081:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L79
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z27executeFifthLayer_PSC_partCPdS_S_S_S_S_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L79:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L81
	call	__stack_chk_fail@PLT
.L81:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2081:
	.size	_Z59__device_stub__Z27executeFifthLayer_PSC_partCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, .-_Z59__device_stub__Z27executeFifthLayer_PSC_partCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.globl	_Z27executeFifthLayer_PSC_partCPdS_S_S_S_S_S_
	.type	_Z27executeFifthLayer_PSC_partCPdS_S_S_S_S_S_, @function
_Z27executeFifthLayer_PSC_partCPdS_S_S_S_S_S_:
.LFB2082:
	.cfi_startproc
	endbr64
	jmp	_Z59__device_stub__Z27executeFifthLayer_PSC_partCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.cfi_endproc
.LFE2082:
	.size	_Z27executeFifthLayer_PSC_partCPdS_S_S_S_S_S_, .-_Z27executeFifthLayer_PSC_partCPdS_S_S_S_S_S_
	.globl	_Z59__device_stub__Z27executeFifthLayer_PSC_partDPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.type	_Z59__device_stub__Z27executeFifthLayer_PSC_partDPdS_S_S_S_S_S_PdS_S_S_S_S_S_, @function
_Z59__device_stub__Z27executeFifthLayer_PSC_partDPdS_S_S_S_S_S_PdS_S_S_S_S_S_:
.LFB2083:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L84
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z27executeFifthLayer_PSC_partDPdS_S_S_S_S_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L84:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L86
	call	__stack_chk_fail@PLT
.L86:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2083:
	.size	_Z59__device_stub__Z27executeFifthLayer_PSC_partDPdS_S_S_S_S_S_PdS_S_S_S_S_S_, .-_Z59__device_stub__Z27executeFifthLayer_PSC_partDPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.globl	_Z27executeFifthLayer_PSC_partDPdS_S_S_S_S_S_
	.type	_Z27executeFifthLayer_PSC_partDPdS_S_S_S_S_S_, @function
_Z27executeFifthLayer_PSC_partDPdS_S_S_S_S_S_:
.LFB2084:
	.cfi_startproc
	endbr64
	jmp	_Z59__device_stub__Z27executeFifthLayer_PSC_partDPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.cfi_endproc
.LFE2084:
	.size	_Z27executeFifthLayer_PSC_partDPdS_S_S_S_S_S_, .-_Z27executeFifthLayer_PSC_partDPdS_S_S_S_S_S_
	.globl	_Z59__device_stub__Z27executeSixthLayer_DSC_partAPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.type	_Z59__device_stub__Z27executeSixthLayer_DSC_partAPdS_S_S_S_S_S_PdS_S_S_S_S_S_, @function
_Z59__device_stub__Z27executeSixthLayer_DSC_partAPdS_S_S_S_S_S_PdS_S_S_S_S_S_:
.LFB2085:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L89
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z27executeSixthLayer_DSC_partAPdS_S_S_S_S_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L89:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L91
	call	__stack_chk_fail@PLT
.L91:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2085:
	.size	_Z59__device_stub__Z27executeSixthLayer_DSC_partAPdS_S_S_S_S_S_PdS_S_S_S_S_S_, .-_Z59__device_stub__Z27executeSixthLayer_DSC_partAPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.globl	_Z27executeSixthLayer_DSC_partAPdS_S_S_S_S_S_
	.type	_Z27executeSixthLayer_DSC_partAPdS_S_S_S_S_S_, @function
_Z27executeSixthLayer_DSC_partAPdS_S_S_S_S_S_:
.LFB2086:
	.cfi_startproc
	endbr64
	jmp	_Z59__device_stub__Z27executeSixthLayer_DSC_partAPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.cfi_endproc
.LFE2086:
	.size	_Z27executeSixthLayer_DSC_partAPdS_S_S_S_S_S_, .-_Z27executeSixthLayer_DSC_partAPdS_S_S_S_S_S_
	.globl	_Z59__device_stub__Z27executeSixthLayer_DSC_partBPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.type	_Z59__device_stub__Z27executeSixthLayer_DSC_partBPdS_S_S_S_S_S_PdS_S_S_S_S_S_, @function
_Z59__device_stub__Z27executeSixthLayer_DSC_partBPdS_S_S_S_S_S_PdS_S_S_S_S_S_:
.LFB2087:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L94
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z27executeSixthLayer_DSC_partBPdS_S_S_S_S_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L94:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L96
	call	__stack_chk_fail@PLT
.L96:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2087:
	.size	_Z59__device_stub__Z27executeSixthLayer_DSC_partBPdS_S_S_S_S_S_PdS_S_S_S_S_S_, .-_Z59__device_stub__Z27executeSixthLayer_DSC_partBPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.globl	_Z27executeSixthLayer_DSC_partBPdS_S_S_S_S_S_
	.type	_Z27executeSixthLayer_DSC_partBPdS_S_S_S_S_S_, @function
_Z27executeSixthLayer_DSC_partBPdS_S_S_S_S_S_:
.LFB2088:
	.cfi_startproc
	endbr64
	jmp	_Z59__device_stub__Z27executeSixthLayer_DSC_partBPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.cfi_endproc
.LFE2088:
	.size	_Z27executeSixthLayer_DSC_partBPdS_S_S_S_S_S_, .-_Z27executeSixthLayer_DSC_partBPdS_S_S_S_S_S_
	.globl	_Z59__device_stub__Z27executeSixthLayer_DSC_partCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.type	_Z59__device_stub__Z27executeSixthLayer_DSC_partCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, @function
_Z59__device_stub__Z27executeSixthLayer_DSC_partCPdS_S_S_S_S_S_PdS_S_S_S_S_S_:
.LFB2089:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L99
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z27executeSixthLayer_DSC_partCPdS_S_S_S_S_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L99:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L101
	call	__stack_chk_fail@PLT
.L101:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2089:
	.size	_Z59__device_stub__Z27executeSixthLayer_DSC_partCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, .-_Z59__device_stub__Z27executeSixthLayer_DSC_partCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.globl	_Z27executeSixthLayer_DSC_partCPdS_S_S_S_S_S_
	.type	_Z27executeSixthLayer_DSC_partCPdS_S_S_S_S_S_, @function
_Z27executeSixthLayer_DSC_partCPdS_S_S_S_S_S_:
.LFB2090:
	.cfi_startproc
	endbr64
	jmp	_Z59__device_stub__Z27executeSixthLayer_DSC_partCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.cfi_endproc
.LFE2090:
	.size	_Z27executeSixthLayer_DSC_partCPdS_S_S_S_S_S_, .-_Z27executeSixthLayer_DSC_partCPdS_S_S_S_S_S_
	.globl	_Z59__device_stub__Z27executeSixthLayer_DSC_partDPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.type	_Z59__device_stub__Z27executeSixthLayer_DSC_partDPdS_S_S_S_S_S_PdS_S_S_S_S_S_, @function
_Z59__device_stub__Z27executeSixthLayer_DSC_partDPdS_S_S_S_S_S_PdS_S_S_S_S_S_:
.LFB2091:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L104
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z27executeSixthLayer_DSC_partDPdS_S_S_S_S_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L104:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L106
	call	__stack_chk_fail@PLT
.L106:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2091:
	.size	_Z59__device_stub__Z27executeSixthLayer_DSC_partDPdS_S_S_S_S_S_PdS_S_S_S_S_S_, .-_Z59__device_stub__Z27executeSixthLayer_DSC_partDPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.globl	_Z27executeSixthLayer_DSC_partDPdS_S_S_S_S_S_
	.type	_Z27executeSixthLayer_DSC_partDPdS_S_S_S_S_S_, @function
_Z27executeSixthLayer_DSC_partDPdS_S_S_S_S_S_:
.LFB2092:
	.cfi_startproc
	endbr64
	jmp	_Z59__device_stub__Z27executeSixthLayer_DSC_partDPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.cfi_endproc
.LFE2092:
	.size	_Z27executeSixthLayer_DSC_partDPdS_S_S_S_S_S_, .-_Z27executeSixthLayer_DSC_partDPdS_S_S_S_S_S_
	.globl	_Z61__device_stub__Z29executeSeventhLayer_PSC_partAPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.type	_Z61__device_stub__Z29executeSeventhLayer_PSC_partAPdS_S_S_S_S_S_PdS_S_S_S_S_S_, @function
_Z61__device_stub__Z29executeSeventhLayer_PSC_partAPdS_S_S_S_S_S_PdS_S_S_S_S_S_:
.LFB2093:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L109
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z29executeSeventhLayer_PSC_partAPdS_S_S_S_S_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L109:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L111
	call	__stack_chk_fail@PLT
.L111:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2093:
	.size	_Z61__device_stub__Z29executeSeventhLayer_PSC_partAPdS_S_S_S_S_S_PdS_S_S_S_S_S_, .-_Z61__device_stub__Z29executeSeventhLayer_PSC_partAPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.globl	_Z29executeSeventhLayer_PSC_partAPdS_S_S_S_S_S_
	.type	_Z29executeSeventhLayer_PSC_partAPdS_S_S_S_S_S_, @function
_Z29executeSeventhLayer_PSC_partAPdS_S_S_S_S_S_:
.LFB2094:
	.cfi_startproc
	endbr64
	jmp	_Z61__device_stub__Z29executeSeventhLayer_PSC_partAPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.cfi_endproc
.LFE2094:
	.size	_Z29executeSeventhLayer_PSC_partAPdS_S_S_S_S_S_, .-_Z29executeSeventhLayer_PSC_partAPdS_S_S_S_S_S_
	.globl	_Z61__device_stub__Z29executeSeventhLayer_PSC_partBPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.type	_Z61__device_stub__Z29executeSeventhLayer_PSC_partBPdS_S_S_S_S_S_PdS_S_S_S_S_S_, @function
_Z61__device_stub__Z29executeSeventhLayer_PSC_partBPdS_S_S_S_S_S_PdS_S_S_S_S_S_:
.LFB2095:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L114
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z29executeSeventhLayer_PSC_partBPdS_S_S_S_S_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L114:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L116
	call	__stack_chk_fail@PLT
.L116:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2095:
	.size	_Z61__device_stub__Z29executeSeventhLayer_PSC_partBPdS_S_S_S_S_S_PdS_S_S_S_S_S_, .-_Z61__device_stub__Z29executeSeventhLayer_PSC_partBPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.globl	_Z29executeSeventhLayer_PSC_partBPdS_S_S_S_S_S_
	.type	_Z29executeSeventhLayer_PSC_partBPdS_S_S_S_S_S_, @function
_Z29executeSeventhLayer_PSC_partBPdS_S_S_S_S_S_:
.LFB2096:
	.cfi_startproc
	endbr64
	jmp	_Z61__device_stub__Z29executeSeventhLayer_PSC_partBPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.cfi_endproc
.LFE2096:
	.size	_Z29executeSeventhLayer_PSC_partBPdS_S_S_S_S_S_, .-_Z29executeSeventhLayer_PSC_partBPdS_S_S_S_S_S_
	.globl	_Z61__device_stub__Z29executeSeventhLayer_PSC_partCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.type	_Z61__device_stub__Z29executeSeventhLayer_PSC_partCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, @function
_Z61__device_stub__Z29executeSeventhLayer_PSC_partCPdS_S_S_S_S_S_PdS_S_S_S_S_S_:
.LFB2097:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L119
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z29executeSeventhLayer_PSC_partCPdS_S_S_S_S_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L119:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L121
	call	__stack_chk_fail@PLT
.L121:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2097:
	.size	_Z61__device_stub__Z29executeSeventhLayer_PSC_partCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, .-_Z61__device_stub__Z29executeSeventhLayer_PSC_partCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.globl	_Z29executeSeventhLayer_PSC_partCPdS_S_S_S_S_S_
	.type	_Z29executeSeventhLayer_PSC_partCPdS_S_S_S_S_S_, @function
_Z29executeSeventhLayer_PSC_partCPdS_S_S_S_S_S_:
.LFB2098:
	.cfi_startproc
	endbr64
	jmp	_Z61__device_stub__Z29executeSeventhLayer_PSC_partCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.cfi_endproc
.LFE2098:
	.size	_Z29executeSeventhLayer_PSC_partCPdS_S_S_S_S_S_, .-_Z29executeSeventhLayer_PSC_partCPdS_S_S_S_S_S_
	.globl	_Z61__device_stub__Z29executeSeventhLayer_PSC_partDPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.type	_Z61__device_stub__Z29executeSeventhLayer_PSC_partDPdS_S_S_S_S_S_PdS_S_S_S_S_S_, @function
_Z61__device_stub__Z29executeSeventhLayer_PSC_partDPdS_S_S_S_S_S_PdS_S_S_S_S_S_:
.LFB2099:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L124
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z29executeSeventhLayer_PSC_partDPdS_S_S_S_S_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L124:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L126
	call	__stack_chk_fail@PLT
.L126:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2099:
	.size	_Z61__device_stub__Z29executeSeventhLayer_PSC_partDPdS_S_S_S_S_S_PdS_S_S_S_S_S_, .-_Z61__device_stub__Z29executeSeventhLayer_PSC_partDPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.globl	_Z29executeSeventhLayer_PSC_partDPdS_S_S_S_S_S_
	.type	_Z29executeSeventhLayer_PSC_partDPdS_S_S_S_S_S_, @function
_Z29executeSeventhLayer_PSC_partDPdS_S_S_S_S_S_:
.LFB2100:
	.cfi_startproc
	endbr64
	jmp	_Z61__device_stub__Z29executeSeventhLayer_PSC_partDPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.cfi_endproc
.LFE2100:
	.size	_Z29executeSeventhLayer_PSC_partDPdS_S_S_S_S_S_, .-_Z29executeSeventhLayer_PSC_partDPdS_S_S_S_S_S_
	.globl	_Z54__device_stub__Z22executeEighthLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.type	_Z54__device_stub__Z22executeEighthLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, @function
_Z54__device_stub__Z22executeEighthLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_:
.LFB2101:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L129
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z22executeEighthLayer_DSCPdS_S_S_S_S_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L129:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L131
	call	__stack_chk_fail@PLT
.L131:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2101:
	.size	_Z54__device_stub__Z22executeEighthLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, .-_Z54__device_stub__Z22executeEighthLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.globl	_Z22executeEighthLayer_DSCPdS_S_S_S_S_S_
	.type	_Z22executeEighthLayer_DSCPdS_S_S_S_S_S_, @function
_Z22executeEighthLayer_DSCPdS_S_S_S_S_S_:
.LFB2102:
	.cfi_startproc
	endbr64
	jmp	_Z54__device_stub__Z22executeEighthLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.cfi_endproc
.LFE2102:
	.size	_Z22executeEighthLayer_DSCPdS_S_S_S_S_S_, .-_Z22executeEighthLayer_DSCPdS_S_S_S_S_S_
	.globl	_Z53__device_stub__Z21executeNinthLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.type	_Z53__device_stub__Z21executeNinthLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, @function
_Z53__device_stub__Z21executeNinthLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_:
.LFB2103:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L134
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z21executeNinthLayer_PSCPdS_S_S_S_S_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L134:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L136
	call	__stack_chk_fail@PLT
.L136:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2103:
	.size	_Z53__device_stub__Z21executeNinthLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, .-_Z53__device_stub__Z21executeNinthLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.globl	_Z21executeNinthLayer_PSCPdS_S_S_S_S_S_
	.type	_Z21executeNinthLayer_PSCPdS_S_S_S_S_S_, @function
_Z21executeNinthLayer_PSCPdS_S_S_S_S_S_:
.LFB2104:
	.cfi_startproc
	endbr64
	jmp	_Z53__device_stub__Z21executeNinthLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.cfi_endproc
.LFE2104:
	.size	_Z21executeNinthLayer_PSCPdS_S_S_S_S_S_, .-_Z21executeNinthLayer_PSCPdS_S_S_S_S_S_
	.globl	_Z53__device_stub__Z21executeTenthLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.type	_Z53__device_stub__Z21executeTenthLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, @function
_Z53__device_stub__Z21executeTenthLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_:
.LFB2105:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L139
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z21executeTenthLayer_DSCPdS_S_S_S_S_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L139:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L141
	call	__stack_chk_fail@PLT
.L141:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2105:
	.size	_Z53__device_stub__Z21executeTenthLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, .-_Z53__device_stub__Z21executeTenthLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.globl	_Z21executeTenthLayer_DSCPdS_S_S_S_S_S_
	.type	_Z21executeTenthLayer_DSCPdS_S_S_S_S_S_, @function
_Z21executeTenthLayer_DSCPdS_S_S_S_S_S_:
.LFB2106:
	.cfi_startproc
	endbr64
	jmp	_Z53__device_stub__Z21executeTenthLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.cfi_endproc
.LFE2106:
	.size	_Z21executeTenthLayer_DSCPdS_S_S_S_S_S_, .-_Z21executeTenthLayer_DSCPdS_S_S_S_S_S_
	.globl	_Z56__device_stub__Z24executeEleventhLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.type	_Z56__device_stub__Z24executeEleventhLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, @function
_Z56__device_stub__Z24executeEleventhLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_:
.LFB2107:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L144
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z24executeEleventhLayer_PSCPdS_S_S_S_S_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L144:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L146
	call	__stack_chk_fail@PLT
.L146:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2107:
	.size	_Z56__device_stub__Z24executeEleventhLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, .-_Z56__device_stub__Z24executeEleventhLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.globl	_Z24executeEleventhLayer_PSCPdS_S_S_S_S_S_
	.type	_Z24executeEleventhLayer_PSCPdS_S_S_S_S_S_, @function
_Z24executeEleventhLayer_PSCPdS_S_S_S_S_S_:
.LFB2108:
	.cfi_startproc
	endbr64
	jmp	_Z56__device_stub__Z24executeEleventhLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.cfi_endproc
.LFE2108:
	.size	_Z24executeEleventhLayer_PSCPdS_S_S_S_S_S_, .-_Z24executeEleventhLayer_PSCPdS_S_S_S_S_S_
	.globl	_Z55__device_stub__Z23executeTwelfthLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.type	_Z55__device_stub__Z23executeTwelfthLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, @function
_Z55__device_stub__Z23executeTwelfthLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_:
.LFB2109:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L149
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z23executeTwelfthLayer_DSCPdS_S_S_S_S_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L149:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L151
	call	__stack_chk_fail@PLT
.L151:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2109:
	.size	_Z55__device_stub__Z23executeTwelfthLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, .-_Z55__device_stub__Z23executeTwelfthLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.globl	_Z23executeTwelfthLayer_DSCPdS_S_S_S_S_S_
	.type	_Z23executeTwelfthLayer_DSCPdS_S_S_S_S_S_, @function
_Z23executeTwelfthLayer_DSCPdS_S_S_S_S_S_:
.LFB2110:
	.cfi_startproc
	endbr64
	jmp	_Z55__device_stub__Z23executeTwelfthLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.cfi_endproc
.LFE2110:
	.size	_Z23executeTwelfthLayer_DSCPdS_S_S_S_S_S_, .-_Z23executeTwelfthLayer_DSCPdS_S_S_S_S_S_
	.globl	_Z58__device_stub__Z26executeThirteenthLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.type	_Z58__device_stub__Z26executeThirteenthLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, @function
_Z58__device_stub__Z26executeThirteenthLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_:
.LFB2111:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L154
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z26executeThirteenthLayer_PSCPdS_S_S_S_S_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L154:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L156
	call	__stack_chk_fail@PLT
.L156:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2111:
	.size	_Z58__device_stub__Z26executeThirteenthLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, .-_Z58__device_stub__Z26executeThirteenthLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.globl	_Z26executeThirteenthLayer_PSCPdS_S_S_S_S_S_
	.type	_Z26executeThirteenthLayer_PSCPdS_S_S_S_S_S_, @function
_Z26executeThirteenthLayer_PSCPdS_S_S_S_S_S_:
.LFB2112:
	.cfi_startproc
	endbr64
	jmp	_Z58__device_stub__Z26executeThirteenthLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.cfi_endproc
.LFE2112:
	.size	_Z26executeThirteenthLayer_PSCPdS_S_S_S_S_S_, .-_Z26executeThirteenthLayer_PSCPdS_S_S_S_S_S_
	.globl	_Z58__device_stub__Z26executeFourteenthLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.type	_Z58__device_stub__Z26executeFourteenthLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, @function
_Z58__device_stub__Z26executeFourteenthLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_:
.LFB2113:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L159
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z26executeFourteenthLayer_DSCPdS_S_S_S_S_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L159:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L161
	call	__stack_chk_fail@PLT
.L161:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2113:
	.size	_Z58__device_stub__Z26executeFourteenthLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, .-_Z58__device_stub__Z26executeFourteenthLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.globl	_Z26executeFourteenthLayer_DSCPdS_S_S_S_S_S_
	.type	_Z26executeFourteenthLayer_DSCPdS_S_S_S_S_S_, @function
_Z26executeFourteenthLayer_DSCPdS_S_S_S_S_S_:
.LFB2114:
	.cfi_startproc
	endbr64
	jmp	_Z58__device_stub__Z26executeFourteenthLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.cfi_endproc
.LFE2114:
	.size	_Z26executeFourteenthLayer_DSCPdS_S_S_S_S_S_, .-_Z26executeFourteenthLayer_DSCPdS_S_S_S_S_S_
	.globl	_Z57__device_stub__Z25executeFifteenthLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.type	_Z57__device_stub__Z25executeFifteenthLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, @function
_Z57__device_stub__Z25executeFifteenthLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_:
.LFB2115:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L164
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z25executeFifteenthLayer_PSCPdS_S_S_S_S_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L164:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L166
	call	__stack_chk_fail@PLT
.L166:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2115:
	.size	_Z57__device_stub__Z25executeFifteenthLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, .-_Z57__device_stub__Z25executeFifteenthLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.globl	_Z25executeFifteenthLayer_PSCPdS_S_S_S_S_S_
	.type	_Z25executeFifteenthLayer_PSCPdS_S_S_S_S_S_, @function
_Z25executeFifteenthLayer_PSCPdS_S_S_S_S_S_:
.LFB2116:
	.cfi_startproc
	endbr64
	jmp	_Z57__device_stub__Z25executeFifteenthLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.cfi_endproc
.LFE2116:
	.size	_Z25executeFifteenthLayer_PSCPdS_S_S_S_S_S_, .-_Z25executeFifteenthLayer_PSCPdS_S_S_S_S_S_
	.globl	_Z57__device_stub__Z25executeSixteenthLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.type	_Z57__device_stub__Z25executeSixteenthLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, @function
_Z57__device_stub__Z25executeSixteenthLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_:
.LFB2117:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L169
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z25executeSixteenthLayer_DSCPdS_S_S_S_S_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L169:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L171
	call	__stack_chk_fail@PLT
.L171:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2117:
	.size	_Z57__device_stub__Z25executeSixteenthLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, .-_Z57__device_stub__Z25executeSixteenthLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.globl	_Z25executeSixteenthLayer_DSCPdS_S_S_S_S_S_
	.type	_Z25executeSixteenthLayer_DSCPdS_S_S_S_S_S_, @function
_Z25executeSixteenthLayer_DSCPdS_S_S_S_S_S_:
.LFB2118:
	.cfi_startproc
	endbr64
	jmp	_Z57__device_stub__Z25executeSixteenthLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.cfi_endproc
.LFE2118:
	.size	_Z25executeSixteenthLayer_DSCPdS_S_S_S_S_S_, .-_Z25executeSixteenthLayer_DSCPdS_S_S_S_S_S_
	.globl	_Z59__device_stub__Z27executeSeventeenthLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.type	_Z59__device_stub__Z27executeSeventeenthLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, @function
_Z59__device_stub__Z27executeSeventeenthLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_:
.LFB2119:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L174
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z27executeSeventeenthLayer_PSCPdS_S_S_S_S_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L174:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L176
	call	__stack_chk_fail@PLT
.L176:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2119:
	.size	_Z59__device_stub__Z27executeSeventeenthLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, .-_Z59__device_stub__Z27executeSeventeenthLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.globl	_Z27executeSeventeenthLayer_PSCPdS_S_S_S_S_S_
	.type	_Z27executeSeventeenthLayer_PSCPdS_S_S_S_S_S_, @function
_Z27executeSeventeenthLayer_PSCPdS_S_S_S_S_S_:
.LFB2120:
	.cfi_startproc
	endbr64
	jmp	_Z59__device_stub__Z27executeSeventeenthLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.cfi_endproc
.LFE2120:
	.size	_Z27executeSeventeenthLayer_PSCPdS_S_S_S_S_S_, .-_Z27executeSeventeenthLayer_PSCPdS_S_S_S_S_S_
	.globl	_Z58__device_stub__Z26executeEighteenthLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.type	_Z58__device_stub__Z26executeEighteenthLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, @function
_Z58__device_stub__Z26executeEighteenthLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_:
.LFB2121:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L179
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z26executeEighteenthLayer_DSCPdS_S_S_S_S_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L179:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L181
	call	__stack_chk_fail@PLT
.L181:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2121:
	.size	_Z58__device_stub__Z26executeEighteenthLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, .-_Z58__device_stub__Z26executeEighteenthLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.globl	_Z26executeEighteenthLayer_DSCPdS_S_S_S_S_S_
	.type	_Z26executeEighteenthLayer_DSCPdS_S_S_S_S_S_, @function
_Z26executeEighteenthLayer_DSCPdS_S_S_S_S_S_:
.LFB2122:
	.cfi_startproc
	endbr64
	jmp	_Z58__device_stub__Z26executeEighteenthLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.cfi_endproc
.LFE2122:
	.size	_Z26executeEighteenthLayer_DSCPdS_S_S_S_S_S_, .-_Z26executeEighteenthLayer_DSCPdS_S_S_S_S_S_
	.globl	_Z58__device_stub__Z26executeNineteenthLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.type	_Z58__device_stub__Z26executeNineteenthLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, @function
_Z58__device_stub__Z26executeNineteenthLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_:
.LFB2123:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L184
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z26executeNineteenthLayer_PSCPdS_S_S_S_S_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L184:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L186
	call	__stack_chk_fail@PLT
.L186:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2123:
	.size	_Z58__device_stub__Z26executeNineteenthLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, .-_Z58__device_stub__Z26executeNineteenthLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.globl	_Z26executeNineteenthLayer_PSCPdS_S_S_S_S_S_
	.type	_Z26executeNineteenthLayer_PSCPdS_S_S_S_S_S_, @function
_Z26executeNineteenthLayer_PSCPdS_S_S_S_S_S_:
.LFB2124:
	.cfi_startproc
	endbr64
	jmp	_Z58__device_stub__Z26executeNineteenthLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.cfi_endproc
.LFE2124:
	.size	_Z26executeNineteenthLayer_PSCPdS_S_S_S_S_S_, .-_Z26executeNineteenthLayer_PSCPdS_S_S_S_S_S_
	.globl	_Z54__device_stub__Z22executeTwentyLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.type	_Z54__device_stub__Z22executeTwentyLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, @function
_Z54__device_stub__Z22executeTwentyLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_:
.LFB2125:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L189
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z22executeTwentyLayer_DSCPdS_S_S_S_S_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L189:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L191
	call	__stack_chk_fail@PLT
.L191:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2125:
	.size	_Z54__device_stub__Z22executeTwentyLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, .-_Z54__device_stub__Z22executeTwentyLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.globl	_Z22executeTwentyLayer_DSCPdS_S_S_S_S_S_
	.type	_Z22executeTwentyLayer_DSCPdS_S_S_S_S_S_, @function
_Z22executeTwentyLayer_DSCPdS_S_S_S_S_S_:
.LFB2126:
	.cfi_startproc
	endbr64
	jmp	_Z54__device_stub__Z22executeTwentyLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.cfi_endproc
.LFE2126:
	.size	_Z22executeTwentyLayer_DSCPdS_S_S_S_S_S_, .-_Z22executeTwentyLayer_DSCPdS_S_S_S_S_S_
	.globl	_Z57__device_stub__Z25executeTwentyOneLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.type	_Z57__device_stub__Z25executeTwentyOneLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, @function
_Z57__device_stub__Z25executeTwentyOneLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_:
.LFB2127:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L194
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z25executeTwentyOneLayer_PSCPdS_S_S_S_S_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L194:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L196
	call	__stack_chk_fail@PLT
.L196:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2127:
	.size	_Z57__device_stub__Z25executeTwentyOneLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, .-_Z57__device_stub__Z25executeTwentyOneLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.globl	_Z25executeTwentyOneLayer_PSCPdS_S_S_S_S_S_
	.type	_Z25executeTwentyOneLayer_PSCPdS_S_S_S_S_S_, @function
_Z25executeTwentyOneLayer_PSCPdS_S_S_S_S_S_:
.LFB2128:
	.cfi_startproc
	endbr64
	jmp	_Z57__device_stub__Z25executeTwentyOneLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.cfi_endproc
.LFE2128:
	.size	_Z25executeTwentyOneLayer_PSCPdS_S_S_S_S_S_, .-_Z25executeTwentyOneLayer_PSCPdS_S_S_S_S_S_
	.globl	_Z57__device_stub__Z25executeTwentyTwoLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.type	_Z57__device_stub__Z25executeTwentyTwoLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, @function
_Z57__device_stub__Z25executeTwentyTwoLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_:
.LFB2129:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L199
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z25executeTwentyTwoLayer_DSCPdS_S_S_S_S_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L199:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L201
	call	__stack_chk_fail@PLT
.L201:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2129:
	.size	_Z57__device_stub__Z25executeTwentyTwoLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, .-_Z57__device_stub__Z25executeTwentyTwoLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.globl	_Z25executeTwentyTwoLayer_DSCPdS_S_S_S_S_S_
	.type	_Z25executeTwentyTwoLayer_DSCPdS_S_S_S_S_S_, @function
_Z25executeTwentyTwoLayer_DSCPdS_S_S_S_S_S_:
.LFB2130:
	.cfi_startproc
	endbr64
	jmp	_Z57__device_stub__Z25executeTwentyTwoLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.cfi_endproc
.LFE2130:
	.size	_Z25executeTwentyTwoLayer_DSCPdS_S_S_S_S_S_, .-_Z25executeTwentyTwoLayer_DSCPdS_S_S_S_S_S_
	.globl	_Z59__device_stub__Z27executeTwentyThreeLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.type	_Z59__device_stub__Z27executeTwentyThreeLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, @function
_Z59__device_stub__Z27executeTwentyThreeLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_:
.LFB2131:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L204
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z27executeTwentyThreeLayer_PSCPdS_S_S_S_S_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L204:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L206
	call	__stack_chk_fail@PLT
.L206:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2131:
	.size	_Z59__device_stub__Z27executeTwentyThreeLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, .-_Z59__device_stub__Z27executeTwentyThreeLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.globl	_Z27executeTwentyThreeLayer_PSCPdS_S_S_S_S_S_
	.type	_Z27executeTwentyThreeLayer_PSCPdS_S_S_S_S_S_, @function
_Z27executeTwentyThreeLayer_PSCPdS_S_S_S_S_S_:
.LFB2132:
	.cfi_startproc
	endbr64
	jmp	_Z59__device_stub__Z27executeTwentyThreeLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.cfi_endproc
.LFE2132:
	.size	_Z27executeTwentyThreeLayer_PSCPdS_S_S_S_S_S_, .-_Z27executeTwentyThreeLayer_PSCPdS_S_S_S_S_S_
	.globl	_Z58__device_stub__Z26executeTwentyFourLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.type	_Z58__device_stub__Z26executeTwentyFourLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, @function
_Z58__device_stub__Z26executeTwentyFourLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_:
.LFB2133:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L209
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z26executeTwentyFourLayer_DSCPdS_S_S_S_S_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L209:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L211
	call	__stack_chk_fail@PLT
.L211:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2133:
	.size	_Z58__device_stub__Z26executeTwentyFourLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, .-_Z58__device_stub__Z26executeTwentyFourLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.globl	_Z26executeTwentyFourLayer_DSCPdS_S_S_S_S_S_
	.type	_Z26executeTwentyFourLayer_DSCPdS_S_S_S_S_S_, @function
_Z26executeTwentyFourLayer_DSCPdS_S_S_S_S_S_:
.LFB2134:
	.cfi_startproc
	endbr64
	jmp	_Z58__device_stub__Z26executeTwentyFourLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.cfi_endproc
.LFE2134:
	.size	_Z26executeTwentyFourLayer_DSCPdS_S_S_S_S_S_, .-_Z26executeTwentyFourLayer_DSCPdS_S_S_S_S_S_
	.globl	_Z58__device_stub__Z26executeTwentyFiveLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.type	_Z58__device_stub__Z26executeTwentyFiveLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, @function
_Z58__device_stub__Z26executeTwentyFiveLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_:
.LFB2135:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L214
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z26executeTwentyFiveLayer_PSCPdS_S_S_S_S_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L214:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L216
	call	__stack_chk_fail@PLT
.L216:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2135:
	.size	_Z58__device_stub__Z26executeTwentyFiveLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, .-_Z58__device_stub__Z26executeTwentyFiveLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.globl	_Z26executeTwentyFiveLayer_PSCPdS_S_S_S_S_S_
	.type	_Z26executeTwentyFiveLayer_PSCPdS_S_S_S_S_S_, @function
_Z26executeTwentyFiveLayer_PSCPdS_S_S_S_S_S_:
.LFB2136:
	.cfi_startproc
	endbr64
	jmp	_Z58__device_stub__Z26executeTwentyFiveLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.cfi_endproc
.LFE2136:
	.size	_Z26executeTwentyFiveLayer_PSCPdS_S_S_S_S_S_, .-_Z26executeTwentyFiveLayer_PSCPdS_S_S_S_S_S_
	.globl	_Z57__device_stub__Z25executeTwentySixLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.type	_Z57__device_stub__Z25executeTwentySixLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, @function
_Z57__device_stub__Z25executeTwentySixLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_:
.LFB2137:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L219
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z25executeTwentySixLayer_DSCPdS_S_S_S_S_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L219:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L221
	call	__stack_chk_fail@PLT
.L221:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2137:
	.size	_Z57__device_stub__Z25executeTwentySixLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, .-_Z57__device_stub__Z25executeTwentySixLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.globl	_Z25executeTwentySixLayer_DSCPdS_S_S_S_S_S_
	.type	_Z25executeTwentySixLayer_DSCPdS_S_S_S_S_S_, @function
_Z25executeTwentySixLayer_DSCPdS_S_S_S_S_S_:
.LFB2138:
	.cfi_startproc
	endbr64
	jmp	_Z57__device_stub__Z25executeTwentySixLayer_DSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.cfi_endproc
.LFE2138:
	.size	_Z25executeTwentySixLayer_DSCPdS_S_S_S_S_S_, .-_Z25executeTwentySixLayer_DSCPdS_S_S_S_S_S_
	.globl	_Z59__device_stub__Z27executeTwentySevenLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.type	_Z59__device_stub__Z27executeTwentySevenLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, @function
_Z59__device_stub__Z27executeTwentySevenLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_:
.LFB2139:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movq	%rdx, 40(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 112(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L224
	pushq	80(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z27executeTwentySevenLayer_PSCPdS_S_S_S_S_S_(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 208
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	128(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L224:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L226
	call	__stack_chk_fail@PLT
.L226:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2139:
	.size	_Z59__device_stub__Z27executeTwentySevenLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_, .-_Z59__device_stub__Z27executeTwentySevenLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.globl	_Z27executeTwentySevenLayer_PSCPdS_S_S_S_S_S_
	.type	_Z27executeTwentySevenLayer_PSCPdS_S_S_S_S_S_, @function
_Z27executeTwentySevenLayer_PSCPdS_S_S_S_S_S_:
.LFB2140:
	.cfi_startproc
	endbr64
	jmp	_Z59__device_stub__Z27executeTwentySevenLayer_PSCPdS_S_S_S_S_S_PdS_S_S_S_S_S_
	.cfi_endproc
.LFE2140:
	.size	_Z27executeTwentySevenLayer_PSCPdS_S_S_S_S_S_, .-_Z27executeTwentySevenLayer_PSCPdS_S_S_S_S_S_
	.globl	_Z56__device_stub__Z34executeTwentyEightLayer_AvgPoolingPdS_PdS_
	.type	_Z56__device_stub__Z34executeTwentyEightLayer_AvgPoolingPdS_PdS_, @function
_Z56__device_stub__Z34executeTwentyEightLayer_AvgPoolingPdS_PdS_:
.LFB2141:
	.cfi_startproc
	endbr64
	subq	$88, %rsp
	.cfi_def_cfa_offset 96
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	32(%rsp), %rdi
	leaq	44(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 56(%rsp)
	movq	%rsp, %rax
	movq	%rax, 64(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L229
	pushq	24(%rsp)
	.cfi_def_cfa_offset 104
	leaq	_Z34executeTwentyEightLayer_AvgPoolingPdS_(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 112
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	72(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 104
	popq	%rdx
	.cfi_def_cfa_offset 96
.L229:
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L231
	call	__stack_chk_fail@PLT
.L231:
	addq	$88, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2141:
	.size	_Z56__device_stub__Z34executeTwentyEightLayer_AvgPoolingPdS_PdS_, .-_Z56__device_stub__Z34executeTwentyEightLayer_AvgPoolingPdS_PdS_
	.globl	_Z34executeTwentyEightLayer_AvgPoolingPdS_
	.type	_Z34executeTwentyEightLayer_AvgPoolingPdS_, @function
_Z34executeTwentyEightLayer_AvgPoolingPdS_:
.LFB2142:
	.cfi_startproc
	endbr64
	jmp	_Z56__device_stub__Z34executeTwentyEightLayer_AvgPoolingPdS_PdS_
	.cfi_endproc
.LFE2142:
	.size	_Z34executeTwentyEightLayer_AvgPoolingPdS_, .-_Z34executeTwentyEightLayer_AvgPoolingPdS_
	.globl	_Z63__device_stub__Z37executeTwentyNineLayer_FullyConnectedPdS_S_S_PdS_S_S_
	.type	_Z63__device_stub__Z37executeTwentyNineLayer_FullyConnectedPdS_S_S_PdS_S_S_, @function
_Z63__device_stub__Z37executeTwentyNineLayer_FullyConnectedPdS_S_S_PdS_S_S_:
.LFB2143:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	40(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 72(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 80(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L234
	pushq	40(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z37executeTwentyNineLayer_FullyConnectedPdS_S_S_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 144
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	88(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L234:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L236
	call	__stack_chk_fail@PLT
.L236:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2143:
	.size	_Z63__device_stub__Z37executeTwentyNineLayer_FullyConnectedPdS_S_S_PdS_S_S_, .-_Z63__device_stub__Z37executeTwentyNineLayer_FullyConnectedPdS_S_S_PdS_S_S_
	.globl	_Z37executeTwentyNineLayer_FullyConnectedPdS_S_S_
	.type	_Z37executeTwentyNineLayer_FullyConnectedPdS_S_S_, @function
_Z37executeTwentyNineLayer_FullyConnectedPdS_S_S_:
.LFB2144:
	.cfi_startproc
	endbr64
	jmp	_Z63__device_stub__Z37executeTwentyNineLayer_FullyConnectedPdS_S_S_PdS_S_S_
	.cfi_endproc
.LFE2144:
	.size	_Z37executeTwentyNineLayer_FullyConnectedPdS_S_S_, .-_Z37executeTwentyNineLayer_FullyConnectedPdS_S_S_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z37executeTwentyNineLayer_FullyConnectedPdS_S_S_"
.LC1:
	.string	"_Z34executeTwentyEightLayer_AvgPoolingPdS_"
.LC2:
	.string	"_Z27executeTwentySevenLayer_PSCPdS_S_S_S_S_S_"
.LC3:
	.string	"_Z25executeTwentySixLayer_DSCPdS_S_S_S_S_S_"
.LC4:
	.string	"_Z26executeTwentyFiveLayer_PSCPdS_S_S_S_S_S_"
.LC5:
	.string	"_Z26executeTwentyFourLayer_DSCPdS_S_S_S_S_S_"
.LC6:
	.string	"_Z27executeTwentyThreeLayer_PSCPdS_S_S_S_S_S_"
.LC7:
	.string	"_Z25executeTwentyTwoLayer_DSCPdS_S_S_S_S_S_"
.LC8:
	.string	"_Z25executeTwentyOneLayer_PSCPdS_S_S_S_S_S_"
.LC9:
	.string	"_Z22executeTwentyLayer_DSCPdS_S_S_S_S_S_"
.LC10:
	.string	"_Z26executeNineteenthLayer_PSCPdS_S_S_S_S_S_"
.LC11:
	.string	"_Z26executeEighteenthLayer_DSCPdS_S_S_S_S_S_"
.LC12:
	.string	"_Z27executeSeventeenthLayer_PSCPdS_S_S_S_S_S_"
.LC13:
	.string	"_Z25executeSixteenthLayer_DSCPdS_S_S_S_S_S_"
.LC14:
	.string	"_Z25executeFifteenthLayer_PSCPdS_S_S_S_S_S_"
.LC15:
	.string	"_Z26executeFourteenthLayer_DSCPdS_S_S_S_S_S_"
.LC16:
	.string	"_Z26executeThirteenthLayer_PSCPdS_S_S_S_S_S_"
.LC17:
	.string	"_Z23executeTwelfthLayer_DSCPdS_S_S_S_S_S_"
.LC18:
	.string	"_Z24executeEleventhLayer_PSCPdS_S_S_S_S_S_"
.LC19:
	.string	"_Z21executeTenthLayer_DSCPdS_S_S_S_S_S_"
.LC20:
	.string	"_Z21executeNinthLayer_PSCPdS_S_S_S_S_S_"
.LC21:
	.string	"_Z22executeEighthLayer_DSCPdS_S_S_S_S_S_"
.LC22:
	.string	"_Z29executeSeventhLayer_PSC_partDPdS_S_S_S_S_S_"
.LC23:
	.string	"_Z29executeSeventhLayer_PSC_partCPdS_S_S_S_S_S_"
.LC24:
	.string	"_Z29executeSeventhLayer_PSC_partBPdS_S_S_S_S_S_"
.LC25:
	.string	"_Z29executeSeventhLayer_PSC_partAPdS_S_S_S_S_S_"
.LC26:
	.string	"_Z27executeSixthLayer_DSC_partDPdS_S_S_S_S_S_"
.LC27:
	.string	"_Z27executeSixthLayer_DSC_partCPdS_S_S_S_S_S_"
.LC28:
	.string	"_Z27executeSixthLayer_DSC_partBPdS_S_S_S_S_S_"
.LC29:
	.string	"_Z27executeSixthLayer_DSC_partAPdS_S_S_S_S_S_"
.LC30:
	.string	"_Z27executeFifthLayer_PSC_partDPdS_S_S_S_S_S_"
.LC31:
	.string	"_Z27executeFifthLayer_PSC_partCPdS_S_S_S_S_S_"
.LC32:
	.string	"_Z27executeFifthLayer_PSC_partBPdS_S_S_S_S_S_"
.LC33:
	.string	"_Z27executeFifthLayer_PSC_partAPdS_S_S_S_S_S_"
.LC34:
	.string	"_Z28executeFourthLayer_DSC_partDPdS_S_S_S_S_S_"
.LC35:
	.string	"_Z28executeFourthLayer_DSC_partCPdS_S_S_S_S_S_"
.LC36:
	.string	"_Z28executeFourthLayer_DSC_partBPdS_S_S_S_S_S_"
.LC37:
	.string	"_Z28executeFourthLayer_DSC_partAPdS_S_S_S_S_S_"
.LC38:
	.string	"_Z27executeThirdLayer_PSC_partCPdS_S_S_S_S_S_"
.LC39:
	.string	"_Z27executeThirdLayer_PSC_partBPdS_S_S_S_S_S_"
.LC40:
	.string	"_Z27executeThirdLayer_PSC_partAPdS_S_S_S_S_S_"
.LC41:
	.string	"_Z28executeSecondLayer_DSC_partCPdS_S_S_S_S_S_"
.LC42:
	.string	"_Z28executeSecondLayer_DSC_partBPdS_S_S_S_S_S_"
.LC43:
	.string	"_Z28executeSecondLayer_DSC_partAPdS_S_S_S_S_S_"
.LC44:
	.string	"_Z30executeFirstLayer_CONV3D_partCPdS_S_S_S_S_S_"
.LC45:
	.string	"_Z30executeFirstLayer_CONV3D_partBPdS_S_S_S_S_S_"
.LC46:
	.string	"_Z30executeFirstLayer_CONV3D_partAPdS_S_S_S_S_S_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2146:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z37executeTwentyNineLayer_FullyConnectedPdS_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z34executeTwentyEightLayer_AvgPoolingPdS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z27executeTwentySevenLayer_PSCPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z25executeTwentySixLayer_DSCPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z26executeTwentyFiveLayer_PSCPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z26executeTwentyFourLayer_DSCPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z27executeTwentyThreeLayer_PSCPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z25executeTwentyTwoLayer_DSCPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC8(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_Z25executeTwentyOneLayer_PSCPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC9(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z22executeTwentyLayer_DSCPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC10(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z26executeNineteenthLayer_PSCPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC11(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z26executeEighteenthLayer_DSCPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC12(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z27executeSeventeenthLayer_PSCPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC13(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z25executeSixteenthLayer_DSCPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC14(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z25executeFifteenthLayer_PSCPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC15(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z26executeFourteenthLayer_DSCPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC16(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_Z26executeThirteenthLayer_PSCPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC17(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z23executeTwelfthLayer_DSCPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC18(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z24executeEleventhLayer_PSCPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC19(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z21executeTenthLayer_DSCPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC20(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z21executeNinthLayer_PSCPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC21(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z22executeEighthLayer_DSCPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC22(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z29executeSeventhLayer_PSC_partDPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC23(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z29executeSeventhLayer_PSC_partCPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC24(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_Z29executeSeventhLayer_PSC_partBPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC25(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z29executeSeventhLayer_PSC_partAPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC26(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z27executeSixthLayer_DSC_partDPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC27(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z27executeSixthLayer_DSC_partCPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC28(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z27executeSixthLayer_DSC_partBPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC29(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z27executeSixthLayer_DSC_partAPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC30(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z27executeFifthLayer_PSC_partDPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC31(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z27executeFifthLayer_PSC_partCPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC32(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_Z27executeFifthLayer_PSC_partBPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC33(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z27executeFifthLayer_PSC_partAPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC34(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z28executeFourthLayer_DSC_partDPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC35(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z28executeFourthLayer_DSC_partCPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC36(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z28executeFourthLayer_DSC_partBPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC37(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z28executeFourthLayer_DSC_partAPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC38(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z27executeThirdLayer_PSC_partCPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC39(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z27executeThirdLayer_PSC_partBPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC40(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	movq	%rdx, %rcx
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_Z27executeThirdLayer_PSC_partAPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC41(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z28executeSecondLayer_DSC_partCPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC42(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z28executeSecondLayer_DSC_partBPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC43(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z28executeSecondLayer_DSC_partAPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC44(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z30executeFirstLayer_CONV3D_partCPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC45(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z30executeFirstLayer_CONV3D_partBPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC46(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z30executeFirstLayer_CONV3D_partAPdS_S_S_S_S_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2146:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>

/*  ************************************************** FIRST LAYER START ********************************************************* */
/*
    Layer 1: Normal 3D Convolution Layer
    Input: 225 * 225 * 3 (Padding of 1)
    Weight: 3 * 3 * 3 with a Stride of 2
    Output: 112 * 112 * 32
    Next Layer is a padding layer, so padding operation is handled in this layer itself & hence
    Final Output = 114 * 114 * 32
*/
__global__ void executeFirstLayer_CONV3D_partA(double *Layer1_Neurons_GPU,
                            double *Layer1_Weights_GPU,
                            double *Layer2_Neurons_GPU,
                            double *Layer1_Mean_GPU,
                            double *Layer1_StanDev_GPU,
                            double *Layer1_Gamma_GPU,
                            double *Layer1_Beta_GPU
                        )
{
	double product = 0.0;
    int outputOffset = 115;
    int stride = 2;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 114 * 114)   // channel to work with
                        + (blockIdx.y * 32 * 114)    // Position in the grid row-wise
                        + (blockIdx.z * 32)          // Position in the grid column-wise
                        + (threadIdx.x * 114)
                        + (threadIdx.y);

    int weight_Position = filter_number * 27;

    int input_Position = ((blockIdx.y * 32 * 225) * stride) // Position in the grid row-wise
                       + (blockIdx.z * 32 * stride)         // Position in the grid column-wise
                       + (threadIdx.x * 225 * stride )
                       + (threadIdx.y * stride);

    /* RGB weights and input 3*3*3 */
    for(int channel = 0; channel < 3; channel++) // This is the Channel loop
    {
        for(int row = 0; row < 3; row++)       // This is the Row Loop
        {
            product += ((Layer1_Neurons_GPU[(channel * 225 * 225) + input_Position + (row * 225)] * Layer1_Weights_GPU[weight_Position + (channel * 3 * 3) + (row * 3)])
                    + (Layer1_Neurons_GPU[(channel * 225 * 225) + input_Position + (row * 225) + 1] * Layer1_Weights_GPU[weight_Position + (channel * 3 * 3) + (row * 3) + 1])
                    + (Layer1_Neurons_GPU[(channel * 225 * 225) + input_Position + (row * 225) + 2] * Layer1_Weights_GPU[weight_Position + (channel * 3 * 3) + (row * 3) + 2]));
        }
    }

    double Z = (product - Layer1_Mean_GPU[filter_number]) / Layer1_StanDev_GPU[filter_number];
    Z = (Z * Layer1_Gamma_GPU[filter_number]) + Layer1_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer2_Neurons_GPU[output_Position + outputOffset] = Z;
}

__global__ void executeFirstLayer_CONV3D_partB(double *Layer1_Neurons_GPU,
                            double *Layer1_Weights_GPU,
                            double *Layer2_Neurons_GPU,
                            double *Layer1_Mean_GPU,
                            double *Layer1_StanDev_GPU,
                            double *Layer1_Gamma_GPU,
                            double *Layer1_Beta_GPU
                        )
{
	double product = 0.0;
    int outputOffset = 115;
    int stride = 2;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 114 * 114)   // channel to work with
                        + (blockIdx.y * 16 * 114 + 96)  // Position in the grid row-wise and there is no column-wise position
                        + (threadIdx.x * 114)           // Position inside the 256 (16 * 16) block
                        + (threadIdx.y);

    int weight_Position = filter_number * 27;

    int input_Position = ((blockIdx.y * 16 * 225) * stride) + (96 * stride) // Position in the grid row-wise and column-wise
                       + (threadIdx.x * 225 * stride)
                       + (threadIdx.y * stride);

    /* RGB weights and input 3*3*3 */
    for(int channel = 0; channel < 3; channel++) // This is the Channel loop
    {
        for(int row = 0; row < 3; row++)       // This is the Row Loop
        {
            product += ((Layer1_Neurons_GPU[(channel * 225 * 225) + input_Position + (row * 225)] * Layer1_Weights_GPU[weight_Position + (channel * 3 * 3) + (row * 3)])
                    + (Layer1_Neurons_GPU[(channel * 225 * 225) + input_Position + (row * 225) + 1] * Layer1_Weights_GPU[weight_Position + (channel * 3 * 3) + (row * 3) + 1])
                    + (Layer1_Neurons_GPU[(channel * 225 * 225) + input_Position + (row * 225) + 2] * Layer1_Weights_GPU[weight_Position + (channel * 3 * 3) + (row * 3) + 2]));
        }
    }

    double Z = (product - Layer1_Mean_GPU[filter_number]) / Layer1_StanDev_GPU[filter_number];
    Z = (Z * Layer1_Gamma_GPU[filter_number]) + Layer1_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer2_Neurons_GPU[output_Position + outputOffset] = Z;
}

__global__ void executeFirstLayer_CONV3D_partC(double *Layer1_Neurons_GPU,
                            double *Layer1_Weights_GPU,
                            double *Layer2_Neurons_GPU,
                            double *Layer1_Mean_GPU,
                            double *Layer1_StanDev_GPU,
                            double *Layer1_Gamma_GPU,
                            double *Layer1_Beta_GPU
                        )
{
	double product = 0.0;
    int outputOffset = 115;
    int stride = 2;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 114 * 114)   // channel to work with
                        + (96 * 114)                    // Position in the grid row-wise as row is last
                        + (blockIdx.y * 16)             // Position in the grid column-wise
                        + (threadIdx.x * 114)           // Position inside the 256 (16 * 16) block
                        + (threadIdx.y);

    int weight_Position = filter_number * 27;

    int input_Position = ((96 * 225) * stride)
                       + (blockIdx.y * 16 * stride)     // Position in the grid row-wise and column-wise
                       + (threadIdx.x * 225 * stride)
                       + (threadIdx.y * stride);

    /* RGB weights and input 3*3*3 */
    for(int channel = 0; channel < 3; channel++) // This is the Channel loop
    {
        for(int row = 0; row < 3; row++)       // This is the Row Loop
        {
            product += ((Layer1_Neurons_GPU[(channel * 225 * 225) + input_Position + (row * 225)] * Layer1_Weights_GPU[weight_Position + (channel * 3 * 3) + (row * 3)])
                    + (Layer1_Neurons_GPU[(channel * 225 * 225) + input_Position + (row * 225) + 1] * Layer1_Weights_GPU[weight_Position + (channel * 3 * 3) + (row * 3) + 1])
                    + (Layer1_Neurons_GPU[(channel * 225 * 225) + input_Position + (row * 225) + 2] * Layer1_Weights_GPU[weight_Position + (channel * 3 * 3) + (row * 3) + 2]));
        }
    }

    double Z = (product - Layer1_Mean_GPU[filter_number]) / Layer1_StanDev_GPU[filter_number];
    Z = (Z * Layer1_Gamma_GPU[filter_number]) + Layer1_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer2_Neurons_GPU[output_Position + outputOffset] = Z;
}
/*  ************************************************** FIRST LAYER END ************************************************************ */

/*  ************************************************** SECOND LAYER START ********************************************************* */
/*
    Layer 2: Depthwise Separable Convolution Layer
    Input: 114 * 114 * 3 (After padding)
    Weight: 3 * 3 * 32 with a Stride of 1
    Output: 112 * 112 * 32
*/
__global__ void executeSecondLayer_DSC_partA(double *Layer2_Neurons_GPU,
                            double *Layer2_Weights_GPU,
                            double *Layer3_Neurons_GPU,
                            double *Layer2_Mean_GPU,
                            double *Layer2_StanDev_GPU,
                            double *Layer2_Gamma_GPU,
                            double *Layer2_Beta_GPU
                        )
{
	double product = 0.0;

    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 112 * 112)   // channel to work with
                        + (blockIdx.y * 32 * 112)    // Position in the grid row-wise
                        + (blockIdx.z * 32)          // Position in the grid column-wise
                        + (threadIdx.x * 112)
                        + (threadIdx.y);

    int weight_Position = filter_number * 9;

    int input_Position = (blockIdx.y * 32 * 114) // Position in the grid row-wise
                       + (blockIdx.z * 32)         // Position in the grid column-wise
                       + (threadIdx.x * 114)
                       + (threadIdx.y);

    for(int row = 0; row < 3; row++)       // This is the Row Loop
    {
        product += ((Layer2_Neurons_GPU[(filter_number * 114 * 114) + input_Position + (row * 114)] * Layer2_Weights_GPU[weight_Position + (row * 3)])
                + (Layer2_Neurons_GPU[(filter_number * 114 * 114) + input_Position + (row * 114) + 1] * Layer2_Weights_GPU[weight_Position + (row * 3) + 1])
                + (Layer2_Neurons_GPU[(filter_number * 114 * 114) + input_Position + (row * 114) + 2] * Layer2_Weights_GPU[weight_Position + (row * 3) + 2]));
    }

    double Z = (product - Layer2_Mean_GPU[filter_number]) / Layer2_StanDev_GPU[filter_number];
    Z = (Z * Layer2_Gamma_GPU[filter_number]) + Layer2_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer3_Neurons_GPU[output_Position] = Z;
}

__global__ void executeSecondLayer_DSC_partB(double *Layer2_Neurons_GPU,
                                    double *Layer2_Weights_GPU,
                                    double *Layer3_Neurons_GPU,
                                    double *Layer2_Mean_GPU,
                                    double *Layer2_StanDev_GPU,
                                    double *Layer2_Gamma_GPU,
                                    double *Layer2_Beta_GPU
                                )
{
    double product = 0.0;

    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 112 * 112)   // channel to work with
                        + (blockIdx.y * 16 * 112 + 96)  // Position in the grid row-wise and there is no column-wise position
                        + (threadIdx.x * 112)           // Position inside the 256 (16 * 16) block
                        + (threadIdx.y);

    int weight_Position = filter_number * 9;

    int input_Position  = (blockIdx.y * 16 * 114)
                        + (96) // Position in the grid row-wise and column-wise
                        + (threadIdx.x * 114)
                        + (threadIdx.y);

    for(int row = 0; row < 3; row++)       // This is the Row Loop
    {
        product += ((Layer2_Neurons_GPU[(filter_number * 114 * 114) + input_Position + (row * 114)] * Layer2_Weights_GPU[weight_Position + (row * 3)])
                + (Layer2_Neurons_GPU[(filter_number * 114 * 114) + input_Position + (row * 114) + 1] * Layer2_Weights_GPU[weight_Position + (row * 3) + 1])
                + (Layer2_Neurons_GPU[(filter_number * 114 * 114) + input_Position + (row * 114) + 2] * Layer2_Weights_GPU[weight_Position + (row * 3) + 2]));
    }

    double Z = (product - Layer2_Mean_GPU[filter_number]) / Layer2_StanDev_GPU[filter_number];
    Z = (Z * Layer2_Gamma_GPU[filter_number]) + Layer2_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer3_Neurons_GPU[output_Position] = Z;
}

__global__ void executeSecondLayer_DSC_partC(double *Layer2_Neurons_GPU,
                                    double *Layer2_Weights_GPU,
                                    double *Layer3_Neurons_GPU,
                                    double *Layer2_Mean_GPU,
                                    double *Layer2_StanDev_GPU,
                                    double *Layer2_Gamma_GPU,
                                    double *Layer2_Beta_GPU
                                )
{
    double product = 0.0;

    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 112 * 112)   // channel to work with
                        + (96 * 112)                    // Position in the grid row-wise as row is last
                        + (blockIdx.y * 16)             // Position in the grid column-wise
                        + (threadIdx.x * 112)           // Position inside the 256 (16 * 16) block
                        + (threadIdx.y);

    int weight_Position = filter_number * 9;

    int input_Position = (96 * 114)
                        + (blockIdx.y * 16)     // Position in the grid row-wise and column-wise
                        + (threadIdx.x * 114)
                        + (threadIdx.y);

    for(int row = 0; row < 3; row++)       // This is the Row Loop
    {
        product += ((Layer2_Neurons_GPU[(filter_number * 114 * 114) + input_Position + (row * 114)] * Layer2_Weights_GPU[weight_Position + (row * 3)])
                + (Layer2_Neurons_GPU[(filter_number * 114 * 114) + input_Position + (row * 114) + 1] * Layer2_Weights_GPU[weight_Position + (row * 3) + 1])
                + (Layer2_Neurons_GPU[(filter_number * 114 * 114) + input_Position + (row * 114) + 2] * Layer2_Weights_GPU[weight_Position + (row * 3) + 2]));
    }

    double Z = (product - Layer2_Mean_GPU[filter_number]) / Layer2_StanDev_GPU[filter_number];
    Z = (Z * Layer2_Gamma_GPU[filter_number]) + Layer2_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer3_Neurons_GPU[output_Position] = Z;
}
/*  ************************************************** SECOND LAYER END ********************************************************* */

/*  ************************************************** THIRD LAYER START ******************************************************** */
/*
    Layer 3: Pointwise Separable Convolution Layer
    Input: 112 * 112 * 32 (After padding)
    Weight: 1 * 1 * 32 * 64 with a Stride of 1
    Output: 113 * 113 * 64 (Padding of 1 is handled in this layer execution itself)
*/
__global__ void executeThirdLayer_PSC_partA(double *Layer3_Neurons_GPU,
    double *Layer3_Weights_GPU,
    double *Layer4_Neurons_GPU,
    double *Layer3_Mean_GPU,
    double *Layer3_StanDev_GPU,
    double *Layer3_Gamma_GPU,
    double *Layer3_Beta_GPU
)
{
    double product = 0.0;

    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 113 * 113)   // channel to work with
                        + (blockIdx.y * 32 * 113)    // Position in the grid row-wise
                        + (blockIdx.z * 32)          // Position in the grid column-wise
                        + (threadIdx.x * 113)
                        + (threadIdx.y);

    int weight_Position = filter_number * 32;

    int input_Position = (blockIdx.y * 32 * 112) // Position in the grid row-wise
                       + (blockIdx.z * 32)         // Position in the grid column-wise
                       + (threadIdx.x * 112)
                       + (threadIdx.y);

    for(int channel = 0; channel < 32; channel++)       // This is the channel loop as we have 32 channels to work with
    {
        product += (Layer3_Neurons_GPU[(channel * 112 * 112) + input_Position] * Layer3_Weights_GPU[weight_Position + channel]);
    }

    double Z = (product - Layer3_Mean_GPU[filter_number]) / Layer3_StanDev_GPU[filter_number];
    Z = (Z * Layer3_Gamma_GPU[filter_number]) + Layer3_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer4_Neurons_GPU[output_Position] = Z;
}

__global__ void executeThirdLayer_PSC_partB(double *Layer3_Neurons_GPU,
    double *Layer3_Weights_GPU,
    double *Layer4_Neurons_GPU,
    double *Layer3_Mean_GPU,
    double *Layer3_StanDev_GPU,
    double *Layer3_Gamma_GPU,
    double *Layer3_Beta_GPU
)
{
    double product = 0.0;

    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 113 * 113)   // channel to work with
                        + (blockIdx.y * 16 * 113 + 96)  // Position in the grid row-wise and there is no column-wise position
                        + (threadIdx.x * 113)           // Position inside the 256 (16 * 16) block
                        + (threadIdx.y);

    int weight_Position = filter_number * 32;

    int input_Position = (blockIdx.y * 16 * 112)         // Position in the grid row-wise
                       + (96)                   // Position in the grid column-wise
                       + (threadIdx.x * 112)
                       + (threadIdx.y);

    for(int channel = 0 ; channel < 32 ; channel++) // Channel loop as we have 32 input channels to work with
    {
        product += (Layer3_Neurons_GPU[(channel * 112 * 112) + input_Position] * Layer3_Weights_GPU[weight_Position + channel]);
    }

    double Z = (product - Layer3_Mean_GPU[filter_number]) / Layer3_StanDev_GPU[filter_number];
    Z = (Z * Layer3_Gamma_GPU[filter_number]) + Layer3_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer4_Neurons_GPU[output_Position] = Z;
}

__global__ void executeThirdLayer_PSC_partC(double *Layer3_Neurons_GPU,
    double *Layer3_Weights_GPU,
    double *Layer4_Neurons_GPU,
    double *Layer3_Mean_GPU,
    double *Layer3_StanDev_GPU,
    double *Layer3_Gamma_GPU,
    double *Layer3_Beta_GPU
)
{
    double product = 0.0;

    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 113 * 113)   // channel to work with
                        + (96 * 113)                    // Position in the grid row-wise as row is last
                        + (blockIdx.y * 16)             // Position in the grid column-wise
                        + (threadIdx.x * 113)           // Position inside the 256 (16 * 16) block
                        + (threadIdx.y);

    int weight_Position = filter_number * 32;

    int input_Position = (96 * 112)            // row-wise: the bottom part of the grid after 96th row
                       + (blockIdx.y * 16)     // column-wise: block number in the 6 blocks of 16 * 16 threads
                       + (threadIdx.x * 112)   // Position inside one the above block row-wise
                       + (threadIdx.y);        // Position inside one the above block column-wise

    for(int channel = 0 ; channel < 32 ; channel++) // Channel loop as we have 32 input channels to work with
    {
        product += (Layer3_Neurons_GPU[(channel * 112 * 112) + input_Position] * Layer3_Weights_GPU[weight_Position + channel]);
    }

    double Z = (product - Layer3_Mean_GPU[filter_number]) / Layer3_StanDev_GPU[filter_number];
    Z = (Z * Layer3_Gamma_GPU[filter_number]) + Layer3_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer4_Neurons_GPU[output_Position] = Z;
}
/*  ************************************************** THIRD LAYER END ********************************************************* */

/*  ************************************************** FOURTH LAYER START ****************************************************** */
/*
    Layer 4: Depthwise Separable Convolution Layer
    Input: 113 * 113 * 64
    Weight: 3 * 3 * 64 with a Stride of 2
    Output: 56 * 56 * 64
*/
__global__ void executeFourthLayer_DSC_partA(double *Layer4_Neurons_GPU,
    double *Layer4_Weights_GPU,
    double *Layer5_Neurons_GPU,
    double *Layer4_Mean_GPU,
    double *Layer4_StanDev_GPU,
    double *Layer4_Gamma_GPU,
    double *Layer4_Beta_GPU
)
{
    double product = 0.0;
    int stride = 2;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 56 * 56)   // channel to work with
                        + (threadIdx.x * 56)
                        + (threadIdx.y);

    int weight_Position = filter_number * 9;

    int input_Position = (threadIdx.x * 113 * stride )
                       + (threadIdx.y * stride);

    for(int row = 0; row < 3; row++)       // This is the Row Loop
    {
        product += ((Layer4_Neurons_GPU[(filter_number * 113 * 113) + input_Position + (row * 113)] * Layer4_Weights_GPU[weight_Position + (row * 3)])
                + (Layer4_Neurons_GPU[(filter_number * 113 * 113) + input_Position + (row * 113) + 1] * Layer4_Weights_GPU[weight_Position + (row * 3) + 1])
                + (Layer4_Neurons_GPU[(filter_number * 113 * 113) + input_Position + (row * 113) + 2] * Layer4_Weights_GPU[weight_Position + (row * 3) + 2]));
    }

    double Z = (product - Layer4_Mean_GPU[filter_number]) / Layer4_StanDev_GPU[filter_number];
    Z = (Z * Layer4_Gamma_GPU[filter_number]) + Layer4_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer5_Neurons_GPU[output_Position] = Z;
}

__global__ void executeFourthLayer_DSC_partB(double *Layer4_Neurons_GPU,
    double *Layer4_Weights_GPU,
    double *Layer5_Neurons_GPU,
    double *Layer4_Mean_GPU,
    double *Layer4_StanDev_GPU,
    double *Layer4_Gamma_GPU,
    double *Layer4_Beta_GPU
)
{
    double product = 0.0;
    int stride = 2;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 56 * 56)   // channel to work with
                        + (threadIdx.x * 56)
                        + (threadIdx.y + 32);

    int weight_Position = filter_number * 9;

    int input_Position = (threadIdx.x * 113 * stride)
                       + (threadIdx.y * stride)
                       + (32 * stride);

    for(int row = 0; row < 3; row++)       // This is the Row Loop
    {
        product += ((Layer4_Neurons_GPU[(filter_number * 113 * 113) + input_Position + (row * 113)] * Layer4_Weights_GPU[weight_Position + (row * 3)])
                + (Layer4_Neurons_GPU[(filter_number * 113 * 113) + input_Position + (row * 113) + 1] * Layer4_Weights_GPU[weight_Position + (row * 3) + 1])
                + (Layer4_Neurons_GPU[(filter_number * 113 * 113) + input_Position + (row * 113) + 2] * Layer4_Weights_GPU[weight_Position + (row * 3) + 2]));
    }

    double Z = (product - Layer4_Mean_GPU[filter_number]) / Layer4_StanDev_GPU[filter_number];
    Z = (Z * Layer4_Gamma_GPU[filter_number]) + Layer4_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer5_Neurons_GPU[output_Position] = Z;
}

__global__ void executeFourthLayer_DSC_partC(double *Layer4_Neurons_GPU,
    double *Layer4_Weights_GPU,
    double *Layer5_Neurons_GPU,
    double *Layer4_Mean_GPU,
    double *Layer4_StanDev_GPU,
    double *Layer4_Gamma_GPU,
    double *Layer4_Beta_GPU
)
{
    double product = 0.0;
    int stride = 2;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 56 * 56)   // channel to work with
                        + (56 * 32)
                        + (threadIdx.x * 56)
                        + (threadIdx.y);

    int weight_Position = filter_number * 9;

    int input_Position = (113 * 32 * stride)
                       + (threadIdx.x * 113 * stride)
                       + (threadIdx.y * stride);

    for(int row = 0; row < 3; row++)       // This is the Row Loop
    {
        product += ((Layer4_Neurons_GPU[(filter_number * 113 * 113) + input_Position + (row * 113)] * Layer4_Weights_GPU[weight_Position + (row * 3)])
                + (Layer4_Neurons_GPU[(filter_number * 113 * 113) + input_Position + (row * 113) + 1] * Layer4_Weights_GPU[weight_Position + (row * 3) + 1])
                + (Layer4_Neurons_GPU[(filter_number * 113 * 113) + input_Position + (row * 113) + 2] * Layer4_Weights_GPU[weight_Position + (row * 3) + 2]));
    }

    double Z = (product - Layer4_Mean_GPU[filter_number]) / Layer4_StanDev_GPU[filter_number];
    Z = (Z * Layer4_Gamma_GPU[filter_number]) + Layer4_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer5_Neurons_GPU[output_Position] = Z;
}

__global__ void executeFourthLayer_DSC_partD(double *Layer4_Neurons_GPU,
    double *Layer4_Weights_GPU,
    double *Layer5_Neurons_GPU,
    double *Layer4_Mean_GPU,
    double *Layer4_StanDev_GPU,
    double *Layer4_Gamma_GPU,
    double *Layer4_Beta_GPU
)
{
    double product = 0.0;
    int stride = 2;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 56 * 56)   // channel to work with
                        + (56 * 32)
                        + 32
                        + (threadIdx.x * 56)
                        + (threadIdx.y);

    int weight_Position = filter_number * 9;

    int input_Position = (113 * 32 * stride)
                       + (32 * stride)
                       + (threadIdx.x * 113 * stride)
                       + (threadIdx.y * stride);

    for(int row = 0; row < 3; row++) // This is the Row Loop
    {
        product += ((Layer4_Neurons_GPU[(filter_number * 113 * 113) + input_Position + (row * 113)] * Layer4_Weights_GPU[weight_Position + (row * 3)])
                + (Layer4_Neurons_GPU[(filter_number * 113 * 113) + input_Position + (row * 113) + 1] * Layer4_Weights_GPU[weight_Position + (row * 3) + 1])
                + (Layer4_Neurons_GPU[(filter_number * 113 * 113) + input_Position + (row * 113) + 2] * Layer4_Weights_GPU[weight_Position + (row * 3) + 2]));
    }

    double Z = (product - Layer4_Mean_GPU[filter_number]) / Layer4_StanDev_GPU[filter_number];
    Z = (Z * Layer4_Gamma_GPU[filter_number]) + Layer4_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer5_Neurons_GPU[output_Position] = Z;
}
/*  ************************************************** FOURTH LAYER END ****************************************************** */

/*  *************************************************** FIFTH LAYER START **************************************************** */
/*
    Layer 5: Pointwise Separable Convolution Layer
    Input: 56 * 56 * 64
    Weight: 1 * 1 * 64 * 128 with a Stride of 1
    Output: 58 * 58 * 128 (Padding for the next layer is handled here itself)
*/
__global__ void executeFifthLayer_PSC_partA(double *Layer5_Neurons_GPU,
    double *Layer5_Weights_GPU,
    double *Layer6_Neurons_GPU,
    double *Layer5_Mean_GPU,
    double *Layer5_StanDev_GPU,
    double *Layer5_Gamma_GPU,
    double *Layer5_Beta_GPU
)
{
    double product = 0.0;
    int offset = 59;

    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 58 * 58)   // channel to work with
                        + (threadIdx.x * 58)
                        + (threadIdx.y);

    int weight_Position = filter_number * 64;

    int input_Position = (threadIdx.x * 56)
                       + (threadIdx.y);

    for(int channel = 0; channel < 64; channel++)       // This is the channel loop as we have 32 channels to work with
    {
        product += (Layer5_Neurons_GPU[(channel * 56 * 56) + input_Position] * Layer5_Weights_GPU[weight_Position + channel]);
    }

    double Z = (product - Layer5_Mean_GPU[filter_number]) / Layer5_StanDev_GPU[filter_number];
    Z = (Z * Layer5_Gamma_GPU[filter_number]) + Layer5_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer6_Neurons_GPU[output_Position + offset] = Z;
}

__global__ void executeFifthLayer_PSC_partB(double *Layer5_Neurons_GPU,
    double *Layer5_Weights_GPU,
    double *Layer6_Neurons_GPU,
    double *Layer5_Mean_GPU,
    double *Layer5_StanDev_GPU,
    double *Layer5_Gamma_GPU,
    double *Layer5_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;
    int offset = 59;

    // Output position
    int output_Position = (filter_number * 58 * 58)   // channel to work with
                        + (threadIdx.x * 58)
                        + (threadIdx.y + 32);

    int weight_Position = filter_number * 64;

    int input_Position = (threadIdx.x * 56)
                       + (threadIdx.y)
                       + (32);

    for(int channel = 0; channel < 64; channel++)       // This is the channel loop as we have 32 channels to work with
    {
        product += (Layer5_Neurons_GPU[(channel * 56 * 56) + input_Position] * Layer5_Weights_GPU[weight_Position + channel]);
    }

    double Z = (product - Layer5_Mean_GPU[filter_number]) / Layer5_StanDev_GPU[filter_number];
    Z = (Z * Layer5_Gamma_GPU[filter_number]) + Layer5_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer6_Neurons_GPU[output_Position + offset] = Z;
}

__global__ void executeFifthLayer_PSC_partC(double *Layer5_Neurons_GPU,
    double *Layer5_Weights_GPU,
    double *Layer6_Neurons_GPU,
    double *Layer5_Mean_GPU,
    double *Layer5_StanDev_GPU,
    double *Layer5_Gamma_GPU,
    double *Layer5_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;
    int offset = 59;

    // Output position
    int output_Position = (filter_number * 58 * 58)   // channel to work with
                        + (58 * 32)
                        + (threadIdx.x * 58)
                        + (threadIdx.y);

    int weight_Position = filter_number * 64;

    int input_Position = (56 * 32)
                       + (threadIdx.x * 56)
                       + (threadIdx.y);

    for(int channel = 0; channel < 64; channel++)       // This is the channel loop as we have 32 channels to work with
    {
        product += (Layer5_Neurons_GPU[(channel * 56 * 56) + input_Position] * Layer5_Weights_GPU[weight_Position + channel]);
    }

    double Z = (product - Layer5_Mean_GPU[filter_number]) / Layer5_StanDev_GPU[filter_number];
    Z = (Z * Layer5_Gamma_GPU[filter_number]) + Layer5_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer6_Neurons_GPU[output_Position + offset] = Z;
}

__global__ void executeFifthLayer_PSC_partD(double *Layer5_Neurons_GPU,
    double *Layer5_Weights_GPU,
    double *Layer6_Neurons_GPU,
    double *Layer5_Mean_GPU,
    double *Layer5_StanDev_GPU,
    double *Layer5_Gamma_GPU,
    double *Layer5_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;
    int offset = 59;

    // Output position
    int output_Position = (filter_number * 58 * 58)   // channel to work with
                        + (58 * 32)
                        + 32
                        + (threadIdx.x * 58)
                        + (threadIdx.y);

    int weight_Position = filter_number * 64;

    int input_Position = (56 * 32)
                       + (32)
                       + (threadIdx.x * 56)
                       + (threadIdx.y);

    for(int channel = 0; channel < 64; channel++)       // This is the channel loop as we have 32 channels to work with
    {
        product += (Layer5_Neurons_GPU[(channel * 56 * 56) + input_Position] * Layer5_Weights_GPU[weight_Position + channel]);
    }

    double Z = (product - Layer5_Mean_GPU[filter_number]) / Layer5_StanDev_GPU[filter_number];
    Z = (Z * Layer5_Gamma_GPU[filter_number]) + Layer5_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer6_Neurons_GPU[output_Position + offset] = Z;
}
/*  *************************************************** FIFTH LAYER END **************************************************** */

/*  *************************************************** SIXTH LAYER START ************************************************** */
/*
    Layer 6: Depthwise Separable Convolution Layer
    Input: 58 * 58 * 128
    Weight: 3 * 3 * 128 with a Stride of 1
    Output: 56 * 56 * 128
*/
__global__ void executeSixthLayer_DSC_partA(double *Layer6_Neurons_GPU,
    double *Layer6_Weights_GPU,
    double *Layer7_Neurons_GPU,
    double *Layer6_Mean_GPU,
    double *Layer6_StanDev_GPU,
    double *Layer6_Gamma_GPU,
    double *Layer6_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 56 * 56)   // channel to work with
                        + (threadIdx.x * 56)
                        + (threadIdx.y);

    int weight_Position = filter_number * 9;

    int input_Position = (threadIdx.x * 58)
                       + (threadIdx.y);

    for(int row = 0; row < 3; row++)       // This is the Row Loop
    {
        product += ((Layer6_Neurons_GPU[(filter_number * 58 * 58) + input_Position + (row * 58)] * Layer6_Weights_GPU[weight_Position + (row * 3)])
                + (Layer6_Neurons_GPU[(filter_number * 58 * 58) + input_Position + (row * 58) + 1] * Layer6_Weights_GPU[weight_Position + (row * 3) + 1])
                + (Layer6_Neurons_GPU[(filter_number * 58 * 58) + input_Position + (row * 58) + 2] * Layer6_Weights_GPU[weight_Position + (row * 3) + 2]));
    }

    double Z = (product - Layer6_Mean_GPU[filter_number]) / Layer6_StanDev_GPU[filter_number];
    Z = (Z * Layer6_Gamma_GPU[filter_number]) + Layer6_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer7_Neurons_GPU[output_Position] = Z;
}

__global__ void executeSixthLayer_DSC_partB(double *Layer6_Neurons_GPU,
    double *Layer6_Weights_GPU,
    double *Layer7_Neurons_GPU,
    double *Layer6_Mean_GPU,
    double *Layer6_StanDev_GPU,
    double *Layer6_Gamma_GPU,
    double *Layer6_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 56 * 56)   // channel to work with
                        + (threadIdx.x * 56)
                        + (threadIdx.y + 32);

    int weight_Position = filter_number * 9;

    int input_Position = (threadIdx.x * 58)
                       + (threadIdx.y)
                       + (32);

    for(int row = 0; row < 3; row++)       // This is the Row Loop
    {
        product += ((Layer6_Neurons_GPU[(filter_number * 58 * 58) + input_Position + (row * 58)] * Layer6_Weights_GPU[weight_Position + (row * 3)])
                + (Layer6_Neurons_GPU[(filter_number * 58 * 58) + input_Position + (row * 58) + 1] * Layer6_Weights_GPU[weight_Position + (row * 3) + 1])
                + (Layer6_Neurons_GPU[(filter_number * 58 * 58) + input_Position + (row * 58) + 2] * Layer6_Weights_GPU[weight_Position + (row * 3) + 2]));
    }

    double Z = (product - Layer6_Mean_GPU[filter_number]) / Layer6_StanDev_GPU[filter_number];
    Z = (Z * Layer6_Gamma_GPU[filter_number]) + Layer6_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer7_Neurons_GPU[output_Position] = Z;
}

__global__ void executeSixthLayer_DSC_partC(double *Layer6_Neurons_GPU,
    double *Layer6_Weights_GPU,
    double *Layer7_Neurons_GPU,
    double *Layer6_Mean_GPU,
    double *Layer6_StanDev_GPU,
    double *Layer6_Gamma_GPU,
    double *Layer6_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 56 * 56)   // channel to work with
                        + (56 * 32)
                        + (threadIdx.x * 56)
                        + (threadIdx.y);

    int weight_Position = filter_number * 9;

    int input_Position = (58 * 32)
                       + (threadIdx.x * 58)
                       + (threadIdx.y);

    for(int row = 0; row < 3; row++)       // This is the Row Loop
    {
        product += ((Layer6_Neurons_GPU[(filter_number * 58 * 58) + input_Position + (row * 58)] * Layer6_Weights_GPU[weight_Position + (row * 3)])
                + (Layer6_Neurons_GPU[(filter_number * 58 * 58) + input_Position + (row * 58) + 1] * Layer6_Weights_GPU[weight_Position + (row * 3) + 1])
                + (Layer6_Neurons_GPU[(filter_number * 58 * 58) + input_Position + (row * 58) + 2] * Layer6_Weights_GPU[weight_Position + (row * 3) + 2]));
    }

    double Z = (product - Layer6_Mean_GPU[filter_number]) / Layer6_StanDev_GPU[filter_number];
    Z = (Z * Layer6_Gamma_GPU[filter_number]) + Layer6_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer7_Neurons_GPU[output_Position] = Z;
}

__global__ void executeSixthLayer_DSC_partD(double *Layer6_Neurons_GPU,
    double *Layer6_Weights_GPU,
    double *Layer7_Neurons_GPU,
    double *Layer6_Mean_GPU,
    double *Layer6_StanDev_GPU,
    double *Layer6_Gamma_GPU,
    double *Layer6_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 56 * 56)   // channel to work with
                        + (56 * 32)
                        + 32
                        + (threadIdx.x * 56)
                        + (threadIdx.y);

    int weight_Position = filter_number * 9;

    int input_Position = (58 * 32)
                       + (32)
                       + (threadIdx.x * 58)
                       + (threadIdx.y);

    for(int row = 0; row < 3; row++)       // This is the Row Loop
    {
        product += ((Layer6_Neurons_GPU[(filter_number * 58 * 58) + input_Position + (row * 58)] * Layer6_Weights_GPU[weight_Position + (row * 3)])
                + (Layer6_Neurons_GPU[(filter_number * 58 * 58) + input_Position + (row * 58) + 1] * Layer6_Weights_GPU[weight_Position + (row * 3) + 1])
                + (Layer6_Neurons_GPU[(filter_number * 58 * 58) + input_Position + (row * 58) + 2] * Layer6_Weights_GPU[weight_Position + (row * 3) + 2]));
    }

    double Z = (product - Layer6_Mean_GPU[filter_number]) / Layer6_StanDev_GPU[filter_number];
    Z = (Z * Layer6_Gamma_GPU[filter_number]) + Layer6_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer7_Neurons_GPU[output_Position] = Z;
}

/*  *************************************************** SIXTH LAYER END **************************************************** */

/*  *************************************************** SEVENTH LAYER START ************************************************ */
/*
    Layer 7: Pointwise Separable Convolution Layer
    Input: 56 * 56 * 128
    Weight: 1 * 1 * 128 * 128 with a Stride of 1
    Output: 57 * 57 * 128  (Padding for the next layer is handled in this layer itself)
*/
__global__ void executeSeventhLayer_PSC_partA(double *Layer7_Neurons_GPU,
    double *Layer7_Weights_GPU,
    double *Layer8_Neurons_GPU,
    double *Layer7_Mean_GPU,
    double *Layer7_StanDev_GPU,
    double *Layer7_Gamma_GPU,
    double *Layer7_Beta_GPU
)
{
    double product = 0.0;

    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 57 * 57)   // channel to work with
                        + (threadIdx.x * 57)
                        + (threadIdx.y);

    int weight_Position = filter_number * 128;

    int input_Position = (threadIdx.x * 56)
                       + (threadIdx.y);

    for(int channel = 0; channel < 128; channel++)       // This is the channel loop as we have 32 channels to work with
    {
        product += (Layer7_Neurons_GPU[(channel * 56 * 56) + input_Position] * Layer7_Weights_GPU[weight_Position + channel]);
    }

    double Z = (product - Layer7_Mean_GPU[filter_number]) / Layer7_StanDev_GPU[filter_number];
    Z = (Z * Layer7_Gamma_GPU[filter_number]) + Layer7_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer8_Neurons_GPU[output_Position] = Z;
}

__global__ void executeSeventhLayer_PSC_partB(double *Layer7_Neurons_GPU,
    double *Layer7_Weights_GPU,
    double *Layer8_Neurons_GPU,
    double *Layer7_Mean_GPU,
    double *Layer7_StanDev_GPU,
    double *Layer7_Gamma_GPU,
    double *Layer7_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 57 * 57)   // channel to work with
                        + (threadIdx.x * 57)
                        + (threadIdx.y + 32);

    int weight_Position = filter_number * 128;

    int input_Position = (threadIdx.x * 56)
                       + (threadIdx.y)
                       + (32);

    for(int channel = 0; channel < 128 ; channel++)       // This is the channel loop as we have 32 channels to work with
    {
        product += (Layer7_Neurons_GPU[(channel * 56 * 56) + input_Position] * Layer7_Weights_GPU[weight_Position + channel]);
    }

    double Z = (product - Layer7_Mean_GPU[filter_number]) / Layer7_StanDev_GPU[filter_number];
    Z = (Z * Layer7_Gamma_GPU[filter_number]) + Layer7_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer8_Neurons_GPU[output_Position] = Z;
}

__global__ void executeSeventhLayer_PSC_partC(double *Layer7_Neurons_GPU,
    double *Layer7_Weights_GPU,
    double *Layer8_Neurons_GPU,
    double *Layer7_Mean_GPU,
    double *Layer7_StanDev_GPU,
    double *Layer7_Gamma_GPU,
    double *Layer7_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 57 * 57)   // channel to work with
                        + (57 * 32)
                        + (threadIdx.x * 57)
                        + (threadIdx.y);

    int weight_Position = filter_number * 128;

    int input_Position = (56 * 32)
                       + (threadIdx.x * 56)
                       + (threadIdx.y);

    for(int channel = 0; channel < 128 ; channel++)       // This is the channel loop as we have 32 channels to work with
    {
        product += (Layer7_Neurons_GPU[(channel * 56 * 56) + input_Position] * Layer7_Weights_GPU[weight_Position + channel]);
    }

    double Z = (product - Layer7_Mean_GPU[filter_number]) / Layer7_StanDev_GPU[filter_number];
    Z = (Z * Layer7_Gamma_GPU[filter_number]) + Layer7_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer8_Neurons_GPU[output_Position] = Z;
}

__global__ void executeSeventhLayer_PSC_partD(double *Layer7_Neurons_GPU,
    double *Layer7_Weights_GPU,
    double *Layer8_Neurons_GPU,
    double *Layer7_Mean_GPU,
    double *Layer7_StanDev_GPU,
    double *Layer7_Gamma_GPU,
    double *Layer7_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 57 * 57)   // channel to work with
                        + (57 * 32)
                        + 32
                        + (threadIdx.x * 57)
                        + (threadIdx.y);

    int weight_Position = filter_number * 128;

    int input_Position = (56 * 32)
                       + (32)
                       + (threadIdx.x * 56)
                       + (threadIdx.y);

    for(int channel = 0; channel < 128 ; channel++)       // This is the channel loop as we have 32 channels to work with
    {
        product += (Layer7_Neurons_GPU[(channel * 56 * 56) + input_Position] * Layer7_Weights_GPU[weight_Position + channel]);
    }

    double Z = (product - Layer7_Mean_GPU[filter_number]) / Layer7_StanDev_GPU[filter_number];
    Z = (Z * Layer7_Gamma_GPU[filter_number]) + Layer7_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer8_Neurons_GPU[output_Position] = Z;
}

/*  *************************************************** SEVENTH LAYER END **************************************************** */

/*  *************************************************** EIGHTH LAYER START ************************************************** */
/*
    Layer 8: Depthwise Separable Convolution Layer
    Input: 57 * 57 * 128
    Weight: 3 * 3 * 128  with a Stride of 2
    Output: 28 * 28 * 128
*/
__global__ void executeEighthLayer_DSC(double *Layer8_Neurons_GPU,
    double *Layer8_Weights_GPU,
    double *Layer9_Neurons_GPU,
    double *Layer8_Mean_GPU,
    double *Layer8_StanDev_GPU,
    double *Layer8_Gamma_GPU,
    double *Layer8_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;
    int stride = 2;

    // Output position
    int output_Position = (filter_number * 28 * 28)   // channel to work with
                        + (threadIdx.x * 28)
                        + (threadIdx.y);

    int weight_Position = filter_number * 9;

    int input_Position = (threadIdx.x * 57 * stride)
                       + (threadIdx.y * stride);

    for(int row = 0; row < 3; row++)       // This is the Row Loop
    {
        product += ((Layer8_Neurons_GPU[(filter_number * 57 * 57) + input_Position + (row * 57)] * Layer8_Weights_GPU[weight_Position + (row * 3)])
                + (Layer8_Neurons_GPU[(filter_number * 57 * 57) + input_Position + (row * 57) + 1] * Layer8_Weights_GPU[weight_Position + (row * 3) + 1])
                + (Layer8_Neurons_GPU[(filter_number * 57 * 57) + input_Position + (row * 57) + 2] * Layer8_Weights_GPU[weight_Position + (row * 3) + 2]));
    }

    double Z = (product - Layer8_Mean_GPU[filter_number]) / Layer8_StanDev_GPU[filter_number];
    Z = (Z * Layer8_Gamma_GPU[filter_number]) + Layer8_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer9_Neurons_GPU[output_Position] = Z;
}

/*  *************************************************** EIGHTH LAYER END **************************************************** */

/*  *************************************************** NINTH LAYER START ************************************************** */
/*
    Layer 9: Pointwise Separable Convolution Layer
    Input: 28 * 28 * 128
    Weight: 1 * 1 * 128 * 256  with a Stride of 1
    Output: 30 * 30 * 256 (Handling the padding for the next layer)
*/
__global__ void executeNinthLayer_PSC(double *Layer9_Neurons_GPU,
    double *Layer9_Weights_GPU,
    double *Layer10_Neurons_GPU,
    double *Layer9_Mean_GPU,
    double *Layer9_StanDev_GPU,
    double *Layer9_Gamma_GPU,
    double *Layer9_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;
    int offset = 31;

    // Output position
    int output_Position = (filter_number * 30 * 30)   // channel to work with
                        + (threadIdx.x * 30)
                        + (threadIdx.y);

    int weight_Position = filter_number * 128;

    int input_Position = (threadIdx.x * 28)
                        + (threadIdx.y);

    for(int channel = 0; channel < 128; channel++)       // This is the channel loop as we have 32 channels to work with
    {
        product += (Layer9_Neurons_GPU[(channel * 28 * 28) + input_Position] * Layer9_Weights_GPU[weight_Position + channel]);
    }

    double Z = (product - Layer9_Mean_GPU[filter_number]) / Layer9_StanDev_GPU[filter_number];
    Z = (Z * Layer9_Gamma_GPU[filter_number]) + Layer9_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer10_Neurons_GPU[output_Position + offset] = Z;
}

/*  *************************************************** NINTH LAYER END **************************************************** */

/*  *************************************************** TENTH LAYER START ************************************************** */
/*
    Layer 10: Depthwise Separable Convolution Layer
    Input: 30 * 30 * 256
    Weight: 3 * 3 * 256  with a Stride of 1
    Output: 28 * 28 * 256
*/
__global__ void executeTenthLayer_DSC(double *Layer10_Neurons_GPU,
    double *Layer10_Weights_GPU,
    double *Layer11_Neurons_GPU,
    double *Layer10_Mean_GPU,
    double *Layer10_StanDev_GPU,
    double *Layer10_Gamma_GPU,
    double *Layer10_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 28 * 28)   // channel to work with
                        + (threadIdx.x * 28)
                        + (threadIdx.y);

    int weight_Position = filter_number * 9;

    int input_Position = (threadIdx.x * 30)
                       + (threadIdx.y);

    for(int row = 0; row < 3; row++)       // This is the Row Loop
    {
        product += ((Layer10_Neurons_GPU[(filter_number * 30 * 30) + input_Position + (row * 30)] * Layer10_Weights_GPU[weight_Position + (row * 3)])
                + (Layer10_Neurons_GPU[(filter_number * 30 * 30) + input_Position + (row * 30) + 1] * Layer10_Weights_GPU[weight_Position + (row * 3) + 1])
                + (Layer10_Neurons_GPU[(filter_number * 30 * 30) + input_Position + (row * 30) + 2] * Layer10_Weights_GPU[weight_Position + (row * 3) + 2]));
    }

    double Z = (product - Layer10_Mean_GPU[filter_number]) / Layer10_StanDev_GPU[filter_number];
    Z = (Z * Layer10_Gamma_GPU[filter_number]) + Layer10_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer11_Neurons_GPU[output_Position] = Z;
}

/*  *************************************************** TENTH LAYER END **************************************************** */

/*  *************************************************** ELEVENTH LAYER START ************************************************** */
/*
    Layer 11: Pointwise Separable Convolution Layer
    Input: 28 * 28 * 256
    Weight: 1 * 1 * 256 * 256  with a Stride of 1
    Output: 29 * 29 * 256  (Padding for the next layer is handled in this layer itself)
*/
__global__ void executeEleventhLayer_PSC(double *Layer11_Neurons_GPU,
    double *Layer11_Weights_GPU,
    double *Layer12_Neurons_GPU,
    double *Layer11_Mean_GPU,
    double *Layer11_StanDev_GPU,
    double *Layer11_Gamma_GPU,
    double *Layer11_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 29 * 29)   // channel to work with
                        + (threadIdx.x * 29)
                        + (threadIdx.y);

    int weight_Position = filter_number * 256;

    int input_Position = (threadIdx.x * 28)
                        + (threadIdx.y);

    for(int channel = 0; channel < 256; channel++)       // This is the channel loop as we have 32 channels to work with
    {
        product += (Layer11_Neurons_GPU[(channel * 28 * 28) + input_Position] * Layer11_Weights_GPU[weight_Position + channel]);
    }

    double Z = (product - Layer11_Mean_GPU[filter_number]) / Layer11_StanDev_GPU[filter_number];
    Z = (Z * Layer11_Gamma_GPU[filter_number]) + Layer11_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer12_Neurons_GPU[output_Position] = Z;
}

/*  *************************************************** ELEVENTH LAYER END **************************************************** */

/*  *************************************************** TWELFTH LAYER START ************************************************** */
/*
    Layer 12: Depthwise Separable Convolution Layer
    Input: 29 * 29 * 256
    Weight: 3 * 3 * 256 with a Stride of 2
    Output: 14 * 14 * 256
*/
__global__ void executeTwelfthLayer_DSC(double *Layer12_Neurons_GPU,
    double *Layer12_Weights_GPU,
    double *Layer13_Neurons_GPU,
    double *Layer12_Mean_GPU,
    double *Layer12_StanDev_GPU,
    double *Layer12_Gamma_GPU,
    double *Layer12_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;
    int stride = 2;

    // Output position
    int output_Position = (filter_number * 14 * 14)   // channel to work with
                        + (threadIdx.x * 14)
                        + (threadIdx.y);

    int weight_Position = filter_number * 9;

    int input_Position = (threadIdx.x * 29 * stride)
                       + (threadIdx.y * stride);

    for(int row = 0; row < 3; row++)       // This is the Row Loop
    {
        product += ((Layer12_Neurons_GPU[(filter_number * 29 * 29) + input_Position + (row * 29)] * Layer12_Weights_GPU[weight_Position + (row * 3)])
                + (Layer12_Neurons_GPU[(filter_number * 29 * 29) + input_Position + (row * 29) + 1] * Layer12_Weights_GPU[weight_Position + (row * 3) + 1])
                + (Layer12_Neurons_GPU[(filter_number * 29 * 29) + input_Position + (row * 29) + 2] * Layer12_Weights_GPU[weight_Position + (row * 3) + 2]));
    }

    double Z = (product - Layer12_Mean_GPU[filter_number]) / Layer12_StanDev_GPU[filter_number];
    Z = (Z * Layer12_Gamma_GPU[filter_number]) + Layer12_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer13_Neurons_GPU[output_Position] = Z;
}

/*  *************************************************** TWELFTH LAYER END **************************************************** */

/*  *************************************************** THIRTEENTH LAYER START ************************************************** */
/*
    Layer 13: Pointwise Separable Convolution Layer
    Input: 14 * 14 * 256
    Weight: 1 * 1 * 256 * 512 with a Stride of 1
    Output: 16 * 16 * 512  (Handling padding for next layer)
*/
__global__ void executeThirteenthLayer_PSC(double *Layer13_Neurons_GPU,
    double *Layer13_Weights_GPU,
    double *Layer14_Neurons_GPU,
    double *Layer13_Mean_GPU,
    double *Layer13_StanDev_GPU,
    double *Layer13_Gamma_GPU,
    double *Layer13_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;
    int offset = 17;

    // Output position
    int output_Position = (filter_number * 16 * 16)   // channel to work with
                        + (threadIdx.x * 16)
                        + (threadIdx.y);

    int weight_Position = filter_number * 256;

    int input_Position = (threadIdx.x * 14)
                        + (threadIdx.y);

    for(int channel = 0; channel < 256; channel++)       // This is the channel loop as we have 32 channels to work with
    {
        product += (Layer13_Neurons_GPU[(channel * 14 * 14) + input_Position] * Layer13_Weights_GPU[weight_Position + channel]);
    }

    double Z = (product - Layer13_Mean_GPU[filter_number]) / Layer13_StanDev_GPU[filter_number];
    Z = (Z * Layer13_Gamma_GPU[filter_number]) + Layer13_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer14_Neurons_GPU[output_Position + offset] = Z;
}

/*  *************************************************** THIRTEENTH LAYER END **************************************************** */

/*  *************************************************** FOURTEENTH LAYER START ************************************************** */
/*
    Layer 14: Depthwise Separable Convolution Layer
    Input: 16 * 16 * 512
    Weight: 3 * 3 * 512 with a Stride of 1
    Output: 14 * 14 * 512  (Handling padding for next layer)
*/
__global__ void executeFourteenthLayer_DSC(double *Layer14_Neurons_GPU,
    double *Layer14_Weights_GPU,
    double *Layer15_Neurons_GPU,
    double *Layer14_Mean_GPU,
    double *Layer14_StanDev_GPU,
    double *Layer14_Gamma_GPU,
    double *Layer14_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 14 * 14)   // channel to work with
                        + (threadIdx.x * 14)
                        + (threadIdx.y);

    int weight_Position = filter_number * 9;

    int input_Position = (threadIdx.x * 16)
                       + (threadIdx.y);

    for(int row = 0; row < 3; row++)       // This is the Row Loop
    {
        product += ((Layer14_Neurons_GPU[(filter_number * 16 * 16) + input_Position + (row * 16)] * Layer14_Weights_GPU[weight_Position + (row * 3)])
                + (Layer14_Neurons_GPU[(filter_number * 16 * 16) + input_Position + (row * 16) + 1] * Layer14_Weights_GPU[weight_Position + (row * 3) + 1])
                + (Layer14_Neurons_GPU[(filter_number * 16 * 16) + input_Position + (row * 16) + 2] * Layer14_Weights_GPU[weight_Position + (row * 3) + 2]));
    }

    double Z = (product - Layer14_Mean_GPU[filter_number]) / Layer14_StanDev_GPU[filter_number];
    Z = (Z * Layer14_Gamma_GPU[filter_number]) + Layer14_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer15_Neurons_GPU[output_Position] = Z;
}

/*  *************************************************** FOURTEENTH LAYER END **************************************************** */

/*  *************************************************** FIFTEENTH LAYER START ************************************************** */
/*
    Layer 15: Pointwise Separable Convolution Layer
    Input: 14 * 14 * 512
    Weight: 1 * 1 * 512 * 512 with a Stride of 1
    Output: 16 * 16 * 512  (Handling padding for next layer)
*/
__global__ void executeFifteenthLayer_PSC(double *Layer15_Neurons_GPU,
    double *Layer15_Weights_GPU,
    double *Layer16_Neurons_GPU,
    double *Layer15_Mean_GPU,
    double *Layer15_StanDev_GPU,
    double *Layer15_Gamma_GPU,
    double *Layer15_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;
    int offset = 17;

    // Output position
    int output_Position = (filter_number * 16 * 16)   // channel to work with
                        + (threadIdx.x * 16)
                        + (threadIdx.y);

    int weight_Position = filter_number * 512;

    int input_Position = (threadIdx.x * 14)
                        + (threadIdx.y);

    for(int channel = 0; channel < 512 ; channel++)       // This is the channel loop as we have 32 channels to work with
    {
        product += (Layer15_Neurons_GPU[(channel * 14 * 14) + input_Position] * Layer15_Weights_GPU[weight_Position + channel]);
    }

    double Z = (product - Layer15_Mean_GPU[filter_number]) / Layer15_StanDev_GPU[filter_number];
    Z = (Z * Layer15_Gamma_GPU[filter_number]) + Layer15_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer16_Neurons_GPU[output_Position + offset] = Z;
}

/*  *************************************************** FIFTEENTH LAYER END **************************************************** */

/*  *************************************************** SIXTEENTH LAYER START ************************************************** */
/*
    Layer 16: Depthwise Separable Convolution Layer
    Input: 16 * 16 * 512
    Weight: 3 * 3 * 512 with a Stride of 1
    Output: 14 * 14 * 512  (Handling padding for next layer)
*/
__global__ void executeSixteenthLayer_DSC(double *Layer16_Neurons_GPU,
    double *Layer16_Weights_GPU,
    double *Layer17_Neurons_GPU,
    double *Layer16_Mean_GPU,
    double *Layer16_StanDev_GPU,
    double *Layer16_Gamma_GPU,
    double *Layer16_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 14 * 14)   // channel to work with
                        + (threadIdx.x * 14)
                        + (threadIdx.y);

    int weight_Position = filter_number * 9;

    int input_Position = (threadIdx.x * 16)
                       + (threadIdx.y);

    for(int row = 0; row < 3; row++)       // This is the Row Loop
    {
        product += ((Layer16_Neurons_GPU[(filter_number * 16 * 16) + input_Position + (row * 16)] * Layer16_Weights_GPU[weight_Position + (row * 3)])
                + (Layer16_Neurons_GPU[(filter_number * 16 * 16) + input_Position + (row * 16) + 1] * Layer16_Weights_GPU[weight_Position + (row * 3) + 1])
                + (Layer16_Neurons_GPU[(filter_number * 16 * 16) + input_Position + (row * 16) + 2] * Layer16_Weights_GPU[weight_Position + (row * 3) + 2]));
    }

    double Z = (product - Layer16_Mean_GPU[filter_number]) / Layer16_StanDev_GPU[filter_number];
    Z = (Z * Layer16_Gamma_GPU[filter_number]) + Layer16_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer17_Neurons_GPU[output_Position] = Z;
}

/*  *************************************************** SIXTEENTH LAYER END **************************************************** */

/*  *************************************************** SEVENTEENTH LAYER START ************************************************** */
/*
    Layer 17: Pointwise Separable Convolution Layer
    Input: 14 * 14 * 512
    Weight: 1 * 1 * 512 * 512 with a Stride of 1
    Output: 16 * 16 * 512  (Handling padding for next layer)
*/
__global__ void executeSeventeenthLayer_PSC(double *Layer17_Neurons_GPU,
    double *Layer17_Weights_GPU,
    double *Layer18_Neurons_GPU,
    double *Layer17_Mean_GPU,
    double *Layer17_StanDev_GPU,
    double *Layer17_Gamma_GPU,
    double *Layer17_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;
    int offset = 17;

    // Output position
    int output_Position = (filter_number * 16 * 16)   // channel to work with
                        + (threadIdx.x * 16)
                        + (threadIdx.y);

    int weight_Position = filter_number * 512;

    int input_Position = (threadIdx.x * 14)
                        + (threadIdx.y);

    for(int channel = 0; channel < 512 ; channel++)       // This is the channel loop as we have 32 channels to work with
    {
        product += (Layer17_Neurons_GPU[(channel * 14 * 14) + input_Position] * Layer17_Weights_GPU[weight_Position + channel]);
    }

    double Z = (product - Layer17_Mean_GPU[filter_number]) / Layer17_StanDev_GPU[filter_number];
    Z = (Z * Layer17_Gamma_GPU[filter_number]) + Layer17_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer18_Neurons_GPU[output_Position + offset] = Z;
}

/*  *************************************************** SEVENTEENTH LAYER END **************************************************** */

/*  *************************************************** EIGHTEENTH LAYER START ************************************************** */
/*
    Layer 18: Depthwise Separable Convolution Layer
    Input: 16 * 16 * 512
    Weight: 3 * 3 * 512 with a Stride of 1
    Output: 14 * 14 * 512
*/
__global__ void executeEighteenthLayer_DSC(double *Layer18_Neurons_GPU,
    double *Layer18_Weights_GPU,
    double *Layer19_Neurons_GPU,
    double *Layer18_Mean_GPU,
    double *Layer18_StanDev_GPU,
    double *Layer18_Gamma_GPU,
    double *Layer18_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 14 * 14)   // channel to work with
                        + (threadIdx.x * 14)
                        + (threadIdx.y);

    int weight_Position = filter_number * 9;

    int input_Position = (threadIdx.x * 16)
                       + (threadIdx.y);

    for(int row = 0; row < 3; row++)       // This is the Row Loop
    {
        product += ((Layer18_Neurons_GPU[(filter_number * 16 * 16) + input_Position + (row * 16)] * Layer18_Weights_GPU[weight_Position + (row * 3)])
                + (Layer18_Neurons_GPU[(filter_number * 16 * 16) + input_Position + (row * 16) + 1] * Layer18_Weights_GPU[weight_Position + (row * 3) + 1])
                + (Layer18_Neurons_GPU[(filter_number * 16 * 16) + input_Position + (row * 16) + 2] * Layer18_Weights_GPU[weight_Position + (row * 3) + 2]));
    }

    double Z = (product - Layer18_Mean_GPU[filter_number]) / Layer18_StanDev_GPU[filter_number];
    Z = (Z * Layer18_Gamma_GPU[filter_number]) + Layer18_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer19_Neurons_GPU[output_Position] = Z;
}

/*  *************************************************** EIGHTEENTH LAYER END **************************************************** */

/*  *************************************************** NINETEENTH LAYER START ************************************************** */
/*
    Layer 19: Pointwise Separable Convolution Layer
    Input: 14 * 14 * 512
    Weight: 1 * 1 * 512 * 512 with a Stride of 1
    Output: 16 * 16 * 512  (Handling padding for next layer)
*/
__global__ void executeNineteenthLayer_PSC(double *Layer19_Neurons_GPU,
    double *Layer19_Weights_GPU,
    double *Layer20_Neurons_GPU,
    double *Layer19_Mean_GPU,
    double *Layer19_StanDev_GPU,
    double *Layer19_Gamma_GPU,
    double *Layer19_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;
    int offset = 17;

    // Output position
    int output_Position = (filter_number * 16 * 16)   // channel to work with
                        + (threadIdx.x * 16)
                        + (threadIdx.y);

    int weight_Position = filter_number * 512;

    int input_Position = (threadIdx.x * 14)
                        + (threadIdx.y);

    for(int channel = 0; channel < 512 ; channel++)       // This is the channel loop as we have 32 channels to work with
    {
        product += (Layer19_Neurons_GPU[(channel * 14 * 14) + input_Position] * Layer19_Weights_GPU[weight_Position + channel]);
    }

    double Z = (product - Layer19_Mean_GPU[filter_number]) / Layer19_StanDev_GPU[filter_number];
    Z = (Z * Layer19_Gamma_GPU[filter_number]) + Layer19_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer20_Neurons_GPU[output_Position + offset] = Z;
}

/*  *************************************************** NINETEENTH LAYER END **************************************************** */

/*  *************************************************** TWENTY LAYER START ************************************************** */
/*
    Layer 20: Depthwise Separable Convolution Layer
    Input: 16 * 16 * 512
    Weight: 3 * 3 * 512 with a Stride of 1
    Output: 14 * 14 * 512
*/
__global__ void executeTwentyLayer_DSC(double *Layer20_Neurons_GPU,
    double *Layer20_Weights_GPU,
    double *Layer21_Neurons_GPU,
    double *Layer20_Mean_GPU,
    double *Layer20_StanDev_GPU,
    double *Layer20_Gamma_GPU,
    double *Layer20_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 14 * 14)   // channel to work with
                        + (threadIdx.x * 14)
                        + (threadIdx.y);

    int weight_Position = filter_number * 9;

    int input_Position = (threadIdx.x * 16)
                       + (threadIdx.y);

    for(int row = 0; row < 3; row++)       // This is the Row Loop
    {
        product += ((Layer20_Neurons_GPU[(filter_number * 16 * 16) + input_Position + (row * 16)] * Layer20_Weights_GPU[weight_Position + (row * 3)])
                + (Layer20_Neurons_GPU[(filter_number * 16 * 16) + input_Position + (row * 16) + 1] * Layer20_Weights_GPU[weight_Position + (row * 3) + 1])
                + (Layer20_Neurons_GPU[(filter_number * 16 * 16) + input_Position + (row * 16) + 2] * Layer20_Weights_GPU[weight_Position + (row * 3) + 2]));
    }

    double Z = (product - Layer20_Mean_GPU[filter_number]) / Layer20_StanDev_GPU[filter_number];
    Z = (Z * Layer20_Gamma_GPU[filter_number]) + Layer20_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer21_Neurons_GPU[output_Position] = Z;
}
/*  *************************************************** TWENTY LAYER END **************************************************** */

/*  *************************************************** TWENTYONE LAYER START ************************************************** */
/*
    Layer 21: Pointwise Separable Convolution Layer
    Input: 14 * 14 * 512
    Weight: 1 * 1 * 512 * 512 with a Stride of 1
    Output: 16 * 16 * 512  (Handling padding for next layer)
*/
__global__ void executeTwentyOneLayer_PSC(double *Layer21_Neurons_GPU,
    double *Layer21_Weights_GPU,
    double *Layer22_Neurons_GPU,
    double *Layer21_Mean_GPU,
    double *Layer21_StanDev_GPU,
    double *Layer21_Gamma_GPU,
    double *Layer21_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;
    int offset = 17;

    // Output position
    int output_Position = (filter_number * 16 * 16)   // channel to work with
                        + (threadIdx.x * 16)
                        + (threadIdx.y);

    int weight_Position = filter_number * 512;

    int input_Position = (threadIdx.x * 14)
                        + (threadIdx.y);

    for(int channel = 0; channel < 512 ; channel++)       // This is the channel loop as we have 32 channels to work with
    {
        product += (Layer21_Neurons_GPU[(channel * 14 * 14) + input_Position] * Layer21_Weights_GPU[weight_Position + channel]);
    }

    double Z = (product - Layer21_Mean_GPU[filter_number]) / Layer21_StanDev_GPU[filter_number];
    Z = (Z * Layer21_Gamma_GPU[filter_number]) + Layer21_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer22_Neurons_GPU[output_Position + offset] = Z;
}

/*  *************************************************** TWENTYONE LAYER END **************************************************** */

/*  *************************************************** TWENTYTWO LAYER START ************************************************** */
/*
    Layer 22: Depthwise Separable Convolution Layer
    Input: 16 * 16 * 512
    Weight: 3 * 3 * 512 with a Stride of 1
    Output: 14 * 14 * 512
*/
__global__ void executeTwentyTwoLayer_DSC(double *Layer22_Neurons_GPU,
    double *Layer22_Weights_GPU,
    double *Layer23_Neurons_GPU,
    double *Layer22_Mean_GPU,
    double *Layer22_StanDev_GPU,
    double *Layer22_Gamma_GPU,
    double *Layer22_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 14 * 14)   // channel to work with
                        + (threadIdx.x * 14)
                        + (threadIdx.y);

    int weight_Position = filter_number * 9;

    int input_Position = (threadIdx.x * 16)
                       + (threadIdx.y);

    for(int row = 0; row < 3; row++)       // This is the Row Loop
    {
        product += ((Layer22_Neurons_GPU[(filter_number * 16 * 16) + input_Position + (row * 16)] * Layer22_Weights_GPU[weight_Position + (row * 3)])
                + (Layer22_Neurons_GPU[(filter_number * 16 * 16) + input_Position + (row * 16) + 1] * Layer22_Weights_GPU[weight_Position + (row * 3) + 1])
                + (Layer22_Neurons_GPU[(filter_number * 16 * 16) + input_Position + (row * 16) + 2] * Layer22_Weights_GPU[weight_Position + (row * 3) + 2]));
    }

    double Z = (product - Layer22_Mean_GPU[filter_number]) / Layer22_StanDev_GPU[filter_number];
    Z = (Z * Layer22_Gamma_GPU[filter_number]) + Layer22_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer23_Neurons_GPU[output_Position] = Z;
}
/*  *************************************************** TWENTYTWO LAYER END **************************************************** */

/*  *************************************************** TWENTYTHREE LAYER START ************************************************** */
/*
    Layer 23: Pointwise Separable Convolution Layer
    Input: 14 * 14 * 512
    Weight: 1 * 1 * 512 * 512 with a Stride of 1
    Output: 14 * 14 * 512  (Handling padding for next layer)
*/
__global__ void executeTwentyThreeLayer_PSC(double *Layer23_Neurons_GPU,
    double *Layer23_Weights_GPU,
    double *Layer24_Neurons_GPU,
    double *Layer23_Mean_GPU,
    double *Layer23_StanDev_GPU,
    double *Layer23_Gamma_GPU,
    double *Layer23_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 15 * 15)   // channel to work with
                        + (threadIdx.x * 15)
                        + (threadIdx.y);

    int weight_Position = filter_number * 512;

    int input_Position = (threadIdx.x * 14)
                        + (threadIdx.y);

    for(int channel = 0; channel < 512 ; channel++)       // This is the channel loop as we have 32 channels to work with
    {
        product += (Layer23_Neurons_GPU[(channel * 14 * 14) + input_Position] * Layer23_Weights_GPU[weight_Position + channel]);
    }

    double Z = (product - Layer23_Mean_GPU[filter_number]) / Layer23_StanDev_GPU[filter_number];
    Z = (Z * Layer23_Gamma_GPU[filter_number]) + Layer23_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer24_Neurons_GPU[output_Position] = Z;
}
/*  *************************************************** TWENTYTHREE LAYER END **************************************************** */

/*  *************************************************** TWENTYFOUR LAYER START ************************************************** */
/*
    Layer 24: Depthwise Separable Convolution Layer
    Input: 15 * 15 * 512
    Weight: 3 * 3 * 512 with a Stride of 2
    Output: 14 * 14 * 512  (Handling padding for next layer)
*/
__global__ void executeTwentyFourLayer_DSC(double *Layer24_Neurons_GPU,
    double *Layer24_Weights_GPU,
    double *Layer25_Neurons_GPU,
    double *Layer24_Mean_GPU,
    double *Layer24_StanDev_GPU,
    double *Layer24_Gamma_GPU,
    double *Layer24_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;
    int stride = 2;

    // Output position
    int output_Position = (filter_number * 7 * 7)   // channel to work with
                        + (threadIdx.x * 7)
                        + (threadIdx.y);

    int weight_Position = filter_number * 9;

    int input_Position = (threadIdx.x * 15 * stride)
                       + (threadIdx.y * stride);

    for(int row = 0; row < 3; row++)       // This is the Row Loop
    {
        product += ((Layer24_Neurons_GPU[(filter_number * 15 * 15) + input_Position + (row * 15)] * Layer24_Weights_GPU[weight_Position + (row * 3)])
                + (Layer24_Neurons_GPU[(filter_number * 15 * 15) + input_Position + (row * 15) + 1] * Layer24_Weights_GPU[weight_Position + (row * 3) + 1])
                + (Layer24_Neurons_GPU[(filter_number * 15 * 15) + input_Position + (row * 15) + 2] * Layer24_Weights_GPU[weight_Position + (row * 3) + 2]));
    }

    double Z = (product - Layer24_Mean_GPU[filter_number]) / Layer24_StanDev_GPU[filter_number];
    Z = (Z * Layer24_Gamma_GPU[filter_number]) + Layer24_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer25_Neurons_GPU[output_Position] = Z;
}
/*  *************************************************** TWENTYFOUR LAYER END **************************************************** */

/*  *************************************************** TWENTYFIVE LAYER START ************************************************** */
/*
    Layer 25: Pointwise Separable Convolution Layer
    Input: 7 * 7 * 512
    Weight: 1 * 1 * 512 * 1024 with a Stride of 1
    Output: 9 * 9 * 1024 (Handling padding for next layer)
*/
__global__ void executeTwentyFiveLayer_PSC(double *Layer25_Neurons_GPU,
    double *Layer25_Weights_GPU,
    double *Layer26_Neurons_GPU,
    double *Layer25_Mean_GPU,
    double *Layer25_StanDev_GPU,
    double *Layer25_Gamma_GPU,
    double *Layer25_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;
    int offset = 10;

    // Output position
    int output_Position = (filter_number * 9 * 9)   // channel to work with
                        + (threadIdx.x * 9)
                        + (threadIdx.y);

    int weight_Position = filter_number * 512;

    int input_Position = (threadIdx.x * 7)
                        + (threadIdx.y);

    for(int channel = 0; channel < 512 ; channel++)
    {
        product += (Layer25_Neurons_GPU[(channel * 7 * 7) + input_Position] * Layer25_Weights_GPU[weight_Position + channel]);
    }

    double Z = (product - Layer25_Mean_GPU[filter_number]) / Layer25_StanDev_GPU[filter_number];
    Z = (Z * Layer25_Gamma_GPU[filter_number]) + Layer25_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer26_Neurons_GPU[output_Position + offset] = Z;
}
/*  *************************************************** TWENTYFIVE LAYER END **************************************************** */

/*  *************************************************** TWENTYSIX LAYER START ************************************************** */
/*
    Layer 26: Depthwise Separable Convolution Layer
    Input: 9 * 9 * 1024
    Weight: 3 * 3 * 1024 with a Stride of 1
    Output: 7 * 7 * 1024  (Handling padding for next layer)
*/
__global__ void executeTwentySixLayer_DSC(double *Layer26_Neurons_GPU,
    double *Layer26_Weights_GPU,
    double *Layer27_Neurons_GPU,
    double *Layer26_Mean_GPU,
    double *Layer26_StanDev_GPU,
    double *Layer26_Gamma_GPU,
    double *Layer26_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 7 * 7)   // channel to work with
                        + (threadIdx.x * 7)
                        + (threadIdx.y);

    int weight_Position = filter_number * 9;

    int input_Position = (threadIdx.x * 9)
                       + (threadIdx.y);

    for(int row = 0; row < 3; row++)       // This is the Row Loop
    {
        product += ((Layer26_Neurons_GPU[(filter_number * 9 * 9) + input_Position + (row * 9)] * Layer26_Weights_GPU[weight_Position + (row * 3)])
                + (Layer26_Neurons_GPU[(filter_number * 9 * 9) + input_Position + (row * 9) + 1] * Layer26_Weights_GPU[weight_Position + (row * 3) + 1])
                + (Layer26_Neurons_GPU[(filter_number * 9 * 9) + input_Position + (row * 9) + 2] * Layer26_Weights_GPU[weight_Position + (row * 3) + 2]));
    }

    double Z = (product - Layer26_Mean_GPU[filter_number]) / Layer26_StanDev_GPU[filter_number];
    Z = (Z * Layer26_Gamma_GPU[filter_number]) + Layer26_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer27_Neurons_GPU[output_Position] = Z;
}
/*  *************************************************** TWENTYSIX LAYER END **************************************************** */

/*  *************************************************** TWENTYSEVEN LAYER START ************************************************** */
/*
    Layer 27: Pointwise Separable Convolution Layer
    Input: 7 * 7 * 1024
    Weight: 1 * 1 * 1024 * 1024 with a Stride of 1
    Output: 7 * 7 * 1024
*/
__global__ void executeTwentySevenLayer_PSC(double *Layer27_Neurons_GPU,
    double *Layer27_Weights_GPU,
    double *Layer28_Neurons_GPU,
    double *Layer27_Mean_GPU,
    double *Layer27_StanDev_GPU,
    double *Layer27_Gamma_GPU,
    double *Layer27_Beta_GPU
)
{
    double product = 0.0;
    int filter_number = blockIdx.x;

    // Output position
    int output_Position = (filter_number * 7 * 7)   // channel to work with
                        + (threadIdx.x * 7)
                        + (threadIdx.y);

    int weight_Position = filter_number * 1024;

    int input_Position = (threadIdx.x * 7)
                        + (threadIdx.y);

    for(int channel = 0; channel < 1024 ; channel++)
    {
        product += (Layer27_Neurons_GPU[(channel * 7 * 7) + input_Position] * Layer27_Weights_GPU[weight_Position + channel]);
    }

    double Z = (product - Layer27_Mean_GPU[filter_number]) / Layer27_StanDev_GPU[filter_number];
    Z = (Z * Layer27_Gamma_GPU[filter_number]) + Layer27_Beta_GPU[filter_number];

    // ReLU Layer
    if(Z < 0)
        Z = 0; // max(0,x)

    // ReLU 6 Layer
    if(Z > 6)
        Z = 6.0;

    Layer28_Neurons_GPU[output_Position] = Z;
}
/*  *************************************************** TWENTYSEVEN LAYER END **************************************************** */

/*  *************************************************** TWENTYEIGHT LAYER START ************************************************** */
/*
    Layer 28: Global Average Pooling Layer
    Input: 7 * 7 * 1024
    Weight: None
    Output: 1 * 1 * 1024
*/
__global__ void executeTwentyEightLayer_AvgPooling(double *Layer28_Neurons_GPU,
    double *Layer29_Neurons_GPU
)
{
    double sum = 0.0;
    int filter_number = threadIdx.x * 32 + threadIdx.y;

    // Output position
    int output_Position = filter_number;

    int input_Position_start = filter_number * 49;
    for(int row = 0 ; row < 7 ; row++)
        for(int col = 0 ; col < 7 ; col++)
            sum += Layer28_Neurons_GPU[input_Position_start + row * 7 + col];

    sum = sum / 49;
    Layer29_Neurons_GPU[output_Position] = sum;
}
/*  *************************************************** TWENTYEIGHT LAYER END **************************************************** */

/*  *************************************************** TWENTYNINE LAYER START ************************************************** */
/*
    Layer 29: Fully Connected Layer
    Input: 1 * 1 * 1024
    Weight: 1000 * 1024
    Bias: 1000
    Output: 1000
*/
__global__ void executeTwentyNineLayer_FullyConnected(double *Layer29_Neurons_GPU,
    double *Layer30_Neurons_GPU,
    double *Layer29_Weights_GPU,
    double *Layer29_Bias_GPU
)
{
    double product = 0.0;
    int filter_number = threadIdx.x;

    // Output position
    int output_Position = filter_number;

    int weight_Position = filter_number * 1024;

    for(int channel = 0; channel < 1024 ; channel++)
    {
        product += (Layer29_Neurons_GPU[channel] * Layer29_Weights_GPU[weight_Position + channel]);
    }

    //Adding Bias to the output
    product += Layer29_Bias_GPU[filter_number];

    Layer30_Neurons_GPU[output_Position] = product;
}
/*  *************************************************** TWENTYNINE LAYER END **************************************************** */

	.text
	.file	"MobileNets_kernel.hip"
	.globl	_Z45__device_stub__executeFirstLayer_CONV3D_partAPdS_S_S_S_S_S_ # -- Begin function _Z45__device_stub__executeFirstLayer_CONV3D_partAPdS_S_S_S_S_S_
	.type	_Z45__device_stub__executeFirstLayer_CONV3D_partAPdS_S_S_S_S_S_,@function
_Z45__device_stub__executeFirstLayer_CONV3D_partAPdS_S_S_S_S_S_: # @_Z45__device_stub__executeFirstLayer_CONV3D_partAPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z30executeFirstLayer_CONV3D_partAPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z45__device_stub__executeFirstLayer_CONV3D_partAPdS_S_S_S_S_S_, .Lfunc_end0-_Z45__device_stub__executeFirstLayer_CONV3D_partAPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z45__device_stub__executeFirstLayer_CONV3D_partBPdS_S_S_S_S_S_ # -- Begin function _Z45__device_stub__executeFirstLayer_CONV3D_partBPdS_S_S_S_S_S_
	.type	_Z45__device_stub__executeFirstLayer_CONV3D_partBPdS_S_S_S_S_S_,@function
_Z45__device_stub__executeFirstLayer_CONV3D_partBPdS_S_S_S_S_S_: # @_Z45__device_stub__executeFirstLayer_CONV3D_partBPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z30executeFirstLayer_CONV3D_partBPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z45__device_stub__executeFirstLayer_CONV3D_partBPdS_S_S_S_S_S_, .Lfunc_end1-_Z45__device_stub__executeFirstLayer_CONV3D_partBPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z45__device_stub__executeFirstLayer_CONV3D_partCPdS_S_S_S_S_S_ # -- Begin function _Z45__device_stub__executeFirstLayer_CONV3D_partCPdS_S_S_S_S_S_
	.type	_Z45__device_stub__executeFirstLayer_CONV3D_partCPdS_S_S_S_S_S_,@function
_Z45__device_stub__executeFirstLayer_CONV3D_partCPdS_S_S_S_S_S_: # @_Z45__device_stub__executeFirstLayer_CONV3D_partCPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z30executeFirstLayer_CONV3D_partCPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z45__device_stub__executeFirstLayer_CONV3D_partCPdS_S_S_S_S_S_, .Lfunc_end2-_Z45__device_stub__executeFirstLayer_CONV3D_partCPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z43__device_stub__executeSecondLayer_DSC_partAPdS_S_S_S_S_S_ # -- Begin function _Z43__device_stub__executeSecondLayer_DSC_partAPdS_S_S_S_S_S_
	.type	_Z43__device_stub__executeSecondLayer_DSC_partAPdS_S_S_S_S_S_,@function
_Z43__device_stub__executeSecondLayer_DSC_partAPdS_S_S_S_S_S_: # @_Z43__device_stub__executeSecondLayer_DSC_partAPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z28executeSecondLayer_DSC_partAPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z43__device_stub__executeSecondLayer_DSC_partAPdS_S_S_S_S_S_, .Lfunc_end3-_Z43__device_stub__executeSecondLayer_DSC_partAPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z43__device_stub__executeSecondLayer_DSC_partBPdS_S_S_S_S_S_ # -- Begin function _Z43__device_stub__executeSecondLayer_DSC_partBPdS_S_S_S_S_S_
	.type	_Z43__device_stub__executeSecondLayer_DSC_partBPdS_S_S_S_S_S_,@function
_Z43__device_stub__executeSecondLayer_DSC_partBPdS_S_S_S_S_S_: # @_Z43__device_stub__executeSecondLayer_DSC_partBPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z28executeSecondLayer_DSC_partBPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z43__device_stub__executeSecondLayer_DSC_partBPdS_S_S_S_S_S_, .Lfunc_end4-_Z43__device_stub__executeSecondLayer_DSC_partBPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z43__device_stub__executeSecondLayer_DSC_partCPdS_S_S_S_S_S_ # -- Begin function _Z43__device_stub__executeSecondLayer_DSC_partCPdS_S_S_S_S_S_
	.type	_Z43__device_stub__executeSecondLayer_DSC_partCPdS_S_S_S_S_S_,@function
_Z43__device_stub__executeSecondLayer_DSC_partCPdS_S_S_S_S_S_: # @_Z43__device_stub__executeSecondLayer_DSC_partCPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z28executeSecondLayer_DSC_partCPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z43__device_stub__executeSecondLayer_DSC_partCPdS_S_S_S_S_S_, .Lfunc_end5-_Z43__device_stub__executeSecondLayer_DSC_partCPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z42__device_stub__executeThirdLayer_PSC_partAPdS_S_S_S_S_S_ # -- Begin function _Z42__device_stub__executeThirdLayer_PSC_partAPdS_S_S_S_S_S_
	.type	_Z42__device_stub__executeThirdLayer_PSC_partAPdS_S_S_S_S_S_,@function
_Z42__device_stub__executeThirdLayer_PSC_partAPdS_S_S_S_S_S_: # @_Z42__device_stub__executeThirdLayer_PSC_partAPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z27executeThirdLayer_PSC_partAPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z42__device_stub__executeThirdLayer_PSC_partAPdS_S_S_S_S_S_, .Lfunc_end6-_Z42__device_stub__executeThirdLayer_PSC_partAPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z42__device_stub__executeThirdLayer_PSC_partBPdS_S_S_S_S_S_ # -- Begin function _Z42__device_stub__executeThirdLayer_PSC_partBPdS_S_S_S_S_S_
	.type	_Z42__device_stub__executeThirdLayer_PSC_partBPdS_S_S_S_S_S_,@function
_Z42__device_stub__executeThirdLayer_PSC_partBPdS_S_S_S_S_S_: # @_Z42__device_stub__executeThirdLayer_PSC_partBPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z27executeThirdLayer_PSC_partBPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_Z42__device_stub__executeThirdLayer_PSC_partBPdS_S_S_S_S_S_, .Lfunc_end7-_Z42__device_stub__executeThirdLayer_PSC_partBPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z42__device_stub__executeThirdLayer_PSC_partCPdS_S_S_S_S_S_ # -- Begin function _Z42__device_stub__executeThirdLayer_PSC_partCPdS_S_S_S_S_S_
	.type	_Z42__device_stub__executeThirdLayer_PSC_partCPdS_S_S_S_S_S_,@function
_Z42__device_stub__executeThirdLayer_PSC_partCPdS_S_S_S_S_S_: # @_Z42__device_stub__executeThirdLayer_PSC_partCPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z27executeThirdLayer_PSC_partCPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end8:
	.size	_Z42__device_stub__executeThirdLayer_PSC_partCPdS_S_S_S_S_S_, .Lfunc_end8-_Z42__device_stub__executeThirdLayer_PSC_partCPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z43__device_stub__executeFourthLayer_DSC_partAPdS_S_S_S_S_S_ # -- Begin function _Z43__device_stub__executeFourthLayer_DSC_partAPdS_S_S_S_S_S_
	.type	_Z43__device_stub__executeFourthLayer_DSC_partAPdS_S_S_S_S_S_,@function
_Z43__device_stub__executeFourthLayer_DSC_partAPdS_S_S_S_S_S_: # @_Z43__device_stub__executeFourthLayer_DSC_partAPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z28executeFourthLayer_DSC_partAPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end9:
	.size	_Z43__device_stub__executeFourthLayer_DSC_partAPdS_S_S_S_S_S_, .Lfunc_end9-_Z43__device_stub__executeFourthLayer_DSC_partAPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z43__device_stub__executeFourthLayer_DSC_partBPdS_S_S_S_S_S_ # -- Begin function _Z43__device_stub__executeFourthLayer_DSC_partBPdS_S_S_S_S_S_
	.type	_Z43__device_stub__executeFourthLayer_DSC_partBPdS_S_S_S_S_S_,@function
_Z43__device_stub__executeFourthLayer_DSC_partBPdS_S_S_S_S_S_: # @_Z43__device_stub__executeFourthLayer_DSC_partBPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z28executeFourthLayer_DSC_partBPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end10:
	.size	_Z43__device_stub__executeFourthLayer_DSC_partBPdS_S_S_S_S_S_, .Lfunc_end10-_Z43__device_stub__executeFourthLayer_DSC_partBPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z43__device_stub__executeFourthLayer_DSC_partCPdS_S_S_S_S_S_ # -- Begin function _Z43__device_stub__executeFourthLayer_DSC_partCPdS_S_S_S_S_S_
	.type	_Z43__device_stub__executeFourthLayer_DSC_partCPdS_S_S_S_S_S_,@function
_Z43__device_stub__executeFourthLayer_DSC_partCPdS_S_S_S_S_S_: # @_Z43__device_stub__executeFourthLayer_DSC_partCPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z28executeFourthLayer_DSC_partCPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end11:
	.size	_Z43__device_stub__executeFourthLayer_DSC_partCPdS_S_S_S_S_S_, .Lfunc_end11-_Z43__device_stub__executeFourthLayer_DSC_partCPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z43__device_stub__executeFourthLayer_DSC_partDPdS_S_S_S_S_S_ # -- Begin function _Z43__device_stub__executeFourthLayer_DSC_partDPdS_S_S_S_S_S_
	.type	_Z43__device_stub__executeFourthLayer_DSC_partDPdS_S_S_S_S_S_,@function
_Z43__device_stub__executeFourthLayer_DSC_partDPdS_S_S_S_S_S_: # @_Z43__device_stub__executeFourthLayer_DSC_partDPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z28executeFourthLayer_DSC_partDPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end12:
	.size	_Z43__device_stub__executeFourthLayer_DSC_partDPdS_S_S_S_S_S_, .Lfunc_end12-_Z43__device_stub__executeFourthLayer_DSC_partDPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z42__device_stub__executeFifthLayer_PSC_partAPdS_S_S_S_S_S_ # -- Begin function _Z42__device_stub__executeFifthLayer_PSC_partAPdS_S_S_S_S_S_
	.type	_Z42__device_stub__executeFifthLayer_PSC_partAPdS_S_S_S_S_S_,@function
_Z42__device_stub__executeFifthLayer_PSC_partAPdS_S_S_S_S_S_: # @_Z42__device_stub__executeFifthLayer_PSC_partAPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z27executeFifthLayer_PSC_partAPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end13:
	.size	_Z42__device_stub__executeFifthLayer_PSC_partAPdS_S_S_S_S_S_, .Lfunc_end13-_Z42__device_stub__executeFifthLayer_PSC_partAPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z42__device_stub__executeFifthLayer_PSC_partBPdS_S_S_S_S_S_ # -- Begin function _Z42__device_stub__executeFifthLayer_PSC_partBPdS_S_S_S_S_S_
	.type	_Z42__device_stub__executeFifthLayer_PSC_partBPdS_S_S_S_S_S_,@function
_Z42__device_stub__executeFifthLayer_PSC_partBPdS_S_S_S_S_S_: # @_Z42__device_stub__executeFifthLayer_PSC_partBPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z27executeFifthLayer_PSC_partBPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end14:
	.size	_Z42__device_stub__executeFifthLayer_PSC_partBPdS_S_S_S_S_S_, .Lfunc_end14-_Z42__device_stub__executeFifthLayer_PSC_partBPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z42__device_stub__executeFifthLayer_PSC_partCPdS_S_S_S_S_S_ # -- Begin function _Z42__device_stub__executeFifthLayer_PSC_partCPdS_S_S_S_S_S_
	.type	_Z42__device_stub__executeFifthLayer_PSC_partCPdS_S_S_S_S_S_,@function
_Z42__device_stub__executeFifthLayer_PSC_partCPdS_S_S_S_S_S_: # @_Z42__device_stub__executeFifthLayer_PSC_partCPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z27executeFifthLayer_PSC_partCPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end15:
	.size	_Z42__device_stub__executeFifthLayer_PSC_partCPdS_S_S_S_S_S_, .Lfunc_end15-_Z42__device_stub__executeFifthLayer_PSC_partCPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z42__device_stub__executeFifthLayer_PSC_partDPdS_S_S_S_S_S_ # -- Begin function _Z42__device_stub__executeFifthLayer_PSC_partDPdS_S_S_S_S_S_
	.type	_Z42__device_stub__executeFifthLayer_PSC_partDPdS_S_S_S_S_S_,@function
_Z42__device_stub__executeFifthLayer_PSC_partDPdS_S_S_S_S_S_: # @_Z42__device_stub__executeFifthLayer_PSC_partDPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z27executeFifthLayer_PSC_partDPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end16:
	.size	_Z42__device_stub__executeFifthLayer_PSC_partDPdS_S_S_S_S_S_, .Lfunc_end16-_Z42__device_stub__executeFifthLayer_PSC_partDPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z42__device_stub__executeSixthLayer_DSC_partAPdS_S_S_S_S_S_ # -- Begin function _Z42__device_stub__executeSixthLayer_DSC_partAPdS_S_S_S_S_S_
	.type	_Z42__device_stub__executeSixthLayer_DSC_partAPdS_S_S_S_S_S_,@function
_Z42__device_stub__executeSixthLayer_DSC_partAPdS_S_S_S_S_S_: # @_Z42__device_stub__executeSixthLayer_DSC_partAPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z27executeSixthLayer_DSC_partAPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end17:
	.size	_Z42__device_stub__executeSixthLayer_DSC_partAPdS_S_S_S_S_S_, .Lfunc_end17-_Z42__device_stub__executeSixthLayer_DSC_partAPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z42__device_stub__executeSixthLayer_DSC_partBPdS_S_S_S_S_S_ # -- Begin function _Z42__device_stub__executeSixthLayer_DSC_partBPdS_S_S_S_S_S_
	.type	_Z42__device_stub__executeSixthLayer_DSC_partBPdS_S_S_S_S_S_,@function
_Z42__device_stub__executeSixthLayer_DSC_partBPdS_S_S_S_S_S_: # @_Z42__device_stub__executeSixthLayer_DSC_partBPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z27executeSixthLayer_DSC_partBPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end18:
	.size	_Z42__device_stub__executeSixthLayer_DSC_partBPdS_S_S_S_S_S_, .Lfunc_end18-_Z42__device_stub__executeSixthLayer_DSC_partBPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z42__device_stub__executeSixthLayer_DSC_partCPdS_S_S_S_S_S_ # -- Begin function _Z42__device_stub__executeSixthLayer_DSC_partCPdS_S_S_S_S_S_
	.type	_Z42__device_stub__executeSixthLayer_DSC_partCPdS_S_S_S_S_S_,@function
_Z42__device_stub__executeSixthLayer_DSC_partCPdS_S_S_S_S_S_: # @_Z42__device_stub__executeSixthLayer_DSC_partCPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z27executeSixthLayer_DSC_partCPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end19:
	.size	_Z42__device_stub__executeSixthLayer_DSC_partCPdS_S_S_S_S_S_, .Lfunc_end19-_Z42__device_stub__executeSixthLayer_DSC_partCPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z42__device_stub__executeSixthLayer_DSC_partDPdS_S_S_S_S_S_ # -- Begin function _Z42__device_stub__executeSixthLayer_DSC_partDPdS_S_S_S_S_S_
	.type	_Z42__device_stub__executeSixthLayer_DSC_partDPdS_S_S_S_S_S_,@function
_Z42__device_stub__executeSixthLayer_DSC_partDPdS_S_S_S_S_S_: # @_Z42__device_stub__executeSixthLayer_DSC_partDPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z27executeSixthLayer_DSC_partDPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end20:
	.size	_Z42__device_stub__executeSixthLayer_DSC_partDPdS_S_S_S_S_S_, .Lfunc_end20-_Z42__device_stub__executeSixthLayer_DSC_partDPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z44__device_stub__executeSeventhLayer_PSC_partAPdS_S_S_S_S_S_ # -- Begin function _Z44__device_stub__executeSeventhLayer_PSC_partAPdS_S_S_S_S_S_
	.type	_Z44__device_stub__executeSeventhLayer_PSC_partAPdS_S_S_S_S_S_,@function
_Z44__device_stub__executeSeventhLayer_PSC_partAPdS_S_S_S_S_S_: # @_Z44__device_stub__executeSeventhLayer_PSC_partAPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z29executeSeventhLayer_PSC_partAPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end21:
	.size	_Z44__device_stub__executeSeventhLayer_PSC_partAPdS_S_S_S_S_S_, .Lfunc_end21-_Z44__device_stub__executeSeventhLayer_PSC_partAPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z44__device_stub__executeSeventhLayer_PSC_partBPdS_S_S_S_S_S_ # -- Begin function _Z44__device_stub__executeSeventhLayer_PSC_partBPdS_S_S_S_S_S_
	.type	_Z44__device_stub__executeSeventhLayer_PSC_partBPdS_S_S_S_S_S_,@function
_Z44__device_stub__executeSeventhLayer_PSC_partBPdS_S_S_S_S_S_: # @_Z44__device_stub__executeSeventhLayer_PSC_partBPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z29executeSeventhLayer_PSC_partBPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end22:
	.size	_Z44__device_stub__executeSeventhLayer_PSC_partBPdS_S_S_S_S_S_, .Lfunc_end22-_Z44__device_stub__executeSeventhLayer_PSC_partBPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z44__device_stub__executeSeventhLayer_PSC_partCPdS_S_S_S_S_S_ # -- Begin function _Z44__device_stub__executeSeventhLayer_PSC_partCPdS_S_S_S_S_S_
	.type	_Z44__device_stub__executeSeventhLayer_PSC_partCPdS_S_S_S_S_S_,@function
_Z44__device_stub__executeSeventhLayer_PSC_partCPdS_S_S_S_S_S_: # @_Z44__device_stub__executeSeventhLayer_PSC_partCPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z29executeSeventhLayer_PSC_partCPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end23:
	.size	_Z44__device_stub__executeSeventhLayer_PSC_partCPdS_S_S_S_S_S_, .Lfunc_end23-_Z44__device_stub__executeSeventhLayer_PSC_partCPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z44__device_stub__executeSeventhLayer_PSC_partDPdS_S_S_S_S_S_ # -- Begin function _Z44__device_stub__executeSeventhLayer_PSC_partDPdS_S_S_S_S_S_
	.type	_Z44__device_stub__executeSeventhLayer_PSC_partDPdS_S_S_S_S_S_,@function
_Z44__device_stub__executeSeventhLayer_PSC_partDPdS_S_S_S_S_S_: # @_Z44__device_stub__executeSeventhLayer_PSC_partDPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z29executeSeventhLayer_PSC_partDPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end24:
	.size	_Z44__device_stub__executeSeventhLayer_PSC_partDPdS_S_S_S_S_S_, .Lfunc_end24-_Z44__device_stub__executeSeventhLayer_PSC_partDPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z37__device_stub__executeEighthLayer_DSCPdS_S_S_S_S_S_ # -- Begin function _Z37__device_stub__executeEighthLayer_DSCPdS_S_S_S_S_S_
	.type	_Z37__device_stub__executeEighthLayer_DSCPdS_S_S_S_S_S_,@function
_Z37__device_stub__executeEighthLayer_DSCPdS_S_S_S_S_S_: # @_Z37__device_stub__executeEighthLayer_DSCPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z22executeEighthLayer_DSCPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end25:
	.size	_Z37__device_stub__executeEighthLayer_DSCPdS_S_S_S_S_S_, .Lfunc_end25-_Z37__device_stub__executeEighthLayer_DSCPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z36__device_stub__executeNinthLayer_PSCPdS_S_S_S_S_S_ # -- Begin function _Z36__device_stub__executeNinthLayer_PSCPdS_S_S_S_S_S_
	.type	_Z36__device_stub__executeNinthLayer_PSCPdS_S_S_S_S_S_,@function
_Z36__device_stub__executeNinthLayer_PSCPdS_S_S_S_S_S_: # @_Z36__device_stub__executeNinthLayer_PSCPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z21executeNinthLayer_PSCPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end26:
	.size	_Z36__device_stub__executeNinthLayer_PSCPdS_S_S_S_S_S_, .Lfunc_end26-_Z36__device_stub__executeNinthLayer_PSCPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z36__device_stub__executeTenthLayer_DSCPdS_S_S_S_S_S_ # -- Begin function _Z36__device_stub__executeTenthLayer_DSCPdS_S_S_S_S_S_
	.type	_Z36__device_stub__executeTenthLayer_DSCPdS_S_S_S_S_S_,@function
_Z36__device_stub__executeTenthLayer_DSCPdS_S_S_S_S_S_: # @_Z36__device_stub__executeTenthLayer_DSCPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z21executeTenthLayer_DSCPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end27:
	.size	_Z36__device_stub__executeTenthLayer_DSCPdS_S_S_S_S_S_, .Lfunc_end27-_Z36__device_stub__executeTenthLayer_DSCPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z39__device_stub__executeEleventhLayer_PSCPdS_S_S_S_S_S_ # -- Begin function _Z39__device_stub__executeEleventhLayer_PSCPdS_S_S_S_S_S_
	.type	_Z39__device_stub__executeEleventhLayer_PSCPdS_S_S_S_S_S_,@function
_Z39__device_stub__executeEleventhLayer_PSCPdS_S_S_S_S_S_: # @_Z39__device_stub__executeEleventhLayer_PSCPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z24executeEleventhLayer_PSCPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end28:
	.size	_Z39__device_stub__executeEleventhLayer_PSCPdS_S_S_S_S_S_, .Lfunc_end28-_Z39__device_stub__executeEleventhLayer_PSCPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z38__device_stub__executeTwelfthLayer_DSCPdS_S_S_S_S_S_ # -- Begin function _Z38__device_stub__executeTwelfthLayer_DSCPdS_S_S_S_S_S_
	.type	_Z38__device_stub__executeTwelfthLayer_DSCPdS_S_S_S_S_S_,@function
_Z38__device_stub__executeTwelfthLayer_DSCPdS_S_S_S_S_S_: # @_Z38__device_stub__executeTwelfthLayer_DSCPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z23executeTwelfthLayer_DSCPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end29:
	.size	_Z38__device_stub__executeTwelfthLayer_DSCPdS_S_S_S_S_S_, .Lfunc_end29-_Z38__device_stub__executeTwelfthLayer_DSCPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z41__device_stub__executeThirteenthLayer_PSCPdS_S_S_S_S_S_ # -- Begin function _Z41__device_stub__executeThirteenthLayer_PSCPdS_S_S_S_S_S_
	.type	_Z41__device_stub__executeThirteenthLayer_PSCPdS_S_S_S_S_S_,@function
_Z41__device_stub__executeThirteenthLayer_PSCPdS_S_S_S_S_S_: # @_Z41__device_stub__executeThirteenthLayer_PSCPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z26executeThirteenthLayer_PSCPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end30:
	.size	_Z41__device_stub__executeThirteenthLayer_PSCPdS_S_S_S_S_S_, .Lfunc_end30-_Z41__device_stub__executeThirteenthLayer_PSCPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z41__device_stub__executeFourteenthLayer_DSCPdS_S_S_S_S_S_ # -- Begin function _Z41__device_stub__executeFourteenthLayer_DSCPdS_S_S_S_S_S_
	.type	_Z41__device_stub__executeFourteenthLayer_DSCPdS_S_S_S_S_S_,@function
_Z41__device_stub__executeFourteenthLayer_DSCPdS_S_S_S_S_S_: # @_Z41__device_stub__executeFourteenthLayer_DSCPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z26executeFourteenthLayer_DSCPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end31:
	.size	_Z41__device_stub__executeFourteenthLayer_DSCPdS_S_S_S_S_S_, .Lfunc_end31-_Z41__device_stub__executeFourteenthLayer_DSCPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z40__device_stub__executeFifteenthLayer_PSCPdS_S_S_S_S_S_ # -- Begin function _Z40__device_stub__executeFifteenthLayer_PSCPdS_S_S_S_S_S_
	.type	_Z40__device_stub__executeFifteenthLayer_PSCPdS_S_S_S_S_S_,@function
_Z40__device_stub__executeFifteenthLayer_PSCPdS_S_S_S_S_S_: # @_Z40__device_stub__executeFifteenthLayer_PSCPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z25executeFifteenthLayer_PSCPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end32:
	.size	_Z40__device_stub__executeFifteenthLayer_PSCPdS_S_S_S_S_S_, .Lfunc_end32-_Z40__device_stub__executeFifteenthLayer_PSCPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z40__device_stub__executeSixteenthLayer_DSCPdS_S_S_S_S_S_ # -- Begin function _Z40__device_stub__executeSixteenthLayer_DSCPdS_S_S_S_S_S_
	.type	_Z40__device_stub__executeSixteenthLayer_DSCPdS_S_S_S_S_S_,@function
_Z40__device_stub__executeSixteenthLayer_DSCPdS_S_S_S_S_S_: # @_Z40__device_stub__executeSixteenthLayer_DSCPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z25executeSixteenthLayer_DSCPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end33:
	.size	_Z40__device_stub__executeSixteenthLayer_DSCPdS_S_S_S_S_S_, .Lfunc_end33-_Z40__device_stub__executeSixteenthLayer_DSCPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z42__device_stub__executeSeventeenthLayer_PSCPdS_S_S_S_S_S_ # -- Begin function _Z42__device_stub__executeSeventeenthLayer_PSCPdS_S_S_S_S_S_
	.type	_Z42__device_stub__executeSeventeenthLayer_PSCPdS_S_S_S_S_S_,@function
_Z42__device_stub__executeSeventeenthLayer_PSCPdS_S_S_S_S_S_: # @_Z42__device_stub__executeSeventeenthLayer_PSCPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z27executeSeventeenthLayer_PSCPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end34:
	.size	_Z42__device_stub__executeSeventeenthLayer_PSCPdS_S_S_S_S_S_, .Lfunc_end34-_Z42__device_stub__executeSeventeenthLayer_PSCPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z41__device_stub__executeEighteenthLayer_DSCPdS_S_S_S_S_S_ # -- Begin function _Z41__device_stub__executeEighteenthLayer_DSCPdS_S_S_S_S_S_
	.type	_Z41__device_stub__executeEighteenthLayer_DSCPdS_S_S_S_S_S_,@function
_Z41__device_stub__executeEighteenthLayer_DSCPdS_S_S_S_S_S_: # @_Z41__device_stub__executeEighteenthLayer_DSCPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z26executeEighteenthLayer_DSCPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end35:
	.size	_Z41__device_stub__executeEighteenthLayer_DSCPdS_S_S_S_S_S_, .Lfunc_end35-_Z41__device_stub__executeEighteenthLayer_DSCPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z41__device_stub__executeNineteenthLayer_PSCPdS_S_S_S_S_S_ # -- Begin function _Z41__device_stub__executeNineteenthLayer_PSCPdS_S_S_S_S_S_
	.type	_Z41__device_stub__executeNineteenthLayer_PSCPdS_S_S_S_S_S_,@function
_Z41__device_stub__executeNineteenthLayer_PSCPdS_S_S_S_S_S_: # @_Z41__device_stub__executeNineteenthLayer_PSCPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z26executeNineteenthLayer_PSCPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end36:
	.size	_Z41__device_stub__executeNineteenthLayer_PSCPdS_S_S_S_S_S_, .Lfunc_end36-_Z41__device_stub__executeNineteenthLayer_PSCPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z37__device_stub__executeTwentyLayer_DSCPdS_S_S_S_S_S_ # -- Begin function _Z37__device_stub__executeTwentyLayer_DSCPdS_S_S_S_S_S_
	.type	_Z37__device_stub__executeTwentyLayer_DSCPdS_S_S_S_S_S_,@function
_Z37__device_stub__executeTwentyLayer_DSCPdS_S_S_S_S_S_: # @_Z37__device_stub__executeTwentyLayer_DSCPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z22executeTwentyLayer_DSCPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end37:
	.size	_Z37__device_stub__executeTwentyLayer_DSCPdS_S_S_S_S_S_, .Lfunc_end37-_Z37__device_stub__executeTwentyLayer_DSCPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z40__device_stub__executeTwentyOneLayer_PSCPdS_S_S_S_S_S_ # -- Begin function _Z40__device_stub__executeTwentyOneLayer_PSCPdS_S_S_S_S_S_
	.type	_Z40__device_stub__executeTwentyOneLayer_PSCPdS_S_S_S_S_S_,@function
_Z40__device_stub__executeTwentyOneLayer_PSCPdS_S_S_S_S_S_: # @_Z40__device_stub__executeTwentyOneLayer_PSCPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z25executeTwentyOneLayer_PSCPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end38:
	.size	_Z40__device_stub__executeTwentyOneLayer_PSCPdS_S_S_S_S_S_, .Lfunc_end38-_Z40__device_stub__executeTwentyOneLayer_PSCPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z40__device_stub__executeTwentyTwoLayer_DSCPdS_S_S_S_S_S_ # -- Begin function _Z40__device_stub__executeTwentyTwoLayer_DSCPdS_S_S_S_S_S_
	.type	_Z40__device_stub__executeTwentyTwoLayer_DSCPdS_S_S_S_S_S_,@function
_Z40__device_stub__executeTwentyTwoLayer_DSCPdS_S_S_S_S_S_: # @_Z40__device_stub__executeTwentyTwoLayer_DSCPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z25executeTwentyTwoLayer_DSCPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end39:
	.size	_Z40__device_stub__executeTwentyTwoLayer_DSCPdS_S_S_S_S_S_, .Lfunc_end39-_Z40__device_stub__executeTwentyTwoLayer_DSCPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z42__device_stub__executeTwentyThreeLayer_PSCPdS_S_S_S_S_S_ # -- Begin function _Z42__device_stub__executeTwentyThreeLayer_PSCPdS_S_S_S_S_S_
	.type	_Z42__device_stub__executeTwentyThreeLayer_PSCPdS_S_S_S_S_S_,@function
_Z42__device_stub__executeTwentyThreeLayer_PSCPdS_S_S_S_S_S_: # @_Z42__device_stub__executeTwentyThreeLayer_PSCPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z27executeTwentyThreeLayer_PSCPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end40:
	.size	_Z42__device_stub__executeTwentyThreeLayer_PSCPdS_S_S_S_S_S_, .Lfunc_end40-_Z42__device_stub__executeTwentyThreeLayer_PSCPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z41__device_stub__executeTwentyFourLayer_DSCPdS_S_S_S_S_S_ # -- Begin function _Z41__device_stub__executeTwentyFourLayer_DSCPdS_S_S_S_S_S_
	.type	_Z41__device_stub__executeTwentyFourLayer_DSCPdS_S_S_S_S_S_,@function
_Z41__device_stub__executeTwentyFourLayer_DSCPdS_S_S_S_S_S_: # @_Z41__device_stub__executeTwentyFourLayer_DSCPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z26executeTwentyFourLayer_DSCPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end41:
	.size	_Z41__device_stub__executeTwentyFourLayer_DSCPdS_S_S_S_S_S_, .Lfunc_end41-_Z41__device_stub__executeTwentyFourLayer_DSCPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z41__device_stub__executeTwentyFiveLayer_PSCPdS_S_S_S_S_S_ # -- Begin function _Z41__device_stub__executeTwentyFiveLayer_PSCPdS_S_S_S_S_S_
	.type	_Z41__device_stub__executeTwentyFiveLayer_PSCPdS_S_S_S_S_S_,@function
_Z41__device_stub__executeTwentyFiveLayer_PSCPdS_S_S_S_S_S_: # @_Z41__device_stub__executeTwentyFiveLayer_PSCPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z26executeTwentyFiveLayer_PSCPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end42:
	.size	_Z41__device_stub__executeTwentyFiveLayer_PSCPdS_S_S_S_S_S_, .Lfunc_end42-_Z41__device_stub__executeTwentyFiveLayer_PSCPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z40__device_stub__executeTwentySixLayer_DSCPdS_S_S_S_S_S_ # -- Begin function _Z40__device_stub__executeTwentySixLayer_DSCPdS_S_S_S_S_S_
	.type	_Z40__device_stub__executeTwentySixLayer_DSCPdS_S_S_S_S_S_,@function
_Z40__device_stub__executeTwentySixLayer_DSCPdS_S_S_S_S_S_: # @_Z40__device_stub__executeTwentySixLayer_DSCPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z25executeTwentySixLayer_DSCPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end43:
	.size	_Z40__device_stub__executeTwentySixLayer_DSCPdS_S_S_S_S_S_, .Lfunc_end43-_Z40__device_stub__executeTwentySixLayer_DSCPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z42__device_stub__executeTwentySevenLayer_PSCPdS_S_S_S_S_S_ # -- Begin function _Z42__device_stub__executeTwentySevenLayer_PSCPdS_S_S_S_S_S_
	.type	_Z42__device_stub__executeTwentySevenLayer_PSCPdS_S_S_S_S_S_,@function
_Z42__device_stub__executeTwentySevenLayer_PSCPdS_S_S_S_S_S_: # @_Z42__device_stub__executeTwentySevenLayer_PSCPdS_S_S_S_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	16(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z27executeTwentySevenLayer_PSCPdS_S_S_S_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end44:
	.size	_Z42__device_stub__executeTwentySevenLayer_PSCPdS_S_S_S_S_S_, .Lfunc_end44-_Z42__device_stub__executeTwentySevenLayer_PSCPdS_S_S_S_S_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z49__device_stub__executeTwentyEightLayer_AvgPoolingPdS_ # -- Begin function _Z49__device_stub__executeTwentyEightLayer_AvgPoolingPdS_
	.type	_Z49__device_stub__executeTwentyEightLayer_AvgPoolingPdS_,@function
_Z49__device_stub__executeTwentyEightLayer_AvgPoolingPdS_: # @_Z49__device_stub__executeTwentyEightLayer_AvgPoolingPdS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z34executeTwentyEightLayer_AvgPoolingPdS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end45:
	.size	_Z49__device_stub__executeTwentyEightLayer_AvgPoolingPdS_, .Lfunc_end45-_Z49__device_stub__executeTwentyEightLayer_AvgPoolingPdS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z52__device_stub__executeTwentyNineLayer_FullyConnectedPdS_S_S_ # -- Begin function _Z52__device_stub__executeTwentyNineLayer_FullyConnectedPdS_S_S_
	.type	_Z52__device_stub__executeTwentyNineLayer_FullyConnectedPdS_S_S_,@function
_Z52__device_stub__executeTwentyNineLayer_FullyConnectedPdS_S_S_: # @_Z52__device_stub__executeTwentyNineLayer_FullyConnectedPdS_S_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z37executeTwentyNineLayer_FullyConnectedPdS_S_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end46:
	.size	_Z52__device_stub__executeTwentyNineLayer_FullyConnectedPdS_S_S_, .Lfunc_end46-_Z52__device_stub__executeTwentyNineLayer_FullyConnectedPdS_S_S_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB47_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB47_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z30executeFirstLayer_CONV3D_partAPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z30executeFirstLayer_CONV3D_partBPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z30executeFirstLayer_CONV3D_partCPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z28executeSecondLayer_DSC_partAPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z28executeSecondLayer_DSC_partBPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z28executeSecondLayer_DSC_partCPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z27executeThirdLayer_PSC_partAPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z27executeThirdLayer_PSC_partBPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_8, %edx
	movl	$.L__unnamed_8, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z27executeThirdLayer_PSC_partCPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_9, %edx
	movl	$.L__unnamed_9, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z28executeFourthLayer_DSC_partAPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_10, %edx
	movl	$.L__unnamed_10, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z28executeFourthLayer_DSC_partBPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_11, %edx
	movl	$.L__unnamed_11, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z28executeFourthLayer_DSC_partCPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_12, %edx
	movl	$.L__unnamed_12, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z28executeFourthLayer_DSC_partDPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_13, %edx
	movl	$.L__unnamed_13, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z27executeFifthLayer_PSC_partAPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_14, %edx
	movl	$.L__unnamed_14, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z27executeFifthLayer_PSC_partBPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_15, %edx
	movl	$.L__unnamed_15, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z27executeFifthLayer_PSC_partCPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_16, %edx
	movl	$.L__unnamed_16, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z27executeFifthLayer_PSC_partDPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_17, %edx
	movl	$.L__unnamed_17, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z27executeSixthLayer_DSC_partAPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_18, %edx
	movl	$.L__unnamed_18, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z27executeSixthLayer_DSC_partBPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_19, %edx
	movl	$.L__unnamed_19, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z27executeSixthLayer_DSC_partCPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_20, %edx
	movl	$.L__unnamed_20, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z27executeSixthLayer_DSC_partDPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_21, %edx
	movl	$.L__unnamed_21, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z29executeSeventhLayer_PSC_partAPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_22, %edx
	movl	$.L__unnamed_22, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z29executeSeventhLayer_PSC_partBPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_23, %edx
	movl	$.L__unnamed_23, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z29executeSeventhLayer_PSC_partCPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_24, %edx
	movl	$.L__unnamed_24, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z29executeSeventhLayer_PSC_partDPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_25, %edx
	movl	$.L__unnamed_25, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z22executeEighthLayer_DSCPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_26, %edx
	movl	$.L__unnamed_26, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z21executeNinthLayer_PSCPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_27, %edx
	movl	$.L__unnamed_27, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z21executeTenthLayer_DSCPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_28, %edx
	movl	$.L__unnamed_28, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z24executeEleventhLayer_PSCPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_29, %edx
	movl	$.L__unnamed_29, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z23executeTwelfthLayer_DSCPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_30, %edx
	movl	$.L__unnamed_30, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z26executeThirteenthLayer_PSCPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_31, %edx
	movl	$.L__unnamed_31, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z26executeFourteenthLayer_DSCPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_32, %edx
	movl	$.L__unnamed_32, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z25executeFifteenthLayer_PSCPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_33, %edx
	movl	$.L__unnamed_33, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z25executeSixteenthLayer_DSCPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_34, %edx
	movl	$.L__unnamed_34, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z27executeSeventeenthLayer_PSCPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_35, %edx
	movl	$.L__unnamed_35, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z26executeEighteenthLayer_DSCPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_36, %edx
	movl	$.L__unnamed_36, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z26executeNineteenthLayer_PSCPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_37, %edx
	movl	$.L__unnamed_37, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z22executeTwentyLayer_DSCPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_38, %edx
	movl	$.L__unnamed_38, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z25executeTwentyOneLayer_PSCPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_39, %edx
	movl	$.L__unnamed_39, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z25executeTwentyTwoLayer_DSCPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_40, %edx
	movl	$.L__unnamed_40, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z27executeTwentyThreeLayer_PSCPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_41, %edx
	movl	$.L__unnamed_41, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z26executeTwentyFourLayer_DSCPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_42, %edx
	movl	$.L__unnamed_42, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z26executeTwentyFiveLayer_PSCPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_43, %edx
	movl	$.L__unnamed_43, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z25executeTwentySixLayer_DSCPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_44, %edx
	movl	$.L__unnamed_44, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z27executeTwentySevenLayer_PSCPdS_S_S_S_S_S_, %esi
	movl	$.L__unnamed_45, %edx
	movl	$.L__unnamed_45, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z34executeTwentyEightLayer_AvgPoolingPdS_, %esi
	movl	$.L__unnamed_46, %edx
	movl	$.L__unnamed_46, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z37executeTwentyNineLayer_FullyConnectedPdS_S_S_, %esi
	movl	$.L__unnamed_47, %edx
	movl	$.L__unnamed_47, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end47:
	.size	__hip_module_ctor, .Lfunc_end47-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB48_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB48_2:
	retq
.Lfunc_end48:
	.size	__hip_module_dtor, .Lfunc_end48-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z30executeFirstLayer_CONV3D_partAPdS_S_S_S_S_S_,@object # @_Z30executeFirstLayer_CONV3D_partAPdS_S_S_S_S_S_
	.section	.rodata,"a",@progbits
	.globl	_Z30executeFirstLayer_CONV3D_partAPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z30executeFirstLayer_CONV3D_partAPdS_S_S_S_S_S_:
	.quad	_Z45__device_stub__executeFirstLayer_CONV3D_partAPdS_S_S_S_S_S_
	.size	_Z30executeFirstLayer_CONV3D_partAPdS_S_S_S_S_S_, 8

	.type	_Z30executeFirstLayer_CONV3D_partBPdS_S_S_S_S_S_,@object # @_Z30executeFirstLayer_CONV3D_partBPdS_S_S_S_S_S_
	.globl	_Z30executeFirstLayer_CONV3D_partBPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z30executeFirstLayer_CONV3D_partBPdS_S_S_S_S_S_:
	.quad	_Z45__device_stub__executeFirstLayer_CONV3D_partBPdS_S_S_S_S_S_
	.size	_Z30executeFirstLayer_CONV3D_partBPdS_S_S_S_S_S_, 8

	.type	_Z30executeFirstLayer_CONV3D_partCPdS_S_S_S_S_S_,@object # @_Z30executeFirstLayer_CONV3D_partCPdS_S_S_S_S_S_
	.globl	_Z30executeFirstLayer_CONV3D_partCPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z30executeFirstLayer_CONV3D_partCPdS_S_S_S_S_S_:
	.quad	_Z45__device_stub__executeFirstLayer_CONV3D_partCPdS_S_S_S_S_S_
	.size	_Z30executeFirstLayer_CONV3D_partCPdS_S_S_S_S_S_, 8

	.type	_Z28executeSecondLayer_DSC_partAPdS_S_S_S_S_S_,@object # @_Z28executeSecondLayer_DSC_partAPdS_S_S_S_S_S_
	.globl	_Z28executeSecondLayer_DSC_partAPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z28executeSecondLayer_DSC_partAPdS_S_S_S_S_S_:
	.quad	_Z43__device_stub__executeSecondLayer_DSC_partAPdS_S_S_S_S_S_
	.size	_Z28executeSecondLayer_DSC_partAPdS_S_S_S_S_S_, 8

	.type	_Z28executeSecondLayer_DSC_partBPdS_S_S_S_S_S_,@object # @_Z28executeSecondLayer_DSC_partBPdS_S_S_S_S_S_
	.globl	_Z28executeSecondLayer_DSC_partBPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z28executeSecondLayer_DSC_partBPdS_S_S_S_S_S_:
	.quad	_Z43__device_stub__executeSecondLayer_DSC_partBPdS_S_S_S_S_S_
	.size	_Z28executeSecondLayer_DSC_partBPdS_S_S_S_S_S_, 8

	.type	_Z28executeSecondLayer_DSC_partCPdS_S_S_S_S_S_,@object # @_Z28executeSecondLayer_DSC_partCPdS_S_S_S_S_S_
	.globl	_Z28executeSecondLayer_DSC_partCPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z28executeSecondLayer_DSC_partCPdS_S_S_S_S_S_:
	.quad	_Z43__device_stub__executeSecondLayer_DSC_partCPdS_S_S_S_S_S_
	.size	_Z28executeSecondLayer_DSC_partCPdS_S_S_S_S_S_, 8

	.type	_Z27executeThirdLayer_PSC_partAPdS_S_S_S_S_S_,@object # @_Z27executeThirdLayer_PSC_partAPdS_S_S_S_S_S_
	.globl	_Z27executeThirdLayer_PSC_partAPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z27executeThirdLayer_PSC_partAPdS_S_S_S_S_S_:
	.quad	_Z42__device_stub__executeThirdLayer_PSC_partAPdS_S_S_S_S_S_
	.size	_Z27executeThirdLayer_PSC_partAPdS_S_S_S_S_S_, 8

	.type	_Z27executeThirdLayer_PSC_partBPdS_S_S_S_S_S_,@object # @_Z27executeThirdLayer_PSC_partBPdS_S_S_S_S_S_
	.globl	_Z27executeThirdLayer_PSC_partBPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z27executeThirdLayer_PSC_partBPdS_S_S_S_S_S_:
	.quad	_Z42__device_stub__executeThirdLayer_PSC_partBPdS_S_S_S_S_S_
	.size	_Z27executeThirdLayer_PSC_partBPdS_S_S_S_S_S_, 8

	.type	_Z27executeThirdLayer_PSC_partCPdS_S_S_S_S_S_,@object # @_Z27executeThirdLayer_PSC_partCPdS_S_S_S_S_S_
	.globl	_Z27executeThirdLayer_PSC_partCPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z27executeThirdLayer_PSC_partCPdS_S_S_S_S_S_:
	.quad	_Z42__device_stub__executeThirdLayer_PSC_partCPdS_S_S_S_S_S_
	.size	_Z27executeThirdLayer_PSC_partCPdS_S_S_S_S_S_, 8

	.type	_Z28executeFourthLayer_DSC_partAPdS_S_S_S_S_S_,@object # @_Z28executeFourthLayer_DSC_partAPdS_S_S_S_S_S_
	.globl	_Z28executeFourthLayer_DSC_partAPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z28executeFourthLayer_DSC_partAPdS_S_S_S_S_S_:
	.quad	_Z43__device_stub__executeFourthLayer_DSC_partAPdS_S_S_S_S_S_
	.size	_Z28executeFourthLayer_DSC_partAPdS_S_S_S_S_S_, 8

	.type	_Z28executeFourthLayer_DSC_partBPdS_S_S_S_S_S_,@object # @_Z28executeFourthLayer_DSC_partBPdS_S_S_S_S_S_
	.globl	_Z28executeFourthLayer_DSC_partBPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z28executeFourthLayer_DSC_partBPdS_S_S_S_S_S_:
	.quad	_Z43__device_stub__executeFourthLayer_DSC_partBPdS_S_S_S_S_S_
	.size	_Z28executeFourthLayer_DSC_partBPdS_S_S_S_S_S_, 8

	.type	_Z28executeFourthLayer_DSC_partCPdS_S_S_S_S_S_,@object # @_Z28executeFourthLayer_DSC_partCPdS_S_S_S_S_S_
	.globl	_Z28executeFourthLayer_DSC_partCPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z28executeFourthLayer_DSC_partCPdS_S_S_S_S_S_:
	.quad	_Z43__device_stub__executeFourthLayer_DSC_partCPdS_S_S_S_S_S_
	.size	_Z28executeFourthLayer_DSC_partCPdS_S_S_S_S_S_, 8

	.type	_Z28executeFourthLayer_DSC_partDPdS_S_S_S_S_S_,@object # @_Z28executeFourthLayer_DSC_partDPdS_S_S_S_S_S_
	.globl	_Z28executeFourthLayer_DSC_partDPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z28executeFourthLayer_DSC_partDPdS_S_S_S_S_S_:
	.quad	_Z43__device_stub__executeFourthLayer_DSC_partDPdS_S_S_S_S_S_
	.size	_Z28executeFourthLayer_DSC_partDPdS_S_S_S_S_S_, 8

	.type	_Z27executeFifthLayer_PSC_partAPdS_S_S_S_S_S_,@object # @_Z27executeFifthLayer_PSC_partAPdS_S_S_S_S_S_
	.globl	_Z27executeFifthLayer_PSC_partAPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z27executeFifthLayer_PSC_partAPdS_S_S_S_S_S_:
	.quad	_Z42__device_stub__executeFifthLayer_PSC_partAPdS_S_S_S_S_S_
	.size	_Z27executeFifthLayer_PSC_partAPdS_S_S_S_S_S_, 8

	.type	_Z27executeFifthLayer_PSC_partBPdS_S_S_S_S_S_,@object # @_Z27executeFifthLayer_PSC_partBPdS_S_S_S_S_S_
	.globl	_Z27executeFifthLayer_PSC_partBPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z27executeFifthLayer_PSC_partBPdS_S_S_S_S_S_:
	.quad	_Z42__device_stub__executeFifthLayer_PSC_partBPdS_S_S_S_S_S_
	.size	_Z27executeFifthLayer_PSC_partBPdS_S_S_S_S_S_, 8

	.type	_Z27executeFifthLayer_PSC_partCPdS_S_S_S_S_S_,@object # @_Z27executeFifthLayer_PSC_partCPdS_S_S_S_S_S_
	.globl	_Z27executeFifthLayer_PSC_partCPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z27executeFifthLayer_PSC_partCPdS_S_S_S_S_S_:
	.quad	_Z42__device_stub__executeFifthLayer_PSC_partCPdS_S_S_S_S_S_
	.size	_Z27executeFifthLayer_PSC_partCPdS_S_S_S_S_S_, 8

	.type	_Z27executeFifthLayer_PSC_partDPdS_S_S_S_S_S_,@object # @_Z27executeFifthLayer_PSC_partDPdS_S_S_S_S_S_
	.globl	_Z27executeFifthLayer_PSC_partDPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z27executeFifthLayer_PSC_partDPdS_S_S_S_S_S_:
	.quad	_Z42__device_stub__executeFifthLayer_PSC_partDPdS_S_S_S_S_S_
	.size	_Z27executeFifthLayer_PSC_partDPdS_S_S_S_S_S_, 8

	.type	_Z27executeSixthLayer_DSC_partAPdS_S_S_S_S_S_,@object # @_Z27executeSixthLayer_DSC_partAPdS_S_S_S_S_S_
	.globl	_Z27executeSixthLayer_DSC_partAPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z27executeSixthLayer_DSC_partAPdS_S_S_S_S_S_:
	.quad	_Z42__device_stub__executeSixthLayer_DSC_partAPdS_S_S_S_S_S_
	.size	_Z27executeSixthLayer_DSC_partAPdS_S_S_S_S_S_, 8

	.type	_Z27executeSixthLayer_DSC_partBPdS_S_S_S_S_S_,@object # @_Z27executeSixthLayer_DSC_partBPdS_S_S_S_S_S_
	.globl	_Z27executeSixthLayer_DSC_partBPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z27executeSixthLayer_DSC_partBPdS_S_S_S_S_S_:
	.quad	_Z42__device_stub__executeSixthLayer_DSC_partBPdS_S_S_S_S_S_
	.size	_Z27executeSixthLayer_DSC_partBPdS_S_S_S_S_S_, 8

	.type	_Z27executeSixthLayer_DSC_partCPdS_S_S_S_S_S_,@object # @_Z27executeSixthLayer_DSC_partCPdS_S_S_S_S_S_
	.globl	_Z27executeSixthLayer_DSC_partCPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z27executeSixthLayer_DSC_partCPdS_S_S_S_S_S_:
	.quad	_Z42__device_stub__executeSixthLayer_DSC_partCPdS_S_S_S_S_S_
	.size	_Z27executeSixthLayer_DSC_partCPdS_S_S_S_S_S_, 8

	.type	_Z27executeSixthLayer_DSC_partDPdS_S_S_S_S_S_,@object # @_Z27executeSixthLayer_DSC_partDPdS_S_S_S_S_S_
	.globl	_Z27executeSixthLayer_DSC_partDPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z27executeSixthLayer_DSC_partDPdS_S_S_S_S_S_:
	.quad	_Z42__device_stub__executeSixthLayer_DSC_partDPdS_S_S_S_S_S_
	.size	_Z27executeSixthLayer_DSC_partDPdS_S_S_S_S_S_, 8

	.type	_Z29executeSeventhLayer_PSC_partAPdS_S_S_S_S_S_,@object # @_Z29executeSeventhLayer_PSC_partAPdS_S_S_S_S_S_
	.globl	_Z29executeSeventhLayer_PSC_partAPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z29executeSeventhLayer_PSC_partAPdS_S_S_S_S_S_:
	.quad	_Z44__device_stub__executeSeventhLayer_PSC_partAPdS_S_S_S_S_S_
	.size	_Z29executeSeventhLayer_PSC_partAPdS_S_S_S_S_S_, 8

	.type	_Z29executeSeventhLayer_PSC_partBPdS_S_S_S_S_S_,@object # @_Z29executeSeventhLayer_PSC_partBPdS_S_S_S_S_S_
	.globl	_Z29executeSeventhLayer_PSC_partBPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z29executeSeventhLayer_PSC_partBPdS_S_S_S_S_S_:
	.quad	_Z44__device_stub__executeSeventhLayer_PSC_partBPdS_S_S_S_S_S_
	.size	_Z29executeSeventhLayer_PSC_partBPdS_S_S_S_S_S_, 8

	.type	_Z29executeSeventhLayer_PSC_partCPdS_S_S_S_S_S_,@object # @_Z29executeSeventhLayer_PSC_partCPdS_S_S_S_S_S_
	.globl	_Z29executeSeventhLayer_PSC_partCPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z29executeSeventhLayer_PSC_partCPdS_S_S_S_S_S_:
	.quad	_Z44__device_stub__executeSeventhLayer_PSC_partCPdS_S_S_S_S_S_
	.size	_Z29executeSeventhLayer_PSC_partCPdS_S_S_S_S_S_, 8

	.type	_Z29executeSeventhLayer_PSC_partDPdS_S_S_S_S_S_,@object # @_Z29executeSeventhLayer_PSC_partDPdS_S_S_S_S_S_
	.globl	_Z29executeSeventhLayer_PSC_partDPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z29executeSeventhLayer_PSC_partDPdS_S_S_S_S_S_:
	.quad	_Z44__device_stub__executeSeventhLayer_PSC_partDPdS_S_S_S_S_S_
	.size	_Z29executeSeventhLayer_PSC_partDPdS_S_S_S_S_S_, 8

	.type	_Z22executeEighthLayer_DSCPdS_S_S_S_S_S_,@object # @_Z22executeEighthLayer_DSCPdS_S_S_S_S_S_
	.globl	_Z22executeEighthLayer_DSCPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z22executeEighthLayer_DSCPdS_S_S_S_S_S_:
	.quad	_Z37__device_stub__executeEighthLayer_DSCPdS_S_S_S_S_S_
	.size	_Z22executeEighthLayer_DSCPdS_S_S_S_S_S_, 8

	.type	_Z21executeNinthLayer_PSCPdS_S_S_S_S_S_,@object # @_Z21executeNinthLayer_PSCPdS_S_S_S_S_S_
	.globl	_Z21executeNinthLayer_PSCPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z21executeNinthLayer_PSCPdS_S_S_S_S_S_:
	.quad	_Z36__device_stub__executeNinthLayer_PSCPdS_S_S_S_S_S_
	.size	_Z21executeNinthLayer_PSCPdS_S_S_S_S_S_, 8

	.type	_Z21executeTenthLayer_DSCPdS_S_S_S_S_S_,@object # @_Z21executeTenthLayer_DSCPdS_S_S_S_S_S_
	.globl	_Z21executeTenthLayer_DSCPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z21executeTenthLayer_DSCPdS_S_S_S_S_S_:
	.quad	_Z36__device_stub__executeTenthLayer_DSCPdS_S_S_S_S_S_
	.size	_Z21executeTenthLayer_DSCPdS_S_S_S_S_S_, 8

	.type	_Z24executeEleventhLayer_PSCPdS_S_S_S_S_S_,@object # @_Z24executeEleventhLayer_PSCPdS_S_S_S_S_S_
	.globl	_Z24executeEleventhLayer_PSCPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z24executeEleventhLayer_PSCPdS_S_S_S_S_S_:
	.quad	_Z39__device_stub__executeEleventhLayer_PSCPdS_S_S_S_S_S_
	.size	_Z24executeEleventhLayer_PSCPdS_S_S_S_S_S_, 8

	.type	_Z23executeTwelfthLayer_DSCPdS_S_S_S_S_S_,@object # @_Z23executeTwelfthLayer_DSCPdS_S_S_S_S_S_
	.globl	_Z23executeTwelfthLayer_DSCPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z23executeTwelfthLayer_DSCPdS_S_S_S_S_S_:
	.quad	_Z38__device_stub__executeTwelfthLayer_DSCPdS_S_S_S_S_S_
	.size	_Z23executeTwelfthLayer_DSCPdS_S_S_S_S_S_, 8

	.type	_Z26executeThirteenthLayer_PSCPdS_S_S_S_S_S_,@object # @_Z26executeThirteenthLayer_PSCPdS_S_S_S_S_S_
	.globl	_Z26executeThirteenthLayer_PSCPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z26executeThirteenthLayer_PSCPdS_S_S_S_S_S_:
	.quad	_Z41__device_stub__executeThirteenthLayer_PSCPdS_S_S_S_S_S_
	.size	_Z26executeThirteenthLayer_PSCPdS_S_S_S_S_S_, 8

	.type	_Z26executeFourteenthLayer_DSCPdS_S_S_S_S_S_,@object # @_Z26executeFourteenthLayer_DSCPdS_S_S_S_S_S_
	.globl	_Z26executeFourteenthLayer_DSCPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z26executeFourteenthLayer_DSCPdS_S_S_S_S_S_:
	.quad	_Z41__device_stub__executeFourteenthLayer_DSCPdS_S_S_S_S_S_
	.size	_Z26executeFourteenthLayer_DSCPdS_S_S_S_S_S_, 8

	.type	_Z25executeFifteenthLayer_PSCPdS_S_S_S_S_S_,@object # @_Z25executeFifteenthLayer_PSCPdS_S_S_S_S_S_
	.globl	_Z25executeFifteenthLayer_PSCPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z25executeFifteenthLayer_PSCPdS_S_S_S_S_S_:
	.quad	_Z40__device_stub__executeFifteenthLayer_PSCPdS_S_S_S_S_S_
	.size	_Z25executeFifteenthLayer_PSCPdS_S_S_S_S_S_, 8

	.type	_Z25executeSixteenthLayer_DSCPdS_S_S_S_S_S_,@object # @_Z25executeSixteenthLayer_DSCPdS_S_S_S_S_S_
	.globl	_Z25executeSixteenthLayer_DSCPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z25executeSixteenthLayer_DSCPdS_S_S_S_S_S_:
	.quad	_Z40__device_stub__executeSixteenthLayer_DSCPdS_S_S_S_S_S_
	.size	_Z25executeSixteenthLayer_DSCPdS_S_S_S_S_S_, 8

	.type	_Z27executeSeventeenthLayer_PSCPdS_S_S_S_S_S_,@object # @_Z27executeSeventeenthLayer_PSCPdS_S_S_S_S_S_
	.globl	_Z27executeSeventeenthLayer_PSCPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z27executeSeventeenthLayer_PSCPdS_S_S_S_S_S_:
	.quad	_Z42__device_stub__executeSeventeenthLayer_PSCPdS_S_S_S_S_S_
	.size	_Z27executeSeventeenthLayer_PSCPdS_S_S_S_S_S_, 8

	.type	_Z26executeEighteenthLayer_DSCPdS_S_S_S_S_S_,@object # @_Z26executeEighteenthLayer_DSCPdS_S_S_S_S_S_
	.globl	_Z26executeEighteenthLayer_DSCPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z26executeEighteenthLayer_DSCPdS_S_S_S_S_S_:
	.quad	_Z41__device_stub__executeEighteenthLayer_DSCPdS_S_S_S_S_S_
	.size	_Z26executeEighteenthLayer_DSCPdS_S_S_S_S_S_, 8

	.type	_Z26executeNineteenthLayer_PSCPdS_S_S_S_S_S_,@object # @_Z26executeNineteenthLayer_PSCPdS_S_S_S_S_S_
	.globl	_Z26executeNineteenthLayer_PSCPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z26executeNineteenthLayer_PSCPdS_S_S_S_S_S_:
	.quad	_Z41__device_stub__executeNineteenthLayer_PSCPdS_S_S_S_S_S_
	.size	_Z26executeNineteenthLayer_PSCPdS_S_S_S_S_S_, 8

	.type	_Z22executeTwentyLayer_DSCPdS_S_S_S_S_S_,@object # @_Z22executeTwentyLayer_DSCPdS_S_S_S_S_S_
	.globl	_Z22executeTwentyLayer_DSCPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z22executeTwentyLayer_DSCPdS_S_S_S_S_S_:
	.quad	_Z37__device_stub__executeTwentyLayer_DSCPdS_S_S_S_S_S_
	.size	_Z22executeTwentyLayer_DSCPdS_S_S_S_S_S_, 8

	.type	_Z25executeTwentyOneLayer_PSCPdS_S_S_S_S_S_,@object # @_Z25executeTwentyOneLayer_PSCPdS_S_S_S_S_S_
	.globl	_Z25executeTwentyOneLayer_PSCPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z25executeTwentyOneLayer_PSCPdS_S_S_S_S_S_:
	.quad	_Z40__device_stub__executeTwentyOneLayer_PSCPdS_S_S_S_S_S_
	.size	_Z25executeTwentyOneLayer_PSCPdS_S_S_S_S_S_, 8

	.type	_Z25executeTwentyTwoLayer_DSCPdS_S_S_S_S_S_,@object # @_Z25executeTwentyTwoLayer_DSCPdS_S_S_S_S_S_
	.globl	_Z25executeTwentyTwoLayer_DSCPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z25executeTwentyTwoLayer_DSCPdS_S_S_S_S_S_:
	.quad	_Z40__device_stub__executeTwentyTwoLayer_DSCPdS_S_S_S_S_S_
	.size	_Z25executeTwentyTwoLayer_DSCPdS_S_S_S_S_S_, 8

	.type	_Z27executeTwentyThreeLayer_PSCPdS_S_S_S_S_S_,@object # @_Z27executeTwentyThreeLayer_PSCPdS_S_S_S_S_S_
	.globl	_Z27executeTwentyThreeLayer_PSCPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z27executeTwentyThreeLayer_PSCPdS_S_S_S_S_S_:
	.quad	_Z42__device_stub__executeTwentyThreeLayer_PSCPdS_S_S_S_S_S_
	.size	_Z27executeTwentyThreeLayer_PSCPdS_S_S_S_S_S_, 8

	.type	_Z26executeTwentyFourLayer_DSCPdS_S_S_S_S_S_,@object # @_Z26executeTwentyFourLayer_DSCPdS_S_S_S_S_S_
	.globl	_Z26executeTwentyFourLayer_DSCPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z26executeTwentyFourLayer_DSCPdS_S_S_S_S_S_:
	.quad	_Z41__device_stub__executeTwentyFourLayer_DSCPdS_S_S_S_S_S_
	.size	_Z26executeTwentyFourLayer_DSCPdS_S_S_S_S_S_, 8

	.type	_Z26executeTwentyFiveLayer_PSCPdS_S_S_S_S_S_,@object # @_Z26executeTwentyFiveLayer_PSCPdS_S_S_S_S_S_
	.globl	_Z26executeTwentyFiveLayer_PSCPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z26executeTwentyFiveLayer_PSCPdS_S_S_S_S_S_:
	.quad	_Z41__device_stub__executeTwentyFiveLayer_PSCPdS_S_S_S_S_S_
	.size	_Z26executeTwentyFiveLayer_PSCPdS_S_S_S_S_S_, 8

	.type	_Z25executeTwentySixLayer_DSCPdS_S_S_S_S_S_,@object # @_Z25executeTwentySixLayer_DSCPdS_S_S_S_S_S_
	.globl	_Z25executeTwentySixLayer_DSCPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z25executeTwentySixLayer_DSCPdS_S_S_S_S_S_:
	.quad	_Z40__device_stub__executeTwentySixLayer_DSCPdS_S_S_S_S_S_
	.size	_Z25executeTwentySixLayer_DSCPdS_S_S_S_S_S_, 8

	.type	_Z27executeTwentySevenLayer_PSCPdS_S_S_S_S_S_,@object # @_Z27executeTwentySevenLayer_PSCPdS_S_S_S_S_S_
	.globl	_Z27executeTwentySevenLayer_PSCPdS_S_S_S_S_S_
	.p2align	3, 0x0
_Z27executeTwentySevenLayer_PSCPdS_S_S_S_S_S_:
	.quad	_Z42__device_stub__executeTwentySevenLayer_PSCPdS_S_S_S_S_S_
	.size	_Z27executeTwentySevenLayer_PSCPdS_S_S_S_S_S_, 8

	.type	_Z34executeTwentyEightLayer_AvgPoolingPdS_,@object # @_Z34executeTwentyEightLayer_AvgPoolingPdS_
	.globl	_Z34executeTwentyEightLayer_AvgPoolingPdS_
	.p2align	3, 0x0
_Z34executeTwentyEightLayer_AvgPoolingPdS_:
	.quad	_Z49__device_stub__executeTwentyEightLayer_AvgPoolingPdS_
	.size	_Z34executeTwentyEightLayer_AvgPoolingPdS_, 8

	.type	_Z37executeTwentyNineLayer_FullyConnectedPdS_S_S_,@object # @_Z37executeTwentyNineLayer_FullyConnectedPdS_S_S_
	.globl	_Z37executeTwentyNineLayer_FullyConnectedPdS_S_S_
	.p2align	3, 0x0
_Z37executeTwentyNineLayer_FullyConnectedPdS_S_S_:
	.quad	_Z52__device_stub__executeTwentyNineLayer_FullyConnectedPdS_S_S_
	.size	_Z37executeTwentyNineLayer_FullyConnectedPdS_S_S_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z30executeFirstLayer_CONV3D_partAPdS_S_S_S_S_S_"
	.size	.L__unnamed_1, 49

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z30executeFirstLayer_CONV3D_partBPdS_S_S_S_S_S_"
	.size	.L__unnamed_2, 49

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z30executeFirstLayer_CONV3D_partCPdS_S_S_S_S_S_"
	.size	.L__unnamed_3, 49

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z28executeSecondLayer_DSC_partAPdS_S_S_S_S_S_"
	.size	.L__unnamed_4, 47

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z28executeSecondLayer_DSC_partBPdS_S_S_S_S_S_"
	.size	.L__unnamed_5, 47

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_Z28executeSecondLayer_DSC_partCPdS_S_S_S_S_S_"
	.size	.L__unnamed_6, 47

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"_Z27executeThirdLayer_PSC_partAPdS_S_S_S_S_S_"
	.size	.L__unnamed_7, 46

	.type	.L__unnamed_8,@object           # @7
.L__unnamed_8:
	.asciz	"_Z27executeThirdLayer_PSC_partBPdS_S_S_S_S_S_"
	.size	.L__unnamed_8, 46

	.type	.L__unnamed_9,@object           # @8
.L__unnamed_9:
	.asciz	"_Z27executeThirdLayer_PSC_partCPdS_S_S_S_S_S_"
	.size	.L__unnamed_9, 46

	.type	.L__unnamed_10,@object          # @9
.L__unnamed_10:
	.asciz	"_Z28executeFourthLayer_DSC_partAPdS_S_S_S_S_S_"
	.size	.L__unnamed_10, 47

	.type	.L__unnamed_11,@object          # @10
.L__unnamed_11:
	.asciz	"_Z28executeFourthLayer_DSC_partBPdS_S_S_S_S_S_"
	.size	.L__unnamed_11, 47

	.type	.L__unnamed_12,@object          # @11
.L__unnamed_12:
	.asciz	"_Z28executeFourthLayer_DSC_partCPdS_S_S_S_S_S_"
	.size	.L__unnamed_12, 47

	.type	.L__unnamed_13,@object          # @12
.L__unnamed_13:
	.asciz	"_Z28executeFourthLayer_DSC_partDPdS_S_S_S_S_S_"
	.size	.L__unnamed_13, 47

	.type	.L__unnamed_14,@object          # @13
.L__unnamed_14:
	.asciz	"_Z27executeFifthLayer_PSC_partAPdS_S_S_S_S_S_"
	.size	.L__unnamed_14, 46

	.type	.L__unnamed_15,@object          # @14
.L__unnamed_15:
	.asciz	"_Z27executeFifthLayer_PSC_partBPdS_S_S_S_S_S_"
	.size	.L__unnamed_15, 46

	.type	.L__unnamed_16,@object          # @15
.L__unnamed_16:
	.asciz	"_Z27executeFifthLayer_PSC_partCPdS_S_S_S_S_S_"
	.size	.L__unnamed_16, 46

	.type	.L__unnamed_17,@object          # @16
.L__unnamed_17:
	.asciz	"_Z27executeFifthLayer_PSC_partDPdS_S_S_S_S_S_"
	.size	.L__unnamed_17, 46

	.type	.L__unnamed_18,@object          # @17
.L__unnamed_18:
	.asciz	"_Z27executeSixthLayer_DSC_partAPdS_S_S_S_S_S_"
	.size	.L__unnamed_18, 46

	.type	.L__unnamed_19,@object          # @18
.L__unnamed_19:
	.asciz	"_Z27executeSixthLayer_DSC_partBPdS_S_S_S_S_S_"
	.size	.L__unnamed_19, 46

	.type	.L__unnamed_20,@object          # @19
.L__unnamed_20:
	.asciz	"_Z27executeSixthLayer_DSC_partCPdS_S_S_S_S_S_"
	.size	.L__unnamed_20, 46

	.type	.L__unnamed_21,@object          # @20
.L__unnamed_21:
	.asciz	"_Z27executeSixthLayer_DSC_partDPdS_S_S_S_S_S_"
	.size	.L__unnamed_21, 46

	.type	.L__unnamed_22,@object          # @21
.L__unnamed_22:
	.asciz	"_Z29executeSeventhLayer_PSC_partAPdS_S_S_S_S_S_"
	.size	.L__unnamed_22, 48

	.type	.L__unnamed_23,@object          # @22
.L__unnamed_23:
	.asciz	"_Z29executeSeventhLayer_PSC_partBPdS_S_S_S_S_S_"
	.size	.L__unnamed_23, 48

	.type	.L__unnamed_24,@object          # @23
.L__unnamed_24:
	.asciz	"_Z29executeSeventhLayer_PSC_partCPdS_S_S_S_S_S_"
	.size	.L__unnamed_24, 48

	.type	.L__unnamed_25,@object          # @24
.L__unnamed_25:
	.asciz	"_Z29executeSeventhLayer_PSC_partDPdS_S_S_S_S_S_"
	.size	.L__unnamed_25, 48

	.type	.L__unnamed_26,@object          # @25
.L__unnamed_26:
	.asciz	"_Z22executeEighthLayer_DSCPdS_S_S_S_S_S_"
	.size	.L__unnamed_26, 41

	.type	.L__unnamed_27,@object          # @26
.L__unnamed_27:
	.asciz	"_Z21executeNinthLayer_PSCPdS_S_S_S_S_S_"
	.size	.L__unnamed_27, 40

	.type	.L__unnamed_28,@object          # @27
.L__unnamed_28:
	.asciz	"_Z21executeTenthLayer_DSCPdS_S_S_S_S_S_"
	.size	.L__unnamed_28, 40

	.type	.L__unnamed_29,@object          # @28
.L__unnamed_29:
	.asciz	"_Z24executeEleventhLayer_PSCPdS_S_S_S_S_S_"
	.size	.L__unnamed_29, 43

	.type	.L__unnamed_30,@object          # @29
.L__unnamed_30:
	.asciz	"_Z23executeTwelfthLayer_DSCPdS_S_S_S_S_S_"
	.size	.L__unnamed_30, 42

	.type	.L__unnamed_31,@object          # @30
.L__unnamed_31:
	.asciz	"_Z26executeThirteenthLayer_PSCPdS_S_S_S_S_S_"
	.size	.L__unnamed_31, 45

	.type	.L__unnamed_32,@object          # @31
.L__unnamed_32:
	.asciz	"_Z26executeFourteenthLayer_DSCPdS_S_S_S_S_S_"
	.size	.L__unnamed_32, 45

	.type	.L__unnamed_33,@object          # @32
.L__unnamed_33:
	.asciz	"_Z25executeFifteenthLayer_PSCPdS_S_S_S_S_S_"
	.size	.L__unnamed_33, 44

	.type	.L__unnamed_34,@object          # @33
.L__unnamed_34:
	.asciz	"_Z25executeSixteenthLayer_DSCPdS_S_S_S_S_S_"
	.size	.L__unnamed_34, 44

	.type	.L__unnamed_35,@object          # @34
.L__unnamed_35:
	.asciz	"_Z27executeSeventeenthLayer_PSCPdS_S_S_S_S_S_"
	.size	.L__unnamed_35, 46

	.type	.L__unnamed_36,@object          # @35
.L__unnamed_36:
	.asciz	"_Z26executeEighteenthLayer_DSCPdS_S_S_S_S_S_"
	.size	.L__unnamed_36, 45

	.type	.L__unnamed_37,@object          # @36
.L__unnamed_37:
	.asciz	"_Z26executeNineteenthLayer_PSCPdS_S_S_S_S_S_"
	.size	.L__unnamed_37, 45

	.type	.L__unnamed_38,@object          # @37
.L__unnamed_38:
	.asciz	"_Z22executeTwentyLayer_DSCPdS_S_S_S_S_S_"
	.size	.L__unnamed_38, 41

	.type	.L__unnamed_39,@object          # @38
.L__unnamed_39:
	.asciz	"_Z25executeTwentyOneLayer_PSCPdS_S_S_S_S_S_"
	.size	.L__unnamed_39, 44

	.type	.L__unnamed_40,@object          # @39
.L__unnamed_40:
	.asciz	"_Z25executeTwentyTwoLayer_DSCPdS_S_S_S_S_S_"
	.size	.L__unnamed_40, 44

	.type	.L__unnamed_41,@object          # @40
.L__unnamed_41:
	.asciz	"_Z27executeTwentyThreeLayer_PSCPdS_S_S_S_S_S_"
	.size	.L__unnamed_41, 46

	.type	.L__unnamed_42,@object          # @41
.L__unnamed_42:
	.asciz	"_Z26executeTwentyFourLayer_DSCPdS_S_S_S_S_S_"
	.size	.L__unnamed_42, 45

	.type	.L__unnamed_43,@object          # @42
.L__unnamed_43:
	.asciz	"_Z26executeTwentyFiveLayer_PSCPdS_S_S_S_S_S_"
	.size	.L__unnamed_43, 45

	.type	.L__unnamed_44,@object          # @43
.L__unnamed_44:
	.asciz	"_Z25executeTwentySixLayer_DSCPdS_S_S_S_S_S_"
	.size	.L__unnamed_44, 44

	.type	.L__unnamed_45,@object          # @44
.L__unnamed_45:
	.asciz	"_Z27executeTwentySevenLayer_PSCPdS_S_S_S_S_S_"
	.size	.L__unnamed_45, 46

	.type	.L__unnamed_46,@object          # @45
.L__unnamed_46:
	.asciz	"_Z34executeTwentyEightLayer_AvgPoolingPdS_"
	.size	.L__unnamed_46, 43

	.type	.L__unnamed_47,@object          # @46
.L__unnamed_47:
	.asciz	"_Z37executeTwentyNineLayer_FullyConnectedPdS_S_S_"
	.size	.L__unnamed_47, 50

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z45__device_stub__executeFirstLayer_CONV3D_partAPdS_S_S_S_S_S_
	.addrsig_sym _Z45__device_stub__executeFirstLayer_CONV3D_partBPdS_S_S_S_S_S_
	.addrsig_sym _Z45__device_stub__executeFirstLayer_CONV3D_partCPdS_S_S_S_S_S_
	.addrsig_sym _Z43__device_stub__executeSecondLayer_DSC_partAPdS_S_S_S_S_S_
	.addrsig_sym _Z43__device_stub__executeSecondLayer_DSC_partBPdS_S_S_S_S_S_
	.addrsig_sym _Z43__device_stub__executeSecondLayer_DSC_partCPdS_S_S_S_S_S_
	.addrsig_sym _Z42__device_stub__executeThirdLayer_PSC_partAPdS_S_S_S_S_S_
	.addrsig_sym _Z42__device_stub__executeThirdLayer_PSC_partBPdS_S_S_S_S_S_
	.addrsig_sym _Z42__device_stub__executeThirdLayer_PSC_partCPdS_S_S_S_S_S_
	.addrsig_sym _Z43__device_stub__executeFourthLayer_DSC_partAPdS_S_S_S_S_S_
	.addrsig_sym _Z43__device_stub__executeFourthLayer_DSC_partBPdS_S_S_S_S_S_
	.addrsig_sym _Z43__device_stub__executeFourthLayer_DSC_partCPdS_S_S_S_S_S_
	.addrsig_sym _Z43__device_stub__executeFourthLayer_DSC_partDPdS_S_S_S_S_S_
	.addrsig_sym _Z42__device_stub__executeFifthLayer_PSC_partAPdS_S_S_S_S_S_
	.addrsig_sym _Z42__device_stub__executeFifthLayer_PSC_partBPdS_S_S_S_S_S_
	.addrsig_sym _Z42__device_stub__executeFifthLayer_PSC_partCPdS_S_S_S_S_S_
	.addrsig_sym _Z42__device_stub__executeFifthLayer_PSC_partDPdS_S_S_S_S_S_
	.addrsig_sym _Z42__device_stub__executeSixthLayer_DSC_partAPdS_S_S_S_S_S_
	.addrsig_sym _Z42__device_stub__executeSixthLayer_DSC_partBPdS_S_S_S_S_S_
	.addrsig_sym _Z42__device_stub__executeSixthLayer_DSC_partCPdS_S_S_S_S_S_
	.addrsig_sym _Z42__device_stub__executeSixthLayer_DSC_partDPdS_S_S_S_S_S_
	.addrsig_sym _Z44__device_stub__executeSeventhLayer_PSC_partAPdS_S_S_S_S_S_
	.addrsig_sym _Z44__device_stub__executeSeventhLayer_PSC_partBPdS_S_S_S_S_S_
	.addrsig_sym _Z44__device_stub__executeSeventhLayer_PSC_partCPdS_S_S_S_S_S_
	.addrsig_sym _Z44__device_stub__executeSeventhLayer_PSC_partDPdS_S_S_S_S_S_
	.addrsig_sym _Z37__device_stub__executeEighthLayer_DSCPdS_S_S_S_S_S_
	.addrsig_sym _Z36__device_stub__executeNinthLayer_PSCPdS_S_S_S_S_S_
	.addrsig_sym _Z36__device_stub__executeTenthLayer_DSCPdS_S_S_S_S_S_
	.addrsig_sym _Z39__device_stub__executeEleventhLayer_PSCPdS_S_S_S_S_S_
	.addrsig_sym _Z38__device_stub__executeTwelfthLayer_DSCPdS_S_S_S_S_S_
	.addrsig_sym _Z41__device_stub__executeThirteenthLayer_PSCPdS_S_S_S_S_S_
	.addrsig_sym _Z41__device_stub__executeFourteenthLayer_DSCPdS_S_S_S_S_S_
	.addrsig_sym _Z40__device_stub__executeFifteenthLayer_PSCPdS_S_S_S_S_S_
	.addrsig_sym _Z40__device_stub__executeSixteenthLayer_DSCPdS_S_S_S_S_S_
	.addrsig_sym _Z42__device_stub__executeSeventeenthLayer_PSCPdS_S_S_S_S_S_
	.addrsig_sym _Z41__device_stub__executeEighteenthLayer_DSCPdS_S_S_S_S_S_
	.addrsig_sym _Z41__device_stub__executeNineteenthLayer_PSCPdS_S_S_S_S_S_
	.addrsig_sym _Z37__device_stub__executeTwentyLayer_DSCPdS_S_S_S_S_S_
	.addrsig_sym _Z40__device_stub__executeTwentyOneLayer_PSCPdS_S_S_S_S_S_
	.addrsig_sym _Z40__device_stub__executeTwentyTwoLayer_DSCPdS_S_S_S_S_S_
	.addrsig_sym _Z42__device_stub__executeTwentyThreeLayer_PSCPdS_S_S_S_S_S_
	.addrsig_sym _Z41__device_stub__executeTwentyFourLayer_DSCPdS_S_S_S_S_S_
	.addrsig_sym _Z41__device_stub__executeTwentyFiveLayer_PSCPdS_S_S_S_S_S_
	.addrsig_sym _Z40__device_stub__executeTwentySixLayer_DSCPdS_S_S_S_S_S_
	.addrsig_sym _Z42__device_stub__executeTwentySevenLayer_PSCPdS_S_S_S_S_S_
	.addrsig_sym _Z49__device_stub__executeTwentyEightLayer_AvgPoolingPdS_
	.addrsig_sym _Z52__device_stub__executeTwentyNineLayer_FullyConnectedPdS_S_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z30executeFirstLayer_CONV3D_partAPdS_S_S_S_S_S_
	.addrsig_sym _Z30executeFirstLayer_CONV3D_partBPdS_S_S_S_S_S_
	.addrsig_sym _Z30executeFirstLayer_CONV3D_partCPdS_S_S_S_S_S_
	.addrsig_sym _Z28executeSecondLayer_DSC_partAPdS_S_S_S_S_S_
	.addrsig_sym _Z28executeSecondLayer_DSC_partBPdS_S_S_S_S_S_
	.addrsig_sym _Z28executeSecondLayer_DSC_partCPdS_S_S_S_S_S_
	.addrsig_sym _Z27executeThirdLayer_PSC_partAPdS_S_S_S_S_S_
	.addrsig_sym _Z27executeThirdLayer_PSC_partBPdS_S_S_S_S_S_
	.addrsig_sym _Z27executeThirdLayer_PSC_partCPdS_S_S_S_S_S_
	.addrsig_sym _Z28executeFourthLayer_DSC_partAPdS_S_S_S_S_S_
	.addrsig_sym _Z28executeFourthLayer_DSC_partBPdS_S_S_S_S_S_
	.addrsig_sym _Z28executeFourthLayer_DSC_partCPdS_S_S_S_S_S_
	.addrsig_sym _Z28executeFourthLayer_DSC_partDPdS_S_S_S_S_S_
	.addrsig_sym _Z27executeFifthLayer_PSC_partAPdS_S_S_S_S_S_
	.addrsig_sym _Z27executeFifthLayer_PSC_partBPdS_S_S_S_S_S_
	.addrsig_sym _Z27executeFifthLayer_PSC_partCPdS_S_S_S_S_S_
	.addrsig_sym _Z27executeFifthLayer_PSC_partDPdS_S_S_S_S_S_
	.addrsig_sym _Z27executeSixthLayer_DSC_partAPdS_S_S_S_S_S_
	.addrsig_sym _Z27executeSixthLayer_DSC_partBPdS_S_S_S_S_S_
	.addrsig_sym _Z27executeSixthLayer_DSC_partCPdS_S_S_S_S_S_
	.addrsig_sym _Z27executeSixthLayer_DSC_partDPdS_S_S_S_S_S_
	.addrsig_sym _Z29executeSeventhLayer_PSC_partAPdS_S_S_S_S_S_
	.addrsig_sym _Z29executeSeventhLayer_PSC_partBPdS_S_S_S_S_S_
	.addrsig_sym _Z29executeSeventhLayer_PSC_partCPdS_S_S_S_S_S_
	.addrsig_sym _Z29executeSeventhLayer_PSC_partDPdS_S_S_S_S_S_
	.addrsig_sym _Z22executeEighthLayer_DSCPdS_S_S_S_S_S_
	.addrsig_sym _Z21executeNinthLayer_PSCPdS_S_S_S_S_S_
	.addrsig_sym _Z21executeTenthLayer_DSCPdS_S_S_S_S_S_
	.addrsig_sym _Z24executeEleventhLayer_PSCPdS_S_S_S_S_S_
	.addrsig_sym _Z23executeTwelfthLayer_DSCPdS_S_S_S_S_S_
	.addrsig_sym _Z26executeThirteenthLayer_PSCPdS_S_S_S_S_S_
	.addrsig_sym _Z26executeFourteenthLayer_DSCPdS_S_S_S_S_S_
	.addrsig_sym _Z25executeFifteenthLayer_PSCPdS_S_S_S_S_S_
	.addrsig_sym _Z25executeSixteenthLayer_DSCPdS_S_S_S_S_S_
	.addrsig_sym _Z27executeSeventeenthLayer_PSCPdS_S_S_S_S_S_
	.addrsig_sym _Z26executeEighteenthLayer_DSCPdS_S_S_S_S_S_
	.addrsig_sym _Z26executeNineteenthLayer_PSCPdS_S_S_S_S_S_
	.addrsig_sym _Z22executeTwentyLayer_DSCPdS_S_S_S_S_S_
	.addrsig_sym _Z25executeTwentyOneLayer_PSCPdS_S_S_S_S_S_
	.addrsig_sym _Z25executeTwentyTwoLayer_DSCPdS_S_S_S_S_S_
	.addrsig_sym _Z27executeTwentyThreeLayer_PSCPdS_S_S_S_S_S_
	.addrsig_sym _Z26executeTwentyFourLayer_DSCPdS_S_S_S_S_S_
	.addrsig_sym _Z26executeTwentyFiveLayer_PSCPdS_S_S_S_S_S_
	.addrsig_sym _Z25executeTwentySixLayer_DSCPdS_S_S_S_S_S_
	.addrsig_sym _Z27executeTwentySevenLayer_PSCPdS_S_S_S_S_S_
	.addrsig_sym _Z34executeTwentyEightLayer_AvgPoolingPdS_
	.addrsig_sym _Z37executeTwentyNineLayer_FullyConnectedPdS_S_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z30executeFirstLayer_CONV3D_partAPdS_S_S_S_S_S_ ; -- Begin function _Z30executeFirstLayer_CONV3D_partAPdS_S_S_S_S_S_
	.globl	_Z30executeFirstLayer_CONV3D_partAPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z30executeFirstLayer_CONV3D_partAPdS_S_S_S_S_S_,@function
_Z30executeFirstLayer_CONV3D_partAPdS_S_S_S_S_S_: ; @_Z30executeFirstLayer_CONV3D_partAPdS_S_S_S_S_S_
; %bb.0:
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b256 s[16:23], s[0:1], 0x20
	v_bfe_u32 v5, v0, 10, 10
	v_and_b32_e32 v6, 0x3ff, v0
	s_mul_i32 s1, s14, 0x3840
	s_lshl_b32 s3, s15, 6
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	v_lshlrev_b32_e32 v3, 1, v5
	v_mul_u32_u24_e32 v2, 0x1c2, v6
	s_mul_i32 s0, s13, 27
	s_add_i32 s12, s1, s3
	s_mov_b32 s2, s13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	v_add3_u32 v2, s12, v2, v3
	s_waitcnt lgkmcnt(0)
	s_add_u32 s3, s4, 8
	s_addc_u32 s4, s5, 0
	s_ashr_i32 s1, s0, 31
	s_lshl_b64 s[0:1], s[0:1], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s5, s6, s0
	s_addc_u32 s6, s7, s1
	s_mov_b32 s7, 0
.LBB0_1:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_2 Depth 2
	v_ashrrev_i32_e32 v3, 31, v2
	s_mov_b64 s[0:1], 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 3, v[2:3]
	v_add_co_u32 v3, vcc_lo, s3, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s4, v4, vcc_lo
.LBB0_2:                                ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_clause 0x1
	global_load_b128 v[7:10], v[3:4], off offset:-8
	global_load_b64 v[11:12], v[3:4], off offset:8
	s_add_u32 s12, s5, s0
	s_addc_u32 s13, s6, s1
	s_clause 0x1
	s_load_b128 s[24:27], s[12:13], 0x0
	s_load_b64 s[12:13], s[12:13], 0x10
	v_add_co_u32 v3, vcc_lo, 0x708, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s0, 0x48
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_mul_f64 v[9:10], v[9:10], s[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], v[7:8], s[24:25], v[9:10]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[7:8], v[11:12], s[12:13], v[7:8]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], v[7:8]
	s_cbranch_scc0 .LBB0_2
; %bb.3:                                ;   in Loop: Header=BB0_1 Depth=1
	s_add_i32 s7, s7, 1
	v_add_nc_u32_e32 v2, 0xc5c1, v2
	s_add_u32 s5, s5, 0x48
	s_addc_u32 s6, s6, 0
	s_cmp_eq_u32 s7, 3
	s_cbranch_scc0 .LBB0_1
; %bb.4:
	s_ashr_i32 s3, s2, 31
	s_mulk_i32 s14, 0xe40
	s_lshl_b64 s[0:1], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_add_u32 s4, s10, s0
	s_addc_u32 s5, s11, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[0:1], v[0:1], -s[4:5]
	s_add_u32 s4, s16, s0
	s_addc_u32 s5, s17, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[2:3], null, s[4:5], s[4:5], v[0:1]
	v_div_scale_f64 v[11:12], vcc_lo, v[0:1], s[4:5], v[0:1]
	v_rcp_f64_e32 v[7:8], v[2:3]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[9:10], -v[2:3], v[7:8], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	v_fma_f64 v[9:10], -v[2:3], v[7:8], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	v_mul_f64 v[9:10], v[11:12], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[2:3], -v[2:3], v[9:10], v[11:12]
	v_div_fmas_f64 v[2:3], v[2:3], v[7:8], v[9:10]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[0:1], v[2:3], s[4:5], v[0:1]
	s_add_u32 s4, s18, s0
	s_addc_u32 s5, s19, s1
	s_add_u32 s0, s20, s0
	s_addc_u32 s1, s21, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	v_mul_u32_u24_e32 v2, 0x72, v6
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[0:1], v[0:1], s[4:5], s[0:1]
	s_mul_i32 s0, s2, 0x32c4
	s_lshl_b32 s1, s15, 5
	s_add_i32 s0, s1, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s14
	v_add3_u32 v2, s0, v5, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, 0, v1 :: v_dual_cndmask_b32 v0, 0, v0
	v_cmp_nlt_f64_e32 vcc_lo, 0x40180000, v[0:1]
	v_cndmask_b32_e32 v1, 0x40180000, v1, vcc_lo
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	global_store_b64 v[2:3], v[0:1], off offset:920
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z30executeFirstLayer_CONV3D_partAPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 28
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z30executeFirstLayer_CONV3D_partAPdS_S_S_S_S_S_, .Lfunc_end0-_Z30executeFirstLayer_CONV3D_partAPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 668
; NumSgprs: 30
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 30
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z30executeFirstLayer_CONV3D_partBPdS_S_S_S_S_S_ ; -- Begin function _Z30executeFirstLayer_CONV3D_partBPdS_S_S_S_S_S_
	.globl	_Z30executeFirstLayer_CONV3D_partBPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z30executeFirstLayer_CONV3D_partBPdS_S_S_S_S_S_,@function
_Z30executeFirstLayer_CONV3D_partBPdS_S_S_S_S_S_: ; @_Z30executeFirstLayer_CONV3D_partBPdS_S_S_S_S_S_
; %bb.0:
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b256 s[16:23], s[0:1], 0x20
	v_and_b32_e32 v5, 0x3ff, v0
	v_bfe_u32 v6, v0, 10, 10
	v_mov_b32_e32 v0, 0
	s_mul_i32 s1, s15, 0x1c20
	s_mul_i32 s0, s14, 27
	v_mul_u32_u24_e32 v2, 0x1c2, v5
	v_lshlrev_b32_e32 v3, 1, v6
	s_add_i32 s12, s1, 0xc0
	v_mov_b32_e32 v1, 0
	s_mov_b32 s2, s15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	v_add3_u32 v2, s12, v2, v3
	s_waitcnt lgkmcnt(0)
	s_add_u32 s3, s4, 8
	s_addc_u32 s4, s5, 0
	s_ashr_i32 s1, s0, 31
	s_lshl_b64 s[0:1], s[0:1], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s5, s6, s0
	s_addc_u32 s6, s7, s1
	s_mov_b32 s7, 0
.LBB1_1:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_2 Depth 2
	v_ashrrev_i32_e32 v3, 31, v2
	s_mov_b64 s[0:1], 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 3, v[2:3]
	v_add_co_u32 v3, vcc_lo, s3, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s4, v4, vcc_lo
.LBB1_2:                                ;   Parent Loop BB1_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_clause 0x1
	global_load_b128 v[7:10], v[3:4], off offset:-8
	global_load_b64 v[11:12], v[3:4], off offset:8
	s_add_u32 s12, s5, s0
	s_addc_u32 s13, s6, s1
	s_clause 0x1
	s_load_b128 s[24:27], s[12:13], 0x0
	s_load_b64 s[12:13], s[12:13], 0x10
	v_add_co_u32 v3, vcc_lo, 0x708, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s0, 0x48
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_mul_f64 v[9:10], v[9:10], s[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], v[7:8], s[24:25], v[9:10]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[7:8], v[11:12], s[12:13], v[7:8]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], v[7:8]
	s_cbranch_scc0 .LBB1_2
; %bb.3:                                ;   in Loop: Header=BB1_1 Depth=1
	s_add_i32 s7, s7, 1
	v_add_nc_u32_e32 v2, 0xc5c1, v2
	s_add_u32 s5, s5, 0x48
	s_addc_u32 s6, s6, 0
	s_cmp_eq_u32 s7, 3
	s_cbranch_scc0 .LBB1_1
; %bb.4:
	s_ashr_i32 s15, s14, 31
	s_mulk_i32 s2, 0x720
	s_lshl_b64 s[0:1], s[14:15], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_add_u32 s4, s10, s0
	s_addc_u32 s5, s11, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[0:1], v[0:1], -s[4:5]
	s_add_u32 s4, s16, s0
	s_addc_u32 s5, s17, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[2:3], null, s[4:5], s[4:5], v[0:1]
	v_div_scale_f64 v[11:12], vcc_lo, v[0:1], s[4:5], v[0:1]
	v_rcp_f64_e32 v[7:8], v[2:3]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[9:10], -v[2:3], v[7:8], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	v_fma_f64 v[9:10], -v[2:3], v[7:8], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	v_mul_f64 v[9:10], v[11:12], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[2:3], -v[2:3], v[9:10], v[11:12]
	v_div_fmas_f64 v[2:3], v[2:3], v[7:8], v[9:10]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[0:1], v[2:3], s[4:5], v[0:1]
	s_add_u32 s4, s18, s0
	s_addc_u32 s5, s19, s1
	s_add_u32 s0, s20, s0
	s_addc_u32 s1, s21, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	v_mul_u32_u24_e32 v2, 0x72, v5
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[0:1], v[0:1], s[4:5], s[0:1]
	s_mul_i32 s0, s14, 0x32c4
	v_add3_u32 v3, s0, s2, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v2, v3, v2, 0x60
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, 0, v1 :: v_dual_cndmask_b32 v0, 0, v0
	v_cmp_nlt_f64_e32 vcc_lo, 0x40180000, v[0:1]
	v_cndmask_b32_e32 v1, 0x40180000, v1, vcc_lo
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	global_store_b64 v[2:3], v[0:1], off offset:920
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z30executeFirstLayer_CONV3D_partBPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 28
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z30executeFirstLayer_CONV3D_partBPdS_S_S_S_S_S_, .Lfunc_end1-_Z30executeFirstLayer_CONV3D_partBPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 664
; NumSgprs: 30
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 30
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z30executeFirstLayer_CONV3D_partCPdS_S_S_S_S_S_ ; -- Begin function _Z30executeFirstLayer_CONV3D_partCPdS_S_S_S_S_S_
	.globl	_Z30executeFirstLayer_CONV3D_partCPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z30executeFirstLayer_CONV3D_partCPdS_S_S_S_S_S_,@function
_Z30executeFirstLayer_CONV3D_partCPdS_S_S_S_S_S_: ; @_Z30executeFirstLayer_CONV3D_partCPdS_S_S_S_S_S_
; %bb.0:
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b256 s[16:23], s[0:1], 0x20
	v_and_b32_e32 v5, 0x3ff, v0
	v_bfe_u32 v6, v0, 10, 10
	v_mov_b32_e32 v0, 0
	s_lshl_b32 s1, s15, 5
	s_mul_i32 s0, s14, 27
	v_mul_u32_u24_e32 v2, 0x1c2, v5
	v_lshlrev_b32_e32 v3, 1, v6
	s_add_i32 s12, s1, 0xa8c0
	v_mov_b32_e32 v1, 0
	s_mov_b32 s2, s15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	v_add3_u32 v2, s12, v2, v3
	s_waitcnt lgkmcnt(0)
	s_add_u32 s3, s4, 8
	s_addc_u32 s4, s5, 0
	s_ashr_i32 s1, s0, 31
	s_lshl_b64 s[0:1], s[0:1], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s5, s6, s0
	s_addc_u32 s6, s7, s1
	s_mov_b32 s7, 0
.LBB2_1:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_2 Depth 2
	v_ashrrev_i32_e32 v3, 31, v2
	s_mov_b64 s[0:1], 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 3, v[2:3]
	v_add_co_u32 v3, vcc_lo, s3, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s4, v4, vcc_lo
.LBB2_2:                                ;   Parent Loop BB2_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_clause 0x1
	global_load_b128 v[7:10], v[3:4], off offset:-8
	global_load_b64 v[11:12], v[3:4], off offset:8
	s_add_u32 s12, s5, s0
	s_addc_u32 s13, s6, s1
	s_clause 0x1
	s_load_b128 s[24:27], s[12:13], 0x0
	s_load_b64 s[12:13], s[12:13], 0x10
	v_add_co_u32 v3, vcc_lo, 0x708, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s0, 0x48
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_mul_f64 v[9:10], v[9:10], s[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], v[7:8], s[24:25], v[9:10]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[7:8], v[11:12], s[12:13], v[7:8]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], v[7:8]
	s_cbranch_scc0 .LBB2_2
; %bb.3:                                ;   in Loop: Header=BB2_1 Depth=1
	s_add_i32 s7, s7, 1
	v_add_nc_u32_e32 v2, 0xc5c1, v2
	s_add_u32 s5, s5, 0x48
	s_addc_u32 s6, s6, 0
	s_cmp_eq_u32 s7, 3
	s_cbranch_scc0 .LBB2_1
; %bb.4:
	s_ashr_i32 s15, s14, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[14:15], 3
	s_add_u32 s4, s10, s0
	s_addc_u32 s5, s11, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], -s[4:5]
	s_add_u32 s4, s16, s0
	s_addc_u32 s5, s17, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_div_scale_f64 v[2:3], null, s[4:5], s[4:5], v[0:1]
	v_div_scale_f64 v[11:12], vcc_lo, v[0:1], s[4:5], v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[7:8], v[2:3]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[9:10], -v[2:3], v[7:8], 1.0
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], -v[2:3], v[7:8], 1.0
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[9:10], v[11:12], v[7:8]
	v_fma_f64 v[2:3], -v[2:3], v[9:10], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[2:3], v[2:3], v[7:8], v[9:10]
	v_div_fixup_f64 v[0:1], v[2:3], s[4:5], v[0:1]
	s_add_u32 s4, s18, s0
	s_addc_u32 s5, s19, s1
	s_add_u32 s0, s20, s0
	s_addc_u32 s1, s21, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	v_mul_u32_u24_e32 v2, 0x72, v5
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[0:1], v[0:1], s[4:5], s[0:1]
	s_mul_i32 s0, s14, 0x32c4
	s_lshl_b32 s1, s2, 4
	v_add3_u32 v3, s1, s0, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v2, v3, v2, 0x2ac0
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, 0, v1 :: v_dual_cndmask_b32 v0, 0, v0
	v_cmp_nlt_f64_e32 vcc_lo, 0x40180000, v[0:1]
	v_cndmask_b32_e32 v1, 0x40180000, v1, vcc_lo
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	global_store_b64 v[2:3], v[0:1], off offset:920
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z30executeFirstLayer_CONV3D_partCPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 28
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z30executeFirstLayer_CONV3D_partCPdS_S_S_S_S_S_, .Lfunc_end2-_Z30executeFirstLayer_CONV3D_partCPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 660
; NumSgprs: 30
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 30
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z28executeSecondLayer_DSC_partAPdS_S_S_S_S_S_ ; -- Begin function _Z28executeSecondLayer_DSC_partAPdS_S_S_S_S_S_
	.globl	_Z28executeSecondLayer_DSC_partAPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z28executeSecondLayer_DSC_partAPdS_S_S_S_S_S_,@function
_Z28executeSecondLayer_DSC_partAPdS_S_S_S_S_S_: ; @_Z28executeSecondLayer_DSC_partAPdS_S_S_S_S_S_
; %bb.0:
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b256 s[16:23], s[0:1], 0x20
	v_bfe_u32 v2, v0, 10, 10
	v_dual_mov_b32 v0, 0 :: v_dual_and_b32 v3, 0x3ff, v0
	s_mul_i32 s1, s14, 0xe40
	s_mul_i32 s3, s13, 0x32c4
	s_mul_i32 s0, s13, 9
	v_add3_u32 v4, s1, s3, v2
	v_mul_u32_u24_e32 v5, 0x72, v3
	s_ashr_i32 s1, s0, 31
	s_lshl_b32 s12, s15, 5
	s_lshl_b64 s[0:1], s[0:1], 3
	v_mov_b32_e32 v1, 0
	v_add3_u32 v4, v4, v5, s12
	s_mov_b32 s2, s13
	s_mov_b32 s3, 0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s0, s6
	s_addc_u32 s1, s1, s7
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB3_1:                                ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v5, s3, v4
	s_add_u32 s6, s0, -8
	s_addc_u32 s7, s1, -1
	s_addk_i32 s3, 0x72
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v6, vcc_lo
	s_clause 0x1
	global_load_b128 v[5:8], v[9:10], off
	global_load_b64 v[9:10], v[9:10], off offset:16
	s_clause 0x1
	s_load_b128 s[24:27], s[6:7], 0x0
	s_load_b64 s[6:7], s[0:1], 0x8
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s3, 0x156
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_mul_f64 v[7:8], v[7:8], s[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], v[5:6], s[24:25], v[7:8]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[5:6], v[9:10], s[6:7], v[5:6]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], v[5:6]
	s_cbranch_scc0 .LBB3_1
; %bb.2:
	s_ashr_i32 s3, s2, 31
	v_mul_u32_u24_e32 v3, 0x70, v3
	s_lshl_b64 s[0:1], s[2:3], 3
	s_mulk_i32 s14, 0xe00
	s_add_u32 s4, s10, s0
	s_addc_u32 s5, s11, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], -s[4:5]
	s_add_u32 s4, s16, s0
	s_addc_u32 s5, s17, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_div_scale_f64 v[4:5], null, s[4:5], s[4:5], v[0:1]
	v_div_scale_f64 v[10:11], vcc_lo, v[0:1], s[4:5], v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[6:7], v[4:5]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[8:9], v[10:11], v[6:7]
	v_fma_f64 v[4:5], -v[4:5], v[8:9], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9]
	v_div_fixup_f64 v[0:1], v[4:5], s[4:5], v[0:1]
	s_add_u32 s4, s18, s0
	s_addc_u32 s5, s19, s1
	s_add_u32 s0, s20, s0
	s_addc_u32 s1, s21, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[0:1], v[0:1], s[4:5], s[0:1]
	s_mul_i32 s0, s2, 0x3100
	s_add_i32 s0, s12, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s14
	v_add3_u32 v2, s0, v2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, 0, v1 :: v_dual_cndmask_b32 v0, 0, v0
	v_cmp_nlt_f64_e32 vcc_lo, 0x40180000, v[0:1]
	v_cndmask_b32_e32 v1, 0x40180000, v1, vcc_lo
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	global_store_b64 v[2:3], v[0:1], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z28executeSecondLayer_DSC_partAPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 28
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z28executeSecondLayer_DSC_partAPdS_S_S_S_S_S_, .Lfunc_end3-_Z28executeSecondLayer_DSC_partAPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 616
; NumSgprs: 30
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 30
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z28executeSecondLayer_DSC_partBPdS_S_S_S_S_S_ ; -- Begin function _Z28executeSecondLayer_DSC_partBPdS_S_S_S_S_S_
	.globl	_Z28executeSecondLayer_DSC_partBPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z28executeSecondLayer_DSC_partBPdS_S_S_S_S_S_,@function
_Z28executeSecondLayer_DSC_partBPdS_S_S_S_S_S_: ; @_Z28executeSecondLayer_DSC_partBPdS_S_S_S_S_S_
; %bb.0:
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b256 s[16:23], s[0:1], 0x20
	v_bfe_u32 v3, v0, 10, 10
	v_and_b32_e32 v2, 0x3ff, v0
	s_mul_i32 s3, s15, 0x720
	s_mul_i32 s1, s14, 0x32c4
	s_mul_i32 s0, s14, 9
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	v_add3_u32 v4, s3, s1, v3
	v_mul_u32_u24_e32 v5, 0x72, v2
	s_ashr_i32 s1, s0, 31
	s_mov_b32 s2, s15
	s_lshl_b64 s[0:1], s[0:1], 3
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v4, v4, v5, 0x60
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s0, s6
	s_addc_u32 s1, s1, s7
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_mov_b32 s6, 0
.LBB4_1:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v5, s6, v4
	s_add_u32 s12, s0, -8
	s_addc_u32 s13, s1, -1
	s_addk_i32 s6, 0x72
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	v_add_co_u32 v9, vcc_lo, s4, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v6, vcc_lo
	s_clause 0x1
	global_load_b128 v[5:8], v[9:10], off
	global_load_b64 v[9:10], v[9:10], off offset:16
	s_clause 0x1
	s_load_b128 s[24:27], s[12:13], 0x0
	s_load_b64 s[12:13], s[0:1], 0x8
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s6, 0x156
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_mul_f64 v[7:8], v[7:8], s[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], v[5:6], s[24:25], v[7:8]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[5:6], v[9:10], s[12:13], v[5:6]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], v[5:6]
	s_cbranch_scc0 .LBB4_1
; %bb.2:
	s_ashr_i32 s15, s14, 31
	v_mul_u32_u24_e32 v2, 0x70, v2
	s_lshl_b64 s[0:1], s[14:15], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_add_u32 s4, s10, s0
	s_addc_u32 s5, s11, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[0:1], v[0:1], -s[4:5]
	s_add_u32 s4, s16, s0
	s_addc_u32 s5, s17, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[4:5], null, s[4:5], s[4:5], v[0:1]
	v_div_scale_f64 v[10:11], vcc_lo, v[0:1], s[4:5], v[0:1]
	v_rcp_f64_e32 v[6:7], v[4:5]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_mul_f64 v[8:9], v[10:11], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], -v[4:5], v[8:9], v[10:11]
	v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[0:1], v[4:5], s[4:5], v[0:1]
	s_add_u32 s4, s18, s0
	s_addc_u32 s5, s19, s1
	s_add_u32 s0, s20, s0
	s_addc_u32 s1, s21, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[0:1], v[0:1], s[4:5], s[0:1]
	s_lshl_b32 s0, s2, 5
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, 0, v1 :: v_dual_cndmask_b32 v0, 0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_nlt_f64_e32 vcc_lo, 0x40180000, v[0:1]
	v_dual_cndmask_b32 v0, 0, v0 :: v_dual_add_nc_u32 v3, s3, v3
	v_subrev_nc_u32_e32 v3, s0, v3
	v_cndmask_b32_e32 v1, 0x40180000, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, 0x3100, s14, v[3:4]
	v_add3_u32 v2, v4, v2, 0x60
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	global_store_b64 v[2:3], v[0:1], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z28executeSecondLayer_DSC_partBPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 28
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z28executeSecondLayer_DSC_partBPdS_S_S_S_S_S_, .Lfunc_end4-_Z28executeSecondLayer_DSC_partBPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 640
; NumSgprs: 30
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 30
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z28executeSecondLayer_DSC_partCPdS_S_S_S_S_S_ ; -- Begin function _Z28executeSecondLayer_DSC_partCPdS_S_S_S_S_S_
	.globl	_Z28executeSecondLayer_DSC_partCPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z28executeSecondLayer_DSC_partCPdS_S_S_S_S_S_,@function
_Z28executeSecondLayer_DSC_partCPdS_S_S_S_S_S_: ; @_Z28executeSecondLayer_DSC_partCPdS_S_S_S_S_S_
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_and_b32_e32 v2, 0x3ff, v0
	s_load_b256 s[16:23], s[0:1], 0x20
	v_bfe_u32 v3, v0, 10, 10
	s_mul_i32 s1, s14, 0x32c4
	s_mul_i32 s0, s14, 9
	v_mul_u32_u24_e32 v0, 0x72, v2
	s_lshl_b32 s2, s15, 4
	s_mov_b32 s3, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v4, v3, s1, v0
	s_ashr_i32 s1, s0, 31
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	s_lshl_b64 s[0:1], s[0:1], 3
	v_add3_u32 v4, v4, s2, 0x2ac0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s0, s6
	s_addc_u32 s1, s1, s7
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB5_1:                                ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v5, s3, v4
	s_add_u32 s6, s0, -8
	s_addc_u32 s7, s1, -1
	s_addk_i32 s3, 0x72
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v6, vcc_lo
	s_clause 0x1
	global_load_b128 v[5:8], v[9:10], off
	global_load_b64 v[9:10], v[9:10], off offset:16
	s_clause 0x1
	s_load_b128 s[24:27], s[6:7], 0x0
	s_load_b64 s[6:7], s[0:1], 0x8
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s3, 0x156
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_mul_f64 v[7:8], v[7:8], s[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], v[5:6], s[24:25], v[7:8]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[5:6], v[9:10], s[6:7], v[5:6]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], v[5:6]
	s_cbranch_scc0 .LBB5_1
; %bb.2:
	s_ashr_i32 s15, s14, 31
	v_mul_u32_u24_e32 v2, 0x70, v2
	s_lshl_b64 s[0:1], s[14:15], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_add_u32 s4, s10, s0
	s_addc_u32 s5, s11, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[0:1], v[0:1], -s[4:5]
	s_add_u32 s4, s16, s0
	s_addc_u32 s5, s17, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[4:5], null, s[4:5], s[4:5], v[0:1]
	v_div_scale_f64 v[10:11], vcc_lo, v[0:1], s[4:5], v[0:1]
	v_rcp_f64_e32 v[6:7], v[4:5]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_mul_f64 v[8:9], v[10:11], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], -v[4:5], v[8:9], v[10:11]
	v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[0:1], v[4:5], s[4:5], v[0:1]
	s_add_u32 s4, s18, s0
	s_addc_u32 s5, s19, s1
	s_add_u32 s0, s20, s0
	s_addc_u32 s1, s21, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[0:1], v[0:1], s[4:5], s[0:1]
	s_mul_i32 s0, s14, 0x3100
	v_add3_u32 v3, s2, s0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v2, v3, v2, 0x2a00
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, 0, v1 :: v_dual_cndmask_b32 v0, 0, v0
	v_cmp_nlt_f64_e32 vcc_lo, 0x40180000, v[0:1]
	v_cndmask_b32_e32 v1, 0x40180000, v1, vcc_lo
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	global_store_b64 v[2:3], v[0:1], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z28executeSecondLayer_DSC_partCPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 28
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	_Z28executeSecondLayer_DSC_partCPdS_S_S_S_S_S_, .Lfunc_end5-_Z28executeSecondLayer_DSC_partCPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 608
; NumSgprs: 30
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 30
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z27executeThirdLayer_PSC_partAPdS_S_S_S_S_S_ ; -- Begin function _Z27executeThirdLayer_PSC_partAPdS_S_S_S_S_S_
	.globl	_Z27executeThirdLayer_PSC_partAPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z27executeThirdLayer_PSC_partAPdS_S_S_S_S_S_,@function
_Z27executeThirdLayer_PSC_partAPdS_S_S_S_S_S_: ; @_Z27executeThirdLayer_PSC_partAPdS_S_S_S_S_S_
; %bb.0:
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b256 s[16:23], s[0:1], 0x20
	v_and_b32_e32 v5, 0x3ff, v0
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	v_bfe_u32 v0, v0, 10, 10
	s_lshl_b32 s0, s13, 5
	v_mul_u32_u24_e32 v3, 0x70, v5
	s_mul_i32 s3, s14, 0xe00
	s_lshl_b32 s12, s15, 5
	s_ashr_i32 s1, s0, 31
	s_add_i32 s3, s3, s12
	s_lshl_b64 s[0:1], s[0:1], 3
	v_add3_u32 v3, s3, v0, v3
	s_mov_b32 s2, s13
	s_waitcnt lgkmcnt(0)
	s_add_u32 s3, s6, s0
	s_addc_u32 s6, s7, s1
	s_mov_b64 s[0:1], 0
.LBB6_1:                                ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v4, 31, v3
	s_add_u32 s22, s3, s0
	s_addc_u32 s23, s6, s1
	s_add_u32 s0, s0, 8
	s_load_b64 s[22:23], s[22:23], 0x0
	v_lshlrev_b64 v[6:7], 3, v[3:4]
	v_add_nc_u32_e32 v3, 0x3100, v3
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s0, 0x100
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, s4, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	global_load_b64 v[6:7], v[6:7], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fma_f64 v[1:2], v[6:7], s[22:23], v[1:2]
	s_cbranch_scc0 .LBB6_1
; %bb.2:
	s_ashr_i32 s3, s2, 31
	s_mulk_i32 s14, 0xe20
	s_lshl_b64 s[0:1], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_add_u32 s4, s10, s0
	s_addc_u32 s5, s11, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], v[1:2], -s[4:5]
	s_add_u32 s4, s16, s0
	s_addc_u32 s5, s17, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[3:4], null, s[4:5], s[4:5], v[1:2]
	v_div_scale_f64 v[10:11], vcc_lo, v[1:2], s[4:5], v[1:2]
	v_rcp_f64_e32 v[6:7], v[3:4]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[3:4], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_fma_f64 v[8:9], -v[3:4], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_mul_f64 v[8:9], v[10:11], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[3:4], -v[3:4], v[8:9], v[10:11]
	v_div_fmas_f64 v[3:4], v[3:4], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[1:2], v[3:4], s[4:5], v[1:2]
	s_add_u32 s4, s18, s0
	s_addc_u32 s5, s19, s1
	s_add_u32 s0, s20, s0
	s_addc_u32 s1, s21, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	v_mul_u32_u24_e32 v3, 0x71, v5
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[1:2], v[1:2], s[4:5], s[0:1]
	s_mul_i32 s0, s2, 0x31e1
	s_add_i32 s0, s12, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s0, s0, s14
	v_add3_u32 v3, s0, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[1:2]
	v_dual_cndmask_b32 v2, 0, v2 :: v_dual_cndmask_b32 v1, 0, v1
	v_cmp_nlt_f64_e32 vcc_lo, 0x40180000, v[1:2]
	v_cndmask_b32_e32 v2, 0x40180000, v2, vcc_lo
	v_cndmask_b32_e32 v1, 0, v1, vcc_lo
	v_add_co_u32 v3, vcc_lo, s8, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
	global_store_b64 v[3:4], v[1:2], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z27executeThirdLayer_PSC_partAPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end6:
	.size	_Z27executeThirdLayer_PSC_partAPdS_S_S_S_S_S_, .Lfunc_end6-_Z27executeThirdLayer_PSC_partAPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 536
; NumSgprs: 26
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z27executeThirdLayer_PSC_partBPdS_S_S_S_S_S_ ; -- Begin function _Z27executeThirdLayer_PSC_partBPdS_S_S_S_S_S_
	.globl	_Z27executeThirdLayer_PSC_partBPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z27executeThirdLayer_PSC_partBPdS_S_S_S_S_S_,@function
_Z27executeThirdLayer_PSC_partBPdS_S_S_S_S_S_: ; @_Z27executeThirdLayer_PSC_partBPdS_S_S_S_S_S_
; %bb.0:
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b256 s[16:23], s[0:1], 0x20
	v_bfe_u32 v1, v0, 10, 10
	s_mul_i32 s0, s15, 0x700
	v_and_b32_e32 v5, 0x3ff, v0
	s_mov_b32 s2, s15
	s_delay_alu instid0(VALU_DEP_2)
	v_add3_u32 v4, v1, s0, 0x60
	v_mov_b32_e32 v0, 0
	s_lshl_b32 s0, s14, 5
	v_mov_b32_e32 v1, 0
	s_ashr_i32 s1, s0, 31
	v_mad_u32_u24 v2, 0x70, v5, v4
	s_lshl_b64 s[0:1], s[0:1], 3
	s_waitcnt lgkmcnt(0)
	s_add_u32 s3, s6, s0
	s_addc_u32 s6, s7, s1
	s_mov_b64 s[0:1], 0
.LBB7_1:                                ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v3, 31, v2
	s_add_u32 s12, s3, s0
	s_addc_u32 s13, s6, s1
	s_add_u32 s0, s0, 8
	s_load_b64 s[12:13], s[12:13], 0x0
	v_lshlrev_b64 v[6:7], 3, v[2:3]
	v_add_nc_u32_e32 v2, 0x3100, v2
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s0, 0x100
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, s4, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	global_load_b64 v[6:7], v[6:7], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fma_f64 v[0:1], v[6:7], s[12:13], v[0:1]
	s_cbranch_scc0 .LBB7_1
; %bb.2:
	s_ashr_i32 s15, s14, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[14:15], 3
	s_add_u32 s4, s10, s0
	s_addc_u32 s5, s11, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], -s[4:5]
	s_add_u32 s4, s16, s0
	s_addc_u32 s5, s17, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_div_scale_f64 v[2:3], null, s[4:5], s[4:5], v[0:1]
	v_div_scale_f64 v[10:11], vcc_lo, v[0:1], s[4:5], v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[6:7], v[2:3]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[2:3], v[6:7], 1.0
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], -v[2:3], v[6:7], 1.0
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[8:9], v[10:11], v[6:7]
	v_fma_f64 v[2:3], -v[2:3], v[8:9], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[2:3], v[2:3], v[6:7], v[8:9]
	v_div_fixup_f64 v[0:1], v[2:3], s[4:5], v[0:1]
	s_add_u32 s4, s18, s0
	s_addc_u32 s5, s19, s1
	s_add_u32 s0, s20, s0
	s_addc_u32 s1, s21, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	v_mul_u32_u24_e32 v2, 0x71, v5
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[0:1], v[0:1], s[4:5], s[0:1]
	s_mul_i32 s0, s14, 0x31e1
	s_lshl_b32 s1, s2, 4
	s_add_i32 s0, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v2, s0, v4, v2
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, 0, v1 :: v_dual_cndmask_b32 v0, 0, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_nlt_f64_e32 vcc_lo, 0x40180000, v[0:1]
	v_cndmask_b32_e32 v1, 0x40180000, v1, vcc_lo
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	global_store_b64 v[2:3], v[0:1], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z27executeThirdLayer_PSC_partBPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end7:
	.size	_Z27executeThirdLayer_PSC_partBPdS_S_S_S_S_S_, .Lfunc_end7-_Z27executeThirdLayer_PSC_partBPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 536
; NumSgprs: 26
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z27executeThirdLayer_PSC_partCPdS_S_S_S_S_S_ ; -- Begin function _Z27executeThirdLayer_PSC_partCPdS_S_S_S_S_S_
	.globl	_Z27executeThirdLayer_PSC_partCPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z27executeThirdLayer_PSC_partCPdS_S_S_S_S_S_,@function
_Z27executeThirdLayer_PSC_partCPdS_S_S_S_S_S_: ; @_Z27executeThirdLayer_PSC_partCPdS_S_S_S_S_S_
; %bb.0:
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b256 s[16:23], s[0:1], 0x20
	v_bfe_u32 v5, v0, 10, 10
	v_and_b32_e32 v4, 0x3ff, v0
	s_lshl_b32 s2, s15, 4
	s_lshl_b32 s0, s14, 5
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	v_add_nc_u32_e32 v3, s2, v5
	v_mul_u32_u24_e32 v2, 0x70, v4
	s_ashr_i32 s1, s0, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_lshl_b64 s[0:1], s[0:1], 3
	v_add3_u32 v2, v3, v2, 0x2a00
	s_waitcnt lgkmcnt(0)
	s_add_u32 s3, s6, s0
	s_addc_u32 s6, s7, s1
	s_mov_b64 s[0:1], 0
.LBB8_1:                                ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v3, 31, v2
	s_add_u32 s12, s3, s0
	s_addc_u32 s13, s6, s1
	s_add_u32 s0, s0, 8
	s_load_b64 s[12:13], s[12:13], 0x0
	v_lshlrev_b64 v[6:7], 3, v[2:3]
	v_add_nc_u32_e32 v2, 0x3100, v2
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s0, 0x100
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, s4, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	global_load_b64 v[6:7], v[6:7], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fma_f64 v[0:1], v[6:7], s[12:13], v[0:1]
	s_cbranch_scc0 .LBB8_1
; %bb.2:
	s_ashr_i32 s15, s14, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[14:15], 3
	s_add_u32 s4, s10, s0
	s_addc_u32 s5, s11, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], -s[4:5]
	s_add_u32 s4, s16, s0
	s_addc_u32 s5, s17, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_div_scale_f64 v[2:3], null, s[4:5], s[4:5], v[0:1]
	v_div_scale_f64 v[10:11], vcc_lo, v[0:1], s[4:5], v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[6:7], v[2:3]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[2:3], v[6:7], 1.0
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], -v[2:3], v[6:7], 1.0
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[8:9], v[10:11], v[6:7]
	v_fma_f64 v[2:3], -v[2:3], v[8:9], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[2:3], v[2:3], v[6:7], v[8:9]
	v_div_fixup_f64 v[0:1], v[2:3], s[4:5], v[0:1]
	s_add_u32 s4, s18, s0
	s_addc_u32 s5, s19, s1
	s_add_u32 s0, s20, s0
	s_addc_u32 s1, s21, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	v_mul_u32_u24_e32 v2, 0x71, v4
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[0:1], v[0:1], s[4:5], s[0:1]
	s_mul_i32 s0, s14, 0x31e1
	v_add3_u32 v3, s2, s0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v2, v3, v2, 0x2a60
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, 0, v1 :: v_dual_cndmask_b32 v0, 0, v0
	v_cmp_nlt_f64_e32 vcc_lo, 0x40180000, v[0:1]
	v_cndmask_b32_e32 v1, 0x40180000, v1, vcc_lo
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	global_store_b64 v[2:3], v[0:1], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z27executeThirdLayer_PSC_partCPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end8:
	.size	_Z27executeThirdLayer_PSC_partCPdS_S_S_S_S_S_, .Lfunc_end8-_Z27executeThirdLayer_PSC_partCPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 528
; NumSgprs: 26
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z28executeFourthLayer_DSC_partAPdS_S_S_S_S_S_ ; -- Begin function _Z28executeFourthLayer_DSC_partAPdS_S_S_S_S_S_
	.globl	_Z28executeFourthLayer_DSC_partAPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z28executeFourthLayer_DSC_partAPdS_S_S_S_S_S_,@function
_Z28executeFourthLayer_DSC_partAPdS_S_S_S_S_S_: ; @_Z28executeFourthLayer_DSC_partAPdS_S_S_S_S_S_
; %bb.0:
	s_mov_b32 s2, s15
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b256 s[12:19], s[0:1], 0x20
	v_and_b32_e32 v3, 0x3ff, v0
	v_bfe_u32 v2, v0, 10, 10
	v_mov_b32_e32 v0, 0
	s_mul_i32 s0, s2, 9
	s_mul_i32 s3, s2, 0x31e1
	v_mul_u32_u24_e32 v4, 0xe2, v3
	v_lshlrev_b32_e32 v5, 1, v2
	s_ashr_i32 s1, s0, 31
	v_mov_b32_e32 v1, 0
	s_lshl_b64 s[0:1], s[0:1], 3
	s_delay_alu instid0(VALU_DEP_2)
	v_add3_u32 v4, v4, v5, s3
	s_mov_b32 s3, 0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s0, s6
	s_addc_u32 s1, s1, s7
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB9_1:                                ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v5, s3, v4
	s_add_u32 s6, s0, -8
	s_addc_u32 s7, s1, -1
	s_addk_i32 s3, 0x71
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v6, vcc_lo
	s_clause 0x1
	global_load_b128 v[5:8], v[9:10], off
	global_load_b64 v[9:10], v[9:10], off offset:16
	s_clause 0x1
	s_load_b128 s[20:23], s[6:7], 0x0
	s_load_b64 s[6:7], s[0:1], 0x8
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s3, 0x153
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_mul_f64 v[7:8], v[7:8], s[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], v[5:6], s[20:21], v[7:8]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[5:6], v[9:10], s[6:7], v[5:6]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], v[5:6]
	s_cbranch_scc0 .LBB9_1
; %bb.2:
	s_ashr_i32 s3, s2, 31
	v_mul_u32_u24_e32 v3, 56, v3
	s_lshl_b64 s[0:1], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_add_u32 s4, s10, s0
	s_addc_u32 s5, s11, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[0:1], v[0:1], -s[4:5]
	s_add_u32 s4, s12, s0
	s_addc_u32 s5, s13, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[4:5], null, s[4:5], s[4:5], v[0:1]
	v_div_scale_f64 v[10:11], vcc_lo, v[0:1], s[4:5], v[0:1]
	v_rcp_f64_e32 v[6:7], v[4:5]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_mul_f64 v[8:9], v[10:11], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], -v[4:5], v[8:9], v[10:11]
	v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[0:1], v[4:5], s[4:5], v[0:1]
	s_add_u32 s4, s14, s0
	s_addc_u32 s5, s15, s1
	s_add_u32 s0, s16, s0
	s_addc_u32 s1, s17, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[0:1], v[0:1], s[4:5], s[0:1]
	s_mul_i32 s0, s2, 0xc40
	v_add3_u32 v2, v3, v2, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, 0, v1 :: v_dual_cndmask_b32 v0, 0, v0
	v_cmp_nlt_f64_e32 vcc_lo, 0x40180000, v[0:1]
	v_cndmask_b32_e32 v1, 0x40180000, v1, vcc_lo
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	global_store_b64 v[2:3], v[0:1], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z28executeFourthLayer_DSC_partAPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end9:
	.size	_Z28executeFourthLayer_DSC_partAPdS_S_S_S_S_S_, .Lfunc_end9-_Z28executeFourthLayer_DSC_partAPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 588
; NumSgprs: 26
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z28executeFourthLayer_DSC_partBPdS_S_S_S_S_S_ ; -- Begin function _Z28executeFourthLayer_DSC_partBPdS_S_S_S_S_S_
	.globl	_Z28executeFourthLayer_DSC_partBPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z28executeFourthLayer_DSC_partBPdS_S_S_S_S_S_,@function
_Z28executeFourthLayer_DSC_partBPdS_S_S_S_S_S_: ; @_Z28executeFourthLayer_DSC_partBPdS_S_S_S_S_S_
; %bb.0:
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_load_b256 s[4:11], s[0:1], 0x0
	s_mov_b32 s2, s15
	s_load_b256 s[12:19], s[0:1], 0x20
	v_mul_u32_u24_e32 v0, 0xe2, v2
	v_lshlrev_b32_e32 v1, 1, v3
	s_mul_i32 s0, s2, 0x31e1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v0, s1, v1, v0
	v_add_co_ci_u32_e64 v1, null, 0, 0, s1
	s_ashr_i32 s1, s0, 31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, s0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_mul_i32 s0, s2, 9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_ashr_i32 s1, s0, 31
	v_lshlrev_b64 v[4:5], 3, v[0:1]
	s_lshl_b64 s[0:1], s[0:1], 3
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s0, s6
	s_addc_u32 s1, s1, s7
	v_add_co_u32 v4, vcc_lo, s4, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v5, vcc_lo
	s_add_u32 s0, s0, 16
	s_addc_u32 s1, s1, 0
	s_mov_b64 s[4:5], 0
.LBB10_1:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_co_u32 v10, vcc_lo, v4, s4
	v_add_co_ci_u32_e32 v11, vcc_lo, s5, v5, vcc_lo
	s_add_u32 s6, s0, -16
	s_addc_u32 s7, s1, -1
	s_add_u32 s4, s4, 0x388
	s_clause 0x1
	global_load_b128 v[6:9], v[10:11], off offset:512
	global_load_b64 v[10:11], v[10:11], off offset:528
	s_clause 0x1
	s_load_b128 s[20:23], s[6:7], 0x0
	s_load_b64 s[6:7], s[0:1], 0x0
	s_addc_u32 s5, s5, 0
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s4, 0xa98
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_mul_f64 v[8:9], v[8:9], s[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], s[20:21], v[8:9]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[6:7], v[10:11], s[6:7], v[6:7]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], v[6:7]
	s_cbranch_scc0 .LBB10_1
; %bb.2:
	s_ashr_i32 s3, s2, 31
	v_mad_u32_u24 v2, v2, 56, v3
	s_lshl_b64 s[0:1], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_add_u32 s4, s10, s0
	s_addc_u32 s5, s11, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[0:1], v[0:1], -s[4:5]
	s_add_u32 s4, s12, s0
	s_addc_u32 s5, s13, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[4:5], null, s[4:5], s[4:5], v[0:1]
	v_div_scale_f64 v[10:11], vcc_lo, v[0:1], s[4:5], v[0:1]
	v_rcp_f64_e32 v[6:7], v[4:5]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_mul_f64 v[8:9], v[10:11], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], -v[4:5], v[8:9], v[10:11]
	v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[0:1], v[4:5], s[4:5], v[0:1]
	s_add_u32 s4, s14, s0
	s_addc_u32 s5, s15, s1
	s_add_u32 s0, s16, s0
	s_addc_u32 s1, s17, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[0:1], v[0:1], s[4:5], s[0:1]
	s_mul_i32 s0, s2, 0xc40
	v_add3_u32 v2, v2, s0, 32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, 0, v1 :: v_dual_cndmask_b32 v0, 0, v0
	v_cmp_nlt_f64_e32 vcc_lo, 0x40180000, v[0:1]
	v_cndmask_b32_e32 v1, 0x40180000, v1, vcc_lo
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	global_store_b64 v[2:3], v[0:1], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z28executeFourthLayer_DSC_partBPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end10:
	.size	_Z28executeFourthLayer_DSC_partBPdS_S_S_S_S_S_, .Lfunc_end10-_Z28executeFourthLayer_DSC_partBPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 628
; NumSgprs: 26
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z28executeFourthLayer_DSC_partCPdS_S_S_S_S_S_ ; -- Begin function _Z28executeFourthLayer_DSC_partCPdS_S_S_S_S_S_
	.globl	_Z28executeFourthLayer_DSC_partCPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z28executeFourthLayer_DSC_partCPdS_S_S_S_S_S_,@function
_Z28executeFourthLayer_DSC_partCPdS_S_S_S_S_S_: ; @_Z28executeFourthLayer_DSC_partCPdS_S_S_S_S_S_
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x0
	s_mov_b32 s2, s15
	v_bfe_u32 v1, v0, 10, 10
	s_load_b256 s[12:19], s[0:1], 0x20
	v_and_b32_e32 v0, 0x3ff, v0
	s_mul_i32 s0, s2, 9
	s_mul_i32 s3, s2, 0x31e1
	v_lshlrev_b32_e32 v2, 1, v1
	s_ashr_i32 s1, s0, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_lshl_b64 s[0:1], s[0:1], 3
	v_mad_u32_u24 v4, 0xe2, v0, v2
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_3)
	v_add3_u32 v4, v4, s3, 0x1c40
	s_mov_b32 s3, 0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s0, s6
	s_addc_u32 s1, s1, s7
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB11_1:                               ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v5, s3, v4
	s_add_u32 s6, s0, -8
	s_addc_u32 s7, s1, -1
	s_addk_i32 s3, 0x71
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v6, vcc_lo
	s_clause 0x1
	global_load_b128 v[5:8], v[9:10], off
	global_load_b64 v[9:10], v[9:10], off offset:16
	s_clause 0x1
	s_load_b128 s[20:23], s[6:7], 0x0
	s_load_b64 s[6:7], s[0:1], 0x8
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s3, 0x153
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_mul_f64 v[7:8], v[7:8], s[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], v[5:6], s[20:21], v[7:8]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[5:6], v[9:10], s[6:7], v[5:6]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[2:3], v[2:3], v[5:6]
	s_cbranch_scc0 .LBB11_1
; %bb.2:
	s_ashr_i32 s3, s2, 31
	v_mul_u32_u24_e32 v0, 56, v0
	s_lshl_b64 s[0:1], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_add_u32 s4, s10, s0
	s_addc_u32 s5, s11, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[2:3], v[2:3], -s[4:5]
	s_add_u32 s4, s12, s0
	s_addc_u32 s5, s13, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[4:5], null, s[4:5], s[4:5], v[2:3]
	v_div_scale_f64 v[10:11], vcc_lo, v[2:3], s[4:5], v[2:3]
	v_rcp_f64_e32 v[6:7], v[4:5]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_mul_f64 v[8:9], v[10:11], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], -v[4:5], v[8:9], v[10:11]
	v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[2:3], v[4:5], s[4:5], v[2:3]
	s_add_u32 s4, s14, s0
	s_addc_u32 s5, s15, s1
	s_add_u32 s0, s16, s0
	s_addc_u32 s1, s17, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[2:3], v[2:3], s[4:5], s[0:1]
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, 0, v3 :: v_dual_cndmask_b32 v2, 0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_nlt_f64_e32 vcc_lo, 0x40180000, v[2:3]
	v_mad_u64_u32 v[4:5], null, 0xc40, s2, v[1:2]
	v_add3_u32 v0, v4, v0, 0x700
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_cndmask_b32_e32 v3, 0x40180000, v3, vcc_lo
	v_cndmask_b32_e32 v2, 0, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	global_store_b64 v[0:1], v[2:3], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z28executeFourthLayer_DSC_partCPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end11:
	.size	_Z28executeFourthLayer_DSC_partCPdS_S_S_S_S_S_, .Lfunc_end11-_Z28executeFourthLayer_DSC_partCPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 608
; NumSgprs: 26
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z28executeFourthLayer_DSC_partDPdS_S_S_S_S_S_ ; -- Begin function _Z28executeFourthLayer_DSC_partDPdS_S_S_S_S_S_
	.globl	_Z28executeFourthLayer_DSC_partDPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z28executeFourthLayer_DSC_partDPdS_S_S_S_S_S_,@function
_Z28executeFourthLayer_DSC_partDPdS_S_S_S_S_S_: ; @_Z28executeFourthLayer_DSC_partDPdS_S_S_S_S_S_
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x0
	s_mov_b32 s2, s15
	v_bfe_u32 v1, v0, 10, 10
	s_load_b256 s[12:19], s[0:1], 0x20
	v_and_b32_e32 v0, 0x3ff, v0
	s_mul_i32 s0, s2, 9
	s_mul_i32 s3, s2, 0x31e1
	v_lshlrev_b32_e32 v2, 1, v1
	s_ashr_i32 s1, s0, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_lshl_b64 s[0:1], s[0:1], 3
	v_mad_u32_u24 v4, 0xe2, v0, v2
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_3)
	v_add3_u32 v4, v4, s3, 0x1c80
	s_mov_b32 s3, 0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s0, s6
	s_addc_u32 s1, s1, s7
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB12_1:                               ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v5, s3, v4
	s_add_u32 s6, s0, -8
	s_addc_u32 s7, s1, -1
	s_addk_i32 s3, 0x71
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v6, vcc_lo
	s_clause 0x1
	global_load_b128 v[5:8], v[9:10], off
	global_load_b64 v[9:10], v[9:10], off offset:16
	s_clause 0x1
	s_load_b128 s[20:23], s[6:7], 0x0
	s_load_b64 s[6:7], s[0:1], 0x8
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s3, 0x153
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_mul_f64 v[7:8], v[7:8], s[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], v[5:6], s[20:21], v[7:8]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[5:6], v[9:10], s[6:7], v[5:6]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[2:3], v[2:3], v[5:6]
	s_cbranch_scc0 .LBB12_1
; %bb.2:
	s_ashr_i32 s3, s2, 31
	v_mul_u32_u24_e32 v0, 56, v0
	s_lshl_b64 s[0:1], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_add_u32 s4, s10, s0
	s_addc_u32 s5, s11, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[2:3], v[2:3], -s[4:5]
	s_add_u32 s4, s12, s0
	s_addc_u32 s5, s13, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[4:5], null, s[4:5], s[4:5], v[2:3]
	v_div_scale_f64 v[10:11], vcc_lo, v[2:3], s[4:5], v[2:3]
	v_rcp_f64_e32 v[6:7], v[4:5]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_mul_f64 v[8:9], v[10:11], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], -v[4:5], v[8:9], v[10:11]
	v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[2:3], v[4:5], s[4:5], v[2:3]
	s_add_u32 s4, s14, s0
	s_addc_u32 s5, s15, s1
	s_add_u32 s0, s16, s0
	s_addc_u32 s1, s17, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[2:3], v[2:3], s[4:5], s[0:1]
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, 0, v3 :: v_dual_cndmask_b32 v2, 0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_nlt_f64_e32 vcc_lo, 0x40180000, v[2:3]
	v_mad_u64_u32 v[4:5], null, 0xc40, s2, v[1:2]
	v_add3_u32 v0, v4, v0, 0x720
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_cndmask_b32_e32 v3, 0x40180000, v3, vcc_lo
	v_cndmask_b32_e32 v2, 0, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	global_store_b64 v[0:1], v[2:3], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z28executeFourthLayer_DSC_partDPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end12:
	.size	_Z28executeFourthLayer_DSC_partDPdS_S_S_S_S_S_, .Lfunc_end12-_Z28executeFourthLayer_DSC_partDPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 608
; NumSgprs: 26
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z27executeFifthLayer_PSC_partAPdS_S_S_S_S_S_ ; -- Begin function _Z27executeFifthLayer_PSC_partAPdS_S_S_S_S_S_
	.globl	_Z27executeFifthLayer_PSC_partAPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z27executeFifthLayer_PSC_partAPdS_S_S_S_S_S_,@function
_Z27executeFifthLayer_PSC_partAPdS_S_S_S_S_S_: ; @_Z27executeFifthLayer_PSC_partAPdS_S_S_S_S_S_
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_and_b32_e32 v4, 0x3ff, v0
	s_mov_b32 s2, s15
	s_load_b256 s[12:19], s[0:1], 0x20
	v_bfe_u32 v5, v0, 10, 10
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	v_mul_u32_u24_e32 v6, 56, v4
	s_lshl_b32 s0, s2, 6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_ashr_i32 s1, s0, 31
	v_add_lshl_u32 v2, v6, v5, 3
	s_lshl_b64 s[0:1], s[0:1], 3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v2, s3, s4, v2
	v_add_co_ci_u32_e64 v3, null, s5, 0, s3
	s_add_u32 s3, s6, s0
	s_addc_u32 s4, s7, s1
	s_mov_b64 s[0:1], 0
.LBB13_1:                               ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[7:8], v[2:3], off
	s_add_u32 s6, s3, s0
	s_addc_u32 s7, s4, s1
	v_add_co_u32 v2, vcc_lo, 0x6200, v2
	s_load_b64 s[6:7], s[6:7], 0x0
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s0, 0x200
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fma_f64 v[0:1], v[7:8], s[6:7], v[0:1]
	s_cbranch_scc0 .LBB13_1
; %bb.2:
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[2:3], 3
	s_add_u32 s4, s10, s0
	s_addc_u32 s5, s11, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], -s[4:5]
	s_add_u32 s4, s12, s0
	s_addc_u32 s5, s13, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_div_scale_f64 v[2:3], null, s[4:5], s[4:5], v[0:1]
	v_div_scale_f64 v[11:12], vcc_lo, v[0:1], s[4:5], v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[7:8], v[2:3]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[9:10], -v[2:3], v[7:8], 1.0
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], -v[2:3], v[7:8], 1.0
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[9:10], v[11:12], v[7:8]
	v_fma_f64 v[2:3], -v[2:3], v[9:10], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[2:3], v[2:3], v[7:8], v[9:10]
	v_div_fixup_f64 v[0:1], v[2:3], s[4:5], v[0:1]
	s_add_u32 s4, s14, s0
	s_addc_u32 s5, s15, s1
	s_add_u32 s0, s16, s0
	s_addc_u32 s1, s17, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	v_add_nc_u32_e32 v2, v6, v5
	v_lshlrev_b32_e32 v3, 1, v4
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f64 v[0:1], v[0:1], s[4:5], s[0:1]
	s_mul_i32 s0, s2, 0xd24
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_add3_u32 v2, v2, v3, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, 0, v1 :: v_dual_cndmask_b32 v0, 0, v0
	v_cmp_nlt_f64_e32 vcc_lo, 0x40180000, v[0:1]
	v_cndmask_b32_e32 v1, 0x40180000, v1, vcc_lo
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	global_store_b64 v[2:3], v[0:1], off offset:472
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z27executeFifthLayer_PSC_partAPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end13:
	.size	_Z27executeFifthLayer_PSC_partAPdS_S_S_S_S_S_, .Lfunc_end13-_Z27executeFifthLayer_PSC_partAPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 504
; NumSgprs: 22
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z27executeFifthLayer_PSC_partBPdS_S_S_S_S_S_ ; -- Begin function _Z27executeFifthLayer_PSC_partBPdS_S_S_S_S_S_
	.globl	_Z27executeFifthLayer_PSC_partBPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z27executeFifthLayer_PSC_partBPdS_S_S_S_S_S_,@function
_Z27executeFifthLayer_PSC_partBPdS_S_S_S_S_S_: ; @_Z27executeFifthLayer_PSC_partBPdS_S_S_S_S_S_
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_and_b32_e32 v4, 0x3ff, v0
	v_bfe_u32 v5, v0, 10, 10
	s_mov_b32 s2, s15
	s_load_b256 s[12:19], s[0:1], 0x20
	s_lshl_b32 s0, s2, 6
	v_mul_u32_u24_e32 v0, 56, v4
	s_ashr_i32 s1, s0, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_lshl_b64 s[0:1], s[0:1], 3
	v_add_lshl_u32 v2, v0, v5, 3
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v2, s3, v2, s4
	v_add_co_ci_u32_e64 v3, null, 0, s5, s3
	s_add_u32 s3, s6, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, 0x100, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_addc_u32 s4, s7, s1
	s_mov_b64 s[0:1], 0
.LBB14_1:                               ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[6:7], v[2:3], off
	s_add_u32 s6, s3, s0
	s_addc_u32 s7, s4, s1
	v_add_co_u32 v2, vcc_lo, 0x6200, v2
	s_load_b64 s[6:7], s[6:7], 0x0
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s0, 0x200
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fma_f64 v[0:1], v[6:7], s[6:7], v[0:1]
	s_cbranch_scc0 .LBB14_1
; %bb.2:
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[2:3], 3
	s_add_u32 s4, s10, s0
	s_addc_u32 s5, s11, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], -s[4:5]
	s_add_u32 s4, s12, s0
	s_addc_u32 s5, s13, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_div_scale_f64 v[2:3], null, s[4:5], s[4:5], v[0:1]
	v_div_scale_f64 v[10:11], vcc_lo, v[0:1], s[4:5], v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[6:7], v[2:3]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[2:3], v[6:7], 1.0
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], -v[2:3], v[6:7], 1.0
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[8:9], v[10:11], v[6:7]
	v_fma_f64 v[2:3], -v[2:3], v[8:9], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[2:3], v[2:3], v[6:7], v[8:9]
	v_div_fixup_f64 v[0:1], v[2:3], s[4:5], v[0:1]
	s_add_u32 s4, s14, s0
	s_addc_u32 s5, s15, s1
	s_add_u32 s0, s16, s0
	s_addc_u32 s1, s17, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	v_mad_u32_u24 v2, v4, 58, v5
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[0:1], v[0:1], s[4:5], s[0:1]
	s_mul_i32 s0, s2, 0xd24
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_add3_u32 v2, v2, s0, 32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, 0, v1 :: v_dual_cndmask_b32 v0, 0, v0
	v_cmp_nlt_f64_e32 vcc_lo, 0x40180000, v[0:1]
	v_cndmask_b32_e32 v1, 0x40180000, v1, vcc_lo
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	global_store_b64 v[2:3], v[0:1], off offset:472
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z27executeFifthLayer_PSC_partBPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end14:
	.size	_Z27executeFifthLayer_PSC_partBPdS_S_S_S_S_S_, .Lfunc_end14-_Z27executeFifthLayer_PSC_partBPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 524
; NumSgprs: 22
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z27executeFifthLayer_PSC_partCPdS_S_S_S_S_S_ ; -- Begin function _Z27executeFifthLayer_PSC_partCPdS_S_S_S_S_S_
	.globl	_Z27executeFifthLayer_PSC_partCPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z27executeFifthLayer_PSC_partCPdS_S_S_S_S_S_,@function
_Z27executeFifthLayer_PSC_partCPdS_S_S_S_S_S_: ; @_Z27executeFifthLayer_PSC_partCPdS_S_S_S_S_S_
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_and_b32_e32 v5, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_mov_b32 s2, s15
	s_load_b256 s[12:19], s[0:1], 0x20
	s_lshl_b32 s0, s2, 6
	v_mul_u32_u24_e32 v1, 56, v5
	s_ashr_i32 s1, s0, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_lshl_b64 s[0:1], s[0:1], 3
	v_add_lshl_u32 v3, v1, v0, 3
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v3, s3, v3, s4
	v_add_co_ci_u32_e64 v4, null, 0, s5, s3
	s_add_u32 s3, s6, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, 0x3800, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
	s_addc_u32 s4, s7, s1
	s_mov_b64 s[0:1], 0
.LBB15_1:                               ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[6:7], v[3:4], off
	s_add_u32 s6, s3, s0
	s_addc_u32 s7, s4, s1
	v_add_co_u32 v3, vcc_lo, 0x6200, v3
	s_load_b64 s[6:7], s[6:7], 0x0
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s0, 0x200
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fma_f64 v[1:2], v[6:7], s[6:7], v[1:2]
	s_cbranch_scc0 .LBB15_1
; %bb.2:
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[2:3], 3
	s_add_u32 s4, s10, s0
	s_addc_u32 s5, s11, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_f64 v[1:2], v[1:2], -s[4:5]
	s_add_u32 s4, s12, s0
	s_addc_u32 s5, s13, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_div_scale_f64 v[3:4], null, s[4:5], s[4:5], v[1:2]
	v_div_scale_f64 v[10:11], vcc_lo, v[1:2], s[4:5], v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[6:7], v[3:4]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[3:4], v[6:7], 1.0
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], -v[3:4], v[6:7], 1.0
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[8:9], v[10:11], v[6:7]
	v_fma_f64 v[3:4], -v[3:4], v[8:9], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[3:4], v[3:4], v[6:7], v[8:9]
	v_div_fixup_f64 v[1:2], v[3:4], s[4:5], v[1:2]
	s_add_u32 s4, s14, s0
	s_addc_u32 s5, s15, s1
	s_add_u32 s0, s16, s0
	s_addc_u32 s1, s17, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[1:2], v[1:2], s[4:5], s[0:1]
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[1:2]
	v_dual_cndmask_b32 v2, 0, v2 :: v_dual_cndmask_b32 v1, 0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_nlt_f64_e32 vcc_lo, 0x40180000, v[1:2]
	v_mad_u64_u32 v[3:4], null, 0xd24, s2, v[0:1]
	v_mul_u32_u24_e32 v0, 58, v5
	v_add3_u32 v3, v3, v0, 0x740
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	v_cndmask_b32_e32 v2, 0x40180000, v2, vcc_lo
	v_cndmask_b32_e32 v1, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s8, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
	global_store_b64 v[3:4], v[1:2], off offset:472
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z27executeFifthLayer_PSC_partCPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end15:
	.size	_Z27executeFifthLayer_PSC_partCPdS_S_S_S_S_S_, .Lfunc_end15-_Z27executeFifthLayer_PSC_partCPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 528
; NumSgprs: 22
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z27executeFifthLayer_PSC_partDPdS_S_S_S_S_S_ ; -- Begin function _Z27executeFifthLayer_PSC_partDPdS_S_S_S_S_S_
	.globl	_Z27executeFifthLayer_PSC_partDPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z27executeFifthLayer_PSC_partDPdS_S_S_S_S_S_,@function
_Z27executeFifthLayer_PSC_partDPdS_S_S_S_S_S_: ; @_Z27executeFifthLayer_PSC_partDPdS_S_S_S_S_S_
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_and_b32_e32 v5, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_mov_b32 s2, s15
	s_load_b256 s[12:19], s[0:1], 0x20
	s_lshl_b32 s0, s2, 6
	v_mul_u32_u24_e32 v1, 56, v5
	s_ashr_i32 s1, s0, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_lshl_b64 s[0:1], s[0:1], 3
	v_add_lshl_u32 v3, v1, v0, 3
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v3, s3, v3, s4
	v_add_co_ci_u32_e64 v4, null, 0, s5, s3
	s_add_u32 s3, s6, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, 0x3900, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
	s_addc_u32 s4, s7, s1
	s_mov_b64 s[0:1], 0
.LBB16_1:                               ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[6:7], v[3:4], off
	s_add_u32 s6, s3, s0
	s_addc_u32 s7, s4, s1
	v_add_co_u32 v3, vcc_lo, 0x6200, v3
	s_load_b64 s[6:7], s[6:7], 0x0
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s0, 0x200
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fma_f64 v[1:2], v[6:7], s[6:7], v[1:2]
	s_cbranch_scc0 .LBB16_1
; %bb.2:
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[2:3], 3
	s_add_u32 s4, s10, s0
	s_addc_u32 s5, s11, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_f64 v[1:2], v[1:2], -s[4:5]
	s_add_u32 s4, s12, s0
	s_addc_u32 s5, s13, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_div_scale_f64 v[3:4], null, s[4:5], s[4:5], v[1:2]
	v_div_scale_f64 v[10:11], vcc_lo, v[1:2], s[4:5], v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[6:7], v[3:4]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[3:4], v[6:7], 1.0
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], -v[3:4], v[6:7], 1.0
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[8:9], v[10:11], v[6:7]
	v_fma_f64 v[3:4], -v[3:4], v[8:9], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[3:4], v[3:4], v[6:7], v[8:9]
	v_div_fixup_f64 v[1:2], v[3:4], s[4:5], v[1:2]
	s_add_u32 s4, s14, s0
	s_addc_u32 s5, s15, s1
	s_add_u32 s0, s16, s0
	s_addc_u32 s1, s17, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[1:2], v[1:2], s[4:5], s[0:1]
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[1:2]
	v_dual_cndmask_b32 v2, 0, v2 :: v_dual_cndmask_b32 v1, 0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_nlt_f64_e32 vcc_lo, 0x40180000, v[1:2]
	v_mad_u64_u32 v[3:4], null, 0xd24, s2, v[0:1]
	v_mul_u32_u24_e32 v0, 58, v5
	v_add3_u32 v3, v3, v0, 0x760
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	v_cndmask_b32_e32 v2, 0x40180000, v2, vcc_lo
	v_cndmask_b32_e32 v1, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s8, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
	global_store_b64 v[3:4], v[1:2], off offset:472
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z27executeFifthLayer_PSC_partDPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end16:
	.size	_Z27executeFifthLayer_PSC_partDPdS_S_S_S_S_S_, .Lfunc_end16-_Z27executeFifthLayer_PSC_partDPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 528
; NumSgprs: 22
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z27executeSixthLayer_DSC_partAPdS_S_S_S_S_S_ ; -- Begin function _Z27executeSixthLayer_DSC_partAPdS_S_S_S_S_S_
	.globl	_Z27executeSixthLayer_DSC_partAPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z27executeSixthLayer_DSC_partAPdS_S_S_S_S_S_,@function
_Z27executeSixthLayer_DSC_partAPdS_S_S_S_S_S_: ; @_Z27executeSixthLayer_DSC_partAPdS_S_S_S_S_S_
; %bb.0:
	s_mov_b32 s2, s15
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b256 s[12:19], s[0:1], 0x20
	v_and_b32_e32 v2, 0x3ff, v0
	s_mul_i32 s0, s2, 9
	v_bfe_u32 v3, v0, 10, 10
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	v_mul_u32_u24_e32 v4, 58, v2
	s_ashr_i32 s1, s0, 31
	s_mul_i32 s3, s2, 0xd24
	s_lshl_b64 s[0:1], s[0:1], 3
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v4, v3, s3, v4
	s_mov_b32 s3, 0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s0, s6
	s_addc_u32 s1, s1, s7
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB17_1:                               ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v5, s3, v4
	s_add_u32 s6, s0, -8
	s_addc_u32 s7, s1, -1
	s_add_i32 s3, s3, 58
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v6, vcc_lo
	s_clause 0x1
	global_load_b128 v[5:8], v[9:10], off
	global_load_b64 v[9:10], v[9:10], off offset:16
	s_clause 0x1
	s_load_b128 s[20:23], s[6:7], 0x0
	s_load_b64 s[6:7], s[0:1], 0x8
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s3, 0xae
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_mul_f64 v[7:8], v[7:8], s[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], v[5:6], s[20:21], v[7:8]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[5:6], v[9:10], s[6:7], v[5:6]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], v[5:6]
	s_cbranch_scc0 .LBB17_1
; %bb.2:
	s_ashr_i32 s3, s2, 31
	v_mul_u32_u24_e32 v2, 56, v2
	s_lshl_b64 s[0:1], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_add_u32 s4, s10, s0
	s_addc_u32 s5, s11, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[0:1], v[0:1], -s[4:5]
	s_add_u32 s4, s12, s0
	s_addc_u32 s5, s13, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[4:5], null, s[4:5], s[4:5], v[0:1]
	v_div_scale_f64 v[10:11], vcc_lo, v[0:1], s[4:5], v[0:1]
	v_rcp_f64_e32 v[6:7], v[4:5]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_mul_f64 v[8:9], v[10:11], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], -v[4:5], v[8:9], v[10:11]
	v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[0:1], v[4:5], s[4:5], v[0:1]
	s_add_u32 s4, s14, s0
	s_addc_u32 s5, s15, s1
	s_add_u32 s0, s16, s0
	s_addc_u32 s1, s17, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[0:1], v[0:1], s[4:5], s[0:1]
	s_mul_i32 s0, s2, 0xc40
	v_add3_u32 v2, v2, v3, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, 0, v1 :: v_dual_cndmask_b32 v0, 0, v0
	v_cmp_nlt_f64_e32 vcc_lo, 0x40180000, v[0:1]
	v_cndmask_b32_e32 v1, 0x40180000, v1, vcc_lo
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	global_store_b64 v[2:3], v[0:1], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z27executeSixthLayer_DSC_partAPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end17:
	.size	_Z27executeSixthLayer_DSC_partAPdS_S_S_S_S_S_, .Lfunc_end17-_Z27executeSixthLayer_DSC_partAPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 580
; NumSgprs: 26
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z27executeSixthLayer_DSC_partBPdS_S_S_S_S_S_ ; -- Begin function _Z27executeSixthLayer_DSC_partBPdS_S_S_S_S_S_
	.globl	_Z27executeSixthLayer_DSC_partBPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z27executeSixthLayer_DSC_partBPdS_S_S_S_S_S_,@function
_Z27executeSixthLayer_DSC_partBPdS_S_S_S_S_S_: ; @_Z27executeSixthLayer_DSC_partBPdS_S_S_S_S_S_
; %bb.0:
	s_mov_b32 s2, s15
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b256 s[12:19], s[0:1], 0x20
	v_and_b32_e32 v2, 0x3ff, v0
	s_mul_i32 s0, s2, 9
	v_bfe_u32 v3, v0, 10, 10
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	v_mul_u32_u24_e32 v4, 58, v2
	s_ashr_i32 s1, s0, 31
	s_mul_i32 s3, s2, 0xd24
	s_lshl_b64 s[0:1], s[0:1], 3
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v4, v3, s3, v4
	s_mov_b32 s3, 32
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s0, s6
	s_addc_u32 s1, s1, s7
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB18_1:                               ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v5, s3, v4
	s_add_u32 s6, s0, -8
	s_addc_u32 s7, s1, -1
	s_add_i32 s3, s3, 58
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v6, vcc_lo
	s_clause 0x1
	global_load_b128 v[5:8], v[9:10], off
	global_load_b64 v[9:10], v[9:10], off offset:16
	s_clause 0x1
	s_load_b128 s[20:23], s[6:7], 0x0
	s_load_b64 s[6:7], s[0:1], 0x8
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s3, 0xce
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_mul_f64 v[7:8], v[7:8], s[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], v[5:6], s[20:21], v[7:8]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[5:6], v[9:10], s[6:7], v[5:6]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], v[5:6]
	s_cbranch_scc0 .LBB18_1
; %bb.2:
	s_ashr_i32 s3, s2, 31
	v_mad_u32_u24 v2, v2, 56, v3
	s_lshl_b64 s[0:1], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_add_u32 s4, s10, s0
	s_addc_u32 s5, s11, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[0:1], v[0:1], -s[4:5]
	s_add_u32 s4, s12, s0
	s_addc_u32 s5, s13, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[4:5], null, s[4:5], s[4:5], v[0:1]
	v_div_scale_f64 v[10:11], vcc_lo, v[0:1], s[4:5], v[0:1]
	v_rcp_f64_e32 v[6:7], v[4:5]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_mul_f64 v[8:9], v[10:11], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], -v[4:5], v[8:9], v[10:11]
	v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[0:1], v[4:5], s[4:5], v[0:1]
	s_add_u32 s4, s14, s0
	s_addc_u32 s5, s15, s1
	s_add_u32 s0, s16, s0
	s_addc_u32 s1, s17, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[0:1], v[0:1], s[4:5], s[0:1]
	s_mul_i32 s0, s2, 0xc40
	v_add3_u32 v2, v2, s0, 32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, 0, v1 :: v_dual_cndmask_b32 v0, 0, v0
	v_cmp_nlt_f64_e32 vcc_lo, 0x40180000, v[0:1]
	v_cndmask_b32_e32 v1, 0x40180000, v1, vcc_lo
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	global_store_b64 v[2:3], v[0:1], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z27executeSixthLayer_DSC_partBPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end18:
	.size	_Z27executeSixthLayer_DSC_partBPdS_S_S_S_S_S_, .Lfunc_end18-_Z27executeSixthLayer_DSC_partBPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 584
; NumSgprs: 26
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z27executeSixthLayer_DSC_partCPdS_S_S_S_S_S_ ; -- Begin function _Z27executeSixthLayer_DSC_partCPdS_S_S_S_S_S_
	.globl	_Z27executeSixthLayer_DSC_partCPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z27executeSixthLayer_DSC_partCPdS_S_S_S_S_S_,@function
_Z27executeSixthLayer_DSC_partCPdS_S_S_S_S_S_: ; @_Z27executeSixthLayer_DSC_partCPdS_S_S_S_S_S_
; %bb.0:
	s_mov_b32 s2, s15
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b256 s[12:19], s[0:1], 0x20
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v0, 0x3ff, v0
	s_mul_i32 s0, s2, 9
	s_mov_b32 s3, 0
	s_ashr_i32 s1, s0, 31
	v_mad_u64_u32 v[4:5], null, 0xd24, s2, v[1:2]
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0
	v_mul_u32_u24_e32 v5, 58, v0
	s_lshl_b64 s[0:1], s[0:1], 3
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v4, v4, v5, 0x740
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s0, s6
	s_addc_u32 s1, s1, s7
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB19_1:                               ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v5, s3, v4
	s_add_u32 s6, s0, -8
	s_addc_u32 s7, s1, -1
	s_add_i32 s3, s3, 58
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v6, vcc_lo
	s_clause 0x1
	global_load_b128 v[5:8], v[9:10], off
	global_load_b64 v[9:10], v[9:10], off offset:16
	s_clause 0x1
	s_load_b128 s[20:23], s[6:7], 0x0
	s_load_b64 s[6:7], s[0:1], 0x8
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s3, 0xae
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_mul_f64 v[7:8], v[7:8], s[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], v[5:6], s[20:21], v[7:8]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[5:6], v[9:10], s[6:7], v[5:6]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[2:3], v[2:3], v[5:6]
	s_cbranch_scc0 .LBB19_1
; %bb.2:
	s_ashr_i32 s3, s2, 31
	v_mul_u32_u24_e32 v0, 56, v0
	s_lshl_b64 s[0:1], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_add_u32 s4, s10, s0
	s_addc_u32 s5, s11, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[2:3], v[2:3], -s[4:5]
	s_add_u32 s4, s12, s0
	s_addc_u32 s5, s13, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[4:5], null, s[4:5], s[4:5], v[2:3]
	v_div_scale_f64 v[10:11], vcc_lo, v[2:3], s[4:5], v[2:3]
	v_rcp_f64_e32 v[6:7], v[4:5]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_mul_f64 v[8:9], v[10:11], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], -v[4:5], v[8:9], v[10:11]
	v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[2:3], v[4:5], s[4:5], v[2:3]
	s_add_u32 s4, s14, s0
	s_addc_u32 s5, s15, s1
	s_add_u32 s0, s16, s0
	s_addc_u32 s1, s17, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[2:3], v[2:3], s[4:5], s[0:1]
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, 0, v3 :: v_dual_cndmask_b32 v2, 0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_nlt_f64_e32 vcc_lo, 0x40180000, v[2:3]
	v_mad_u64_u32 v[4:5], null, 0xc40, s2, v[1:2]
	v_add3_u32 v0, v4, v0, 0x700
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_cndmask_b32_e32 v3, 0x40180000, v3, vcc_lo
	v_cndmask_b32_e32 v2, 0, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	global_store_b64 v[0:1], v[2:3], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z27executeSixthLayer_DSC_partCPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end19:
	.size	_Z27executeSixthLayer_DSC_partCPdS_S_S_S_S_S_, .Lfunc_end19-_Z27executeSixthLayer_DSC_partCPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 600
; NumSgprs: 26
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z27executeSixthLayer_DSC_partDPdS_S_S_S_S_S_ ; -- Begin function _Z27executeSixthLayer_DSC_partDPdS_S_S_S_S_S_
	.globl	_Z27executeSixthLayer_DSC_partDPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z27executeSixthLayer_DSC_partDPdS_S_S_S_S_S_,@function
_Z27executeSixthLayer_DSC_partDPdS_S_S_S_S_S_: ; @_Z27executeSixthLayer_DSC_partDPdS_S_S_S_S_S_
; %bb.0:
	s_mov_b32 s2, s15
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b256 s[12:19], s[0:1], 0x20
	v_bfe_u32 v1, v0, 10, 10
	v_and_b32_e32 v0, 0x3ff, v0
	s_mul_i32 s0, s2, 9
	s_mov_b32 s3, 0
	s_ashr_i32 s1, s0, 31
	v_mad_u64_u32 v[4:5], null, 0xd24, s2, v[1:2]
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0
	v_mul_u32_u24_e32 v5, 58, v0
	s_lshl_b64 s[0:1], s[0:1], 3
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v4, v4, v5, 0x760
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s0, s6
	s_addc_u32 s1, s1, s7
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB20_1:                               ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v5, s3, v4
	s_add_u32 s6, s0, -8
	s_addc_u32 s7, s1, -1
	s_add_i32 s3, s3, 58
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v6, vcc_lo
	s_clause 0x1
	global_load_b128 v[5:8], v[9:10], off
	global_load_b64 v[9:10], v[9:10], off offset:16
	s_clause 0x1
	s_load_b128 s[20:23], s[6:7], 0x0
	s_load_b64 s[6:7], s[0:1], 0x8
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s3, 0xae
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_mul_f64 v[7:8], v[7:8], s[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], v[5:6], s[20:21], v[7:8]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[5:6], v[9:10], s[6:7], v[5:6]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[2:3], v[2:3], v[5:6]
	s_cbranch_scc0 .LBB20_1
; %bb.2:
	s_ashr_i32 s3, s2, 31
	v_mul_u32_u24_e32 v0, 56, v0
	s_lshl_b64 s[0:1], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_add_u32 s4, s10, s0
	s_addc_u32 s5, s11, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[2:3], v[2:3], -s[4:5]
	s_add_u32 s4, s12, s0
	s_addc_u32 s5, s13, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[4:5], null, s[4:5], s[4:5], v[2:3]
	v_div_scale_f64 v[10:11], vcc_lo, v[2:3], s[4:5], v[2:3]
	v_rcp_f64_e32 v[6:7], v[4:5]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_mul_f64 v[8:9], v[10:11], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], -v[4:5], v[8:9], v[10:11]
	v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[2:3], v[4:5], s[4:5], v[2:3]
	s_add_u32 s4, s14, s0
	s_addc_u32 s5, s15, s1
	s_add_u32 s0, s16, s0
	s_addc_u32 s1, s17, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[2:3], v[2:3], s[4:5], s[0:1]
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, 0, v3 :: v_dual_cndmask_b32 v2, 0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_nlt_f64_e32 vcc_lo, 0x40180000, v[2:3]
	v_mad_u64_u32 v[4:5], null, 0xc40, s2, v[1:2]
	v_add3_u32 v0, v4, v0, 0x720
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_cndmask_b32_e32 v3, 0x40180000, v3, vcc_lo
	v_cndmask_b32_e32 v2, 0, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	global_store_b64 v[0:1], v[2:3], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z27executeSixthLayer_DSC_partDPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end20:
	.size	_Z27executeSixthLayer_DSC_partDPdS_S_S_S_S_S_, .Lfunc_end20-_Z27executeSixthLayer_DSC_partDPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 600
; NumSgprs: 26
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z29executeSeventhLayer_PSC_partAPdS_S_S_S_S_S_ ; -- Begin function _Z29executeSeventhLayer_PSC_partAPdS_S_S_S_S_S_
	.globl	_Z29executeSeventhLayer_PSC_partAPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z29executeSeventhLayer_PSC_partAPdS_S_S_S_S_S_,@function
_Z29executeSeventhLayer_PSC_partAPdS_S_S_S_S_S_: ; @_Z29executeSeventhLayer_PSC_partAPdS_S_S_S_S_S_
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_and_b32_e32 v4, 0x3ff, v0
	s_mov_b32 s2, s15
	s_load_b256 s[12:19], s[0:1], 0x20
	v_bfe_u32 v5, v0, 10, 10
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	v_mul_u32_u24_e32 v6, 56, v4
	s_lshl_b32 s0, s2, 7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_ashr_i32 s1, s0, 31
	v_add_lshl_u32 v2, v6, v5, 3
	s_lshl_b64 s[0:1], s[0:1], 3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v2, s3, s4, v2
	v_add_co_ci_u32_e64 v3, null, s5, 0, s3
	s_add_u32 s3, s6, s0
	s_addc_u32 s4, s7, s1
	s_mov_b64 s[0:1], 0
.LBB21_1:                               ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[7:8], v[2:3], off
	s_add_u32 s6, s3, s0
	s_addc_u32 s7, s4, s1
	v_add_co_u32 v2, vcc_lo, 0x6200, v2
	s_load_b64 s[6:7], s[6:7], 0x0
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s0, 0x400
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fma_f64 v[0:1], v[7:8], s[6:7], v[0:1]
	s_cbranch_scc0 .LBB21_1
; %bb.2:
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[2:3], 3
	s_add_u32 s4, s10, s0
	s_addc_u32 s5, s11, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], -s[4:5]
	s_add_u32 s4, s12, s0
	s_addc_u32 s5, s13, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_div_scale_f64 v[2:3], null, s[4:5], s[4:5], v[0:1]
	v_div_scale_f64 v[11:12], vcc_lo, v[0:1], s[4:5], v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[7:8], v[2:3]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[9:10], -v[2:3], v[7:8], 1.0
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], -v[2:3], v[7:8], 1.0
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[9:10], v[11:12], v[7:8]
	v_fma_f64 v[2:3], -v[2:3], v[9:10], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[2:3], v[2:3], v[7:8], v[9:10]
	v_div_fixup_f64 v[0:1], v[2:3], s[4:5], v[0:1]
	s_add_u32 s4, s14, s0
	s_addc_u32 s5, s15, s1
	s_add_u32 s0, s16, s0
	s_addc_u32 s1, s17, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	v_add_nc_u32_e32 v2, v6, v5
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[0:1], v[0:1], s[4:5], s[0:1]
	s_mul_i32 s0, s2, 0xcb1
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_add3_u32 v2, v2, v4, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, 0, v1 :: v_dual_cndmask_b32 v0, 0, v0
	v_cmp_nlt_f64_e32 vcc_lo, 0x40180000, v[0:1]
	v_cndmask_b32_e32 v1, 0x40180000, v1, vcc_lo
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	global_store_b64 v[2:3], v[0:1], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z29executeSeventhLayer_PSC_partAPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end21:
	.size	_Z29executeSeventhLayer_PSC_partAPdS_S_S_S_S_S_, .Lfunc_end21-_Z29executeSeventhLayer_PSC_partAPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 500
; NumSgprs: 22
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z29executeSeventhLayer_PSC_partBPdS_S_S_S_S_S_ ; -- Begin function _Z29executeSeventhLayer_PSC_partBPdS_S_S_S_S_S_
	.globl	_Z29executeSeventhLayer_PSC_partBPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z29executeSeventhLayer_PSC_partBPdS_S_S_S_S_S_,@function
_Z29executeSeventhLayer_PSC_partBPdS_S_S_S_S_S_: ; @_Z29executeSeventhLayer_PSC_partBPdS_S_S_S_S_S_
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_and_b32_e32 v4, 0x3ff, v0
	v_bfe_u32 v5, v0, 10, 10
	s_mov_b32 s2, s15
	s_load_b256 s[12:19], s[0:1], 0x20
	s_lshl_b32 s0, s2, 7
	v_mul_u32_u24_e32 v0, 56, v4
	s_ashr_i32 s1, s0, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_lshl_b64 s[0:1], s[0:1], 3
	v_add_lshl_u32 v2, v0, v5, 3
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v2, s3, v2, s4
	v_add_co_ci_u32_e64 v3, null, 0, s5, s3
	s_add_u32 s3, s6, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, 0x100, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_addc_u32 s4, s7, s1
	s_mov_b64 s[0:1], 0
.LBB22_1:                               ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[6:7], v[2:3], off
	s_add_u32 s6, s3, s0
	s_addc_u32 s7, s4, s1
	v_add_co_u32 v2, vcc_lo, 0x6200, v2
	s_load_b64 s[6:7], s[6:7], 0x0
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s0, 0x400
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fma_f64 v[0:1], v[6:7], s[6:7], v[0:1]
	s_cbranch_scc0 .LBB22_1
; %bb.2:
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[2:3], 3
	s_add_u32 s4, s10, s0
	s_addc_u32 s5, s11, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], -s[4:5]
	s_add_u32 s4, s12, s0
	s_addc_u32 s5, s13, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_div_scale_f64 v[2:3], null, s[4:5], s[4:5], v[0:1]
	v_div_scale_f64 v[10:11], vcc_lo, v[0:1], s[4:5], v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[6:7], v[2:3]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[2:3], v[6:7], 1.0
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], -v[2:3], v[6:7], 1.0
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[8:9], v[10:11], v[6:7]
	v_fma_f64 v[2:3], -v[2:3], v[8:9], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[2:3], v[2:3], v[6:7], v[8:9]
	v_div_fixup_f64 v[0:1], v[2:3], s[4:5], v[0:1]
	s_add_u32 s4, s14, s0
	s_addc_u32 s5, s15, s1
	s_add_u32 s0, s16, s0
	s_addc_u32 s1, s17, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	v_mad_u32_u24 v2, v4, 57, v5
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[0:1], v[0:1], s[4:5], s[0:1]
	s_mul_i32 s0, s2, 0xcb1
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_add3_u32 v2, v2, s0, 32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, 0, v1 :: v_dual_cndmask_b32 v0, 0, v0
	v_cmp_nlt_f64_e32 vcc_lo, 0x40180000, v[0:1]
	v_cndmask_b32_e32 v1, 0x40180000, v1, vcc_lo
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	global_store_b64 v[2:3], v[0:1], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z29executeSeventhLayer_PSC_partBPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end22:
	.size	_Z29executeSeventhLayer_PSC_partBPdS_S_S_S_S_S_, .Lfunc_end22-_Z29executeSeventhLayer_PSC_partBPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 524
; NumSgprs: 22
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z29executeSeventhLayer_PSC_partCPdS_S_S_S_S_S_ ; -- Begin function _Z29executeSeventhLayer_PSC_partCPdS_S_S_S_S_S_
	.globl	_Z29executeSeventhLayer_PSC_partCPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z29executeSeventhLayer_PSC_partCPdS_S_S_S_S_S_,@function
_Z29executeSeventhLayer_PSC_partCPdS_S_S_S_S_S_: ; @_Z29executeSeventhLayer_PSC_partCPdS_S_S_S_S_S_
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_and_b32_e32 v5, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_mov_b32 s2, s15
	s_load_b256 s[12:19], s[0:1], 0x20
	s_lshl_b32 s0, s2, 7
	v_mul_u32_u24_e32 v1, 56, v5
	s_ashr_i32 s1, s0, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_lshl_b64 s[0:1], s[0:1], 3
	v_add_lshl_u32 v3, v1, v0, 3
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v3, s3, v3, s4
	v_add_co_ci_u32_e64 v4, null, 0, s5, s3
	s_add_u32 s3, s6, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, 0x3800, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
	s_addc_u32 s4, s7, s1
	s_mov_b64 s[0:1], 0
.LBB23_1:                               ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[6:7], v[3:4], off
	s_add_u32 s6, s3, s0
	s_addc_u32 s7, s4, s1
	v_add_co_u32 v3, vcc_lo, 0x6200, v3
	s_load_b64 s[6:7], s[6:7], 0x0
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s0, 0x400
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fma_f64 v[1:2], v[6:7], s[6:7], v[1:2]
	s_cbranch_scc0 .LBB23_1
; %bb.2:
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[2:3], 3
	s_add_u32 s4, s10, s0
	s_addc_u32 s5, s11, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_f64 v[1:2], v[1:2], -s[4:5]
	s_add_u32 s4, s12, s0
	s_addc_u32 s5, s13, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_div_scale_f64 v[3:4], null, s[4:5], s[4:5], v[1:2]
	v_div_scale_f64 v[10:11], vcc_lo, v[1:2], s[4:5], v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[6:7], v[3:4]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[3:4], v[6:7], 1.0
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], -v[3:4], v[6:7], 1.0
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[8:9], v[10:11], v[6:7]
	v_fma_f64 v[3:4], -v[3:4], v[8:9], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[3:4], v[3:4], v[6:7], v[8:9]
	v_div_fixup_f64 v[1:2], v[3:4], s[4:5], v[1:2]
	s_add_u32 s4, s14, s0
	s_addc_u32 s5, s15, s1
	s_add_u32 s0, s16, s0
	s_addc_u32 s1, s17, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[1:2], v[1:2], s[4:5], s[0:1]
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[1:2]
	v_dual_cndmask_b32 v2, 0, v2 :: v_dual_cndmask_b32 v1, 0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_nlt_f64_e32 vcc_lo, 0x40180000, v[1:2]
	v_mad_u64_u32 v[3:4], null, 0xcb1, s2, v[0:1]
	v_mul_u32_u24_e32 v0, 57, v5
	v_add3_u32 v3, v3, v0, 0x720
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	v_cndmask_b32_e32 v2, 0x40180000, v2, vcc_lo
	v_cndmask_b32_e32 v1, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s8, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
	global_store_b64 v[3:4], v[1:2], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z29executeSeventhLayer_PSC_partCPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end23:
	.size	_Z29executeSeventhLayer_PSC_partCPdS_S_S_S_S_S_, .Lfunc_end23-_Z29executeSeventhLayer_PSC_partCPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 528
; NumSgprs: 22
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z29executeSeventhLayer_PSC_partDPdS_S_S_S_S_S_ ; -- Begin function _Z29executeSeventhLayer_PSC_partDPdS_S_S_S_S_S_
	.globl	_Z29executeSeventhLayer_PSC_partDPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z29executeSeventhLayer_PSC_partDPdS_S_S_S_S_S_,@function
_Z29executeSeventhLayer_PSC_partDPdS_S_S_S_S_S_: ; @_Z29executeSeventhLayer_PSC_partDPdS_S_S_S_S_S_
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_and_b32_e32 v5, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_mov_b32 s2, s15
	s_load_b256 s[12:19], s[0:1], 0x20
	s_lshl_b32 s0, s2, 7
	v_mul_u32_u24_e32 v1, 56, v5
	s_ashr_i32 s1, s0, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_lshl_b64 s[0:1], s[0:1], 3
	v_add_lshl_u32 v3, v1, v0, 3
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v3, s3, v3, s4
	v_add_co_ci_u32_e64 v4, null, 0, s5, s3
	s_add_u32 s3, s6, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, 0x3900, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
	s_addc_u32 s4, s7, s1
	s_mov_b64 s[0:1], 0
.LBB24_1:                               ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[6:7], v[3:4], off
	s_add_u32 s6, s3, s0
	s_addc_u32 s7, s4, s1
	v_add_co_u32 v3, vcc_lo, 0x6200, v3
	s_load_b64 s[6:7], s[6:7], 0x0
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s0, 0x400
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fma_f64 v[1:2], v[6:7], s[6:7], v[1:2]
	s_cbranch_scc0 .LBB24_1
; %bb.2:
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[2:3], 3
	s_add_u32 s4, s10, s0
	s_addc_u32 s5, s11, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_f64 v[1:2], v[1:2], -s[4:5]
	s_add_u32 s4, s12, s0
	s_addc_u32 s5, s13, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_div_scale_f64 v[3:4], null, s[4:5], s[4:5], v[1:2]
	v_div_scale_f64 v[10:11], vcc_lo, v[1:2], s[4:5], v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[6:7], v[3:4]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[3:4], v[6:7], 1.0
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], -v[3:4], v[6:7], 1.0
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[8:9], v[10:11], v[6:7]
	v_fma_f64 v[3:4], -v[3:4], v[8:9], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[3:4], v[3:4], v[6:7], v[8:9]
	v_div_fixup_f64 v[1:2], v[3:4], s[4:5], v[1:2]
	s_add_u32 s4, s14, s0
	s_addc_u32 s5, s15, s1
	s_add_u32 s0, s16, s0
	s_addc_u32 s1, s17, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[1:2], v[1:2], s[4:5], s[0:1]
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[1:2]
	v_dual_cndmask_b32 v2, 0, v2 :: v_dual_cndmask_b32 v1, 0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cmp_nlt_f64_e32 vcc_lo, 0x40180000, v[1:2]
	v_mad_u64_u32 v[3:4], null, 0xcb1, s2, v[0:1]
	v_mul_u32_u24_e32 v0, 57, v5
	v_add3_u32 v3, v3, v0, 0x740
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	v_cndmask_b32_e32 v2, 0x40180000, v2, vcc_lo
	v_cndmask_b32_e32 v1, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s8, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
	global_store_b64 v[3:4], v[1:2], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z29executeSeventhLayer_PSC_partDPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end24:
	.size	_Z29executeSeventhLayer_PSC_partDPdS_S_S_S_S_S_, .Lfunc_end24-_Z29executeSeventhLayer_PSC_partDPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 528
; NumSgprs: 22
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z22executeEighthLayer_DSCPdS_S_S_S_S_S_ ; -- Begin function _Z22executeEighthLayer_DSCPdS_S_S_S_S_S_
	.globl	_Z22executeEighthLayer_DSCPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z22executeEighthLayer_DSCPdS_S_S_S_S_S_,@function
_Z22executeEighthLayer_DSCPdS_S_S_S_S_S_: ; @_Z22executeEighthLayer_DSCPdS_S_S_S_S_S_
; %bb.0:
	s_mov_b32 s2, s15
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b256 s[12:19], s[0:1], 0x20
	v_and_b32_e32 v3, 0x3ff, v0
	v_bfe_u32 v2, v0, 10, 10
	v_mov_b32_e32 v0, 0
	s_mul_i32 s0, s2, 9
	s_mul_i32 s3, s2, 0xcb1
	v_mul_u32_u24_e32 v4, 0x72, v3
	v_lshlrev_b32_e32 v5, 1, v2
	s_ashr_i32 s1, s0, 31
	v_mov_b32_e32 v1, 0
	s_lshl_b64 s[0:1], s[0:1], 3
	s_delay_alu instid0(VALU_DEP_2)
	v_add3_u32 v4, v4, v5, s3
	s_mov_b32 s3, 0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s0, s6
	s_addc_u32 s1, s1, s7
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB25_1:                               ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v5, s3, v4
	s_add_u32 s6, s0, -8
	s_addc_u32 s7, s1, -1
	s_add_i32 s3, s3, 57
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v6, vcc_lo
	s_clause 0x1
	global_load_b128 v[5:8], v[9:10], off
	global_load_b64 v[9:10], v[9:10], off offset:16
	s_clause 0x1
	s_load_b128 s[20:23], s[6:7], 0x0
	s_load_b64 s[6:7], s[0:1], 0x8
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s3, 0xab
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_mul_f64 v[7:8], v[7:8], s[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], v[5:6], s[20:21], v[7:8]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[5:6], v[9:10], s[6:7], v[5:6]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], v[5:6]
	s_cbranch_scc0 .LBB25_1
; %bb.2:
	s_ashr_i32 s3, s2, 31
	v_mul_u32_u24_e32 v3, 28, v3
	s_lshl_b64 s[0:1], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_add_u32 s4, s10, s0
	s_addc_u32 s5, s11, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[0:1], v[0:1], -s[4:5]
	s_add_u32 s4, s12, s0
	s_addc_u32 s5, s13, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[4:5], null, s[4:5], s[4:5], v[0:1]
	v_div_scale_f64 v[10:11], vcc_lo, v[0:1], s[4:5], v[0:1]
	v_rcp_f64_e32 v[6:7], v[4:5]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_mul_f64 v[8:9], v[10:11], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], -v[4:5], v[8:9], v[10:11]
	v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[0:1], v[4:5], s[4:5], v[0:1]
	s_add_u32 s4, s14, s0
	s_addc_u32 s5, s15, s1
	s_add_u32 s0, s16, s0
	s_addc_u32 s1, s17, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[0:1], v[0:1], s[4:5], s[0:1]
	s_mul_i32 s0, s2, 0x310
	v_add3_u32 v2, v3, v2, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, 0, v1 :: v_dual_cndmask_b32 v0, 0, v0
	v_cmp_nlt_f64_e32 vcc_lo, 0x40180000, v[0:1]
	v_cndmask_b32_e32 v1, 0x40180000, v1, vcc_lo
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	global_store_b64 v[2:3], v[0:1], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z22executeEighthLayer_DSCPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end25:
	.size	_Z22executeEighthLayer_DSCPdS_S_S_S_S_S_, .Lfunc_end25-_Z22executeEighthLayer_DSCPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 588
; NumSgprs: 26
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z21executeNinthLayer_PSCPdS_S_S_S_S_S_ ; -- Begin function _Z21executeNinthLayer_PSCPdS_S_S_S_S_S_
	.globl	_Z21executeNinthLayer_PSCPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z21executeNinthLayer_PSCPdS_S_S_S_S_S_,@function
_Z21executeNinthLayer_PSCPdS_S_S_S_S_S_: ; @_Z21executeNinthLayer_PSCPdS_S_S_S_S_S_
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_and_b32_e32 v4, 0x3ff, v0
	s_mov_b32 s2, s15
	s_load_b256 s[12:19], s[0:1], 0x20
	v_bfe_u32 v5, v0, 10, 10
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	v_mul_u32_u24_e32 v6, 28, v4
	s_lshl_b32 s0, s2, 7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_ashr_i32 s1, s0, 31
	v_add_lshl_u32 v2, v6, v5, 3
	s_lshl_b64 s[0:1], s[0:1], 3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v2, s3, s4, v2
	v_add_co_ci_u32_e64 v3, null, s5, 0, s3
	s_add_u32 s3, s6, s0
	s_addc_u32 s4, s7, s1
	s_mov_b64 s[0:1], 0
.LBB26_1:                               ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[7:8], v[2:3], off
	s_add_u32 s6, s3, s0
	s_addc_u32 s7, s4, s1
	v_add_co_u32 v2, vcc_lo, 0x1880, v2
	s_load_b64 s[6:7], s[6:7], 0x0
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s0, 0x400
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fma_f64 v[0:1], v[7:8], s[6:7], v[0:1]
	s_cbranch_scc0 .LBB26_1
; %bb.2:
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[2:3], 3
	s_add_u32 s4, s10, s0
	s_addc_u32 s5, s11, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], -s[4:5]
	s_add_u32 s4, s12, s0
	s_addc_u32 s5, s13, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_div_scale_f64 v[2:3], null, s[4:5], s[4:5], v[0:1]
	v_div_scale_f64 v[11:12], vcc_lo, v[0:1], s[4:5], v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[7:8], v[2:3]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[9:10], -v[2:3], v[7:8], 1.0
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], -v[2:3], v[7:8], 1.0
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[9:10], v[11:12], v[7:8]
	v_fma_f64 v[2:3], -v[2:3], v[9:10], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[2:3], v[2:3], v[7:8], v[9:10]
	v_div_fixup_f64 v[0:1], v[2:3], s[4:5], v[0:1]
	s_add_u32 s4, s14, s0
	s_addc_u32 s5, s15, s1
	s_add_u32 s0, s16, s0
	s_addc_u32 s1, s17, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	v_add_nc_u32_e32 v2, v6, v5
	v_lshlrev_b32_e32 v3, 1, v4
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f64 v[0:1], v[0:1], s[4:5], s[0:1]
	s_mul_i32 s0, s2, 0x384
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_add3_u32 v2, v2, v3, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, 0, v1 :: v_dual_cndmask_b32 v0, 0, v0
	v_cmp_nlt_f64_e32 vcc_lo, 0x40180000, v[0:1]
	v_cndmask_b32_e32 v1, 0x40180000, v1, vcc_lo
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	global_store_b64 v[2:3], v[0:1], off offset:248
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z21executeNinthLayer_PSCPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end26:
	.size	_Z21executeNinthLayer_PSCPdS_S_S_S_S_S_, .Lfunc_end26-_Z21executeNinthLayer_PSCPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 504
; NumSgprs: 22
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z21executeTenthLayer_DSCPdS_S_S_S_S_S_ ; -- Begin function _Z21executeTenthLayer_DSCPdS_S_S_S_S_S_
	.globl	_Z21executeTenthLayer_DSCPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z21executeTenthLayer_DSCPdS_S_S_S_S_S_,@function
_Z21executeTenthLayer_DSCPdS_S_S_S_S_S_: ; @_Z21executeTenthLayer_DSCPdS_S_S_S_S_S_
; %bb.0:
	s_mov_b32 s2, s15
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b256 s[12:19], s[0:1], 0x20
	v_and_b32_e32 v2, 0x3ff, v0
	s_mul_i32 s0, s2, 9
	v_bfe_u32 v3, v0, 10, 10
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	v_mul_u32_u24_e32 v4, 30, v2
	s_ashr_i32 s1, s0, 31
	s_mul_i32 s3, s2, 0x384
	s_lshl_b64 s[0:1], s[0:1], 3
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v4, v3, s3, v4
	s_mov_b32 s3, 0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s0, s6
	s_addc_u32 s1, s1, s7
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB27_1:                               ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v5, s3, v4
	s_add_u32 s6, s0, -8
	s_addc_u32 s7, s1, -1
	s_add_i32 s3, s3, 30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v6, vcc_lo
	s_clause 0x1
	global_load_b128 v[5:8], v[9:10], off
	global_load_b64 v[9:10], v[9:10], off offset:16
	s_clause 0x1
	s_load_b128 s[20:23], s[6:7], 0x0
	s_load_b64 s[6:7], s[0:1], 0x8
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s3, 0x5a
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_mul_f64 v[7:8], v[7:8], s[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], v[5:6], s[20:21], v[7:8]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[5:6], v[9:10], s[6:7], v[5:6]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], v[5:6]
	s_cbranch_scc0 .LBB27_1
; %bb.2:
	s_ashr_i32 s3, s2, 31
	v_mul_u32_u24_e32 v2, 28, v2
	s_lshl_b64 s[0:1], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_add_u32 s4, s10, s0
	s_addc_u32 s5, s11, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[0:1], v[0:1], -s[4:5]
	s_add_u32 s4, s12, s0
	s_addc_u32 s5, s13, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[4:5], null, s[4:5], s[4:5], v[0:1]
	v_div_scale_f64 v[10:11], vcc_lo, v[0:1], s[4:5], v[0:1]
	v_rcp_f64_e32 v[6:7], v[4:5]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_mul_f64 v[8:9], v[10:11], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], -v[4:5], v[8:9], v[10:11]
	v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[0:1], v[4:5], s[4:5], v[0:1]
	s_add_u32 s4, s14, s0
	s_addc_u32 s5, s15, s1
	s_add_u32 s0, s16, s0
	s_addc_u32 s1, s17, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[0:1], v[0:1], s[4:5], s[0:1]
	s_mul_i32 s0, s2, 0x310
	v_add3_u32 v2, v2, v3, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, 0, v1 :: v_dual_cndmask_b32 v0, 0, v0
	v_cmp_nlt_f64_e32 vcc_lo, 0x40180000, v[0:1]
	v_cndmask_b32_e32 v1, 0x40180000, v1, vcc_lo
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	global_store_b64 v[2:3], v[0:1], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z21executeTenthLayer_DSCPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end27:
	.size	_Z21executeTenthLayer_DSCPdS_S_S_S_S_S_, .Lfunc_end27-_Z21executeTenthLayer_DSCPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 580
; NumSgprs: 26
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z24executeEleventhLayer_PSCPdS_S_S_S_S_S_ ; -- Begin function _Z24executeEleventhLayer_PSCPdS_S_S_S_S_S_
	.globl	_Z24executeEleventhLayer_PSCPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z24executeEleventhLayer_PSCPdS_S_S_S_S_S_,@function
_Z24executeEleventhLayer_PSCPdS_S_S_S_S_S_: ; @_Z24executeEleventhLayer_PSCPdS_S_S_S_S_S_
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_and_b32_e32 v4, 0x3ff, v0
	s_mov_b32 s2, s15
	s_load_b256 s[12:19], s[0:1], 0x20
	v_bfe_u32 v5, v0, 10, 10
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	v_mul_u32_u24_e32 v6, 28, v4
	s_lshl_b32 s0, s2, 8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_ashr_i32 s1, s0, 31
	v_add_lshl_u32 v2, v6, v5, 3
	s_lshl_b64 s[0:1], s[0:1], 3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v2, s3, s4, v2
	v_add_co_ci_u32_e64 v3, null, s5, 0, s3
	s_add_u32 s3, s6, s0
	s_addc_u32 s4, s7, s1
	s_mov_b64 s[0:1], 0
.LBB28_1:                               ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[7:8], v[2:3], off
	s_add_u32 s6, s3, s0
	s_addc_u32 s7, s4, s1
	v_add_co_u32 v2, vcc_lo, 0x1880, v2
	s_load_b64 s[6:7], s[6:7], 0x0
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s0, 0x800
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fma_f64 v[0:1], v[7:8], s[6:7], v[0:1]
	s_cbranch_scc0 .LBB28_1
; %bb.2:
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[2:3], 3
	s_add_u32 s4, s10, s0
	s_addc_u32 s5, s11, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], -s[4:5]
	s_add_u32 s4, s12, s0
	s_addc_u32 s5, s13, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_div_scale_f64 v[2:3], null, s[4:5], s[4:5], v[0:1]
	v_div_scale_f64 v[11:12], vcc_lo, v[0:1], s[4:5], v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[7:8], v[2:3]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[9:10], -v[2:3], v[7:8], 1.0
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], -v[2:3], v[7:8], 1.0
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[9:10], v[11:12], v[7:8]
	v_fma_f64 v[2:3], -v[2:3], v[9:10], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[2:3], v[2:3], v[7:8], v[9:10]
	v_div_fixup_f64 v[0:1], v[2:3], s[4:5], v[0:1]
	s_add_u32 s4, s14, s0
	s_addc_u32 s5, s15, s1
	s_add_u32 s0, s16, s0
	s_addc_u32 s1, s17, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	v_add_nc_u32_e32 v2, v6, v5
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[0:1], v[0:1], s[4:5], s[0:1]
	s_mul_i32 s0, s2, 0x349
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_add3_u32 v2, v2, v4, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, 0, v1 :: v_dual_cndmask_b32 v0, 0, v0
	v_cmp_nlt_f64_e32 vcc_lo, 0x40180000, v[0:1]
	v_cndmask_b32_e32 v1, 0x40180000, v1, vcc_lo
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	global_store_b64 v[2:3], v[0:1], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z24executeEleventhLayer_PSCPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end28:
	.size	_Z24executeEleventhLayer_PSCPdS_S_S_S_S_S_, .Lfunc_end28-_Z24executeEleventhLayer_PSCPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 500
; NumSgprs: 22
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z23executeTwelfthLayer_DSCPdS_S_S_S_S_S_ ; -- Begin function _Z23executeTwelfthLayer_DSCPdS_S_S_S_S_S_
	.globl	_Z23executeTwelfthLayer_DSCPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z23executeTwelfthLayer_DSCPdS_S_S_S_S_S_,@function
_Z23executeTwelfthLayer_DSCPdS_S_S_S_S_S_: ; @_Z23executeTwelfthLayer_DSCPdS_S_S_S_S_S_
; %bb.0:
	s_mov_b32 s2, s15
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b256 s[12:19], s[0:1], 0x20
	v_and_b32_e32 v3, 0x3ff, v0
	v_bfe_u32 v2, v0, 10, 10
	v_mov_b32_e32 v0, 0
	s_mul_i32 s0, s2, 9
	s_mul_i32 s3, s2, 0x349
	v_mul_u32_u24_e32 v4, 58, v3
	v_lshlrev_b32_e32 v5, 1, v2
	s_ashr_i32 s1, s0, 31
	v_mov_b32_e32 v1, 0
	s_lshl_b64 s[0:1], s[0:1], 3
	s_delay_alu instid0(VALU_DEP_2)
	v_add3_u32 v4, v4, v5, s3
	s_mov_b32 s3, 0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s0, s6
	s_addc_u32 s1, s1, s7
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB29_1:                               ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v5, s3, v4
	s_add_u32 s6, s0, -8
	s_addc_u32 s7, s1, -1
	s_add_i32 s3, s3, 29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v6, vcc_lo
	s_clause 0x1
	global_load_b128 v[5:8], v[9:10], off
	global_load_b64 v[9:10], v[9:10], off offset:16
	s_clause 0x1
	s_load_b128 s[20:23], s[6:7], 0x0
	s_load_b64 s[6:7], s[0:1], 0x8
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s3, 0x57
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_mul_f64 v[7:8], v[7:8], s[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], v[5:6], s[20:21], v[7:8]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[5:6], v[9:10], s[6:7], v[5:6]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], v[5:6]
	s_cbranch_scc0 .LBB29_1
; %bb.2:
	s_ashr_i32 s3, s2, 31
	v_mul_u32_u24_e32 v3, 14, v3
	s_lshl_b64 s[0:1], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_add_u32 s4, s10, s0
	s_addc_u32 s5, s11, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[0:1], v[0:1], -s[4:5]
	s_add_u32 s4, s12, s0
	s_addc_u32 s5, s13, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[4:5], null, s[4:5], s[4:5], v[0:1]
	v_div_scale_f64 v[10:11], vcc_lo, v[0:1], s[4:5], v[0:1]
	v_rcp_f64_e32 v[6:7], v[4:5]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_mul_f64 v[8:9], v[10:11], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], -v[4:5], v[8:9], v[10:11]
	v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[0:1], v[4:5], s[4:5], v[0:1]
	s_add_u32 s4, s14, s0
	s_addc_u32 s5, s15, s1
	s_add_u32 s0, s16, s0
	s_addc_u32 s1, s17, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[0:1], v[0:1], s[4:5], s[0:1]
	s_mul_i32 s0, s2, 0xc4
	v_add3_u32 v2, v3, v2, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, 0, v1 :: v_dual_cndmask_b32 v0, 0, v0
	v_cmp_nlt_f64_e32 vcc_lo, 0x40180000, v[0:1]
	v_cndmask_b32_e32 v1, 0x40180000, v1, vcc_lo
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	global_store_b64 v[2:3], v[0:1], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z23executeTwelfthLayer_DSCPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end29:
	.size	_Z23executeTwelfthLayer_DSCPdS_S_S_S_S_S_, .Lfunc_end29-_Z23executeTwelfthLayer_DSCPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 584
; NumSgprs: 26
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z26executeThirteenthLayer_PSCPdS_S_S_S_S_S_ ; -- Begin function _Z26executeThirteenthLayer_PSCPdS_S_S_S_S_S_
	.globl	_Z26executeThirteenthLayer_PSCPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z26executeThirteenthLayer_PSCPdS_S_S_S_S_S_,@function
_Z26executeThirteenthLayer_PSCPdS_S_S_S_S_S_: ; @_Z26executeThirteenthLayer_PSCPdS_S_S_S_S_S_
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_and_b32_e32 v4, 0x3ff, v0
	s_mov_b32 s2, s15
	s_load_b256 s[12:19], s[0:1], 0x20
	v_bfe_u32 v5, v0, 10, 10
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	v_mul_u32_u24_e32 v6, 14, v4
	s_lshl_b32 s0, s2, 8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_ashr_i32 s1, s0, 31
	v_add_lshl_u32 v2, v6, v5, 3
	s_waitcnt lgkmcnt(0)
	s_lshl_b64 s[18:19], s[0:1], 3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v2, s1, s4, v2
	v_add_co_ci_u32_e64 v3, null, s5, 0, s1
	s_add_u32 s1, s6, s18
	s_addc_u32 s3, s7, s19
	s_mov_b64 s[4:5], 0
.LBB30_1:                               ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[7:8], v[2:3], off
	s_add_u32 s6, s1, s4
	s_addc_u32 s7, s3, s5
	v_add_co_u32 v2, vcc_lo, 0x620, v2
	s_load_b64 s[6:7], s[6:7], 0x0
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_add_u32 s4, s4, 8
	s_addc_u32 s5, s5, 0
	s_cmpk_eq_i32 s4, 0x800
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fma_f64 v[0:1], v[7:8], s[6:7], v[0:1]
	s_cbranch_scc0 .LBB30_1
; %bb.2:
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[2:3], s[2:3], 3
	s_add_u32 s4, s10, s2
	s_addc_u32 s5, s11, s3
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], -s[4:5]
	s_add_u32 s4, s12, s2
	s_addc_u32 s5, s13, s3
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_div_scale_f64 v[2:3], null, s[4:5], s[4:5], v[0:1]
	v_div_scale_f64 v[11:12], vcc_lo, v[0:1], s[4:5], v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[7:8], v[2:3]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[9:10], -v[2:3], v[7:8], 1.0
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], -v[2:3], v[7:8], 1.0
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[9:10], v[11:12], v[7:8]
	v_fma_f64 v[2:3], -v[2:3], v[9:10], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[2:3], v[2:3], v[7:8], v[9:10]
	v_div_fixup_f64 v[0:1], v[2:3], s[4:5], v[0:1]
	s_add_u32 s4, s14, s2
	s_addc_u32 s5, s15, s3
	s_add_u32 s2, s16, s2
	s_addc_u32 s3, s17, s3
	s_load_b64 s[4:5], s[4:5], 0x0
	s_load_b64 s[2:3], s[2:3], 0x0
	v_add_nc_u32_e32 v2, v6, v5
	v_lshlrev_b32_e32 v3, 1, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v2, v2, v3, s0
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[0:1], v[0:1], s[4:5], s[2:3]
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, 0, v1 :: v_dual_cndmask_b32 v0, 0, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_nlt_f64_e32 vcc_lo, 0x40180000, v[0:1]
	v_cndmask_b32_e32 v1, 0x40180000, v1, vcc_lo
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	global_store_b64 v[2:3], v[0:1], off offset:136
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z26executeThirteenthLayer_PSCPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end30:
	.size	_Z26executeThirteenthLayer_PSCPdS_S_S_S_S_S_, .Lfunc_end30-_Z26executeThirteenthLayer_PSCPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 492
; NumSgprs: 22
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z26executeFourteenthLayer_DSCPdS_S_S_S_S_S_ ; -- Begin function _Z26executeFourteenthLayer_DSCPdS_S_S_S_S_S_
	.globl	_Z26executeFourteenthLayer_DSCPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z26executeFourteenthLayer_DSCPdS_S_S_S_S_S_,@function
_Z26executeFourteenthLayer_DSCPdS_S_S_S_S_S_: ; @_Z26executeFourteenthLayer_DSCPdS_S_S_S_S_S_
; %bb.0:
	s_mov_b32 s2, s15
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b256 s[12:19], s[0:1], 0x20
	v_and_b32_e32 v2, 0x3ff, v0
	s_mul_i32 s0, s2, 9
	v_bfe_u32 v3, v0, 10, 10
	v_mov_b32_e32 v0, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v4, 4, v2
	s_ashr_i32 s1, s0, 31
	s_lshl_b32 s3, s2, 8
	s_lshl_b64 s[0:1], s[0:1], 3
	v_add3_u32 v4, v3, s3, v4
	s_mov_b32 s3, 0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s0, s6
	s_addc_u32 s1, s1, s7
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB31_1:                               ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v5, s3, v4
	s_add_u32 s6, s0, -8
	s_addc_u32 s7, s1, -1
	s_add_i32 s3, s3, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v6, vcc_lo
	s_clause 0x1
	global_load_b128 v[5:8], v[9:10], off
	global_load_b64 v[9:10], v[9:10], off offset:16
	s_clause 0x1
	s_load_b128 s[20:23], s[6:7], 0x0
	s_load_b64 s[6:7], s[0:1], 0x8
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_cmp_eq_u32 s3, 48
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_mul_f64 v[7:8], v[7:8], s[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], v[5:6], s[20:21], v[7:8]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[5:6], v[9:10], s[6:7], v[5:6]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], v[5:6]
	s_cbranch_scc0 .LBB31_1
; %bb.2:
	s_ashr_i32 s3, s2, 31
	v_mul_u32_u24_e32 v2, 14, v2
	s_lshl_b64 s[0:1], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_add_u32 s4, s10, s0
	s_addc_u32 s5, s11, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[0:1], v[0:1], -s[4:5]
	s_add_u32 s4, s12, s0
	s_addc_u32 s5, s13, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[4:5], null, s[4:5], s[4:5], v[0:1]
	v_div_scale_f64 v[10:11], vcc_lo, v[0:1], s[4:5], v[0:1]
	v_rcp_f64_e32 v[6:7], v[4:5]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_mul_f64 v[8:9], v[10:11], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], -v[4:5], v[8:9], v[10:11]
	v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[0:1], v[4:5], s[4:5], v[0:1]
	s_add_u32 s4, s14, s0
	s_addc_u32 s5, s15, s1
	s_add_u32 s0, s16, s0
	s_addc_u32 s1, s17, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[0:1], v[0:1], s[4:5], s[0:1]
	s_mul_i32 s0, s2, 0xc4
	v_add3_u32 v2, v2, v3, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, 0, v1 :: v_dual_cndmask_b32 v0, 0, v0
	v_cmp_nlt_f64_e32 vcc_lo, 0x40180000, v[0:1]
	v_cndmask_b32_e32 v1, 0x40180000, v1, vcc_lo
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	global_store_b64 v[2:3], v[0:1], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z26executeFourteenthLayer_DSCPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end31:
	.size	_Z26executeFourteenthLayer_DSCPdS_S_S_S_S_S_, .Lfunc_end31-_Z26executeFourteenthLayer_DSCPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 576
; NumSgprs: 26
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z25executeFifteenthLayer_PSCPdS_S_S_S_S_S_ ; -- Begin function _Z25executeFifteenthLayer_PSCPdS_S_S_S_S_S_
	.globl	_Z25executeFifteenthLayer_PSCPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z25executeFifteenthLayer_PSCPdS_S_S_S_S_S_,@function
_Z25executeFifteenthLayer_PSCPdS_S_S_S_S_S_: ; @_Z25executeFifteenthLayer_PSCPdS_S_S_S_S_S_
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_and_b32_e32 v4, 0x3ff, v0
	s_mov_b32 s2, s15
	s_load_b256 s[12:19], s[0:1], 0x20
	v_bfe_u32 v5, v0, 10, 10
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	v_mul_u32_u24_e32 v6, 14, v4
	s_lshl_b32 s0, s2, 9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_ashr_i32 s1, s0, 31
	v_add_lshl_u32 v2, v6, v5, 3
	s_lshl_b64 s[0:1], s[0:1], 3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v2, s3, s4, v2
	v_add_co_ci_u32_e64 v3, null, s5, 0, s3
	s_add_u32 s3, s6, s0
	s_addc_u32 s4, s7, s1
	s_mov_b64 s[0:1], 0
.LBB32_1:                               ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[7:8], v[2:3], off
	s_add_u32 s6, s3, s0
	s_addc_u32 s7, s4, s1
	v_add_co_u32 v2, vcc_lo, 0x620, v2
	s_load_b64 s[6:7], s[6:7], 0x0
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s0, 0x1000
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fma_f64 v[0:1], v[7:8], s[6:7], v[0:1]
	s_cbranch_scc0 .LBB32_1
; %bb.2:
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[2:3], 3
	s_add_u32 s4, s10, s0
	s_addc_u32 s5, s11, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], -s[4:5]
	s_add_u32 s4, s12, s0
	s_addc_u32 s5, s13, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_div_scale_f64 v[2:3], null, s[4:5], s[4:5], v[0:1]
	v_div_scale_f64 v[11:12], vcc_lo, v[0:1], s[4:5], v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[7:8], v[2:3]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[9:10], -v[2:3], v[7:8], 1.0
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], -v[2:3], v[7:8], 1.0
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[9:10], v[11:12], v[7:8]
	v_fma_f64 v[2:3], -v[2:3], v[9:10], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[2:3], v[2:3], v[7:8], v[9:10]
	v_div_fixup_f64 v[0:1], v[2:3], s[4:5], v[0:1]
	s_add_u32 s4, s14, s0
	s_addc_u32 s5, s15, s1
	s_add_u32 s0, s16, s0
	s_addc_u32 s1, s17, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	v_add_nc_u32_e32 v2, v6, v5
	v_lshlrev_b32_e32 v3, 1, v4
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f64 v[0:1], v[0:1], s[4:5], s[0:1]
	s_lshl_b32 s0, s2, 8
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_add3_u32 v2, v2, v3, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, 0, v1 :: v_dual_cndmask_b32 v0, 0, v0
	v_cmp_nlt_f64_e32 vcc_lo, 0x40180000, v[0:1]
	v_cndmask_b32_e32 v1, 0x40180000, v1, vcc_lo
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	global_store_b64 v[2:3], v[0:1], off offset:136
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z25executeFifteenthLayer_PSCPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end32:
	.size	_Z25executeFifteenthLayer_PSCPdS_S_S_S_S_S_, .Lfunc_end32-_Z25executeFifteenthLayer_PSCPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 500
; NumSgprs: 22
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z25executeSixteenthLayer_DSCPdS_S_S_S_S_S_ ; -- Begin function _Z25executeSixteenthLayer_DSCPdS_S_S_S_S_S_
	.globl	_Z25executeSixteenthLayer_DSCPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z25executeSixteenthLayer_DSCPdS_S_S_S_S_S_,@function
_Z25executeSixteenthLayer_DSCPdS_S_S_S_S_S_: ; @_Z25executeSixteenthLayer_DSCPdS_S_S_S_S_S_
; %bb.0:
	s_mov_b32 s2, s15
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b256 s[12:19], s[0:1], 0x20
	v_and_b32_e32 v2, 0x3ff, v0
	s_mul_i32 s0, s2, 9
	v_bfe_u32 v3, v0, 10, 10
	v_mov_b32_e32 v0, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v4, 4, v2
	s_ashr_i32 s1, s0, 31
	s_lshl_b32 s3, s2, 8
	s_lshl_b64 s[0:1], s[0:1], 3
	v_add3_u32 v4, v3, s3, v4
	s_mov_b32 s3, 0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s0, s6
	s_addc_u32 s1, s1, s7
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB33_1:                               ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v5, s3, v4
	s_add_u32 s6, s0, -8
	s_addc_u32 s7, s1, -1
	s_add_i32 s3, s3, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v6, vcc_lo
	s_clause 0x1
	global_load_b128 v[5:8], v[9:10], off
	global_load_b64 v[9:10], v[9:10], off offset:16
	s_clause 0x1
	s_load_b128 s[20:23], s[6:7], 0x0
	s_load_b64 s[6:7], s[0:1], 0x8
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_cmp_eq_u32 s3, 48
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_mul_f64 v[7:8], v[7:8], s[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], v[5:6], s[20:21], v[7:8]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[5:6], v[9:10], s[6:7], v[5:6]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], v[5:6]
	s_cbranch_scc0 .LBB33_1
; %bb.2:
	s_ashr_i32 s3, s2, 31
	v_mul_u32_u24_e32 v2, 14, v2
	s_lshl_b64 s[0:1], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_add_u32 s4, s10, s0
	s_addc_u32 s5, s11, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[0:1], v[0:1], -s[4:5]
	s_add_u32 s4, s12, s0
	s_addc_u32 s5, s13, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[4:5], null, s[4:5], s[4:5], v[0:1]
	v_div_scale_f64 v[10:11], vcc_lo, v[0:1], s[4:5], v[0:1]
	v_rcp_f64_e32 v[6:7], v[4:5]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_mul_f64 v[8:9], v[10:11], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], -v[4:5], v[8:9], v[10:11]
	v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[0:1], v[4:5], s[4:5], v[0:1]
	s_add_u32 s4, s14, s0
	s_addc_u32 s5, s15, s1
	s_add_u32 s0, s16, s0
	s_addc_u32 s1, s17, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[0:1], v[0:1], s[4:5], s[0:1]
	s_mul_i32 s0, s2, 0xc4
	v_add3_u32 v2, v2, v3, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, 0, v1 :: v_dual_cndmask_b32 v0, 0, v0
	v_cmp_nlt_f64_e32 vcc_lo, 0x40180000, v[0:1]
	v_cndmask_b32_e32 v1, 0x40180000, v1, vcc_lo
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	global_store_b64 v[2:3], v[0:1], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z25executeSixteenthLayer_DSCPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end33:
	.size	_Z25executeSixteenthLayer_DSCPdS_S_S_S_S_S_, .Lfunc_end33-_Z25executeSixteenthLayer_DSCPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 576
; NumSgprs: 26
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z27executeSeventeenthLayer_PSCPdS_S_S_S_S_S_ ; -- Begin function _Z27executeSeventeenthLayer_PSCPdS_S_S_S_S_S_
	.globl	_Z27executeSeventeenthLayer_PSCPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z27executeSeventeenthLayer_PSCPdS_S_S_S_S_S_,@function
_Z27executeSeventeenthLayer_PSCPdS_S_S_S_S_S_: ; @_Z27executeSeventeenthLayer_PSCPdS_S_S_S_S_S_
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_and_b32_e32 v4, 0x3ff, v0
	s_mov_b32 s2, s15
	s_load_b256 s[12:19], s[0:1], 0x20
	v_bfe_u32 v5, v0, 10, 10
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	v_mul_u32_u24_e32 v6, 14, v4
	s_lshl_b32 s0, s2, 9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_ashr_i32 s1, s0, 31
	v_add_lshl_u32 v2, v6, v5, 3
	s_lshl_b64 s[0:1], s[0:1], 3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v2, s3, s4, v2
	v_add_co_ci_u32_e64 v3, null, s5, 0, s3
	s_add_u32 s3, s6, s0
	s_addc_u32 s4, s7, s1
	s_mov_b64 s[0:1], 0
.LBB34_1:                               ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[7:8], v[2:3], off
	s_add_u32 s6, s3, s0
	s_addc_u32 s7, s4, s1
	v_add_co_u32 v2, vcc_lo, 0x620, v2
	s_load_b64 s[6:7], s[6:7], 0x0
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s0, 0x1000
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fma_f64 v[0:1], v[7:8], s[6:7], v[0:1]
	s_cbranch_scc0 .LBB34_1
; %bb.2:
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[2:3], 3
	s_add_u32 s4, s10, s0
	s_addc_u32 s5, s11, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], -s[4:5]
	s_add_u32 s4, s12, s0
	s_addc_u32 s5, s13, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_div_scale_f64 v[2:3], null, s[4:5], s[4:5], v[0:1]
	v_div_scale_f64 v[11:12], vcc_lo, v[0:1], s[4:5], v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[7:8], v[2:3]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[9:10], -v[2:3], v[7:8], 1.0
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], -v[2:3], v[7:8], 1.0
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[9:10], v[11:12], v[7:8]
	v_fma_f64 v[2:3], -v[2:3], v[9:10], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[2:3], v[2:3], v[7:8], v[9:10]
	v_div_fixup_f64 v[0:1], v[2:3], s[4:5], v[0:1]
	s_add_u32 s4, s14, s0
	s_addc_u32 s5, s15, s1
	s_add_u32 s0, s16, s0
	s_addc_u32 s1, s17, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	v_add_nc_u32_e32 v2, v6, v5
	v_lshlrev_b32_e32 v3, 1, v4
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f64 v[0:1], v[0:1], s[4:5], s[0:1]
	s_lshl_b32 s0, s2, 8
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_add3_u32 v2, v2, v3, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, 0, v1 :: v_dual_cndmask_b32 v0, 0, v0
	v_cmp_nlt_f64_e32 vcc_lo, 0x40180000, v[0:1]
	v_cndmask_b32_e32 v1, 0x40180000, v1, vcc_lo
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	global_store_b64 v[2:3], v[0:1], off offset:136
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z27executeSeventeenthLayer_PSCPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end34:
	.size	_Z27executeSeventeenthLayer_PSCPdS_S_S_S_S_S_, .Lfunc_end34-_Z27executeSeventeenthLayer_PSCPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 500
; NumSgprs: 22
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z26executeEighteenthLayer_DSCPdS_S_S_S_S_S_ ; -- Begin function _Z26executeEighteenthLayer_DSCPdS_S_S_S_S_S_
	.globl	_Z26executeEighteenthLayer_DSCPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z26executeEighteenthLayer_DSCPdS_S_S_S_S_S_,@function
_Z26executeEighteenthLayer_DSCPdS_S_S_S_S_S_: ; @_Z26executeEighteenthLayer_DSCPdS_S_S_S_S_S_
; %bb.0:
	s_mov_b32 s2, s15
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b256 s[12:19], s[0:1], 0x20
	v_and_b32_e32 v2, 0x3ff, v0
	s_mul_i32 s0, s2, 9
	v_bfe_u32 v3, v0, 10, 10
	v_mov_b32_e32 v0, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v4, 4, v2
	s_ashr_i32 s1, s0, 31
	s_lshl_b32 s3, s2, 8
	s_lshl_b64 s[0:1], s[0:1], 3
	v_add3_u32 v4, v3, s3, v4
	s_mov_b32 s3, 0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s0, s6
	s_addc_u32 s1, s1, s7
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB35_1:                               ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v5, s3, v4
	s_add_u32 s6, s0, -8
	s_addc_u32 s7, s1, -1
	s_add_i32 s3, s3, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v6, vcc_lo
	s_clause 0x1
	global_load_b128 v[5:8], v[9:10], off
	global_load_b64 v[9:10], v[9:10], off offset:16
	s_clause 0x1
	s_load_b128 s[20:23], s[6:7], 0x0
	s_load_b64 s[6:7], s[0:1], 0x8
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_cmp_eq_u32 s3, 48
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_mul_f64 v[7:8], v[7:8], s[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], v[5:6], s[20:21], v[7:8]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[5:6], v[9:10], s[6:7], v[5:6]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], v[5:6]
	s_cbranch_scc0 .LBB35_1
; %bb.2:
	s_ashr_i32 s3, s2, 31
	v_mul_u32_u24_e32 v2, 14, v2
	s_lshl_b64 s[0:1], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_add_u32 s4, s10, s0
	s_addc_u32 s5, s11, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[0:1], v[0:1], -s[4:5]
	s_add_u32 s4, s12, s0
	s_addc_u32 s5, s13, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[4:5], null, s[4:5], s[4:5], v[0:1]
	v_div_scale_f64 v[10:11], vcc_lo, v[0:1], s[4:5], v[0:1]
	v_rcp_f64_e32 v[6:7], v[4:5]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_mul_f64 v[8:9], v[10:11], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], -v[4:5], v[8:9], v[10:11]
	v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[0:1], v[4:5], s[4:5], v[0:1]
	s_add_u32 s4, s14, s0
	s_addc_u32 s5, s15, s1
	s_add_u32 s0, s16, s0
	s_addc_u32 s1, s17, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[0:1], v[0:1], s[4:5], s[0:1]
	s_mul_i32 s0, s2, 0xc4
	v_add3_u32 v2, v2, v3, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, 0, v1 :: v_dual_cndmask_b32 v0, 0, v0
	v_cmp_nlt_f64_e32 vcc_lo, 0x40180000, v[0:1]
	v_cndmask_b32_e32 v1, 0x40180000, v1, vcc_lo
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	global_store_b64 v[2:3], v[0:1], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z26executeEighteenthLayer_DSCPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end35:
	.size	_Z26executeEighteenthLayer_DSCPdS_S_S_S_S_S_, .Lfunc_end35-_Z26executeEighteenthLayer_DSCPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 576
; NumSgprs: 26
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z26executeNineteenthLayer_PSCPdS_S_S_S_S_S_ ; -- Begin function _Z26executeNineteenthLayer_PSCPdS_S_S_S_S_S_
	.globl	_Z26executeNineteenthLayer_PSCPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z26executeNineteenthLayer_PSCPdS_S_S_S_S_S_,@function
_Z26executeNineteenthLayer_PSCPdS_S_S_S_S_S_: ; @_Z26executeNineteenthLayer_PSCPdS_S_S_S_S_S_
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_and_b32_e32 v4, 0x3ff, v0
	s_mov_b32 s2, s15
	s_load_b256 s[12:19], s[0:1], 0x20
	v_bfe_u32 v5, v0, 10, 10
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	v_mul_u32_u24_e32 v6, 14, v4
	s_lshl_b32 s0, s2, 9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_ashr_i32 s1, s0, 31
	v_add_lshl_u32 v2, v6, v5, 3
	s_lshl_b64 s[0:1], s[0:1], 3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v2, s3, s4, v2
	v_add_co_ci_u32_e64 v3, null, s5, 0, s3
	s_add_u32 s3, s6, s0
	s_addc_u32 s4, s7, s1
	s_mov_b64 s[0:1], 0
.LBB36_1:                               ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[7:8], v[2:3], off
	s_add_u32 s6, s3, s0
	s_addc_u32 s7, s4, s1
	v_add_co_u32 v2, vcc_lo, 0x620, v2
	s_load_b64 s[6:7], s[6:7], 0x0
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s0, 0x1000
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fma_f64 v[0:1], v[7:8], s[6:7], v[0:1]
	s_cbranch_scc0 .LBB36_1
; %bb.2:
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[2:3], 3
	s_add_u32 s4, s10, s0
	s_addc_u32 s5, s11, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], -s[4:5]
	s_add_u32 s4, s12, s0
	s_addc_u32 s5, s13, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_div_scale_f64 v[2:3], null, s[4:5], s[4:5], v[0:1]
	v_div_scale_f64 v[11:12], vcc_lo, v[0:1], s[4:5], v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[7:8], v[2:3]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[9:10], -v[2:3], v[7:8], 1.0
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], -v[2:3], v[7:8], 1.0
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[9:10], v[11:12], v[7:8]
	v_fma_f64 v[2:3], -v[2:3], v[9:10], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[2:3], v[2:3], v[7:8], v[9:10]
	v_div_fixup_f64 v[0:1], v[2:3], s[4:5], v[0:1]
	s_add_u32 s4, s14, s0
	s_addc_u32 s5, s15, s1
	s_add_u32 s0, s16, s0
	s_addc_u32 s1, s17, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	v_add_nc_u32_e32 v2, v6, v5
	v_lshlrev_b32_e32 v3, 1, v4
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f64 v[0:1], v[0:1], s[4:5], s[0:1]
	s_lshl_b32 s0, s2, 8
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_add3_u32 v2, v2, v3, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, 0, v1 :: v_dual_cndmask_b32 v0, 0, v0
	v_cmp_nlt_f64_e32 vcc_lo, 0x40180000, v[0:1]
	v_cndmask_b32_e32 v1, 0x40180000, v1, vcc_lo
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	global_store_b64 v[2:3], v[0:1], off offset:136
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z26executeNineteenthLayer_PSCPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end36:
	.size	_Z26executeNineteenthLayer_PSCPdS_S_S_S_S_S_, .Lfunc_end36-_Z26executeNineteenthLayer_PSCPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 500
; NumSgprs: 22
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z22executeTwentyLayer_DSCPdS_S_S_S_S_S_ ; -- Begin function _Z22executeTwentyLayer_DSCPdS_S_S_S_S_S_
	.globl	_Z22executeTwentyLayer_DSCPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z22executeTwentyLayer_DSCPdS_S_S_S_S_S_,@function
_Z22executeTwentyLayer_DSCPdS_S_S_S_S_S_: ; @_Z22executeTwentyLayer_DSCPdS_S_S_S_S_S_
; %bb.0:
	s_mov_b32 s2, s15
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b256 s[12:19], s[0:1], 0x20
	v_and_b32_e32 v2, 0x3ff, v0
	s_mul_i32 s0, s2, 9
	v_bfe_u32 v3, v0, 10, 10
	v_mov_b32_e32 v0, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v4, 4, v2
	s_ashr_i32 s1, s0, 31
	s_lshl_b32 s3, s2, 8
	s_lshl_b64 s[0:1], s[0:1], 3
	v_add3_u32 v4, v3, s3, v4
	s_mov_b32 s3, 0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s0, s6
	s_addc_u32 s1, s1, s7
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB37_1:                               ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v5, s3, v4
	s_add_u32 s6, s0, -8
	s_addc_u32 s7, s1, -1
	s_add_i32 s3, s3, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v6, vcc_lo
	s_clause 0x1
	global_load_b128 v[5:8], v[9:10], off
	global_load_b64 v[9:10], v[9:10], off offset:16
	s_clause 0x1
	s_load_b128 s[20:23], s[6:7], 0x0
	s_load_b64 s[6:7], s[0:1], 0x8
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_cmp_eq_u32 s3, 48
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_mul_f64 v[7:8], v[7:8], s[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], v[5:6], s[20:21], v[7:8]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[5:6], v[9:10], s[6:7], v[5:6]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], v[5:6]
	s_cbranch_scc0 .LBB37_1
; %bb.2:
	s_ashr_i32 s3, s2, 31
	v_mul_u32_u24_e32 v2, 14, v2
	s_lshl_b64 s[0:1], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_add_u32 s4, s10, s0
	s_addc_u32 s5, s11, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[0:1], v[0:1], -s[4:5]
	s_add_u32 s4, s12, s0
	s_addc_u32 s5, s13, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[4:5], null, s[4:5], s[4:5], v[0:1]
	v_div_scale_f64 v[10:11], vcc_lo, v[0:1], s[4:5], v[0:1]
	v_rcp_f64_e32 v[6:7], v[4:5]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_mul_f64 v[8:9], v[10:11], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], -v[4:5], v[8:9], v[10:11]
	v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[0:1], v[4:5], s[4:5], v[0:1]
	s_add_u32 s4, s14, s0
	s_addc_u32 s5, s15, s1
	s_add_u32 s0, s16, s0
	s_addc_u32 s1, s17, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[0:1], v[0:1], s[4:5], s[0:1]
	s_mul_i32 s0, s2, 0xc4
	v_add3_u32 v2, v2, v3, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, 0, v1 :: v_dual_cndmask_b32 v0, 0, v0
	v_cmp_nlt_f64_e32 vcc_lo, 0x40180000, v[0:1]
	v_cndmask_b32_e32 v1, 0x40180000, v1, vcc_lo
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	global_store_b64 v[2:3], v[0:1], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z22executeTwentyLayer_DSCPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end37:
	.size	_Z22executeTwentyLayer_DSCPdS_S_S_S_S_S_, .Lfunc_end37-_Z22executeTwentyLayer_DSCPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 576
; NumSgprs: 26
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z25executeTwentyOneLayer_PSCPdS_S_S_S_S_S_ ; -- Begin function _Z25executeTwentyOneLayer_PSCPdS_S_S_S_S_S_
	.globl	_Z25executeTwentyOneLayer_PSCPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z25executeTwentyOneLayer_PSCPdS_S_S_S_S_S_,@function
_Z25executeTwentyOneLayer_PSCPdS_S_S_S_S_S_: ; @_Z25executeTwentyOneLayer_PSCPdS_S_S_S_S_S_
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_and_b32_e32 v4, 0x3ff, v0
	s_mov_b32 s2, s15
	s_load_b256 s[12:19], s[0:1], 0x20
	v_bfe_u32 v5, v0, 10, 10
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	v_mul_u32_u24_e32 v6, 14, v4
	s_lshl_b32 s0, s2, 9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_ashr_i32 s1, s0, 31
	v_add_lshl_u32 v2, v6, v5, 3
	s_lshl_b64 s[0:1], s[0:1], 3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v2, s3, s4, v2
	v_add_co_ci_u32_e64 v3, null, s5, 0, s3
	s_add_u32 s3, s6, s0
	s_addc_u32 s4, s7, s1
	s_mov_b64 s[0:1], 0
.LBB38_1:                               ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[7:8], v[2:3], off
	s_add_u32 s6, s3, s0
	s_addc_u32 s7, s4, s1
	v_add_co_u32 v2, vcc_lo, 0x620, v2
	s_load_b64 s[6:7], s[6:7], 0x0
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s0, 0x1000
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fma_f64 v[0:1], v[7:8], s[6:7], v[0:1]
	s_cbranch_scc0 .LBB38_1
; %bb.2:
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[2:3], 3
	s_add_u32 s4, s10, s0
	s_addc_u32 s5, s11, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], -s[4:5]
	s_add_u32 s4, s12, s0
	s_addc_u32 s5, s13, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_div_scale_f64 v[2:3], null, s[4:5], s[4:5], v[0:1]
	v_div_scale_f64 v[11:12], vcc_lo, v[0:1], s[4:5], v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[7:8], v[2:3]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[9:10], -v[2:3], v[7:8], 1.0
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], -v[2:3], v[7:8], 1.0
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[9:10], v[11:12], v[7:8]
	v_fma_f64 v[2:3], -v[2:3], v[9:10], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[2:3], v[2:3], v[7:8], v[9:10]
	v_div_fixup_f64 v[0:1], v[2:3], s[4:5], v[0:1]
	s_add_u32 s4, s14, s0
	s_addc_u32 s5, s15, s1
	s_add_u32 s0, s16, s0
	s_addc_u32 s1, s17, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	v_add_nc_u32_e32 v2, v6, v5
	v_lshlrev_b32_e32 v3, 1, v4
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f64 v[0:1], v[0:1], s[4:5], s[0:1]
	s_lshl_b32 s0, s2, 8
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_add3_u32 v2, v2, v3, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, 0, v1 :: v_dual_cndmask_b32 v0, 0, v0
	v_cmp_nlt_f64_e32 vcc_lo, 0x40180000, v[0:1]
	v_cndmask_b32_e32 v1, 0x40180000, v1, vcc_lo
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	global_store_b64 v[2:3], v[0:1], off offset:136
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z25executeTwentyOneLayer_PSCPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end38:
	.size	_Z25executeTwentyOneLayer_PSCPdS_S_S_S_S_S_, .Lfunc_end38-_Z25executeTwentyOneLayer_PSCPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 500
; NumSgprs: 22
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z25executeTwentyTwoLayer_DSCPdS_S_S_S_S_S_ ; -- Begin function _Z25executeTwentyTwoLayer_DSCPdS_S_S_S_S_S_
	.globl	_Z25executeTwentyTwoLayer_DSCPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z25executeTwentyTwoLayer_DSCPdS_S_S_S_S_S_,@function
_Z25executeTwentyTwoLayer_DSCPdS_S_S_S_S_S_: ; @_Z25executeTwentyTwoLayer_DSCPdS_S_S_S_S_S_
; %bb.0:
	s_mov_b32 s2, s15
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b256 s[12:19], s[0:1], 0x20
	v_and_b32_e32 v2, 0x3ff, v0
	s_mul_i32 s0, s2, 9
	v_bfe_u32 v3, v0, 10, 10
	v_mov_b32_e32 v0, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v4, 4, v2
	s_ashr_i32 s1, s0, 31
	s_lshl_b32 s3, s2, 8
	s_lshl_b64 s[0:1], s[0:1], 3
	v_add3_u32 v4, v3, s3, v4
	s_mov_b32 s3, 0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s0, s6
	s_addc_u32 s1, s1, s7
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB39_1:                               ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v5, s3, v4
	s_add_u32 s6, s0, -8
	s_addc_u32 s7, s1, -1
	s_add_i32 s3, s3, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v6, vcc_lo
	s_clause 0x1
	global_load_b128 v[5:8], v[9:10], off
	global_load_b64 v[9:10], v[9:10], off offset:16
	s_clause 0x1
	s_load_b128 s[20:23], s[6:7], 0x0
	s_load_b64 s[6:7], s[0:1], 0x8
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_cmp_eq_u32 s3, 48
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_mul_f64 v[7:8], v[7:8], s[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], v[5:6], s[20:21], v[7:8]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[5:6], v[9:10], s[6:7], v[5:6]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], v[5:6]
	s_cbranch_scc0 .LBB39_1
; %bb.2:
	s_ashr_i32 s3, s2, 31
	v_mul_u32_u24_e32 v2, 14, v2
	s_lshl_b64 s[0:1], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_add_u32 s4, s10, s0
	s_addc_u32 s5, s11, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[0:1], v[0:1], -s[4:5]
	s_add_u32 s4, s12, s0
	s_addc_u32 s5, s13, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[4:5], null, s[4:5], s[4:5], v[0:1]
	v_div_scale_f64 v[10:11], vcc_lo, v[0:1], s[4:5], v[0:1]
	v_rcp_f64_e32 v[6:7], v[4:5]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_mul_f64 v[8:9], v[10:11], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], -v[4:5], v[8:9], v[10:11]
	v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[0:1], v[4:5], s[4:5], v[0:1]
	s_add_u32 s4, s14, s0
	s_addc_u32 s5, s15, s1
	s_add_u32 s0, s16, s0
	s_addc_u32 s1, s17, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[0:1], v[0:1], s[4:5], s[0:1]
	s_mul_i32 s0, s2, 0xc4
	v_add3_u32 v2, v2, v3, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, 0, v1 :: v_dual_cndmask_b32 v0, 0, v0
	v_cmp_nlt_f64_e32 vcc_lo, 0x40180000, v[0:1]
	v_cndmask_b32_e32 v1, 0x40180000, v1, vcc_lo
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	global_store_b64 v[2:3], v[0:1], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z25executeTwentyTwoLayer_DSCPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end39:
	.size	_Z25executeTwentyTwoLayer_DSCPdS_S_S_S_S_S_, .Lfunc_end39-_Z25executeTwentyTwoLayer_DSCPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 576
; NumSgprs: 26
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z27executeTwentyThreeLayer_PSCPdS_S_S_S_S_S_ ; -- Begin function _Z27executeTwentyThreeLayer_PSCPdS_S_S_S_S_S_
	.globl	_Z27executeTwentyThreeLayer_PSCPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z27executeTwentyThreeLayer_PSCPdS_S_S_S_S_S_,@function
_Z27executeTwentyThreeLayer_PSCPdS_S_S_S_S_S_: ; @_Z27executeTwentyThreeLayer_PSCPdS_S_S_S_S_S_
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_and_b32_e32 v4, 0x3ff, v0
	s_mov_b32 s2, s15
	s_load_b256 s[12:19], s[0:1], 0x20
	v_bfe_u32 v5, v0, 10, 10
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	v_mul_u32_u24_e32 v6, 14, v4
	s_lshl_b32 s0, s2, 9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_ashr_i32 s1, s0, 31
	v_add_lshl_u32 v2, v6, v5, 3
	s_lshl_b64 s[0:1], s[0:1], 3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v2, s3, s4, v2
	v_add_co_ci_u32_e64 v3, null, s5, 0, s3
	s_add_u32 s3, s6, s0
	s_addc_u32 s4, s7, s1
	s_mov_b64 s[0:1], 0
.LBB40_1:                               ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[7:8], v[2:3], off
	s_add_u32 s6, s3, s0
	s_addc_u32 s7, s4, s1
	v_add_co_u32 v2, vcc_lo, 0x620, v2
	s_load_b64 s[6:7], s[6:7], 0x0
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s0, 0x1000
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fma_f64 v[0:1], v[7:8], s[6:7], v[0:1]
	s_cbranch_scc0 .LBB40_1
; %bb.2:
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[2:3], 3
	s_add_u32 s4, s10, s0
	s_addc_u32 s5, s11, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], -s[4:5]
	s_add_u32 s4, s12, s0
	s_addc_u32 s5, s13, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_div_scale_f64 v[2:3], null, s[4:5], s[4:5], v[0:1]
	v_div_scale_f64 v[11:12], vcc_lo, v[0:1], s[4:5], v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[7:8], v[2:3]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[9:10], -v[2:3], v[7:8], 1.0
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], -v[2:3], v[7:8], 1.0
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[9:10], v[11:12], v[7:8]
	v_fma_f64 v[2:3], -v[2:3], v[9:10], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[2:3], v[2:3], v[7:8], v[9:10]
	v_div_fixup_f64 v[0:1], v[2:3], s[4:5], v[0:1]
	s_add_u32 s4, s14, s0
	s_addc_u32 s5, s15, s1
	s_add_u32 s0, s16, s0
	s_addc_u32 s1, s17, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	v_add_nc_u32_e32 v2, v6, v5
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[0:1], v[0:1], s[4:5], s[0:1]
	s_mul_i32 s0, s2, 0xe1
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_add3_u32 v2, v2, v4, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, 0, v1 :: v_dual_cndmask_b32 v0, 0, v0
	v_cmp_nlt_f64_e32 vcc_lo, 0x40180000, v[0:1]
	v_cndmask_b32_e32 v1, 0x40180000, v1, vcc_lo
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	global_store_b64 v[2:3], v[0:1], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z27executeTwentyThreeLayer_PSCPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end40:
	.size	_Z27executeTwentyThreeLayer_PSCPdS_S_S_S_S_S_, .Lfunc_end40-_Z27executeTwentyThreeLayer_PSCPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 500
; NumSgprs: 22
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z26executeTwentyFourLayer_DSCPdS_S_S_S_S_S_ ; -- Begin function _Z26executeTwentyFourLayer_DSCPdS_S_S_S_S_S_
	.globl	_Z26executeTwentyFourLayer_DSCPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z26executeTwentyFourLayer_DSCPdS_S_S_S_S_S_,@function
_Z26executeTwentyFourLayer_DSCPdS_S_S_S_S_S_: ; @_Z26executeTwentyFourLayer_DSCPdS_S_S_S_S_S_
; %bb.0:
	s_mov_b32 s2, s15
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b256 s[12:19], s[0:1], 0x20
	v_and_b32_e32 v3, 0x3ff, v0
	v_bfe_u32 v2, v0, 10, 10
	v_mov_b32_e32 v0, 0
	s_mul_i32 s0, s2, 9
	s_mul_i32 s3, s2, 0xe1
	v_mul_u32_u24_e32 v4, 30, v3
	v_lshlrev_b32_e32 v5, 1, v2
	s_ashr_i32 s1, s0, 31
	v_mov_b32_e32 v1, 0
	s_lshl_b64 s[0:1], s[0:1], 3
	s_delay_alu instid0(VALU_DEP_2)
	v_add3_u32 v4, v4, v5, s3
	s_mov_b32 s3, 0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s0, s6
	s_addc_u32 s1, s1, s7
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB41_1:                               ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v5, s3, v4
	s_add_u32 s6, s0, -8
	s_addc_u32 s7, s1, -1
	s_add_i32 s3, s3, 15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v6, vcc_lo
	s_clause 0x1
	global_load_b128 v[5:8], v[9:10], off
	global_load_b64 v[9:10], v[9:10], off offset:16
	s_clause 0x1
	s_load_b128 s[20:23], s[6:7], 0x0
	s_load_b64 s[6:7], s[0:1], 0x8
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_cmp_eq_u32 s3, 45
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_mul_f64 v[7:8], v[7:8], s[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], v[5:6], s[20:21], v[7:8]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[5:6], v[9:10], s[6:7], v[5:6]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], v[5:6]
	s_cbranch_scc0 .LBB41_1
; %bb.2:
	s_ashr_i32 s3, s2, 31
	v_mul_u32_u24_e32 v3, 7, v3
	s_lshl_b64 s[0:1], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_add_u32 s4, s10, s0
	s_addc_u32 s5, s11, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[0:1], v[0:1], -s[4:5]
	s_add_u32 s4, s12, s0
	s_addc_u32 s5, s13, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[4:5], null, s[4:5], s[4:5], v[0:1]
	v_div_scale_f64 v[10:11], vcc_lo, v[0:1], s[4:5], v[0:1]
	v_rcp_f64_e32 v[6:7], v[4:5]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_mul_f64 v[8:9], v[10:11], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], -v[4:5], v[8:9], v[10:11]
	v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[0:1], v[4:5], s[4:5], v[0:1]
	s_add_u32 s4, s14, s0
	s_addc_u32 s5, s15, s1
	s_add_u32 s0, s16, s0
	s_addc_u32 s1, s17, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[0:1], v[0:1], s[4:5], s[0:1]
	s_mul_i32 s0, s2, 49
	v_add3_u32 v2, v3, v2, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, 0, v1 :: v_dual_cndmask_b32 v0, 0, v0
	v_cmp_nlt_f64_e32 vcc_lo, 0x40180000, v[0:1]
	v_cndmask_b32_e32 v1, 0x40180000, v1, vcc_lo
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	global_store_b64 v[2:3], v[0:1], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z26executeTwentyFourLayer_DSCPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end41:
	.size	_Z26executeTwentyFourLayer_DSCPdS_S_S_S_S_S_, .Lfunc_end41-_Z26executeTwentyFourLayer_DSCPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 580
; NumSgprs: 26
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z26executeTwentyFiveLayer_PSCPdS_S_S_S_S_S_ ; -- Begin function _Z26executeTwentyFiveLayer_PSCPdS_S_S_S_S_S_
	.globl	_Z26executeTwentyFiveLayer_PSCPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z26executeTwentyFiveLayer_PSCPdS_S_S_S_S_S_,@function
_Z26executeTwentyFiveLayer_PSCPdS_S_S_S_S_S_: ; @_Z26executeTwentyFiveLayer_PSCPdS_S_S_S_S_S_
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_and_b32_e32 v4, 0x3ff, v0
	s_mov_b32 s2, s15
	s_load_b256 s[12:19], s[0:1], 0x20
	v_bfe_u32 v5, v0, 10, 10
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	v_mul_u32_u24_e32 v6, 7, v4
	s_lshl_b32 s0, s2, 9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_ashr_i32 s1, s0, 31
	v_add_lshl_u32 v2, v6, v5, 3
	s_lshl_b64 s[0:1], s[0:1], 3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v2, s3, s4, v2
	v_add_co_ci_u32_e64 v3, null, s5, 0, s3
	s_add_u32 s3, s6, s0
	s_addc_u32 s4, s7, s1
	s_mov_b64 s[0:1], 0
.LBB42_1:                               ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[7:8], v[2:3], off
	s_add_u32 s6, s3, s0
	s_addc_u32 s7, s4, s1
	v_add_co_u32 v2, vcc_lo, 0x188, v2
	s_load_b64 s[6:7], s[6:7], 0x0
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s0, 0x1000
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fma_f64 v[0:1], v[7:8], s[6:7], v[0:1]
	s_cbranch_scc0 .LBB42_1
; %bb.2:
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[2:3], 3
	s_add_u32 s4, s10, s0
	s_addc_u32 s5, s11, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], -s[4:5]
	s_add_u32 s4, s12, s0
	s_addc_u32 s5, s13, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_div_scale_f64 v[2:3], null, s[4:5], s[4:5], v[0:1]
	v_div_scale_f64 v[11:12], vcc_lo, v[0:1], s[4:5], v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[7:8], v[2:3]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[9:10], -v[2:3], v[7:8], 1.0
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], -v[2:3], v[7:8], 1.0
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[9:10], v[11:12], v[7:8]
	v_fma_f64 v[2:3], -v[2:3], v[9:10], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[2:3], v[2:3], v[7:8], v[9:10]
	v_div_fixup_f64 v[0:1], v[2:3], s[4:5], v[0:1]
	s_add_u32 s4, s14, s0
	s_addc_u32 s5, s15, s1
	s_add_u32 s0, s16, s0
	s_addc_u32 s1, s17, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	v_add_nc_u32_e32 v2, v6, v5
	v_lshlrev_b32_e32 v3, 1, v4
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f64 v[0:1], v[0:1], s[4:5], s[0:1]
	s_mul_i32 s0, s2, 0x51
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_add3_u32 v2, v2, v3, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, 0, v1 :: v_dual_cndmask_b32 v0, 0, v0
	v_cmp_nlt_f64_e32 vcc_lo, 0x40180000, v[0:1]
	v_cndmask_b32_e32 v1, 0x40180000, v1, vcc_lo
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	global_store_b64 v[2:3], v[0:1], off offset:80
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z26executeTwentyFiveLayer_PSCPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end42:
	.size	_Z26executeTwentyFiveLayer_PSCPdS_S_S_S_S_S_, .Lfunc_end42-_Z26executeTwentyFiveLayer_PSCPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 504
; NumSgprs: 22
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z25executeTwentySixLayer_DSCPdS_S_S_S_S_S_ ; -- Begin function _Z25executeTwentySixLayer_DSCPdS_S_S_S_S_S_
	.globl	_Z25executeTwentySixLayer_DSCPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z25executeTwentySixLayer_DSCPdS_S_S_S_S_S_,@function
_Z25executeTwentySixLayer_DSCPdS_S_S_S_S_S_: ; @_Z25executeTwentySixLayer_DSCPdS_S_S_S_S_S_
; %bb.0:
	s_mov_b32 s2, s15
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b256 s[12:19], s[0:1], 0x20
	v_and_b32_e32 v2, 0x3ff, v0
	s_mul_i32 s0, s2, 9
	v_bfe_u32 v3, v0, 10, 10
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	v_mul_u32_u24_e32 v4, 9, v2
	s_ashr_i32 s1, s0, 31
	s_mul_i32 s3, s2, 0x51
	s_lshl_b64 s[0:1], s[0:1], 3
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v4, v3, s3, v4
	s_mov_b32 s3, 0
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s0, s6
	s_addc_u32 s1, s1, s7
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB43_1:                               ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v5, s3, v4
	s_add_u32 s6, s0, -8
	s_addc_u32 s7, s1, -1
	s_add_i32 s3, s3, 9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[5:6], 3, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v6, vcc_lo
	s_clause 0x1
	global_load_b128 v[5:8], v[9:10], off
	global_load_b64 v[9:10], v[9:10], off offset:16
	s_clause 0x1
	s_load_b128 s[20:23], s[6:7], 0x0
	s_load_b64 s[6:7], s[0:1], 0x8
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_cmp_eq_u32 s3, 27
	s_waitcnt vmcnt(1) lgkmcnt(0)
	v_mul_f64 v[7:8], v[7:8], s[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], v[5:6], s[20:21], v[7:8]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[5:6], v[9:10], s[6:7], v[5:6]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], v[5:6]
	s_cbranch_scc0 .LBB43_1
; %bb.2:
	s_ashr_i32 s3, s2, 31
	v_mul_u32_u24_e32 v2, 7, v2
	s_lshl_b64 s[0:1], s[2:3], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_add_u32 s4, s10, s0
	s_addc_u32 s5, s11, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[0:1], v[0:1], -s[4:5]
	s_add_u32 s4, s12, s0
	s_addc_u32 s5, s13, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[4:5], null, s[4:5], s[4:5], v[0:1]
	v_div_scale_f64 v[10:11], vcc_lo, v[0:1], s[4:5], v[0:1]
	v_rcp_f64_e32 v[6:7], v[4:5]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_mul_f64 v[8:9], v[10:11], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], -v[4:5], v[8:9], v[10:11]
	v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[0:1], v[4:5], s[4:5], v[0:1]
	s_add_u32 s4, s14, s0
	s_addc_u32 s5, s15, s1
	s_add_u32 s0, s16, s0
	s_addc_u32 s1, s17, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[0:1], v[0:1], s[4:5], s[0:1]
	s_mul_i32 s0, s2, 49
	v_add3_u32 v2, v2, v3, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, 0, v1 :: v_dual_cndmask_b32 v0, 0, v0
	v_cmp_nlt_f64_e32 vcc_lo, 0x40180000, v[0:1]
	v_cndmask_b32_e32 v1, 0x40180000, v1, vcc_lo
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	global_store_b64 v[2:3], v[0:1], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z25executeTwentySixLayer_DSCPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end43:
	.size	_Z25executeTwentySixLayer_DSCPdS_S_S_S_S_S_, .Lfunc_end43-_Z25executeTwentySixLayer_DSCPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 576
; NumSgprs: 26
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z27executeTwentySevenLayer_PSCPdS_S_S_S_S_S_ ; -- Begin function _Z27executeTwentySevenLayer_PSCPdS_S_S_S_S_S_
	.globl	_Z27executeTwentySevenLayer_PSCPdS_S_S_S_S_S_
	.p2align	8
	.type	_Z27executeTwentySevenLayer_PSCPdS_S_S_S_S_S_,@function
_Z27executeTwentySevenLayer_PSCPdS_S_S_S_S_S_: ; @_Z27executeTwentySevenLayer_PSCPdS_S_S_S_S_S_
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_and_b32_e32 v1, 0x3ff, v0
	s_mov_b32 s2, s15
	s_load_b256 s[12:19], s[0:1], 0x20
	v_bfe_u32 v4, v0, 10, 10
	s_lshl_b32 s0, s2, 10
	v_mul_u32_u24_e32 v5, 7, v1
	s_ashr_i32 s1, s0, 31
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	s_lshl_b64 s[0:1], s[0:1], 3
	v_add_lshl_u32 v2, v5, v4, 3
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v2, s3, s4, v2
	v_add_co_ci_u32_e64 v3, null, s5, 0, s3
	s_add_u32 s3, s6, s0
	s_addc_u32 s4, s7, s1
	s_mov_b64 s[0:1], 0
.LBB44_1:                               ; =>This Inner Loop Header: Depth=1
	global_load_b64 v[6:7], v[2:3], off
	s_add_u32 s6, s3, s0
	s_addc_u32 s7, s4, s1
	v_add_co_u32 v2, vcc_lo, 0x188, v2
	s_load_b64 s[6:7], s[6:7], 0x0
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_cmpk_eq_i32 s0, 0x2000
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fma_f64 v[0:1], v[6:7], s[6:7], v[0:1]
	s_cbranch_scc0 .LBB44_1
; %bb.2:
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[2:3], 3
	s_add_u32 s4, s10, s0
	s_addc_u32 s5, s11, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], -s[4:5]
	s_add_u32 s4, s12, s0
	s_addc_u32 s5, s13, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_waitcnt lgkmcnt(0)
	v_div_scale_f64 v[2:3], null, s[4:5], s[4:5], v[0:1]
	v_div_scale_f64 v[10:11], vcc_lo, v[0:1], s[4:5], v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[6:7], v[2:3]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[2:3], v[6:7], 1.0
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], -v[2:3], v[6:7], 1.0
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[8:9], v[10:11], v[6:7]
	v_fma_f64 v[2:3], -v[2:3], v[8:9], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[2:3], v[2:3], v[6:7], v[8:9]
	v_div_fixup_f64 v[0:1], v[2:3], s[4:5], v[0:1]
	s_add_u32 s4, s14, s0
	s_addc_u32 s5, s15, s1
	s_add_u32 s0, s16, s0
	s_addc_u32 s1, s17, s1
	s_load_b64 s[4:5], s[4:5], 0x0
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[0:1], v[0:1], s[4:5], s[0:1]
	s_mul_i32 s0, s2, 49
	v_add3_u32 v2, v5, v4, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_ngt_f64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, 0, v1 :: v_dual_cndmask_b32 v0, 0, v0
	v_cmp_nlt_f64_e32 vcc_lo, 0x40180000, v[0:1]
	v_cndmask_b32_e32 v1, 0x40180000, v1, vcc_lo
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	global_store_b64 v[2:3], v[0:1], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z27executeTwentySevenLayer_PSCPdS_S_S_S_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 56
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end44:
	.size	_Z27executeTwentySevenLayer_PSCPdS_S_S_S_S_S_, .Lfunc_end44-_Z27executeTwentySevenLayer_PSCPdS_S_S_S_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 484
; NumSgprs: 22
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z34executeTwentyEightLayer_AvgPoolingPdS_ ; -- Begin function _Z34executeTwentyEightLayer_AvgPoolingPdS_
	.globl	_Z34executeTwentyEightLayer_AvgPoolingPdS_
	.p2align	8
	.type	_Z34executeTwentyEightLayer_AvgPoolingPdS_,@function
_Z34executeTwentyEightLayer_AvgPoolingPdS_: ; @_Z34executeTwentyEightLayer_AvgPoolingPdS_
; %bb.0:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_mov_b32 s4, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v2, v1, 5, v0
	v_mul_u32_u24_e32 v0, 49, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v0, 0 :: v_dual_lshlrev_b32 v3, 3, v0
	v_mov_b32_e32 v1, 0
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v3, s0, s0, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v4, null, s1, 0, s0
.LBB45_1:                               ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB45_2 Depth 2
	s_mov_b64 s[0:1], 0
.LBB45_2:                               ;   Parent Loop BB45_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_add_co_u32 v5, vcc_lo, v3, s0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s1, v4, vcc_lo
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	s_cmp_eq_u32 s0, 56
	global_load_b64 v[5:6], v[5:6], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[0:1], v[0:1], v[5:6]
	s_cbranch_scc0 .LBB45_2
; %bb.3:                                ;   in Loop: Header=BB45_1 Depth=1
	v_add_co_u32 v3, vcc_lo, v3, 56
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
	s_add_i32 s4, s4, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s4, 7
	s_cbranch_scc0 .LBB45_1
; %bb.4:
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[3:4], null, 0x40488000, 0x40488000, v[0:1]
	v_lshlrev_b32_e32 v2, 3, v2
	v_rcp_f64_e32 v[5:6], v[3:4]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[7:8], -v[3:4], v[5:6], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], v[5:6], v[7:8], v[5:6]
	v_fma_f64 v[7:8], -v[3:4], v[5:6], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], v[5:6], v[7:8], v[5:6]
	v_div_scale_f64 v[7:8], vcc_lo, v[0:1], 0x40488000, v[0:1]
	v_mul_f64 v[9:10], v[7:8], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[3:4], -v[3:4], v[9:10], v[7:8]
	v_div_fmas_f64 v[3:4], v[3:4], v[5:6], v[9:10]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[0:1], v[3:4], 0x40488000, v[0:1]
	global_store_b64 v2, v[0:1], s[2:3]
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z34executeTwentyEightLayer_AvgPoolingPdS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 16
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 5
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end45:
	.size	_Z34executeTwentyEightLayer_AvgPoolingPdS_, .Lfunc_end45-_Z34executeTwentyEightLayer_AvgPoolingPdS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 316
; NumSgprs: 7
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 7
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z37executeTwentyNineLayer_FullyConnectedPdS_S_S_ ; -- Begin function _Z37executeTwentyNineLayer_FullyConnectedPdS_S_S_
	.globl	_Z37executeTwentyNineLayer_FullyConnectedPdS_S_S_
	.p2align	8
	.type	_Z37executeTwentyNineLayer_FullyConnectedPdS_S_S_,@function
_Z37executeTwentyNineLayer_FullyConnectedPdS_S_S_: ; @_Z37executeTwentyNineLayer_FullyConnectedPdS_S_S_
; %bb.0:
	s_load_b256 s[0:7], s[0:1], 0x0
	v_lshlrev_b32_e32 v3, 13, v0
	v_mov_b32_e32 v1, 0
	v_mov_b32_e32 v2, 0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v3, s4, s4, v3
	v_add_co_ci_u32_e64 v4, null, s5, 0, s4
	s_mov_b64 s[4:5], 0
.LBB46_1:                               ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_add_co_u32 v5, vcc_lo, v3, s4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v4, vcc_lo
	s_add_u32 s8, s0, s4
	s_addc_u32 s9, s1, s5
	s_add_u32 s4, s4, 8
	global_load_b64 v[5:6], v[5:6], off
	s_load_b64 s[8:9], s[8:9], 0x0
	s_addc_u32 s5, s5, 0
	s_cmpk_eq_i32 s4, 0x2000
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fma_f64 v[1:2], s[8:9], v[5:6], v[1:2]
	s_cbranch_scc0 .LBB46_1
; %bb.2:
	v_lshlrev_b32_e32 v5, 3, v0
	global_load_b64 v[3:4], v5, s[6:7]
	s_waitcnt vmcnt(0)
	v_add_f64 v[0:1], v[1:2], v[3:4]
	global_store_b64 v5, v[0:1], s[2:3]
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z37executeTwentyNineLayer_FullyConnectedPdS_S_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 32
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 10
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end46:
	.size	_Z37executeTwentyNineLayer_FullyConnectedPdS_S_S_, .Lfunc_end46-_Z37executeTwentyNineLayer_FullyConnectedPdS_S_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 164
; NumSgprs: 12
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 12
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 56
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z30executeFirstLayer_CONV3D_partAPdS_S_S_S_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     30
    .sgpr_spill_count: 0
    .symbol:         _Z30executeFirstLayer_CONV3D_partAPdS_S_S_S_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     13
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
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        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 56
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z30executeFirstLayer_CONV3D_partBPdS_S_S_S_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     30
    .sgpr_spill_count: 0
    .symbol:         _Z30executeFirstLayer_CONV3D_partBPdS_S_S_S_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     13
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
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        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 56
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z30executeFirstLayer_CONV3D_partCPdS_S_S_S_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     30
    .sgpr_spill_count: 0
    .symbol:         _Z30executeFirstLayer_CONV3D_partCPdS_S_S_S_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     13
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
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        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
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        .size:           8
        .value_kind:     global_buffer
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        .size:           8
        .value_kind:     global_buffer
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        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 56
    .language:       OpenCL C
    .language_version:
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      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z28executeSecondLayer_DSC_partAPdS_S_S_S_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     30
    .sgpr_spill_count: 0
    .symbol:         _Z28executeSecondLayer_DSC_partAPdS_S_S_S_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
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        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
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        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
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        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
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        .size:           8
        .value_kind:     global_buffer
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        .size:           8
        .value_kind:     global_buffer
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        .size:           8
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        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 56
    .language:       OpenCL C
    .language_version:
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      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z28executeSecondLayer_DSC_partBPdS_S_S_S_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     30
    .sgpr_spill_count: 0
    .symbol:         _Z28executeSecondLayer_DSC_partBPdS_S_S_S_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
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        .offset:         0
        .size:           8
        .value_kind:     global_buffer
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        .size:           8
        .value_kind:     global_buffer
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        .value_kind:     global_buffer
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    .group_segment_fixed_size: 0
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    .kernarg_segment_size: 56
    .language:       OpenCL C
    .language_version:
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      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z28executeSecondLayer_DSC_partCPdS_S_S_S_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     30
    .sgpr_spill_count: 0
    .symbol:         _Z28executeSecondLayer_DSC_partCPdS_S_S_S_S_S_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
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    .language:       OpenCL C
    .language_version:
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      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z27executeThirdLayer_PSC_partAPdS_S_S_S_S_S_
    .private_segment_fixed_size: 0
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    .sgpr_spill_count: 0
    .symbol:         _Z27executeThirdLayer_PSC_partAPdS_S_S_S_S_S_.kd
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    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
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    .name:           _Z27executeThirdLayer_PSC_partCPdS_S_S_S_S_S_
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    .sgpr_spill_count: 0
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  - .args:
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    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 56
    .language:       OpenCL C
    .language_version:
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    .max_flat_workgroup_size: 1024
    .name:           _Z25executeTwentySixLayer_DSCPdS_S_S_S_S_S_
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         _Z25executeTwentySixLayer_DSCPdS_S_S_S_S_S_.kd
    .uniform_work_group_size: 1
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    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
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    .language:       OpenCL C
    .language_version:
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      - 0
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    .name:           _Z27executeTwentySevenLayer_PSCPdS_S_S_S_S_S_
    .private_segment_fixed_size: 0
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    .sgpr_spill_count: 0
    .symbol:         _Z27executeTwentySevenLayer_PSCPdS_S_S_S_S_S_.kd
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    .vgpr_spill_count: 0
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        .size:           8
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    .language:       OpenCL C
    .language_version:
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    .name:           _Z34executeTwentyEightLayer_AvgPoolingPdS_
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    .sgpr_spill_count: 0
    .symbol:         _Z34executeTwentyEightLayer_AvgPoolingPdS_.kd
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    .wavefront_size: 32
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amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
