// Assumption is input size == output size


#include <stdio.h>
#include <stdlib.h>


#define mask_width  2
#define block_size  o_tile_width + mask_width - 1
#define o_tile_width 2


__global__
void gpu_conv2d(float *d_out, float *d_in, float *d_filter, int height, int width){
    __shared__ float sh_din[block_size][block_size];
    int tx = threadIdx.x;
    int ty = threadIdx.y;
    int row_o = blockIdx.y*o_tile_width + ty;
    int col_o = blockIdx.x * o_tile_width + tx;
    int diff = mask_width - 1;
    int row_i = row_o - diff;
    int col_i = col_o - diff;

    if ((row_i >= 0  && row_i < height) &&
    	(col_i >=0 && col_i < width )){
    	sh_din[ty][tx] = d_in[row_i*width + col_i];
    }
    else{
    	sh_din[ty][tx] = 0.0;
    }
    __syncthreads();

    float output = 0.0;

    if (tx < o_tile_width && ty < o_tile_width){
    	for (int i=0; i < mask_width; i++){
    		for (int j =0; j < mask_width; j++){
    			output += d_filter[i*mask_width + j] * sh_din[ty+i][tx+j]; 
    		}
    	}
    }
	if (tx < o_tile_width && ty < o_tile_width){
		d_out[row_o*width + col_o] = output;
	}

}


void init(float *arr, int h, int w, float val){
	for (int r=0; r < h; r++){
		for (int c=0; c < w; c++){
			arr[r*w + c] = val;
		}
	}
}



void host_conv2d(float *h_out, float *h_in, float *h_filter, int height, int width){

	for (int r=0; r<height; r++){
		for (int c =0; c < width; c++){
			float output = 0.0;
			int r_i = r - mask_width + 1;
			int c_i = c - mask_width + 1;
			//printf("r_i: %d , c_i: %d\n", r_i, c_i);
			for (int mr=0; mr<mask_width; mr++){
		        for (int mc=0; mc< mask_width; mc++){
	                if ( ((r_i+mr) >= 0 && (r_i + mr) < height) && ((c_i+mc) >=0 && (c_i+mc) < width) )
	                    output+= h_in[(mr + r_i)*width + (c_i+mc)] * h_filter[mr*mask_width + mc];
		        }
			}
			h_out[r*width + c] = output;
		}
	}

}



int main(){
	float *d_in, *d_filter, *d_out;
	float *h_in, *h_filter, *h_out; // Only for checking. Not needed for functionality

	int height = 6;
	int width = 6;

	size_t size_in = height*width*sizeof(float);
	size_t size_filter = mask_width*mask_width*sizeof(float);
	size_t size_out = height*width*sizeof(float);

	h_in = (float*) malloc (size_in);
	h_filter = (float*) malloc (size_filter);
	h_out = (float*) malloc (size_out);

	cudaMallocManaged(&d_in, size_in);
	cudaMallocManaged(&d_filter, size_filter);
	cudaMallocManaged(&d_out, size_out);

	init(d_in, height, width, 1.0);
	init(d_filter, mask_width, mask_width, 1.0);
	init(d_out, height, width, 0.0);

	dim3 num_threads (block_size, block_size);
	dim3 num_blocks ((height-1)/(o_tile_width) + 1, (width-1)/(o_tile_width) + 1) ;

	gpu_conv2d<<<num_blocks, num_threads>>>(d_out, d_in, d_filter, height, width);
	cudaDeviceSynchronize();


	init(h_in, height, width, 1.0);
	init(h_filter, mask_width, mask_width, 1.0);
	init(h_out, height, width, 0.0);

	host_conv2d(h_out, h_in, h_filter, height, width);
    
    for(int i=0; i<height; i++){
        for (int j=0; j<width; j++){
                if (d_out[i*width +j] != h_out[i*width +j]){
                        printf(" h_out[%d][%d]: %f", i, j, h_out[i*width + j]);
                        printf(" d_out[%d][%d]: %f", i, j, d_out[i*width + j]);
                        return 0;
                }
        }
    }

	/*
    for (int i =0; i<dout_size; i++)
            if (d_out[i] != h_out[i]){
                    printf("Program failed!! Check the idx: %d", i);
                    return 0;
            }
    */
    printf("Success!!\n");
}

	.file	"tmpxft_002203ee_00000000-6_conv2d.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2032:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z4initPfiif
	.type	_Z4initPfiif, @function
_Z4initPfiif:
.LFB2027:
	.cfi_startproc
	endbr64
	xorl	%ecx, %ecx
	xorl	%r8d, %r8d
.L3:
	cmpl	%esi, %r8d
	jge	.L2
	movslq	%ecx, %rax
	leaq	(%rdi,%rax,4), %r9
	xorl	%eax, %eax
.L6:
	cmpl	%eax, %edx
	jle	.L8
	movss	%xmm0, (%r9,%rax,4)
	incq	%rax
	jmp	.L6
.L8:
	incl	%r8d
	addl	%edx, %ecx
	jmp	.L3
.L2:
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z4initPfiif, .-_Z4initPfiif
	.globl	_Z11host_conv2dPfS_S_ii
	.type	_Z11host_conv2dPfS_S_ii, @function
_Z11host_conv2dPfS_S_ii:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rdx, %r11
	orl	$-1, %r10d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rdi, -8(%rsp)
	movl	%ecx, -16(%rsp)
	xorl	%ecx, %ecx
.L10:
	leal	1(%r10), %r14d
	cmpl	%r14d, -16(%rsp)
	jle	.L9
	movq	-8(%rsp), %rdi
	movslq	%ecx, %rax
	leaq	(%rdi,%rax,4), %rax
	movq	%rax, -24(%rsp)
	xorl	%eax, %eax
.L17:
	cmpl	%eax, %r8d
	jle	.L32
	leal	-1(%rax), %ebx
	movl	%ecx, %ebp
	movl	%eax, %r15d
	movl	%r10d, %r9d
	movl	%ebx, -12(%rsp)
	subl	%r8d, %ebp
	xorl	%edi, %edi
	xorps	%xmm0, %xmm0
.L11:
	movl	-12(%rsp), %edx
	movl	%edi, %ebx
.L13:
	cmpl	%r9d, -16(%rsp)
	jle	.L12
	cmpl	$-1, %r9d
	je	.L12
	cmpl	%edx, %r8d
	jle	.L12
	cmpl	$-1, %edx
	je	.L12
	leal	(%rdx,%rbp), %r13d
	movslq	%ebx, %r12
	movslq	%r13d, %r13
	movss	(%rsi,%r13,4), %xmm1
	mulss	(%r11,%r12,4), %xmm1
	addss	%xmm1, %xmm0
.L12:
	leal	1(%rdx), %r12d
	incl	%ebx
	cmpl	%r15d, %edx
	je	.L33
	movl	%r12d, %edx
	jmp	.L13
.L33:
	addl	$2, %edi
	addl	%r8d, %ebp
	incl	%r9d
	cmpl	$4, %edi
	jne	.L11
	movq	-24(%rsp), %rbx
	movss	%xmm0, (%rbx,%rax,4)
	incq	%rax
	jmp	.L17
.L32:
	addl	%r8d, %ecx
	movl	%r14d, %r10d
	jmp	.L10
.L9:
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z11host_conv2dPfS_S_ii, .-_Z11host_conv2dPfS_S_ii
	.globl	_Z36__device_stub__Z10gpu_conv2dPfS_S_iiPfS_S_ii
	.type	_Z36__device_stub__Z10gpu_conv2dPfS_S_iiPfS_S_ii, @function
_Z36__device_stub__Z10gpu_conv2dPfS_S_iiPfS_S_ii:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L34
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z10gpu_conv2dPfS_S_ii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L34:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L36
	call	__stack_chk_fail@PLT
.L36:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z36__device_stub__Z10gpu_conv2dPfS_S_iiPfS_S_ii, .-_Z36__device_stub__Z10gpu_conv2dPfS_S_iiPfS_S_ii
	.globl	_Z10gpu_conv2dPfS_S_ii
	.type	_Z10gpu_conv2dPfS_S_ii, @function
_Z10gpu_conv2dPfS_S_ii:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z10gpu_conv2dPfS_S_iiPfS_S_ii
	.cfi_endproc
.LFE2055:
	.size	_Z10gpu_conv2dPfS_S_ii, .-_Z10gpu_conv2dPfS_S_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	" h_out[%d][%d]: %f"
.LC3:
	.string	" d_out[%d][%d]: %f"
.LC4:
	.string	"Success!!\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$144, %edi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$64, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$16, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	movl	$144, %edi
	movq	%rax, %r12
	call	malloc@PLT
	leaq	8(%rsp), %rdi
	movl	$1, %edx
	movl	$144, %esi
	movq	%rax, %rbx
	call	cudaMallocManaged@PLT
	leaq	16(%rsp), %rdi
	movl	$1, %edx
	movl	$16, %esi
	call	cudaMallocManaged@PLT
	leaq	24(%rsp), %rdi
	movl	$1, %edx
	movl	$144, %esi
	call	cudaMallocManaged@PLT
	movq	8(%rsp), %rdi
	movl	$6, %edx
	movss	.LC1(%rip), %xmm0
	movl	$6, %esi
	call	_Z4initPfiif
	movq	16(%rsp), %rdi
	movl	$2, %edx
	movss	.LC1(%rip), %xmm0
	movl	$2, %esi
	call	_Z4initPfiif
	movq	24(%rsp), %rdi
	movl	$6, %edx
	xorps	%xmm0, %xmm0
	movl	$6, %esi
	call	_Z4initPfiif
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$12884901891, %rdi
	movl	$1, %esi
	movl	$1, 40(%rsp)
	movq	%rdi, %rdx
	movq	%rdi, 32(%rsp)
	movq	%rdi, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L40
	movq	16(%rsp), %rdx
	movq	8(%rsp), %rsi
	movl	$6, %ecx
	movl	$6, %r8d
	movq	24(%rsp), %rdi
	call	_Z36__device_stub__Z10gpu_conv2dPfS_S_iiPfS_S_ii
.L40:
	call	cudaDeviceSynchronize@PLT
	movss	.LC1(%rip), %xmm0
	movl	$6, %edx
	movq	%rbp, %rdi
	movl	$6, %esi
	call	_Z4initPfiif
	movss	.LC1(%rip), %xmm0
	movl	$2, %edx
	movq	%r12, %rdi
	movl	$2, %esi
	call	_Z4initPfiif
	xorps	%xmm0, %xmm0
	movl	$6, %edx
	movq	%rbx, %rdi
	movl	$6, %esi
	call	_Z4initPfiif
	movq	%r12, %rdx
	movl	$6, %ecx
	movq	%rbp, %rsi
	movl	$6, %r8d
	call	_Z11host_conv2dPfS_S_ii
	movq	24(%rsp), %rdx
	xorl	%eax, %eax
.L41:
	imulq	$24, %rax, %r12
	xorl	%ebp, %ebp
.L45:
	movss	(%rbx,%r12), %xmm0
	ucomiss	(%rdx,%r12), %xmm0
	jp	.L48
	je	.L42
.L48:
	movl	%eax, %ebx
	movl	%ebp, %ecx
	movl	%eax, %edx
	movl	$2, %edi
	leaq	.LC2(%rip), %rsi
	movb	$1, %al
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	movq	24(%rsp), %rax
	movl	%ebp, %ecx
	movl	%ebx, %edx
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	cvtss2sd	(%rax,%r12), %xmm0
	movb	$1, %al
	call	__printf_chk@PLT
	jmp	.L44
.L42:
	incl	%ebp
	addq	$4, %r12
	cmpl	$6, %ebp
	jne	.L45
	incq	%rax
	cmpq	$6, %rax
	jne	.L41
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L44:
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L47
	call	__stack_chk_fail@PLT
.L47:
	addq	$64, %rsp
	.cfi_def_cfa_offset 32
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	main, .-main
	.section	.rodata.str1.1
.LC5:
	.string	"_Z10gpu_conv2dPfS_S_ii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z10gpu_conv2dPfS_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2057:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC1:
	.long	1065353216
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

// Assumption is input size == output size



#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>


#define mask_width  2
#define block_size  o_tile_width + mask_width - 1
#define o_tile_width 2


__global__
void gpu_conv2d(float *d_out, float *d_in, float *d_filter, int height, int width){
    __shared__ float sh_din[block_size][block_size];
    int tx = threadIdx.x;
    int ty = threadIdx.y;
    int row_o = blockIdx.y*o_tile_width + ty;
    int col_o = blockIdx.x * o_tile_width + tx;
    int diff = mask_width - 1;
    int row_i = row_o - diff;
    int col_i = col_o - diff;

    if ((row_i >= 0  && row_i < height) &&
    	(col_i >=0 && col_i < width )){
    	sh_din[ty][tx] = d_in[row_i*width + col_i];
    }
    else{
    	sh_din[ty][tx] = 0.0;
    }
    __syncthreads();

    float output = 0.0;

    if (tx < o_tile_width && ty < o_tile_width){
    	for (int i=0; i < mask_width; i++){
    		for (int j =0; j < mask_width; j++){
    			output += d_filter[i*mask_width + j] * sh_din[ty+i][tx+j]; 
    		}
    	}
    }
	if (tx < o_tile_width && ty < o_tile_width){
		d_out[row_o*width + col_o] = output;
	}

}


void init(float *arr, int h, int w, float val){
	for (int r=0; r < h; r++){
		for (int c=0; c < w; c++){
			arr[r*w + c] = val;
		}
	}
}



void host_conv2d(float *h_out, float *h_in, float *h_filter, int height, int width){

	for (int r=0; r<height; r++){
		for (int c =0; c < width; c++){
			float output = 0.0;
			int r_i = r - mask_width + 1;
			int c_i = c - mask_width + 1;
			//printf("r_i: %d , c_i: %d\n", r_i, c_i);
			for (int mr=0; mr<mask_width; mr++){
		        for (int mc=0; mc< mask_width; mc++){
	                if ( ((r_i+mr) >= 0 && (r_i + mr) < height) && ((c_i+mc) >=0 && (c_i+mc) < width) )
	                    output+= h_in[(mr + r_i)*width + (c_i+mc)] * h_filter[mr*mask_width + mc];
		        }
			}
			h_out[r*width + c] = output;
		}
	}

}



int main(){
	float *d_in, *d_filter, *d_out;
	float *h_in, *h_filter, *h_out; // Only for checking. Not needed for functionality

	int height = 6;
	int width = 6;

	size_t size_in = height*width*sizeof(float);
	size_t size_filter = mask_width*mask_width*sizeof(float);
	size_t size_out = height*width*sizeof(float);

	h_in = (float*) malloc (size_in);
	h_filter = (float*) malloc (size_filter);
	h_out = (float*) malloc (size_out);

	hipMallocManaged(&d_in, size_in);
	hipMallocManaged(&d_filter, size_filter);
	hipMallocManaged(&d_out, size_out);

	init(d_in, height, width, 1.0);
	init(d_filter, mask_width, mask_width, 1.0);
	init(d_out, height, width, 0.0);

	dim3 num_threads (block_size, block_size);
	dim3 num_blocks ((height-1)/(o_tile_width) + 1, (width-1)/(o_tile_width) + 1) ;

	gpu_conv2d<<<num_blocks, num_threads>>>(d_out, d_in, d_filter, height, width);
	hipDeviceSynchronize();


	init(h_in, height, width, 1.0);
	init(h_filter, mask_width, mask_width, 1.0);
	init(h_out, height, width, 0.0);

	host_conv2d(h_out, h_in, h_filter, height, width);
    
    for(int i=0; i<height; i++){
        for (int j=0; j<width; j++){
                if (d_out[i*width +j] != h_out[i*width +j]){
                        printf(" h_out[%d][%d]: %f", i, j, h_out[i*width + j]);
                        printf(" d_out[%d][%d]: %f", i, j, d_out[i*width + j]);
                        return 0;
                }
        }
    }

	/*
    for (int i =0; i<dout_size; i++)
            if (d_out[i] != h_out[i]){
                    printf("Program failed!! Check the idx: %d", i);
                    return 0;
            }
    */
    printf("Success!!\n");
}

	.text
	.file	"conv2d.hip"
	.globl	_Z25__device_stub__gpu_conv2dPfS_S_ii # -- Begin function _Z25__device_stub__gpu_conv2dPfS_S_ii
	.type	_Z25__device_stub__gpu_conv2dPfS_S_ii,@function
_Z25__device_stub__gpu_conv2dPfS_S_ii:  # @_Z25__device_stub__gpu_conv2dPfS_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10gpu_conv2dPfS_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z25__device_stub__gpu_conv2dPfS_S_ii, .Lfunc_end0-_Z25__device_stub__gpu_conv2dPfS_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z4initPfiif                    # -- Begin function _Z4initPfiif
	.type	_Z4initPfiif,@function
_Z4initPfiif:                           # @_Z4initPfiif
	.cfi_startproc
# %bb.0:
	testl	%esi, %esi
	jle	.LBB1_6
# %bb.1:                                # %.preheader.lr.ph
	movl	%esi, %eax
	movl	%edx, %ecx
	xorl	%esi, %esi
	xorl	%r8d, %r8d
.LBB1_2:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_4 Depth 2
	testl	%edx, %edx
	jle	.LBB1_5
# %bb.3:                                # %.lr.ph
                                        #   in Loop: Header=BB1_2 Depth=1
	movl	%esi, %r9d
	leaq	(%rdi,%r9,4), %r9
	xorl	%r10d, %r10d
.LBB1_4:                                #   Parent Loop BB1_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movss	%xmm0, (%r9,%r10,4)
	incq	%r10
	cmpq	%r10, %rcx
	jne	.LBB1_4
.LBB1_5:                                # %._crit_edge
                                        #   in Loop: Header=BB1_2 Depth=1
	incq	%r8
	addl	%edx, %esi
	cmpq	%rax, %r8
	jne	.LBB1_2
.LBB1_6:                                # %._crit_edge14
	retq
.Lfunc_end1:
	.size	_Z4initPfiif, .Lfunc_end1-_Z4initPfiif
	.cfi_endproc
                                        # -- End function
	.globl	_Z11host_conv2dPfS_S_ii         # -- Begin function _Z11host_conv2dPfS_S_ii
	.type	_Z11host_conv2dPfS_S_ii,@function
_Z11host_conv2dPfS_S_ii:                # @_Z11host_conv2dPfS_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r8d, -28(%rsp)                 # 4-byte Spill
	movq	%rdi, -16(%rsp)                 # 8-byte Spill
	testl	%ecx, %ecx
	jle	.LBB2_13
# %bb.1:                                # %.preheader45.lr.ph
	movslq	-28(%rsp), %rax                 # 4-byte Folded Reload
	movl	%ecx, %ecx
	movq	%rcx, -8(%rsp)                  # 8-byte Spill
	movl	%eax, %r9d
	xorl	%ecx, %ecx
	movq	%rcx, -24(%rsp)                 # 8-byte Spill
.LBB2_2:                                # %.preheader45
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_4 Depth 2
                                        #       Child Loop BB2_5 Depth 3
                                        #         Child Loop BB2_6 Depth 4
	cmpl	$0, -28(%rsp)                   # 4-byte Folded Reload
	jle	.LBB2_12
# %bb.3:                                # %.lr.ph
                                        #   in Loop: Header=BB2_2 Depth=1
	movq	-24(%rsp), %rcx                 # 8-byte Reload
	leaq	-1(%rcx), %r11
	imulq	%rax, %rcx
	movq	-16(%rsp), %rdi                 # 8-byte Reload
	leaq	(%rdi,%rcx,4), %rbx
	xorl	%r14d, %r14d
.LBB2_4:                                #   Parent Loop BB2_2 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB2_5 Depth 3
                                        #         Child Loop BB2_6 Depth 4
	leaq	-1(%r14), %r10
	xorps	%xmm0, %xmm0
	movb	$1, %bpl
	xorl	%ecx, %ecx
.LBB2_5:                                # %.preheader
                                        #   Parent Loop BB2_2 Depth=1
                                        #     Parent Loop BB2_4 Depth=2
                                        # =>    This Loop Header: Depth=3
                                        #         Child Loop BB2_6 Depth 4
	leaq	(%r11,%rcx), %r12
	movq	%r12, %rdi
	imulq	%rax, %rdi
	leaq	(%rsi,%rdi,4), %r13
	leaq	(%rdx,%rcx,8), %rcx
	movb	$1, %dil
	xorl	%r8d, %r8d
.LBB2_6:                                #   Parent Loop BB2_2 Depth=1
                                        #     Parent Loop BB2_4 Depth=2
                                        #       Parent Loop BB2_5 Depth=3
                                        # =>      This Inner Loop Header: Depth=4
	testq	%r12, %r12
	js	.LBB2_9
# %bb.7:                                #   in Loop: Header=BB2_6 Depth=4
	movq	%r10, %r15
	addq	%r8, %r15
	js	.LBB2_9
# %bb.8:                                #   in Loop: Header=BB2_6 Depth=4
	movss	(%r13,%r15,4), %xmm1            # xmm1 = mem[0],zero,zero,zero
	mulss	(%rcx,%r8,4), %xmm1
	addss	%xmm1, %xmm0
.LBB2_9:                                #   in Loop: Header=BB2_6 Depth=4
	movl	$1, %r8d
	testb	$1, %dil
	movl	$0, %edi
	jne	.LBB2_6
# %bb.10:                               #   in Loop: Header=BB2_5 Depth=3
	movl	$1, %ecx
	testb	$1, %bpl
	movl	$0, %ebp
	jne	.LBB2_5
# %bb.11:                               #   in Loop: Header=BB2_4 Depth=2
	movss	%xmm0, (%rbx,%r14,4)
	incq	%r14
	cmpq	%r9, %r14
	jne	.LBB2_4
.LBB2_12:                               # %._crit_edge
                                        #   in Loop: Header=BB2_2 Depth=1
	movq	-24(%rsp), %rdi                 # 8-byte Reload
	incq	%rdi
	movq	%rdi, %rcx
	movq	%rdi, -24(%rsp)                 # 8-byte Spill
	cmpq	-8(%rsp), %rdi                  # 8-byte Folded Reload
	jne	.LBB2_2
.LBB2_13:                               # %._crit_edge52
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z11host_conv2dPfS_S_ii, .Lfunc_end2-_Z11host_conv2dPfS_S_ii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function main
.LCPI3_0:
	.long	0x3f800000                      # float 1
	.long	0x3f800000                      # float 1
	.long	0x3f800000                      # float 1
	.long	0x3f800000                      # float 1
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$32, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	$144, %edi
	callq	malloc
	movq	%rax, %r14
	movl	$16, %edi
	callq	malloc
	movq	%rax, %r15
	movl	$144, %edi
	callq	malloc
	movq	%rax, %rbx
	leaq	24(%rsp), %r12
	movl	$144, %esi
	movq	%r12, %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	leaq	16(%rsp), %rdi
	movl	$16, %esi
	movl	$1, %edx
	callq	hipMallocManaged
	leaq	8(%rsp), %rdi
	movl	$144, %esi
	movl	$1, %edx
	callq	hipMallocManaged
	xorl	%eax, %eax
	movq	(%r12), %rcx
.LBB3_1:                                # %.preheader.i
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_2 Depth 2
	xorl	%edx, %edx
.LBB3_2:                                #   Parent Loop BB3_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	$1065353216, (%rcx,%rdx,4)      # imm = 0x3F800000
	incq	%rdx
	cmpq	$6, %rdx
	jne	.LBB3_2
# %bb.3:                                # %._crit_edge.i
                                        #   in Loop: Header=BB3_1 Depth=1
	incq	%rax
	addq	$24, %rcx
	cmpq	$6, %rax
	jne	.LBB3_1
# %bb.4:                                # %_Z4initPfiif.exit
	movq	16(%rsp), %rax
	movaps	.LCPI3_0(%rip), %xmm0           # xmm0 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0]
	movups	%xmm0, (%rax)
	movq	8(%rsp), %rdi
	movl	$144, %edx
	xorl	%esi, %esi
	callq	memset@PLT
	movabsq	$12884901891, %rdi              # imm = 0x300000003
	movl	$1, %esi
	movq	%rdi, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_6
# %bb.5:
	movq	8(%rsp), %rdi
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	movl	$6, %ecx
	movl	$6, %r8d
	callq	_Z25__device_stub__gpu_conv2dPfS_S_ii
.LBB3_6:
	callq	hipDeviceSynchronize
	xorl	%eax, %eax
	movq	%r14, %rcx
.LBB3_7:                                # %.preheader.i92
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_8 Depth 2
	xorl	%edx, %edx
.LBB3_8:                                #   Parent Loop BB3_7 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	$1065353216, (%rcx,%rdx,4)      # imm = 0x3F800000
	incq	%rdx
	cmpq	$6, %rdx
	jne	.LBB3_8
# %bb.9:                                # %._crit_edge.i99
                                        #   in Loop: Header=BB3_7 Depth=1
	incq	%rax
	addq	$24, %rcx
	cmpq	$6, %rax
	jne	.LBB3_7
# %bb.10:                               # %.preheader.i103.preheader
	movaps	.LCPI3_0(%rip), %xmm0           # xmm0 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0]
	movups	%xmm0, (%r15)
	xorl	%r12d, %r12d
	movl	$144, %edx
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
	movq	%rbx, %rdi
	movq	%r14, %rsi
	movq	%r15, %rdx
	movl	$6, %ecx
	movl	$6, %r8d
	callq	_Z11host_conv2dPfS_S_ii
	movq	8(%rsp), %rax
	xorl	%r14d, %r14d
.LBB3_11:                               # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_12 Depth 2
	movq	%r12, %r13
	xorl	%r15d, %r15d
.LBB3_12:                               #   Parent Loop BB3_11 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movss	(%rax,%r13), %xmm1              # xmm1 = mem[0],zero,zero,zero
	movss	(%rbx,%r13), %xmm0              # xmm0 = mem[0],zero,zero,zero
	ucomiss	%xmm0, %xmm1
	jne	.LBB3_17
	jp	.LBB3_17
# %bb.13:                               #   in Loop: Header=BB3_12 Depth=2
	decq	%r15
	addq	$4, %r13
	cmpq	$-6, %r15
	jne	.LBB3_12
# %bb.14:                               # %.critedge
                                        #   in Loop: Header=BB3_11 Depth=1
	incq	%r14
	addq	$24, %r12
	cmpq	$6, %r14
	jne	.LBB3_11
# %bb.15:                               # %.critedge69
	movl	$.Lstr, %edi
	callq	puts@PLT
	jmp	.LBB3_16
.LBB3_17:
	negl	%r15d
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str, %edi
	movl	%r14d, %esi
	movl	%r15d, %edx
	movb	$1, %al
	callq	printf
	movq	8(%rsp), %rax
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rax,%r13), %xmm0
	movl	$.L.str.1, %edi
	movl	%r14d, %esi
	movl	%r15d, %edx
	movb	$1, %al
	callq	printf
.LBB3_16:
	xorl	%eax, %eax
	addq	$32, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10gpu_conv2dPfS_S_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z10gpu_conv2dPfS_S_ii,@object  # @_Z10gpu_conv2dPfS_S_ii
	.section	.rodata,"a",@progbits
	.globl	_Z10gpu_conv2dPfS_S_ii
	.p2align	3, 0x0
_Z10gpu_conv2dPfS_S_ii:
	.quad	_Z25__device_stub__gpu_conv2dPfS_S_ii
	.size	_Z10gpu_conv2dPfS_S_ii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	" h_out[%d][%d]: %f"
	.size	.L.str, 19

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	" d_out[%d][%d]: %f"
	.size	.L.str.1, 19

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z10gpu_conv2dPfS_S_ii"
	.size	.L__unnamed_1, 23

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Success!!"
	.size	.Lstr, 10

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub__gpu_conv2dPfS_S_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z10gpu_conv2dPfS_S_ii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z10gpu_conv2dPfS_S_ii  ; -- Begin function _Z10gpu_conv2dPfS_S_ii
	.globl	_Z10gpu_conv2dPfS_S_ii
	.p2align	8
	.type	_Z10gpu_conv2dPfS_S_ii,@function
_Z10gpu_conv2dPfS_S_ii:                 ; @_Z10gpu_conv2dPfS_S_ii
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_bfe_u32 v1, v0, 10, 10
	v_dual_mov_b32 v5, 0 :: v_dual_and_b32 v4, 0x3ff, v0
	v_mov_b32_e32 v2, 0
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshl_add_u32 v3, s15, 1, v1
	v_lshl_add_u32 v0, s14, 1, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_lt_i32_e32 0, v3
	s_cbranch_execz .LBB0_4
; %bb.1:
	s_waitcnt lgkmcnt(0)
	v_cmp_ge_i32_e32 vcc_lo, s10, v3
	v_cmp_ge_i32_e64 s0, s11, v0
	v_cmp_lt_i32_e64 s1, 0, v0
	v_mov_b32_e32 v5, 0
	s_delay_alu instid0(VALU_DEP_3)
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_3
; %bb.2:
	v_add_nc_u32_e32 v5, -1, v3
	v_ashrrev_i32_e32 v6, 31, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v5, v5, s11
	v_ashrrev_i32_e32 v7, 31, v5
	v_add_co_u32 v5, vcc_lo, v0, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v6, vcc_lo, v6, v7, vcc_lo
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, s6, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo
	global_load_b32 v5, v[5:6], off offset:-4
.LBB0_3:                                ; %Flow80
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_4:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s2
	v_lshlrev_b32_e32 v6, 2, v4
	v_or_b32_e32 v4, v4, v1
	v_mad_u32_u24 v1, v1, 12, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_gt_u32_e64 s0, 2, v4
	s_waitcnt vmcnt(0)
	ds_store_b32 v1, v5
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_7
; %bb.5:                                ; %.preheader.preheader
	v_mov_b32_e32 v2, 0
	s_mov_b32 s3, 0
	s_mov_b32 s6, -1
	s_mov_b32 s2, 0
.LBB0_6:                                ; %.preheader
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[4:5], null, s2, 12, v[1:2]
	s_lshl_b32 s2, s2, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[12:13], s[2:3], 2
	s_mov_b32 s2, 1
	s_add_u32 s12, s8, s12
	s_addc_u32 s13, s9, s13
	ds_load_2addr_b32 v[4:5], v4 offset1:1
	s_load_b64 s[12:13], s[12:13], 0x0
	s_and_b32 vcc_lo, exec_lo, s6
	s_mov_b32 s6, 0
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v2, s12, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v2, s13, v5
	s_cbranch_vccnz .LBB0_6
.LBB0_7:                                ; %Flow79
	s_or_b32 exec_lo, exec_lo, s1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_9
; %bb.8:
	v_mad_u64_u32 v[4:5], null, v3, s11, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[0:1], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB0_9:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10gpu_conv2dPfS_S_ii
		.amdhsa_group_segment_fixed_size 36
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 32
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z10gpu_conv2dPfS_S_ii, .Lfunc_end0-_Z10gpu_conv2dPfS_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 440
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 36 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 36
    .kernarg_segment_align: 8
    .kernarg_segment_size: 32
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10gpu_conv2dPfS_S_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z10gpu_conv2dPfS_S_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
