#include "includes.h"
/*
* CudaOperations.cu
*
*  Created on: Feb 6, 2019
*      Author: alexander
*/


__global__ void cudaKernelPull(float* mat, float* spins, int size, float* temp, float tempStep, float* meanFieldElements, bool* continueIteration, float minDiff, int* unemptyCells, float linearCoef) {
int blockId = blockIdx.x;
int thrId = threadIdx.x;

do {
// Lessen temperature
if (thrId == 0)
temp[blockId] = temp[blockId] - tempStep;

// Stabilize
do {
__syncthreads();
// By default current iteration is the last one
if (thrId == 0)
continueIteration[blockId] = false;

for (int spinId = 0; spinId < size; ++spinId) {
__syncthreads();

// Transitional value assignment
int wIndex = thrId;
while (wIndex < unemptyCells[spinId * (size + 1)]) {
meanFieldElements[wIndex + blockId * size] =
spins[unemptyCells[spinId * (size + 1) + wIndex + 1]
+ blockId * size]
* mat[spinId * size
+ unemptyCells[spinId * (size + 1)
+ wIndex + 1]];
// BEWARE: Matrix is symmetrical!
wIndex = wIndex + blockDim.x;
}
__syncthreads();

// Parallelized mean-field computation
long long offset = 1;
while (offset < unemptyCells[spinId * (size + 1)]) {
wIndex = thrId;
while ((wIndex * 2 + 1) * offset
< unemptyCells[spinId * (size + 1)]) {
meanFieldElements[wIndex * 2 * offset + blockId * size] +=
meanFieldElements[(wIndex * 2 + 1) * offset
+ blockId * size];
wIndex = wIndex + blockDim.x;
}
offset *= 2;
__syncthreads();
}
__syncthreads();

// Mean-field calculation complete - write new spin and delta
if (thrId == 0) {
float meanField = meanFieldElements[blockId * size];
float old = spins[spinId + blockId * size];
if (temp[blockId] > 0) {
spins[spinId + blockId * size] = -1
* tanh(meanField / temp[blockId]) * linearCoef
+ spins[spinId + blockId * size]
* (1 - linearCoef);
} else if (meanField > 0)
spins[spinId + blockId * size] = -1;
else
spins[spinId + blockId * size] = 1;

if (minDiff < fabs(old - spins[spinId + blockId * size]))
continueIteration[blockId] = true; // Too big delta. One more iteration needed
}
__syncthreads();
}
} while (continueIteration[blockId]);
} while (temp[blockId] >= 0);
}
	.file	"tmpxft_00344f98_00000000-6_cudaKernelPull.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z48__device_stub__Z14cudaKernelPullPfS_iS_fS_PbfPifPfS_iS_fS_PbfPif
	.type	_Z48__device_stub__Z14cudaKernelPullPfS_iS_fS_PbfPifPfS_iS_fS_PbfPif, @function
_Z48__device_stub__Z14cudaKernelPullPfS_iS_fS_PbfPifPfS_iS_fS_PbfPif:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$232, %rsp
	.cfi_def_cfa_offset 240
	movq	240(%rsp), %rax
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movl	%edx, 44(%rsp)
	leaq	72(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	80(%rsp), %rcx
	movq	%r8, 24(%rsp)
	movq	%r9, 16(%rsp)
	movq	%rax, (%rsp)
	movss	%xmm0, 40(%rsp)
	movss	%xmm1, 12(%rsp)
	movss	%xmm2, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 216(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movl	$1, 96(%rsp)
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	44(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 192(%rsp)
	movq	%rsp, %rax
	movq	%rax, 200(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 208(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	80(%rsp)
	.cfi_def_cfa_offset 248
	leaq	_Z14cudaKernelPullPfS_iS_fS_PbfPif(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 256
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 248
	popq	%rdx
	.cfi_def_cfa_offset 240
.L2:
	movq	216(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$232, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z48__device_stub__Z14cudaKernelPullPfS_iS_fS_PbfPifPfS_iS_fS_PbfPif, .-_Z48__device_stub__Z14cudaKernelPullPfS_iS_fS_PbfPifPfS_iS_fS_PbfPif
	.globl	_Z14cudaKernelPullPfS_iS_fS_PbfPif
	.type	_Z14cudaKernelPullPfS_iS_fS_PbfPif, @function
_Z14cudaKernelPullPfS_iS_fS_PbfPif:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z48__device_stub__Z14cudaKernelPullPfS_iS_fS_PbfPifPfS_iS_fS_PbfPif
	.cfi_endproc
.LFE2033:
	.size	_Z14cudaKernelPullPfS_iS_fS_PbfPif, .-_Z14cudaKernelPullPfS_iS_fS_PbfPif
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z14cudaKernelPullPfS_iS_fS_PbfPif"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z14cudaKernelPullPfS_iS_fS_PbfPif(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
/*
* CudaOperations.cu
*
*  Created on: Feb 6, 2019
*      Author: alexander
*/


__global__ void cudaKernelPull(float* mat, float* spins, int size, float* temp, float tempStep, float* meanFieldElements, bool* continueIteration, float minDiff, int* unemptyCells, float linearCoef) {
int blockId = blockIdx.x;
int thrId = threadIdx.x;

do {
// Lessen temperature
if (thrId == 0)
temp[blockId] = temp[blockId] - tempStep;

// Stabilize
do {
__syncthreads();
// By default current iteration is the last one
if (thrId == 0)
continueIteration[blockId] = false;

for (int spinId = 0; spinId < size; ++spinId) {
__syncthreads();

// Transitional value assignment
int wIndex = thrId;
while (wIndex < unemptyCells[spinId * (size + 1)]) {
meanFieldElements[wIndex + blockId * size] =
spins[unemptyCells[spinId * (size + 1) + wIndex + 1]
+ blockId * size]
* mat[spinId * size
+ unemptyCells[spinId * (size + 1)
+ wIndex + 1]];
// BEWARE: Matrix is symmetrical!
wIndex = wIndex + blockDim.x;
}
__syncthreads();

// Parallelized mean-field computation
long long offset = 1;
while (offset < unemptyCells[spinId * (size + 1)]) {
wIndex = thrId;
while ((wIndex * 2 + 1) * offset
< unemptyCells[spinId * (size + 1)]) {
meanFieldElements[wIndex * 2 * offset + blockId * size] +=
meanFieldElements[(wIndex * 2 + 1) * offset
+ blockId * size];
wIndex = wIndex + blockDim.x;
}
offset *= 2;
__syncthreads();
}
__syncthreads();

// Mean-field calculation complete - write new spin and delta
if (thrId == 0) {
float meanField = meanFieldElements[blockId * size];
float old = spins[spinId + blockId * size];
if (temp[blockId] > 0) {
spins[spinId + blockId * size] = -1
* tanh(meanField / temp[blockId]) * linearCoef
+ spins[spinId + blockId * size]
* (1 - linearCoef);
} else if (meanField > 0)
spins[spinId + blockId * size] = -1;
else
spins[spinId + blockId * size] = 1;

if (minDiff < fabs(old - spins[spinId + blockId * size]))
continueIteration[blockId] = true; // Too big delta. One more iteration needed
}
__syncthreads();
}
} while (continueIteration[blockId]);
} while (temp[blockId] >= 0);
}
	.text
	.file	"cudaKernelPull.hip"
	.globl	_Z29__device_stub__cudaKernelPullPfS_iS_fS_PbfPif # -- Begin function _Z29__device_stub__cudaKernelPullPfS_iS_fS_PbfPif
	.type	_Z29__device_stub__cudaKernelPullPfS_iS_fS_PbfPif,@function
_Z29__device_stub__cudaKernelPullPfS_iS_fS_PbfPif: # @_Z29__device_stub__cudaKernelPullPfS_iS_fS_PbfPif
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	20(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	56(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	16(%rsp), %rcx
	movss	%xmm0, (%rcx)
	leaq	48(%rsp), %r10
	movq	%r8, (%r10)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	12(%rsp), %r9
	movss	%xmm1, (%r9)
	leaq	8(%rsp), %r11
	movss	%xmm2, (%r11)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r10, 40(%rbx)
	movq	%r8, 48(%rbx)
	movq	%r9, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	movq	%r11, 72(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14cudaKernelPullPfS_iS_fS_PbfPif, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z29__device_stub__cudaKernelPullPfS_iS_fS_PbfPif, .Lfunc_end0-_Z29__device_stub__cudaKernelPullPfS_iS_fS_PbfPif
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14cudaKernelPullPfS_iS_fS_PbfPif, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z14cudaKernelPullPfS_iS_fS_PbfPif,@object # @_Z14cudaKernelPullPfS_iS_fS_PbfPif
	.section	.rodata,"a",@progbits
	.globl	_Z14cudaKernelPullPfS_iS_fS_PbfPif
	.p2align	3, 0x0
_Z14cudaKernelPullPfS_iS_fS_PbfPif:
	.quad	_Z29__device_stub__cudaKernelPullPfS_iS_fS_PbfPif
	.size	_Z14cudaKernelPullPfS_iS_fS_PbfPif, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z14cudaKernelPullPfS_iS_fS_PbfPif"
	.size	.L__unnamed_1, 35

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z29__device_stub__cudaKernelPullPfS_iS_fS_PbfPif
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z14cudaKernelPullPfS_iS_fS_PbfPif
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z14cudaKernelPullPfS_iS_fS_PbfPif ; -- Begin function _Z14cudaKernelPullPfS_iS_fS_PbfPif
	.globl	_Z14cudaKernelPullPfS_iS_fS_PbfPif
	.p2align	8
	.type	_Z14cudaKernelPullPfS_iS_fS_PbfPif,@function
_Z14cudaKernelPullPfS_iS_fS_PbfPif:     ; @_Z14cudaKernelPullPfS_iS_fS_PbfPif
; %bb.0:
	s_clause 0x5
	s_load_b64 s[16:17], s[0:1], 0x18
	s_load_b128 s[8:11], s[0:1], 0x28
	s_load_b32 s3, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[12:13], s[0:1], 0x40
	s_load_b32 s24, s[0:1], 0x48
	s_mov_b32 s18, s15
	s_clause 0x1
	s_load_b32 s25, s[0:1], 0x20
	s_load_b32 s26, s[0:1], 0x38
	s_ashr_i32 s19, s18, 31
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v7, 1
	s_lshl_b64 s[20:21], s[18:19], 2
	v_cmp_eq_u32_e64 s2, 0, v0
	s_mov_b32 s15, 0
	s_mov_b32 s30, 0xbbbac73d
	s_waitcnt lgkmcnt(0)
	s_add_u32 s16, s16, s20
	s_addc_u32 s17, s17, s21
	s_add_u32 s10, s10, s18
	s_addc_u32 s11, s11, s19
	s_cmp_gt_i32 s3, 0
	s_mul_i32 s18, s18, s3
	s_cselect_b32 s27, -1, 0
	s_add_i32 s28, s3, 1
	s_add_u32 s20, s0, 0x50
	s_addc_u32 s21, s1, 0
	s_ashr_i32 s19, s18, 31
	v_sub_f32_e64 v8, 1.0, s24
	s_lshl_b64 s[0:1], s[18:19], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s8, s8, s0
	s_addc_u32 s9, s9, s1
	s_add_u32 s19, s12, 4
	s_addc_u32 s29, s13, 0
.LBB0_1:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
                                        ;       Child Loop BB0_8 Depth 3
                                        ;         Child Loop BB0_10 Depth 4
                                        ;         Child Loop BB0_13 Depth 4
                                        ;           Child Loop BB0_14 Depth 5
	s_and_saveexec_b32 s0, s2
	s_cbranch_execz .LBB0_3
; %bb.2:                                ;   in Loop: Header=BB0_1 Depth=1
	global_load_b32 v1, v2, s[16:17]
	s_waitcnt vmcnt(0)
	v_subrev_f32_e32 v1, s25, v1
	global_store_b32 v2, v1, s[16:17]
.LBB0_3:                                ; %.preheader123
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_4:                                ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_8 Depth 3
                                        ;         Child Loop BB0_10 Depth 4
                                        ;         Child Loop BB0_13 Depth 4
                                        ;           Child Loop BB0_14 Depth 5
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s0, s2
	s_cbranch_execz .LBB0_6
; %bb.5:                                ;   in Loop: Header=BB0_4 Depth=2
	global_store_b8 v2, v2, s[10:11]
.LBB0_6:                                ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s27
	s_cbranch_vccnz .LBB0_32
; %bb.7:                                ; %.lr.ph121.preheader
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_mov_b32 s31, 0
	s_mov_b32 s33, 0
.LBB0_8:                                ; %.lr.ph121
                                        ;   Parent Loop BB0_1 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_10 Depth 4
                                        ;         Child Loop BB0_13 Depth 4
                                        ;           Child Loop BB0_14 Depth 5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mul_i32 s14, s33, s28
	s_waitcnt_vscnt null, 0x0
	s_lshl_b64 s[0:1], s[14:15], 2
	s_barrier
	s_add_u32 s22, s12, s0
	s_addc_u32 s23, s13, s1
	buffer_gl0_inv
	global_load_b32 v1, v2, s[22:23]
	s_mov_b32 s1, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e64 v0, v1
	s_cbranch_execz .LBB0_11
; %bb.9:                                ; %.lr.ph
                                        ;   in Loop: Header=BB0_8 Depth=3
	s_load_b32 s0, s[20:21], 0xc
	v_mov_b32_e32 v3, v0
	s_mul_i32 s14, s33, s3
	s_mov_b32 s35, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s34, s0, 0xffff
.LBB0_10:                               ;   Parent Loop BB0_1 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ;       Parent Loop BB0_8 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	v_add_nc_u32_e32 v4, s31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s19, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s29, v5, vcc_lo
	global_load_b32 v5, v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, s18, v5
	v_add_nc_u32_e32 v9, s14, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v5, 31, v4
	v_ashrrev_i32_e32 v10, 31, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_lshlrev_b64 v[9:10], 2, v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, s6, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v9, vcc_lo, s4, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
	global_load_b32 v6, v[4:5], off
	global_load_b32 v9, v[9:10], off
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[4:5], 2, v[3:4]
	v_add_nc_u32_e32 v3, s34, v3
	v_add_co_u32 v4, s0, s8, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v5, s0, s9, v5, s0
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v6, v6, v9
	v_cmp_ge_i32_e32 vcc_lo, v3, v1
	global_store_b32 v[4:5], v6, off
	s_or_b32 s35, vcc_lo, s35
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s35
	s_cbranch_execnz .LBB0_10
.LBB0_11:                               ; %Flow156
                                        ;   in Loop: Header=BB0_8 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	global_load_b32 v1, v2, s[22:23]
	s_waitcnt vmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, 2, v1
	s_cbranch_vccnz .LBB0_18
; %bb.12:                               ; %.preheader.preheader
                                        ;   in Loop: Header=BB0_8 Depth=3
	v_dual_mov_b32 v4, v2 :: v_dual_mov_b32 v3, v1
	s_mov_b64 s[0:1], 1
.LBB0_13:                               ; %.preheader
                                        ;   Parent Loop BB0_1 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ;       Parent Loop BB0_8 Depth=3
                                        ; =>      This Loop Header: Depth=4
                                        ;           Child Loop BB0_14 Depth 5
	v_mov_b32_e32 v1, v0
	s_mov_b32 s14, 0
                                        ; implicit-def: $sgpr34
.LBB0_14:                               ;   Parent Loop BB0_1 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ;       Parent Loop BB0_8 Depth=3
                                        ;         Parent Loop BB0_13 Depth=4
                                        ; =>        This Inner Loop Header: Depth=5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v9, 1, v1
	s_or_b32 s34, s34, exec_lo
	s_mov_b32 s35, exec_lo
	v_ashrrev_i32_e32 v5, 31, v9
	v_or_b32_e32 v11, 1, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v10, s0, v5
	v_mul_lo_u32 v12, s1, v11
	v_mad_u64_u32 v[5:6], null, s0, v11, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v6, v6, v10, v12
	v_cmpx_lt_i64_e64 v[5:6], v[3:4]
	s_cbranch_execz .LBB0_16
; %bb.15:                               ;   in Loop: Header=BB0_14 Depth=5
	v_mul_lo_u32 v13, s1, v9
	v_mad_u64_u32 v[11:12], null, s0, v9, 0
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_and_not1_b32 s34, s34, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v5, vcc_lo, s8, v5
	v_add3_u32 v12, v12, v10, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s9, v6, vcc_lo
	v_lshlrev_b64 v[9:10], 2, v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s8, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s9, v10, vcc_lo
	s_clause 0x1
	global_load_b32 v5, v[5:6], off
	global_load_b32 v6, v[9:10], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v5, v5, v6
	global_store_b32 v[9:10], v5, off
	s_load_b32 s36, s[20:21], 0xc
	s_waitcnt lgkmcnt(0)
	s_and_b32 s36, s36, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_nc_u32_e32 v1, s36, v1
.LBB0_16:                               ; %Flow152
                                        ;   in Loop: Header=BB0_14 Depth=5
	s_or_b32 exec_lo, exec_lo, s35
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s35, exec_lo, s34
	s_or_b32 s14, s35, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s14
	s_cbranch_execnz .LBB0_14
; %bb.17:                               ;   in Loop: Header=BB0_13 Depth=4
	s_or_b32 exec_lo, exec_lo, s14
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	global_load_b32 v3, v2, s[22:23]
	s_lshl_b64 s[0:1], s[0:1], 1
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_i64_e32 vcc_lo, s[0:1], v[3:4]
	s_cbranch_vccnz .LBB0_13
.LBB0_18:                               ; %._crit_edge118
                                        ;   in Loop: Header=BB0_8 Depth=3
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s14, s2
	s_cbranch_execz .LBB0_31
; %bb.19:                               ;   in Loop: Header=BB0_8 Depth=3
	s_add_i32 s0, s33, s18
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s1, s0, 31
	s_lshl_b64 s[0:1], s[0:1], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	s_clause 0x2
	global_load_b32 v1, v2, s[0:1]
	global_load_b32 v3, v2, s[16:17]
	global_load_b32 v4, v2, s[8:9]
	s_waitcnt vmcnt(1)
	v_cmp_nlt_f32_e32 vcc_lo, 0, v3
	s_cbranch_vccz .LBB0_21
; %bb.20:                               ;   in Loop: Header=BB0_8 Depth=3
	s_waitcnt vmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, 0, v4
	s_mov_b32 s22, 0
	v_cndmask_b32_e64 v5, 1.0, -1.0, vcc_lo
	s_branch .LBB0_22
.LBB0_21:                               ;   in Loop: Header=BB0_8 Depth=3
	s_mov_b32 s22, -1
                                        ; implicit-def: $vgpr5
.LBB0_22:                               ; %Flow149
                                        ;   in Loop: Header=BB0_8 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s22
	s_cbranch_vccnz .LBB0_29
; %bb.23:                               ;   in Loop: Header=BB0_8 Depth=3
	s_waitcnt vmcnt(0)
	v_div_scale_f32 v5, null, v3, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v6, v5
	s_waitcnt_depctr 0xfff
	v_fma_f32 v9, -v5, v6, 1.0
	v_fmac_f32_e32 v6, v9, v6
	v_div_scale_f32 v9, vcc_lo, v4, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v10, v9, v6
	v_fma_f32 v11, -v5, v10, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v10, v11, v6
	v_fma_f32 v5, -v5, v10, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v5, v5, v6, v10
	v_div_fixup_f32 v3, v5, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ngt_f32_e64 s22, 0x3f200000, |v3|
	s_and_b32 vcc_lo, exec_lo, s22
	s_cbranch_vccz .LBB0_25
; %bb.24:                               ;   in Loop: Header=BB0_8 Depth=3
	v_add_f32_e64 v4, |v3|, |v3|
	s_mov_b32 s22, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v5, 0x3fb8aa3b, v4
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v4
	v_rndne_f32_e32 v6, v5
	v_fma_f32 v9, 0x3fb8aa3b, v4, -v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v5, v5, v6
	v_fmac_f32_e32 v9, 0x32a5705f, v4
	v_cvt_i32_f32_e32 v6, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v5, v9
	v_exp_f32_e32 v5, v5
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v5, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v5, 0, v5, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v4
	v_cndmask_b32_e32 v4, 0x7f800000, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v4, 1.0, v4
	v_rcp_f32_e32 v4, v4
	s_waitcnt_depctr 0xfff
	v_fma_f32 v4, v4, -2.0, 1.0
	s_branch .LBB0_26
.LBB0_25:                               ;   in Loop: Header=BB0_8 Depth=3
	s_mov_b32 s22, -1
                                        ; implicit-def: $vgpr4
.LBB0_26:                               ; %Flow148
                                        ;   in Loop: Header=BB0_8 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s22
	s_cbranch_vccnz .LBB0_28
; %bb.27:                               ;   in Loop: Header=BB0_8 Depth=3
	v_mul_f32_e32 v4, v3, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v5, s30, v4, 0x3ca908c9
	v_fmaak_f32 v5, v4, v5, 0xbd5c1c4e
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v5, v4, v5, 0x3e088382
	v_fmaak_f32 v5, v4, v5, 0xbeaaaa99
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e64 v5, |v3|, v5
	v_fma_f32 v4, v4, v5, |v3|
.LBB0_28:                               ; %_ZL4tanhf.exit
                                        ;   in Loop: Header=BB0_8 Depth=3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_bfi_b32 v3, 0x7fffffff, v4, v3
	v_mul_f32_e32 v3, s24, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f32 v5, v8, v1, -v3
.LBB0_29:                               ;   in Loop: Header=BB0_8 Depth=3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v1, v1, v5
	global_store_b32 v2, v5, s[0:1]
	v_cmp_ngt_f32_e64 s22, |v1|, s26
	s_and_b32 vcc_lo, exec_lo, s22
	s_cbranch_vccnz .LBB0_31
; %bb.30:                               ;   in Loop: Header=BB0_8 Depth=3
	global_store_b8 v2, v7, s[10:11]
.LBB0_31:                               ; %Flow151
                                        ;   in Loop: Header=BB0_8 Depth=3
	s_or_b32 exec_lo, exec_lo, s14
	s_add_i32 s33, s33, 1
	s_add_i32 s31, s31, s28
	s_cmp_eq_u32 s33, s3
	s_waitcnt vmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_8
.LBB0_32:                               ; %._crit_edge122
                                        ;   in Loop: Header=BB0_4 Depth=2
	global_load_u8 v1, v2, s[10:11]
	s_waitcnt vmcnt(0)
	v_cmp_eq_u16_e32 vcc_lo, 0, v1
	s_cbranch_vccz .LBB0_4
; %bb.33:                               ;   in Loop: Header=BB0_1 Depth=1
	global_load_b32 v1, v2, s[16:17]
	s_waitcnt vmcnt(0)
	v_cmp_le_f32_e32 vcc_lo, 0, v1
	s_cbranch_vccnz .LBB0_1
; %bb.34:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14cudaKernelPullPfS_iS_fS_PbfPif
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 336
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 37
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z14cudaKernelPullPfS_iS_fS_PbfPif, .Lfunc_end0-_Z14cudaKernelPullPfS_iS_fS_PbfPif
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1592
; NumSgprs: 39
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 39
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .offset:         72
        .size:           4
        .value_kind:     by_value
      - .offset:         80
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         84
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         88
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         92
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         94
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         96
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         98
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         100
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         102
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         144
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 336
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z14cudaKernelPullPfS_iS_fS_PbfPif
    .private_segment_fixed_size: 0
    .sgpr_count:     39
    .sgpr_spill_count: 0
    .symbol:         _Z14cudaKernelPullPfS_iS_fS_PbfPif.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     14
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
