
// listPrimes - shows the prime numbers between a fixed range.
//      this is a CUDA version that uses 1 thread in 1 block just using 
//      a simple serial approach
// Eric McCreath 2019 - GPL 

// based on https://en.wikipedia.org/wiki/Integer_square_root
// assumes a positive number


#include<stdio.h>
#include<cuda.h>

// this macro checks for errors in cuda calls
#define Err(ans) { gpucheck((ans), __FILE__, __LINE__); }
inline void gpucheck(cudaError_t code, const char *file, int line)
{
   if (code != cudaSuccess) 
   {
      fprintf(stderr,"GPU Err: %s %s %d\n", cudaGetErrorString(code), file, line);
      exit(code);
   }
}

// based on https://en.wikipedia.org/wiki/Integer_square_root
// assumes a positive number
long intsquroot(long n) {
	long shift = 2;
	long nShifted = n >> shift;

	while (nShifted != 0 && nShifted != n) {
		shift += 2;
		nShifted = n >> shift;
	}
	shift -= 2;
	long result = 0;
    while (shift >= 0) {
	    result = result << 1;
	    long candidateResult = result + 1;
	    if (candidateResult*candidateResult <= n >> shift) {
	        result = candidateResult;
	    }
	    shift = shift - 2;
	}
	return result;
}

__global__  void divides(long v, long sqrt, int *isprime) {
   long i;
   for (i = 2 + blockIdx.x * blockDim.x + threadIdx.x;
        (i <= sqrt) && (*isprime == 1);
         i +=  blockDim.x* gridDim.x) {
         if (v % i == 0) *isprime = 0;    
   }
}

int isPrime(long v) {

	long srt = intsquroot(v);
	int isprime = 1;
	int *isprime_d;
	Err(cudaMalloc( &isprime_d, sizeof(int)));
	
	Err(cudaMemcpy(isprime_d, &isprime, sizeof(int), cudaMemcpyHostToDevice));

        divides<<<100000,1024>>>(v,srt,isprime_d);

	Err(cudaMemcpy(&isprime,isprime_d,sizeof(int),cudaMemcpyDeviceToHost));
	
	Err(cudaFree(isprime_d));

	return isprime;
}

void listPrimes(long start, long end) {
	    for (long num = start; num < end ; num++) {
		    printf ("%ld : %s\n", num, (isPrime(num)? "yes" : "no"));
	    }
}

int main() {
    long largestlong = 0x7FFFFFFFFFFFFFFFL;
	listPrimes(largestlong-100L,largestlong);
    return 0;
}

	.file	"tmpxft_002dd733_00000000-6_listprimesV1eric.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2034:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2034:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata._Z8gpucheck9cudaErrorPKci.str1.1,"aMS",@progbits,1
.LC0:
	.string	"GPU Err: %s %s %d\n"
	.section	.text._Z8gpucheck9cudaErrorPKci,"axG",@progbits,_Z8gpucheck9cudaErrorPKci,comdat
	.weak	_Z8gpucheck9cudaErrorPKci
	.type	_Z8gpucheck9cudaErrorPKci, @function
_Z8gpucheck9cudaErrorPKci:
.LFB2027:
	.cfi_startproc
	endbr64
	testl	%edi, %edi
	je	.L2
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movl	%edi, %ebx
	subq	$16, %rsp
	.cfi_def_cfa_offset 32
	movl	%edx, 12(%rsp)
	movq	%rsi, (%rsp)
	call	cudaGetErrorString@PLT
	movq	stderr(%rip), %rdi
	movq	(%rsp), %r8
	leaq	.LC0(%rip), %rdx
	movl	12(%rsp), %r9d
	movq	%rax, %rcx
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	movl	%ebx, %edi
	call	exit@PLT
.L2:
	.cfi_def_cfa_offset 8
	.cfi_restore 3
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z8gpucheck9cudaErrorPKci, .-_Z8gpucheck9cudaErrorPKci
	.text
	.globl	_Z10intsqurootl
	.type	_Z10intsqurootl, @function
_Z10intsqurootl:
.LFB2028:
	.cfi_startproc
	endbr64
	movq	%rdi, %rax
	movl	$2, %ecx
	sarq	$2, %rax
.L9:
	testq	%rax, %rax
	je	.L14
	cmpq	%rdi, %rax
	je	.L14
	addq	$2, %rcx
	movq	%rdi, %rax
	sarq	%cl, %rax
	jmp	.L9
.L14:
	subq	$2, %rcx
	xorl	%eax, %eax
.L13:
	leaq	(%rax,%rax), %rdx
	movq	%rdi, %rsi
	leaq	1(%rdx), %rax
	sarq	%cl, %rsi
	movq	%rax, %r8
	imulq	%rax, %r8
	cmpq	%rsi, %r8
	cmovg	%rdx, %rax
	subq	$2, %rcx
	jns	.L13
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z10intsqurootl, .-_Z10intsqurootl
	.globl	_Z28__device_stub__Z7dividesllPillPi
	.type	_Z28__device_stub__Z7dividesllPillPi, @function
_Z28__device_stub__Z7dividesllPillPi:
.LFB2056:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z7dividesllPi(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L19:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L21
	call	__stack_chk_fail@PLT
.L21:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_Z28__device_stub__Z7dividesllPillPi, .-_Z28__device_stub__Z7dividesllPillPi
	.globl	_Z7dividesllPi
	.type	_Z7dividesllPi, @function
_Z7dividesllPi:
.LFB2057:
	.cfi_startproc
	endbr64
	jmp	_Z28__device_stub__Z7dividesllPillPi
	.cfi_endproc
.LFE2057:
	.size	_Z7dividesllPi, .-_Z7dividesllPi
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"/home/ubuntu/Datasets/stackv2/train-structured/ANU-HPC/accelerator-programming-course/master/day1_fundamentals/session4_programming/answers/listprimesV1eric.cu"
	.text
	.globl	_Z7isPrimel
	.type	_Z7isPrimel, @function
_Z7isPrimel:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$4, %esi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	movq	%rdi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	leaq	.LC1(%rip), %rbx
	subq	$48, %rsp
	.cfi_def_cfa_offset 80
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rdi
	movl	$1, 4(%rsp)
	leaq	4(%rsp), %r12
	call	cudaMalloc@PLT
	movl	$62, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z8gpucheck9cudaErrorPKci
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%r12, %rsi
	movl	$4, %edx
	call	cudaMemcpy@PLT
	movl	$64, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z8gpucheck9cudaErrorPKci
	movl	$4194305, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$134220853, %edi
	salq	$10, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	salq	$5, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L25
	movq	%rbp, %rdi
	call	_Z10intsqurootl
	movq	8(%rsp), %rdx
	movq	%rax, %rsi
	call	_Z28__device_stub__Z7dividesllPillPi
.L25:
	movq	8(%rsp), %rsi
	movl	$2, %ecx
	movl	$4, %edx
	movq	%r12, %rdi
	call	cudaMemcpy@PLT
	movl	$68, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z8gpucheck9cudaErrorPKci
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movl	$70, %edx
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z8gpucheck9cudaErrorPKci
	movl	4(%rsp), %eax
	movq	40(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L26
	call	__stack_chk_fail@PLT
.L26:
	addq	$48, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	_Z7isPrimel, .-_Z7isPrimel
	.section	.rodata.str1.1
.LC2:
	.string	"yes"
.LC3:
	.string	"no"
.LC4:
	.string	"%ld : %s\n"
	.text
	.globl	_Z10listPrimesll
	.type	_Z10listPrimesll, @function
_Z10listPrimesll:
.LFB2030:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	leaq	.LC3(%rip), %r12
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	movq	%rsi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	movq	%rdi, %rbx
.L29:
	cmpq	%rbp, %rbx
	jge	.L34
	movq	%rbx, %rdi
	call	_Z7isPrimel
	leaq	.LC2(%rip), %rcx
	movq	%rbx, %rdx
	leaq	.LC4(%rip), %rsi
	testl	%eax, %eax
	movl	$2, %edi
	cmove	%r12, %rcx
	xorl	%eax, %eax
	incq	%rbx
	call	__printf_chk@PLT
	jmp	.L29
.L34:
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2030:
	.size	_Z10listPrimesll, .-_Z10listPrimesll
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2031:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	movabsq	$9223372036854775807, %rsi
	movabsq	$9223372036854775707, %rdi
	call	_Z10listPrimesll
	xorl	%eax, %eax
	popq	%rdx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2031:
	.size	main, .-main
	.section	.rodata.str1.1
.LC5:
	.string	"_Z7dividesllPi"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2059:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z7dividesllPi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2059:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


// listPrimes - shows the prime numbers between a fixed range.
//      this is a CUDA version that uses 1 thread in 1 block just using 
//      a simple serial approach
// Eric McCreath 2019 - GPL 

// based on https://en.wikipedia.org/wiki/Integer_square_root
// assumes a positive number


#include<stdio.h>
#include<hip/hip_runtime.h>

// this macro checks for errors in cuda calls
#define Err(ans) { gpucheck((ans), __FILE__, __LINE__); }
inline void gpucheck(hipError_t code, const char *file, int line)
{
   if (code != hipSuccess) 
   {
      fprintf(stderr,"GPU Err: %s %s %d\n", hipGetErrorString(code), file, line);
      exit(code);
   }
}

// based on https://en.wikipedia.org/wiki/Integer_square_root
// assumes a positive number
long intsquroot(long n) {
	long shift = 2;
	long nShifted = n >> shift;

	while (nShifted != 0 && nShifted != n) {
		shift += 2;
		nShifted = n >> shift;
	}
	shift -= 2;
	long result = 0;
    while (shift >= 0) {
	    result = result << 1;
	    long candidateResult = result + 1;
	    if (candidateResult*candidateResult <= n >> shift) {
	        result = candidateResult;
	    }
	    shift = shift - 2;
	}
	return result;
}

__global__  void divides(long v, long sqrt, int *isprime) {
   long i;
   for (i = 2 + blockIdx.x * blockDim.x + threadIdx.x;
        (i <= sqrt) && (*isprime == 1);
         i +=  blockDim.x* gridDim.x) {
         if (v % i == 0) *isprime = 0;    
   }
}

int isPrime(long v) {

	long srt = intsquroot(v);
	int isprime = 1;
	int *isprime_d;
	Err(hipMalloc( &isprime_d, sizeof(int)));
	
	Err(hipMemcpy(isprime_d, &isprime, sizeof(int), hipMemcpyHostToDevice));

        divides<<<100000,1024>>>(v,srt,isprime_d);

	Err(hipMemcpy(&isprime,isprime_d,sizeof(int),hipMemcpyDeviceToHost));
	
	Err(hipFree(isprime_d));

	return isprime;
}

void listPrimes(long start, long end) {
	    for (long num = start; num < end ; num++) {
		    printf ("%ld : %s\n", num, (isPrime(num)? "yes" : "no"));
	    }
}

int main() {
    long largestlong = 0x7FFFFFFFFFFFFFFFL;
	listPrimes(largestlong-100L,largestlong);
    return 0;
}

	.text
	.file	"listprimesV1eric.hip"
	.globl	_Z10intsqurootl                 # -- Begin function _Z10intsqurootl
	.type	_Z10intsqurootl,@function
_Z10intsqurootl:                        # @_Z10intsqurootl
	.cfi_startproc
# %bb.0:
	movl	$2, %edx
	cmpq	$4, %rdi
	jb	.LBB0_4
# %bb.1:
	movq	%rdi, %rax
	sarq	$2, %rax
.LBB0_2:                                # =>This Inner Loop Header: Depth=1
	cmpq	%rdi, %rax
	je	.LBB0_4
# %bb.3:                                # %.lr.ph
                                        #   in Loop: Header=BB0_2 Depth=1
	addq	$2, %rdx
	movq	%rdi, %rax
	movl	%edx, %ecx
	sarq	%cl, %rax
	testq	%rax, %rax
	jne	.LBB0_2
.LBB0_4:                                # %.lr.ph26.preheader
	addq	$2, %rdx
	xorl	%eax, %eax
.LBB0_5:                                # %.lr.ph26
                                        # =>This Inner Loop Header: Depth=1
	leaq	1(,%rax,2), %rsi
	movq	%rsi, %r8
	imulq	%rsi, %r8
	leal	-4(%rdx), %ecx
	movq	%rdi, %r9
                                        # kill: def $cl killed $cl killed $ecx
	sarq	%cl, %r9
	cmpq	%r9, %r8
	jg	.LBB0_6
# %bb.7:                                # %.lr.ph26
                                        #   in Loop: Header=BB0_5 Depth=1
	movq	%rsi, %rax
	jmp	.LBB0_8
.LBB0_6:                                #   in Loop: Header=BB0_5 Depth=1
	addq	%rax, %rax
.LBB0_8:                                # %.lr.ph26
                                        #   in Loop: Header=BB0_5 Depth=1
	addq	$-2, %rdx
	cmpq	$3, %rdx
	ja	.LBB0_5
# %bb.9:                                # %._crit_edge
	retq
.Lfunc_end0:
	.size	_Z10intsqurootl, .Lfunc_end0-_Z10intsqurootl
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__dividesllPi  # -- Begin function _Z22__device_stub__dividesllPi
	.type	_Z22__device_stub__dividesllPi,@function
_Z22__device_stub__dividesllPi:         # @_Z22__device_stub__dividesllPi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7dividesllPi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z22__device_stub__dividesllPi, .Lfunc_end1-_Z22__device_stub__dividesllPi
	.cfi_endproc
                                        # -- End function
	.globl	_Z7isPrimel                     # -- Begin function _Z7isPrimel
	.type	_Z7isPrimel,@function
_Z7isPrimel:                            # @_Z7isPrimel
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$16, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %rbp, -16
	movq	%rdi, %rbx
	callq	_Z10intsqurootl
	movq	%rax, %r14
	movl	$1, 4(%rsp)
	leaq	8(%rsp), %rdi
	movl	$4, %esi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB2_1
# %bb.3:                                # %_Z8gpucheck10hipError_tPKci.exit
	movq	8(%rsp), %rdi
	leaq	4(%rsp), %rsi
	movl	$4, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB2_4
# %bb.5:                                # %_Z8gpucheck10hipError_tPKci.exit6
	movabsq	$4294968320, %rdx               # imm = 0x100000400
	leaq	98976(%rdx), %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_7
# %bb.6:
	movq	8(%rsp), %rdx
	movq	%rbx, %rdi
	movq	%r14, %rsi
	callq	_Z22__device_stub__dividesllPi
.LBB2_7:
	movq	8(%rsp), %rsi
	leaq	4(%rsp), %rdi
	movl	$4, %edx
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB2_8
# %bb.10:                               # %_Z8gpucheck10hipError_tPKci.exit8
	movq	8(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB2_11
# %bb.12:                               # %_Z8gpucheck10hipError_tPKci.exit10
	movl	4(%rsp), %eax
	addq	$16, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB2_1:
	.cfi_def_cfa_offset 48
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.4, %esi
	movl	$.L.str, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$62, %r8d
	jmp	.LBB2_2
.LBB2_4:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.4, %esi
	movl	$.L.str, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$64, %r8d
.LBB2_2:
	xorl	%eax, %eax
	callq	fprintf
	movl	%ebp, %edi
	callq	exit
.LBB2_8:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.4, %esi
	movl	$.L.str, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$68, %r8d
	jmp	.LBB2_9
.LBB2_11:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.4, %esi
	movl	$.L.str, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$70, %r8d
.LBB2_9:
	xorl	%eax, %eax
	callq	fprintf
	movl	%ebx, %edi
	callq	exit
.Lfunc_end2:
	.size	_Z7isPrimel, .Lfunc_end2-_Z7isPrimel
	.cfi_endproc
                                        # -- End function
	.globl	_Z10listPrimesll                # -- Begin function _Z10listPrimesll
	.type	_Z10listPrimesll,@function
_Z10listPrimesll:                       # @_Z10listPrimesll
	.cfi_startproc
# %bb.0:
	cmpq	%rsi, %rdi
	jge	.LBB3_4
# %bb.1:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rsi, %rbx
	movq	%rdi, %r14
	movl	$.L.str.3, %r15d
.LBB3_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movq	%r14, %rdi
	callq	_Z7isPrimel
	testl	%eax, %eax
	movl	$.L.str.2, %edx
	cmoveq	%r15, %rdx
	movl	$.L.str.1, %edi
	movq	%r14, %rsi
	xorl	%eax, %eax
	callq	printf
	incq	%r14
	cmpq	%r14, %rbx
	jne	.LBB3_2
# %bb.3:
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	.cfi_restore %r14
	.cfi_restore %r15
.LBB3_4:                                # %._crit_edge
	retq
.Lfunc_end3:
	.size	_Z10listPrimesll, .Lfunc_end3-_Z10listPrimesll
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rax
	.cfi_def_cfa_offset 16
	movabsq	$9223372036854775707, %rdi      # imm = 0x7FFFFFFFFFFFFF9B
	leaq	100(%rdi), %rsi
	callq	_Z10listPrimesll
	xorl	%eax, %eax
	popq	%rcx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	main, .Lfunc_end4-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7dividesllPi, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z7dividesllPi,@object          # @_Z7dividesllPi
	.section	.rodata,"a",@progbits
	.globl	_Z7dividesllPi
	.p2align	3, 0x0
_Z7dividesllPi:
	.quad	_Z22__device_stub__dividesllPi
	.size	_Z7dividesllPi, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"/home/ubuntu/Datasets/stackv2/train-structured-repos-hip-sm89/ANU-HPC/accelerator-programming-course/master/day1_fundamentals/session4_programming/answers/listprimesV1eric.hip"
	.size	.L.str, 176

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"%ld : %s\n"
	.size	.L.str.1, 10

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"yes"
	.size	.L.str.2, 4

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"no"
	.size	.L.str.3, 3

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"GPU Err: %s %s %d\n"
	.size	.L.str.4, 19

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z7dividesllPi"
	.size	.L__unnamed_1, 15

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z22__device_stub__dividesllPi
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z7dividesllPi
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z7dividesllPi          ; -- Begin function _Z7dividesllPi
	.globl	_Z7dividesllPi
	.p2align	8
	.type	_Z7dividesllPi,@function
_Z7dividesllPi:                         ; @_Z7dividesllPi
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b128 s[4:7], s[0:1], 0x0
	s_add_u32 s8, s0, 24
	s_addc_u32 s9, s1, 0
	v_mov_b32_e32 v1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s10, s2, 0xffff
	s_mov_b32 s2, exec_lo
	s_mul_i32 s15, s15, s10
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, v0, s15, 2
	v_cmpx_ge_i64_e64 s[6:7], v[0:1]
	s_cbranch_execz .LBB0_7
; %bb.1:                                ; %.lr.ph
	s_load_b64 s[2:3], s[0:1], 0x10
                                        ; implicit-def: $sgpr11
	s_waitcnt lgkmcnt(0)
	s_load_b32 s0, s[2:3], 0x0
	s_load_b32 s1, s[8:9], 0x0
	s_ashr_i32 s8, s5, 31
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_waitcnt lgkmcnt(0)
	v_mov_b32_e32 v4, s0
	s_mul_i32 s1, s1, s10
	s_mov_b32 s10, 0
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 1, v4
	s_or_b32 s11, s11, exec_lo
                                        ; implicit-def: $vgpr4
	s_and_saveexec_b32 s12, vcc_lo
	s_cbranch_execz .LBB0_6
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_ashrrev_i32_e32 v0, 31, v3
	s_add_u32 s14, s4, s8
	s_mov_b32 s9, s8
	s_addc_u32 s15, s5, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	s_xor_b64 s[14:15], s[14:15], s[8:9]
	v_add_co_u32 v4, vcc_lo, v2, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, v3, v0, vcc_lo
	v_xor_b32_e32 v11, v4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v0, v5, v0
	v_cvt_f32_u32_e32 v4, v11
	v_sub_co_u32 v12, vcc_lo, 0, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_f32_u32_e32 v5, v0
	v_sub_co_ci_u32_e32 v13, vcc_lo, 0, v0, vcc_lo
	v_fmac_f32_e32 v4, 0x4f800000, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v4, v4
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v4, 0x5f7ffffc, v4
	v_mul_f32_e32 v5, 0x2f800000, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_trunc_f32_e32 v5, v5
	v_fmac_f32_e32 v4, 0xcf800000, v5
	v_cvt_u32_f32_e32 v14, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v15, v4
	v_mul_lo_u32 v6, v12, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v7, v13, v15
	v_mad_u64_u32 v[4:5], null, v12, v15, 0
	v_add3_u32 v16, v5, v6, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v17, v15, v4
	v_mad_u64_u32 v[7:8], null, v14, v4, 0
	v_mad_u64_u32 v[5:6], null, v15, v16, 0
	v_mad_u64_u32 v[9:10], null, v14, v16, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, v17, v5
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v4, v7
	v_add_co_ci_u32_e32 v4, vcc_lo, v5, v8, vcc_lo
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v4, v9
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v15, vcc_lo, v15, v4
	v_add_co_ci_u32_e32 v14, vcc_lo, v14, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v6, v13, v15
	v_mad_u64_u32 v[4:5], null, v12, v15, 0
	v_mul_lo_u32 v7, v12, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v13, v15, v4
	v_add3_u32 v12, v5, v7, v6
	v_mad_u64_u32 v[7:8], null, v14, v4, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[5:6], null, v15, v12, 0
	v_mad_u64_u32 v[9:10], null, v14, v12, 0
	v_add_co_u32 v4, vcc_lo, v13, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v6, vcc_lo
	v_add_co_u32 v4, vcc_lo, v4, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v5, v8, vcc_lo
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v10, vcc_lo
	v_add_co_u32 v4, vcc_lo, v4, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	v_add_co_u32 v8, vcc_lo, v15, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, v14, v5, vcc_lo
	v_mul_hi_u32 v12, s14, v8
	v_mad_u64_u32 v[6:7], null, s15, v8, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[4:5], null, s14, v10, 0
	v_mad_u64_u32 v[8:9], null, s15, v10, 0
	v_add_co_u32 v4, vcc_lo, v12, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	v_add_co_u32 v4, vcc_lo, v4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v5, v7, vcc_lo
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v9, vcc_lo
	v_add_co_u32 v6, vcc_lo, v4, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v5, vcc_lo
	v_mul_lo_u32 v8, v0, v6
	v_mad_u64_u32 v[4:5], null, v11, v6, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v6, v11, v7
	v_sub_co_u32 v4, vcc_lo, s14, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v5, v5, v6, v8
	v_sub_nc_u32_e32 v6, s15, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sub_co_ci_u32_e64 v6, s0, v6, v0, vcc_lo
	v_sub_co_ci_u32_e32 v5, vcc_lo, s15, v5, vcc_lo
	v_sub_co_u32 v7, vcc_lo, v4, v11
	v_subrev_co_ci_u32_e64 v8, s0, 0, v6, vcc_lo
	v_cmp_ge_u32_e64 s0, v4, v11
	v_sub_co_ci_u32_e32 v6, vcc_lo, v6, v0, vcc_lo
	v_cmp_ge_u32_e32 vcc_lo, v5, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v9, 0, -1, s0
	v_cmp_ge_u32_e64 s0, v7, v11
	v_cndmask_b32_e64 v13, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, v8, v0
	v_cndmask_b32_e64 v10, 0, -1, s0
	v_cmp_ge_u32_e64 s0, v8, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v12, 0, -1, s0
	v_cmp_eq_u32_e64 s0, v5, v0
	v_cndmask_b32_e32 v10, v12, v10, vcc_lo
	v_sub_co_u32 v11, vcc_lo, v7, v11
	v_subrev_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_ne_u32_e32 vcc_lo, 0, v10
	v_cndmask_b32_e64 v0, v13, v9, s0
	v_dual_cndmask_b32 v6, v8, v6 :: v_dual_cndmask_b32 v7, v7, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ne_u32_e32 vcc_lo, 0, v0
	v_cndmask_b32_e32 v4, v4, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v0, v5, v6, vcc_lo
	v_xor_b32_e32 v4, s8, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v0, s8, v0
	v_sub_co_u32 v4, vcc_lo, v4, s8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_subrev_co_ci_u32_e32 v5, vcc_lo, s8, v0, vcc_lo
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	v_mov_b32_e32 v4, 1
	s_and_saveexec_b32 s0, vcc_lo
	s_cbranch_execz .LBB0_5
; %bb.4:                                ;   in Loop: Header=BB0_2 Depth=1
	v_mov_b32_e32 v4, 0
	global_store_b32 v1, v1, s[2:3]
.LBB0_5:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_add_co_u32 v2, vcc_lo, v2, s1
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_and_not1_b32 s0, s11, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_lt_i64_e32 vcc_lo, s[6:7], v[2:3]
	s_and_b32 s9, vcc_lo, exec_lo
	s_or_b32 s11, s0, s9
.LBB0_6:                                ; %Flow
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, exec_lo, s11
	s_or_b32 s10, s0, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_2
.LBB0_7:                                ; %.critedge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7dividesllPi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 18
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z7dividesllPi, .Lfunc_end0-_Z7dividesllPi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1020
; NumSgprs: 18
; NumVgprs: 18
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 18
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .offset:         8
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7dividesllPi
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z7dividesllPi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     18
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
