#include <stdio.h>

__global__ void vecSine(float *A, float *B){
	int id = blockIdx.x;
	B[id] = sin(A[id]);
}


int main(){
	float A[100],B[100];
	int n,i,size;

	printf("Enter value for n: ");
	scanf("%d",&n);

	printf("Enter the values for vector A in radians :\n");
	for(i=0;i<n;i++)
		scanf("%f",&A[i]);


	float *da,*db;
	size = sizeof(float)*n;

	cudaMalloc((void **)&da,size);
	cudaMalloc((void**)&db,size);

	cudaMemcpy(da,A,size,cudaMemcpyHostToDevice);


	printf("Result: ");
	vecSine<<<n,1>>>(da,db);

	cudaMemcpy(B,db,size,cudaMemcpyDeviceToHost);

	for(i=0;i<n;i++)
		printf("%f ",B[i]);


	cudaFree(da);
	cudaFree(db);
	return 0;
}

	.file	"tmpxft_0035c947_00000000-6_q4.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z28__device_stub__Z7vecSinePfS_PfS_
	.type	_Z28__device_stub__Z7vecSinePfS_PfS_, @function
_Z28__device_stub__Z7vecSinePfS_PfS_:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z7vecSinePfS_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L2:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z28__device_stub__Z7vecSinePfS_PfS_, .-_Z28__device_stub__Z7vecSinePfS_PfS_
	.globl	_Z7vecSinePfS_
	.type	_Z7vecSinePfS_, @function
_Z7vecSinePfS_:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z28__device_stub__Z7vecSinePfS_PfS_
	.cfi_endproc
.LFE2053:
	.size	_Z7vecSinePfS_, .-_Z7vecSinePfS_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Enter value for n: "
.LC1:
	.string	"%d"
.LC2:
	.string	"Enter the values for vector A in radians :\n"
.LC3:
	.string	"%f"
.LC4:
	.string	"Result: "
.LC5:
	.string	"%f "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	leaq	.LC0(%rip), %rsi
	movl	$2, %edi
	leaq	.LC3(%rip), %r14
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	xorl	%r12d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	subq	$864, %rsp
	.cfi_def_cfa_offset 912
	movq	%fs:40, %rax
	movq	%rax, 856(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rbp
	movq	%rbp, %r13
	call	__printf_chk@PLT
	leaq	12(%rsp), %rsi
	leaq	.LC1(%rip), %rdi
	xorl	%eax, %eax
	call	__isoc23_scanf@PLT
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L9:
	movl	12(%rsp), %ebx
	cmpl	%r12d, %ebx
	jle	.L16
	movq	%rbp, %rsi
	movq	%r14, %rdi
	xorl	%eax, %eax
	incl	%r12d
	call	__isoc23_scanf@PLT
	addq	$4, %rbp
	jmp	.L9
.L16:
	sall	$2, %ebx
	leaq	16(%rsp), %rdi
	movslq	%ebx, %rbx
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r13, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	12(%rsp), %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rdx
	movl	$1, %ecx
	movl	$1, 52(%rsp)
	movq	%rdx, 36(%rsp)
	movl	40(%rsp), %esi
	movl	%eax, 32(%rsp)
	movq	32(%rsp), %rdi
	movq	%rdx, 44(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L11
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdi
	call	_Z28__device_stub__Z7vecSinePfS_PfS_
.L11:
	movq	24(%rsp), %rsi
	leaq	456(%rsp), %rbp
	movq	%rbx, %rdx
	movl	$2, %ecx
	movq	%rbp, %rdi
	xorl	%ebx, %ebx
	leaq	.LC5(%rip), %r12
	call	cudaMemcpy@PLT
.L12:
	cmpl	%ebx, 12(%rsp)
	jle	.L17
	movq	%r12, %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	0(%rbp,%rbx,4), %xmm0
	call	__printf_chk@PLT
	incq	%rbx
	jmp	.L12
.L17:
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	856(%rsp), %rax
	subq	%fs:40, %rax
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$864, %rsp
	.cfi_def_cfa_offset 48
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC6:
	.string	"_Z7vecSinePfS_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z7vecSinePfS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>

__global__ void vecSine(float *A, float *B){
	int id = blockIdx.x;
	B[id] = sin(A[id]);
}


int main(){
	float A[100],B[100];
	int n,i,size;

	printf("Enter value for n: ");
	scanf("%d",&n);

	printf("Enter the values for vector A in radians :\n");
	for(i=0;i<n;i++)
		scanf("%f",&A[i]);


	float *da,*db;
	size = sizeof(float)*n;

	hipMalloc((void **)&da,size);
	hipMalloc((void**)&db,size);

	hipMemcpy(da,A,size,hipMemcpyHostToDevice);


	printf("Result: ");
	vecSine<<<n,1>>>(da,db);

	hipMemcpy(B,db,size,hipMemcpyDeviceToHost);

	for(i=0;i<n;i++)
		printf("%f ",B[i]);


	hipFree(da);
	hipFree(db);
	return 0;
}

	.text
	.file	"q4.hip"
	.globl	_Z22__device_stub__vecSinePfS_  # -- Begin function _Z22__device_stub__vecSinePfS_
	.type	_Z22__device_stub__vecSinePfS_,@function
_Z22__device_stub__vecSinePfS_:         # @_Z22__device_stub__vecSinePfS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7vecSinePfS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z22__device_stub__vecSinePfS_, .Lfunc_end0-_Z22__device_stub__vecSinePfS_
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	subq	$840, %rsp                      # imm = 0x348
	.cfi_def_cfa_offset 864
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movl	$.L.str, %edi
	xorl	%eax, %eax
	callq	printf
	leaq	12(%rsp), %rbx
	movl	$.L.str.1, %edi
	movq	%rbx, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	movl	$.Lstr, %edi
	callq	puts@PLT
	movl	(%rbx), %eax
	testl	%eax, %eax
	jle	.LBB1_3
# %bb.1:                                # %.lr.ph.preheader
	leaq	432(%rsp), %rbx
	xorl	%r14d, %r14d
.LBB1_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	$.L.str.3, %edi
	movq	%rbx, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	incq	%r14
	movslq	12(%rsp), %rax
	addq	$4, %rbx
	cmpq	%rax, %r14
	jl	.LBB1_2
.LBB1_3:                                # %._crit_edge
	shll	$2, %eax
	movslq	%eax, %rbx
	leaq	24(%rsp), %r14
	movq	%r14, %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	movq	(%r14), %rdi
	leaq	432(%rsp), %rsi
	movq	%rbx, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$.L.str.4, %edi
	xorl	%eax, %eax
	callq	printf
	movl	12(%rsp), %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$1, %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_5
# %bb.4:
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	callq	_Z22__device_stub__vecSinePfS_
.LBB1_5:
	movq	16(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%rbx, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	cmpl	$0, 12(%rsp)
	jle	.LBB1_8
# %bb.6:                                # %.lr.ph18.preheader
	xorl	%ebx, %ebx
.LBB1_7:                                # %.lr.ph18
                                        # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtss2sd	32(%rsp,%rbx,4), %xmm0
	movl	$.L.str.5, %edi
	movb	$1, %al
	callq	printf
	incq	%rbx
	movslq	12(%rsp), %rax
	cmpq	%rax, %rbx
	jl	.LBB1_7
.LBB1_8:                                # %._crit_edge19
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$840, %rsp                      # imm = 0x348
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7vecSinePfS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z7vecSinePfS_,@object          # @_Z7vecSinePfS_
	.section	.rodata,"a",@progbits
	.globl	_Z7vecSinePfS_
	.p2align	3, 0x0
_Z7vecSinePfS_:
	.quad	_Z22__device_stub__vecSinePfS_
	.size	_Z7vecSinePfS_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Enter value for n: "
	.size	.L.str, 20

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"%d"
	.size	.L.str.1, 3

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"%f"
	.size	.L.str.3, 3

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"Result: "
	.size	.L.str.4, 9

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"%f "
	.size	.L.str.5, 4

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z7vecSinePfS_"
	.size	.L__unnamed_1, 15

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Enter the values for vector A in radians :"
	.size	.Lstr, 43

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z22__device_stub__vecSinePfS_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z7vecSinePfS_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z7vecSinePfS_          ; -- Begin function _Z7vecSinePfS_
	.globl	_Z7vecSinePfS_
	.p2align	8
	.type	_Z7vecSinePfS_,@function
_Z7vecSinePfS_:                         ; @_Z7vecSinePfS_
; %bb.0:
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_ashr_i32 s5, s15, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[4:5], s[4:5], 2
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s0, s4
	s_addc_u32 s1, s1, s5
	s_load_b32 s0, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	v_cmp_ngt_f32_e64 s1, 0x48000000, |s0|
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s1
	s_and_b32 s1, s0, 0x7fffffff
	s_cbranch_vccz .LBB0_2
; %bb.1:
	s_and_b32 s6, s1, 0x7fffff
	s_lshr_b32 s7, s1, 23
	s_bitset1_b32 s6, 23
	s_addk_i32 s7, 0xff88
	s_mul_hi_u32 s8, s6, 0xfe5163ab
	s_mul_i32 s9, s6, 0x3c439041
	s_mul_hi_u32 s10, s6, 0x3c439041
	s_add_u32 s8, s8, s9
	s_addc_u32 s9, 0, s10
	s_mul_i32 s10, s6, 0xdb629599
	s_mul_hi_u32 s11, s6, 0xdb629599
	s_add_u32 s9, s9, s10
	s_addc_u32 s10, 0, s11
	s_mul_i32 s11, s6, 0xf534ddc0
	s_mul_hi_u32 s12, s6, 0xf534ddc0
	s_add_u32 s10, s10, s11
	s_addc_u32 s11, 0, s12
	s_mul_i32 s12, s6, 0xfc2757d1
	s_mul_hi_u32 s13, s6, 0xfc2757d1
	s_add_u32 s11, s11, s12
	s_addc_u32 s12, 0, s13
	s_mul_i32 s13, s6, 0x4e441529
	s_mul_hi_u32 s14, s6, 0x4e441529
	s_add_u32 s12, s12, s13
	s_addc_u32 s13, 0, s14
	s_cmp_gt_u32 s7, 63
	s_mul_i32 s14, s6, 0xfe5163ab
	s_mul_hi_u32 s15, s6, 0xa2f9836e
	s_mul_i32 s6, s6, 0xa2f9836e
	s_cselect_b32 s16, s9, s11
	s_cselect_b32 s8, s8, s10
	s_cselect_b32 s9, s14, s9
	s_add_u32 s6, s13, s6
	s_addc_u32 s13, 0, s15
	s_cmp_gt_u32 s7, 63
	s_cselect_b32 s14, 0xffffffc0, 0
	s_cselect_b32 s10, s10, s12
	s_cselect_b32 s6, s11, s6
	s_cselect_b32 s11, s12, s13
	s_add_i32 s14, s14, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s14, 31
	s_cselect_b32 s7, 0xffffffe0, 0
	s_cselect_b32 s12, s10, s6
	s_cselect_b32 s6, s6, s11
	s_cselect_b32 s10, s16, s10
	s_cselect_b32 s11, s8, s16
	s_cselect_b32 s8, s9, s8
	s_add_i32 s7, s7, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s7, 31
	s_cselect_b32 s9, 0xffffffe0, 0
	s_cselect_b32 s6, s12, s6
	s_cselect_b32 s12, s10, s12
	s_cselect_b32 s10, s11, s10
	s_cselect_b32 s8, s8, s11
	s_add_i32 s9, s9, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_sub_i32 s7, 32, s9
	s_cmp_eq_u32 s9, 0
	v_mov_b32_e32 v0, s7
	s_cselect_b32 s9, -1, 0
	v_alignbit_b32 v1, s6, s12, v0
	v_alignbit_b32 v2, s12, s10, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s7, v1
	v_cndmask_b32_e64 v1, v2, s12, s9
	s_delay_alu instid0(VALU_DEP_2)
	s_cselect_b32 s6, s6, s7
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v2, s6, v1, 30
	s_bfe_u32 s11, s6, 0x1001d
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s7, 0, s11
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_xor_b32_e32 v2, s7, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v3, v2
	v_min_u32_e32 v3, 32, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v5, 23, v3
	v_alignbit_b32 v0, s10, s8, v0
	v_sub_nc_u32_e32 v4, 31, v3
	v_cndmask_b32_e64 v0, v0, s10, s9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v1, v1, v0, 30
	v_alignbit_b32 v0, v0, s8, 30
	v_xor_b32_e32 v1, s7, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_xor_b32_e32 v0, s7, v0
	s_lshr_b32 s7, s6, 29
	s_lshr_b32 s6, s6, 30
	s_lshl_b32 s7, s7, 31
	v_alignbit_b32 v2, v2, v1, v4
	v_alignbit_b32 v0, v1, v0, v4
	s_or_b32 s8, s7, 0.5
	s_add_i32 s6, s11, s6
	v_sub_nc_u32_e32 v5, s8, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v1, v2, v0, 9
	v_clz_i32_u32_e32 v4, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v4, 32, v4
	v_sub_nc_u32_e32 v6, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v0, v1, v0, v6
	v_lshrrev_b32_e32 v1, 9, v2
	v_lshrrev_b32_e32 v0, 9, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_or_b32_e32 v1, v1, v5
	v_add_nc_u32_e32 v3, v4, v3
	v_lshlrev_b32_e32 v2, 23, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v0, v0, v2
	v_mul_f32_e32 v2, 0x3fc90fda, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v0, 0x33000000, v0
	v_fma_f32 v3, 0x3fc90fda, v1, -v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v0, s7, v0
	v_fmamk_f32 v1, v1, 0x33a22168, v3
	s_mov_b32 s7, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v1, 0x3fc90fda, v0
	v_add_f32_e32 v0, v2, v1
	s_branch .LBB0_3
.LBB0_2:
	s_mov_b32 s7, -1
                                        ; implicit-def: $sgpr6
                                        ; implicit-def: $vgpr0
.LBB0_3:                                ; %Flow
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s7
	s_cbranch_vccnz .LBB0_5
; %bb.4:
	v_mul_f32_e64 v0, 0x3f22f983, |s0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v1, v0
	v_fma_f32 v0, 0xbfc90fda, v1, |s0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v0, v1, 0xb3a22168, v0
	v_fmamk_f32 v0, v1, 0xa7c234c4, v0
	v_cvt_i32_f32_e32 v1, v1
	s_branch .LBB0_6
.LBB0_5:
	v_mov_b32_e32 v1, s6
.LBB0_6:                                ; %_ZL3sinf.exit
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v2, v0, v0 :: v_dual_lshlrev_b32 v5, 30, v1
	s_mov_b32 s6, 0xb94c1982
	s_mov_b32 s7, 0x37d75334
	s_xor_b32 s1, s1, s0
	v_fmaak_f32 v3, s6, v2, 0x3c0881c4
	v_and_b32_e32 v1, 1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmaak_f32 v3, v2, v3, 0xbe2aaa9d
	v_fmaak_f32 v4, s7, v2, 0xbab64f3b
	v_cmp_eq_u32_e32 vcc_lo, 0, v1
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v3, v2, v3
	v_fmaak_f32 v4, v2, v4, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v0, v0, v3 :: v_dual_and_b32 v5, 0x80000000, v5
	v_fmaak_f32 v4, v2, v4, 0xbf000004
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v3, s1, v5
	v_fma_f32 v2, v2, v4, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v0, v2, v0, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, s0, 0x1f8
	s_add_u32 s0, s2, s4
	s_addc_u32 s1, s3, s5
	v_xor_b32_e32 v0, v3, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e32 v0, 0x7fc00000, v0, vcc_lo
	global_store_b32 v1, v0, s[0:1]
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7vecSinePfS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 16
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 17
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z7vecSinePfS_, .Lfunc_end0-_Z7vecSinePfS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1004
; NumSgprs: 19
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 19
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 16
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7vecSinePfS_
    .private_segment_fixed_size: 0
    .sgpr_count:     19
    .sgpr_spill_count: 0
    .symbol:         _Z7vecSinePfS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     7
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
