//http://stackoverflow.com/questions/22217628/integral-image-or-summed-area-table-of-2d-matrix-using-cuda-c
#include <iostream>
#include <cuda_runtime.h>
#include <stdlib.h> 
#include <stdio.h>
#define BLOCK_DIM_X 16
#define BLOCK_DIM_Y 16
using namespace std;

__global__ void sat(int *a, int*b, int rowsTotal,int colsTotal,int start)
{
    // Thread Ids equal to block Ids because the each blocks contains one thread only.
    int col;
    int row;
    if (start<=rowsTotal/blockDim.y-1)
    {
        row = (colsTotal/blockDim.x-1-blockIdx.x)*blockDim.y+threadIdx.y-blockDim.y*(colsTotal/blockDim.x-1-start);
        col = blockIdx.x*blockDim.x+threadIdx.x;
    }
    else
    {
        row = (colsTotal/blockDim.x-1-blockIdx.x)*blockDim.y+threadIdx.y;
        col = (start-(colsTotal/blockDim.x-1))*blockDim.x+blockIdx.x*blockDim.x+threadIdx.x;
    }
    if (row>=rowsTotal || row <0) return;
    if (col>=colsTotal || col <0) return;

    int idx = threadIdx.y*blockDim.x+threadIdx.x; // id in block 
    int didx = row*colsTotal+col;  // compute data id
    __shared__ int s[BLOCK_DIM_X*BLOCK_DIM_Y];
    
    s[idx]=0;
    __syncthreads();

    //printf("run kernel\n");      
    
    while (s[BLOCK_DIM_X*BLOCK_DIM_Y-1]==0){
    if (s[idx]==0){
    if (threadIdx.x>0 && threadIdx.y==0)
    {
        if (s[idx-1])
        {
           if (row>0 )
              b[didx]=b[didx-colsTotal]+a[didx]+b[didx-1]-b[didx-colsTotal-1];
           else 
              b[didx]=a[didx]+b[didx-1];
           s[idx]=1;
        }
            
    }

    if (threadIdx.y>0 && threadIdx.x==0)
    {
        if (s[idx-blockDim.x])
        {
           if (col>0 )
              b[didx]=b[didx-colsTotal]+a[didx]+b[didx-1]-b[didx-colsTotal-1];
           else
              b[didx]=a[didx]+b[didx-colsTotal];
           s[idx]=1;
        }

    }
   
    if (threadIdx.y>0 && threadIdx.x>0)
    {
        if (s[idx-blockDim.x] && s[idx-1])
        {
           b[didx]=b[didx-colsTotal]+a[didx]+b[didx-1]-b[didx-colsTotal-1];
           s[idx]=1;
        }

    }
     if (threadIdx.x==0 && threadIdx.y==0)
     {   
          if (row>0 && col>0)
              b[didx]=b[didx-colsTotal]+a[didx]+b[didx-1]-b[didx-colsTotal-1];
          if (row==0 && col>0)
              b[didx]=a[didx]+b[didx-1];    
          if (row>0 && col==0)
             b[didx]=b[didx-colsTotal]+a[didx];
          if (row==0 && col==0)
              b[didx]=a[didx];
          s[idx]=1; 
     }

    }
    __syncthreads();
    }
}

void cpu_sat(int* a, int* b, int M, int N){

    for(int r=0;r<M;r++)
    {
        for(int c=0; c<N;c++)
        {
            if(r==0) 
            {
              if (c>0)
                  b[r*N+c]=b[r*N+c-1]+a[r*N+c];
              else
                  b[r*N+c]=a[r*N+c];
            }
            else{
              if (c>0)
                  b[r*N+c]=b[r*N+c-1]+a[r*N+c]+b[(r-1)*N+c]-b[(r-1)*N+c-1];
              else
                  b[r*N+c]=a[r*N+c]+b[(r-1)*N+c];
            }
        }
    }

}
int main()
{
    //M is number of rows
    //N is number of columns
    //M,N have to be multiples of BLOCK_DIM_X and BLOCK_DIM_Y
    int M=64,N=64;
    int total_e=M*N;
    int widthstep=total_e*sizeof(int);

    int * matrix_a= (int *)malloc(widthstep);
    int * matrix_b= (int *)malloc(widthstep);
    int * cpu_result = (int *)malloc(widthstep);
    //cout<<"Enter elements for "<< M<<"x"<<N<<" matrix";

    for(int r=0;r<M;r++)
    {
        for(int c=0; c<N;c++)
        {
            //cout<<"Enter Matrix element [ "<<r<<","<<c<<"]";
            matrix_a[r*N+c]=rand()%100;
            matrix_b[r*N+c]=0;
        }
 
    }
    cpu_sat(matrix_a,cpu_result,M,N);
    int * d_matrix_a, * d_matrix_b;

    //cout<<"start copy"<<endl;
    /*
    for(int r=0;r<M;r++)
    {
        for(int c=0; c<N;c++)
        {
            cout << matrix_a[r*N+c]<<" ";
        }
        cout << endl;
    }

    cout<<endl;
    */
    cudaMalloc(&d_matrix_a,widthstep);
    cudaMalloc(&d_matrix_b,widthstep);

    cudaMemcpy(d_matrix_a,matrix_a,widthstep,cudaMemcpyHostToDevice);
    cudaMemcpy(d_matrix_b,matrix_b,widthstep,cudaMemcpyHostToDevice);

    //Creating a grid where the number of blocks are equal to the number of pixels or input matrix elements.

    //Each block contains only one thread.

    dim3 grid(N/BLOCK_DIM_X);  // grid is one dimensional!!
    dim3 blockdim(BLOCK_DIM_X,BLOCK_DIM_Y);
    for (int i=0;i<M/BLOCK_DIM_Y+N/BLOCK_DIM_X-1;i++){
        sat<<<grid,blockdim>>>(d_matrix_a, d_matrix_b,M,N,i);
        //cudaThreadSynchronize();
    }

    cudaThreadSynchronize();
    cudaMemcpy(matrix_b,d_matrix_b,widthstep,cudaMemcpyDeviceToHost);
    cout<<"Compare with CPU result: "<<endl;
    int count=0; 
    for(int r=0;r<M;r++)
    {
        for(int c=0; c<N;c++)
        {
            if(cpu_result[r*N+c]!=matrix_b[r*N+c])
            {   
                count+=1;//cout << matrix_b[r*N+c]<<" "<<;
            //    if(r==0)
                cout<<r<<" "<<c<<" cpu:"<<cpu_result[r*N+c]<<" gpu:"<<matrix_b[r*N+c]<<endl;
            }
        }
        //cout << endl;
    }
    cout<<"mismatch: "<<count<<endl;
    //system("pause");

    cudaFree(d_matrix_a);
    cudaFree(d_matrix_b);
    free(matrix_a);
    free(matrix_b);
    return 0;
}

	.file	"tmpxft_0024bbf4_00000000-6_sat_rk.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3639:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3639:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z7cpu_satPiS_ii
	.type	_Z7cpu_satPiS_ii, @function
_Z7cpu_satPiS_ii:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movl	%ecx, %r10d
	movq	%rsi, %rax
	movl	%ecx, %r8d
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	negl	%r10d
	xorl	%r11d, %r11d
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movl	%edx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
.L3:
	cmpl	%ebp, %r11d
	jge	.L2
	leal	(%r10,%r8), %ebx
	movslq	%r10d, %rdx
	movslq	%ebx, %rsi
	leaq	(%rax,%rdx,4), %r12
	xorl	%edx, %edx
	salq	$2, %rsi
	leaq	(%rdi,%rsi), %r13
	addq	%rax, %rsi
.L10:
	cmpl	%edx, %r8d
	jle	.L13
	testl	%r11d, %r11d
	jne	.L4
	testq	%rdx, %rdx
	je	.L5
	movl	(%rdi,%rdx,4), %ecx
	addl	-4(%rax,%rdx,4), %ecx
	movl	%ecx, (%rax,%rdx,4)
	jmp	.L6
.L5:
	movl	(%rdi), %ecx
	movl	%ecx, (%rax)
	jmp	.L6
.L4:
	testq	%rdx, %rdx
	je	.L7
	leal	(%rbx,%rdx), %r9d
	leal	(%r10,%rdx), %r14d
	movslq	%r9d, %r9
	movslq	%r14d, %r14
	movl	(%rdi,%r9,4), %ecx
	addl	-4(%rax,%r9,4), %ecx
	addl	(%rax,%r14,4), %ecx
	subl	-4(%rax,%r14,4), %ecx
	movl	%ecx, (%rax,%r9,4)
	jmp	.L6
.L7:
	movl	(%r12), %ecx
	addl	0(%r13), %ecx
	movl	%ecx, (%rsi)
.L6:
	incq	%rdx
	jmp	.L10
.L13:
	incl	%r11d
	movl	%ebx, %r10d
	jmp	.L3
.L2:
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	_Z7cpu_satPiS_ii, .-_Z7cpu_satPiS_ii
	.globl	_Z27__device_stub__Z3satPiS_iiiPiS_iii
	.type	_Z27__device_stub__Z3satPiS_iiiPiS_iii, @function
_Z27__device_stub__Z3satPiS_iiiPiS_iii:
.LFB3661:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 8(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z3satPiS_iii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L14:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L16
	call	__stack_chk_fail@PLT
.L16:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3661:
	.size	_Z27__device_stub__Z3satPiS_iiiPiS_iii, .-_Z27__device_stub__Z3satPiS_iiiPiS_iii
	.globl	_Z3satPiS_iii
	.type	_Z3satPiS_iii, @function
_Z3satPiS_iii:
.LFB3662:
	.cfi_startproc
	endbr64
	jmp	_Z27__device_stub__Z3satPiS_iiiPiS_iii
	.cfi_endproc
.LFE3662:
	.size	_Z3satPiS_iii, .-_Z3satPiS_iii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Compare with CPU result: "
.LC1:
	.string	" "
.LC2:
	.string	" cpu:"
.LC3:
	.string	" gpu:"
.LC4:
	.string	"mismatch: "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3636:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$16384, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	xorl	%r12d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$16384, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	movl	$16384, %edi
	movq	%rax, %rbx
	call	malloc@PLT
	movq	%rax, %r13
.L20:
	xorl	%r14d, %r14d
	leaq	0(%rbp,%r12), %r15
.L21:
	call	rand@PLT
	movl	$100, %ecx
	cltd
	idivl	%ecx
	leaq	(%rbx,%r12), %rax
	movl	%edx, (%r15,%r14)
	xorl	%edx, %edx
	movl	%edx, (%rax,%r14)
	addq	$4, %r14
	cmpq	$256, %r14
	jne	.L21
	addq	$256, %r12
	cmpq	$16384, %r12
	jne	.L20
	movl	$64, %ecx
	movl	$64, %edx
	movq	%r13, %rsi
	movq	%rbp, %rdi
	call	_Z7cpu_satPiS_ii
	leaq	16(%rsp), %rdi
	movl	$16384, %esi
	xorl	%r12d, %r12d
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$16384, %esi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$16384, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$16384, %edx
	call	cudaMemcpy@PLT
	movl	$1073741825, %eax
	movl	$1, 40(%rsp)
	salq	$2, %rax
	movl	$1, 52(%rsp)
	movq	%rax, 32(%rsp)
	movabsq	$68719476752, %rax
	movq	%rax, 44(%rsp)
.L24:
	movl	52(%rsp), %ecx
	movq	44(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	32(%rsp), %rdi
	movl	40(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdi
	movl	%r12d, %r8d
	movl	$64, %ecx
	movl	$64, %edx
	call	_Z27__device_stub__Z3satPiS_iiiPiS_iii
.L23:
	incl	%r12d
	cmpl	$7, %r12d
	jne	.L24
	call	cudaThreadSynchronize@PLT
	movq	24(%rsp), %rsi
	movq	%rbx, %rdi
	xorl	%r14d, %r14d
	movl	$2, %ecx
	movl	$16384, %edx
	call	cudaMemcpy@PLT
	leaq	.LC0(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	xorl	%ecx, %ecx
.L25:
	movl	%ecx, 8(%rsp)
	movq	%rcx, %r15
	xorl	%r12d, %r12d
	salq	$8, %r15
.L27:
	movl	0(%r13,%r15), %r8d
	cmpl	(%rbx,%r15), %r8d
	movl	%r8d, 12(%rsp)
	je	.L26
	movl	8(%rsp), %esi
	leaq	_ZSt4cout(%rip), %rdi
	movq	%rcx, (%rsp)
	incl	%r14d
	call	_ZNSolsEi@PLT
	leaq	.LC1(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%r12d, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC2(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	12(%rsp), %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC3(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	(%rbx,%r15), %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	(%rsp), %rcx
.L26:
	incl	%r12d
	addq	$4, %r15
	cmpl	$64, %r12d
	jne	.L27
	incq	%rcx
	cmpq	$64, %rcx
	jne	.L25
	leaq	.LC4(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%r14d, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	%rbp, %rdi
	call	free@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L29
	call	__stack_chk_fail@PLT
.L29:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3636:
	.size	main, .-main
	.section	.rodata.str1.1
.LC5:
	.string	"_Z3satPiS_iii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3664:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z3satPiS_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3664:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

//http://stackoverflow.com/questions/22217628/integral-image-or-summed-area-table-of-2d-matrix-using-cuda-c
#include <iostream>
#include <hip/hip_runtime.h>
#include <stdlib.h> 
#include <stdio.h>
#define BLOCK_DIM_X 16
#define BLOCK_DIM_Y 16
using namespace std;

__global__ void sat(int *a, int*b, int rowsTotal,int colsTotal,int start)
{
    // Thread Ids equal to block Ids because the each blocks contains one thread only.
    int col;
    int row;
    if (start<=rowsTotal/blockDim.y-1)
    {
        row = (colsTotal/blockDim.x-1-blockIdx.x)*blockDim.y+threadIdx.y-blockDim.y*(colsTotal/blockDim.x-1-start);
        col = blockIdx.x*blockDim.x+threadIdx.x;
    }
    else
    {
        row = (colsTotal/blockDim.x-1-blockIdx.x)*blockDim.y+threadIdx.y;
        col = (start-(colsTotal/blockDim.x-1))*blockDim.x+blockIdx.x*blockDim.x+threadIdx.x;
    }
    if (row>=rowsTotal || row <0) return;
    if (col>=colsTotal || col <0) return;

    int idx = threadIdx.y*blockDim.x+threadIdx.x; // id in block 
    int didx = row*colsTotal+col;  // compute data id
    __shared__ int s[BLOCK_DIM_X*BLOCK_DIM_Y];
    
    s[idx]=0;
    __syncthreads();

    //printf("run kernel\n");      
    
    while (s[BLOCK_DIM_X*BLOCK_DIM_Y-1]==0){
    if (s[idx]==0){
    if (threadIdx.x>0 && threadIdx.y==0)
    {
        if (s[idx-1])
        {
           if (row>0 )
              b[didx]=b[didx-colsTotal]+a[didx]+b[didx-1]-b[didx-colsTotal-1];
           else 
              b[didx]=a[didx]+b[didx-1];
           s[idx]=1;
        }
            
    }

    if (threadIdx.y>0 && threadIdx.x==0)
    {
        if (s[idx-blockDim.x])
        {
           if (col>0 )
              b[didx]=b[didx-colsTotal]+a[didx]+b[didx-1]-b[didx-colsTotal-1];
           else
              b[didx]=a[didx]+b[didx-colsTotal];
           s[idx]=1;
        }

    }
   
    if (threadIdx.y>0 && threadIdx.x>0)
    {
        if (s[idx-blockDim.x] && s[idx-1])
        {
           b[didx]=b[didx-colsTotal]+a[didx]+b[didx-1]-b[didx-colsTotal-1];
           s[idx]=1;
        }

    }
     if (threadIdx.x==0 && threadIdx.y==0)
     {   
          if (row>0 && col>0)
              b[didx]=b[didx-colsTotal]+a[didx]+b[didx-1]-b[didx-colsTotal-1];
          if (row==0 && col>0)
              b[didx]=a[didx]+b[didx-1];    
          if (row>0 && col==0)
             b[didx]=b[didx-colsTotal]+a[didx];
          if (row==0 && col==0)
              b[didx]=a[didx];
          s[idx]=1; 
     }

    }
    __syncthreads();
    }
}

void cpu_sat(int* a, int* b, int M, int N){

    for(int r=0;r<M;r++)
    {
        for(int c=0; c<N;c++)
        {
            if(r==0) 
            {
              if (c>0)
                  b[r*N+c]=b[r*N+c-1]+a[r*N+c];
              else
                  b[r*N+c]=a[r*N+c];
            }
            else{
              if (c>0)
                  b[r*N+c]=b[r*N+c-1]+a[r*N+c]+b[(r-1)*N+c]-b[(r-1)*N+c-1];
              else
                  b[r*N+c]=a[r*N+c]+b[(r-1)*N+c];
            }
        }
    }

}
int main()
{
    //M is number of rows
    //N is number of columns
    //M,N have to be multiples of BLOCK_DIM_X and BLOCK_DIM_Y
    int M=64,N=64;
    int total_e=M*N;
    int widthstep=total_e*sizeof(int);

    int * matrix_a= (int *)malloc(widthstep);
    int * matrix_b= (int *)malloc(widthstep);
    int * cpu_result = (int *)malloc(widthstep);
    //cout<<"Enter elements for "<< M<<"x"<<N<<" matrix";

    for(int r=0;r<M;r++)
    {
        for(int c=0; c<N;c++)
        {
            //cout<<"Enter Matrix element [ "<<r<<","<<c<<"]";
            matrix_a[r*N+c]=rand()%100;
            matrix_b[r*N+c]=0;
        }
 
    }
    cpu_sat(matrix_a,cpu_result,M,N);
    int * d_matrix_a, * d_matrix_b;

    //cout<<"start copy"<<endl;
    /*
    for(int r=0;r<M;r++)
    {
        for(int c=0; c<N;c++)
        {
            cout << matrix_a[r*N+c]<<" ";
        }
        cout << endl;
    }

    cout<<endl;
    */
    hipMalloc(&d_matrix_a,widthstep);
    hipMalloc(&d_matrix_b,widthstep);

    hipMemcpy(d_matrix_a,matrix_a,widthstep,hipMemcpyHostToDevice);
    hipMemcpy(d_matrix_b,matrix_b,widthstep,hipMemcpyHostToDevice);

    //Creating a grid where the number of blocks are equal to the number of pixels or input matrix elements.

    //Each block contains only one thread.

    dim3 grid(N/BLOCK_DIM_X);  // grid is one dimensional!!
    dim3 blockdim(BLOCK_DIM_X,BLOCK_DIM_Y);
    for (int i=0;i<M/BLOCK_DIM_Y+N/BLOCK_DIM_X-1;i++){
        sat<<<grid,blockdim>>>(d_matrix_a, d_matrix_b,M,N,i);
        //cudaThreadSynchronize();
    }

    hipDeviceSynchronize();
    hipMemcpy(matrix_b,d_matrix_b,widthstep,hipMemcpyDeviceToHost);
    cout<<"Compare with CPU result: "<<endl;
    int count=0; 
    for(int r=0;r<M;r++)
    {
        for(int c=0; c<N;c++)
        {
            if(cpu_result[r*N+c]!=matrix_b[r*N+c])
            {   
                count+=1;//cout << matrix_b[r*N+c]<<" "<<;
            //    if(r==0)
                cout<<r<<" "<<c<<" cpu:"<<cpu_result[r*N+c]<<" gpu:"<<matrix_b[r*N+c]<<endl;
            }
        }
        //cout << endl;
    }
    cout<<"mismatch: "<<count<<endl;
    //system("pause");

    hipFree(d_matrix_a);
    hipFree(d_matrix_b);
    free(matrix_a);
    free(matrix_b);
    return 0;
}

	.text
	.file	"sat_rk.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z18__device_stub__satPiS_iii   # -- Begin function _Z18__device_stub__satPiS_iii
	.type	_Z18__device_stub__satPiS_iii,@function
_Z18__device_stub__satPiS_iii:          # @_Z18__device_stub__satPiS_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z3satPiS_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z18__device_stub__satPiS_iii, .Lfunc_end0-_Z18__device_stub__satPiS_iii
	.cfi_endproc
                                        # -- End function
	.globl	_Z7cpu_satPiS_ii                # -- Begin function _Z7cpu_satPiS_ii
	.type	_Z7cpu_satPiS_ii,@function
_Z7cpu_satPiS_ii:                       # @_Z7cpu_satPiS_ii
	.cfi_startproc
# %bb.0:
	testl	%edx, %edx
	jle	.LBB1_14
# %bb.1:                                # %.preheader.lr.ph
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movslq	%ecx, %rax
	movl	%edx, %edx
	movl	%eax, %r8d
	leaq	(,%rax,4), %r9
	movq	%rsi, %r10
	subq	%r9, %r10
	shlq	$2, %r8
	xorl	%r11d, %r11d
	movq	%rsi, %rbx
	movq	%rdi, %r14
.LBB1_2:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_4 Depth 2
	testl	%ecx, %ecx
	jle	.LBB1_12
# %bb.3:                                # %.lr.ph
                                        #   in Loop: Header=BB1_2 Depth=1
	movq	%r11, %r15
	imulq	%rax, %r15
	leaq	-1(%r11), %r12
	imulq	%rax, %r12
	xorl	%r13d, %r13d
.LBB1_4:                                #   Parent Loop BB1_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	testq	%r11, %r11
	je	.LBB1_5
# %bb.8:                                #   in Loop: Header=BB1_4 Depth=2
	testq	%r13, %r13
	je	.LBB1_10
# %bb.9:                                #   in Loop: Header=BB1_4 Depth=2
	movl	(%r14,%r13), %ebp
	addl	-4(%rbx,%r13), %ebp
	addl	(%r10,%r13), %ebp
	subl	-4(%r10,%r13), %ebp
	movl	%ebp, (%rbx,%r13)
	jmp	.LBB1_11
.LBB1_5:                                #   in Loop: Header=BB1_4 Depth=2
	testq	%r13, %r13
	je	.LBB1_7
# %bb.6:                                #   in Loop: Header=BB1_4 Depth=2
	movl	(%rdi,%r13), %ebp
	addl	-4(%rsi,%r13), %ebp
	movl	%ebp, (%rsi,%r13)
	jmp	.LBB1_11
.LBB1_10:                               #   in Loop: Header=BB1_4 Depth=2
	movl	(%rsi,%r12,4), %ebp
	addl	(%rdi,%r15,4), %ebp
	movl	%ebp, (%rsi,%r15,4)
	jmp	.LBB1_11
.LBB1_7:                                #   in Loop: Header=BB1_4 Depth=2
	movl	(%rdi), %ebp
	movl	%ebp, (%rsi)
.LBB1_11:                               #   in Loop: Header=BB1_4 Depth=2
	addq	$4, %r13
	cmpq	%r13, %r8
	jne	.LBB1_4
.LBB1_12:                               # %._crit_edge
                                        #   in Loop: Header=BB1_2 Depth=1
	incq	%r11
	addq	%r9, %r10
	addq	%r9, %r14
	addq	%r9, %rbx
	cmpq	%rdx, %r11
	jne	.LBB1_2
# %bb.13:
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	.cfi_restore %r12
	.cfi_restore %r13
	.cfi_restore %r14
	.cfi_restore %r15
	.cfi_restore %rbp
.LBB1_14:                               # %._crit_edge65
	retq
.Lfunc_end1:
	.size	_Z7cpu_satPiS_ii, .Lfunc_end1-_Z7cpu_satPiS_ii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$16384, %edi                    # imm = 0x4000
	callq	malloc
	movq	%rax, %rbp
	movl	$16384, %edi                    # imm = 0x4000
	callq	malloc
	movq	%rax, %r12
	movl	$16384, %edi                    # imm = 0x4000
	callq	malloc
	movq	%rax, 40(%rsp)                  # 8-byte Spill
	xorl	%ebx, %ebx
	movl	$256, %r14d                     # imm = 0x100
	movq	%rbp, %r15
	movq	%r12, 8(%rsp)                   # 8-byte Spill
.LBB2_1:                                # %.preheader82
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_2 Depth 2
	xorl	%r13d, %r13d
.LBB2_2:                                #   Parent Loop BB2_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
	cltq
	imulq	$1374389535, %rax, %rcx         # imm = 0x51EB851F
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$37, %rcx
	addl	%edx, %ecx
	imull	$100, %ecx, %ecx
	subl	%ecx, %eax
	movl	%eax, (%r15,%r13,4)
	movl	$0, (%r12,%r13,4)
	incq	%r13
	cmpq	$64, %r13
	jne	.LBB2_2
# %bb.3:                                #   in Loop: Header=BB2_1 Depth=1
	incq	%rbx
	addq	%r14, %r12
	addq	%r14, %r15
	cmpq	$64, %rbx
	jne	.LBB2_1
# %bb.4:
	movq	%rbp, %rdi
	movq	40(%rsp), %r14                  # 8-byte Reload
	movq	%r14, %rsi
	movl	$64, %edx
	movl	$64, %ecx
	callq	_Z7cpu_satPiS_ii
	leaq	32(%rsp), %rbx
	movl	$16384, %esi                    # imm = 0x4000
	movq	%rbx, %rdi
	callq	hipMalloc
	leaq	24(%rsp), %r12
	movl	$16384, %esi                    # imm = 0x4000
	movq	%r12, %rdi
	callq	hipMalloc
	movq	(%rbx), %rdi
	movl	$16384, %edx                    # imm = 0x4000
	movq	%rbp, 48(%rsp)                  # 8-byte Spill
	movq	%rbp, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r12), %rdi
	movl	$16384, %edx                    # imm = 0x4000
	movq	8(%rsp), %rsi                   # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	xorl	%r12d, %r12d
	movabsq	$4294967300, %r13               # imm = 0x100000004
	movabsq	$68719476752, %rbp              # imm = 0x1000000010
.LBB2_5:                                # =>This Inner Loop Header: Depth=1
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%rbp, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_7
# %bb.6:                                #   in Loop: Header=BB2_5 Depth=1
	movq	32(%rsp), %rdi
	movq	24(%rsp), %rsi
	movl	$64, %edx
	movl	$64, %ecx
	movl	%r12d, %r8d
	callq	_Z18__device_stub__satPiS_iii
.LBB2_7:                                #   in Loop: Header=BB2_5 Depth=1
	incl	%r12d
	cmpl	$7, %r12d
	jne	.LBB2_5
# %bb.8:
	callq	hipDeviceSynchronize
	movq	24(%rsp), %rsi
	movl	$16384, %edx                    # imm = 0x4000
	movq	8(%rsp), %r15                   # 8-byte Reload
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$_ZSt4cout, %ebx
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$25, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	xorl	%eax, %eax
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	xorl	%ebp, %ebp
.LBB2_9:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB2_10 Depth 2
	xorl	%r13d, %r13d
.LBB2_10:                               #   Parent Loop BB2_9 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	(%r14,%r13,4), %ebx
	cmpl	(%r15,%r13,4), %ebx
	je	.LBB2_12
# %bb.11:                               #   in Loop: Header=BB2_10 Depth=2
	incl	%ebp
	movl	$_ZSt4cout, %edi
	movq	16(%rsp), %rsi                  # 8-byte Reload
                                        # kill: def $esi killed $esi killed $rsi
	callq	_ZNSolsEi
	movq	%r14, %r12
	movq	%rax, %r14
	movl	$.L.str.1, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r14, %rdi
	movl	%r13d, %esi
	callq	_ZNSolsEi
	movq	%rax, %r14
	movl	$.L.str.2, %esi
	movl	$5, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r14, %rdi
	movq	%r12, %r14
	movl	%ebx, %esi
	callq	_ZNSolsEi
	movq	%rax, %rbx
	movl	$.L.str.3, %esi
	movl	$5, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	(%r15,%r13,4), %esi
	movq	%rbx, %rdi
	callq	_ZNSolsEi
	movq	%rax, %rbx
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
.LBB2_12:                               #   in Loop: Header=BB2_10 Depth=2
	incq	%r13
	cmpq	$64, %r13
	jne	.LBB2_10
# %bb.13:                               #   in Loop: Header=BB2_9 Depth=1
	movq	16(%rsp), %rcx                  # 8-byte Reload
	incq	%rcx
	movl	$256, %eax                      # imm = 0x100
	addq	%rax, %r15
	addq	%rax, %r14
	movq	%rcx, %rax
	movq	%rcx, 16(%rsp)                  # 8-byte Spill
	cmpq	$64, %rcx
	jne	.LBB2_9
# %bb.14:
	movl	$_ZSt4cout, %edi
	movl	$.L.str.4, %esi
	movl	$10, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	%ebp, %esi
	callq	_ZNSolsEi
	movq	%rax, %rbx
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	48(%rsp), %rdi                  # 8-byte Reload
	callq	free
	movq	8(%rsp), %rdi                   # 8-byte Reload
	callq	free
	xorl	%eax, %eax
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	main, .Lfunc_end2-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z3satPiS_iii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z3satPiS_iii,@object           # @_Z3satPiS_iii
	.section	.rodata,"a",@progbits
	.globl	_Z3satPiS_iii
	.p2align	3, 0x0
_Z3satPiS_iii:
	.quad	_Z18__device_stub__satPiS_iii
	.size	_Z3satPiS_iii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Compare with CPU result: "
	.size	.L.str, 26

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	" "
	.size	.L.str.1, 2

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	" cpu:"
	.size	.L.str.2, 6

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	" gpu:"
	.size	.L.str.3, 6

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"mismatch: "
	.size	.L.str.4, 11

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z3satPiS_iii"
	.size	.L__unnamed_1, 14

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z18__device_stub__satPiS_iii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z3satPiS_iii
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z3satPiS_iii           ; -- Begin function _Z3satPiS_iii
	.globl	_Z3satPiS_iii
	.p2align	8
	.type	_Z3satPiS_iii,@function
_Z3satPiS_iii:                          ; @_Z3satPiS_iii
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x2c
	s_load_b128 s[4:7], s[0:1], 0x10
                                        ; implicit-def: $vgpr6
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s2, s3, 16
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v1, s2
	s_sub_i32 s8, 0, s2
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v1, v1
	v_readfirstlane_b32 s7, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s8, s8, s7
	s_mul_hi_u32 s8, s7, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s7, s7, s8
	s_mul_hi_u32 s7, s4, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_mul_i32 s8, s7, s2
	s_add_i32 s9, s7, 1
	s_sub_i32 s8, s4, s8
	s_sub_i32 s10, s8, s2
	s_cmp_ge_u32 s8, s2
	s_cselect_b32 s7, s9, s7
	s_cselect_b32 s8, s10, s8
	s_add_i32 s9, s7, 1
	s_cmp_ge_u32 s8, s2
	s_cselect_b32 s7, s9, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s7, s7, -1
	s_cmp_lt_u32 s7, s6
	s_mov_b32 s7, -1
	s_cbranch_scc1 .LBB0_2
; %bb.1:
	v_bfe_u32 v1, v0, 10, 10
	s_sub_i32 s7, s6, s15
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[6:7], null, s7, s2, v[1:2]
	s_mov_b32 s7, 0
.LBB0_2:                                ; %Flow206
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s7
	s_and_b32 s3, s3, 0xffff
	s_cbranch_vccnz .LBB0_4
; %bb.3:
	v_cvt_f32_u32_e32 v1, s3
	s_sub_i32 s8, 0, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s7, v1
	v_bfe_u32 v1, v0, 10, 10
	s_mul_i32 s8, s8, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s8, s7, s8
	s_add_i32 s7, s7, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s7, s5, s7
	s_mul_i32 s8, s7, s3
	s_add_i32 s9, s7, 1
	s_sub_i32 s8, s5, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s10, s8, s3
	s_cmp_ge_u32 s8, s3
	s_cselect_b32 s7, s9, s7
	s_cselect_b32 s8, s10, s8
	s_add_i32 s9, s7, 1
	s_cmp_ge_u32 s8, s3
	s_cselect_b32 s7, s9, s7
	s_not_b32 s8, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s8, s7, s8
	v_mad_u64_u32 v[6:7], null, s8, s2, v[1:2]
	s_add_i32 s2, s15, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_sub_i32 s2, s2, s7
	s_add_i32 s15, s2, 1
.LBB0_4:
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e32 vcc_lo, s4, v6
	v_cmp_lt_i32_e64 s2, -1, v6
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s4, s2
	s_cbranch_execz .LBB0_38
; %bb.5:
	v_and_b32_e32 v9, 0x3ff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, s15, s3, v[9:10]
	v_cmp_gt_i32_e32 vcc_lo, s5, v7
	v_cmp_lt_i32_e64 s2, -1, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB0_38
; %bb.6:
	v_bfe_u32 v13, v0, 10, 10
	v_mov_b32_e32 v8, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u32_u24 v0, v13, s3, v9
	v_lshlrev_b32_e32 v10, 2, v0
	ds_store_b32 v10, v8
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v1, v8 offset:1020
	s_waitcnt lgkmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, 0, v1
	s_cbranch_vccnz .LBB0_38
; %bb.7:                                ; %.lr.ph
	s_load_b128 s[8:11], s[0:1], 0x0
	v_mad_u64_u32 v[1:2], null, v6, s5, v[7:8]
	v_subrev_nc_u32_e32 v12, s3, v0
	v_cmp_ne_u32_e32 vcc_lo, 0, v9
	v_cmp_eq_u32_e64 s1, 0, v13
	v_cmp_ne_u32_e64 s4, 0, v6
	v_cmp_eq_u32_e64 s0, 0, v6
	v_or_b32_e32 v9, v9, v13
	v_ashrrev_i32_e32 v2, 31, v1
	v_subrev_nc_u32_e32 v3, s5, v1
	v_or_b32_e32 v6, v6, v7
	s_and_b32 s6, s1, vcc_lo
	s_or_b32 s1, s1, vcc_lo
	v_lshlrev_b64 v[14:15], 2, v[1:2]
	v_ashrrev_i32_e32 v4, 31, v3
	s_xor_b32 s7, s1, -1
	v_cmp_ne_u32_e64 s5, 0, v7
	v_cmp_eq_u32_e64 s1, 0, v7
	v_add_nc_u32_e32 v11, -4, v10
	v_lshlrev_b64 v[4:5], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, s2, s8, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v1, s2, s9, v15, s2
	v_add_co_u32 v2, s2, s10, v14
	v_add_co_ci_u32_e64 v3, s2, s11, v15, s2
	v_add_co_u32 v4, s2, s10, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v5, s2, s11, v5, s2
	v_cmp_ne_u32_e64 s2, 0, v13
	v_lshlrev_b32_e32 v12, 2, v12
	v_cmp_eq_u32_e64 s3, 0, v6
	v_mov_b32_e32 v6, 1
	s_and_b32 s9, s4, s5
	s_and_b32 s8, s2, vcc_lo
	v_cmp_eq_u32_e64 s2, 0, v9
	s_and_b32 s5, s0, s5
	s_and_b32 s4, s4, s1
.LBB0_8:                                ; =>This Inner Loop Header: Depth=1
	ds_load_b32 v7, v10
	s_mov_b32 s10, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_eq_u32_e32 0, v7
	s_cbranch_execz .LBB0_37
; %bb.9:                                ;   in Loop: Header=BB0_8 Depth=1
	s_and_saveexec_b32 s11, s6
	s_cbranch_execz .LBB0_16
; %bb.10:                               ;   in Loop: Header=BB0_8 Depth=1
	ds_load_b32 v7, v11
	s_waitcnt lgkmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, 0, v7
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_16
; %bb.11:                               ;   in Loop: Header=BB0_8 Depth=1
                                        ; implicit-def: $vgpr7
	s_and_saveexec_b32 s12, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s12, exec_lo, s12
	s_cbranch_execz .LBB0_13
; %bb.12:                               ;   in Loop: Header=BB0_8 Depth=1
	global_load_b32 v7, v[0:1], off
	global_load_b32 v9, v[2:3], off offset:-4
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v7, v9, v7
.LBB0_13:                               ; %Flow199
                                        ;   in Loop: Header=BB0_8 Depth=1
	s_and_not1_saveexec_b32 s12, s12
	s_cbranch_execz .LBB0_15
; %bb.14:                               ;   in Loop: Header=BB0_8 Depth=1
	global_load_b32 v7, v[0:1], off
	s_clause 0x1
	global_load_b64 v[13:14], v[4:5], off offset:-4
	global_load_b32 v9, v[2:3], off offset:-4
	s_waitcnt vmcnt(0)
	v_add3_u32 v7, v7, v14, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_nc_u32_e32 v7, v7, v13
.LBB0_15:                               ;   in Loop: Header=BB0_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	global_store_b32 v[2:3], v7, off
	ds_store_b32 v10, v6
.LBB0_16:                               ;   in Loop: Header=BB0_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	s_and_saveexec_b32 s11, s7
	s_cbranch_execz .LBB0_23
; %bb.17:                               ;   in Loop: Header=BB0_8 Depth=1
	ds_load_b32 v7, v12
	s_waitcnt lgkmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, 0, v7
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_23
; %bb.18:                               ;   in Loop: Header=BB0_8 Depth=1
                                        ; implicit-def: $vgpr7
	s_and_saveexec_b32 s12, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s12, exec_lo, s12
	s_cbranch_execz .LBB0_20
; %bb.19:                               ;   in Loop: Header=BB0_8 Depth=1
	global_load_b32 v7, v[0:1], off
	global_load_b32 v9, v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v7, v9, v7
.LBB0_20:                               ; %Flow196
                                        ;   in Loop: Header=BB0_8 Depth=1
	s_and_not1_saveexec_b32 s12, s12
	s_cbranch_execz .LBB0_22
; %bb.21:                               ;   in Loop: Header=BB0_8 Depth=1
	global_load_b32 v7, v[0:1], off
	s_clause 0x1
	global_load_b64 v[13:14], v[4:5], off offset:-4
	global_load_b32 v9, v[2:3], off offset:-4
	s_waitcnt vmcnt(0)
	v_add3_u32 v7, v7, v14, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_nc_u32_e32 v7, v7, v13
.LBB0_22:                               ;   in Loop: Header=BB0_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	global_store_b32 v[2:3], v7, off
	ds_store_b32 v10, v6
.LBB0_23:                               ;   in Loop: Header=BB0_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	s_and_saveexec_b32 s11, s8
	s_cbranch_execz .LBB0_27
; %bb.24:                               ;   in Loop: Header=BB0_8 Depth=1
	ds_load_b32 v7, v12
	s_waitcnt lgkmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, 0, v7
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_27
; %bb.25:                               ;   in Loop: Header=BB0_8 Depth=1
	ds_load_b32 v7, v11
	s_waitcnt lgkmcnt(0)
	v_cmp_ne_u32_e32 vcc_lo, 0, v7
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_27
; %bb.26:                               ;   in Loop: Header=BB0_8 Depth=1
	global_load_b32 v7, v[0:1], off
	s_clause 0x1
	global_load_b64 v[13:14], v[4:5], off offset:-4
	global_load_b32 v9, v[2:3], off offset:-4
	ds_store_b32 v10, v6
	s_waitcnt vmcnt(0)
	v_add3_u32 v7, v7, v14, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_nc_u32_e32 v7, v7, v13
	global_store_b32 v[2:3], v7, off
.LBB0_27:                               ;   in Loop: Header=BB0_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB0_37
; %bb.28:                               ;   in Loop: Header=BB0_8 Depth=1
	s_and_saveexec_b32 s11, s9
	s_cbranch_execz .LBB0_30
; %bb.29:                               ;   in Loop: Header=BB0_8 Depth=1
	global_load_b32 v7, v[0:1], off
	s_clause 0x1
	global_load_b64 v[13:14], v[4:5], off offset:-4
	global_load_b32 v9, v[2:3], off offset:-4
	s_waitcnt vmcnt(0)
	v_add3_u32 v7, v7, v14, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_nc_u32_e32 v7, v7, v13
	global_store_b32 v[2:3], v7, off
.LBB0_30:                               ;   in Loop: Header=BB0_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	s_and_saveexec_b32 s11, s5
	s_cbranch_execz .LBB0_32
; %bb.31:                               ;   in Loop: Header=BB0_8 Depth=1
	global_load_b32 v7, v[0:1], off
	global_load_b32 v9, v[2:3], off offset:-4
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v7, v9, v7
	global_store_b32 v[2:3], v7, off
.LBB0_32:                               ;   in Loop: Header=BB0_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	s_and_saveexec_b32 s11, s4
	s_cbranch_execz .LBB0_34
; %bb.33:                               ;   in Loop: Header=BB0_8 Depth=1
	global_load_b32 v7, v[4:5], off
	global_load_b32 v9, v[0:1], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v7, v9, v7
	global_store_b32 v[2:3], v7, off
.LBB0_34:                               ;   in Loop: Header=BB0_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	s_and_saveexec_b32 s11, s3
	s_cbranch_execz .LBB0_36
; %bb.35:                               ;   in Loop: Header=BB0_8 Depth=1
	global_load_b32 v7, v[0:1], off
	s_waitcnt vmcnt(0)
	global_store_b32 v[2:3], v7, off
.LBB0_36:                               ;   in Loop: Header=BB0_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	ds_store_b32 v10, v6
.LBB0_37:                               ; %Flow201
                                        ;   in Loop: Header=BB0_8 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v7, v8 offset:1020
	s_waitcnt lgkmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, 0, v7
	s_cbranch_vccnz .LBB0_8
.LBB0_38:                               ; %.loopexit
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z3satPiS_iii
		.amdhsa_group_segment_fixed_size 1024
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 16
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z3satPiS_iii, .Lfunc_end0-_Z3satPiS_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1440
; NumSgprs: 18
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1024 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 1024
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z3satPiS_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z3satPiS_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     16
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
