#include <math.h>
#define ABS(x) ((x) > 0 ? (x) : - (x))
#define MAX(a, b) ((a) > (b) ? (a) : (b))

__global__ void kernel_projection(float *proj, float *img, float angle, float SO, float SD, float da, int na, float ai, float db, int nb, float bi, int nx, int ny, int nz){
    int ia = 16 * blockIdx.x + threadIdx.x;
    int ib = 16 * blockIdx.y + threadIdx.y;
    if (ia >= na || ib >= nb)
        return;
    int id = ia + ib * na;
    proj[id] = 0.0f;
    float x1, y1, z1, x2, y2, z2, x20, y20, cphi, sphi;
    cphi = (float)cosf(angle);
    sphi = (float)sinf(angle);
    x1 = -SO * cphi;
    y1 = -SO * sphi;
    z1 = 0.0f;
    x20 = SD - SO;
    y20 = (ia + ai) * da; // locate the detector cell center before any rotation
    x2 = x20 * cphi - y20 * sphi;
    y2 = x20 * sphi + y20 * cphi;
    z2 = (ib + bi) * db;
    float x21, y21, z21; // offset between source and detector center
    x21 = x2 - x1;
    y21 = y2 - y1;
    z21 = z2 - z1;

    // y - z plane, where ABS(x21) > ABS(y21)
    if (ABS(x21) > ABS(y21)){
    // if (ABS(cphi) > ABS(sphi)){
        float yi1, yi2, ky1, ky2, zi1, zi2, kz1, kz2;
        int Yi1, Yi2, Zi1, Zi2;
        // for each y - z plane, we calculate and add the contribution of related pixels
        for (int ix = 0; ix < nx; ix++){
            // calculate y indices of intersecting voxel candidates
            ky1 = (y21 - da / 2 * cphi) / (x21 + da / 2 * sphi);
            yi1 = ky1 * ((float)ix + 0.5f - x1 - nx / 2) + y1 + ny / 2;
            Yi1 = (int)floor(yi1); // lower boundary of related voxels at y-axis
            ky2 = (y21 + da / 2 * cphi) / (x21 - da / 2 * sphi);
            yi2 = ky2 * ((float)ix + 0.5f - x1 - nx / 2) + y1 + ny / 2;
            Yi2 = (int)floor(yi2); // upper boundary of related voxels at y-axis
            // if (Yi1 < 0)
            //     Yi1 = 0;
            // if (Yi2 >= ny)
            //     Yi2 = ny - 1;

            // calculate z indices of intersecting voxel candidates
            kz1 = (z21 - db / 2) / x21;
            zi1 = kz1 * ((float)ix + 0.5f - x1 - nx / 2) + z1 + nz / 2;
            Zi1 = (int)floor(zi1); // lower boundary of related voxels at y-axis
            kz2 = (z21 + db / 2) / x21;
            zi2 = kz2 * ((float)ix + 0.5f - x1 - nx / 2) + z1 + nz / 2;
            Zi2 = (int)floor(zi2); // upper boundary of related voxels at y-axis
            // if (Zi1 < 0)
            //     Zi1 = 0;
            // if (Zi2 >= nz)
            //     Zi2 = nz - 1;

            // calculate contribution of a voxel to the projection value
            int iy, iz;
            float wy1, wy2, wz1, wz2;
            if (ABS(yi2 - yi1) < 0.01f)
            continue;
            if (ABS(zi2 - zi1) < 0.01f)
            continue;
            
            wy1 = (MAX(Yi1, Yi2) - yi1) / (yi2 - yi1); wy2 = 1 - wy1;
            wz1 = (MAX(Zi1, Zi2) - zi1) / (zi2 - zi1); wz2 = 1 - wz1;

            // Yi1 == Yi2 && Zi1 == Zi2
            if (Yi1 == Yi2 && Zi1 == Zi2)
            {
                iy = Yi1; iz = Zi1; 
                if (iy < ny && iy >= 0 && iz < nz && iz >= 0)
                    proj[id] += img[ix + iy * nx + iz * nx * ny] * 1.0f;
                continue;
            }
            // Yi1 != Yi2 && Zi1 == Zi2
            if (Yi1 != Yi2 && Zi1 == Zi2)
            {
                iy = Yi1; iz = Zi1; 
                if (iy < ny && iy >= 0 && iz < nz && iz >= 0)
                    proj[id] += img[ix + iy * nx + iz * nx * ny] * wy1;
                iy = Yi2; iz = Zi1; 
                if (iy < ny && iy >= 0 && iz < nz && iz >= 0)
                    proj[id] += img[ix + iy * nx + iz * nx * ny] * wy2;
                continue;                
            }
            // Yi1 == Yi2 && Zi1 != Zi2
            if (Yi1 == Yi2 && Zi1 != Zi2)
            {
                iy = Yi1; iz = Zi1; 
                if (iy < ny && iy >= 0 && iz < nz && iz >= 0)
                    proj[id] += img[ix + iy * nx + iz * nx * ny] * wz1;
                iy = Yi1; iz = Zi2; 
                if (iy < ny && iy >= 0 && iz < nz && iz >= 0)
                    proj[id] += img[ix + iy * nx + iz * nx * ny] * wz2;
                continue;                
            }
            // Yi1 != Yi2 && Zi1 != Zi2
            if (Yi1 != Yi2 && Zi1 != Zi2)
            {
                iy = Yi1; iz = Zi1; 
                if (iy < ny && iy >= 0 && iz < nz && iz >= 0)
                    proj[id] += img[ix + iy * nx + iz * nx * ny] * wy1 * wz1;
                iy = Yi1; iz = Zi2; 
                if (iy < ny && iy >= 0 && iz < nz && iz >= 0)
                    proj[id] += img[ix + iy * nx + iz * nx * ny] * wy1 * wz2;
                iy = Yi2; iz = Zi1; 
                if (iy < ny && iy >= 0 && iz < nz && iz >= 0)
                    proj[id] += img[ix + iy * nx + iz * nx * ny] * wy2 * wz1;
                iy = Yi2; iz = Zi2; 
                if (iy < ny && iy >= 0 && iz < nz && iz >= 0)
                    proj[id] += img[ix + iy * nx + iz * nx * ny] * wy2 * wz2;
                continue;                
            }
        }
    }
    // x - z plane, where ABS(x21) <= ABS(y21)    
    else{
    float xi1, xi2, kx1, kx2, zi1, zi2, kz1, kz2;
        int Xi1, Xi2, Zi1, Zi2;
        // for each y - z plane, we calculate and add the contribution of related pixels
        for (int iy = 0; iy < ny; iy++){
            // calculate y indices of intersecting voxel candidates
            kx1 = (x21 - da / 2 * sphi) / (y21 + da / 2 * cphi);
            xi1 = kx1 * ((float)iy + 0.5f - y1 - ny / 2) + x1 + nx / 2;
            Xi1 = (int)floor(xi1); // lower boundary of related voxels at y-axis
            kx2 = (x21 + da / 2 * sphi) / (y21 - da / 2 * cphi);
            xi2 = kx2 * ((float)iy + 0.5f - y1 - ny / 2) + x1 + nx / 2;
            Xi2 = (int)floor(xi2); // upper boundary of related voxels at y-axis
            // if (Xi1 < 0)
            //     Xi1 = 0;
            // if (Xi2 >= ny)
            //     Xi2 = ny - 1;

            // calculate z indices of intersecting voxel candidates
            kz1 = (z21 - db / 2) / y21;
            zi1 = kz1 * ((float)iy + 0.5f - y1 - ny / 2) + z1 + nz / 2;
            Zi1 = (int)floor(zi1); // lower boundary of related voxels at y-axis
            kz2 = (z21 + db / 2) / y21;
            zi2 = kz2 * ((float)iy + 0.5f - y1 - ny / 2) + z1 + nz / 2;
            Zi2 = (int)floor(zi2); // upper boundary of related voxels at y-axis
            // if (Zi1 < 0)
            //     Zi1 = 0;
            // if (Zi2 >= nz)
            //     Zi2 = nz - 1;

            // calculate contribution of a voxel to the projection value
            int ix, iz;
            float wx1, wx2, wz1, wz2;
            if (ABS(xi2 - xi1) < 0.01f)
            continue;
            if (ABS(zi2 - zi1) < 0.01f)
            continue;
            wx1 = (MAX(Xi1, Xi2) - xi1) / (xi2 - xi1); wx2 = 1 - wx1;
            wz1 = (MAX(Zi1, Zi2) - zi1) / (zi2 - zi1); wz2 = 1 - wz1;

            // Xi1 == Xi2 && Zi1 == Zi2
            if (Xi1 == Xi2 && Zi1 == Zi2)
            {
                ix = Xi1; iz = Zi1; 
                if (ix < nx && ix >= 0 && iz < nz && iz >= 0)
                    proj[id] += img[ix + iy * nx + iz * nx * ny] * 1.0f;
                continue;
            }
            // Xi1 != Xi2 && Zi1 == Zi2
            if (Xi1 != Xi2 && Zi1 == Zi2)
            {
                ix = Xi1; iz = Zi1; 
                if (ix < nx && ix >= 0 && iz < nz && iz >= 0)
                    proj[id] += img[ix + iy * nx + iz * nx * ny] * wx1;
                ix = Xi2; iz = Zi1; 
                if (ix < nx && ix >= 0 && iz < nz && iz >= 0)
                    proj[id] += img[ix + iy * nx + iz * nx * ny] * wx2;
                continue;                
            }
            // Xi1 == Xi2 && Zi1 != Zi2
            if (Xi1 == Xi2 && Zi1 != Zi2)
            {
                ix = Xi1; iz = Zi1; 
                if (ix < nx && ix >= 0 && iz < nz && iz >= 0)
                    proj[id] += img[ix + iy * nx + iz * nx * ny] * wz1;
                ix = Xi1; iz = Zi2; 
                if (ix < nx && ix >= 0 && iz < nz && iz >= 0)
                    proj[id] += img[ix + iy * nx + iz * nx * ny] * wz2;
                continue;                
            }
            // Xi1 != Xi2 && Zi1 != Zi2
            if (Xi1 != Xi2 && Zi1 != Zi2)
            {
                ix = Xi1; iz = Zi1; 
                if (ix < nx && ix >= 0 && iz < nz && iz >= 0)
                    proj[id] += img[ix + iy * nx + iz * nx * ny] * wx1 * wz1;
                ix = Xi1; iz = Zi2; 
                if (ix < nx && ix >= 0 && iz < nz && iz >= 0)
                    proj[id] += img[ix + iy * nx + iz * nx * ny] * wx1 * wz2;
                ix = Xi2; iz = Zi1; 
                if (ix < nx && ix >= 0 && iz < nz && iz >= 0)
                    proj[id] += img[ix + iy * nx + iz * nx * ny] * wx2 * wz1;
                ix = Xi2; iz = Zi2; 
                if (ix < nx && ix >= 0 && iz < nz && iz >= 0)
                    proj[id] += img[ix + iy * nx + iz * nx * ny] * wx2 * wz2;
                continue;                
            }
        }
    }

        

    
}
	.file	"tmpxft_0020148c_00000000-6_kernel_projection.1.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z51__device_stub__Z17kernel_projectionPfS_ffffiffifiiiPfS_ffffiffifiii
	.type	_Z51__device_stub__Z17kernel_projectionPfS_ffffiffifiiiPfS_ffffiffifiii, @function
_Z51__device_stub__Z17kernel_projectionPfS_ffffiffifiiiPfS_ffffiffifiii:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$264, %rsp
	.cfi_def_cfa_offset 272
	movq	%rdi, 56(%rsp)
	leaq	88(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	100(%rsp), %rsi
	movl	%edx, 28(%rsp)
	leaq	72(%rsp), %rdx
	movl	%ecx, 16(%rsp)
	leaq	80(%rsp), %rcx
	movl	%r8d, 8(%rsp)
	movl	%r9d, 4(%rsp)
	movss	%xmm0, 44(%rsp)
	movss	%xmm1, 40(%rsp)
	movss	%xmm2, 36(%rsp)
	movss	%xmm3, 32(%rsp)
	movss	%xmm4, 24(%rsp)
	movss	%xmm5, 20(%rsp)
	movss	%xmm6, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 248(%rsp)
	xorl	%eax, %eax
	leaq	56(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	44(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	272(%rsp), %rax
	movq	%rax, 240(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 88(%rsp)
	movl	$1, 96(%rsp)
	movq	%rax, 100(%rsp)
	movl	$1, 108(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	80(%rsp)
	.cfi_def_cfa_offset 280
	leaq	_Z17kernel_projectionPfS_ffffiffifiii(%rip), %rdi
	pushq	80(%rsp)
	.cfi_def_cfa_offset 288
	movq	116(%rsp), %rcx
	movl	124(%rsp), %r8d
	movq	104(%rsp), %rsi
	movl	112(%rsp), %edx
	leaq	152(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 280
	popq	%rdx
	.cfi_def_cfa_offset 272
.L2:
	movq	248(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$264, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z51__device_stub__Z17kernel_projectionPfS_ffffiffifiiiPfS_ffffiffifiii, .-_Z51__device_stub__Z17kernel_projectionPfS_ffffiffifiiiPfS_ffffiffifiii
	.globl	_Z17kernel_projectionPfS_ffffiffifiii
	.type	_Z17kernel_projectionPfS_ffffiffifiii, @function
_Z17kernel_projectionPfS_ffffiffifiii:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z51__device_stub__Z17kernel_projectionPfS_ffffiffifiiiPfS_ffffiffifiii
	.cfi_endproc
.LFE2033:
	.size	_Z17kernel_projectionPfS_ffffiffifiii, .-_Z17kernel_projectionPfS_ffffiffifiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z17kernel_projectionPfS_ffffiffifiii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z17kernel_projectionPfS_ffffiffifiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <math.h>
#define ABS(x) ((x) > 0 ? (x) : - (x))
#define MAX(a, b) ((a) > (b) ? (a) : (b))

__global__ void kernel_projection(float *proj, float *img, float angle, float SO, float SD, float da, int na, float ai, float db, int nb, float bi, int nx, int ny, int nz){
    int ia = 16 * blockIdx.x + threadIdx.x;
    int ib = 16 * blockIdx.y + threadIdx.y;
    if (ia >= na || ib >= nb)
        return;
    int id = ia + ib * na;
    proj[id] = 0.0f;
    float x1, y1, z1, x2, y2, z2, x20, y20, cphi, sphi;
    cphi = (float)cosf(angle);
    sphi = (float)sinf(angle);
    x1 = -SO * cphi;
    y1 = -SO * sphi;
    z1 = 0.0f;
    x20 = SD - SO;
    y20 = (ia + ai) * da; // locate the detector cell center before any rotation
    x2 = x20 * cphi - y20 * sphi;
    y2 = x20 * sphi + y20 * cphi;
    z2 = (ib + bi) * db;
    float x21, y21, z21; // offset between source and detector center
    x21 = x2 - x1;
    y21 = y2 - y1;
    z21 = z2 - z1;

    // y - z plane, where ABS(x21) > ABS(y21)
    if (ABS(x21) > ABS(y21)){
    // if (ABS(cphi) > ABS(sphi)){
        float yi1, yi2, ky1, ky2, zi1, zi2, kz1, kz2;
        int Yi1, Yi2, Zi1, Zi2;
        // for each y - z plane, we calculate and add the contribution of related pixels
        for (int ix = 0; ix < nx; ix++){
            // calculate y indices of intersecting voxel candidates
            ky1 = (y21 - da / 2 * cphi) / (x21 + da / 2 * sphi);
            yi1 = ky1 * ((float)ix + 0.5f - x1 - nx / 2) + y1 + ny / 2;
            Yi1 = (int)floor(yi1); // lower boundary of related voxels at y-axis
            ky2 = (y21 + da / 2 * cphi) / (x21 - da / 2 * sphi);
            yi2 = ky2 * ((float)ix + 0.5f - x1 - nx / 2) + y1 + ny / 2;
            Yi2 = (int)floor(yi2); // upper boundary of related voxels at y-axis
            // if (Yi1 < 0)
            //     Yi1 = 0;
            // if (Yi2 >= ny)
            //     Yi2 = ny - 1;

            // calculate z indices of intersecting voxel candidates
            kz1 = (z21 - db / 2) / x21;
            zi1 = kz1 * ((float)ix + 0.5f - x1 - nx / 2) + z1 + nz / 2;
            Zi1 = (int)floor(zi1); // lower boundary of related voxels at y-axis
            kz2 = (z21 + db / 2) / x21;
            zi2 = kz2 * ((float)ix + 0.5f - x1 - nx / 2) + z1 + nz / 2;
            Zi2 = (int)floor(zi2); // upper boundary of related voxels at y-axis
            // if (Zi1 < 0)
            //     Zi1 = 0;
            // if (Zi2 >= nz)
            //     Zi2 = nz - 1;

            // calculate contribution of a voxel to the projection value
            int iy, iz;
            float wy1, wy2, wz1, wz2;
            if (ABS(yi2 - yi1) < 0.01f)
            continue;
            if (ABS(zi2 - zi1) < 0.01f)
            continue;
            
            wy1 = (MAX(Yi1, Yi2) - yi1) / (yi2 - yi1); wy2 = 1 - wy1;
            wz1 = (MAX(Zi1, Zi2) - zi1) / (zi2 - zi1); wz2 = 1 - wz1;

            // Yi1 == Yi2 && Zi1 == Zi2
            if (Yi1 == Yi2 && Zi1 == Zi2)
            {
                iy = Yi1; iz = Zi1; 
                if (iy < ny && iy >= 0 && iz < nz && iz >= 0)
                    proj[id] += img[ix + iy * nx + iz * nx * ny] * 1.0f;
                continue;
            }
            // Yi1 != Yi2 && Zi1 == Zi2
            if (Yi1 != Yi2 && Zi1 == Zi2)
            {
                iy = Yi1; iz = Zi1; 
                if (iy < ny && iy >= 0 && iz < nz && iz >= 0)
                    proj[id] += img[ix + iy * nx + iz * nx * ny] * wy1;
                iy = Yi2; iz = Zi1; 
                if (iy < ny && iy >= 0 && iz < nz && iz >= 0)
                    proj[id] += img[ix + iy * nx + iz * nx * ny] * wy2;
                continue;                
            }
            // Yi1 == Yi2 && Zi1 != Zi2
            if (Yi1 == Yi2 && Zi1 != Zi2)
            {
                iy = Yi1; iz = Zi1; 
                if (iy < ny && iy >= 0 && iz < nz && iz >= 0)
                    proj[id] += img[ix + iy * nx + iz * nx * ny] * wz1;
                iy = Yi1; iz = Zi2; 
                if (iy < ny && iy >= 0 && iz < nz && iz >= 0)
                    proj[id] += img[ix + iy * nx + iz * nx * ny] * wz2;
                continue;                
            }
            // Yi1 != Yi2 && Zi1 != Zi2
            if (Yi1 != Yi2 && Zi1 != Zi2)
            {
                iy = Yi1; iz = Zi1; 
                if (iy < ny && iy >= 0 && iz < nz && iz >= 0)
                    proj[id] += img[ix + iy * nx + iz * nx * ny] * wy1 * wz1;
                iy = Yi1; iz = Zi2; 
                if (iy < ny && iy >= 0 && iz < nz && iz >= 0)
                    proj[id] += img[ix + iy * nx + iz * nx * ny] * wy1 * wz2;
                iy = Yi2; iz = Zi1; 
                if (iy < ny && iy >= 0 && iz < nz && iz >= 0)
                    proj[id] += img[ix + iy * nx + iz * nx * ny] * wy2 * wz1;
                iy = Yi2; iz = Zi2; 
                if (iy < ny && iy >= 0 && iz < nz && iz >= 0)
                    proj[id] += img[ix + iy * nx + iz * nx * ny] * wy2 * wz2;
                continue;                
            }
        }
    }
    // x - z plane, where ABS(x21) <= ABS(y21)    
    else{
    float xi1, xi2, kx1, kx2, zi1, zi2, kz1, kz2;
        int Xi1, Xi2, Zi1, Zi2;
        // for each y - z plane, we calculate and add the contribution of related pixels
        for (int iy = 0; iy < ny; iy++){
            // calculate y indices of intersecting voxel candidates
            kx1 = (x21 - da / 2 * sphi) / (y21 + da / 2 * cphi);
            xi1 = kx1 * ((float)iy + 0.5f - y1 - ny / 2) + x1 + nx / 2;
            Xi1 = (int)floor(xi1); // lower boundary of related voxels at y-axis
            kx2 = (x21 + da / 2 * sphi) / (y21 - da / 2 * cphi);
            xi2 = kx2 * ((float)iy + 0.5f - y1 - ny / 2) + x1 + nx / 2;
            Xi2 = (int)floor(xi2); // upper boundary of related voxels at y-axis
            // if (Xi1 < 0)
            //     Xi1 = 0;
            // if (Xi2 >= ny)
            //     Xi2 = ny - 1;

            // calculate z indices of intersecting voxel candidates
            kz1 = (z21 - db / 2) / y21;
            zi1 = kz1 * ((float)iy + 0.5f - y1 - ny / 2) + z1 + nz / 2;
            Zi1 = (int)floor(zi1); // lower boundary of related voxels at y-axis
            kz2 = (z21 + db / 2) / y21;
            zi2 = kz2 * ((float)iy + 0.5f - y1 - ny / 2) + z1 + nz / 2;
            Zi2 = (int)floor(zi2); // upper boundary of related voxels at y-axis
            // if (Zi1 < 0)
            //     Zi1 = 0;
            // if (Zi2 >= nz)
            //     Zi2 = nz - 1;

            // calculate contribution of a voxel to the projection value
            int ix, iz;
            float wx1, wx2, wz1, wz2;
            if (ABS(xi2 - xi1) < 0.01f)
            continue;
            if (ABS(zi2 - zi1) < 0.01f)
            continue;
            wx1 = (MAX(Xi1, Xi2) - xi1) / (xi2 - xi1); wx2 = 1 - wx1;
            wz1 = (MAX(Zi1, Zi2) - zi1) / (zi2 - zi1); wz2 = 1 - wz1;

            // Xi1 == Xi2 && Zi1 == Zi2
            if (Xi1 == Xi2 && Zi1 == Zi2)
            {
                ix = Xi1; iz = Zi1; 
                if (ix < nx && ix >= 0 && iz < nz && iz >= 0)
                    proj[id] += img[ix + iy * nx + iz * nx * ny] * 1.0f;
                continue;
            }
            // Xi1 != Xi2 && Zi1 == Zi2
            if (Xi1 != Xi2 && Zi1 == Zi2)
            {
                ix = Xi1; iz = Zi1; 
                if (ix < nx && ix >= 0 && iz < nz && iz >= 0)
                    proj[id] += img[ix + iy * nx + iz * nx * ny] * wx1;
                ix = Xi2; iz = Zi1; 
                if (ix < nx && ix >= 0 && iz < nz && iz >= 0)
                    proj[id] += img[ix + iy * nx + iz * nx * ny] * wx2;
                continue;                
            }
            // Xi1 == Xi2 && Zi1 != Zi2
            if (Xi1 == Xi2 && Zi1 != Zi2)
            {
                ix = Xi1; iz = Zi1; 
                if (ix < nx && ix >= 0 && iz < nz && iz >= 0)
                    proj[id] += img[ix + iy * nx + iz * nx * ny] * wz1;
                ix = Xi1; iz = Zi2; 
                if (ix < nx && ix >= 0 && iz < nz && iz >= 0)
                    proj[id] += img[ix + iy * nx + iz * nx * ny] * wz2;
                continue;                
            }
            // Xi1 != Xi2 && Zi1 != Zi2
            if (Xi1 != Xi2 && Zi1 != Zi2)
            {
                ix = Xi1; iz = Zi1; 
                if (ix < nx && ix >= 0 && iz < nz && iz >= 0)
                    proj[id] += img[ix + iy * nx + iz * nx * ny] * wx1 * wz1;
                ix = Xi1; iz = Zi2; 
                if (ix < nx && ix >= 0 && iz < nz && iz >= 0)
                    proj[id] += img[ix + iy * nx + iz * nx * ny] * wx1 * wz2;
                ix = Xi2; iz = Zi1; 
                if (ix < nx && ix >= 0 && iz < nz && iz >= 0)
                    proj[id] += img[ix + iy * nx + iz * nx * ny] * wx2 * wz1;
                ix = Xi2; iz = Zi2; 
                if (ix < nx && ix >= 0 && iz < nz && iz >= 0)
                    proj[id] += img[ix + iy * nx + iz * nx * ny] * wx2 * wz2;
                continue;                
            }
        }
    }

        

    
}
	.text
	.file	"kernel_projection.1.hip"
	.globl	_Z32__device_stub__kernel_projectionPfS_ffffiffifiii # -- Begin function _Z32__device_stub__kernel_projectionPfS_ffffiffifiii
	.type	_Z32__device_stub__kernel_projectionPfS_ffffiffifiii,@function
_Z32__device_stub__kernel_projectionPfS_ffffiffifiii: # @_Z32__device_stub__kernel_projectionPfS_ffffiffifiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$232, %rsp
	.cfi_def_cfa_offset 288
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	44(%rsp), %rsi
	movss	%xmm0, (%rsi)
	leaq	40(%rsp), %r10
	movss	%xmm1, (%r10)
	leaq	36(%rsp), %r11
	movss	%xmm2, (%r11)
	leaq	32(%rsp), %r14
	movss	%xmm3, (%r14)
	leaq	28(%rsp), %r15
	movl	%edx, (%r15)
	leaq	24(%rsp), %rdx
	movss	%xmm4, (%rdx)
	leaq	20(%rsp), %r12
	movss	%xmm5, (%r12)
	leaq	16(%rsp), %r13
	movl	%ecx, (%r13)
	leaq	12(%rsp), %rcx
	movss	%xmm6, (%rcx)
	leaq	8(%rsp), %rbp
	movl	%r8d, (%rbp)
	leaq	4(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%r10, 24(%rbx)
	movq	%r11, 32(%rbx)
	movq	%r14, 40(%rbx)
	movq	%r15, 48(%rbx)
	movq	%rdx, 56(%rbx)
	movq	%r12, 64(%rbx)
	movq	%r13, 72(%rbx)
	movq	%rcx, 80(%rbx)
	movq	%rbp, 88(%rbx)
	movq	%r8, 96(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	56(%rsp), %r12
	leaq	48(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17kernel_projectionPfS_ffffiffifiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$248, %rsp
	.cfi_adjust_cfa_offset -248
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z32__device_stub__kernel_projectionPfS_ffffiffifiii, .Lfunc_end0-_Z32__device_stub__kernel_projectionPfS_ffffiffifiii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17kernel_projectionPfS_ffffiffifiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z17kernel_projectionPfS_ffffiffifiii,@object # @_Z17kernel_projectionPfS_ffffiffifiii
	.section	.rodata,"a",@progbits
	.globl	_Z17kernel_projectionPfS_ffffiffifiii
	.p2align	3, 0x0
_Z17kernel_projectionPfS_ffffiffifiii:
	.quad	_Z32__device_stub__kernel_projectionPfS_ffffiffifiii
	.size	_Z17kernel_projectionPfS_ffffiffifiii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z17kernel_projectionPfS_ffffiffifiii"
	.size	.L__unnamed_1, 38

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z32__device_stub__kernel_projectionPfS_ffffiffifiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z17kernel_projectionPfS_ffffiffifiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z17kernel_projectionPfS_ffffiffifiii ; -- Begin function _Z17kernel_projectionPfS_ffffiffifiii
	.globl	_Z17kernel_projectionPfS_ffffiffifiii
	.p2align	8
	.type	_Z17kernel_projectionPfS_ffffiffifiii,@function
_Z17kernel_projectionPfS_ffffiffifiii:  ; @_Z17kernel_projectionPfS_ffffiffifiii
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x10
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v2, s14, 4, v1
	v_lshl_add_u32 v3, s15, 4, v0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s8, v2
	v_cmp_gt_i32_e64 s2, s11, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_109
; %bb.1:
	s_clause 0x1
	s_load_b128 s[12:15], s[0:1], 0x0
	s_load_b128 s[16:19], s[0:1], 0x30
	v_mad_u64_u32 v[0:1], null, v3, s8, v[2:3]
	v_cmp_ngt_f32_e64 s1, 0x48000000, |s4|
	v_mov_b32_e32 v4, 0
	s_and_b32 s0, s4, 0x7fffffff
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s12, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s13, v1, vcc_lo
	s_and_b32 vcc_lo, exec_lo, s1
	global_store_b32 v[0:1], v4, off
	s_cbranch_vccz .LBB0_3
; %bb.2:
	s_and_b32 s2, s0, 0x7fffff
	s_lshr_b32 s3, s0, 23
	s_bitset1_b32 s2, 23
	s_addk_i32 s3, 0xff88
	s_mul_hi_u32 s8, s2, 0xfe5163ab
	s_mul_i32 s11, s2, 0x3c439041
	s_mul_hi_u32 s12, s2, 0x3c439041
	s_add_u32 s8, s8, s11
	s_addc_u32 s11, 0, s12
	s_mul_i32 s12, s2, 0xdb629599
	s_mul_hi_u32 s13, s2, 0xdb629599
	s_add_u32 s11, s11, s12
	s_addc_u32 s12, 0, s13
	s_mul_i32 s13, s2, 0xf534ddc0
	s_mul_hi_u32 s20, s2, 0xf534ddc0
	s_add_u32 s12, s12, s13
	s_addc_u32 s13, 0, s20
	s_mul_i32 s20, s2, 0xfc2757d1
	s_mul_hi_u32 s21, s2, 0xfc2757d1
	s_add_u32 s13, s13, s20
	s_addc_u32 s20, 0, s21
	s_mul_i32 s21, s2, 0x4e441529
	s_mul_hi_u32 s22, s2, 0x4e441529
	s_add_u32 s20, s20, s21
	s_addc_u32 s21, 0, s22
	s_cmp_gt_u32 s3, 63
	s_mul_i32 s22, s2, 0xfe5163ab
	s_mul_hi_u32 s23, s2, 0xa2f9836e
	s_mul_i32 s2, s2, 0xa2f9836e
	s_cselect_b32 s24, s11, s13
	s_cselect_b32 s8, s8, s12
	s_cselect_b32 s11, s22, s11
	s_add_u32 s2, s21, s2
	s_addc_u32 s21, 0, s23
	s_cmp_gt_u32 s3, 63
	s_cselect_b32 s22, 0xffffffc0, 0
	s_cselect_b32 s12, s12, s20
	s_cselect_b32 s2, s13, s2
	s_cselect_b32 s13, s20, s21
	s_add_i32 s22, s22, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s22, 31
	s_cselect_b32 s3, 0xffffffe0, 0
	s_cselect_b32 s20, s12, s2
	s_cselect_b32 s2, s2, s13
	s_cselect_b32 s12, s24, s12
	s_cselect_b32 s13, s8, s24
	s_cselect_b32 s8, s11, s8
	s_add_i32 s3, s3, s22
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s3, 31
	s_cselect_b32 s11, 0xffffffe0, 0
	s_cselect_b32 s2, s20, s2
	s_cselect_b32 s20, s12, s20
	s_cselect_b32 s12, s13, s12
	s_cselect_b32 s8, s8, s13
	s_add_i32 s11, s11, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_sub_i32 s3, 32, s11
	s_cmp_eq_u32 s11, 0
	v_mov_b32_e32 v4, s3
	s_cselect_b32 s11, -1, 0
	v_alignbit_b32 v5, s2, s20, v4
	v_alignbit_b32 v6, s20, s12, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s3, v5
	v_cndmask_b32_e64 v5, v6, s20, s11
	s_delay_alu instid0(VALU_DEP_2)
	s_cselect_b32 s2, s2, s3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v6, s2, v5, 30
	s_bfe_u32 s3, s2, 0x1001d
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s13, 0, s3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_xor_b32_e32 v6, s13, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v7, v6
	v_min_u32_e32 v7, 32, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v9, 23, v7
	v_alignbit_b32 v4, s12, s8, v4
	v_sub_nc_u32_e32 v8, 31, v7
	v_cndmask_b32_e64 v4, v4, s12, s11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v5, v5, v4, 30
	v_alignbit_b32 v4, v4, s8, 30
	s_lshr_b32 s8, s2, 29
	s_lshl_b32 s8, s8, 31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v5, s13, v5
	v_xor_b32_e32 v4, s13, v4
	s_or_b32 s11, s8, 0.5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v9, s11, v9
	v_alignbit_b32 v6, v6, v5, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v4, v5, v4, v8
	v_alignbit_b32 v5, v6, v4, 9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v8, v5
	v_min_u32_e32 v8, 32, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v10, 31, v8
	v_alignbit_b32 v4, v5, v4, v10
	v_lshrrev_b32_e32 v5, 9, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v4, 9, v4
	v_or_b32_e32 v5, v5, v9
	v_add_nc_u32_e32 v7, v8, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v6, 23, v7
	v_sub_nc_u32_e32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v6, 0x3fc90fda, v5
	v_add_nc_u32_e32 v4, 0x33000000, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v7, 0x3fc90fda, v5, -v6
	v_or_b32_e32 v4, s8, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmamk_f32 v5, v5, 0x33a22168, v7
	s_lshr_b32 s8, s2, 30
	s_mov_b32 s2, 0
	s_add_i32 s3, s3, s8
	v_fmac_f32_e32 v5, 0x3fc90fda, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v4, v6, v5
	s_branch .LBB0_4
.LBB0_3:
	s_mov_b32 s2, -1
                                        ; implicit-def: $sgpr3
                                        ; implicit-def: $vgpr4
.LBB0_4:                                ; %Flow848
	v_mov_b32_e32 v5, s3
	v_mul_f32_e64 v6, 0x3f22f983, |s4|
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB0_6
; %bb.5:
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v5, v6
	v_fma_f32 v4, 0xbfc90fda, v5, |s4|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v4, v5, 0xb3a22168, v4
	v_fmamk_f32 v4, v5, 0xa7c234c4, v4
	v_cvt_i32_f32_e32 v5, v5
.LBB0_6:                                ; %_ZL4cosff.exit
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccz .LBB0_8
; %bb.7:
	s_and_b32 s1, s0, 0x7fffff
	s_lshr_b32 s2, s0, 23
	s_bitset1_b32 s1, 23
	s_addk_i32 s2, 0xff88
	s_mul_hi_u32 s3, s1, 0xfe5163ab
	s_mul_i32 s8, s1, 0x3c439041
	s_mul_hi_u32 s11, s1, 0x3c439041
	s_add_u32 s3, s3, s8
	s_addc_u32 s8, 0, s11
	s_mul_i32 s11, s1, 0xdb629599
	s_mul_hi_u32 s12, s1, 0xdb629599
	s_add_u32 s8, s8, s11
	s_addc_u32 s11, 0, s12
	s_mul_i32 s12, s1, 0xf534ddc0
	s_mul_hi_u32 s13, s1, 0xf534ddc0
	s_add_u32 s11, s11, s12
	s_addc_u32 s12, 0, s13
	s_mul_i32 s13, s1, 0xfc2757d1
	s_mul_hi_u32 s20, s1, 0xfc2757d1
	s_add_u32 s12, s12, s13
	s_addc_u32 s13, 0, s20
	s_mul_i32 s20, s1, 0x4e441529
	s_mul_hi_u32 s21, s1, 0x4e441529
	s_add_u32 s13, s13, s20
	s_addc_u32 s20, 0, s21
	s_cmp_gt_u32 s2, 63
	s_mul_i32 s21, s1, 0xfe5163ab
	s_mul_hi_u32 s22, s1, 0xa2f9836e
	s_mul_i32 s1, s1, 0xa2f9836e
	s_cselect_b32 s23, s8, s12
	s_cselect_b32 s3, s3, s11
	s_cselect_b32 s8, s21, s8
	s_add_u32 s1, s20, s1
	s_addc_u32 s20, 0, s22
	s_cmp_gt_u32 s2, 63
	s_cselect_b32 s21, 0xffffffc0, 0
	s_cselect_b32 s11, s11, s13
	s_cselect_b32 s1, s12, s1
	s_cselect_b32 s12, s13, s20
	s_add_i32 s21, s21, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s21, 31
	s_cselect_b32 s2, 0xffffffe0, 0
	s_cselect_b32 s13, s11, s1
	s_cselect_b32 s1, s1, s12
	s_cselect_b32 s11, s23, s11
	s_cselect_b32 s12, s3, s23
	s_cselect_b32 s3, s8, s3
	s_add_i32 s2, s2, s21
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_u32 s2, 31
	s_cselect_b32 s8, 0xffffffe0, 0
	s_cselect_b32 s1, s13, s1
	s_cselect_b32 s13, s11, s13
	s_cselect_b32 s11, s12, s11
	s_cselect_b32 s3, s3, s12
	s_add_i32 s8, s8, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_sub_i32 s2, 32, s8
	s_cmp_eq_u32 s8, 0
	v_mov_b32_e32 v7, s2
	s_cselect_b32 s8, -1, 0
	v_alignbit_b32 v8, s1, s13, v7
	v_alignbit_b32 v9, s13, s11, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s2, v8
	v_cndmask_b32_e64 v8, v9, s13, s8
	s_delay_alu instid0(VALU_DEP_2)
	s_cselect_b32 s1, s1, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v9, s1, v8, 30
	s_bfe_u32 s2, s1, 0x1001d
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s12, 0, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_xor_b32_e32 v9, s12, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v10, v9
	v_min_u32_e32 v10, 32, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v12, 23, v10
	v_alignbit_b32 v7, s11, s3, v7
	v_sub_nc_u32_e32 v11, 31, v10
	v_cndmask_b32_e64 v7, v7, s11, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_alignbit_b32 v8, v8, v7, 30
	v_alignbit_b32 v7, v7, s3, 30
	s_lshr_b32 s3, s1, 29
	s_lshl_b32 s3, s3, 31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v8, s12, v8
	v_xor_b32_e32 v7, s12, v7
	s_or_b32 s8, s3, 0.5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v12, s8, v12
	v_alignbit_b32 v9, v9, v8, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v7, v8, v7, v11
	v_alignbit_b32 v8, v9, v7, 9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v11, v8
	v_min_u32_e32 v11, 32, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v13, 31, v11
	v_alignbit_b32 v7, v8, v7, v13
	v_lshrrev_b32_e32 v8, 9, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshrrev_b32_e32 v7, 9, v7
	v_or_b32_e32 v8, v8, v12
	v_add_nc_u32_e32 v10, v11, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v9, 23, v10
	v_sub_nc_u32_e32 v7, v7, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v9, 0x3fc90fda, v8
	v_add_nc_u32_e32 v7, 0x33000000, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v10, 0x3fc90fda, v8, -v9
	v_or_b32_e32 v7, s3, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmamk_f32 v8, v8, 0x33a22168, v10
	s_lshr_b32 s3, s1, 30
	s_mov_b32 s1, 0
	s_add_i32 s2, s2, s3
	v_fmac_f32_e32 v8, 0x3fc90fda, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v7, v9, v8
	s_branch .LBB0_9
.LBB0_8:
	s_mov_b32 s1, -1
                                        ; implicit-def: $sgpr2
                                        ; implicit-def: $vgpr7
.LBB0_9:                                ; %Flow847
	v_mov_b32_e32 v8, s2
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_11
; %bb.10:
	v_rndne_f32_e32 v6, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v7, 0xbfc90fda, v6, |s4|
	v_cvt_i32_f32_e32 v8, v6
	v_fmamk_f32 v7, v6, 0xb3a22168, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_fmamk_f32 v7, v6, 0xa7c234c4, v7
.LBB0_11:                               ; %_ZL4sinff.exit
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v6, v4, v4 :: v_dual_mul_f32 v9, v7, v7
	s_mov_b32 s1, 0xb94c1982
	s_mov_b32 s2, 0x37d75334
	s_xor_b32 s0, s0, s4
	v_dual_fmaak_f32 v10, s1, v6, 0x3c0881c4 :: v_dual_fmaak_f32 v13, s1, v9, 0x3c0881c4
	v_dual_fmaak_f32 v11, s2, v6, 0xbab64f3b :: v_dual_and_b32 v12, 1, v5
	v_dual_fmaak_f32 v14, s2, v9, 0xbab64f3b :: v_dual_and_b32 v15, 1, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmaak_f32 v10, v6, v10, 0xbe2aaa9d :: v_dual_lshlrev_b32 v5, 30, v5
	v_dual_fmaak_f32 v11, v6, v11, 0x3d2aabf7 :: v_dual_fmaak_f32 v14, v9, v14, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmaak_f32 v13, v9, v13, 0xbe2aaa9d :: v_dual_mul_f32 v10, v6, v10
	v_cmp_eq_u32_e32 vcc_lo, 0, v12
	v_dual_fmaak_f32 v11, v6, v11, 0xbf000004 :: v_dual_fmaak_f32 v14, v9, v14, 0xbf000004
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v13, v9, v13 :: v_dual_fmac_f32 v4, v4, v10
	v_lshlrev_b32_e32 v8, 30, v8
	v_fma_f32 v6, v6, v11, 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v9, v9, v14, 1.0
	v_fmac_f32_e32 v7, v7, v13
	v_cvt_f32_i32_e32 v2, v2
	v_and_b32_e32 v5, 0x80000000, v5
	v_cndmask_b32_e64 v4, -v4, v6, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v15
	v_and_b32_e32 v6, 0x80000000, v8
	v_add_f32_e32 v2, s9, v2
	v_cvt_f32_i32_e32 v3, v3
	v_xor_b32_e32 v4, v5, v4
	v_cndmask_b32_e32 v7, v9, v7, vcc_lo
	v_xor_b32_e32 v6, s0, v6
	v_cmp_class_f32_e64 vcc_lo, s4, 0x1f8
	s_mov_b32 s0, exec_lo
	v_add_f32_e32 v3, s16, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v6, v6, v7
	v_mul_f32_e32 v3, s10, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v15, 0x7fc00000, v6, vcc_lo
	v_cndmask_b32_e32 v5, 0x7fc00000, v4, vcc_lo
	v_sub_f32_e64 v4, s6, s5
	v_mul_f32_e32 v6, s7, v2
	v_mul_f32_e32 v2, v4, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v2, v6, v5
	v_mul_f32_e32 v7, v6, v15
	v_mul_f32_e64 v6, v5, -s5
	v_fmac_f32_e32 v2, s5, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v4, v4, v5, -v7
	v_mul_f32_e64 v7, v15, -s5
	v_fmac_f32_e32 v4, s5, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e32 vcc_lo, 0, v4
	v_cndmask_b32_e64 v8, -v4, v4, vcc_lo
	v_cmp_lt_f32_e32 vcc_lo, 0, v2
	v_cndmask_b32_e64 v9, -v2, v2, vcc_lo
	v_cmpx_ngt_f32_e32 v8, v9
	s_xor_b32 s3, exec_lo, s0
	s_cbranch_execz .LBB0_60
; %bb.12:                               ; %.preheader747
	s_cmp_lt_i32 s18, 1
	s_cbranch_scc1 .LBB0_60
; %bb.13:                               ; %.lr.ph
	v_mul_f32_e64 v8, s7, 0.5
	v_fma_f32 v12, -0.5, s10, v3
	v_fmac_f32_e64 v3, s10, 0.5
	s_lshr_b32 s0, s18, 1
	s_lshr_b32 s1, s17, 31
	v_fma_f32 v10, -v8, v15, v4
	v_fma_f32 v11, v8, v5, v2
	v_fmac_f32_e32 v4, v8, v15
	v_fma_f32 v5, -v8, v5, v2
	v_div_scale_f32 v15, null, v2, v2, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_scale_f32 v13, null, v11, v11, v10
	v_div_scale_f32 v14, null, v5, v5, v4
	v_div_scale_f32 v18, null, v2, v2, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v16, v13
	v_rcp_f32_e32 v17, v14
	v_rcp_f32_e32 v19, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_rcp_f32_e32 v21, v18
	v_cvt_f32_i32_e32 v8, s0
	v_div_scale_f32 v20, vcc_lo, v10, v11, v10
	s_add_i32 s4, s17, s1
	s_ashr_i32 s4, s4, 1
	v_fma_f32 v9, -v13, v16, 1.0
	s_delay_alu instid0(TRANS32_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_fma_f32 v22, -v14, v17, 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v24, -v15, v19, 1.0
	v_dual_fmac_f32 v16, v9, v16 :: v_dual_fmac_f32 v17, v22, v17
	v_fmac_f32_e32 v19, v24, v19
	v_div_scale_f32 v23, s0, v4, v5, v4
	v_fma_f32 v9, -v18, v21, 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v25, v20, v16
	v_div_scale_f32 v22, s1, v12, v2, v12
	v_mul_f32_e32 v26, v23, v17
	v_div_scale_f32 v24, s2, v3, v2, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f32 v27, -v13, v25, v20
	v_fmac_f32_e32 v21, v9, v21
	v_fma_f32 v28, -v14, v26, v23
	v_mul_f32_e32 v29, v22, v19
	v_cvt_f32_i32_e32 v9, s4
	v_fmac_f32_e32 v25, v27, v16
	s_mov_b32 s4, 0
	v_fmac_f32_e32 v26, v28, v17
	v_mul_f32_e32 v28, v24, v21
	v_fma_f32 v27, -v15, v29, v22
	v_fma_f32 v13, -v13, v25, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v14, -v14, v26, v23
	v_fma_f32 v20, -v18, v28, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v29, v27, v19
	v_div_fmas_f32 v13, v13, v16, v25
	s_mov_b32 vcc_lo, s0
	s_lshr_b32 s0, s19, 31
	v_fmac_f32_e32 v28, v20, v21
	v_fma_f32 v15, -v15, v29, v22
	v_div_fixup_f32 v10, v13, v11, v10
	v_div_fmas_f32 v14, v14, v17, v26
	s_mov_b32 vcc_lo, s1
	v_fma_f32 v11, -v18, v28, v24
	v_div_fmas_f32 v13, v15, v19, v29
	s_mov_b32 vcc_lo, s2
	s_add_i32 s0, s19, s0
	s_delay_alu instid0(VALU_DEP_2)
	v_div_fmas_f32 v15, v11, v21, v28
	s_ashr_i32 s0, s0, 1
	v_div_fixup_f32 v11, v14, v5, v4
	v_div_fixup_f32 v12, v13, v2, v12
	v_cvt_f32_i32_e32 v13, s0
	v_div_fixup_f32 v14, v15, v2, v3
.LBB0_14:                               ; =>This Inner Loop Header: Depth=1
	v_cvt_f32_i32_e32 v2, s4
	s_mov_b32 s5, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v2, 0.5, v2
	v_sub_f32_e32 v2, v2, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v3, v2, v8
	v_fma_f32 v2, v10, v3, v6
	v_fma_f32 v4, v11, v3, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v20, v2, v9
	v_add_f32_e32 v2, v4, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v16, v2, v20
	v_cmp_lt_f32_e32 vcc_lo, 0, v16
	v_cndmask_b32_e64 v4, -v16, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ngt_f32_e32 0x3c23d70a, v4
	s_cbranch_execz .LBB0_59
; %bb.15:                               ;   in Loop: Header=BB0_14 Depth=1
	v_fma_f32 v4, v12, v3, 0
	v_fma_f32 v3, v14, v3, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v21, v4, v13
	v_add_f32_e32 v3, v3, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v19, v3, v21
	v_cmp_lt_f32_e32 vcc_lo, 0, v19
	v_cndmask_b32_e64 v4, -v19, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ngt_f32_e32 vcc_lo, 0x3c23d70a, v4
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_59
; %bb.16:                               ;   in Loop: Header=BB0_14 Depth=1
	v_floor_f32_e32 v4, v20
	v_floor_f32_e32 v2, v2
	v_floor_f32_e32 v5, v21
	s_waitcnt vmcnt(0)
	v_floor_f32_e32 v17, v3
	v_cvt_i32_f32_e32 v3, v4
	v_cvt_i32_f32_e32 v2, v2
	v_cvt_i32_f32_e32 v15, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_i32_f32_e32 v18, v17
                                        ; implicit-def: $vgpr4_vgpr5
                                        ; implicit-def: $vgpr17
	v_cmp_eq_u32_e64 s0, v3, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s1, v15, v18
	s_and_b32 s2, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_xor_b32 s6, s2, -1
	s_mov_b32 s2, 0
	s_and_saveexec_b32 s8, s6
	s_xor_b32 s6, exec_lo, s8
	s_cbranch_execz .LBB0_51
; %bb.17:                               ;   in Loop: Header=BB0_14 Depth=1
	v_max_i32_e32 v4, v3, v2
	s_xor_b32 s2, s0, -1
	s_mov_b32 s9, 0
	s_and_b32 s8, s2, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_xor_b32 s8, s8, -1
	v_cvt_f32_i32_e32 v4, v4
	v_sub_f32_e32 v4, v4, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v5, null, v16, v16, v4
	v_div_scale_f32 v22, vcc_lo, v4, v16, v4
	v_rcp_f32_e32 v17, v5
	s_waitcnt_depctr 0xfff
	v_fma_f32 v20, -v5, v17, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v17, v20, v17
	v_mul_f32_e32 v20, v22, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v23, -v5, v20, v22
	v_fmac_f32_e32 v20, v23, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v5, -v5, v20, v22
	v_div_fmas_f32 v5, v5, v17, v20
                                        ; implicit-def: $vgpr17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v20, v5, v16, v4
                                        ; implicit-def: $vgpr4_vgpr5
	v_sub_f32_e32 v16, 1.0, v20
	s_and_saveexec_b32 s11, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s8, exec_lo, s11
	s_cbranch_execz .LBB0_42
; %bb.18:                               ;   in Loop: Header=BB0_14 Depth=1
	v_max_i32_e32 v4, v15, v18
	s_or_b32 s2, s2, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_xor_b32 s9, s2, -1
	s_mov_b32 s2, 0
	v_cvt_f32_i32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v4, v4, v21
	v_div_scale_f32 v5, null, v19, v19, v4
	v_div_scale_f32 v22, vcc_lo, v4, v19, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v17, v5
	s_waitcnt_depctr 0xfff
	v_fma_f32 v21, -v5, v17, 1.0
	v_fmac_f32_e32 v17, v21, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v21, v22, v17
	v_fma_f32 v23, -v5, v21, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v21, v23, v17
	v_fma_f32 v5, -v5, v21, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v5, v5, v17, v21
                                        ; implicit-def: $vgpr17
	v_div_fixup_f32 v21, v5, v19, v4
                                        ; implicit-def: $vgpr4_vgpr5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_sub_f32_e32 v19, 1.0, v21
	s_and_saveexec_b32 s11, s9
	s_xor_b32 s9, exec_lo, s11
	s_cbranch_execz .LBB0_26
; %bb.19:                               ;   in Loop: Header=BB0_14 Depth=1
	v_cmp_gt_i32_e32 vcc_lo, s17, v3
	v_cmp_lt_i32_e64 s2, -1, v3
                                        ; implicit-def: $vgpr4_vgpr5
                                        ; implicit-def: $vgpr17
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s12, vcc_lo, s2
	s_mov_b32 s2, 0
	s_and_saveexec_b32 s11, s12
	s_cbranch_execz .LBB0_25
; %bb.20:                               ;   in Loop: Header=BB0_14 Depth=1
	v_cmp_gt_i32_e32 vcc_lo, s19, v15
	v_cmp_lt_i32_e64 s2, -1, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s12, vcc_lo, s2
	s_and_saveexec_b32 s2, s12
	s_cbranch_execz .LBB0_22
; %bb.21:                               ;   in Loop: Header=BB0_14 Depth=1
	v_mad_u64_u32 v[4:5], null, v15, s18, s[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[15:16], null, v4, s17, v[3:4]
	v_ashrrev_i32_e32 v16, 31, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[15:16]
	v_add_co_u32 v4, vcc_lo, s14, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s15, v5, vcc_lo
	global_load_b32 v2, v[4:5], off
	global_load_b32 v4, v[0:1], off
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v4, v21, v2
	global_store_b32 v[0:1], v4, off
.LBB0_22:                               ;   in Loop: Header=BB0_14 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	v_cmp_gt_i32_e32 vcc_lo, s19, v18
	v_cmp_lt_i32_e64 s2, -1, v18
                                        ; implicit-def: $vgpr17
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s13, vcc_lo, s2
	s_mov_b32 s2, 0
	s_and_saveexec_b32 s12, s13
	s_cbranch_execz .LBB0_24
; %bb.23:                               ;   in Loop: Header=BB0_14 Depth=1
	v_mad_u64_u32 v[4:5], null, v18, s18, s[4:5]
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[15:16], null, v4, s17, v[3:4]
	v_ashrrev_i32_e32 v16, 31, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[15:16]
	v_add_co_u32 v2, vcc_lo, s14, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s15, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v17, v19, v2
.LBB0_24:                               ; %Flow809
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_or_b32 exec_lo, exec_lo, s12
	v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
	s_and_b32 s2, s2, exec_lo
.LBB0_25:                               ; %Flow808
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s2, s2, exec_lo
                                        ; implicit-def: $vgpr2
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr3
                                        ; implicit-def: $vgpr15
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr20
.LBB0_26:                               ; %Flow807
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_and_not1_saveexec_b32 s9, s9
	s_cbranch_execz .LBB0_41
; %bb.27:                               ;   in Loop: Header=BB0_14 Depth=1
	s_or_b32 s0, s0, s1
                                        ; implicit-def: $vgpr4_vgpr5
                                        ; implicit-def: $vgpr17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s11, s0, -1
	s_mov_b32 s0, s2
	s_and_saveexec_b32 s1, s11
	s_cbranch_execz .LBB0_40
; %bb.28:                               ;   in Loop: Header=BB0_14 Depth=1
	v_cmp_gt_i32_e32 vcc_lo, s17, v3
	v_cmp_lt_i32_e64 s0, -1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s11, s0
	s_cbranch_execz .LBB0_33
; %bb.29:                               ;   in Loop: Header=BB0_14 Depth=1
	v_cmp_gt_i32_e32 vcc_lo, s19, v15
	v_cmp_lt_i32_e64 s0, -1, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s12, vcc_lo, s0
	s_and_saveexec_b32 s0, s12
	s_cbranch_execz .LBB0_31
; %bb.30:                               ;   in Loop: Header=BB0_14 Depth=1
	v_mad_u64_u32 v[4:5], null, v15, s18, s[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[22:23], null, v4, s17, v[3:4]
	v_ashrrev_i32_e32 v23, 31, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[22:23]
	v_add_co_u32 v4, vcc_lo, s14, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s15, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	global_load_b32 v5, v[0:1], off
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v4, v20, v4
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v5, v21, v4
	global_store_b32 v[0:1], v5, off
.LBB0_31:                               ;   in Loop: Header=BB0_14 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_gt_i32_e32 vcc_lo, s19, v18
	v_cmp_lt_i32_e64 s0, -1, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_33
; %bb.32:                               ;   in Loop: Header=BB0_14 Depth=1
	v_mad_u64_u32 v[4:5], null, v18, s18, s[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[22:23], null, v4, s17, v[3:4]
	v_ashrrev_i32_e32 v23, 31, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[22:23]
	v_add_co_u32 v3, vcc_lo, s14, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s15, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	global_load_b32 v4, v[0:1], off
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v3, v20, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v4, v19, v3
	global_store_b32 v[0:1], v4, off
.LBB0_33:                               ; %Flow804
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	v_cmp_gt_i32_e32 vcc_lo, s17, v2
	v_cmp_lt_i32_e64 s0, -1, v2
                                        ; implicit-def: $vgpr17
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s12, vcc_lo, s0
	s_mov_b32 s0, s2
	s_and_saveexec_b32 s11, s12
	s_cbranch_execz .LBB0_39
; %bb.34:                               ;   in Loop: Header=BB0_14 Depth=1
	v_cmp_gt_i32_e32 vcc_lo, s19, v15
	v_cmp_lt_i32_e64 s0, -1, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s12, vcc_lo, s0
	s_and_saveexec_b32 s0, s12
	s_cbranch_execz .LBB0_36
; %bb.35:                               ;   in Loop: Header=BB0_14 Depth=1
	v_mad_u64_u32 v[3:4], null, v15, s18, s[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v3, s17, v[2:3]
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[4:5]
	v_add_co_u32 v3, vcc_lo, s14, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s15, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	global_load_b32 v4, v[0:1], off
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v3, v16, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v4, v21, v3
	global_store_b32 v[0:1], v4, off
.LBB0_36:                               ;   in Loop: Header=BB0_14 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_gt_i32_e32 vcc_lo, s19, v18
	v_cmp_lt_i32_e64 s0, -1, v18
	s_mov_b32 s12, s2
                                        ; implicit-def: $vgpr17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s13, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s13
	s_cbranch_execz .LBB0_38
; %bb.37:                               ;   in Loop: Header=BB0_14 Depth=1
	v_mad_u64_u32 v[3:4], null, v18, s18, s[4:5]
	s_or_b32 s12, s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v3, s17, v[2:3]
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[4:5]
	v_add_co_u32 v2, vcc_lo, s14, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v3, vcc_lo, s15, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v2, v16, v2
	v_mul_f32_e32 v17, v19, v2
.LBB0_38:                               ; %Flow813
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s0, s2, exec_lo
	s_and_b32 s12, s12, exec_lo
	s_or_b32 s0, s0, s12
.LBB0_39:                               ; %Flow812
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
	s_and_not1_b32 s11, s2, exec_lo
	s_and_b32 s0, s0, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s0, s11, s0
.LBB0_40:                               ; %Flow811
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s1, s2, exec_lo
	s_and_b32 s0, s0, exec_lo
	s_or_b32 s2, s1, s0
.LBB0_41:                               ; %Flow810
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s9, s2, exec_lo
                                        ; implicit-def: $vgpr2
                                        ; implicit-def: $vgpr3
                                        ; implicit-def: $vgpr15
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr16
.LBB0_42:                               ; %Flow806
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_and_not1_saveexec_b32 s8, s8
	s_cbranch_execz .LBB0_50
; %bb.43:                               ;   in Loop: Header=BB0_14 Depth=1
	v_cmp_gt_i32_e32 vcc_lo, s17, v3
	v_cmp_lt_i32_e64 s0, -1, v3
	v_cmp_gt_i32_e64 s1, s19, v15
	v_cmp_lt_i32_e64 s2, -1, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_b32 s1, s1, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s0, s1
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_45
; %bb.44:                               ;   in Loop: Header=BB0_14 Depth=1
	v_mad_u64_u32 v[4:5], null, v15, s18, s[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[17:18], null, v4, s17, v[3:4]
	v_ashrrev_i32_e32 v18, 31, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[17:18]
	v_add_co_u32 v3, vcc_lo, s14, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s15, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	global_load_b32 v4, v[0:1], off
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v4, v20, v3
	global_store_b32 v[0:1], v4, off
.LBB0_45:                               ;   in Loop: Header=BB0_14 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_gt_i32_e32 vcc_lo, s17, v2
	v_cmp_lt_i32_e64 s0, -1, v2
                                        ; implicit-def: $vgpr17
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s2, vcc_lo, s0
	s_mov_b32 s0, s9
	s_and_saveexec_b32 s1, s2
	s_cbranch_execz .LBB0_49
; %bb.46:                               ;   in Loop: Header=BB0_14 Depth=1
	v_cmp_gt_i32_e32 vcc_lo, s19, v15
	v_cmp_lt_i32_e64 s0, -1, v15
	s_mov_b32 s2, s9
                                        ; implicit-def: $vgpr17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s11, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s11
	s_cbranch_execz .LBB0_48
; %bb.47:                               ;   in Loop: Header=BB0_14 Depth=1
	v_mad_u64_u32 v[3:4], null, v15, s18, s[4:5]
	s_or_b32 s2, s9, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v3, s17, v[2:3]
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[4:5]
	v_add_co_u32 v2, vcc_lo, s14, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s15, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v17, v16, v2
.LBB0_48:                               ; %Flow816
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s0, s9, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_or_b32 s0, s0, s2
.LBB0_49:                               ; %Flow815
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s1, s9, exec_lo
	s_and_b32 s0, s0, exec_lo
	v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
	s_or_b32 s9, s1, s0
.LBB0_50:                               ; %Flow814
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_or_b32 exec_lo, exec_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s2, s9, exec_lo
                                        ; implicit-def: $vgpr3
                                        ; implicit-def: $vgpr15
.LBB0_51:                               ; %Flow805
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_and_not1_saveexec_b32 s1, s6
	s_cbranch_execz .LBB0_57
; %bb.52:                               ;   in Loop: Header=BB0_14 Depth=1
	v_cmp_gt_i32_e32 vcc_lo, s17, v3
	v_cmp_lt_i32_e64 s0, -1, v3
                                        ; implicit-def: $vgpr4_vgpr5
                                        ; implicit-def: $vgpr17
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s8, vcc_lo, s0
	s_mov_b32 s0, s2
	s_and_saveexec_b32 s6, s8
	s_cbranch_execz .LBB0_56
; %bb.53:                               ;   in Loop: Header=BB0_14 Depth=1
	v_cmp_gt_i32_e32 vcc_lo, s19, v15
	v_cmp_lt_i32_e64 s0, -1, v15
	s_mov_b32 s8, s2
                                        ; implicit-def: $vgpr4_vgpr5
                                        ; implicit-def: $vgpr17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s9, vcc_lo, s0
	s_and_saveexec_b32 s0, s9
	s_cbranch_execz .LBB0_55
; %bb.54:                               ;   in Loop: Header=BB0_14 Depth=1
	global_load_b32 v17, v[0:1], off
	v_mad_u64_u32 v[4:5], null, v15, s18, s[4:5]
	s_or_b32 s8, s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[15:16], null, v4, s17, v[3:4]
	v_ashrrev_i32_e32 v16, 31, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[15:16]
	v_add_co_u32 v4, vcc_lo, s14, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s15, v3, vcc_lo
.LBB0_55:                               ; %Flow819
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s0, s2, exec_lo
	s_and_b32 s8, s8, exec_lo
	s_or_b32 s0, s0, s8
.LBB0_56:                               ; %Flow818
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s2, s2, exec_lo
	s_and_b32 s0, s0, exec_lo
	s_or_b32 s2, s2, s0
.LBB0_57:                               ; %Flow817
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB0_59
; %bb.58:                               ; %.critedge699.sink.split
                                        ;   in Loop: Header=BB0_14 Depth=1
	global_load_b32 v2, v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, v2, v17
	global_store_b32 v[0:1], v2, off
.LBB0_59:                               ; %.critedge699
                                        ;   in Loop: Header=BB0_14 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_add_i32 s4, s4, 1
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr2
                                        ; implicit-def: $vgpr15
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s18, s4
	s_cbranch_scc1 .LBB0_14
.LBB0_60:                               ; %Flow845
	s_and_not1_saveexec_b32 s0, s3
	s_cbranch_execz .LBB0_109
; %bb.61:                               ; %.preheader
	s_cmp_lt_i32 s17, 1
	s_cbranch_scc1 .LBB0_109
; %bb.62:                               ; %.lr.ph751
	v_mul_f32_e64 v8, s7, 0.5
	v_fma_f32 v12, -0.5, s10, v3
	v_fmac_f32_e64 v3, s10, 0.5
	s_lshr_b32 s1, s18, 31
	s_lshr_b32 s0, s17, 1
	v_fma_f32 v10, -v8, v5, v2
	v_fma_f32 v11, v8, v15, v4
	v_fmac_f32_e32 v2, v8, v5
	v_fma_f32 v5, -v8, v15, v4
	v_div_scale_f32 v15, null, v4, v4, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_scale_f32 v13, null, v11, v11, v10
	v_div_scale_f32 v14, null, v5, v5, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v19, v15
	v_rcp_f32_e32 v16, v13
	v_div_scale_f32 v18, null, v4, v4, v3
	s_waitcnt vmcnt(0)
	v_rcp_f32_e32 v17, v14
	s_add_i32 s3, s18, s1
	v_cvt_f32_i32_e32 v8, s0
	v_rcp_f32_e32 v21, v18
	v_div_scale_f32 v20, vcc_lo, v10, v11, v10
	v_fma_f32 v24, -v15, v19, 1.0
	s_delay_alu instid0(TRANS32_DEP_3)
	v_fma_f32 v9, -v13, v16, 1.0
	s_ashr_i32 s3, s3, 1
	s_mov_b32 s4, 0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v22, -v14, v17, 1.0
	v_dual_fmac_f32 v19, v24, v19 :: v_dual_fmac_f32 v16, v9, v16
	v_fma_f32 v9, -v18, v21, 1.0
	v_div_scale_f32 v24, s2, v3, v4, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v17, v22, v17
	v_div_scale_f32 v22, s1, v12, v4, v12
	v_fmac_f32_e32 v21, v9, v21
	v_cvt_f32_i32_e32 v9, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v29, v22, v19
	v_div_scale_f32 v23, s0, v2, v5, v2
	v_dual_mul_f32 v25, v20, v16 :: v_dual_mul_f32 v26, v23, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v27, -v13, v25, v20
	v_fma_f32 v28, -v14, v26, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v25, v27, v16
	v_fma_f32 v27, -v15, v29, v22
	v_fmac_f32_e32 v26, v28, v17
	v_mul_f32_e32 v28, v24, v21
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v13, -v13, v25, v20
	v_fmac_f32_e32 v29, v27, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v14, -v14, v26, v23
	v_fma_f32 v20, -v18, v28, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_fmas_f32 v13, v13, v16, v25
	v_fma_f32 v15, -v15, v29, v22
	s_mov_b32 vcc_lo, s0
	s_lshr_b32 s0, s19, 31
	v_fmac_f32_e32 v28, v20, v21
	v_div_fixup_f32 v10, v13, v11, v10
	v_div_fmas_f32 v14, v14, v17, v26
	s_mov_b32 vcc_lo, s1
	s_add_i32 s0, s19, s0
	v_fma_f32 v11, -v18, v28, v24
	v_div_fmas_f32 v13, v15, v19, v29
	s_mov_b32 vcc_lo, s2
	s_ashr_i32 s0, s0, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_div_fmas_f32 v15, v11, v21, v28
	v_div_fixup_f32 v11, v14, v5, v2
	v_div_fixup_f32 v12, v13, v4, v12
	v_cvt_f32_i32_e32 v13, s0
	v_div_fixup_f32 v14, v15, v4, v3
.LBB0_63:                               ; =>This Inner Loop Header: Depth=1
	v_cvt_f32_i32_e32 v2, s4
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v2, 0.5, v2
	v_sub_f32_e32 v2, v2, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v3, v2, v8
	v_fma_f32 v2, v10, v3, v7
	v_fma_f32 v4, v11, v3, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v20, v2, v9
	v_add_f32_e32 v2, v4, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v16, v2, v20
	v_cmp_lt_f32_e32 vcc_lo, 0, v16
	v_cndmask_b32_e64 v4, -v16, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ngt_f32_e32 0x3c23d70a, v4
	s_cbranch_execz .LBB0_108
; %bb.64:                               ;   in Loop: Header=BB0_63 Depth=1
	v_fma_f32 v4, v12, v3, 0
	v_fma_f32 v3, v14, v3, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v21, v4, v13
	v_add_f32_e32 v3, v3, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v19, v3, v21
	v_cmp_lt_f32_e32 vcc_lo, 0, v19
	v_cndmask_b32_e64 v4, -v19, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ngt_f32_e32 vcc_lo, 0x3c23d70a, v4
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_108
; %bb.65:                               ;   in Loop: Header=BB0_63 Depth=1
	v_floor_f32_e32 v4, v20
	v_floor_f32_e32 v2, v2
	v_floor_f32_e32 v5, v21
	s_waitcnt vmcnt(0)
	v_floor_f32_e32 v17, v3
	v_cvt_i32_f32_e32 v3, v4
	v_cvt_i32_f32_e32 v2, v2
	v_cvt_i32_f32_e32 v15, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_i32_f32_e32 v18, v17
                                        ; implicit-def: $vgpr4_vgpr5
                                        ; implicit-def: $vgpr17
	v_cmp_eq_u32_e64 s0, v3, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s1, v15, v18
	s_and_b32 s2, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_xor_b32 s5, s2, -1
	s_mov_b32 s2, 0
	s_and_saveexec_b32 s6, s5
	s_xor_b32 s5, exec_lo, s6
	s_cbranch_execz .LBB0_100
; %bb.66:                               ;   in Loop: Header=BB0_63 Depth=1
	v_max_i32_e32 v4, v3, v2
	s_xor_b32 s2, s0, -1
	s_mov_b32 s7, 0
	s_and_b32 s6, s2, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_xor_b32 s6, s6, -1
	v_cvt_f32_i32_e32 v4, v4
	v_sub_f32_e32 v4, v4, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v5, null, v16, v16, v4
	v_div_scale_f32 v22, vcc_lo, v4, v16, v4
	v_rcp_f32_e32 v17, v5
	s_waitcnt_depctr 0xfff
	v_fma_f32 v20, -v5, v17, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v17, v20, v17
	v_mul_f32_e32 v20, v22, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v23, -v5, v20, v22
	v_fmac_f32_e32 v20, v23, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v5, -v5, v20, v22
	v_div_fmas_f32 v5, v5, v17, v20
                                        ; implicit-def: $vgpr17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v20, v5, v16, v4
                                        ; implicit-def: $vgpr4_vgpr5
	v_sub_f32_e32 v16, 1.0, v20
	s_and_saveexec_b32 s8, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s6, exec_lo, s8
	s_cbranch_execz .LBB0_91
; %bb.67:                               ;   in Loop: Header=BB0_63 Depth=1
	v_max_i32_e32 v4, v15, v18
	s_or_b32 s2, s2, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_xor_b32 s7, s2, -1
	s_mov_b32 s2, 0
	v_cvt_f32_i32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v4, v4, v21
	v_div_scale_f32 v5, null, v19, v19, v4
	v_div_scale_f32 v22, vcc_lo, v4, v19, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v17, v5
	s_waitcnt_depctr 0xfff
	v_fma_f32 v21, -v5, v17, 1.0
	v_fmac_f32_e32 v17, v21, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v21, v22, v17
	v_fma_f32 v23, -v5, v21, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v21, v23, v17
	v_fma_f32 v5, -v5, v21, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v5, v5, v17, v21
                                        ; implicit-def: $vgpr17
	v_div_fixup_f32 v21, v5, v19, v4
                                        ; implicit-def: $vgpr4_vgpr5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_sub_f32_e32 v19, 1.0, v21
	s_and_saveexec_b32 s8, s7
	s_xor_b32 s7, exec_lo, s8
	s_cbranch_execz .LBB0_75
; %bb.68:                               ;   in Loop: Header=BB0_63 Depth=1
	v_cmp_gt_i32_e32 vcc_lo, s18, v3
	v_cmp_lt_i32_e64 s2, -1, v3
                                        ; implicit-def: $vgpr4_vgpr5
                                        ; implicit-def: $vgpr17
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s9, vcc_lo, s2
	s_mov_b32 s2, 0
	s_and_saveexec_b32 s8, s9
	s_cbranch_execz .LBB0_74
; %bb.69:                               ;   in Loop: Header=BB0_63 Depth=1
	v_cmp_gt_i32_e32 vcc_lo, s19, v15
	v_cmp_lt_i32_e64 s2, -1, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s9, vcc_lo, s2
	s_and_saveexec_b32 s2, s9
	s_cbranch_execz .LBB0_71
; %bb.70:                               ;   in Loop: Header=BB0_63 Depth=1
	v_mad_u64_u32 v[4:5], null, v15, s18, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[15:16], null, v4, s17, s[4:5]
	v_ashrrev_i32_e32 v16, 31, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[15:16]
	v_add_co_u32 v4, vcc_lo, s14, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s15, v5, vcc_lo
	global_load_b32 v2, v[4:5], off
	global_load_b32 v4, v[0:1], off
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v4, v21, v2
	global_store_b32 v[0:1], v4, off
.LBB0_71:                               ;   in Loop: Header=BB0_63 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	v_cmp_gt_i32_e32 vcc_lo, s19, v18
	v_cmp_lt_i32_e64 s2, -1, v18
                                        ; implicit-def: $vgpr17
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s10, vcc_lo, s2
	s_mov_b32 s2, 0
	s_and_saveexec_b32 s9, s10
	s_cbranch_execz .LBB0_73
; %bb.72:                               ;   in Loop: Header=BB0_63 Depth=1
	v_mad_u64_u32 v[4:5], null, v18, s18, v[3:4]
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, v4, s17, s[4:5]
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v2, vcc_lo, s14, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s15, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v17, v19, v2
.LBB0_73:                               ; %Flow830
                                        ;   in Loop: Header=BB0_63 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
	s_and_b32 s2, s2, exec_lo
.LBB0_74:                               ; %Flow829
                                        ;   in Loop: Header=BB0_63 Depth=1
	s_or_b32 exec_lo, exec_lo, s8
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s2, s2, exec_lo
                                        ; implicit-def: $vgpr2
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $vgpr16
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr3
                                        ; implicit-def: $vgpr15
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr20
.LBB0_75:                               ; %Flow828
                                        ;   in Loop: Header=BB0_63 Depth=1
	s_and_not1_saveexec_b32 s7, s7
	s_cbranch_execz .LBB0_90
; %bb.76:                               ;   in Loop: Header=BB0_63 Depth=1
	s_or_b32 s0, s0, s1
                                        ; implicit-def: $vgpr4_vgpr5
                                        ; implicit-def: $vgpr17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s8, s0, -1
	s_mov_b32 s0, s2
	s_and_saveexec_b32 s1, s8
	s_cbranch_execz .LBB0_89
; %bb.77:                               ;   in Loop: Header=BB0_63 Depth=1
	v_cmp_gt_i32_e32 vcc_lo, s18, v3
	v_cmp_lt_i32_e64 s0, -1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s8, s0
	s_cbranch_execz .LBB0_82
; %bb.78:                               ;   in Loop: Header=BB0_63 Depth=1
	v_cmp_gt_i32_e32 vcc_lo, s19, v15
	v_cmp_lt_i32_e64 s0, -1, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s9, vcc_lo, s0
	s_and_saveexec_b32 s0, s9
	s_cbranch_execz .LBB0_80
; %bb.79:                               ;   in Loop: Header=BB0_63 Depth=1
	v_mad_u64_u32 v[4:5], null, v15, s18, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[22:23], null, v4, s17, s[4:5]
	v_ashrrev_i32_e32 v23, 31, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[22:23]
	v_add_co_u32 v4, vcc_lo, s14, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s15, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	global_load_b32 v5, v[0:1], off
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v4, v20, v4
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v5, v21, v4
	global_store_b32 v[0:1], v5, off
.LBB0_80:                               ;   in Loop: Header=BB0_63 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_gt_i32_e32 vcc_lo, s19, v18
	v_cmp_lt_i32_e64 s0, -1, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_82
; %bb.81:                               ;   in Loop: Header=BB0_63 Depth=1
	v_mad_u64_u32 v[4:5], null, v18, s18, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[22:23], null, v4, s17, s[4:5]
	v_ashrrev_i32_e32 v23, 31, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[22:23]
	v_add_co_u32 v3, vcc_lo, s14, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s15, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	global_load_b32 v4, v[0:1], off
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v3, v20, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v4, v19, v3
	global_store_b32 v[0:1], v4, off
.LBB0_82:                               ; %Flow825
                                        ;   in Loop: Header=BB0_63 Depth=1
	s_or_b32 exec_lo, exec_lo, s8
	v_cmp_gt_i32_e32 vcc_lo, s18, v2
	v_cmp_lt_i32_e64 s0, -1, v2
                                        ; implicit-def: $vgpr17
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s9, vcc_lo, s0
	s_mov_b32 s0, s2
	s_and_saveexec_b32 s8, s9
	s_cbranch_execz .LBB0_88
; %bb.83:                               ;   in Loop: Header=BB0_63 Depth=1
	v_cmp_gt_i32_e32 vcc_lo, s19, v15
	v_cmp_lt_i32_e64 s0, -1, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s9, vcc_lo, s0
	s_and_saveexec_b32 s0, s9
	s_cbranch_execz .LBB0_85
; %bb.84:                               ;   in Loop: Header=BB0_63 Depth=1
	v_mad_u64_u32 v[3:4], null, v15, s18, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v3, s17, s[4:5]
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[4:5]
	v_add_co_u32 v3, vcc_lo, s14, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s15, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	global_load_b32 v4, v[0:1], off
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v3, v16, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v4, v21, v3
	global_store_b32 v[0:1], v4, off
.LBB0_85:                               ;   in Loop: Header=BB0_63 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_gt_i32_e32 vcc_lo, s19, v18
	v_cmp_lt_i32_e64 s0, -1, v18
	s_mov_b32 s9, s2
                                        ; implicit-def: $vgpr17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s10, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s10
	s_cbranch_execz .LBB0_87
; %bb.86:                               ;   in Loop: Header=BB0_63 Depth=1
	v_mad_u64_u32 v[3:4], null, v18, s18, v[2:3]
	s_or_b32 s9, s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v3, s17, s[4:5]
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[4:5]
	v_add_co_u32 v2, vcc_lo, s14, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v3, vcc_lo, s15, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v2, v16, v2
	v_mul_f32_e32 v17, v19, v2
.LBB0_87:                               ; %Flow834
                                        ;   in Loop: Header=BB0_63 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s0, s2, exec_lo
	s_and_b32 s9, s9, exec_lo
	s_or_b32 s0, s0, s9
.LBB0_88:                               ; %Flow833
                                        ;   in Loop: Header=BB0_63 Depth=1
	s_or_b32 exec_lo, exec_lo, s8
	v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
	s_and_not1_b32 s8, s2, exec_lo
	s_and_b32 s0, s0, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s0, s8, s0
.LBB0_89:                               ; %Flow832
                                        ;   in Loop: Header=BB0_63 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s1, s2, exec_lo
	s_and_b32 s0, s0, exec_lo
	s_or_b32 s2, s1, s0
.LBB0_90:                               ; %Flow831
                                        ;   in Loop: Header=BB0_63 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s7, s2, exec_lo
                                        ; implicit-def: $vgpr2
                                        ; implicit-def: $vgpr3
                                        ; implicit-def: $vgpr15
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr16
.LBB0_91:                               ; %Flow827
                                        ;   in Loop: Header=BB0_63 Depth=1
	s_and_not1_saveexec_b32 s6, s6
	s_cbranch_execz .LBB0_99
; %bb.92:                               ;   in Loop: Header=BB0_63 Depth=1
	v_cmp_gt_i32_e32 vcc_lo, s18, v3
	v_cmp_lt_i32_e64 s0, -1, v3
	v_cmp_gt_i32_e64 s1, s19, v15
	v_cmp_lt_i32_e64 s2, -1, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_b32 s1, s1, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s0, s1
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_94
; %bb.93:                               ;   in Loop: Header=BB0_63 Depth=1
	v_mad_u64_u32 v[4:5], null, v15, s18, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[17:18], null, v4, s17, s[4:5]
	v_ashrrev_i32_e32 v18, 31, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[17:18]
	v_add_co_u32 v3, vcc_lo, s14, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s15, v4, vcc_lo
	global_load_b32 v3, v[3:4], off
	global_load_b32 v4, v[0:1], off
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v4, v20, v3
	global_store_b32 v[0:1], v4, off
.LBB0_94:                               ;   in Loop: Header=BB0_63 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_gt_i32_e32 vcc_lo, s18, v2
	v_cmp_lt_i32_e64 s0, -1, v2
                                        ; implicit-def: $vgpr17
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s2, vcc_lo, s0
	s_mov_b32 s0, s7
	s_and_saveexec_b32 s1, s2
	s_cbranch_execz .LBB0_98
; %bb.95:                               ;   in Loop: Header=BB0_63 Depth=1
	v_cmp_gt_i32_e32 vcc_lo, s19, v15
	v_cmp_lt_i32_e64 s0, -1, v15
	s_mov_b32 s2, s7
                                        ; implicit-def: $vgpr17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s0, vcc_lo, s0
	s_and_saveexec_b32 s8, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s8
	s_cbranch_execz .LBB0_97
; %bb.96:                               ;   in Loop: Header=BB0_63 Depth=1
	v_mad_u64_u32 v[3:4], null, v15, s18, v[2:3]
	s_or_b32 s2, s7, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v3, s17, s[4:5]
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[4:5]
	v_add_co_u32 v2, vcc_lo, s14, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s15, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v17, v16, v2
.LBB0_97:                               ; %Flow837
                                        ;   in Loop: Header=BB0_63 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s0, s7, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_or_b32 s0, s0, s2
.LBB0_98:                               ; %Flow836
                                        ;   in Loop: Header=BB0_63 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s1, s7, exec_lo
	s_and_b32 s0, s0, exec_lo
	v_dual_mov_b32 v5, v1 :: v_dual_mov_b32 v4, v0
	s_or_b32 s7, s1, s0
.LBB0_99:                               ; %Flow835
                                        ;   in Loop: Header=BB0_63 Depth=1
	s_or_b32 exec_lo, exec_lo, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s2, s7, exec_lo
                                        ; implicit-def: $vgpr3
                                        ; implicit-def: $vgpr15
.LBB0_100:                              ; %Flow826
                                        ;   in Loop: Header=BB0_63 Depth=1
	s_and_not1_saveexec_b32 s1, s5
	s_cbranch_execz .LBB0_106
; %bb.101:                              ;   in Loop: Header=BB0_63 Depth=1
	v_cmp_gt_i32_e32 vcc_lo, s18, v3
	v_cmp_lt_i32_e64 s0, -1, v3
                                        ; implicit-def: $vgpr4_vgpr5
                                        ; implicit-def: $vgpr17
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s6, vcc_lo, s0
	s_mov_b32 s0, s2
	s_and_saveexec_b32 s5, s6
	s_cbranch_execz .LBB0_105
; %bb.102:                              ;   in Loop: Header=BB0_63 Depth=1
	v_cmp_gt_i32_e32 vcc_lo, s19, v15
	v_cmp_lt_i32_e64 s0, -1, v15
	s_mov_b32 s6, s2
                                        ; implicit-def: $vgpr4_vgpr5
                                        ; implicit-def: $vgpr17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s7, vcc_lo, s0
	s_and_saveexec_b32 s0, s7
	s_cbranch_execz .LBB0_104
; %bb.103:                              ;   in Loop: Header=BB0_63 Depth=1
	global_load_b32 v17, v[0:1], off
	v_mad_u64_u32 v[4:5], null, v15, s18, v[3:4]
	s_or_b32 s6, s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, v4, s17, s[4:5]
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v4, vcc_lo, s14, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s15, v3, vcc_lo
.LBB0_104:                              ; %Flow840
                                        ;   in Loop: Header=BB0_63 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s0, s2, exec_lo
	s_and_b32 s6, s6, exec_lo
	s_or_b32 s0, s0, s6
.LBB0_105:                              ; %Flow839
                                        ;   in Loop: Header=BB0_63 Depth=1
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s2, s2, exec_lo
	s_and_b32 s0, s0, exec_lo
	s_or_b32 s2, s2, s0
.LBB0_106:                              ; %Flow838
                                        ;   in Loop: Header=BB0_63 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s2
	s_cbranch_execz .LBB0_108
; %bb.107:                              ; %.critedge.sink.split
                                        ;   in Loop: Header=BB0_63 Depth=1
	global_load_b32 v2, v[4:5], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, v2, v17
	global_store_b32 v[0:1], v2, off
.LBB0_108:                              ; %.critedge
                                        ;   in Loop: Header=BB0_63 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_add_i32 s4, s4, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s17, s4
	s_cbranch_scc0 .LBB0_63
.LBB0_109:                              ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17kernel_projectionPfS_ffffiffifiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 64
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 30
		.amdhsa_next_free_sgpr 25
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z17kernel_projectionPfS_ffffiffifiii, .Lfunc_end0-_Z17kernel_projectionPfS_ffffiffifiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 7108
; NumSgprs: 27
; NumVgprs: 30
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 27
; NumVGPRsForWavesPerEU: 30
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         60
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 64
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z17kernel_projectionPfS_ffffiffifiii
    .private_segment_fixed_size: 0
    .sgpr_count:     27
    .sgpr_spill_count: 0
    .symbol:         _Z17kernel_projectionPfS_ffffiffifiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     30
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
