#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <ctime>


//Function that verify cuda calls and return cuda error if any
#define gpuCheck(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(cudaError_t code, const char *file, int line, bool abort=true)
{
   if (code != cudaSuccess)
   {
      fprintf(stderr,"GPUassert: %s %s %d\n", cudaGetErrorString(code), file, line);
      if (abort) exit(code);
   }
}

//Initialise ascendant array with random values in
void init_array(int* array, int size, int const adder=10)
{
    array[0] = rand()%adder;
    for(int i = 0; i < size;i++)
    {
        array[i] = array[i-1] + rand()%adder;
    }
}

//Function that initialise array with random values
void init_array_no_order(int* array, int size, int const adder=10)
{
    array[0] = rand()%adder;
    for(int i = 0; i < size;i++)
    {
        array[i] = rand()%adder;
    }
}

//Function that copy array in another
void copy_array(int* a, int* a_copy, int n){
    for(int i = 0;i < n;i++){
        a_copy[i] = a[i];
    }
}

//Function that print an array of size size
void print_array(int* a, int size)
{
    printf("[");
    for(int i = 0; i < size;i++)
    {
        //printf("i = %d | v = %d " ,i, a[i]);
        printf("%d " ,a[i]);
    }
    printf("]\n");
}

//Globall version of parallel merge of a and b in m with |m|<1024
__global__ void mergeSmall_k(int* d_a, int* d_b, int* d_m, int n_a, int n_b, int n_m){
    int i = threadIdx.x;
    if(i < n_m)
    {
        int2 K;
        int2 P;
        int2 Q;
        if(i > n_a)
        {
            K.x = i - n_a;
            K.y = n_a;
            P.x = n_a;
            P.y = i - n_a;
        }
        else
        {
            K.x = 0;
            K.y = i;
            P.x = i;
            P.y = 0;
        }

        int offset = 0;
        while(1)
        {
            offset = abs(K.y - P.y)/2;
            Q.x = K.x + offset;
            Q.y = K.y - offset;
            if(Q.y >= 0 && Q.x <= n_b && (Q.y == n_a || Q.x == 0 || d_a[Q.y] > d_b[Q.x - 1]))
            {
                if(Q.x == n_b || Q.y == 0 || d_a[Q.y - 1] <= d_b[Q.x])
                {
                    if(Q.y < n_a && (Q.x == n_b || d_a[Q.y] <= d_b[Q.x]))
                    {
                        d_m[i] = d_a[Q.y];
                    }
                    else
                    {
                        d_m[i] = d_b[Q.x];
                    }
                    break;
                }
                else
                {
                    K.x = Q.x + 1;
                    K.y = Q.y - 1;
                }
            }
            else
            {
              P.x = Q.x - 1;
              P.y = Q.y + 1;

            }

        }
    }
}

//Device version of parallel merge of a and b in m with |m|<1024
__device__ void mergeParallel(int* d_a, int* d_b, int* d_m, int n_a, int n_b, int n_m){
    int i = threadIdx.x;
    if(i < n_m)
    {
        int2 K;
        int2 P;
        int2 Q;
        if(i > n_a)
        {
            K.x = i - n_a;
            K.y = n_a;
            P.x = n_a;
            P.y = i - n_a;
        }
        else
        {
            K.x = 0;
            K.y = i;
            P.x = i;
            P.y = 0;
        }

        int offset = 0;
        while(1)
        {
            offset = abs(K.y - P.y)/2;
            Q.x = K.x + offset;
            Q.y = K.y - offset;
            if(Q.y >= 0 && Q.x <= n_b && (Q.y == n_a || Q.x == 0 || d_a[Q.y] > d_b[Q.x - 1]))
            {
                if(Q.x == n_b || Q.y == 0 || d_a[Q.y - 1] <= d_b[Q.x])
                {
                    if(Q.y < n_a && (Q.x == n_b || d_a[Q.y] <= d_b[Q.x]))
                    {
                        d_m[i] = d_a[Q.y];
                    }
                    else
                    {
                        d_m[i] = d_b[Q.x];
                    }
                    break;
                }
                else
                {
                    K.x = Q.x + 1;
                    K.y = Q.y - 1;
                }
            }
            else
            {
              P.x = Q.x - 1;
              P.y = Q.y + 1;

            }

        }
    }
}

//Giving a path ( from pathBig_k ) each block merge (with mergeParallel) each piece a_k and b_k in m_k of a and b. Then it replace elements in m
__global__ void mergeBig_k(int *m, int n_m, int *a, int n_a, int *b, int n_b, int2 *path, int n_path, int nbPartitions)
{
  int blockId = blockIdx.x;
  int threadId = threadIdx.x;
  int i = blockId * blockDim.x + threadId;
  if (blockId <= nbPartitions)//On utilise un block pour chaque partition
  {
    int x0, y0, x1, y1;
    x0 = path[blockId].x;
    y0 = path[blockId].y;
    x1 = path[blockId+1].x;
    y1 = path[blockId+1].y;

    const int dimx=x1-x0;
    const int dimy = y1-y0;

    //A modifier par dimx dimy dimx+dimy
     __shared__ int a_k[1024];
     __shared__ int b_k[1024];
     __shared__ int m_k[1024];

    if (threadId < dimx) //On rempli a_k[i] :  0 <= i < dimx
    {
      a_k[threadId] = a[x0+threadId];
    }
    else if (threadId < dimy+dimx)//On rempli b_k[i] : indice dimx <= i < dimx+dimy+1
    {
      b_k[threadId-dimx] = b[y0+threadId-dimx];
    }
    __syncthreads();
    mergeParallel(a_k, b_k, m_k, dimx, dimy, dimx+dimy);
    m[i] = m_k[threadId];

  }
}

//Function that generate a path to break down m into pieces that could be merge without conflict
//On appelle |m|/TPB blocks avec chacun un seul thread. Chaque thread s'occupe de la diagonale thread
__global__ void pathBig_k(int pas, int2* path, int n_path , int* d_a, int n_a ,int* d_b, int n_b)
{
    int thread_i = blockIdx.x * blockDim.x + threadIdx.x;
    if(thread_i <= (n_a + n_b)/pas)        //<------------//On vérifie que l'indice du thread est inférieur à la taille du tableau de retour et qu'il est un multiple du pas
    {
        int i = thread_i*pas;
        int2 K;
        int2 P;
        int2 Q;
        if(i > n_a)
        {
            K.x = i - n_a;
            K.y = n_a;
            P.x = n_a;
            P.y = i - n_a;
        }
        else
        {
            K.x = 0;
            K.y = i;
            P.x = i;
            P.y = 0;
        }

        int offset = 0;
        while(1)
        {
            //Calcul des coordonnées du milieu de P et K
            offset = abs(K.y - P.y)/2;
            Q.x = K.x + offset;
            Q.y = K.y - offset;

            //
            if(Q.y >= 0 && Q.x <= n_b && (Q.y == n_a || Q.x == 0 || d_a[Q.y] > d_b[Q.x - 1]))
            {
                //
                if(Q.x == n_b || Q.y == 0 || d_a[Q.y - 1] <= d_b[Q.x])
                {
                  break;
                }
                else
                {
                    K.x = Q.x + 1;
                    K.y = Q.y - 1;
                }
            }
            else
            {
              P.x = Q.x - 1;
              P.y = Q.y + 1;

            }

        }
        //printf("thread : %d => (%d, %d)\n", thread_i, Q.y, Q.x);
        //!\\ Problème ordre x et y
        path[thread_i].x=Q.y;
        path[thread_i].y=Q.x;
    }
    //Si |m| n'est pas un mutliple de pas, le thread 0 ajoute (n_a, n_b) à la fin du tableau
    if (thread_i==0 && (n_a+n_b)%pas!=0)
    {
      //printf("thread : %d => (%d, %d)\n", thread_i, n_a, n_b);
      path[n_path-1].x=n_a;
      path[n_path-1].y=n_b;
    }

}

//Function that decide wether to use mergeSmall_k or mergeBig_k giving the size of the pieces
void mergeAll(int* m, int n_m, int* a, int n_a, int* b, int n_b){
    int pas = 1024; // <1024
    int nbPartitions = n_m/pas+(n_m%pas!=0); // On ajoute 1 si n_m n'est pas un mutliple de p
    int n_path = (1 + nbPartitions); //1(pour (0,0)) + |m|/pas(nbr de morceau de taille pas) + 1(si dernier morceau de taille < pas))

    // printf("n_m : %d\nn_a : %d\nn_b : %d\n", n_m, n_a, n_b);
    int *mGPU, *aGPU, *bGPU;
    gpuCheck(cudaMalloc(&mGPU, n_m*sizeof(int)));
    gpuCheck(cudaMalloc(&aGPU, n_a*sizeof(int)));
    gpuCheck(cudaMalloc(&bGPU, n_b*sizeof(int)));

    //Declaration et allocation de path
    int2 *pathGPU;
    gpuCheck(cudaMalloc(&pathGPU, n_path*sizeof(int2)));

    gpuCheck(cudaMemcpy(aGPU, a, n_a*sizeof(int), cudaMemcpyHostToDevice));
    gpuCheck(cudaMemcpy(bGPU, b, n_b*sizeof(int), cudaMemcpyHostToDevice));

    // printf("n_12 : %d, n_1 : %d, n_2 : %d\n", n_m, n_a, n_b);
    if(n_m <= 1024){
        // printf("case mergeSmall\n");
        // printf("n_m = %d, n_a = %d, n_b = %d\n", n_a, n_b, n_m);
        mergeSmall_k<<<1, 1024>>>(aGPU, bGPU, mGPU, n_a, n_b, n_m);
        gpuCheck( cudaPeekAtLastError() );
        //gpuCheck(cudaDeviceSynchronize());
        gpuCheck(cudaMemcpy(m, mGPU, n_m*sizeof(int), cudaMemcpyDeviceToHost));
    }
    else{
        //================ Parallel : =======================\\
        // printf("\n");
        // printf("case mergeBig\n");
        pathBig_k<<<nbPartitions/1024+1, 1024>>>(pas, pathGPU, n_path, aGPU, n_a, bGPU, n_b);
        gpuCheck( cudaPeekAtLastError() );
        gpuCheck( cudaDeviceSynchronize() );
        mergeBig_k<<<nbPartitions, pas>>>(mGPU, n_m, aGPU, n_a, bGPU, n_b, pathGPU, n_path, nbPartitions);
        gpuCheck( cudaDeviceSynchronize() );

        gpuCheck(cudaMemcpy(m, mGPU, n_m*sizeof(int), cudaMemcpyDeviceToHost));

        gpuCheck( cudaDeviceSynchronize() );
    }
    gpuCheck(cudaFree(aGPU));
    gpuCheck(cudaFree(bGPU));
    gpuCheck(cudaFree(pathGPU));
}

//Fonction de prétraitement qui trie chaque paire contigüe d'éléments d'un tableau m
__global__ void pretraitementFusionSort(int* m, int* mGPU, int n){
    int blockId = blockIdx.x;
    int threadId = threadIdx.x;
    int i = blockId * blockDim.x + threadId;
    int tmp;
    if(i < n/2)
    {
        int indice = 2*i;
        if(mGPU[indice] > mGPU[indice+1])
        {
            tmp = mGPU[indice];
            mGPU[indice] = mGPU[indice+1];
            mGPU[indice+1] = tmp;
        }
    }
}


//Function that sort any array
void fusionSort(int *m, int n_m)
{
  //L1 : indice du premier élément de m_part1
  //R1 : indice du dernier élément de m_part1
  //L2 : indice du premier élément de m_part2
  //R2 : indice du dernier élément de m_part2
  int size = 1;
  int L1, R1, L2, R2;
  int i;

  while (size <= n_m)
  {
    i = 0;
    while(i < n_m){
      // printf("m : ");
      // print_array(m, n_m);
      L1 = i;
      R1 = i + size-1;
      L2 = i + size;
      R2 = i + 2*size-1;
      if(L2 >= n_m){
          break;
      }
      if(R2 >= n_m){
          R2 = n_m-1;
      }
      int size_1 = R1-L1+1;
      int size_2 = R2-L2+1;
      int size_12 = size_1+size_2;
      int *m_12, *m_1, *m_2;
      m_12 = (int*)malloc(size_12*sizeof(int));
      m_1 = (int*)malloc(size_1*sizeof(int));
      m_2 = (int*)malloc(size_2*sizeof(int));

      //Remplir les tableaux m_1 et m_2
      for (int j = 0; j < size_1; j++)
      {
        m_1[j] = m[L1 + j];
      }
      for (int j = 0; j < size_2; j++)
      {
        m_2[j] = m[L2 + j];
      }

      mergeAll(m_12, size_12, m_1, size_1, m_2, size_2);

      for (int j = 0; j < size_12; j++)
      {
        m[L1+j] = m_12[j];
      }
      free(m_12);
      free(m_1);
      free(m_2);
      i = i + 2*size;
    }
    size *= 2;
  }
}


void fusionMergeSeq(int* A, int* tmp, int L1, int R1, int L2, int R2){
    int i = 0;
    while(L1 <= R1 && L2 <= R2){
        if(A[L1] <= A[L2]){
            tmp[i] = A[L1];
            i++;
            L1++;
        }
        else{
            tmp[i] = A[L2];
            i++;
            L2++;
        }
    }
    while(L1 <= R1){
        tmp[i] = A[L1];
        i++;
        L1++;
    }
    while(L2 <= R2){
        tmp[i] = A[L2];
        i++;
        L2++;
    }

}

void fusionSortSeq(int* A, int n){
    int len = 1;
    int i;
    int L1, R1, L2, R2;
    int* tmp = (int*)malloc(n*sizeof(int));
    while(len < n){
        i = 0;
        while(i < n){
            L1 = i;
            R1 = i + len - 1;
            L2 = i + len;
            R2 = i + 2*len - 1;
            tmp = (int*)realloc(tmp, (R2-L1+1)*sizeof(int));
            if(L2 >= n){
                break;
            }
            if(R2 >= n){
                R2 = n - 1;
            }
            fusionMergeSeq(A, tmp, L1, R1, L2, R2);
            for(int j = 0;j < R2-L1+1;j++){
                A[i+j] = tmp[j];
            }
            i = i + 2*len;
        }
        len *= 2;
    }
    free(tmp);
}

//Fonction qui trie un tableau M en parallèle par tri fusion itératif (question 3)

//Fonctions de vérification

//Fonction qui vérifie qu'un tableau est bien trié (tous ses éléments rangés dans l'ordre croissant)
int assertOrder(int *tab, int size){
  for (int i=0; i<size-1; i++){
    if (tab[i] > tab[i+1]){
      printf("WARNING : Unsuccessful merge or sort ... : unordered array on indice %d ...\n", i);
      printf("tab[i]= %d > tab[i+1] = %d\n", tab[i], tab[i+1]);
      return 0;
    }
  }
  return 1;
}

//Fonction qui vérifie qu'on retrouve bien dans le nouveau tableau tous les éléments des deux tableaux qu'on veut fusionner
int assertMergeAllValuesPresent(int *tab, int n1, int *tab2, int n2, int* m, int size)
{
  int verif[size]; //tableau avec des 1 là où l'on a déjà vérifié qu'il correspond déjà à un élément de a ou de b
  for(int i = 0;i<size;i++){
      verif[i] = 0;
  }

  for (int i=0; i<size; i++){
    for(int j = 0;j < n1;j++){
      if(tab[j] == m[i] && verif[i] == 0){ //si il y a une valeur identique et que celle-ci n'a pas été vérifiée
          verif[i] = 1;
      }
    }
  }
  for (int i=0; i<size; i++){
    for(int j = 0;j < n2;j++){
      if(tab2[j] == m[i] && verif[i] == 0){
          verif[i] = 1;
      }
    }
  }

  for(int i = 0;i<size;i++){
    if(verif[i] != 1){
        printf("\nWARNING : Unsuccessful merge : incorrect elements...\n");
        return 0;
    }
  }

  return 1;
}

//Fonction qui vérifie qu'on retrouve bien dans le nouveau tableau tous les éléments du tableau qu'on veut trier
int assertSortAllValuesPresent(int* m, int* m_sorted, int size){
  int verif[size]; //tableau avec des 1 là où l'on a déjà vérifié qu'il correspond déjà à un élément de a ou de b
  for(int i = 0;i<size;i++){
      verif[i] = 0;
  }

  for (int i=0; i<size; i++){
    for(int j = 0;j < size;j++){
      if(m_sorted[j] == m[i]){ //si il y a une valeur identique
          verif[i] = 1;
      }
    }
  }

  for(int i = 0;i<size;i++){
    if(verif[i] != 1){
        printf("i : %d\n", i);
        printf("\nWARNING : Unsuccessful sort : incorrect elements...\n");
        return 0;
    }
  }

  return 1;
}

//Fonction qui vérifie qu'un tableau est bien trié et la fusion de deux tableaux
//tab et tab2 : les deux tableaux qu'on veut fusionner
//m : le tableau qui est la fusion triée de tab et tab2
int assertMerge(int *tab, int n1, int *tab2, int n2, int* m, int size){
    int successfulOrder = assertOrder(m, size);
    int successfulElements = assertMergeAllValuesPresent(tab, n1, tab2, n2, m, size);
    //assertMergeAllValuesPresent(int *tab, int n1, int *tab2, int n2, int* m, int size)
    if(successfulOrder && successfulElements){
        printf("\nSuccessful merge !\n");
        return 1;
    }
    else{
        printf("\nUnsuccessful merge !\n");
        return 0;
    }
}

//Fonction qui vérifie qu'un tableau est bien trié
//m : le tableau non trié qu'on veut trier
//m_sorted : le tableau m soi-disant trié (on veut vérifier si c'est bien le cas)
//size : la taille du tableau
int assertSorted(int* m, int* m_sorted, int size)
{
    int successfulOrder = assertOrder(m_sorted, size); // les éléments du tableau sont ils bien dans le bon ordre ?
    int successfulElements = assertSortAllValuesPresent(m, m_sorted, size); //retrouve t-on bien toutes les valeurs ?
    if(successfulOrder && successfulElements){
        printf("\nSuccessful sort !\n");
        return 1;
    }
    else{
        printf("\nUnsuccessful sort !\n");
        return 0;
    }
}

int main(int argc, char *argv[])
{
    std::clock_t startS, endS;
    float seqMergeTime, parMergeTime;

    srand(time(NULL));
    int n_m = 100000;
    int *m, *mseq, *mref;

    if(argc==2)
    {
      n_m = atoi(argv[1]);
    }

    printf("========== Path Sort : =========\n");
    printf("* Size of array : %d\n\n", n_m);
    //int* mseq;
    m = (int*)malloc(n_m*sizeof(int));
    init_array_no_order(m, n_m, n_m*10);
    mseq = (int*)malloc(n_m*sizeof(int)); //copie de m
    copy_array(m, mseq, n_m);
    mref = (int*)malloc(n_m*sizeof(int)); //copie de m
    copy_array(m, mref, n_m);
    //Partie des calculs1024
    //================ Paral1024lel : =======================\\
    //Etape de prétraitement :
    startS = std::clock();
    fusionSort(m, n_m);
    gpuCheck(cudaDeviceSynchronize());
    endS = std::clock();
    parMergeTime = (endS - startS) / (float) CLOCKS_PER_SEC;
    //Etape du tri fusion :

    startS = std::clock();
    fusionSortSeq(mseq, n_m);
    endS = std::clock();
    seqMergeTime = (endS - startS) / (float) CLOCKS_PER_SEC;

    printf("========= Parallel sort : =============\n");
    printf("Total time elapsed : %f s\n", parMergeTime);
    // assertSorted(mref, m, n_m);
    printf("Parrallel algorithm is %f times faster than sequential merge !\n", seqMergeTime/parMergeTime);
    printf("Parrallel merge is %f times faster than sequential merge !\n", seqMergeTime/parMergeTime);

    printf("========= Sequential sort : =============\n");
    printf("Total time elapsed : %f s\n", seqMergeTime);
    // assertSorted(mref, mseq, n_m);




    return 0;
}

	.file	"tmpxft_002f13d9_00000000-6_pathSortFinal.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2045:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2045:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata._Z9gpuAssert9cudaErrorPKcib.str1.1,"aMS",@progbits,1
.LC0:
	.string	"GPUassert: %s %s %d\n"
	.section	.text._Z9gpuAssert9cudaErrorPKcib,"axG",@progbits,_Z9gpuAssert9cudaErrorPKcib,comdat
	.weak	_Z9gpuAssert9cudaErrorPKcib
	.type	_Z9gpuAssert9cudaErrorPKcib, @function
_Z9gpuAssert9cudaErrorPKcib:
.LFB2027:
	.cfi_startproc
	endbr64
	testl	%edi, %edi
	je	.L8
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	%ecx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movl	%edi, %ebx
	subq	$24, %rsp
	.cfi_def_cfa_offset 48
	movl	%edx, 12(%rsp)
	movq	%rsi, (%rsp)
	call	cudaGetErrorString@PLT
	movl	12(%rsp), %r9d
	movq	(%rsp), %r8
	leaq	.LC0(%rip), %rdx
	movq	stderr(%rip), %rdi
	movq	%rax, %rcx
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	testb	%bpl, %bpl
	je	.L2
	movl	%ebx, %edi
	call	exit@PLT
.L2:
	addq	$24, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
.L8:
	.cfi_restore 3
	.cfi_restore 6
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z9gpuAssert9cudaErrorPKcib, .-_Z9gpuAssert9cudaErrorPKcib
	.text
	.globl	_Z10init_arrayPiii
	.type	_Z10init_arrayPiii, @function
_Z10init_arrayPiii:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movl	%esi, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	movq	%rdi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	xorl	%ebp, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	movl	%edx, %ebx
	call	rand@PLT
	cltd
	idivl	%ebx
	movl	%edx, (%r12)
.L13:
	cmpl	%ebp, %r13d
	jle	.L16
	movl	-4(%r12,%rbp,4), %r14d
	call	rand@PLT
	cltd
	idivl	%ebx
	addl	%r14d, %edx
	movl	%edx, (%r12,%rbp,4)
	incq	%rbp
	jmp	.L13
.L16:
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z10init_arrayPiii, .-_Z10init_arrayPiii
	.globl	_Z19init_array_no_orderPiii
	.type	_Z19init_array_no_orderPiii, @function
_Z19init_array_no_orderPiii:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movl	%esi, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movq	%rdi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	xorl	%ebp, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movl	%edx, %ebx
	pushq	%rcx
	.cfi_def_cfa_offset 48
	call	rand@PLT
	cltd
	idivl	%ebx
	movl	%edx, (%r12)
.L18:
	cmpl	%ebp, %r13d
	jle	.L21
	call	rand@PLT
	cltd
	idivl	%ebx
	movl	%edx, (%r12,%rbp,4)
	incq	%rbp
	jmp	.L18
.L21:
	popq	%rax
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	_Z19init_array_no_orderPiii, .-_Z19init_array_no_orderPiii
	.globl	_Z10copy_arrayPiS_i
	.type	_Z10copy_arrayPiS_i, @function
_Z10copy_arrayPiS_i:
.LFB2030:
	.cfi_startproc
	endbr64
	xorl	%eax, %eax
.L23:
	cmpl	%eax, %edx
	jle	.L25
	movl	(%rdi,%rax,4), %ecx
	movl	%ecx, (%rsi,%rax,4)
	incq	%rax
	jmp	.L23
.L25:
	ret
	.cfi_endproc
.LFE2030:
	.size	_Z10copy_arrayPiS_i, .-_Z10copy_arrayPiS_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"["
.LC2:
	.string	"%d "
.LC3:
	.string	"]\n"
	.text
	.globl	_Z11print_arrayPii
	.type	_Z11print_arrayPii, @function
_Z11print_arrayPii:
.LFB2031:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	xorl	%eax, %eax
	leaq	.LC2(%rip), %r13
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movq	%rdi, %r12
	movl	$2, %edi
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movl	%esi, %ebp
	leaq	.LC1(%rip), %rsi
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	xorl	%ebx, %ebx
	pushq	%rcx
	.cfi_def_cfa_offset 48
	call	__printf_chk@PLT
.L27:
	cmpl	%ebx, %ebp
	jle	.L30
	movl	(%r12,%rbx,4), %edx
	movq	%r13, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%rbx
	call	__printf_chk@PLT
	jmp	.L27
.L30:
	popq	%rdx
	.cfi_def_cfa_offset 40
	leaq	.LC3(%rip), %rsi
	popq	%rbx
	.cfi_def_cfa_offset 32
	movl	$2, %edi
	popq	%rbp
	.cfi_def_cfa_offset 24
	xorl	%eax, %eax
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	__printf_chk@PLT
	.cfi_endproc
.LFE2031:
	.size	_Z11print_arrayPii, .-_Z11print_arrayPii
	.globl	_Z13mergeParallelPiS_S_iii
	.type	_Z13mergeParallelPiS_S_iii, @function
_Z13mergeParallelPiS_S_iii:
.LFB2032:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2032:
	.size	_Z13mergeParallelPiS_S_iii, .-_Z13mergeParallelPiS_S_iii
	.globl	_Z14fusionMergeSeqPiS_iiii
	.type	_Z14fusionMergeSeqPiS_iiii, @function
_Z14fusionMergeSeqPiS_iiii:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	xorl	%eax, %eax
.L34:
	cmpl	%ecx, %edx
	movslq	%edx, %r10
	jg	.L43
	cmpl	%r9d, %r8d
	jg	.L43
	movslq	%r8d, %r11
	movl	(%rdi,%r10,4), %r10d
	movl	(%rdi,%r11,4), %r11d
	cmpl	%r11d, %r10d
	jg	.L35
	incl	%edx
	jmp	.L36
.L35:
	incl	%r8d
	movl	%r11d, %r10d
.L36:
	movl	%r10d, (%rsi,%rax,4)
	incq	%rax
	jmp	.L34
.L43:
	movl	%eax, %r11d
	cltq
.L39:
	cmpl	%r10d, %ecx
	jl	.L48
	movl	(%rdi,%r10,4), %ebx
	incq	%r10
	movl	%ebx, (%rsi,%rax,4)
	incq	%rax
	jmp	.L39
.L48:
	incl	%ecx
	movslq	%r8d, %r8
	movl	%ecx, %eax
	subl	%edx, %eax
	cmpl	%edx, %ecx
	movl	$0, %edx
	cmovl	%edx, %eax
	addl	%r11d, %eax
	cltq
.L41:
	cmpl	%r8d, %r9d
	jl	.L49
	movl	(%rdi,%r8,4), %edx
	incq	%r8
	movl	%edx, (%rsi,%rax,4)
	incq	%rax
	jmp	.L41
.L49:
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2035:
	.size	_Z14fusionMergeSeqPiS_iiii, .-_Z14fusionMergeSeqPiS_iiii
	.globl	_Z13fusionSortSeqPii
	.type	_Z13fusionSortSeqPii, @function
_Z13fusionSortSeqPii:
.LFB2036:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	$1, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 16(%rsp)
	movslq	%esi, %rdi
	movq	%rdi, %rbp
	salq	$2, %rdi
	call	malloc@PLT
	movq	%rax, %rbx
.L51:
	cmpl	%ebp, %r13d
	jge	.L57
	leal	(%r13,%r13), %r14d
	movl	%r13d, %r8d
	xorl	%r15d, %r15d
	movslq	%r14d, %rax
	salq	$2, %rax
	movq	%rax, 24(%rsp)
	movq	16(%rsp), %rax
	movq	%rax, 8(%rsp)
	leal	-1(%rbp), %eax
	movl	%eax, 36(%rsp)
.L58:
	cmpl	%ebp, %r15d
	jge	.L52
	leal	(%r14,%r15), %eax
	leal	-1(%r8), %ecx
	movq	%rbx, %rdi
	movl	%r8d, 40(%rsp)
	movl	%eax, %esi
	movl	%ecx, 44(%rsp)
	leal	-1(%rax), %r12d
	subl	%r15d, %esi
	movl	%eax, 32(%rsp)
	movslq	%esi, %rsi
	salq	$2, %rsi
	call	realloc@PLT
	movl	40(%rsp), %r8d
	movq	%rax, %rbx
	cmpl	%ebp, %r8d
	jge	.L52
	cmpl	%r12d, %ebp
	cmovle	36(%rsp), %r12d
	movl	44(%rsp), %ecx
	movq	%rax, %rsi
	movq	16(%rsp), %rdi
	movl	%r15d, %edx
	movl	%r12d, %r9d
	subl	%r15d, %r12d
	call	_Z14fusionMergeSeqPiS_iiii
	movl	40(%rsp), %r8d
	xorl	%eax, %eax
.L54:
	cmpl	%eax, %r12d
	jl	.L60
	movl	(%rbx,%rax,4), %edx
	movq	8(%rsp), %rcx
	movl	%edx, (%rcx,%rax,4)
	incq	%rax
	jmp	.L54
.L60:
	movq	24(%rsp), %rdx
	movl	32(%rsp), %r15d
	addl	%r14d, %r8d
	addq	%rdx, 8(%rsp)
	jmp	.L58
.L52:
	addl	%r13d, %r13d
	jmp	.L51
.L57:
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	free@PLT
	.cfi_endproc
.LFE2036:
	.size	_Z13fusionSortSeqPii, .-_Z13fusionSortSeqPii
	.section	.rodata.str1.1
.LC4:
	.string	"WARNING : Unsuccessful merge or sort ... : unordered array on indice %d ...\n"
.LC5:
	.string	"tab[i]= %d > tab[i+1] = %d\n"
	.text
	.globl	_Z11assertOrderPii
	.type	_Z11assertOrderPii, @function
_Z11assertOrderPii:
.LFB2037:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	xorl	%edx, %edx
	decl	%esi
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movq	%rdi, %rbx
	pushq	%rcx
	.cfi_def_cfa_offset 32
.L62:
	cmpl	%edx, %esi
	jle	.L67
	movq	%rbx, %rbp
	addq	$4, %rbx
	movl	(%rbx), %eax
	cmpl	%eax, 0(%rbp)
	jle	.L63
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	(%rbx), %ecx
	movl	0(%rbp), %edx
	movl	$2, %edi
	leaq	.LC5(%rip), %rsi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	xorl	%eax, %eax
	jmp	.L61
.L63:
	incl	%edx
	jmp	.L62
.L67:
	movl	$1, %eax
.L61:
	popq	%rdx
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2037:
	.size	_Z11assertOrderPii, .-_Z11assertOrderPii
	.section	.rodata.str1.1
.LC6:
	.string	"\nWARNING : Unsuccessful merge : incorrect elements...\n"
	.text
	.globl	_Z27assertMergeAllValuesPresentPiiS_iS_i
	.type	_Z27assertMergeAllValuesPresentPiiS_iS_i, @function
_Z27assertMergeAllValuesPresentPiiS_iS_i:
.LFB2038:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	%esi, %r11d
	movq	%rdx, %rsi
	movq	%rdi, %r10
	movl	%ecx, %edi
	movq	%rsp, %rbp
	.cfi_def_cfa_register 6
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset 3, -24
	movq	%fs:40, %rax
	movq	%rax, -24(%rbp)
	xorl	%eax, %eax
	movslq	%r9d, %rax
	movq	%rsp, %rcx
	leaq	15(,%rax,4), %rdx
	movq	%rdx, %rax
	andq	$-4096, %rdx
	andq	$-16, %rax
	subq	%rdx, %rcx
.L69:
	cmpq	%rcx, %rsp
	je	.L70
	subq	$4096, %rsp
	orq	$0, 4088(%rsp)
	jmp	.L69
.L70:
	andl	$4095, %eax
	subq	%rax, %rsp
	testq	%rax, %rax
	je	.L71
	orq	$0, -8(%rsp,%rax)
.L71:
	movq	%rsp, %rax
	xorl	%edx, %edx
.L72:
	cmpl	%edx, %r9d
	jle	.L93
	xorl	%ecx, %ecx
	movl	%ecx, (%rax,%rdx,4)
	incq	%rdx
	jmp	.L72
.L93:
	xorl	%edx, %edx
.L74:
	cmpl	%edx, %r9d
	jle	.L94
	xorl	%ecx, %ecx
.L77:
	cmpl	%ecx, %r11d
	jle	.L95
	movl	(%r8,%rdx,4), %ebx
	cmpl	%ebx, (%r10,%rcx,4)
	jne	.L75
	cmpl	$0, (%rax,%rdx,4)
	jne	.L75
	movl	$1, (%rax,%rdx,4)
.L75:
	incq	%rcx
	jmp	.L77
.L95:
	incq	%rdx
	jmp	.L74
.L94:
	xorl	%edx, %edx
.L78:
	cmpl	%edx, %r9d
	jle	.L96
	xorl	%ecx, %ecx
.L81:
	cmpl	%ecx, %edi
	jle	.L97
	movl	(%r8,%rdx,4), %ebx
	cmpl	%ebx, (%rsi,%rcx,4)
	jne	.L79
	cmpl	$0, (%rax,%rdx,4)
	jne	.L79
	movl	$1, (%rax,%rdx,4)
.L79:
	incq	%rcx
	jmp	.L81
.L97:
	incq	%rdx
	jmp	.L78
.L96:
	xorl	%edx, %edx
.L82:
	cmpl	%edx, %r9d
	jle	.L98
	incq	%rdx
	cmpl	$1, -4(%rax,%rdx,4)
	je	.L82
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	xorl	%eax, %eax
	jmp	.L68
.L98:
	movl	$1, %eax
.L68:
	movq	-24(%rbp), %rdx
	subq	%fs:40, %rdx
	je	.L85
	call	__stack_chk_fail@PLT
.L85:
	movq	-8(%rbp), %rbx
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE2038:
	.size	_Z27assertMergeAllValuesPresentPiiS_iS_i, .-_Z27assertMergeAllValuesPresentPiiS_iS_i
	.section	.rodata.str1.1
.LC7:
	.string	"i : %d\n"
.LC8:
	.string	"\nWARNING : Unsuccessful sort : incorrect elements...\n"
	.text
	.globl	_Z26assertSortAllValuesPresentPiS_i
	.type	_Z26assertSortAllValuesPresentPiS_i, @function
_Z26assertSortAllValuesPresentPiS_i:
.LFB2039:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	%edx, %eax
	movq	%rsi, %r8
	movq	%rsp, %rbp
	.cfi_def_cfa_register 6
	subq	$16, %rsp
	movq	%fs:40, %rdx
	movq	%rdx, -8(%rbp)
	xorl	%edx, %edx
	movslq	%eax, %rdx
	movq	%rsp, %rsi
	leaq	15(,%rdx,4), %rcx
	movq	%rcx, %rdx
	andq	$-4096, %rcx
	andq	$-16, %rdx
	subq	%rcx, %rsi
.L100:
	cmpq	%rsi, %rsp
	je	.L101
	subq	$4096, %rsp
	orq	$0, 4088(%rsp)
	jmp	.L100
.L101:
	andl	$4095, %edx
	subq	%rdx, %rsp
	testq	%rdx, %rdx
	je	.L102
	orq	$0, -8(%rsp,%rdx)
.L102:
	movq	%rsp, %rsi
	xorl	%edx, %edx
.L103:
	cmpl	%edx, %eax
	jle	.L119
	xorl	%ecx, %ecx
	movl	%ecx, (%rsi,%rdx,4)
	incq	%rdx
	jmp	.L103
.L119:
	xorl	%edx, %edx
.L105:
	cmpl	%edx, %eax
	jle	.L120
	movl	(%rdi,%rdx,4), %r9d
	xorl	%ecx, %ecx
.L107:
	cmpl	%r9d, (%r8,%rcx,4)
	jne	.L106
	movl	$1, (%rsi,%rdx,4)
.L106:
	incq	%rcx
	cmpl	%ecx, %eax
	jg	.L107
	incq	%rdx
	jmp	.L105
.L120:
	xorl	%edx, %edx
.L109:
	cmpl	%edx, %eax
	jle	.L121
	cmpl	$1, (%rsi,%rdx,4)
	leaq	1(%rdx), %rcx
	je	.L113
	leaq	.LC7(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC8(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	xorl	%eax, %eax
	jmp	.L99
.L113:
	movq	%rcx, %rdx
	jmp	.L109
.L121:
	movl	$1, %eax
.L99:
	movq	-8(%rbp), %rdx
	subq	%fs:40, %rdx
	je	.L112
	call	__stack_chk_fail@PLT
.L112:
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE2039:
	.size	_Z26assertSortAllValuesPresentPiS_i, .-_Z26assertSortAllValuesPresentPiS_i
	.section	.rodata.str1.1
.LC9:
	.string	"\nSuccessful merge !\n"
.LC10:
	.string	"\nUnsuccessful merge !\n"
	.text
	.globl	_Z11assertMergePiiS_iS_i
	.type	_Z11assertMergePiiS_iS_i, @function
_Z11assertMergePiiS_iS_i:
.LFB2040:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	%esi, %r12d
	movl	%r9d, %esi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	movq	%rdi, %rbp
	movq	%r8, %rdi
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$32, %rsp
	.cfi_def_cfa_offset 64
	movq	%rdx, 24(%rsp)
	movl	%ecx, 20(%rsp)
	movl	%r9d, 16(%rsp)
	movq	%r8, 8(%rsp)
	call	_Z11assertOrderPii
	movl	16(%rsp), %r9d
	movl	%r12d, %esi
	movq	%rbp, %rdi
	movq	8(%rsp), %r8
	movl	20(%rsp), %ecx
	movl	%eax, %ebx
	movq	24(%rsp), %rdx
	call	_Z27assertMergeAllValuesPresentPiiS_iS_i
	testl	%ebx, %ebx
	je	.L123
	testl	%eax, %eax
	je	.L123
	leaq	.LC9(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$1, %eax
	jmp	.L122
.L123:
	leaq	.LC10(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	xorl	%eax, %eax
.L122:
	addq	$32, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2040:
	.size	_Z11assertMergePiiS_iS_i, .-_Z11assertMergePiiS_iS_i
	.section	.rodata.str1.1
.LC11:
	.string	"\nSuccessful sort !\n"
.LC12:
	.string	"\nUnsuccessful sort !\n"
	.text
	.globl	_Z12assertSortedPiS_i
	.type	_Z12assertSortedPiS_i, @function
_Z12assertSortedPiS_i:
.LFB2041:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	movq	%rdi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	movq	%rsi, %rbx
	movl	%edx, %esi
	movq	%rbx, %rdi
	subq	$16, %rsp
	.cfi_def_cfa_offset 48
	movl	%edx, 12(%rsp)
	call	_Z11assertOrderPii
	movl	12(%rsp), %edx
	movq	%rbx, %rsi
	movq	%r13, %rdi
	movl	%eax, %r12d
	call	_Z26assertSortAllValuesPresentPiS_i
	testl	%r12d, %r12d
	je	.L133
	testl	%eax, %eax
	je	.L133
	leaq	.LC11(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$1, %eax
	jmp	.L132
.L133:
	leaq	.LC12(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	xorl	%eax, %eax
.L132:
	addq	$16, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2041:
	.size	_Z12assertSortedPiS_i, .-_Z12assertSortedPiS_i
	.globl	_Z39__device_stub__Z12mergeSmall_kPiS_S_iiiPiS_S_iii
	.type	_Z39__device_stub__Z12mergeSmall_kPiS_S_iiiPiS_S_iii, @function
_Z39__device_stub__Z12mergeSmall_kPiS_S_iiiPiS_S_iii:
.LFB2067:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L142
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z12mergeSmall_kPiS_S_iii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L142:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L144
	call	__stack_chk_fail@PLT
.L144:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2067:
	.size	_Z39__device_stub__Z12mergeSmall_kPiS_S_iiiPiS_S_iii, .-_Z39__device_stub__Z12mergeSmall_kPiS_S_iiiPiS_S_iii
	.globl	_Z12mergeSmall_kPiS_S_iii
	.type	_Z12mergeSmall_kPiS_S_iii, @function
_Z12mergeSmall_kPiS_S_iii:
.LFB2068:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z12mergeSmall_kPiS_S_iiiPiS_S_iii
	.cfi_endproc
.LFE2068:
	.size	_Z12mergeSmall_kPiS_S_iii, .-_Z12mergeSmall_kPiS_S_iii
	.globl	_Z45__device_stub__Z10mergeBig_kPiiS_iS_iP4int2iiPiiS_iS_iP4int2ii
	.type	_Z45__device_stub__Z10mergeBig_kPiiS_iS_iP4int2iiPiiS_iS_iP4int2ii, @function
_Z45__device_stub__Z10mergeBig_kPiiS_iS_iP4int2iiPiiS_iS_iP4int2ii:
.LFB2069:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	208(%rsp), %rax
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movl	%esi, 36(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 32(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	movq	%rsp, %rax
	movq	%rax, 160(%rsp)
	leaq	216(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L147
	pushq	56(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z10mergeBig_kPiiS_iS_iP4int2ii(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 224
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L147:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L149
	call	__stack_chk_fail@PLT
.L149:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2069:
	.size	_Z45__device_stub__Z10mergeBig_kPiiS_iS_iP4int2iiPiiS_iS_iP4int2ii, .-_Z45__device_stub__Z10mergeBig_kPiiS_iS_iP4int2iiPiiS_iS_iP4int2ii
	.globl	_Z10mergeBig_kPiiS_iS_iP4int2ii
	.type	_Z10mergeBig_kPiiS_iS_iP4int2ii, @function
_Z10mergeBig_kPiiS_iS_iP4int2ii:
.LFB2070:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z10mergeBig_kPiiS_iS_iP4int2iiPiiS_iS_iP4int2ii
	.cfi_endproc
.LFE2070:
	.size	_Z10mergeBig_kPiiS_iS_iP4int2ii, .-_Z10mergeBig_kPiiS_iS_iP4int2ii
	.globl	_Z41__device_stub__Z9pathBig_kiP4int2iPiiS1_iiP4int2iPiiS1_i
	.type	_Z41__device_stub__Z9pathBig_kiP4int2iPiiS1_iiP4int2iPiiS1_i, @function
_Z41__device_stub__Z9pathBig_kiP4int2iPiiS1_iiP4int2iPiiS1_i:
.LFB2071:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movl	%edi, 44(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movl	%edx, 40(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 20(%rsp)
	movq	%r9, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	192(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L152
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z9pathBig_kiP4int2iPiiS1_i(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L152:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L154
	call	__stack_chk_fail@PLT
.L154:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2071:
	.size	_Z41__device_stub__Z9pathBig_kiP4int2iPiiS1_iiP4int2iPiiS1_i, .-_Z41__device_stub__Z9pathBig_kiP4int2iPiiS1_iiP4int2iPiiS1_i
	.globl	_Z9pathBig_kiP4int2iPiiS1_i
	.type	_Z9pathBig_kiP4int2iPiiS1_i, @function
_Z9pathBig_kiP4int2iPiiS1_i:
.LFB2072:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z9pathBig_kiP4int2iPiiS1_iiP4int2iPiiS1_i
	.cfi_endproc
.LFE2072:
	.size	_Z9pathBig_kiP4int2iPiiS1_i, .-_Z9pathBig_kiP4int2iPiiS1_i
	.section	.rodata.str1.1
.LC13:
	.string	"/home/ubuntu/Datasets/stackv2/train-structured/homerdurand/HPCA/main/pathSortFinal.cu"
	.text
	.globl	_Z8mergeAllPiiS_iS_i
	.type	_Z8mergeAllPiiS_iS_i, @function
_Z8mergeAllPiiS_iS_i:
.LFB2033:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$1024, %r15d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	%r9d, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%ecx, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	xorl	%ebp, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%esi, %ebx
	subq	$120, %rsp
	.cfi_def_cfa_offset 176
	movq	%r8, 40(%rsp)
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rdx, 32(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	testl	$1023, %esi
	movl	%esi, %eax
	setne	%bpl
	cltd
	idivl	%r15d
	addl	%eax, %ebp
	movslq	%esi, %rax
	salq	$2, %rax
	leal	1(%rbp), %r14d
	movq	%rax, %rsi
	movq	%rax, (%rsp)
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$293, %edx
	leaq	.LC13(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movslq	%r12d, %rax
	leaq	56(%rsp), %rdi
	salq	$2, %rax
	movq	%rax, %rsi
	movq	%rax, 8(%rsp)
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$294, %edx
	leaq	.LC13(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movslq	%r13d, %rax
	leaq	64(%rsp), %rdi
	salq	$2, %rax
	movq	%rax, %rsi
	movq	%rax, 16(%rsp)
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$295, %edx
	leaq	.LC13(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movslq	%r14d, %rsi
	leaq	72(%rsp), %rdi
	salq	$3, %rsi
	call	cudaMalloc@PLT
	movl	$1, %ecx
	movl	$299, %edx
	leaq	.LC13(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	8(%rsp), %rdx
	movq	32(%rsp), %rsi
	movl	$1, %ecx
	movq	56(%rsp), %rdi
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$301, %edx
	leaq	.LC13(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	16(%rsp), %rdx
	movq	40(%rsp), %rsi
	movl	$1, %ecx
	movq	64(%rsp), %rdi
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$302, %edx
	leaq	.LC13(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	cmpl	$1024, %ebx
	movabsq	$4294968320, %rcx
	movl	$1, 100(%rsp)
	movq	%rcx, 92(%rsp)
	jg	.L158
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%rcx, %rdx
	movl	$1, %esi
	movabsq	$4294967297, %rdi
	movl	$1, %ecx
	movl	$1, 88(%rsp)
	movq	%rdi, 80(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L159
	movq	48(%rsp), %rdx
	movq	64(%rsp), %rsi
	movl	%ebx, %r9d
	movl	%r13d, %r8d
	movq	56(%rsp), %rdi
	movl	%r12d, %ecx
	call	_Z39__device_stub__Z12mergeSmall_kPiS_S_iiiPiS_S_iii
.L159:
	call	cudaPeekAtLastError@PLT
	movl	$1, %ecx
	movl	$309, %edx
	leaq	.LC13(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	(%rsp), %rdx
	movq	24(%rsp), %rdi
	movl	$2, %ecx
	movq	48(%rsp), %rsi
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$311, %edx
	movl	%eax, %edi
	jmp	.L165
.L158:
	movl	%ebp, %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	cltd
	idivl	%r15d
	movq	%rcx, %rdx
	movl	$1, %ecx
	incl	%eax
	movl	%eax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 84(%rsp)
	movq	80(%rsp), %rdi
	movl	88(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L161
	pushq	%rdx
	.cfi_def_cfa_offset 184
	movl	%r12d, %r8d
	movl	%r14d, %edx
	movl	$1024, %edi
	pushq	%r13
	.cfi_def_cfa_offset 192
	movq	80(%rsp), %r9
	movq	72(%rsp), %rcx
	movq	88(%rsp), %rsi
	call	_Z41__device_stub__Z9pathBig_kiP4int2iPiiS1_iiP4int2iPiiS1_i
	popq	%rcx
	.cfi_def_cfa_offset 184
	popq	%rsi
	.cfi_def_cfa_offset 176
.L161:
	call	cudaPeekAtLastError@PLT
	movl	$1, %ecx
	movl	$318, %edx
	leaq	.LC13(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	call	cudaDeviceSynchronize@PLT
	movl	$1, %ecx
	movl	$319, %edx
	leaq	.LC13(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movl	%ebp, 80(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rax
	movl	$4194305, %edx
	movl	$1, %ecx
	movl	$1, 100(%rsp)
	movq	%rax, 84(%rsp)
	movq	80(%rsp), %rdi
	salq	$10, %rdx
	movl	88(%rsp), %esi
	movq	%rdx, 92(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L162
	pushq	%rax
	.cfi_def_cfa_offset 184
	movl	%r13d, %r9d
	movl	%r12d, %ecx
	movl	%ebx, %esi
	pushq	%rbp
	.cfi_def_cfa_offset 192
	pushq	%r14
	.cfi_def_cfa_offset 200
	pushq	96(%rsp)
	.cfi_def_cfa_offset 208
	movq	96(%rsp), %r8
	movq	88(%rsp), %rdx
	movq	80(%rsp), %rdi
	call	_Z45__device_stub__Z10mergeBig_kPiiS_iS_iP4int2iiPiiS_iS_iP4int2ii
	addq	$32, %rsp
	.cfi_def_cfa_offset 176
.L162:
	call	cudaDeviceSynchronize@PLT
	movl	$1, %ecx
	movl	$321, %edx
	leaq	.LC13(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	(%rsp), %rdx
	movq	48(%rsp), %rsi
	movl	$2, %ecx
	movq	24(%rsp), %rdi
	call	cudaMemcpy@PLT
	movl	$1, %ecx
	movl	$323, %edx
	leaq	.LC13(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	call	cudaDeviceSynchronize@PLT
	movl	$1, %ecx
	movl	$325, %edx
	movl	%eax, %edi
.L165:
	leaq	.LC13(%rip), %rsi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movl	$1, %ecx
	movl	$327, %edx
	leaq	.LC13(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	64(%rsp), %rdi
	call	cudaFree@PLT
	movl	$1, %ecx
	movl	$328, %edx
	leaq	.LC13(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movl	$1, %ecx
	movl	$329, %edx
	leaq	.LC13(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L163
	call	__stack_chk_fail@PLT
.L163:
	addq	$120, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z8mergeAllPiiS_iS_i, .-_Z8mergeAllPiiS_iS_i
	.globl	_Z10fusionSortPii
	.type	_Z10fusionSortPii, @function
_Z10fusionSortPii:
.LFB2034:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	$1, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%esi, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 40(%rsp)
.L167:
	cmpl	%ebp, %r12d
	jg	.L166
	leal	(%r12,%r12), %r15d
	leal	-1(%rbp), %edx
	movq	40(%rsp), %r14
	movl	%r12d, %r13d
	movslq	%r15d, %rax
	movl	%edx, 52(%rsp)
	salq	$2, %rax
	movq	%rax, 24(%rsp)
	movslq	%r12d, %rax
	salq	$2, %rax
	movq	%rax, 32(%rsp)
	xorl	%eax, %eax
.L179:
	cmpl	%ebp, %eax
	jge	.L177
	leal	(%r15,%rax), %esi
	leal	-1(%r13), %ecx
	movl	%esi, 48(%rsp)
	leal	-1(%rsi), %ebx
	cmpl	%ebp, %r13d
	jl	.L168
.L177:
	addl	%r12d, %r12d
	jmp	.L167
.L168:
	cmpl	%ebx, %ebp
	cmovle	52(%rsp), %ebx
	subl	%eax, %ecx
	incl	%ecx
	subl	%r13d, %ebx
	movl	%ecx, 8(%rsp)
	leal	1(%rbx), %r9d
	leal	(%rcx,%r9), %eax
	movl	%r9d, 16(%rsp)
	movslq	%eax, %rdi
	movl	%eax, 4(%rsp)
	salq	$2, %rdi
	call	malloc@PLT
	movslq	8(%rsp), %rdi
	movq	%rax, %rbx
	movl	%edi, 60(%rsp)
	salq	$2, %rdi
	call	malloc@PLT
	movslq	16(%rsp), %rdi
	movq	%rax, 8(%rsp)
	movl	%edi, 56(%rsp)
	salq	$2, %rdi
	call	malloc@PLT
	movl	56(%rsp), %r9d
	movl	60(%rsp), %ecx
	movq	%rax, 16(%rsp)
	xorl	%eax, %eax
.L170:
	cmpl	%eax, %ecx
	jle	.L181
	movl	(%r14,%rax,4), %edx
	movq	8(%rsp), %rsi
	movl	%edx, (%rsi,%rax,4)
	incq	%rax
	jmp	.L170
.L181:
	movq	32(%rsp), %rax
	leaq	(%r14,%rax), %rdx
	xorl	%eax, %eax
.L172:
	cmpl	%eax, %r9d
	jle	.L182
	movl	(%rdx,%rax,4), %esi
	movq	16(%rsp), %rdi
	movl	%esi, (%rdi,%rax,4)
	incq	%rax
	jmp	.L172
.L182:
	movq	16(%rsp), %r8
	movq	8(%rsp), %rdx
	movq	%rbx, %rdi
	movl	4(%rsp), %esi
	call	_Z8mergeAllPiiS_iS_i
	xorl	%eax, %eax
.L174:
	cmpl	%eax, 4(%rsp)
	jle	.L183
	movl	(%rbx,%rax,4), %edx
	movl	%edx, (%r14,%rax,4)
	incq	%rax
	jmp	.L174
.L183:
	movq	%rbx, %rdi
	addl	%r15d, %r13d
	call	free@PLT
	movq	8(%rsp), %rdi
	call	free@PLT
	movq	16(%rsp), %rdi
	call	free@PLT
	movq	24(%rsp), %rax
	addq	%rax, %r14
	movl	48(%rsp), %eax
	jmp	.L179
.L166:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2034:
	.size	_Z10fusionSortPii, .-_Z10fusionSortPii
	.section	.rodata.str1.1
.LC14:
	.string	"========== Path Sort : =========\n"
.LC15:
	.string	"* Size of array : %d\n\n"
.LC17:
	.string	"========= Parallel sort : =============\n"
.LC18:
	.string	"Total time elapsed : %f s\n"
.LC19:
	.string	"Parrallel algorithm is %f times faster than sequential merge !\n"
.LC20:
	.string	"Parrallel merge is %f times faster than sequential merge !\n"
.LC21:
	.string	"========= Sequential sort : =============\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2042:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movl	%edi, %r12d
	xorl	%edi, %edi
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movq	%rsi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movl	$100000, %ebx
	subq	$24, %rsp
	.cfi_def_cfa_offset 64
	call	time@PLT
	movl	%eax, %edi
	call	srand@PLT
	cmpl	$2, %r12d
	jne	.L185
	movq	8(%rbp), %rdi
	call	atoi@PLT
	movl	%eax, %ebx
.L185:
	leaq	.LC14(%rip), %rsi
	movl	$2, %edi
	movslq	%ebx, %rbp
	xorl	%eax, %eax
	call	__printf_chk@PLT
	salq	$2, %rbp
	movl	%ebx, %edx
	movl	$2, %edi
	leaq	.LC15(%rip), %rsi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	%rbp, %rdi
	call	malloc@PLT
	imull	$10, %ebx, %edx
	movl	%ebx, %esi
	movq	%rax, %rdi
	movq	%rax, %r12
	call	_Z19init_array_no_orderPiii
	movq	%rbp, %rdi
	call	malloc@PLT
	movl	%ebx, %edx
	movq	%r12, %rdi
	movq	%rax, %rsi
	movq	%rax, %r13
	call	_Z10copy_arrayPiS_i
	movq	%rbp, %rdi
	call	malloc@PLT
	movl	%ebx, %edx
	movq	%r12, %rdi
	movq	%rax, %rsi
	call	_Z10copy_arrayPiS_i
	call	clock@PLT
	movl	%ebx, %esi
	movq	%r12, %rdi
	movq	%rax, %rbp
	call	_Z10fusionSortPii
	call	cudaDeviceSynchronize@PLT
	movl	$1, %ecx
	movl	$607, %edx
	leaq	.LC13(%rip), %rsi
	movl	%eax, %edi
	call	_Z9gpuAssert9cudaErrorPKcib
	call	clock@PLT
	subq	%rbp, %rax
	cvtsi2ssq	%rax, %xmm0
	divss	.LC16(%rip), %xmm0
	movss	%xmm0, 8(%rsp)
	call	clock@PLT
	movl	%ebx, %esi
	movq	%r13, %rdi
	movq	%rax, %rbp
	call	_Z13fusionSortSeqPii
	call	clock@PLT
	leaq	.LC17(%rip), %rsi
	movl	$2, %edi
	subq	%rbp, %rax
	leaq	.LC18(%rip), %rbp
	cvtsi2ssq	%rax, %xmm0
	xorl	%eax, %eax
	divss	.LC16(%rip), %xmm0
	movd	%xmm0, %ebx
	call	__printf_chk@PLT
	movq	%rbp, %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	8(%rsp), %xmm0
	call	__printf_chk@PLT
	movl	$2, %edi
	leaq	.LC19(%rip), %rsi
	movb	$1, %al
	movd	%ebx, %xmm0
	divss	8(%rsp), %xmm0
	cvtss2sd	%xmm0, %xmm0
	movsd	%xmm0, 8(%rsp)
	call	__printf_chk@PLT
	movsd	8(%rsp), %xmm0
	leaq	.LC20(%rip), %rsi
	movb	$1, %al
	movl	$2, %edi
	call	__printf_chk@PLT
	leaq	.LC21(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movd	%ebx, %xmm2
	movq	%rbp, %rsi
	movb	$1, %al
	movl	$2, %edi
	cvtss2sd	%xmm2, %xmm0
	call	__printf_chk@PLT
	addq	$24, %rsp
	.cfi_def_cfa_offset 40
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2042:
	.size	main, .-main
	.text
	.globl	_Z46__device_stub__Z23pretraitementFusionSortPiS_iPiS_i
	.type	_Z46__device_stub__Z23pretraitementFusionSortPiS_iPiS_i, @function
_Z46__device_stub__Z23pretraitementFusionSortPiS_iPiS_i:
.LFB2073:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L189
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z23pretraitementFusionSortPiS_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L189:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L191
	call	__stack_chk_fail@PLT
.L191:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2073:
	.size	_Z46__device_stub__Z23pretraitementFusionSortPiS_iPiS_i, .-_Z46__device_stub__Z23pretraitementFusionSortPiS_iPiS_i
	.globl	_Z23pretraitementFusionSortPiS_i
	.type	_Z23pretraitementFusionSortPiS_i, @function
_Z23pretraitementFusionSortPiS_i:
.LFB2074:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z23pretraitementFusionSortPiS_iPiS_i
	.cfi_endproc
.LFE2074:
	.size	_Z23pretraitementFusionSortPiS_i, .-_Z23pretraitementFusionSortPiS_i
	.section	.rodata.str1.1
.LC22:
	.string	"_Z23pretraitementFusionSortPiS_i"
.LC23:
	.string	"_Z9pathBig_kiP4int2iPiiS1_i"
.LC24:
	.string	"_Z10mergeBig_kPiiS_iS_iP4int2ii"
.LC25:
	.string	"_Z12mergeSmall_kPiS_S_iii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2076:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC22(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z23pretraitementFusionSortPiS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC23(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z9pathBig_kiP4int2iPiiS1_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC24(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z10mergeBig_kPiiS_iS_iP4int2ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC25(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z12mergeSmall_kPiS_S_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2076:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC16:
	.long	1232348160
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <time.h>
#include <ctime>


//Function that verify cuda calls and return cuda error if any
#define gpuCheck(ans) { gpuAssert((ans), __FILE__, __LINE__); }
inline void gpuAssert(hipError_t code, const char *file, int line, bool abort=true)
{
   if (code != hipSuccess)
   {
      fprintf(stderr,"GPUassert: %s %s %d\n", hipGetErrorString(code), file, line);
      if (abort) exit(code);
   }
}

//Initialise ascendant array with random values in
void init_array(int* array, int size, int const adder=10)
{
    array[0] = rand()%adder;
    for(int i = 0; i < size;i++)
    {
        array[i] = array[i-1] + rand()%adder;
    }
}

//Function that initialise array with random values
void init_array_no_order(int* array, int size, int const adder=10)
{
    array[0] = rand()%adder;
    for(int i = 0; i < size;i++)
    {
        array[i] = rand()%adder;
    }
}

//Function that copy array in another
void copy_array(int* a, int* a_copy, int n){
    for(int i = 0;i < n;i++){
        a_copy[i] = a[i];
    }
}

//Function that print an array of size size
void print_array(int* a, int size)
{
    printf("[");
    for(int i = 0; i < size;i++)
    {
        //printf("i = %d | v = %d " ,i, a[i]);
        printf("%d " ,a[i]);
    }
    printf("]\n");
}

//Globall version of parallel merge of a and b in m with |m|<1024
__global__ void mergeSmall_k(int* d_a, int* d_b, int* d_m, int n_a, int n_b, int n_m){
    int i = threadIdx.x;
    if(i < n_m)
    {
        int2 K;
        int2 P;
        int2 Q;
        if(i > n_a)
        {
            K.x = i - n_a;
            K.y = n_a;
            P.x = n_a;
            P.y = i - n_a;
        }
        else
        {
            K.x = 0;
            K.y = i;
            P.x = i;
            P.y = 0;
        }

        int offset = 0;
        while(1)
        {
            offset = abs(K.y - P.y)/2;
            Q.x = K.x + offset;
            Q.y = K.y - offset;
            if(Q.y >= 0 && Q.x <= n_b && (Q.y == n_a || Q.x == 0 || d_a[Q.y] > d_b[Q.x - 1]))
            {
                if(Q.x == n_b || Q.y == 0 || d_a[Q.y - 1] <= d_b[Q.x])
                {
                    if(Q.y < n_a && (Q.x == n_b || d_a[Q.y] <= d_b[Q.x]))
                    {
                        d_m[i] = d_a[Q.y];
                    }
                    else
                    {
                        d_m[i] = d_b[Q.x];
                    }
                    break;
                }
                else
                {
                    K.x = Q.x + 1;
                    K.y = Q.y - 1;
                }
            }
            else
            {
              P.x = Q.x - 1;
              P.y = Q.y + 1;

            }

        }
    }
}

//Device version of parallel merge of a and b in m with |m|<1024
__device__ void mergeParallel(int* d_a, int* d_b, int* d_m, int n_a, int n_b, int n_m){
    int i = threadIdx.x;
    if(i < n_m)
    {
        int2 K;
        int2 P;
        int2 Q;
        if(i > n_a)
        {
            K.x = i - n_a;
            K.y = n_a;
            P.x = n_a;
            P.y = i - n_a;
        }
        else
        {
            K.x = 0;
            K.y = i;
            P.x = i;
            P.y = 0;
        }

        int offset = 0;
        while(1)
        {
            offset = abs(K.y - P.y)/2;
            Q.x = K.x + offset;
            Q.y = K.y - offset;
            if(Q.y >= 0 && Q.x <= n_b && (Q.y == n_a || Q.x == 0 || d_a[Q.y] > d_b[Q.x - 1]))
            {
                if(Q.x == n_b || Q.y == 0 || d_a[Q.y - 1] <= d_b[Q.x])
                {
                    if(Q.y < n_a && (Q.x == n_b || d_a[Q.y] <= d_b[Q.x]))
                    {
                        d_m[i] = d_a[Q.y];
                    }
                    else
                    {
                        d_m[i] = d_b[Q.x];
                    }
                    break;
                }
                else
                {
                    K.x = Q.x + 1;
                    K.y = Q.y - 1;
                }
            }
            else
            {
              P.x = Q.x - 1;
              P.y = Q.y + 1;

            }

        }
    }
}

//Giving a path ( from pathBig_k ) each block merge (with mergeParallel) each piece a_k and b_k in m_k of a and b. Then it replace elements in m
__global__ void mergeBig_k(int *m, int n_m, int *a, int n_a, int *b, int n_b, int2 *path, int n_path, int nbPartitions)
{
  int blockId = blockIdx.x;
  int threadId = threadIdx.x;
  int i = blockId * blockDim.x + threadId;
  if (blockId <= nbPartitions)//On utilise un block pour chaque partition
  {
    int x0, y0, x1, y1;
    x0 = path[blockId].x;
    y0 = path[blockId].y;
    x1 = path[blockId+1].x;
    y1 = path[blockId+1].y;

    const int dimx=x1-x0;
    const int dimy = y1-y0;

    //A modifier par dimx dimy dimx+dimy
     __shared__ int a_k[1024];
     __shared__ int b_k[1024];
     __shared__ int m_k[1024];

    if (threadId < dimx) //On rempli a_k[i] :  0 <= i < dimx
    {
      a_k[threadId] = a[x0+threadId];
    }
    else if (threadId < dimy+dimx)//On rempli b_k[i] : indice dimx <= i < dimx+dimy+1
    {
      b_k[threadId-dimx] = b[y0+threadId-dimx];
    }
    __syncthreads();
    mergeParallel(a_k, b_k, m_k, dimx, dimy, dimx+dimy);
    m[i] = m_k[threadId];

  }
}

//Function that generate a path to break down m into pieces that could be merge without conflict
//On appelle |m|/TPB blocks avec chacun un seul thread. Chaque thread s'occupe de la diagonale thread
__global__ void pathBig_k(int pas, int2* path, int n_path , int* d_a, int n_a ,int* d_b, int n_b)
{
    int thread_i = blockIdx.x * blockDim.x + threadIdx.x;
    if(thread_i <= (n_a + n_b)/pas)        //<------------//On vérifie que l'indice du thread est inférieur à la taille du tableau de retour et qu'il est un multiple du pas
    {
        int i = thread_i*pas;
        int2 K;
        int2 P;
        int2 Q;
        if(i > n_a)
        {
            K.x = i - n_a;
            K.y = n_a;
            P.x = n_a;
            P.y = i - n_a;
        }
        else
        {
            K.x = 0;
            K.y = i;
            P.x = i;
            P.y = 0;
        }

        int offset = 0;
        while(1)
        {
            //Calcul des coordonnées du milieu de P et K
            offset = abs(K.y - P.y)/2;
            Q.x = K.x + offset;
            Q.y = K.y - offset;

            //
            if(Q.y >= 0 && Q.x <= n_b && (Q.y == n_a || Q.x == 0 || d_a[Q.y] > d_b[Q.x - 1]))
            {
                //
                if(Q.x == n_b || Q.y == 0 || d_a[Q.y - 1] <= d_b[Q.x])
                {
                  break;
                }
                else
                {
                    K.x = Q.x + 1;
                    K.y = Q.y - 1;
                }
            }
            else
            {
              P.x = Q.x - 1;
              P.y = Q.y + 1;

            }

        }
        //printf("thread : %d => (%d, %d)\n", thread_i, Q.y, Q.x);
        //!\\ Problème ordre x et y
        path[thread_i].x=Q.y;
        path[thread_i].y=Q.x;
    }
    //Si |m| n'est pas un mutliple de pas, le thread 0 ajoute (n_a, n_b) à la fin du tableau
    if (thread_i==0 && (n_a+n_b)%pas!=0)
    {
      //printf("thread : %d => (%d, %d)\n", thread_i, n_a, n_b);
      path[n_path-1].x=n_a;
      path[n_path-1].y=n_b;
    }

}

//Function that decide wether to use mergeSmall_k or mergeBig_k giving the size of the pieces
void mergeAll(int* m, int n_m, int* a, int n_a, int* b, int n_b){
    int pas = 1024; // <1024
    int nbPartitions = n_m/pas+(n_m%pas!=0); // On ajoute 1 si n_m n'est pas un mutliple de p
    int n_path = (1 + nbPartitions); //1(pour (0,0)) + |m|/pas(nbr de morceau de taille pas) + 1(si dernier morceau de taille < pas))

    // printf("n_m : %d\nn_a : %d\nn_b : %d\n", n_m, n_a, n_b);
    int *mGPU, *aGPU, *bGPU;
    gpuCheck(hipMalloc(&mGPU, n_m*sizeof(int)));
    gpuCheck(hipMalloc(&aGPU, n_a*sizeof(int)));
    gpuCheck(hipMalloc(&bGPU, n_b*sizeof(int)));

    //Declaration et allocation de path
    int2 *pathGPU;
    gpuCheck(hipMalloc(&pathGPU, n_path*sizeof(int2)));

    gpuCheck(hipMemcpy(aGPU, a, n_a*sizeof(int), hipMemcpyHostToDevice));
    gpuCheck(hipMemcpy(bGPU, b, n_b*sizeof(int), hipMemcpyHostToDevice));

    // printf("n_12 : %d, n_1 : %d, n_2 : %d\n", n_m, n_a, n_b);
    if(n_m <= 1024){
        // printf("case mergeSmall\n");
        // printf("n_m = %d, n_a = %d, n_b = %d\n", n_a, n_b, n_m);
        mergeSmall_k<<<1, 1024>>>(aGPU, bGPU, mGPU, n_a, n_b, n_m);
        gpuCheck( hipPeekAtLastError() );
        //gpuCheck(cudaDeviceSynchronize());
        gpuCheck(hipMemcpy(m, mGPU, n_m*sizeof(int), hipMemcpyDeviceToHost));
    }
    else{
        //================ Parallel : =======================\\
        // printf("\n");
        // printf("case mergeBig\n");
        pathBig_k<<<nbPartitions/1024+1, 1024>>>(pas, pathGPU, n_path, aGPU, n_a, bGPU, n_b);
        gpuCheck( hipPeekAtLastError() );
        gpuCheck( hipDeviceSynchronize() );
        mergeBig_k<<<nbPartitions, pas>>>(mGPU, n_m, aGPU, n_a, bGPU, n_b, pathGPU, n_path, nbPartitions);
        gpuCheck( hipDeviceSynchronize() );

        gpuCheck(hipMemcpy(m, mGPU, n_m*sizeof(int), hipMemcpyDeviceToHost));

        gpuCheck( hipDeviceSynchronize() );
    }
    gpuCheck(hipFree(aGPU));
    gpuCheck(hipFree(bGPU));
    gpuCheck(hipFree(pathGPU));
}

//Fonction de prétraitement qui trie chaque paire contigüe d'éléments d'un tableau m
__global__ void pretraitementFusionSort(int* m, int* mGPU, int n){
    int blockId = blockIdx.x;
    int threadId = threadIdx.x;
    int i = blockId * blockDim.x + threadId;
    int tmp;
    if(i < n/2)
    {
        int indice = 2*i;
        if(mGPU[indice] > mGPU[indice+1])
        {
            tmp = mGPU[indice];
            mGPU[indice] = mGPU[indice+1];
            mGPU[indice+1] = tmp;
        }
    }
}


//Function that sort any array
void fusionSort(int *m, int n_m)
{
  //L1 : indice du premier élément de m_part1
  //R1 : indice du dernier élément de m_part1
  //L2 : indice du premier élément de m_part2
  //R2 : indice du dernier élément de m_part2
  int size = 1;
  int L1, R1, L2, R2;
  int i;

  while (size <= n_m)
  {
    i = 0;
    while(i < n_m){
      // printf("m : ");
      // print_array(m, n_m);
      L1 = i;
      R1 = i + size-1;
      L2 = i + size;
      R2 = i + 2*size-1;
      if(L2 >= n_m){
          break;
      }
      if(R2 >= n_m){
          R2 = n_m-1;
      }
      int size_1 = R1-L1+1;
      int size_2 = R2-L2+1;
      int size_12 = size_1+size_2;
      int *m_12, *m_1, *m_2;
      m_12 = (int*)malloc(size_12*sizeof(int));
      m_1 = (int*)malloc(size_1*sizeof(int));
      m_2 = (int*)malloc(size_2*sizeof(int));

      //Remplir les tableaux m_1 et m_2
      for (int j = 0; j < size_1; j++)
      {
        m_1[j] = m[L1 + j];
      }
      for (int j = 0; j < size_2; j++)
      {
        m_2[j] = m[L2 + j];
      }

      mergeAll(m_12, size_12, m_1, size_1, m_2, size_2);

      for (int j = 0; j < size_12; j++)
      {
        m[L1+j] = m_12[j];
      }
      free(m_12);
      free(m_1);
      free(m_2);
      i = i + 2*size;
    }
    size *= 2;
  }
}


void fusionMergeSeq(int* A, int* tmp, int L1, int R1, int L2, int R2){
    int i = 0;
    while(L1 <= R1 && L2 <= R2){
        if(A[L1] <= A[L2]){
            tmp[i] = A[L1];
            i++;
            L1++;
        }
        else{
            tmp[i] = A[L2];
            i++;
            L2++;
        }
    }
    while(L1 <= R1){
        tmp[i] = A[L1];
        i++;
        L1++;
    }
    while(L2 <= R2){
        tmp[i] = A[L2];
        i++;
        L2++;
    }

}

void fusionSortSeq(int* A, int n){
    int len = 1;
    int i;
    int L1, R1, L2, R2;
    int* tmp = (int*)malloc(n*sizeof(int));
    while(len < n){
        i = 0;
        while(i < n){
            L1 = i;
            R1 = i + len - 1;
            L2 = i + len;
            R2 = i + 2*len - 1;
            tmp = (int*)realloc(tmp, (R2-L1+1)*sizeof(int));
            if(L2 >= n){
                break;
            }
            if(R2 >= n){
                R2 = n - 1;
            }
            fusionMergeSeq(A, tmp, L1, R1, L2, R2);
            for(int j = 0;j < R2-L1+1;j++){
                A[i+j] = tmp[j];
            }
            i = i + 2*len;
        }
        len *= 2;
    }
    free(tmp);
}

//Fonction qui trie un tableau M en parallèle par tri fusion itératif (question 3)

//Fonctions de vérification

//Fonction qui vérifie qu'un tableau est bien trié (tous ses éléments rangés dans l'ordre croissant)
int assertOrder(int *tab, int size){
  for (int i=0; i<size-1; i++){
    if (tab[i] > tab[i+1]){
      printf("WARNING : Unsuccessful merge or sort ... : unordered array on indice %d ...\n", i);
      printf("tab[i]= %d > tab[i+1] = %d\n", tab[i], tab[i+1]);
      return 0;
    }
  }
  return 1;
}

//Fonction qui vérifie qu'on retrouve bien dans le nouveau tableau tous les éléments des deux tableaux qu'on veut fusionner
int assertMergeAllValuesPresent(int *tab, int n1, int *tab2, int n2, int* m, int size)
{
  int verif[size]; //tableau avec des 1 là où l'on a déjà vérifié qu'il correspond déjà à un élément de a ou de b
  for(int i = 0;i<size;i++){
      verif[i] = 0;
  }

  for (int i=0; i<size; i++){
    for(int j = 0;j < n1;j++){
      if(tab[j] == m[i] && verif[i] == 0){ //si il y a une valeur identique et que celle-ci n'a pas été vérifiée
          verif[i] = 1;
      }
    }
  }
  for (int i=0; i<size; i++){
    for(int j = 0;j < n2;j++){
      if(tab2[j] == m[i] && verif[i] == 0){
          verif[i] = 1;
      }
    }
  }

  for(int i = 0;i<size;i++){
    if(verif[i] != 1){
        printf("\nWARNING : Unsuccessful merge : incorrect elements...\n");
        return 0;
    }
  }

  return 1;
}

//Fonction qui vérifie qu'on retrouve bien dans le nouveau tableau tous les éléments du tableau qu'on veut trier
int assertSortAllValuesPresent(int* m, int* m_sorted, int size){
  int verif[size]; //tableau avec des 1 là où l'on a déjà vérifié qu'il correspond déjà à un élément de a ou de b
  for(int i = 0;i<size;i++){
      verif[i] = 0;
  }

  for (int i=0; i<size; i++){
    for(int j = 0;j < size;j++){
      if(m_sorted[j] == m[i]){ //si il y a une valeur identique
          verif[i] = 1;
      }
    }
  }

  for(int i = 0;i<size;i++){
    if(verif[i] != 1){
        printf("i : %d\n", i);
        printf("\nWARNING : Unsuccessful sort : incorrect elements...\n");
        return 0;
    }
  }

  return 1;
}

//Fonction qui vérifie qu'un tableau est bien trié et la fusion de deux tableaux
//tab et tab2 : les deux tableaux qu'on veut fusionner
//m : le tableau qui est la fusion triée de tab et tab2
int assertMerge(int *tab, int n1, int *tab2, int n2, int* m, int size){
    int successfulOrder = assertOrder(m, size);
    int successfulElements = assertMergeAllValuesPresent(tab, n1, tab2, n2, m, size);
    //assertMergeAllValuesPresent(int *tab, int n1, int *tab2, int n2, int* m, int size)
    if(successfulOrder && successfulElements){
        printf("\nSuccessful merge !\n");
        return 1;
    }
    else{
        printf("\nUnsuccessful merge !\n");
        return 0;
    }
}

//Fonction qui vérifie qu'un tableau est bien trié
//m : le tableau non trié qu'on veut trier
//m_sorted : le tableau m soi-disant trié (on veut vérifier si c'est bien le cas)
//size : la taille du tableau
int assertSorted(int* m, int* m_sorted, int size)
{
    int successfulOrder = assertOrder(m_sorted, size); // les éléments du tableau sont ils bien dans le bon ordre ?
    int successfulElements = assertSortAllValuesPresent(m, m_sorted, size); //retrouve t-on bien toutes les valeurs ?
    if(successfulOrder && successfulElements){
        printf("\nSuccessful sort !\n");
        return 1;
    }
    else{
        printf("\nUnsuccessful sort !\n");
        return 0;
    }
}

int main(int argc, char *argv[])
{
    std::clock_t startS, endS;
    float seqMergeTime, parMergeTime;

    srand(time(NULL));
    int n_m = 100000;
    int *m, *mseq, *mref;

    if(argc==2)
    {
      n_m = atoi(argv[1]);
    }

    printf("========== Path Sort : =========\n");
    printf("* Size of array : %d\n\n", n_m);
    //int* mseq;
    m = (int*)malloc(n_m*sizeof(int));
    init_array_no_order(m, n_m, n_m*10);
    mseq = (int*)malloc(n_m*sizeof(int)); //copie de m
    copy_array(m, mseq, n_m);
    mref = (int*)malloc(n_m*sizeof(int)); //copie de m
    copy_array(m, mref, n_m);
    //Partie des calculs1024
    //================ Paral1024lel : =======================\\
    //Etape de prétraitement :
    startS = std::clock();
    fusionSort(m, n_m);
    gpuCheck(hipDeviceSynchronize());
    endS = std::clock();
    parMergeTime = (endS - startS) / (float) CLOCKS_PER_SEC;
    //Etape du tri fusion :

    startS = std::clock();
    fusionSortSeq(mseq, n_m);
    endS = std::clock();
    seqMergeTime = (endS - startS) / (float) CLOCKS_PER_SEC;

    printf("========= Parallel sort : =============\n");
    printf("Total time elapsed : %f s\n", parMergeTime);
    // assertSorted(mref, m, n_m);
    printf("Parrallel algorithm is %f times faster than sequential merge !\n", seqMergeTime/parMergeTime);
    printf("Parrallel merge is %f times faster than sequential merge !\n", seqMergeTime/parMergeTime);

    printf("========= Sequential sort : =============\n");
    printf("Total time elapsed : %f s\n", seqMergeTime);
    // assertSorted(mref, mseq, n_m);




    return 0;
}

	.text
	.file	"pathSortFinal.hip"
	.globl	_Z10init_arrayPiii              # -- Begin function _Z10init_arrayPiii
	.type	_Z10init_arrayPiii,@function
_Z10init_arrayPiii:                     # @_Z10init_arrayPiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edx, %ebx
	movl	%esi, %ebp
	movq	%rdi, %r14
	callq	rand
	cltd
	idivl	%ebx
	movl	%edx, (%r14)
	testl	%ebp, %ebp
	jle	.LBB0_3
# %bb.1:                                # %.lr.ph.preheader
	movl	%ebp, %r15d
	xorl	%r12d, %r12d
.LBB0_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	-4(%r14,%r12,4), %ebp
	callq	rand
	cltd
	idivl	%ebx
	addl	%ebp, %edx
	movl	%edx, (%r14,%r12,4)
	incq	%r12
	cmpq	%r12, %r15
	jne	.LBB0_2
.LBB0_3:                                # %._crit_edge
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z10init_arrayPiii, .Lfunc_end0-_Z10init_arrayPiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z19init_array_no_orderPiii     # -- Begin function _Z19init_array_no_orderPiii
	.type	_Z19init_array_no_orderPiii,@function
_Z19init_array_no_orderPiii:            # @_Z19init_array_no_orderPiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edx, %ebx
	movl	%esi, %ebp
	movq	%rdi, %r14
	callq	rand
	cltd
	idivl	%ebx
	movl	%edx, (%r14)
	testl	%ebp, %ebp
	jle	.LBB1_3
# %bb.1:                                # %.lr.ph.preheader
	movl	%ebp, %r15d
	xorl	%r12d, %r12d
.LBB1_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	cltd
	idivl	%ebx
	movl	%edx, (%r14,%r12,4)
	incq	%r12
	cmpq	%r12, %r15
	jne	.LBB1_2
.LBB1_3:                                # %._crit_edge
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z19init_array_no_orderPiii, .Lfunc_end1-_Z19init_array_no_orderPiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z10copy_arrayPiS_i             # -- Begin function _Z10copy_arrayPiS_i
	.type	_Z10copy_arrayPiS_i,@function
_Z10copy_arrayPiS_i:                    # @_Z10copy_arrayPiS_i
	.cfi_startproc
# %bb.0:
	testl	%edx, %edx
	jle	.LBB2_3
# %bb.1:                                # %.lr.ph.preheader
	movl	%edx, %eax
	xorl	%ecx, %ecx
.LBB2_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	(%rdi,%rcx,4), %edx
	movl	%edx, (%rsi,%rcx,4)
	incq	%rcx
	cmpq	%rcx, %rax
	jne	.LBB2_2
.LBB2_3:                                # %._crit_edge
	retq
.Lfunc_end2:
	.size	_Z10copy_arrayPiS_i, .Lfunc_end2-_Z10copy_arrayPiS_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z11print_arrayPii              # -- Begin function _Z11print_arrayPii
	.type	_Z11print_arrayPii,@function
_Z11print_arrayPii:                     # @_Z11print_arrayPii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%esi, %ebp
	movq	%rdi, %rbx
	movl	$91, %edi
	callq	putchar@PLT
	testl	%ebp, %ebp
	jle	.LBB3_3
# %bb.1:                                # %.lr.ph.preheader
	movl	%ebp, %r14d
	xorl	%r15d, %r15d
.LBB3_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	(%rbx,%r15,4), %esi
	movl	$.L.str.1, %edi
	xorl	%eax, %eax
	callq	printf
	incq	%r15
	cmpq	%r15, %r14
	jne	.LBB3_2
.LBB3_3:                                # %._crit_edge
	movl	$.Lstr, %edi
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	puts@PLT                        # TAILCALL
.Lfunc_end3:
	.size	_Z11print_arrayPii, .Lfunc_end3-_Z11print_arrayPii
	.cfi_endproc
                                        # -- End function
	.globl	_Z27__device_stub__mergeSmall_kPiS_S_iii # -- Begin function _Z27__device_stub__mergeSmall_kPiS_S_iii
	.type	_Z27__device_stub__mergeSmall_kPiS_S_iii,@function
_Z27__device_stub__mergeSmall_kPiS_S_iii: # @_Z27__device_stub__mergeSmall_kPiS_S_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12mergeSmall_kPiS_S_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z27__device_stub__mergeSmall_kPiS_S_iii, .Lfunc_end4-_Z27__device_stub__mergeSmall_kPiS_S_iii
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii # -- Begin function _Z25__device_stub__mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii
	.type	_Z25__device_stub__mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii,@function
_Z25__device_stub__mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii: # @_Z25__device_stub__mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	48(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z25__device_stub__mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii, .Lfunc_end5-_Z25__device_stub__mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i # -- Begin function _Z24__device_stub__pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i
	.type	_Z24__device_stub__pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i,@function
_Z24__device_stub__pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i: # @_Z24__device_stub__pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	56(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z24__device_stub__pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i, .Lfunc_end6-_Z24__device_stub__pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z8mergeAllPiiS_iS_i            # -- Begin function _Z8mergeAllPiiS_iS_i
	.type	_Z8mergeAllPiiS_iS_i,@function
_Z8mergeAllPiiS_iS_i:                   # @_Z8mergeAllPiiS_iS_i
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
                                        # kill: def $r9d killed $r9d def $r9
	movq	%r9, 24(%rsp)                   # 8-byte Spill
	movq	%r8, 72(%rsp)                   # 8-byte Spill
	movl	%ecx, %r13d
	movq	%rdx, 80(%rsp)                  # 8-byte Spill
	movl	%esi, %r12d
	movl	$1023, %eax                     # imm = 0x3FF
	leal	(%r12,%rax), %r14d
	testl	%esi, %esi
	cmovnsl	%esi, %r14d
	movq	%rdi, %rbx
	sarl	$10, %r14d
	andl	%esi, %eax
	cmpl	$1, %eax
	sbbl	$-1, %r14d
	movslq	%esi, %rsi
	shlq	$2, %rsi
	leaq	32(%rsp), %rdi
	movq	%rsi, 64(%rsp)                  # 8-byte Spill
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB7_1
# %bb.3:                                # %_Z9gpuAssert10hipError_tPKcib.exit
	movq	%rbx, 56(%rsp)                  # 8-byte Spill
	movl	%r13d, %r15d
	movslq	%r13d, %rbp
	shlq	$2, %rbp
	leaq	16(%rsp), %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB7_41
# %bb.4:                                # %_Z9gpuAssert10hipError_tPKcib.exit45
	movslq	24(%rsp), %r13                  # 4-byte Folded Reload
	shlq	$2, %r13
	leaq	8(%rsp), %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB7_5
# %bb.7:                                # %_Z9gpuAssert10hipError_tPKcib.exit47
	leal	1(%r14), %eax
	movq	%rax, 48(%rsp)                  # 8-byte Spill
	movslq	%eax, %rsi
	shlq	$3, %rsi
	leaq	40(%rsp), %rdi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB7_8
# %bb.9:                                # %_Z9gpuAssert10hipError_tPKcib.exit49
	movq	16(%rsp), %rdi
	movq	80(%rsp), %rsi                  # 8-byte Reload
	movq	%rbp, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB7_10
# %bb.11:                               # %_Z9gpuAssert10hipError_tPKcib.exit51
	movq	8(%rsp), %rdi
	movq	72(%rsp), %rsi                  # 8-byte Reload
	movq	%r13, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB7_12
# %bb.13:                               # %_Z9gpuAssert10hipError_tPKcib.exit53
	cmpl	$1024, %r12d                    # imm = 0x400
	jg	.LBB7_20
# %bb.14:
	movabsq	$4294968320, %rdx               # imm = 0x100000400
	leaq	-1023(%rdx), %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_16
# %bb.15:
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	32(%rsp), %rdx
	movl	%r15d, %ecx
	movq	24(%rsp), %r8                   # 8-byte Reload
                                        # kill: def $r8d killed $r8d killed $r8
	movl	%r12d, %r9d
	callq	_Z27__device_stub__mergeSmall_kPiS_S_iii
.LBB7_16:
	callq	hipPeekAtLastError
	testl	%eax, %eax
	jne	.LBB7_17
# %bb.18:                               # %_Z9gpuAssert10hipError_tPKcib.exit55
	movq	32(%rsp), %rsi
	movq	56(%rsp), %rdi                  # 8-byte Reload
	movq	64(%rsp), %rdx                  # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	je	.LBB7_34
# %bb.19:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.20, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$313, %r8d                      # imm = 0x139
	jmp	.LBB7_6
.LBB7_20:
	movabsq	$4294968320, %rbx               # imm = 0x100000400
	movl	%r14d, %eax
	shrl	$10, %eax
	leaq	(%rax,%rbx), %rdi
	addq	$-1023, %rdi                    # imm = 0xFC01
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_22
# %bb.21:
	movq	40(%rsp), %rsi
	movq	16(%rsp), %rcx
	movq	8(%rsp), %r9
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movl	$1024, %edi                     # imm = 0x400
	movq	56(%rsp), %rdx                  # 8-byte Reload
                                        # kill: def $edx killed $edx killed $rdx
	movl	%r15d, %r8d
	pushq	32(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	callq	_Z24__device_stub__pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
.LBB7_22:
	callq	hipPeekAtLastError
	testl	%eax, %eax
	jne	.LBB7_23
# %bb.24:                               # %_Z9gpuAssert10hipError_tPKcib.exit59
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB7_25
# %bb.26:                               # %_Z9gpuAssert10hipError_tPKcib.exit61
	movl	%r14d, %eax
	leaq	(%rbx,%rax), %rdi
	addq	$-1024, %rdi                    # imm = 0xFC00
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_28
# %bb.27:
	movq	32(%rsp), %rdi
	movq	16(%rsp), %rdx
	movq	8(%rsp), %r8
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movl	%r12d, %esi
	movl	%r15d, %ecx
	movq	32(%rsp), %r9                   # 8-byte Reload
                                        # kill: def $r9d killed $r9d killed $r9
	pushq	%r14
	.cfi_adjust_cfa_offset 8
	pushq	64(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	64(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z25__device_stub__mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
.LBB7_28:
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB7_29
# %bb.30:                               # %_Z9gpuAssert10hipError_tPKcib.exit63
	movq	32(%rsp), %rsi
	movq	56(%rsp), %rdi                  # 8-byte Reload
	movq	64(%rsp), %rdx                  # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB7_31
# %bb.32:                               # %_Z9gpuAssert10hipError_tPKcib.exit65
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB7_33
.LBB7_34:                               # %_Z9gpuAssert10hipError_tPKcib.exit57
	movq	16(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB7_35
# %bb.36:                               # %_Z9gpuAssert10hipError_tPKcib.exit69
	movq	8(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB7_37
# %bb.38:                               # %_Z9gpuAssert10hipError_tPKcib.exit71
	movq	40(%rsp), %rdi
	callq	hipFree
	testl	%eax, %eax
	jne	.LBB7_39
# %bb.40:                               # %_Z9gpuAssert10hipError_tPKcib.exit73
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB7_1:
	.cfi_def_cfa_offset 144
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.20, %esi
	movl	$.L.str.3, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$295, %r8d                      # imm = 0x127
	jmp	.LBB7_2
.LBB7_41:
	movl	%eax, %r13d
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.20, %esi
	movl	$.L.str.3, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$296, %r8d                      # imm = 0x128
	xorl	%eax, %eax
	callq	fprintf
	movl	%r13d, %edi
	callq	exit
.LBB7_5:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.20, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$297, %r8d                      # imm = 0x129
	jmp	.LBB7_6
.LBB7_8:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.20, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$301, %r8d                      # imm = 0x12D
	jmp	.LBB7_6
.LBB7_10:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.20, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$303, %r8d                      # imm = 0x12F
	jmp	.LBB7_6
.LBB7_12:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.20, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$304, %r8d                      # imm = 0x130
	jmp	.LBB7_6
.LBB7_35:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.20, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$329, %r8d                      # imm = 0x149
	jmp	.LBB7_6
.LBB7_37:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.20, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$330, %r8d                      # imm = 0x14A
	jmp	.LBB7_6
.LBB7_39:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.20, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$331, %r8d                      # imm = 0x14B
	jmp	.LBB7_6
.LBB7_17:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.20, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$311, %r8d                      # imm = 0x137
	jmp	.LBB7_6
.LBB7_23:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.20, %esi
	movl	$.L.str.3, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$320, %r8d                      # imm = 0x140
	jmp	.LBB7_2
.LBB7_25:
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.20, %esi
	movl	$.L.str.3, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$321, %r8d                      # imm = 0x141
.LBB7_2:
	xorl	%eax, %eax
	callq	fprintf
	movl	%ebp, %edi
	callq	exit
.LBB7_29:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.20, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$323, %r8d                      # imm = 0x143
	jmp	.LBB7_6
.LBB7_31:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.20, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$325, %r8d                      # imm = 0x145
	jmp	.LBB7_6
.LBB7_33:
	movl	%eax, %ebx
	movq	stderr(%rip), %r14
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.20, %esi
	movl	$.L.str.3, %ecx
	movq	%r14, %rdi
	movq	%rax, %rdx
	movl	$327, %r8d                      # imm = 0x147
.LBB7_6:
	xorl	%eax, %eax
	callq	fprintf
	movl	%ebx, %edi
	callq	exit
.Lfunc_end7:
	.size	_Z8mergeAllPiiS_iS_i, .Lfunc_end7-_Z8mergeAllPiiS_iS_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z38__device_stub__pretraitementFusionSortPiS_i # -- Begin function _Z38__device_stub__pretraitementFusionSortPiS_i
	.type	_Z38__device_stub__pretraitementFusionSortPiS_i,@function
_Z38__device_stub__pretraitementFusionSortPiS_i: # @_Z38__device_stub__pretraitementFusionSortPiS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z23pretraitementFusionSortPiS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end8:
	.size	_Z38__device_stub__pretraitementFusionSortPiS_i, .Lfunc_end8-_Z38__device_stub__pretraitementFusionSortPiS_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z10fusionSortPii               # -- Begin function _Z10fusionSortPii
	.type	_Z10fusionSortPii,@function
_Z10fusionSortPii:                      # @_Z10fusionSortPii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$120, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rdi, 48(%rsp)                  # 8-byte Spill
	testl	%esi, %esi
	jle	.LBB9_10
# %bb.1:                                # %.lr.ph80.preheader
	movl	$1, %ebx
	movl	%esi, 8(%rsp)                   # 4-byte Spill
.LBB9_2:                                # %.lr.ph80
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB9_3 Depth 2
	movl	%ebx, %r15d
	leal	(%r15,%r15), %ebx
	movl	%r15d, %eax
	leaq	(,%rax,4), %rcx
	movq	%rcx, 64(%rsp)                  # 8-byte Spill
	cmpq	$1, %rax
	adcq	$0, %rax
	leaq	(,%rbx,4), %rcx
	movq	%rcx, 56(%rsp)                  # 8-byte Spill
	shlq	$2, %rax
	movq	%rax, 72(%rsp)                  # 8-byte Spill
	movq	%r15, 24(%rsp)                  # 8-byte Spill
                                        # kill: def $r15d killed $r15d killed $r15 def $r15
	negl	%r15d
	xorl	%r14d, %r14d
	movl	$-1, %ecx
	movq	48(%rsp), %rbp                  # 8-byte Reload
	movl	%ebx, %edx
	movq	%rbx, 80(%rsp)                  # 8-byte Spill
.LBB9_3:                                #   Parent Loop BB9_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	cmpl	%edx, %esi
	movl	%edx, %r13d
	cmovll	%esi, %r13d
	movq	24(%rsp), %rax                  # 8-byte Reload
	addl	%r14d, %eax
	cmpl	%esi, %eax
	jge	.LBB9_9
# %bb.4:                                # %.preheader
                                        #   in Loop: Header=BB9_3 Depth=2
	movl	%edx, 20(%rsp)                  # 4-byte Spill
	movq	%r14, 96(%rsp)                  # 8-byte Spill
	leal	(%r15,%r13), %ebx
	movq	%rcx, 112(%rsp)                 # 8-byte Spill
	addl	%r13d, %ecx
	movq	%rcx, 88(%rsp)                  # 8-byte Spill
	leal	1(%rcx), %eax
	movl	%eax, 12(%rsp)                  # 4-byte Spill
	movslq	%eax, %rdi
	shlq	$2, %rdi
	movq	%r15, 32(%rsp)                  # 8-byte Spill
	callq	malloc
	movq	%rax, 104(%rsp)                 # 8-byte Spill
	movq	64(%rsp), %r15                  # 8-byte Reload
	movq	%r15, %rdi
	callq	malloc
	movq	%rax, %r14
	movl	%ebx, 16(%rsp)                  # 4-byte Spill
	movslq	%ebx, %rbx
	leaq	(,%rbx,4), %rdi
	callq	malloc
	movq	%rax, %r12
	movq	%r14, 40(%rsp)                  # 8-byte Spill
	movq	%r14, %rdi
	movq	32(%rsp), %r14                  # 8-byte Reload
	movq	%rbp, %rsi
	movq	72(%rsp), %rdx                  # 8-byte Reload
	callq	memcpy@PLT
	testl	%ebx, %ebx
	jle	.LBB9_6
# %bb.5:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB9_3 Depth=2
	leaq	(%r15,%rbp), %rsi
	leal	(%r14,%r13), %eax
	decl	%eax
	leaq	4(,%rax,4), %rdx
	movq	%r12, %rdi
	callq	memcpy@PLT
.LBB9_6:                                # %._crit_edge
                                        #   in Loop: Header=BB9_3 Depth=2
	movq	104(%rsp), %r13                 # 8-byte Reload
	movq	%r13, %rdi
	movl	12(%rsp), %r14d                 # 4-byte Reload
	movl	%r14d, %esi
	movq	40(%rsp), %rdx                  # 8-byte Reload
	movq	24(%rsp), %rcx                  # 8-byte Reload
                                        # kill: def $ecx killed $ecx killed $rcx
	movq	%r12, %r15
	movq	%r12, %r8
	movl	16(%rsp), %r9d                  # 4-byte Reload
	callq	_Z8mergeAllPiiS_iS_i
	testl	%r14d, %r14d
	movq	80(%rsp), %rbx                  # 8-byte Reload
	movq	96(%rsp), %r14                  # 8-byte Reload
	jle	.LBB9_8
# %bb.7:                                # %.lr.ph77.preheader
                                        #   in Loop: Header=BB9_3 Depth=2
	movq	88(%rsp), %rax                  # 8-byte Reload
	leaq	4(,%rax,4), %rdx
	movq	%rbp, %rdi
	movq	%r13, %rsi
	callq	memcpy@PLT
.LBB9_8:                                # %._crit_edge78
                                        #   in Loop: Header=BB9_3 Depth=2
	addl	%ebx, %r14d
	movq	%r13, %rdi
	callq	free
	movq	40(%rsp), %rdi                  # 8-byte Reload
	callq	free
	movq	%r15, %rdi
	callq	free
	movl	20(%rsp), %edx                  # 4-byte Reload
	addl	%ebx, %edx
	movq	32(%rsp), %r15                  # 8-byte Reload
	subl	%ebx, %r15d
	movq	112(%rsp), %rcx                 # 8-byte Reload
	subl	%ebx, %ecx
	addq	56(%rsp), %rbp                  # 8-byte Folded Reload
	movl	8(%rsp), %esi                   # 4-byte Reload
	cmpl	%esi, %r14d
	jl	.LBB9_3
.LBB9_9:                                # %._crit_edge81
                                        #   in Loop: Header=BB9_2 Depth=1
	cmpl	%esi, %ebx
	jle	.LBB9_2
.LBB9_10:                               # %._crit_edge85
	addq	$120, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end9:
	.size	_Z10fusionSortPii, .Lfunc_end9-_Z10fusionSortPii
	.cfi_endproc
                                        # -- End function
	.globl	_Z14fusionMergeSeqPiS_iiii      # -- Begin function _Z14fusionMergeSeqPiS_iiii
	.type	_Z14fusionMergeSeqPiS_iiii,@function
_Z14fusionMergeSeqPiS_iiii:             # @_Z14fusionMergeSeqPiS_iiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset %rbx, -24
	.cfi_offset %rbp, -16
                                        # kill: def $r9d killed $r9d def $r9
                                        # kill: def $r8d killed $r8d def $r8
                                        # kill: def $ecx killed $ecx def $rcx
                                        # kill: def $edx killed $edx def $rdx
	xorl	%eax, %eax
	cmpl	%ecx, %edx
	jg	.LBB10_4
# %bb.1:
	cmpl	%r9d, %r8d
	jg	.LBB10_4
# %bb.2:                                # %.lr.ph.preheader
	xorl	%eax, %eax
.LBB10_3:                               # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movslq	%edx, %rdx
	movl	(%rdi,%rdx,4), %r10d
	movslq	%r8d, %r8
	movl	(%rdi,%r8,4), %r11d
	xorl	%ebx, %ebx
	xorl	%ebp, %ebp
	cmpl	%r11d, %r10d
	setle	%bl
	setg	%bpl
	cmovll	%r10d, %r11d
	addl	%ebp, %r8d
	addl	%ebx, %edx
	movl	%r11d, (%rsi,%rax,4)
	incq	%rax
	cmpl	%ecx, %edx
	jg	.LBB10_4
# %bb.12:                               # %.lr.ph
                                        #   in Loop: Header=BB10_3 Depth=1
	cmpl	%r9d, %r8d
	jle	.LBB10_3
.LBB10_4:                               # %.preheader45
	cmpl	%ecx, %edx
	jg	.LBB10_8
# %bb.5:                                # %.lr.ph54.preheader
	movl	%eax, %eax
	movslq	%edx, %r10
	leaq	(%rdi,%r10,4), %r10
	subl	%edx, %ecx
	incl	%ecx
	leaq	(%rsi,%rax,4), %r11
	xorl	%edx, %edx
.LBB10_6:                               # %.lr.ph54
                                        # =>This Inner Loop Header: Depth=1
	movl	(%r10,%rdx,4), %ebx
	movl	%ebx, (%r11,%rdx,4)
	incq	%rdx
	cmpl	%edx, %ecx
	jne	.LBB10_6
# %bb.7:                                # %.preheader.loopexit
	addl	%edx, %eax
.LBB10_8:                               # %.preheader
	cmpl	%r9d, %r8d
	jg	.LBB10_11
# %bb.9:                                # %.lr.ph59.preheader
	movl	%eax, %ecx
	movslq	%r8d, %rax
	leaq	(%rdi,%rax,4), %rax
	subl	%r8d, %r9d
	incl	%r9d
	leaq	(%rsi,%rcx,4), %rcx
	xorl	%edx, %edx
.LBB10_10:                              # %.lr.ph59
                                        # =>This Inner Loop Header: Depth=1
	movl	(%rax,%rdx,4), %esi
	movl	%esi, (%rcx,%rdx,4)
	incq	%rdx
	cmpl	%edx, %r9d
	jne	.LBB10_10
.LBB10_11:                              # %._crit_edge
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end10:
	.size	_Z14fusionMergeSeqPiS_iiii, .Lfunc_end10-_Z14fusionMergeSeqPiS_iiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z13fusionSortSeqPii            # -- Begin function _Z13fusionSortSeqPii
	.type	_Z13fusionSortSeqPii,@function
_Z13fusionSortSeqPii:                   # @_Z13fusionSortSeqPii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%esi, %r13d
	movq	%rdi, 16(%rsp)                  # 8-byte Spill
	movslq	%esi, %rbx
	leaq	(,%rbx,4), %rdi
	callq	malloc
	cmpl	$2, %ebx
	jl	.LBB11_8
# %bb.1:                                # %.lr.ph51.preheader
	movl	$1, %r15d
	movl	%r13d, 12(%rsp)                 # 4-byte Spill
.LBB11_2:                               # %.lr.ph51
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB11_4 Depth 2
	movl	%r15d, %ecx
	leal	(%rcx,%rcx), %r15d
	leaq	(,%r15,4), %rdx
	movq	%rcx, 64(%rsp)                  # 8-byte Spill
	decl	%ecx
	movq	%rcx, 48(%rsp)                  # 8-byte Spill
	movl	$0, 8(%rsp)                     # 4-byte Folded Spill
	movq	16(%rsp), %rcx                  # 8-byte Reload
	movq	%rcx, 24(%rsp)                  # 8-byte Spill
	movl	%r15d, %ebx
	xorl	%ebp, %ebp
	movq	%r15, 56(%rsp)                  # 8-byte Spill
	movq	%rdx, 32(%rsp)                  # 8-byte Spill
.LBB11_4:                               #   Parent Loop BB11_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	cmpl	%ebx, %r13d
	movl	%ebx, %r14d
	cmovll	%r13d, %r14d
	movq	64(%rsp), %rcx                  # 8-byte Reload
	leal	(%rcx,%rbp), %r12d
	movq	%rax, %rdi
	movq	32(%rsp), %rsi                  # 8-byte Reload
	callq	realloc
	cmpl	%r13d, %r12d
	jge	.LBB11_7
# %bb.5:                                #   in Loop: Header=BB11_4 Depth=2
	addl	%ebp, %r15d
	movq	48(%rsp), %rcx                  # 8-byte Reload
	addl	%ebp, %ecx
	cmpl	%r13d, %r15d
                                        # kill: def $r13d killed $r13d def $r13
	cmovll	%r15d, %r13d
	leal	-1(%r13), %r9d
	movq	16(%rsp), %rdi                  # 8-byte Reload
	movq	%rax, 40(%rsp)                  # 8-byte Spill
	movq	%rax, %rsi
	movl	%ebp, %edx
	movl	%r12d, %r8d
	callq	_Z14fusionMergeSeqPiS_iiii
	cmpl	%ebp, %r13d
	movl	8(%rsp), %ebp                   # 4-byte Reload
	movq	24(%rsp), %r12                  # 8-byte Reload
	jle	.LBB11_3
# %bb.6:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB11_4 Depth=2
	addl	%ebp, %r14d
	shlq	$2, %r14
	movq	%r12, %rdi
	movq	40(%rsp), %rsi                  # 8-byte Reload
	movq	%r14, %rdx
	callq	memcpy@PLT
.LBB11_3:                               # %.loopexit
                                        #   in Loop: Header=BB11_4 Depth=2
	movq	56(%rsp), %rax                  # 8-byte Reload
	addl	%eax, %ebx
	subl	%eax, %ebp
	movl	%ebp, 8(%rsp)                   # 4-byte Spill
	movq	32(%rsp), %rdx                  # 8-byte Reload
	addq	%rdx, %r12
	movq	%r12, 24(%rsp)                  # 8-byte Spill
	movl	%r15d, %ebp
	movl	12(%rsp), %r13d                 # 4-byte Reload
	cmpl	%r13d, %r15d
	movq	%rax, %r15
	movq	40(%rsp), %rax                  # 8-byte Reload
	jl	.LBB11_4
.LBB11_7:                               # %._crit_edge
                                        #   in Loop: Header=BB11_2 Depth=1
	cmpl	%r13d, %r15d
	jl	.LBB11_2
.LBB11_8:                               # %._crit_edge56
	movq	%rax, %rdi
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	free                            # TAILCALL
.Lfunc_end11:
	.size	_Z13fusionSortSeqPii, .Lfunc_end11-_Z13fusionSortSeqPii
	.cfi_endproc
                                        # -- End function
	.globl	_Z11assertOrderPii              # -- Begin function _Z11assertOrderPii
	.type	_Z11assertOrderPii,@function
_Z11assertOrderPii:                     # @_Z11assertOrderPii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	%esi, %ebx
	movq	%rdi, %r14
	decl	%ebx
	xorl	%r12d, %r12d
	testl	%ebx, %ebx
	movl	$0, %eax
	cmovgl	%ebx, %eax
.LBB12_1:                               # =>This Inner Loop Header: Depth=1
	movq	%r12, %r15
	cmpq	%r12, %rax
	je	.LBB12_4
# %bb.2:                                #   in Loop: Header=BB12_1 Depth=1
	movl	(%r14,%r15,4), %ecx
	leaq	1(%r15), %r12
	cmpl	4(%r14,%r15,4), %ecx
	jle	.LBB12_1
# %bb.3:
	leal	-1(%r12), %esi
	movl	$.L.str.4, %edi
	xorl	%eax, %eax
	callq	printf
	movl	-4(%r14,%r12,4), %esi
	movl	(%r14,%r12,4), %edx
	movl	$.L.str.5, %edi
	xorl	%eax, %eax
	callq	printf
.LBB12_4:                               # %.loopexit
	movslq	%ebx, %rcx
	xorl	%eax, %eax
	cmpq	%rcx, %r15
	setge	%al
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end12:
	.size	_Z11assertOrderPii, .Lfunc_end12-_Z11assertOrderPii
	.cfi_endproc
                                        # -- End function
	.globl	_Z27assertMergeAllValuesPresentPiiS_iS_i # -- Begin function _Z27assertMergeAllValuesPresentPiiS_iS_i
	.type	_Z27assertMergeAllValuesPresentPiiS_iS_i,@function
_Z27assertMergeAllValuesPresentPiiS_iS_i: # @_Z27assertMergeAllValuesPresentPiiS_iS_i
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$24, %rsp
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%r9d, %r14d
	movq	%rsp, %rbx
	leaq	15(,%r14,4), %rax
	andq	$-16, %rax
	subq	%rax, %rbx
	movq	%rbx, %rsp
	movb	$1, %r13b
	testl	%r9d, %r9d
	jle	.LBB13_24
# %bb.1:                                # %.preheader47.lr.ph
	movq	%rdx, %r12
	movl	%esi, %r10d
	movq	%rdi, %r15
	movl	%ecx, -44(%rbp)                 # 4-byte Spill
	leaq	(,%r14,4), %rdx
	xorl	%r13d, %r13d
	movq	%rbx, %rdi
	xorl	%esi, %esi
	movq	%r8, -64(%rbp)                  # 8-byte Spill
	movl	%r9d, -52(%rbp)                 # 4-byte Spill
	movl	%r10d, -48(%rbp)                # 4-byte Spill
	callq	memset@PLT
	movl	-48(%rbp), %r9d                 # 4-byte Reload
	movl	-52(%rbp), %edi                 # 4-byte Reload
	movq	-64(%rbp), %r8                  # 8-byte Reload
	movl	%r9d, %eax
.LBB13_2:                               # %.preheader47
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB13_4 Depth 2
	testl	%r9d, %r9d
	jle	.LBB13_7
# %bb.3:                                # %.lr.ph53
                                        #   in Loop: Header=BB13_2 Depth=1
	movl	(%r8,%r13,4), %ecx
	xorl	%edx, %edx
.LBB13_4:                               #   Parent Loop BB13_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	cmpl	%ecx, (%r15,%rdx,4)
	jne	.LBB13_6
# %bb.5:                                #   in Loop: Header=BB13_4 Depth=2
	movl	(%rbx,%r13,4), %esi
	cmpl	$1, %esi
	adcl	$0, %esi
	movl	%esi, (%rbx,%r13,4)
.LBB13_6:                               #   in Loop: Header=BB13_4 Depth=2
	incq	%rdx
	cmpq	%rdx, %rax
	jne	.LBB13_4
.LBB13_7:                               # %._crit_edge
                                        #   in Loop: Header=BB13_2 Depth=1
	incq	%r13
	cmpq	%r14, %r13
	jne	.LBB13_2
# %bb.8:                                # %.preheader46
	testl	%edi, %edi
	movb	$1, %r13b
	jle	.LBB13_24
# %bb.9:                                # %.preheader45.lr.ph
	movl	-44(%rbp), %r9d                 # 4-byte Reload
	movl	%r9d, %eax
	xorl	%ecx, %ecx
.LBB13_10:                              # %.preheader45
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB13_12 Depth 2
	testl	%r9d, %r9d
	jle	.LBB13_15
# %bb.11:                               # %.lr.ph56
                                        #   in Loop: Header=BB13_10 Depth=1
	movl	(%r8,%rcx,4), %edx
	xorl	%esi, %esi
.LBB13_12:                              #   Parent Loop BB13_10 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	cmpl	%edx, (%r12,%rsi,4)
	jne	.LBB13_14
# %bb.13:                               #   in Loop: Header=BB13_12 Depth=2
	movl	(%rbx,%rcx,4), %edi
	cmpl	$1, %edi
	adcl	$0, %edi
	movl	%edi, (%rbx,%rcx,4)
.LBB13_14:                              #   in Loop: Header=BB13_12 Depth=2
	incq	%rsi
	cmpq	%rsi, %rax
	jne	.LBB13_12
.LBB13_15:                              # %._crit_edge57
                                        #   in Loop: Header=BB13_10 Depth=1
	incq	%rcx
	cmpq	%r14, %rcx
	jne	.LBB13_10
# %bb.16:                               # %.lr.ph62.preheader
	cmpl	$1, (%rbx)
	jne	.LBB13_17
# %bb.18:                               # %.lr.ph.preheader
	movl	$1, %eax
.LBB13_19:                              # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	cmpq	%rax, %r14
	je	.LBB13_23
# %bb.20:                               # %.lr.ph62
                                        #   in Loop: Header=BB13_19 Depth=1
	leaq	1(%rax), %rcx
	cmpl	$1, (%rbx,%rax,4)
	movq	%rcx, %rax
	je	.LBB13_19
# %bb.21:                               # %.lr.ph62._crit_edge.loopexit
	decq	%rcx
	cmpq	%r14, %rcx
	setae	%r13b
	jmp	.LBB13_22
.LBB13_17:
	xorl	%r13d, %r13d
.LBB13_22:                              # %.lr.ph62._crit_edge
	movl	$.Lstr.1, %edi
	callq	puts@PLT
	jmp	.LBB13_24
.LBB13_23:                              # %.loopexit.loopexit
	cmpq	%r14, %rax
	setae	%r13b
.LBB13_24:                              # %.loopexit
	movzbl	%r13b, %eax
	leaq	-40(%rbp), %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	.cfi_def_cfa %rsp, 8
	retq
.Lfunc_end13:
	.size	_Z27assertMergeAllValuesPresentPiiS_iS_i, .Lfunc_end13-_Z27assertMergeAllValuesPresentPiiS_iS_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z26assertSortAllValuesPresentPiS_i # -- Begin function _Z26assertSortAllValuesPresentPiS_i
	.type	_Z26assertSortAllValuesPresentPiS_i,@function
_Z26assertSortAllValuesPresentPiS_i:    # @_Z26assertSortAllValuesPresentPiS_i
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	pushq	%rax
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	movl	%edx, %r12d
	movq	%rsp, %rbx
	leaq	15(,%r12,4), %rax
	andq	$-16, %rax
	subq	%rax, %rbx
	movq	%rbx, %rsp
	testl	%edx, %edx
	jle	.LBB14_1
# %bb.2:                                # %.preheader30.lr.ph
	movq	%rsi, %r14
	movq	%rdi, %r15
	leaq	(,%r12,4), %rdx
	xorl	%r13d, %r13d
	movq	%rbx, %rdi
	xorl	%esi, %esi
	callq	memset@PLT
.LBB14_3:                               # %.lr.ph37
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB14_4 Depth 2
	movl	(%r15,%r13,4), %eax
	xorl	%ecx, %ecx
.LBB14_4:                               #   Parent Loop BB14_3 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	cmpl	%eax, (%r14,%rcx,4)
	jne	.LBB14_6
# %bb.5:                                #   in Loop: Header=BB14_4 Depth=2
	movl	$1, (%rbx,%r13,4)
.LBB14_6:                               #   in Loop: Header=BB14_4 Depth=2
	incq	%rcx
	cmpq	%rcx, %r12
	jne	.LBB14_4
# %bb.7:                                # %._crit_edge
                                        #   in Loop: Header=BB14_3 Depth=1
	incq	%r13
	cmpq	%r12, %r13
	jne	.LBB14_3
# %bb.8:                                # %.lr.ph42.preheader
	xorl	%esi, %esi
	cmpl	$1, (%rbx)
	movl	$0, %r14d
	jne	.LBB14_13
# %bb.9:                                # %.lr.ph.preheader
	leaq	-1(%r12), %rcx
	xorl	%eax, %eax
.LBB14_10:                              # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	cmpq	%rax, %rcx
	je	.LBB14_14
# %bb.11:                               # %.lr.ph42
                                        #   in Loop: Header=BB14_10 Depth=1
	leaq	1(%rax), %rsi
	cmpl	$1, 4(%rbx,%rax,4)
	movq	%rsi, %rax
	je	.LBB14_10
# %bb.12:                               # %.lr.ph42._crit_edge
	cmpq	%r12, %rsi
	setae	%r14b
.LBB14_13:
	movl	$.L.str.7, %edi
                                        # kill: def $esi killed $esi killed $rsi
	xorl	%eax, %eax
	callq	printf
	movl	$.Lstr.2, %edi
	callq	puts@PLT
	jmp	.LBB14_15
.LBB14_1:
	movb	$1, %r14b
	jmp	.LBB14_15
.LBB14_14:                              # %.loopexit.loopexit
	incq	%rax
	cmpq	%r12, %rax
	setae	%r14b
.LBB14_15:                              # %.loopexit
	movzbl	%r14b, %eax
	leaq	-40(%rbp), %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	.cfi_def_cfa %rsp, 8
	retq
.Lfunc_end14:
	.size	_Z26assertSortAllValuesPresentPiS_i, .Lfunc_end14-_Z26assertSortAllValuesPresentPiS_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z11assertMergePiiS_iS_i        # -- Begin function _Z11assertMergePiiS_iS_i
	.type	_Z11assertMergePiiS_iS_i,@function
_Z11assertMergePiiS_iS_i:               # @_Z11assertMergePiiS_iS_i
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, %ebx
	movq	%r8, %r14
	movl	%ecx, 4(%rsp)                   # 4-byte Spill
	movq	%rdx, %r15
	movl	%esi, %r12d
	movq	%rdi, %r13
	movq	%r8, %rdi
	movl	%r9d, %esi
	callq	_Z11assertOrderPii
	movl	%eax, %ebp
	movq	%r13, %rdi
	movl	%r12d, %esi
	movq	%r15, %rdx
	movl	4(%rsp), %ecx                   # 4-byte Reload
	movq	%r14, %r8
	movl	%ebx, %r9d
	callq	_Z27assertMergeAllValuesPresentPiiS_iS_i
	testl	%ebp, %ebp
	setne	%cl
	testl	%eax, %eax
	setne	%al
	andb	%cl, %al
	movl	$.Lstr.4, %ecx
	movl	$.Lstr.3, %edi
	cmovneq	%rcx, %rdi
	movzbl	%al, %ebx
	callq	puts@PLT
	movl	%ebx, %eax
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end15:
	.size	_Z11assertMergePiiS_iS_i, .Lfunc_end15-_Z11assertMergePiiS_iS_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z12assertSortedPiS_i           # -- Begin function _Z12assertSortedPiS_i
	.type	_Z12assertSortedPiS_i,@function
_Z12assertSortedPiS_i:                  # @_Z12assertSortedPiS_i
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edx, %ebx
	movq	%rsi, %r14
	movq	%rdi, %r15
	movq	%rsi, %rdi
	movl	%edx, %esi
	callq	_Z11assertOrderPii
	movl	%eax, %ebp
	movq	%r15, %rdi
	movq	%r14, %rsi
	movl	%ebx, %edx
	callq	_Z26assertSortAllValuesPresentPiS_i
	testl	%ebp, %ebp
	setne	%cl
	testl	%eax, %eax
	setne	%al
	andb	%cl, %al
	movl	$.Lstr.6, %ecx
	movl	$.Lstr.5, %edi
	cmovneq	%rcx, %rdi
	movzbl	%al, %ebx
	callq	puts@PLT
	movl	%ebx, %eax
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end16:
	.size	_Z12assertSortedPiS_i, .Lfunc_end16-_Z12assertSortedPiS_i
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI17_0:
	.long	0x49742400                      # float 1.0E+6
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$16, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsi, %r14
	movl	%edi, %ebp
	xorl	%edi, %edi
	callq	time
	movl	%eax, %edi
	callq	srand
	movl	$100000, %ebx                   # imm = 0x186A0
	cmpl	$2, %ebp
	jne	.LBB17_2
# %bb.1:
	movq	8(%r14), %rdi
	callq	atoi
	movl	%eax, %ebx
.LBB17_2:
	movl	$.Lstr.7, %edi
	callq	puts@PLT
	movl	$.L.str.14, %edi
	movl	%ebx, %esi
	xorl	%eax, %eax
	callq	printf
	movslq	%ebx, %r12
	leaq	(,%r12,4), %r14
	movq	%r14, %rdi
	callq	malloc
	movq	%rax, %r15
	leal	(%r12,%r12), %eax
	leal	(%rax,%rax,4), %edx
	movq	%r15, %rdi
	movl	%r12d, %esi
	callq	_Z19init_array_no_orderPiii
	movq	%r14, %rdi
	callq	malloc
	movq	%rax, %r14
	testl	%r12d, %r12d
	jle	.LBB17_4
# %bb.3:                                # %.lr.ph.preheader.i
	movl	%ebx, %edx
	shlq	$2, %rdx
	movq	%r14, %rdi
	movq	%r15, %rsi
	callq	memcpy@PLT
.LBB17_4:                               # %_Z10copy_arrayPiS_i.exit36
	callq	clock
	movq	%rax, %r12
	movq	%r15, %rdi
	movl	%ebx, %esi
	callq	_Z10fusionSortPii
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB17_6
# %bb.5:                                # %_Z9gpuAssert10hipError_tPKcib.exit
	callq	clock
	subq	%r12, %rax
	cvtsi2ss	%rax, %xmm0
	divss	.LCPI17_0(%rip), %xmm0
	movss	%xmm0, 8(%rsp)                  # 4-byte Spill
	callq	clock
	movq	%rax, %r15
	movq	%r14, %rdi
	movl	%ebx, %esi
	callq	_Z13fusionSortSeqPii
	callq	clock
	subq	%r15, %rax
	xorps	%xmm0, %xmm0
	cvtsi2ss	%rax, %xmm0
	divss	.LCPI17_0(%rip), %xmm0
	movss	%xmm0, 4(%rsp)                  # 4-byte Spill
	movl	$.Lstr.8, %edi
	callq	puts@PLT
	xorps	%xmm0, %xmm0
	cvtss2sd	8(%rsp), %xmm0                  # 4-byte Folded Reload
	movl	$.L.str.16, %edi
	movb	$1, %al
	callq	printf
	movss	4(%rsp), %xmm0                  # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	divss	8(%rsp), %xmm0                  # 4-byte Folded Reload
	cvtss2sd	%xmm0, %xmm0
	movsd	%xmm0, 8(%rsp)                  # 8-byte Spill
	movl	$.L.str.17, %edi
	movb	$1, %al
	callq	printf
	movl	$.L.str.18, %edi
	movsd	8(%rsp), %xmm0                  # 8-byte Reload
                                        # xmm0 = mem[0],zero
	movb	$1, %al
	callq	printf
	movl	$.Lstr.9, %edi
	callq	puts@PLT
	xorps	%xmm0, %xmm0
	cvtss2sd	4(%rsp), %xmm0                  # 4-byte Folded Reload
	movl	$.L.str.16, %edi
	movb	$1, %al
	callq	printf
	xorl	%eax, %eax
	addq	$16, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB17_6:
	.cfi_def_cfa_offset 64
	movl	%eax, %ebp
	movq	stderr(%rip), %rbx
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str.20, %esi
	movl	$.L.str.3, %ecx
	movq	%rbx, %rdi
	movq	%rax, %rdx
	movl	$609, %r8d                      # imm = 0x261
	xorl	%eax, %eax
	callq	fprintf
	movl	%ebp, %edi
	callq	exit
.Lfunc_end17:
	.size	main, .Lfunc_end17-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB18_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB18_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12mergeSmall_kPiS_S_iii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z23pretraitementFusionSortPiS_i, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end18:
	.size	__hip_module_ctor, .Lfunc_end18-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB19_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB19_2:
	retq
.Lfunc_end19:
	.size	__hip_module_dtor, .Lfunc_end19-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"%d "
	.size	.L.str.1, 4

	.type	_Z12mergeSmall_kPiS_S_iii,@object # @_Z12mergeSmall_kPiS_S_iii
	.section	.rodata,"a",@progbits
	.globl	_Z12mergeSmall_kPiS_S_iii
	.p2align	3, 0x0
_Z12mergeSmall_kPiS_S_iii:
	.quad	_Z27__device_stub__mergeSmall_kPiS_S_iii
	.size	_Z12mergeSmall_kPiS_S_iii, 8

	.type	_Z10mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii,@object # @_Z10mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii
	.globl	_Z10mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii
	.p2align	3, 0x0
_Z10mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii:
	.quad	_Z25__device_stub__mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii
	.size	_Z10mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii, 8

	.type	_Z9pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i,@object # @_Z9pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i
	.globl	_Z9pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i
	.p2align	3, 0x0
_Z9pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i:
	.quad	_Z24__device_stub__pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i
	.size	_Z9pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i, 8

	.type	.L.str.3,@object                # @.str.3
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.3:
	.asciz	"/home/ubuntu/Datasets/stackv2/train-structured-repos-hip-sm89/homerdurand/HPCA/main/pathSortFinal.hip"
	.size	.L.str.3, 102

	.type	_Z23pretraitementFusionSortPiS_i,@object # @_Z23pretraitementFusionSortPiS_i
	.section	.rodata,"a",@progbits
	.globl	_Z23pretraitementFusionSortPiS_i
	.p2align	3, 0x0
_Z23pretraitementFusionSortPiS_i:
	.quad	_Z38__device_stub__pretraitementFusionSortPiS_i
	.size	_Z23pretraitementFusionSortPiS_i, 8

	.type	.L.str.4,@object                # @.str.4
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.4:
	.asciz	"WARNING : Unsuccessful merge or sort ... : unordered array on indice %d ...\n"
	.size	.L.str.4, 77

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"tab[i]= %d > tab[i+1] = %d\n"
	.size	.L.str.5, 28

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"i : %d\n"
	.size	.L.str.7, 8

	.type	.L.str.14,@object               # @.str.14
.L.str.14:
	.asciz	"* Size of array : %d\n\n"
	.size	.L.str.14, 23

	.type	.L.str.16,@object               # @.str.16
.L.str.16:
	.asciz	"Total time elapsed : %f s\n"
	.size	.L.str.16, 27

	.type	.L.str.17,@object               # @.str.17
.L.str.17:
	.asciz	"Parrallel algorithm is %f times faster than sequential merge !\n"
	.size	.L.str.17, 64

	.type	.L.str.18,@object               # @.str.18
.L.str.18:
	.asciz	"Parrallel merge is %f times faster than sequential merge !\n"
	.size	.L.str.18, 60

	.type	.L.str.20,@object               # @.str.20
.L.str.20:
	.asciz	"GPUassert: %s %s %d\n"
	.size	.L.str.20, 21

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z12mergeSmall_kPiS_S_iii"
	.size	.L__unnamed_1, 26

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z10mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii"
	.size	.L__unnamed_2, 51

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z9pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i"
	.size	.L__unnamed_3, 47

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z23pretraitementFusionSortPiS_i"
	.size	.L__unnamed_4, 33

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"]"
	.size	.Lstr, 2

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"\nWARNING : Unsuccessful merge : incorrect elements..."
	.size	.Lstr.1, 54

	.type	.Lstr.2,@object                 # @str.2
.Lstr.2:
	.asciz	"\nWARNING : Unsuccessful sort : incorrect elements..."
	.size	.Lstr.2, 53

	.type	.Lstr.3,@object                 # @str.3
.Lstr.3:
	.asciz	"\nUnsuccessful merge !"
	.size	.Lstr.3, 22

	.type	.Lstr.4,@object                 # @str.4
.Lstr.4:
	.asciz	"\nSuccessful merge !"
	.size	.Lstr.4, 20

	.type	.Lstr.5,@object                 # @str.5
.Lstr.5:
	.asciz	"\nUnsuccessful sort !"
	.size	.Lstr.5, 21

	.type	.Lstr.6,@object                 # @str.6
.Lstr.6:
	.asciz	"\nSuccessful sort !"
	.size	.Lstr.6, 19

	.type	.Lstr.7,@object                 # @str.7
.Lstr.7:
	.asciz	"========== Path Sort : ========="
	.size	.Lstr.7, 33

	.type	.Lstr.8,@object                 # @str.8
.Lstr.8:
	.asciz	"========= Parallel sort : ============="
	.size	.Lstr.8, 40

	.type	.Lstr.9,@object                 # @str.9
.Lstr.9:
	.asciz	"========= Sequential sort : ============="
	.size	.Lstr.9, 42

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z27__device_stub__mergeSmall_kPiS_S_iii
	.addrsig_sym _Z25__device_stub__mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii
	.addrsig_sym _Z24__device_stub__pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i
	.addrsig_sym _Z38__device_stub__pretraitementFusionSortPiS_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z12mergeSmall_kPiS_S_iii
	.addrsig_sym _Z10mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii
	.addrsig_sym _Z9pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i
	.addrsig_sym _Z23pretraitementFusionSortPiS_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z12mergeSmall_kPiS_S_iii ; -- Begin function _Z12mergeSmall_kPiS_S_iii
	.globl	_Z12mergeSmall_kPiS_S_iii
	.p2align	8
	.type	_Z12mergeSmall_kPiS_S_iii,@function
_Z12mergeSmall_kPiS_S_iii:              ; @_Z12mergeSmall_kPiS_S_iii
; %bb.0:
	s_load_b128 s[8:11], s[0:1], 0x18
	s_mov_b32 s2, exec_lo
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 s10, v0
	s_cbranch_execz .LBB0_24
; %bb.1:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	v_subrev_nc_u32_e32 v1, s8, v0
	v_cmp_lt_i32_e32 vcc_lo, s8, v0
	v_min_i32_e32 v4, s8, v0
	s_mov_b32 s11, 0
	v_mov_b32_e32 v2, 0
                                        ; implicit-def: $sgpr10
	v_cndmask_b32_e32 v7, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v8, v7
	s_waitcnt lgkmcnt(0)
	s_add_u32 s12, s6, -4
	s_addc_u32 s13, s7, -1
.LBB0_2:                                ; %.outer
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_3 Depth 2
	v_mov_b32_e32 v9, v4
	s_mov_b32 s14, 0
                                        ; implicit-def: $sgpr19
                                        ; implicit-def: $sgpr17
                                        ; implicit-def: $sgpr15
                                        ; implicit-def: $sgpr18
                                        ; implicit-def: $sgpr16
.LBB0_3:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v1, v9, v7
	s_or_b32 s16, s16, exec_lo
	s_and_not1_b32 s18, s18, exec_lo
	s_or_b32 s15, s15, exec_lo
	v_sub_nc_u32_e32 v3, 0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v1, v1, v3
	v_lshrrev_b32_e32 v1, 1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v5, v9, v1
	v_add_nc_u32_e32 v3, v1, v8
	v_cmp_lt_i32_e32 vcc_lo, -1, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_i32_e64 s0, s9, v3
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s20, s0
	s_cbranch_execz .LBB0_13
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=2
	v_cmp_eq_u32_e32 vcc_lo, s8, v5
	v_cmp_eq_u32_e64 s0, 0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, vcc_lo, s0
	s_xor_b32 s21, s0, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s21
	s_cbranch_execz .LBB0_6
; %bb.5:                                ;   in Loop: Header=BB0_3 Depth=2
	v_mov_b32_e32 v6, v2
	v_ashrrev_i32_e32 v4, 31, v3
	s_and_not1_b32 s0, s0, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[10:11], 2, v[5:6]
	v_lshlrev_b64 v[12:13], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v10, vcc_lo, s4, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s5, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v12, vcc_lo, s12, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s13, v13, vcc_lo
	global_load_b32 v4, v[10:11], off
	global_load_b32 v6, v[12:13], off
	s_waitcnt vmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, v4, v6
	s_and_b32 s21, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s0, s0, s21
.LBB0_6:                                ; %Flow117
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_mov_b32 s1, -1
	s_mov_b32 s23, -1
                                        ; implicit-def: $sgpr22
	s_and_saveexec_b32 s21, s0
	s_cbranch_execz .LBB0_12
; %bb.7:                                ;   in Loop: Header=BB0_3 Depth=2
	v_cmp_ne_u32_e64 s0, s9, v3
	v_cmp_ne_u32_e64 s1, v9, v1
	v_cmp_eq_u32_e32 vcc_lo, s9, v3
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s22, s1, s0
	s_mov_b32 s0, -1
	s_and_saveexec_b32 s1, s22
	s_cbranch_execz .LBB0_11
; %bb.8:                                ;   in Loop: Header=BB0_3 Depth=2
	v_add_nc_u32_e32 v1, -1, v5
	v_ashrrev_i32_e32 v4, 31, v3
	s_mov_b32 s22, -1
	s_mov_b32 s23, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[10:11], 2, v[1:2]
	v_lshlrev_b64 v[12:13], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v10, s0, s4, v10
	v_add_co_ci_u32_e64 v11, s0, s5, v11, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v12, s0, s6, v12
	v_add_co_ci_u32_e64 v13, s0, s7, v13, s0
	global_load_b32 v4, v[10:11], off
	global_load_b32 v6, v[12:13], off
	s_waitcnt vmcnt(0)
	v_cmpx_gt_i32_e64 v4, v6
; %bb.9:                                ;   in Loop: Header=BB0_3 Depth=2
	v_add_nc_u32_e32 v8, 1, v3
	s_xor_b32 s22, exec_lo, -1
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $vgpr3
                                        ; implicit-def: $vgpr5
; %bb.10:                               ; %Flow120
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s23
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, vcc_lo, exec_lo
	s_or_not1_b32 s0, s22, exec_lo
.LBB0_11:                               ; %Flow119
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s23, exec_lo, -1
	s_and_b32 s22, vcc_lo, exec_lo
	s_or_not1_b32 s1, s0, exec_lo
.LBB0_12:                               ; %Flow118
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s21
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s0, s16, exec_lo
	s_and_b32 s16, s23, exec_lo
	s_and_not1_b32 s15, s15, exec_lo
	s_or_b32 s16, s0, s16
	s_and_not1_b32 s0, s18, exec_lo
	s_and_b32 s18, s22, exec_lo
	s_and_b32 s1, s1, exec_lo
	s_or_b32 s18, s0, s18
	s_or_b32 s15, s15, s1
.LBB0_13:                               ; %Flow116
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s20
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s0, exec_lo, s15
	v_mov_b32_e32 v4, v9
	s_or_b32 s14, s0, s14
	v_mov_b32_e32 v9, v1
	s_and_not1_b32 s0, s17, exec_lo
	s_and_b32 s1, s16, exec_lo
	s_and_not1_b32 s19, s19, exec_lo
	s_and_b32 s20, s18, exec_lo
	s_or_b32 s17, s0, s1
	s_or_b32 s19, s19, s20
	s_and_not1_b32 exec_lo, exec_lo, s14
	s_cbranch_execnz .LBB0_3
; %bb.14:                               ; %loop.exit.guard
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	s_mov_b32 s1, -1
	s_xor_b32 s0, s19, -1
                                        ; implicit-def: $vgpr7
	s_and_saveexec_b32 s14, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s14, exec_lo, s14
; %bb.15:                               ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v7, 1, v5
	s_xor_b32 s1, exec_lo, -1
; %bb.16:                               ; %Flow121
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, exec_lo, s1
	s_or_b32 s11, s1, s11
	s_and_not1_b32 s1, s10, exec_lo
	s_and_b32 s0, s0, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s10, s1, s0
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_2
; %bb.17:
	s_or_b32 exec_lo, exec_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
                                        ; implicit-def: $vgpr1
	v_cmpx_le_i32_e64 s8, v5
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB0_19
; %bb.18:                               ; %._crit_edge
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[3:4]
	v_add_co_u32 v1, vcc_lo, s6, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v2, vcc_lo
	global_load_b32 v1, v[1:2], off
.LBB0_19:                               ; %Flow115
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB0_23
; %bb.20:
	v_mov_b32_e32 v6, 0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[5:6]
	v_add_co_u32 v1, vcc_lo, s4, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
	global_load_b32 v1, v[1:2], off
	s_and_saveexec_b32 s1, s10
	s_cbranch_execz .LBB0_22
; %bb.21:
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[3:4]
	v_add_co_u32 v2, vcc_lo, s6, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_waitcnt vmcnt(0)
	v_min_i32_e32 v1, v1, v2
.LBB0_22:                               ; %Flow
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_23:                               ; %.sink.split
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s0
	v_lshlrev_b32_e32 v0, 2, v0
	s_waitcnt vmcnt(0)
	global_store_b32 v0, v1, s[2:3]
.LBB0_24:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12mergeSmall_kPiS_S_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 36
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z12mergeSmall_kPiS_S_iii, .Lfunc_end0-_Z12mergeSmall_kPiS_S_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 912
; NumSgprs: 26
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z10mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii ; -- Begin function _Z10mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii
	.globl	_Z10mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii
	.p2align	8
	.type	_Z10mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii,@function
_Z10mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii: ; @_Z10mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii
; %bb.0:
	s_load_b32 s2, s[0:1], 0x3c
	s_waitcnt lgkmcnt(0)
	s_cmp_gt_i32 s15, s2
	s_cbranch_scc1 .LBB1_34
; %bb.1:
	s_load_b64 s[2:3], s[0:1], 0x30
	s_mov_b32 s8, s15
	s_ashr_i32 s9, s15, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[4:5], s[8:9], 3
	s_load_b32 s9, s[0:1], 0x4c
	s_waitcnt lgkmcnt(0)
	s_add_u32 s2, s2, s4
	s_addc_u32 s3, s3, s5
	s_load_b128 s[4:7], s[2:3], 0x0
	s_mov_b32 s3, exec_lo
                                        ; implicit-def: $sgpr2
	s_waitcnt lgkmcnt(0)
	s_sub_i32 s6, s6, s4
	s_sub_i32 s7, s7, s5
	v_cmpx_le_i32_e64 s6, v0
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB1_5
; %bb.2:
	s_add_i32 s2, s7, s6
	s_mov_b32 s10, exec_lo
	v_cmpx_gt_i32_e64 s2, v0
	s_cbranch_execz .LBB1_4
; %bb.3:
	v_add_nc_u32_e32 v1, s5, v0
	s_load_b64 s[12:13], s[0:1], 0x20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_subrev_nc_u32_e32 v1, s6, v1
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v1, vcc_lo, s12, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, s13, v2, vcc_lo
	global_load_b32 v1, v[1:2], off
	v_subrev_nc_u32_e32 v2, s6, v0
	v_lshlrev_b32_e32 v2, 2, v2
	s_waitcnt vmcnt(0)
	ds_store_b32 v2, v1 offset:4096
.LBB1_4:                                ; %Flow82
	s_or_b32 exec_lo, exec_lo, s10
.LBB1_5:                                ; %Flow83
	s_or_saveexec_b32 s3, s3
	v_dual_mov_b32 v2, s2 :: v_dual_lshlrev_b32 v1, 2, v0
	s_xor_b32 exec_lo, exec_lo, s3
	s_cbranch_execz .LBB1_7
; %bb.6:
	s_load_b64 s[10:11], s[0:1], 0x10
	v_add_nc_u32_e32 v2, s4, v0
	s_add_i32 s2, s7, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s10, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
	global_load_b32 v3, v[2:3], off
	v_mov_b32_e32 v2, s2
	s_waitcnt vmcnt(0)
	ds_store_b32 v1, v3
.LBB1_7:
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	v_cmp_ge_i32_e32 vcc_lo, v0, v2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
                                        ; implicit-def: $vgpr2
	s_and_saveexec_b32 s2, vcc_lo
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB1_9
; %bb.8:                                ; %._Z13mergeParallelPiS_S_iii.exit_crit_edge
	ds_load_b32 v2, v1 offset:8192
                                        ; implicit-def: $vgpr1
.LBB1_9:                                ; %Flow80
	s_and_not1_saveexec_b32 s4, s2
	s_cbranch_execz .LBB1_33
; %bb.10:
	s_waitcnt lgkmcnt(0)
	v_subrev_nc_u32_e32 v2, s6, v0
	v_cmp_lt_i32_e32 vcc_lo, s6, v0
	v_min_i32_e32 v8, s6, v0
	s_mov_b32 s10, 0
                                        ; implicit-def: $sgpr5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, 0, v2, vcc_lo
	v_mov_b32_e32 v2, v3
.LBB1_11:                               ; %.outer
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_12 Depth 2
	s_delay_alu instid0(VALU_DEP_3)
	v_mov_b32_e32 v6, v8
	s_mov_b32 s11, 0
                                        ; implicit-def: $sgpr16
                                        ; implicit-def: $sgpr14
                                        ; implicit-def: $sgpr12
                                        ; implicit-def: $sgpr15
                                        ; implicit-def: $sgpr13
.LBB1_12:                               ;   Parent Loop BB1_11 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, v6, v3
	s_or_b32 s13, s13, exec_lo
	s_and_not1_b32 s15, s15, exec_lo
	s_or_b32 s12, s12, exec_lo
                                        ; implicit-def: $vgpr7
	v_sub_nc_u32_e32 v5, 0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v4, v4, v5
	v_lshrrev_b32_e32 v8, 1, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v5, v6, v8
	v_add_nc_u32_e32 v4, v8, v2
	v_cmp_lt_i32_e32 vcc_lo, -1, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_i32_e64 s2, s7, v4
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s17, s2
	s_cbranch_execz .LBB1_22
; %bb.13:                               ;   in Loop: Header=BB1_12 Depth=2
	v_cmp_eq_u32_e32 vcc_lo, s6, v5
	v_cmp_eq_u32_e64 s2, 0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s3, vcc_lo, s2
	s_xor_b32 s18, s3, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s18
	s_cbranch_execz .LBB1_15
; %bb.14:                               ;   in Loop: Header=BB1_12 Depth=2
	v_lshlrev_b32_e32 v7, 2, v5
	v_lshlrev_b32_e32 v9, 2, v4
	s_and_not1_b32 s3, s3, exec_lo
	ds_load_b32 v7, v7
	ds_load_b32 v9, v9 offset:4092
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, v7, v9
	s_and_b32 s18, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s3, s3, s18
.LBB1_15:                               ; %Flow75
                                        ;   in Loop: Header=BB1_12 Depth=2
	s_or_b32 exec_lo, exec_lo, s2
	s_mov_b32 s2, -1
	s_mov_b32 s20, -1
                                        ; implicit-def: $sgpr19
                                        ; implicit-def: $vgpr7
	s_and_saveexec_b32 s18, s3
	s_cbranch_execz .LBB1_21
; %bb.16:                               ;   in Loop: Header=BB1_12 Depth=2
	v_cmp_ne_u32_e64 s2, s7, v4
	v_cmp_ne_u32_e64 s3, v6, v8
	v_cmp_eq_u32_e32 vcc_lo, s7, v4
                                        ; implicit-def: $vgpr7
	s_delay_alu instid0(VALU_DEP_2)
	s_and_b32 s19, s3, s2
	s_mov_b32 s2, -1
	s_and_saveexec_b32 s3, s19
	s_cbranch_execz .LBB1_20
; %bb.17:                               ;   in Loop: Header=BB1_12 Depth=2
	v_add_nc_u32_e32 v7, -1, v5
	v_lshlrev_b32_e32 v9, 2, v4
	s_mov_b32 s19, -1
	s_mov_b32 s20, exec_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_lshlrev_b32_e32 v8, 2, v7
	ds_load_b32 v8, v8
	ds_load_b32 v9, v9 offset:4096
	s_waitcnt lgkmcnt(0)
	v_cmpx_gt_i32_e64 v8, v9
; %bb.18:                               ;   in Loop: Header=BB1_12 Depth=2
	v_add_nc_u32_e32 v2, 1, v4
	s_xor_b32 s19, exec_lo, -1
                                        ; implicit-def: $vgpr6
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr5
; %bb.19:                               ; %Flow78
                                        ;   in Loop: Header=BB1_12 Depth=2
	s_or_b32 exec_lo, exec_lo, s20
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, vcc_lo, exec_lo
	s_or_not1_b32 s2, s19, exec_lo
.LBB1_20:                               ; %Flow77
                                        ;   in Loop: Header=BB1_12 Depth=2
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s20, exec_lo, -1
	s_and_b32 s19, vcc_lo, exec_lo
	s_or_not1_b32 s2, s2, exec_lo
.LBB1_21:                               ; %Flow76
                                        ;   in Loop: Header=BB1_12 Depth=2
	s_or_b32 exec_lo, exec_lo, s18
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s3, s13, exec_lo
	s_and_b32 s13, s20, exec_lo
	s_and_not1_b32 s12, s12, exec_lo
	s_or_b32 s13, s3, s13
	s_and_not1_b32 s3, s15, exec_lo
	s_and_b32 s15, s19, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_or_b32 s15, s3, s15
	s_or_b32 s12, s12, s2
.LBB1_22:                               ; %Flow74
                                        ;   in Loop: Header=BB1_12 Depth=2
	s_or_b32 exec_lo, exec_lo, s17
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s2, exec_lo, s12
	v_mov_b32_e32 v8, v6
	s_or_b32 s11, s2, s11
	v_mov_b32_e32 v6, v7
	s_and_not1_b32 s2, s14, exec_lo
	s_and_b32 s3, s13, exec_lo
	s_and_not1_b32 s16, s16, exec_lo
	s_and_b32 s17, s15, exec_lo
	s_or_b32 s14, s2, s3
	s_or_b32 s16, s16, s17
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB1_12
; %bb.23:                               ; %loop.exit.guard
                                        ;   in Loop: Header=BB1_11 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	s_mov_b32 s3, -1
	s_xor_b32 s2, s16, -1
                                        ; implicit-def: $vgpr3
	s_and_saveexec_b32 s11, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s11, exec_lo, s11
; %bb.24:                               ;   in Loop: Header=BB1_11 Depth=1
	v_add_nc_u32_e32 v3, 1, v5
	s_xor_b32 s3, exec_lo, -1
; %bb.25:                               ; %Flow79
                                        ;   in Loop: Header=BB1_11 Depth=1
	s_or_b32 exec_lo, exec_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, exec_lo, s3
	s_or_b32 s10, s3, s10
	s_and_not1_b32 s3, s5, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s5, s3, s2
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB1_11
; %bb.26:
	s_or_b32 exec_lo, exec_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
                                        ; implicit-def: $vgpr2
	v_cmpx_le_i32_e64 s6, v5
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB1_28
; %bb.27:                               ; %._crit_edge.i
	v_lshlrev_b32_e32 v2, 2, v4
	ds_load_b32 v2, v2 offset:4096
.LBB1_28:                               ; %Flow73
	s_and_not1_saveexec_b32 s2, s2
	s_cbranch_execz .LBB1_32
; %bb.29:
	s_waitcnt lgkmcnt(0)
	v_lshlrev_b32_e32 v2, 2, v5
	ds_load_b32 v2, v2
	s_and_saveexec_b32 s3, s5
	s_cbranch_execz .LBB1_31
; %bb.30:
	v_lshlrev_b32_e32 v3, 2, v4
	ds_load_b32 v3, v3 offset:4096
	s_waitcnt lgkmcnt(0)
	v_min_i32_e32 v2, v2, v3
.LBB1_31:                               ; %Flow
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_32:                               ; %.sink.split.i
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt lgkmcnt(0)
	ds_store_b32 v1, v2 offset:8192
.LBB1_33:                               ; %Flow81
	s_or_b32 exec_lo, exec_lo, s4
	s_and_b32 s2, 0xffff, s9
	s_load_b64 s[0:1], s[0:1], 0x0
	v_mad_u64_u32 v[3:4], null, s8, s2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[0:1], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB1_34:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii
		.amdhsa_group_segment_fixed_size 12288
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 21
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z10mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii, .Lfunc_end1-_Z10mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1100
; NumSgprs: 23
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 12288 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 23
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z9pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i ; -- Begin function _Z9pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i
	.globl	_Z9pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i
	.p2align	8
	.type	_Z9pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i,@function
_Z9pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i: ; @_Z9pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i
; %bb.0:
	s_clause 0x4
	s_load_b32 s11, s[0:1], 0x0
	s_load_b64 s[4:5], s[0:1], 0x8
	s_load_b32 s10, s[0:1], 0x20
	s_load_b32 s3, s[0:1], 0x30
	s_load_b32 s2, s[0:1], 0x44
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s6, s11, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s7, s11, s6
	s_add_i32 s12, s3, s10
	s_xor_b32 s7, s7, s6
	s_ashr_i32 s13, s12, 31
	v_cvt_f32_u32_e32 v1, s7
	s_sub_i32 s9, 0, s7
	s_add_i32 s14, s12, s13
	s_and_b32 s2, s2, 0xffff
	s_xor_b32 s14, s14, s13
	v_rcp_iflag_f32_e32 v1, v1
	s_xor_b32 s6, s13, s6
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v1, v1
	v_readfirstlane_b32 s8, v1
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s15, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s9, s9, s8
	s_mul_hi_u32 s9, s8, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s8, s8, s9
	s_mul_hi_u32 s8, s14, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_mul_i32 s9, s8, s7
	s_add_i32 s13, s8, 1
	s_sub_i32 s9, s14, s9
	s_sub_i32 s14, s9, s7
	s_cmp_ge_u32 s9, s7
	s_cselect_b32 s2, s13, s8
	s_cselect_b32 s8, s14, s9
	s_add_i32 s9, s2, 1
	s_cmp_ge_u32 s8, s7
	s_mov_b32 s14, exec_lo
	s_cselect_b32 s2, s9, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s2, s2, s6
	s_sub_i32 s13, s2, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	v_cmpx_ge_i32_e64 s13, v1
	s_cbranch_execz .LBB2_18
; %bb.1:
	s_clause 0x1
	s_load_b64 s[6:7], s[0:1], 0x28
	s_load_b64 s[8:9], s[0:1], 0x18
	v_mul_lo_u32 v2, v1, s11
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_subrev_nc_u32_e32 v0, s10, v2
	v_cmp_lt_i32_e32 vcc_lo, s10, v2
	v_min_i32_e32 v5, s10, v2
	v_cndmask_b32_e32 v0, 0, v0, vcc_lo
	s_waitcnt lgkmcnt(0)
	s_add_u32 s16, s6, -4
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v8, v0
	s_addc_u32 s17, s7, -1
.LBB2_2:                                ; %.outer
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_3 Depth 2
	v_mov_b32_e32 v9, v5
	s_mov_b32 s18, 0
                                        ; implicit-def: $sgpr19
                                        ; implicit-def: $sgpr20
                                        ; implicit-def: $sgpr21
.LBB2_3:                                ;   Parent Loop BB2_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v2, v9, v0
	s_or_b32 s21, s21, exec_lo
	s_or_b32 s20, s20, exec_lo
	v_sub_nc_u32_e32 v4, 0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v2, v2, v4
	v_lshrrev_b32_e32 v2, 1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v6, v9, v2
	v_add_nc_u32_e32 v4, v2, v8
	v_cmp_lt_i32_e32 vcc_lo, -1, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_i32_e64 s2, s3, v4
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s22, s2
	s_cbranch_execz .LBB2_13
; %bb.4:                                ;   in Loop: Header=BB2_3 Depth=2
	v_cmp_eq_u32_e32 vcc_lo, s10, v6
	v_cmp_eq_u32_e64 s2, 0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, vcc_lo, s2
	s_xor_b32 s24, s2, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s23, s24
	s_cbranch_execz .LBB2_6
; %bb.5:                                ;   in Loop: Header=BB2_3 Depth=2
	v_mov_b32_e32 v7, v3
	v_ashrrev_i32_e32 v5, 31, v4
	s_and_not1_b32 s2, s2, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[10:11], 2, v[6:7]
	v_lshlrev_b64 v[12:13], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v10, vcc_lo, s8, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s9, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v12, vcc_lo, s16, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s17, v13, vcc_lo
	global_load_b32 v5, v[10:11], off
	global_load_b32 v7, v[12:13], off
	s_waitcnt vmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, v5, v7
	s_and_b32 s24, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s2, s2, s24
.LBB2_6:                                ; %Flow108
                                        ;   in Loop: Header=BB2_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s23
	s_mov_b32 s24, -1
	s_mov_b32 s25, -1
	s_and_saveexec_b32 s23, s2
	s_cbranch_execz .LBB2_12
; %bb.7:                                ;   in Loop: Header=BB2_3 Depth=2
	v_cmp_ne_u32_e32 vcc_lo, s3, v4
	v_cmp_ne_u32_e64 s2, v9, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s25, s2, vcc_lo
	s_and_saveexec_b32 s2, s25
	s_cbranch_execz .LBB2_11
; %bb.8:                                ;   in Loop: Header=BB2_3 Depth=2
	v_add_nc_u32_e32 v2, -1, v6
	v_ashrrev_i32_e32 v5, 31, v4
	s_mov_b32 s25, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[10:11], 2, v[2:3]
	v_lshlrev_b64 v[12:13], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v10, vcc_lo, s8, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s9, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v12, vcc_lo, s6, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s7, v13, vcc_lo
	global_load_b32 v5, v[10:11], off
	global_load_b32 v7, v[12:13], off
	s_waitcnt vmcnt(0)
	v_cmpx_gt_i32_e64 v5, v7
; %bb.9:                                ;   in Loop: Header=BB2_3 Depth=2
	v_add_nc_u32_e32 v8, 1, v4
	s_xor_b32 s24, exec_lo, -1
                                        ; implicit-def: $vgpr9
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr6
; %bb.10:                               ; %Flow111
                                        ;   in Loop: Header=BB2_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s25
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_not1_b32 s24, s24, exec_lo
.LBB2_11:                               ; %Flow110
                                        ;   in Loop: Header=BB2_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s25, exec_lo, -1
	s_or_not1_b32 s24, s24, exec_lo
.LBB2_12:                               ; %Flow109
                                        ;   in Loop: Header=BB2_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s23
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 s2, s21, exec_lo
	s_and_b32 s21, s25, exec_lo
	s_and_not1_b32 s20, s20, exec_lo
	s_and_b32 s23, s24, exec_lo
	s_or_b32 s21, s2, s21
	s_or_b32 s20, s20, s23
.LBB2_13:                               ; %Flow107
                                        ;   in Loop: Header=BB2_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s22
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s2, exec_lo, s20
	v_mov_b32_e32 v5, v9
	s_or_b32 s18, s2, s18
	v_mov_b32_e32 v9, v2
	s_and_not1_b32 s2, s19, exec_lo
	s_and_b32 s19, s21, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s19, s2, s19
	s_and_not1_b32 exec_lo, exec_lo, s18
	s_cbranch_execnz .LBB2_3
; %bb.14:                               ; %loop.exit.guard
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s18
	s_mov_b32 s2, -1
                                        ; implicit-def: $vgpr0
	s_and_saveexec_b32 s18, s19
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s18, exec_lo, s18
; %bb.15:                               ;   in Loop: Header=BB2_2 Depth=1
	v_add_nc_u32_e32 v0, 1, v6
	s_xor_b32 s2, exec_lo, -1
; %bb.16:                               ; %Flow112
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s18
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, exec_lo, s2
	s_or_b32 s15, s2, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s15
	s_cbranch_execnz .LBB2_2
; %bb.17:
	s_or_b32 exec_lo, exec_lo, s15
	v_ashrrev_i32_e32 v2, 31, v1
	v_mov_b32_e32 v7, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 3, v[1:2]
	v_add_co_u32 v2, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	global_store_b64 v[2:3], v[6:7], off
.LBB2_18:                               ; %Flow113
	s_or_b32 exec_lo, exec_lo, s14
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB2_21
; %bb.19:
	s_mul_i32 s13, s13, s11
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_sub_i32 s2, s12, s13
	s_cmp_eq_u32 s2, 0
	s_cbranch_scc1 .LBB2_21
; %bb.20:
	s_load_b32 s0, s[0:1], 0x10
	v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s3
	v_mov_b32_e32 v0, s10
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s1, s0, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[0:1], 3
	s_add_u32 s0, s4, s0
	s_addc_u32 s1, s5, s1
	global_store_b64 v2, v[0:1], s[0:1] offset:-8
.LBB2_21:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 26
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z9pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i, .Lfunc_end2-_Z9pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 996
; NumSgprs: 28
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 28
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z23pretraitementFusionSortPiS_i ; -- Begin function _Z23pretraitementFusionSortPiS_i
	.globl	_Z23pretraitementFusionSortPiS_i
	.p2align	8
	.type	_Z23pretraitementFusionSortPiS_i,@function
_Z23pretraitementFusionSortPiS_i:       ; @_Z23pretraitementFusionSortPiS_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b32 s3, s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_lshr_b32 s2, s3, 31
	s_add_i32 s3, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_ashr_i32 s2, s3, 1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s2, v1
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB3_3
; %bb.1:
	s_load_b64 s[0:1], s[0:1], 0x8
	v_lshlrev_b32_e32 v0, 1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_load_b64 v[2:3], v[0:1], off
	s_waitcnt vmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, v2, v3
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB3_3
; %bb.2:
	v_mov_b32_e32 v4, v2
	global_store_b64 v[0:1], v[3:4], off
.LBB3_3:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z23pretraitementFusionSortPiS_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z23pretraitementFusionSortPiS_i, .Lfunc_end3-_Z23pretraitementFusionSortPiS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 172
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 36
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12mergeSmall_kPiS_S_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         _Z12mergeSmall_kPiS_S_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     14
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         60
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         68
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         76
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         78
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         80
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         82
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         84
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         86
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         128
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 12288
    .kernarg_segment_align: 8
    .kernarg_segment_size: 320
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii
    .private_segment_fixed_size: 0
    .sgpr_count:     23
    .sgpr_spill_count: 0
    .symbol:         _Z10mergeBig_kPiiS_iS_iP15HIP_vector_typeIiLj2EEii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i
    .private_segment_fixed_size: 0
    .sgpr_count:     28
    .sgpr_spill_count: 0
    .symbol:         _Z9pathBig_kiP15HIP_vector_typeIiLj2EEiPiiS2_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     14
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z23pretraitementFusionSortPiS_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z23pretraitementFusionSortPiS_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     5
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
