
#include <stdio.h>
#include <time.h>
#include <stdlib.h>
#include <stdint.h>

#include <cuda_runtime.h>
#include <cuda_runtime_api.h>
#include <curand_kernel.h>
#include <device_functions.h>
__constant__ uint32_t expo_d[4] = { 1, 256, 65536, 16777216 };

__device__ __host__ inline uint32_t f_CUDA(uint32_t B, uint32_t C, uint32_t D, int t)
{
    if (t < 20)
    {
        return ((B & C) ^ (~B & D));
    }
    if ((t > 19)& (t < 40))
    {
        return (B ^ C ^ D);
    }
    if ((t > 39)& (t < 60))
    {
        return ((B & C) ^ (B & D) ^ (C & D));
    }
    if (t > 59)
    {
        return (B ^ C ^ D);
    }
    return B;
}

__device__ __host__ inline uint32_t Rol_CUDA(uint32_t x, int y)
{
    if (y % 32 == 0) { return x; }
    else { return ((x << y) ^ (x >> -y)); }
}

//SHA1-Function
__device__ __host__ void SHA1(unsigned char* s, int slen, uint32_t *h0, uint32_t* h1, uint32_t* h2, uint32_t* h3, uint32_t* h4)
{
    uint32_t H[5];
    uint32_t K[80];
    uint32_t A, B, C, D, E, TEMP;
    int r, k, ln, t, l, i, j;

    H[0] = 0x67452301;
    H[1] = 0xefcdab89;
    H[2] = 0x98badcfe;
    H[3] = 0x10325476;
    H[4] = 0xc3d2e1f0;

    ln = slen;
    r = (int)((ln + 1) / 64);

    if (((ln + 1) % 64) > 56)
    {
        r = r + 1;
    }

    // initialize Constants
    //pragma unroll
    for (t = 0; t < 80; t++)
    {
        if (t < 20)
        {
            K[t] = 0x5a827999;
        }

        if ((t > 19)& (t < 40))
        {
            K[t] = 0x6ED9EBA1;
        }
        if ((t > 39)& (t < 60))
        {
            K[t] = 0x8F1BBCDC;
        }
        if (t > 59)
        {
            K[t] = 0xca62c1d6;
        }
    }


    for (l = 0; l <= r; l++)
    {
        uint32_t W[80] = { 0 };
        //Initialize Text

        for (i = 0; i < 16; i++)
        {
            //pragma unroll
            for (j = 0; j < 4; j++)
            {
                if (4 * i + j < ln)
                {
                    k = s[64 * l + 4 * i + j];
                }
                else
                {
                    k = 0;
                }

                if (k < 0)
                {
                    k = k + 256;
                }

                if (4 * i + j == ln)
                {
                    k = 0x80;
                }

                //                              W[i]= W[i] + k*(uint32_t)pow(256,(double)3-j);
                W[i] = W[i] + k * expo_d[3 - j];
            }
        }
        if ((W[14] == 0) & (W[15] == 0))
        {
            W[15] = 8 * slen;
        }

        // Hash Cycle


        for (t = 16; t < 80; t++)
        {
            W[t] = Rol_CUDA(W[t - 3] ^ W[t - 8] ^ W[t - 14] ^ W[t - 16], 1);
        }

        A = H[0];
        B = H[1];
        C = H[2];
        D = H[3];
        E = H[4];

        for (t = 0; t < 80; t++)
        {
            TEMP = (Rol_CUDA(A, 5) + f_CUDA(B, C, D, t) + E + W[t] + K[t]);
            E = D;
            D = C;
            C = Rol_CUDA(B, 30);
            B = A;
            A = TEMP;
        }

        H[0] = H[0] + A;
        H[1] = H[1] + B;
        H[2] = H[2] + C;
        H[3] = H[3] + D;
        H[4] = H[4] + E;

        ln = ln - 64;
    }
    h0 = &H[0];
    h1 = &H[1];
    h2 = &H[3];
    h3 = &H[3];
    h4 = &H[4];

}
	.file	"tmpxft_00212e74_00000000-6_sha11.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2246:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2246:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z4SHA1PhiPjS0_S0_S0_S0_
	.type	_Z4SHA1PhiPjS0_S0_S0_S0_, @function
_Z4SHA1PhiPjS0_S0_S0_S0_:
.LFB2243:
	.cfi_startproc
	endbr64
	ret
	.cfi_endproc
.LFE2243:
	.size	_Z4SHA1PhiPjS0_S0_S0_S0_, .-_Z4SHA1PhiPjS0_S0_S0_S0_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"precalc_xorwow_matrix"
.LC1:
	.string	"precalc_xorwow_offset_matrix"
.LC2:
	.string	"mrg32k3aM1"
.LC3:
	.string	"mrg32k3aM2"
.LC4:
	.string	"mrg32k3aM1SubSeq"
.LC5:
	.string	"mrg32k3aM2SubSeq"
.LC6:
	.string	"mrg32k3aM1Seq"
.LC7:
	.string	"mrg32k3aM2Seq"
.LC8:
	.string	"__cr_lgamma_table"
.LC9:
	.string	"expo_d"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2269:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	movl	$102400, %r9d
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	movq	%rdx, %rcx
	leaq	_ZL21precalc_xorwow_matrix(%rip), %rsi
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC1(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$102400, %r9d
	leaq	_ZL28precalc_xorwow_offset_matrix(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM2(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM1SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM2SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM1Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM2Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC8(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$72, %r9d
	leaq	_ZL17__cr_lgamma_table(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC9(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$16, %r9d
	movq	%rdx, %rcx
	leaq	_ZL6expo_d(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2269:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL6expo_d
	.comm	_ZL6expo_d,16,16
	.local	_ZL17__cr_lgamma_table
	.comm	_ZL17__cr_lgamma_table,72,32
	.local	_ZL13mrg32k3aM2Seq
	.comm	_ZL13mrg32k3aM2Seq,2304,32
	.local	_ZL13mrg32k3aM1Seq
	.comm	_ZL13mrg32k3aM1Seq,2304,32
	.local	_ZL16mrg32k3aM2SubSeq
	.comm	_ZL16mrg32k3aM2SubSeq,2016,32
	.local	_ZL16mrg32k3aM1SubSeq
	.comm	_ZL16mrg32k3aM1SubSeq,2016,32
	.local	_ZL10mrg32k3aM2
	.comm	_ZL10mrg32k3aM2,2304,32
	.local	_ZL10mrg32k3aM1
	.comm	_ZL10mrg32k3aM1,2304,32
	.local	_ZL28precalc_xorwow_offset_matrix
	.comm	_ZL28precalc_xorwow_offset_matrix,102400,32
	.local	_ZL21precalc_xorwow_matrix
	.comm	_ZL21precalc_xorwow_matrix,102400,32
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <stdio.h>
#include <time.h>
#include <stdlib.h>
#include <stdint.h>

#include <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <hiprand/hiprand_kernel.h>
#include <hip/device_functions.h>
__constant__ uint32_t expo_d[4] = { 1, 256, 65536, 16777216 };

__device__ __host__ inline uint32_t f_CUDA(uint32_t B, uint32_t C, uint32_t D, int t)
{
    if (t < 20)
    {
        return ((B & C) ^ (~B & D));
    }
    if ((t > 19)& (t < 40))
    {
        return (B ^ C ^ D);
    }
    if ((t > 39)& (t < 60))
    {
        return ((B & C) ^ (B & D) ^ (C & D));
    }
    if (t > 59)
    {
        return (B ^ C ^ D);
    }
    return B;
}

__device__ __host__ inline uint32_t Rol_CUDA(uint32_t x, int y)
{
    if (y % 32 == 0) { return x; }
    else { return ((x << y) ^ (x >> -y)); }
}

//SHA1-Function
__device__ __host__ void SHA1(unsigned char* s, int slen, uint32_t *h0, uint32_t* h1, uint32_t* h2, uint32_t* h3, uint32_t* h4)
{
    uint32_t H[5];
    uint32_t K[80];
    uint32_t A, B, C, D, E, TEMP;
    int r, k, ln, t, l, i, j;

    H[0] = 0x67452301;
    H[1] = 0xefcdab89;
    H[2] = 0x98badcfe;
    H[3] = 0x10325476;
    H[4] = 0xc3d2e1f0;

    ln = slen;
    r = (int)((ln + 1) / 64);

    if (((ln + 1) % 64) > 56)
    {
        r = r + 1;
    }

    // initialize Constants
    //pragma unroll
    for (t = 0; t < 80; t++)
    {
        if (t < 20)
        {
            K[t] = 0x5a827999;
        }

        if ((t > 19)& (t < 40))
        {
            K[t] = 0x6ED9EBA1;
        }
        if ((t > 39)& (t < 60))
        {
            K[t] = 0x8F1BBCDC;
        }
        if (t > 59)
        {
            K[t] = 0xca62c1d6;
        }
    }


    for (l = 0; l <= r; l++)
    {
        uint32_t W[80] = { 0 };
        //Initialize Text

        for (i = 0; i < 16; i++)
        {
            //pragma unroll
            for (j = 0; j < 4; j++)
            {
                if (4 * i + j < ln)
                {
                    k = s[64 * l + 4 * i + j];
                }
                else
                {
                    k = 0;
                }

                if (k < 0)
                {
                    k = k + 256;
                }

                if (4 * i + j == ln)
                {
                    k = 0x80;
                }

                //                              W[i]= W[i] + k*(uint32_t)pow(256,(double)3-j);
                W[i] = W[i] + k * expo_d[3 - j];
            }
        }
        if ((W[14] == 0) & (W[15] == 0))
        {
            W[15] = 8 * slen;
        }

        // Hash Cycle


        for (t = 16; t < 80; t++)
        {
            W[t] = Rol_CUDA(W[t - 3] ^ W[t - 8] ^ W[t - 14] ^ W[t - 16], 1);
        }

        A = H[0];
        B = H[1];
        C = H[2];
        D = H[3];
        E = H[4];

        for (t = 0; t < 80; t++)
        {
            TEMP = (Rol_CUDA(A, 5) + f_CUDA(B, C, D, t) + E + W[t] + K[t]);
            E = D;
            D = C;
            C = Rol_CUDA(B, 30);
            B = A;
            A = TEMP;
        }

        H[0] = H[0] + A;
        H[1] = H[1] + B;
        H[2] = H[2] + C;
        H[3] = H[3] + D;
        H[4] = H[4] + E;

        ln = ln - 64;
    }
    h0 = &H[0];
    h1 = &H[1];
    h2 = &H[3];
    h3 = &H[3];
    h4 = &H[4];

}
	.text
	.file	"sha11.hip"
	.globl	_Z4SHA1PhiPjS0_S0_S0_S0_        # -- Begin function _Z4SHA1PhiPjS0_S0_S0_S0_
	.type	_Z4SHA1PhiPjS0_S0_S0_S0_,@function
_Z4SHA1PhiPjS0_S0_S0_S0_:               # @_Z4SHA1PhiPjS0_S0_S0_S0_
	.cfi_startproc
# %bb.0:                                # %.preheader93
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$344, %rsp                      # imm = 0x158
	.cfi_def_cfa_offset 400
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
                                        # kill: def $esi killed $esi def $rsi
	leal	1(%rsi), %eax
	leal	64(%rsi), %edx
	testl	%eax, %eax
	cmovnsl	%eax, %edx
	movl	%edx, %eax
	andl	$-64, %eax
	negl	%eax
	addl	%esi, %eax
	incl	%eax
	xorl	%ecx, %ecx
	cmpl	$57, %eax
	setge	%cl
	sarl	$6, %edx
	addl	%ecx, %edx
	movq	%rdx, (%rsp)                    # 8-byte Spill
	js	.LBB0_9
# %bb.1:                                # %.lr.ph
	movq	%rdi, %rbx
	movslq	%esi, %r12
	movq	(%rsp), %rax                    # 8-byte Reload
	incl	%eax
	movq	%rax, (%rsp)                    # 8-byte Spill
	xorl	%r13d, %r13d
	movl	$128, %ebp
	xorl	%r14d, %r14d
.LBB0_2:                                # =>This Loop Header: Depth=1
                                        #     Child Loop BB0_3 Depth 2
                                        #       Child Loop BB0_4 Depth 3
	movq	%r13, 8(%rsp)                   # 8-byte Spill
	shrq	$2, %r13
	movl	%r12d, %r15d
	negq	%r15
	movl	$320, %edx                      # imm = 0x140
	leaq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	memset@PLT
	xorl	%eax, %eax
	xorl	%ecx, %ecx
.LBB0_3:                                # %.preheader
                                        #   Parent Loop BB0_2 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB0_4 Depth 3
	leal	(,%r13,4), %edx
	addq	%rbx, %rdx
	movl	16(%rsp,%rcx,4), %esi
	leaq	(%r15,%rax), %rdi
	xorl	%r8d, %r8d
.LBB0_4:                                #   Parent Loop BB0_2 Depth=1
                                        #     Parent Loop BB0_3 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	leaq	(%rax,%r8), %r10
	xorl	%r9d, %r9d
	cmpq	%r12, %r10
	jge	.LBB0_6
# %bb.5:                                #   in Loop: Header=BB0_4 Depth=3
	movzbl	(%rdx,%r8), %r9d
.LBB0_6:                                #   in Loop: Header=BB0_4 Depth=3
	movq	%rdi, %r10
	addq	%r8, %r10
	cmovel	%ebp, %r9d
	movq	%r8, %r10
	xorq	$3, %r10
	imull	expo_d(,%r10,4), %r9d
	addl	%r9d, %esi
	incq	%r8
	cmpq	$4, %r8
	jne	.LBB0_4
# %bb.7:                                #   in Loop: Header=BB0_3 Depth=2
	movl	%esi, 16(%rsp,%rcx,4)
	incq	%rcx
	incl	%r13d
	addq	$4, %rax
	cmpq	$16, %rcx
	jne	.LBB0_3
# %bb.8:                                # %_Z6f_CUDAjjji.exit.preheader
                                        #   in Loop: Header=BB0_2 Depth=1
	addq	$-64, %r12
	incq	%r14
	movq	8(%rsp), %r13                   # 8-byte Reload
	addq	$64, %r13
	cmpq	(%rsp), %r14                    # 8-byte Folded Reload
	jne	.LBB0_2
.LBB0_9:                                # %._crit_edge
	addq	$344, %rsp                      # imm = 0x158
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z4SHA1PhiPjS0_S0_S0_S0_, .Lfunc_end0-_Z4SHA1PhiPjS0_S0_S0_S0_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rax
	.cfi_def_cfa_offset 16
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	movl	$expo_d, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$16, %r9d
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_adjust_cfa_offset 8
	pushq	$1
	.cfi_adjust_cfa_offset 8
	callq	__hipRegisterVar
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	movl	$__hip_module_dtor, %edi
	popq	%rax
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	expo_d,@object                  # @expo_d
	.local	expo_d
	.comm	expo_d,16,16
	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"expo_d"
	.size	.L__unnamed_1, 7

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym expo_d
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	expo_d                  ; @expo_d
	.type	expo_d,@object
	.data
	.globl	expo_d
	.p2align	4, 0x0
expo_d:
	.long	1                               ; 0x1
	.long	256                             ; 0x100
	.long	65536                           ; 0x10000
	.long	16777216                        ; 0x1000000
	.size	expo_d, 16

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym expo_d
	.addrsig_sym __hip_cuid_
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.amdgpu_metadata
---
amdhsa.kernels:  []
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
