#include <iostream>
#include <stdio.h>
#include <cuda.h>

#define BLOCK_SIZE 1024


#define checkCudaErrors(val) check( (val), #val, __FILE__, __LINE__)

template<typename T>
void check(T err, const char* const func, const char* const file, const int line) {
  if (err != cudaSuccess) {
    std::cerr << "CUDA error at: " << file << ":" << line << std::endl;
    std::cerr << cudaGetErrorString(err) << " " << func << std::endl;
    exit(1);
  }
}

#define cudaCheckErrors(msg) \
    do { \
        cudaError_t __err = cudaGetLastError(); \
        if (__err != cudaSuccess) { \
            fprintf(stderr, "Fatal error: %s (%s at %s:%d)\n", \
                msg, cudaGetErrorString(__err), \
                __FILE__, __LINE__); \
            fprintf(stderr, "*** FAILED - ABORTING\n"); \
            exit(1); \
        } \
    } while (0)

__global__ void max_min_cuda(float *d_in1, float *d_in2, float *d_max, float *d_min, size_t nb)
{
	int ft_id = threadIdx.x + blockDim.x * blockIdx.x;
	int tid = threadIdx.x;
	int size = (blockIdx.x == gridDim.x - 1) ? (nb % blockDim.x) : blockDim.x;
 
	for (size_t s = blockDim.x / 2; s > 0; s >>= 1)
	{
		if (ft_id + s < nb && tid < s)
		{
			d_in1[ft_id] = (d_in1[ft_id] > d_in1[ft_id + s]) ? d_in1[ft_id] : d_in1[ft_id + s];
			if (size % 2 == 1 && ft_id + s + s == size - 1)
				d_in1[ft_id] = (d_in1[ft_id] > d_in1[ft_id + s + s]) ? d_in1[ft_id] : d_in1[ft_id + s + s];
			d_in2[ft_id] = (d_in2[ft_id] < d_in2[ft_id + s]) ? d_in2[ft_id] : d_in2[ft_id + s];
			if (size % 2 == 1 && ft_id + s + s == size - 1)
				d_in2[ft_id] = (d_in2[ft_id] < d_in2[ft_id + s + s]) ? d_in2[ft_id] : d_in2[ft_id + s + s];
		}
		__syncthreads();
		size /= 2;
	}
	if (tid == 0)
	{
		d_max[blockIdx.x] = d_in1[ft_id];
		d_min[blockIdx.x] = d_in2[ft_id];
	}
	// __syncthreads();
	// for (int i = 0; i < GRID_SIZE; i++)
	// 	printf("d_out[%d] = %f\n", i, d_out[i]);
}

void				max_min(float *h_values, size_t size, float &h_min, float &h_max)
{
	size_t 		grid_size = size / BLOCK_SIZE + 1;

	float		*d_values;
	float		**d_values_ = &d_values;
	float		*d_values2;
	float		**d_values2_ = &d_values2;

	float		*maxs = (float *)malloc(sizeof(float) * grid_size);
	float		*d_max;
	float		**d_max_ = &d_max;

	float		*mins = (float *)malloc(sizeof(float) * grid_size);
	float		*d_min;
	float		**d_min_ = &d_min;


	// malloc values and max
	checkCudaErrors(cudaMalloc(d_values_, sizeof(float) * size));
	checkCudaErrors(cudaMalloc(d_values2_, sizeof(float) * size));
	checkCudaErrors(cudaMalloc(d_max_, sizeof(float) * grid_size));
	checkCudaErrors(cudaMalloc(d_min_, sizeof(float) * grid_size));

	// memcopy values
	checkCudaErrors(cudaMemcpy(d_values, h_values, sizeof(float) * size, cudaMemcpyHostToDevice));
	checkCudaErrors(cudaMemcpy(d_values2, h_values, sizeof(float) * size, cudaMemcpyHostToDevice));

	// kernel
	max_min_cuda<<<grid_size, BLOCK_SIZE>>>(d_values, d_values2, d_max, d_min, size);
	cudaDeviceSynchronize(); checkCudaErrors(cudaGetLastError());
	
	// printf("GRID SIZE %d\n", GRID_SIZE);

	// memcpy results
	checkCudaErrors(cudaMemcpy(maxs, d_max, sizeof(float) * grid_size, cudaMemcpyDeviceToHost));
	checkCudaErrors(cudaMemcpy(mins, d_min, sizeof(float) * grid_size, cudaMemcpyDeviceToHost));
	h_min = mins[0];
	h_max = maxs[0];
	for (int i = 0; i < grid_size; i++) {
	  if (h_max < maxs[i])
	    h_max = maxs[i];
	  if (h_min > mins[i])
	    h_min = mins[i];
	}

	// free the three
	cudaFree(d_max_);
	cudaFree(d_min_);
	cudaFree(d_values_);
	cudaFree(d_values2_);

}

	.file	"tmpxft_002ba5c8_00000000-6_max_min_reduce.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3639:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3639:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z39__device_stub__Z12max_min_cudaPfS_S_S_mPfS_S_S_m
	.type	_Z39__device_stub__Z12max_min_cudaPfS_S_S_mPfS_S_S_m, @function
_Z39__device_stub__Z12max_min_cudaPfS_S_S_mPfS_S_S_m:
.LFB3661:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z12max_min_cudaPfS_S_S_m(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L2:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3661:
	.size	_Z39__device_stub__Z12max_min_cudaPfS_S_S_mPfS_S_S_m, .-_Z39__device_stub__Z12max_min_cudaPfS_S_S_mPfS_S_S_m
	.globl	_Z12max_min_cudaPfS_S_S_m
	.type	_Z12max_min_cudaPfS_S_S_m, @function
_Z12max_min_cudaPfS_S_S_m:
.LFB3662:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z12max_min_cudaPfS_S_S_mPfS_S_S_m
	.cfi_endproc
.LFE3662:
	.size	_Z12max_min_cudaPfS_S_S_m, .-_Z12max_min_cudaPfS_S_S_m
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z12max_min_cudaPfS_S_S_m"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3664:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z12max_min_cudaPfS_S_S_m(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3664:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.rodata._Z5checkI9cudaErrorEvT_PKcS3_i.str1.1,"aMS",@progbits,1
.LC1:
	.string	"CUDA error at: "
.LC2:
	.string	":"
.LC3:
	.string	" "
	.section	.text._Z5checkI9cudaErrorEvT_PKcS3_i,"axG",@progbits,_Z5checkI9cudaErrorEvT_PKcS3_i,comdat
	.weak	_Z5checkI9cudaErrorEvT_PKcS3_i
	.type	_Z5checkI9cudaErrorEvT_PKcS3_i, @function
_Z5checkI9cudaErrorEvT_PKcS3_i:
.LFB3965:
	.cfi_startproc
	endbr64
	testl	%edi, %edi
	je	.L10
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movq	%rdx, %r14
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movl	%ecx, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	leaq	_ZSt4cerr(%rip), %r12
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movq	%rsi, %rbp
	leaq	.LC1(%rip), %rsi
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	movl	%edi, %ebx
	movq	%r12, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%r14, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC2(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%r13d, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movl	%ebx, %edi
	call	cudaGetErrorString@PLT
	movq	%r12, %rdi
	movq	%rax, %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC3(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rbp, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movl	$1, %edi
	call	exit@PLT
.L10:
	.cfi_def_cfa_offset 8
	.cfi_restore 3
	.cfi_restore 6
	.cfi_restore 12
	.cfi_restore 13
	.cfi_restore 14
	ret
	.cfi_endproc
.LFE3965:
	.size	_Z5checkI9cudaErrorEvT_PKcS3_i, .-_Z5checkI9cudaErrorEvT_PKcS3_i
	.section	.rodata.str1.1
.LC4:
	.string	"/home/ubuntu/Datasets/stackv2/train-structured/valentinlehuger/testCuda/master/udacity/max_min_reduce.cu"
.LC5:
	.string	"cudaMalloc(d_values_, sizeof(float) * size)"
.LC6:
	.string	"cudaMalloc(d_values2_, sizeof(float) * size)"
.LC7:
	.string	"cudaMalloc(d_max_, sizeof(float) * grid_size)"
.LC8:
	.string	"cudaMalloc(d_min_, sizeof(float) * grid_size)"
.LC9:
	.string	"cudaMemcpy(d_values, h_values, sizeof(float) * size, cudaMemcpyHostToDevice)"
.LC10:
	.string	"cudaMemcpy(d_values2, h_values, sizeof(float) * size, cudaMemcpyHostToDevice)"
.LC11:
	.string	"cudaGetLastError()"
.LC12:
	.string	"cudaMemcpy(maxs, d_max, sizeof(float) * grid_size, cudaMemcpyDeviceToHost)"
.LC13:
	.string	"cudaMemcpy(mins, d_min, sizeof(float) * grid_size, cudaMemcpyDeviceToHost)"
	.text
	.globl	_Z7max_minPfmRfS0_
	.type	_Z7max_minPfmRfS0_, @function
_Z7max_minPfmRfS0_:
.LFB3636:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rsi, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rcx, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rdx, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rsi, %rbx
	shrq	$10, %rbx
	incq	%rbx
	subq	$120, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 16(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	0(,%rbx,4), %rax
	movq	%rax, %rdi
	movq	%rax, (%rsp)
	call	malloc@PLT
	leaq	0(,%rbx,4), %rdi
	movq	%rax, %rbp
	call	malloc@PLT
	leaq	0(,%r15,4), %rsi
	movq	%rax, %r12
	leaq	0(,%r15,4), %rax
	movq	%rax, 8(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, %rdi
	movq	%rax, 24(%rsp)
	call	cudaMalloc@PLT
	movl	$80, %ecx
	leaq	.LC4(%rip), %rdx
	leaq	.LC5(%rip), %rsi
	movl	%eax, %edi
	call	_Z5checkI9cudaErrorEvT_PKcS3_i
	leaq	56(%rsp), %rax
	movq	8(%rsp), %rsi
	movq	%rax, %rdi
	movq	%rax, 32(%rsp)
	call	cudaMalloc@PLT
	movl	$81, %ecx
	leaq	.LC4(%rip), %rdx
	leaq	.LC6(%rip), %rsi
	movl	%eax, %edi
	call	_Z5checkI9cudaErrorEvT_PKcS3_i
	leaq	64(%rsp), %rax
	movq	(%rsp), %rsi
	movq	%rax, %rdi
	movq	%rax, 40(%rsp)
	call	cudaMalloc@PLT
	movl	$82, %ecx
	leaq	.LC4(%rip), %rdx
	leaq	.LC7(%rip), %rsi
	movl	%eax, %edi
	call	_Z5checkI9cudaErrorEvT_PKcS3_i
	movq	(%rsp), %rsi
	leaq	72(%rsp), %rdi
	call	cudaMalloc@PLT
	movl	$83, %ecx
	leaq	.LC4(%rip), %rdx
	leaq	.LC8(%rip), %rsi
	movl	%eax, %edi
	call	_Z5checkI9cudaErrorEvT_PKcS3_i
	movq	8(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	$1, %ecx
	movq	48(%rsp), %rdi
	call	cudaMemcpy@PLT
	movl	$86, %ecx
	leaq	.LC4(%rip), %rdx
	leaq	.LC9(%rip), %rsi
	movl	%eax, %edi
	call	_Z5checkI9cudaErrorEvT_PKcS3_i
	movq	8(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	$1, %ecx
	movq	56(%rsp), %rdi
	call	cudaMemcpy@PLT
	movl	$87, %ecx
	leaq	.LC4(%rip), %rdx
	leaq	.LC10(%rip), %rsi
	movl	%eax, %edi
	call	_Z5checkI9cudaErrorEvT_PKcS3_i
	movl	%ebx, 80(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rax
	movl	$4194305, %edx
	movl	$1, %ecx
	movq	%rax, 84(%rsp)
	movq	80(%rsp), %rdi
	salq	$10, %rdx
	movl	88(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	movq	72(%rsp), %rcx
	movq	64(%rsp), %rdx
	movq	%r15, %r8
	movq	56(%rsp), %rsi
	movq	48(%rsp), %rdi
	call	_Z39__device_stub__Z12max_min_cudaPfS_S_S_mPfS_S_S_m
.L16:
	call	cudaDeviceSynchronize@PLT
	call	cudaGetLastError@PLT
	movl	$91, %ecx
	leaq	.LC4(%rip), %rdx
	leaq	.LC11(%rip), %rsi
	movl	%eax, %edi
	call	_Z5checkI9cudaErrorEvT_PKcS3_i
	movq	(%rsp), %rdx
	movq	64(%rsp), %rsi
	movq	%rbp, %rdi
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	movl	$96, %ecx
	leaq	.LC4(%rip), %rdx
	leaq	.LC12(%rip), %rsi
	movl	%eax, %edi
	call	_Z5checkI9cudaErrorEvT_PKcS3_i
	movq	(%rsp), %rdx
	movq	72(%rsp), %rsi
	movq	%r12, %rdi
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	movl	$97, %ecx
	leaq	.LC4(%rip), %rdx
	leaq	.LC13(%rip), %rsi
	movl	%eax, %edi
	call	_Z5checkI9cudaErrorEvT_PKcS3_i
	movss	(%r12), %xmm0
	xorl	%eax, %eax
	movss	%xmm0, 0(%r13)
	movss	0(%rbp), %xmm0
	movss	%xmm0, (%r14)
.L21:
	movss	0(%rbp,%rax,4), %xmm0
	comiss	(%r14), %xmm0
	jbe	.L17
	movss	%xmm0, (%r14)
.L17:
	movss	(%r12,%rax,4), %xmm0
	movss	0(%r13), %xmm1
	comiss	%xmm0, %xmm1
	jbe	.L19
	movss	%xmm0, 0(%r13)
.L19:
	incq	%rax
	cmpq	%rbx, %rax
	jb	.L21
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	leaq	72(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L22
	call	__stack_chk_fail@PLT
.L22:
	addq	$120, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3636:
	.size	_Z7max_minPfmRfS0_, .-_Z7max_minPfmRfS0_
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <stdio.h>
#include <hip/hip_runtime.h>

#define BLOCK_SIZE 1024


#define checkCudaErrors(val) check( (val), #val, __FILE__, __LINE__)

template<typename T>
void check(T err, const char* const func, const char* const file, const int line) {
  if (err != hipSuccess) {
    std::cerr << "CUDA error at: " << file << ":" << line << std::endl;
    std::cerr << hipGetErrorString(err) << " " << func << std::endl;
    exit(1);
  }
}

#define cudaCheckErrors(msg) \
    do { \
        hipError_t __err = hipGetLastError(); \
        if (__err != hipSuccess) { \
            fprintf(stderr, "Fatal error: %s (%s at %s:%d)\n", \
                msg, hipGetErrorString(__err), \
                __FILE__, __LINE__); \
            fprintf(stderr, "*** FAILED - ABORTING\n"); \
            exit(1); \
        } \
    } while (0)

__global__ void max_min_cuda(float *d_in1, float *d_in2, float *d_max, float *d_min, size_t nb)
{
	int ft_id = threadIdx.x + blockDim.x * blockIdx.x;
	int tid = threadIdx.x;
	int size = (blockIdx.x == gridDim.x - 1) ? (nb % blockDim.x) : blockDim.x;
 
	for (size_t s = blockDim.x / 2; s > 0; s >>= 1)
	{
		if (ft_id + s < nb && tid < s)
		{
			d_in1[ft_id] = (d_in1[ft_id] > d_in1[ft_id + s]) ? d_in1[ft_id] : d_in1[ft_id + s];
			if (size % 2 == 1 && ft_id + s + s == size - 1)
				d_in1[ft_id] = (d_in1[ft_id] > d_in1[ft_id + s + s]) ? d_in1[ft_id] : d_in1[ft_id + s + s];
			d_in2[ft_id] = (d_in2[ft_id] < d_in2[ft_id + s]) ? d_in2[ft_id] : d_in2[ft_id + s];
			if (size % 2 == 1 && ft_id + s + s == size - 1)
				d_in2[ft_id] = (d_in2[ft_id] < d_in2[ft_id + s + s]) ? d_in2[ft_id] : d_in2[ft_id + s + s];
		}
		__syncthreads();
		size /= 2;
	}
	if (tid == 0)
	{
		d_max[blockIdx.x] = d_in1[ft_id];
		d_min[blockIdx.x] = d_in2[ft_id];
	}
	// __syncthreads();
	// for (int i = 0; i < GRID_SIZE; i++)
	// 	printf("d_out[%d] = %f\n", i, d_out[i]);
}

void				max_min(float *h_values, size_t size, float &h_min, float &h_max)
{
	size_t 		grid_size = size / BLOCK_SIZE + 1;

	float		*d_values;
	float		**d_values_ = &d_values;
	float		*d_values2;
	float		**d_values2_ = &d_values2;

	float		*maxs = (float *)malloc(sizeof(float) * grid_size);
	float		*d_max;
	float		**d_max_ = &d_max;

	float		*mins = (float *)malloc(sizeof(float) * grid_size);
	float		*d_min;
	float		**d_min_ = &d_min;


	// malloc values and max
	checkCudaErrors(hipMalloc(d_values_, sizeof(float) * size));
	checkCudaErrors(hipMalloc(d_values2_, sizeof(float) * size));
	checkCudaErrors(hipMalloc(d_max_, sizeof(float) * grid_size));
	checkCudaErrors(hipMalloc(d_min_, sizeof(float) * grid_size));

	// memcopy values
	checkCudaErrors(hipMemcpy(d_values, h_values, sizeof(float) * size, hipMemcpyHostToDevice));
	checkCudaErrors(hipMemcpy(d_values2, h_values, sizeof(float) * size, hipMemcpyHostToDevice));

	// kernel
	max_min_cuda<<<grid_size, BLOCK_SIZE>>>(d_values, d_values2, d_max, d_min, size);
	hipDeviceSynchronize(); checkCudaErrors(hipGetLastError());
	
	// printf("GRID SIZE %d\n", GRID_SIZE);

	// memcpy results
	checkCudaErrors(hipMemcpy(maxs, d_max, sizeof(float) * grid_size, hipMemcpyDeviceToHost));
	checkCudaErrors(hipMemcpy(mins, d_min, sizeof(float) * grid_size, hipMemcpyDeviceToHost));
	h_min = mins[0];
	h_max = maxs[0];
	for (int i = 0; i < grid_size; i++) {
	  if (h_max < maxs[i])
	    h_max = maxs[i];
	  if (h_min > mins[i])
	    h_min = mins[i];
	}

	// free the three
	hipFree(d_max_);
	hipFree(d_min_);
	hipFree(d_values_);
	hipFree(d_values2_);

}

	.text
	.file	"max_min_reduce.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z27__device_stub__max_min_cudaPfS_S_S_m # -- Begin function _Z27__device_stub__max_min_cudaPfS_S_S_m
	.type	_Z27__device_stub__max_min_cudaPfS_S_S_m,@function
_Z27__device_stub__max_min_cudaPfS_S_S_m: # @_Z27__device_stub__max_min_cudaPfS_S_S_m
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12max_min_cudaPfS_S_S_m, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z27__device_stub__max_min_cudaPfS_S_S_m, .Lfunc_end0-_Z27__device_stub__max_min_cudaPfS_S_S_m
	.cfi_endproc
                                        # -- End function
	.globl	_Z7max_minPfmRfS0_              # -- Begin function _Z7max_minPfmRfS0_
	.type	_Z7max_minPfmRfS0_,@function
_Z7max_minPfmRfS0_:                     # @_Z7max_minPfmRfS0_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rcx, %rbx
	movq	%rdx, %r14
	movq	%rsi, %rbp
	movq	%rdi, 64(%rsp)                  # 8-byte Spill
	movq	%rsi, %r13
	shrq	$10, %r13
	leaq	4(,%r13,4), %r12
	movq	%r12, 48(%rsp)                  # 8-byte Spill
	incq	%r13
	movq	%r12, %rdi
	callq	malloc
	movq	%rax, %r15
	movq	%r12, %rdi
	callq	malloc
	movq	%rax, %r12
	movq	%rbp, 56(%rsp)                  # 8-byte Spill
	leaq	(,%rbp,4), %rbp
	leaq	32(%rsp), %rdi
	movq	%rbp, %rsi
	movq	%rbp, 40(%rsp)                  # 8-byte Spill
	callq	hipMalloc
	movl	$.L.str, %esi
	movl	$.L.str.1, %edx
	movl	%eax, %edi
	movl	$80, %ecx
	callq	_Z5checkI10hipError_tEvT_PKcS3_i
	leaq	24(%rsp), %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	movl	$.L.str.2, %esi
	movl	$.L.str.1, %edx
	movl	%eax, %edi
	movl	$81, %ecx
	callq	_Z5checkI10hipError_tEvT_PKcS3_i
	leaq	16(%rsp), %rdi
	movq	48(%rsp), %rbp                  # 8-byte Reload
	movq	%rbp, %rsi
	callq	hipMalloc
	movl	$.L.str.3, %esi
	movl	$.L.str.1, %edx
	movl	%eax, %edi
	movl	$82, %ecx
	callq	_Z5checkI10hipError_tEvT_PKcS3_i
	leaq	8(%rsp), %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	movl	$.L.str.4, %esi
	movl	$.L.str.1, %edx
	movl	%eax, %edi
	movl	$83, %ecx
	callq	_Z5checkI10hipError_tEvT_PKcS3_i
	leaq	32(%rsp), %rax
	movq	(%rax), %rdi
	movq	64(%rsp), %rbp                  # 8-byte Reload
	movq	%rbp, %rsi
	movq	40(%rsp), %rdx                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$.L.str.5, %esi
	movl	$.L.str.1, %edx
	movl	%eax, %edi
	movl	$86, %ecx
	callq	_Z5checkI10hipError_tEvT_PKcS3_i
	leaq	24(%rsp), %rax
	movq	(%rax), %rdi
	movq	%rbp, %rsi
	movq	40(%rsp), %rdx                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$.L.str.6, %esi
	movl	$.L.str.1, %edx
	movl	%eax, %edi
	movl	$87, %ecx
	callq	_Z5checkI10hipError_tEvT_PKcS3_i
	movl	%r13d, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$1024, %rdx                     # imm = 0x400
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_2
# %bb.1:
	movq	32(%rsp), %rdi
	movq	24(%rsp), %rsi
	movq	16(%rsp), %rdx
	movq	8(%rsp), %rcx
	movq	56(%rsp), %r8                   # 8-byte Reload
	callq	_Z27__device_stub__max_min_cudaPfS_S_S_m
.LBB1_2:
	callq	hipDeviceSynchronize
	callq	hipGetLastError
	movl	$.L.str.7, %esi
	movl	$.L.str.1, %edx
	movl	%eax, %edi
	movl	$91, %ecx
	callq	_Z5checkI10hipError_tEvT_PKcS3_i
	movq	16(%rsp), %rsi
	movq	%r15, %rdi
	movq	48(%rsp), %rbp                  # 8-byte Reload
	movq	%rbp, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$.L.str.8, %esi
	movl	$.L.str.1, %edx
	movl	%eax, %edi
	movl	$96, %ecx
	callq	_Z5checkI10hipError_tEvT_PKcS3_i
	movq	8(%rsp), %rsi
	movq	%r12, %rdi
	movq	%rbp, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$.L.str.9, %esi
	movl	$.L.str.1, %edx
	movl	%eax, %edi
	movl	$97, %ecx
	callq	_Z5checkI10hipError_tEvT_PKcS3_i
	movss	(%r12), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, (%r14)
	movss	(%r15), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	movss	%xmm0, (%rbx)
	xorl	%eax, %eax
.LBB1_3:                                # =>This Inner Loop Header: Depth=1
	movss	(%r15,%rax,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	ucomiss	(%rbx), %xmm0
	jbe	.LBB1_5
# %bb.4:                                #   in Loop: Header=BB1_3 Depth=1
	movss	%xmm0, (%rbx)
.LBB1_5:                                #   in Loop: Header=BB1_3 Depth=1
	movss	(%r14), %xmm1                   # xmm1 = mem[0],zero,zero,zero
	movss	(%r12,%rax,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	ucomiss	%xmm0, %xmm1
	jbe	.LBB1_7
# %bb.6:                                #   in Loop: Header=BB1_3 Depth=1
	movss	%xmm0, (%r14)
.LBB1_7:                                #   in Loop: Header=BB1_3 Depth=1
	incq	%rax
	cmpq	%rax, %r13
	jne	.LBB1_3
# %bb.8:
	leaq	16(%rsp), %rdi
	callq	hipFree
	leaq	8(%rsp), %rdi
	callq	hipFree
	leaq	32(%rsp), %rdi
	callq	hipFree
	leaq	24(%rsp), %rdi
	callq	hipFree
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z7max_minPfmRfS0_, .Lfunc_end1-_Z7max_minPfmRfS0_
	.cfi_endproc
                                        # -- End function
	.section	.text._Z5checkI10hipError_tEvT_PKcS3_i,"axG",@progbits,_Z5checkI10hipError_tEvT_PKcS3_i,comdat
	.weak	_Z5checkI10hipError_tEvT_PKcS3_i # -- Begin function _Z5checkI10hipError_tEvT_PKcS3_i
	.type	_Z5checkI10hipError_tEvT_PKcS3_i,@function
_Z5checkI10hipError_tEvT_PKcS3_i:       # @_Z5checkI10hipError_tEvT_PKcS3_i
	.cfi_startproc
# %bb.0:
	testl	%edi, %edi
	jne	.LBB2_2
# %bb.1:
	retq
.LBB2_2:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%ecx, %r14d
	movq	%rdx, %r15
	movq	%rsi, %rbx
	movl	%edi, %ebp
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.10, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	movq	%r15, %rsi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.11, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	movl	%r14d, %esi
	callq	_ZNSolsEi
	movq	%rax, %rdi
	callq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
	movl	%ebp, %edi
	callq	hipGetErrorString
	movl	$_ZSt4cerr, %edi
	movq	%rax, %rsi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.12, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	movq	%rbx, %rsi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	callq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
	movl	$1, %edi
	callq	exit
.Lfunc_end2:
	.size	_Z5checkI10hipError_tEvT_PKcS3_i, .Lfunc_end2-_Z5checkI10hipError_tEvT_PKcS3_i
	.cfi_endproc
                                        # -- End function
	.text
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12max_min_cudaPfS_S_S_m, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z12max_min_cudaPfS_S_S_m,@object # @_Z12max_min_cudaPfS_S_S_m
	.section	.rodata,"a",@progbits
	.globl	_Z12max_min_cudaPfS_S_S_m
	.p2align	3, 0x0
_Z12max_min_cudaPfS_S_S_m:
	.quad	_Z27__device_stub__max_min_cudaPfS_S_S_m
	.size	_Z12max_min_cudaPfS_S_S_m, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"hipMalloc(d_values_, sizeof(float) * size)"
	.size	.L.str, 43

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"/home/ubuntu/Datasets/stackv2/train-structured-repos-hip-sm89/valentinlehuger/testCuda/master/udacity/max_min_reduce.hip"
	.size	.L.str.1, 121

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"hipMalloc(d_values2_, sizeof(float) * size)"
	.size	.L.str.2, 44

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"hipMalloc(d_max_, sizeof(float) * grid_size)"
	.size	.L.str.3, 45

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"hipMalloc(d_min_, sizeof(float) * grid_size)"
	.size	.L.str.4, 45

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"hipMemcpy(d_values, h_values, sizeof(float) * size, hipMemcpyHostToDevice)"
	.size	.L.str.5, 75

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"hipMemcpy(d_values2, h_values, sizeof(float) * size, hipMemcpyHostToDevice)"
	.size	.L.str.6, 76

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"hipGetLastError()"
	.size	.L.str.7, 18

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"hipMemcpy(maxs, d_max, sizeof(float) * grid_size, hipMemcpyDeviceToHost)"
	.size	.L.str.8, 73

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"hipMemcpy(mins, d_min, sizeof(float) * grid_size, hipMemcpyDeviceToHost)"
	.size	.L.str.9, 73

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"CUDA error at: "
	.size	.L.str.10, 16

	.type	.L.str.11,@object               # @.str.11
.L.str.11:
	.asciz	":"
	.size	.L.str.11, 2

	.type	.L.str.12,@object               # @.str.12
.L.str.12:
	.asciz	" "
	.size	.L.str.12, 2

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z12max_min_cudaPfS_S_S_m"
	.size	.L__unnamed_1, 26

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z27__device_stub__max_min_cudaPfS_S_S_m
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z12max_min_cudaPfS_S_S_m
	.addrsig_sym _ZSt4cerr
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z12max_min_cudaPfS_S_S_m ; -- Begin function _Z12max_min_cudaPfS_S_S_m
	.globl	_Z12max_min_cudaPfS_S_S_m
	.p2align	8
	.type	_Z12max_min_cudaPfS_S_S_m,@function
_Z12max_min_cudaPfS_S_S_m:              ; @_Z12max_min_cudaPfS_S_S_m
; %bb.0:
	s_clause 0x3
	s_load_b32 s3, s[0:1], 0x28
	s_load_b32 s14, s[0:1], 0x34
	s_load_b64 s[12:13], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_mov_b32 s2, s15
	s_waitcnt lgkmcnt(0)
	s_add_i32 s3, s3, -1
	s_and_b32 s0, s14, 0xffff
	s_cmp_lg_u32 s15, s3
	s_mov_b32 s3, s0
	s_cbranch_scc1 .LBB0_2
; %bb.1:
	v_cvt_f32_u32_e32 v1, s0
	s_sub_u32 s14, 0, s0
	s_subb_u32 s15, 0, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmamk_f32 v1, 0, 0x4f800000, v1
	v_rcp_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x5f7ffffc, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, 0x2f800000, v1
	v_trunc_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmamk_f32 v1, v2, 0xcf800000, v1
	v_cvt_u32_f32_e32 v2, v2
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s1, v2
	v_readfirstlane_b32 s3, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mul_i32 s16, s14, s1
	s_mul_hi_u32 s18, s14, s3
	s_mul_i32 s17, s15, s3
	s_add_i32 s16, s18, s16
	s_mul_i32 s19, s14, s3
	s_add_i32 s16, s16, s17
	s_mul_hi_u32 s18, s3, s19
	s_mul_hi_u32 s20, s1, s19
	s_mul_i32 s17, s1, s19
	s_mul_hi_u32 s19, s3, s16
	s_mul_i32 s3, s3, s16
	s_mul_hi_u32 s21, s1, s16
	s_add_u32 s3, s18, s3
	s_addc_u32 s18, 0, s19
	s_add_u32 s3, s3, s17
	s_mul_i32 s16, s1, s16
	s_addc_u32 s3, s18, s20
	s_addc_u32 s17, s21, 0
	s_add_u32 s3, s3, s16
	s_addc_u32 s16, 0, s17
	v_add_co_u32 v1, s3, v1, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s3, 0
	s_addc_u32 s1, s1, s16
	v_readfirstlane_b32 s3, v1
	s_mul_i32 s16, s14, s1
	s_delay_alu instid0(VALU_DEP_1)
	s_mul_hi_u32 s17, s14, s3
	s_mul_i32 s15, s15, s3
	s_add_i32 s16, s17, s16
	s_mul_i32 s14, s14, s3
	s_add_i32 s16, s16, s15
	s_mul_hi_u32 s17, s1, s14
	s_mul_i32 s18, s1, s14
	s_mul_hi_u32 s14, s3, s14
	s_mul_hi_u32 s19, s3, s16
	s_mul_i32 s3, s3, s16
	s_mul_hi_u32 s15, s1, s16
	s_add_u32 s3, s14, s3
	s_addc_u32 s14, 0, s19
	s_add_u32 s3, s3, s18
	s_mul_i32 s16, s1, s16
	s_addc_u32 s3, s14, s17
	s_addc_u32 s14, s15, 0
	s_add_u32 s3, s3, s16
	s_addc_u32 s14, 0, s14
	v_add_co_u32 v1, s3, v1, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s3, 0
	s_addc_u32 s1, s1, s14
	v_readfirstlane_b32 s3, v1
	s_mul_i32 s15, s12, s1
	s_mul_hi_u32 s14, s12, s1
	s_mul_hi_u32 s16, s13, s1
	s_mul_i32 s1, s13, s1
	s_mul_hi_u32 s17, s12, s3
	s_mul_hi_u32 s18, s13, s3
	s_mul_i32 s3, s13, s3
	s_add_u32 s15, s17, s15
	s_addc_u32 s14, 0, s14
	s_add_u32 s3, s15, s3
	s_addc_u32 s3, s14, s18
	s_addc_u32 s14, s16, 0
	s_add_u32 s1, s3, s1
	s_addc_u32 s14, 0, s14
	s_mul_i32 s3, s0, s1
	s_mul_hi_u32 s1, s0, s1
	v_sub_co_u32 v1, s3, s12, s3
	s_mul_i32 s14, s0, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s1, s1, s14
	v_sub_co_u32 v2, s15, v1, s0
	s_cmp_lg_u32 s3, 0
	s_subb_u32 s1, s13, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s3, v2
	s_cmp_lg_u32 s15, 0
	s_subb_u32 s14, s1, 0
	s_cmp_ge_u32 s3, s0
	s_cselect_b32 s15, -1, 0
	s_cmp_eq_u32 s14, 0
	v_readfirstlane_b32 s14, v1
	s_cselect_b32 s15, s15, -1
	s_sub_i32 s16, s3, s0
	s_cmp_lg_u32 s15, 0
	s_cselect_b32 s3, s16, s3
	s_cmp_ge_u32 s14, s0
	s_cselect_b32 s15, -1, 0
	s_cmp_eq_u32 s1, 0
	s_cselect_b32 s1, s15, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s1, 0
	s_cselect_b32 s3, s3, s14
.LBB0_2:
	v_mad_u64_u32 v[2:3], null, s2, s0, v[0:1]
	s_cmp_lt_u32 s0, 2
	s_delay_alu instid0(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	s_cbranch_scc1 .LBB0_13
; %bb.3:                                ; %.lr.ph
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[6:7], 2, v[2:3]
	v_mov_b32_e32 v1, 0
	s_lshr_b32 s14, s0, 1
	s_mov_b32 s15, 0
	v_add_co_u32 v4, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v7, vcc_lo
	v_add_co_u32 v6, vcc_lo, s6, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
.LBB0_4:                                ; =>This Inner Loop Header: Depth=1
	v_add_co_u32 v8, vcc_lo, s14, v2
	v_add_co_ci_u32_e32 v9, vcc_lo, s15, v3, vcc_lo
	v_cmp_gt_u64_e64 s0, s[14:15], v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_u64_e32 vcc_lo, s[12:13], v[8:9]
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s16, s0
	s_cbranch_execz .LBB0_12
; %bb.5:                                ;   in Loop: Header=BB0_4 Depth=1
	s_lshl_b64 s[0:1], s[14:15], 2
	s_and_b32 s18, s3, 1
	v_add_co_u32 v10, vcc_lo, v4, s0
	v_add_co_ci_u32_e32 v11, vcc_lo, s1, v5, vcc_lo
	s_bitcmp1_b32 s3, 0
	s_clause 0x1
	global_load_b32 v12, v[4:5], off
	global_load_b32 v13, v[10:11], off
	s_cselect_b32 s17, -1, 0
	s_cmp_eq_u32 s18, 0
	s_waitcnt vmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v12, v13
	v_cndmask_b32_e32 v12, v13, v12, vcc_lo
	global_store_b32 v[4:5], v12, off
	s_cbranch_scc1 .LBB0_9
; %bb.6:                                ;   in Loop: Header=BB0_4 Depth=1
	v_add_co_u32 v13, vcc_lo, v8, s14
	v_add_co_ci_u32_e32 v14, vcc_lo, s15, v9, vcc_lo
	s_add_i32 s18, s3, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_ashr_i32 s19, s18, 31
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_eq_u64_e32 vcc_lo, s[18:19], v[13:14]
	s_and_saveexec_b32 s18, vcc_lo
	s_cbranch_execz .LBB0_8
; %bb.7:                                ;   in Loop: Header=BB0_4 Depth=1
	v_add_co_u32 v10, vcc_lo, v10, s0
	v_add_co_ci_u32_e32 v11, vcc_lo, s1, v11, vcc_lo
	global_load_b32 v10, v[10:11], off
	s_waitcnt vmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, v12, v10
	v_cndmask_b32_e32 v10, v10, v12, vcc_lo
	global_store_b32 v[4:5], v10, off
.LBB0_8:                                ; %Flow114
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s18
.LBB0_9:                                ;   in Loop: Header=BB0_4 Depth=1
	v_add_co_u32 v10, vcc_lo, v6, s0
	v_add_co_ci_u32_e32 v11, vcc_lo, s1, v7, vcc_lo
	s_clause 0x1
	global_load_b32 v12, v[6:7], off
	global_load_b32 v13, v[10:11], off
	s_waitcnt vmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v12, v13
	v_cndmask_b32_e32 v12, v13, v12, vcc_lo
	s_and_not1_b32 vcc_lo, exec_lo, s17
	global_store_b32 v[6:7], v12, off
	s_cbranch_vccnz .LBB0_12
; %bb.10:                               ;   in Loop: Header=BB0_4 Depth=1
	v_add_co_u32 v8, vcc_lo, v8, s14
	v_add_co_ci_u32_e32 v9, vcc_lo, s15, v9, vcc_lo
	s_add_i32 s18, s3, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_ashr_i32 s19, s18, 31
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_eq_u64_e32 vcc_lo, s[18:19], v[8:9]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_12
; %bb.11:                               ;   in Loop: Header=BB0_4 Depth=1
	v_add_co_u32 v8, vcc_lo, v10, s0
	v_add_co_ci_u32_e32 v9, vcc_lo, s1, v11, vcc_lo
	global_load_b32 v8, v[8:9], off
	s_waitcnt vmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v12, v8
	v_cndmask_b32_e32 v8, v8, v12, vcc_lo
	global_store_b32 v[6:7], v8, off
.LBB0_12:                               ; %Flow115
                                        ;   in Loop: Header=BB0_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s16
	v_cmp_lt_u64_e64 s0, s[14:15], 2
	s_lshr_b32 s3, s3, 1
	s_lshr_b64 s[14:15], s[14:15], 1
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB0_4
.LBB0_13:                               ; %._crit_edge
	s_mov_b32 s3, 0
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_15
; %bb.14:
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	s_lshl_b64 s[0:1], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_add_u32 s2, s10, s0
	s_addc_u32 s3, s11, s1
	s_add_u32 s0, s8, s0
	v_add_co_u32 v2, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	global_load_b32 v2, v[2:3], off
	v_mov_b32_e32 v3, 0
	s_addc_u32 s1, s9, s1
	s_waitcnt vmcnt(0)
	global_store_b32 v3, v2, s[0:1]
	global_load_b32 v0, v[0:1], off
	s_waitcnt vmcnt(0)
	global_store_b32 v3, v0, s[2:3]
.LBB0_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12max_min_cudaPfS_S_S_m
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z12max_min_cudaPfS_S_S_m, .Lfunc_end0-_Z12max_min_cudaPfS_S_S_m
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1140
; NumSgprs: 24
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12max_min_cudaPfS_S_S_m
    .private_segment_fixed_size: 0
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         _Z12max_min_cudaPfS_S_S_m.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     15
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
