#include <stdio.h>
#include <time.h>   

//original c by brade conte, ported to CUDA by jody

#define uchar unsigned char // 8-bit byte
#define uint unsigned int // 32-bit word


#define DBL_INT_ADD(a,b,c) if (a > 0xffffffff - (c)) ++b; a += c;
#define ROTLEFT(a,b) (((a) << (b)) | ((a) >> (32-(b))))
#define ROTRIGHT(a,b) (((a) >> (b)) | ((a) << (32-(b))))

#define CH(x,y,z) (((x) & (y)) ^ (~(x) & (z)))
#define MAJ(x,y,z) (((x) & (y)) ^ ((x) & (z)) ^ ((y) & (z)))
#define EP0(x) (ROTRIGHT(x,2) ^ ROTRIGHT(x,13) ^ ROTRIGHT(x,22))
#define EP1(x) (ROTRIGHT(x,6) ^ ROTRIGHT(x,11) ^ ROTRIGHT(x,25))
#define SIG0(x) (ROTRIGHT(x,7) ^ ROTRIGHT(x,18) ^ ((x) >> 3))
#define SIG1(x) (ROTRIGHT(x,17) ^ ROTRIGHT(x,19) ^ ((x) >> 10))

typedef struct{
   uchar data[64];
   uint datalen;
   uint bitlen[2];
   uint state[8];
} SHA256_CTX;

__device__ uint k[64] = {
   0x428a2f98,0x71374491,0xb5c0fbcf,0xe9b5dba5,0x3956c25b,0x59f111f1,0x923f82a4,0xab1c5ed5,
   0xd807aa98,0x12835b01,0x243185be,0x550c7dc3,0x72be5d74,0x80deb1fe,0x9bdc06a7,0xc19bf174,
   0xe49b69c1,0xefbe4786,0x0fc19dc6,0x240ca1cc,0x2de92c6f,0x4a7484aa,0x5cb0a9dc,0x76f988da,
   0x983e5152,0xa831c66d,0xb00327c8,0xbf597fc7,0xc6e00bf3,0xd5a79147,0x06ca6351,0x14292967,
   0x27b70a85,0x2e1b2138,0x4d2c6dfc,0x53380d13,0x650a7354,0x766a0abb,0x81c2c92e,0x92722c85,
   0xa2bfe8a1,0xa81a664b,0xc24b8b70,0xc76c51a3,0xd192e819,0xd6990624,0xf40e3585,0x106aa070,
   0x19a4c116,0x1e376c08,0x2748774c,0x34b0bcb5,0x391c0cb3,0x4ed8aa4a,0x5b9cca4f,0x682e6ff3,
   0x748f82ee,0x78a5636f,0x84c87814,0x8cc70208,0x90befffa,0xa4506ceb,0xbef9a3f7,0xc67178f2
};

SHA256_CTX *cpuSHA_CTX;
SHA256_CTX *gpuSHA_CTX;

int BLOCKS = 10;
int THREADS = 500;

extern "C"
__global__ void sha256_init(SHA256_CTX *ctx){
  int i = blockIdx.x * blockDim.x + threadIdx.x;
   ctx[i].datalen = 0; 
   ctx[i].bitlen[0] = 0; 
   ctx[i].bitlen[1] = 0; 
   ctx[i].state[0] = 0x6a09e667;
   ctx[i].state[1] = 0xbb67ae85;
   ctx[i].state[2] = 0x3c6ef372;
   ctx[i].state[3] = 0xa54ff53a;
   ctx[i].state[4] = 0x510e527f;
   ctx[i].state[5] = 0x9b05688c;
   ctx[i].state[6] = 0x1f83d9ab;
   ctx[i].state[7] = 0x5be0cd19;
}

extern "C"
__device__ void sha256_transform(SHA256_CTX *ctx, uchar data[])
{  
   int q = blockIdx.x * blockDim.x + threadIdx.x; 
   uint a,b,c,d,e,f,g,h,i,j,t1,t2,m[64];
      
   for (i=0,j=0; i < 16; ++i, j += 4)
      m[i] = (data[j] << 24) | (data[j+1] << 16) | (data[j+2] << 8) | (data[j+3]);
   for ( ; i < 64; ++i)
      m[i] = SIG1(m[i-2]) + m[i-7] + SIG0(m[i-15]) + m[i-16];

   a = ctx[q].state[0];
   b = ctx[q].state[1];
   c = ctx[q].state[2];
   d = ctx[q].state[3];
   e = ctx[q].state[4];
   f = ctx[q].state[5];
   g = ctx[q].state[6];
   h = ctx[q].state[7];
   
   for (i = 0; i < 64; ++i) {
      t1 = h + EP1(e) + CH(e,f,g) + k[i] + m[i];
      t2 = EP0(a) + MAJ(a,b,c);
      h = g;
      g = f;
      f = e;
      e = d + t1;
      d = c;
      c = b;
      b = a;
      a = t1 + t2;
   }
   
   ctx[q].state[0] += a;
   ctx[q].state[1] += b;
   ctx[q].state[2] += c;
   ctx[q].state[3] += d;
   ctx[q].state[4] += e;
   ctx[q].state[5] += f;
   ctx[q].state[6] += g;
   ctx[q].state[7] += h;
} 

extern "C"
__global__ void sha256_update(SHA256_CTX *ctx, uchar *data, uint len)
{  
   int q = blockIdx.x * blockDim.x + threadIdx.x; 
   uint i;
    
   for (i=0; i < len; ++i) { 
      ctx[q].data[ctx[q].datalen] = data[i]; 
      ctx[q].datalen++; 
      if (ctx[q].datalen == 64) { 
         sha256_transform(ctx,ctx[q].data);
         DBL_INT_ADD(ctx[q].bitlen[0],ctx[q].bitlen[1],512); 
         ctx[q].datalen = 0; 
      }  
   }  
}  


__device__ void print_hex_memory(void *mem) {
  int i;
  unsigned char *p = (unsigned char *)mem;
  for (i=0;i<128;i++) {
    printf("0x%02x ", p[i]);
    if (i%16==0)
      printf("\n");
  }
  printf("\n");
}

extern "C"
__global__ void sha256_final(SHA256_CTX *ctx, uchar *gpuResult)
{  
   int q = blockIdx.x * blockDim.x + threadIdx.x;

   uint i; 
   
   i = ctx[q].datalen; 
   
   // Pad whatever data is left in the buffer. 
   if (ctx[q].datalen < 56) { 
      ctx[q].data[i++] = 0x80; 
      while (i < 56) 
         ctx[q].data[i++] = 0x00; 
   }  
   else { 
      ctx[q].data[i++] = 0x80; 
      while (i < 64) 
         ctx[q].data[i++] = 0x00; 
      sha256_transform(ctx,ctx[q].data);
      memset(ctx[q].data,0,56); 
   } 
   
   // Append to the padding the total message's length in bits and transform. 
   DBL_INT_ADD(ctx[q].bitlen[0],ctx[q].bitlen[1],ctx[q].datalen * 8);
   ctx[q].data[63] = ctx[q].bitlen[0]; 
   ctx[q].data[62] = ctx[q].bitlen[0] >> 8; 
   ctx[q].data[61] = ctx[q].bitlen[0] >> 16; 
   ctx[q].data[60] = ctx[q].bitlen[0] >> 24; 
   ctx[q].data[59] = ctx[q].bitlen[1]; 
   ctx[q].data[58] = ctx[q].bitlen[1] >> 8; 
   ctx[q].data[57] = ctx[q].bitlen[1] >> 16;  
   ctx[q].data[56] = ctx[q].bitlen[1] >> 24; 
   sha256_transform(ctx,ctx[q].data);

   
   // Since this implementation uses little endian byte ordering and SHA uses big endian,
   // reverse all the bytes when copying the final state to the output hash. 
   for (i=0; i < 4; ++i) { 
      gpuResult[i]    = (ctx[q].state[0] >> (24-i*8)) & 0x000000ff; 
      gpuResult[i+4]  = (ctx[q].state[1] >> (24-i*8)) & 0x000000ff; 
      gpuResult[i+8]  = (ctx[q].state[2] >> (24-i*8)) & 0x000000ff;
      gpuResult[i+12] = (ctx[q].state[3] >> (24-i*8)) & 0x000000ff;
      gpuResult[i+16] = (ctx[q].state[4] >> (24-i*8)) & 0x000000ff;
      gpuResult[i+20] = (ctx[q].state[5] >> (24-i*8)) & 0x000000ff;
      gpuResult[i+24] = (ctx[q].state[6] >> (24-i*8)) & 0x000000ff;
      gpuResult[i+28] = (ctx[q].state[7] >> (24-i*8)) & 0x000000ff;
   }  

   /*
    printf("\n");
    for(int a=0; a<32; a++){
      printf("%02x", hash[a]);
    }
    printf("\n");
    */

}  

void host_struct_to_device(){
  cudaMalloc((SHA256_CTX**)&gpuSHA_CTX, THREADS * sizeof(SHA256_CTX));
}
void cudaAllocHash(){
  //cudaMalloc((uchar**)&gpuHash, THREADS * sizeof(plain));
}

	.file	"tmpxft_0037eb60_00000000-6_hashjcuda.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2033:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2033:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	sha256_transform
	.type	sha256_transform, @function
sha256_transform:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2027:
	.size	sha256_transform, .-sha256_transform
	.globl	_Z16print_hex_memoryPv
	.type	_Z16print_hex_memoryPv, @function
_Z16print_hex_memoryPv:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2028:
	.size	_Z16print_hex_memoryPv, .-_Z16print_hex_memoryPv
	.globl	_Z21host_struct_to_devicev
	.type	_Z21host_struct_to_devicev, @function
_Z21host_struct_to_devicev:
.LFB2029:
	.cfi_startproc
	endbr64
	movslq	THREADS(%rip), %rsi
	leaq	gpuSHA_CTX(%rip), %rdi
	imulq	$108, %rsi, %rsi
	jmp	cudaMalloc@PLT
	.cfi_endproc
.LFE2029:
	.size	_Z21host_struct_to_devicev, .-_Z21host_struct_to_devicev
	.globl	_Z13cudaAllocHashv
	.type	_Z13cudaAllocHashv, @function
_Z13cudaAllocHashv:
.LFB2030:
	.cfi_startproc
	endbr64
	ret
	.cfi_endproc
.LFE2030:
	.size	_Z13cudaAllocHashv, .-_Z13cudaAllocHashv
	.globl	_Z42__device_stub__Z11sha256_initP10SHA256_CTXP10SHA256_CTX
	.type	_Z42__device_stub__Z11sha256_initP10SHA256_CTXP10SHA256_CTX, @function
_Z42__device_stub__Z11sha256_initP10SHA256_CTXP10SHA256_CTX:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	sha256_init(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L8:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z42__device_stub__Z11sha256_initP10SHA256_CTXP10SHA256_CTX, .-_Z42__device_stub__Z11sha256_initP10SHA256_CTXP10SHA256_CTX
	.globl	sha256_init
	.type	sha256_init, @function
sha256_init:
.LFB2056:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z11sha256_initP10SHA256_CTXP10SHA256_CTX
	.cfi_endproc
.LFE2056:
	.size	sha256_init, .-sha256_init
	.globl	_Z47__device_stub__Z13sha256_updateP10SHA256_CTXPhjP10SHA256_CTXPhj
	.type	_Z47__device_stub__Z13sha256_updateP10SHA256_CTXPhjP10SHA256_CTXPhj, @function
_Z47__device_stub__Z13sha256_updateP10SHA256_CTXPhjP10SHA256_CTXPhj:
.LFB2057:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	sha256_update(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L14:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L16
	call	__stack_chk_fail@PLT
.L16:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2057:
	.size	_Z47__device_stub__Z13sha256_updateP10SHA256_CTXPhjP10SHA256_CTXPhj, .-_Z47__device_stub__Z13sha256_updateP10SHA256_CTXPhjP10SHA256_CTXPhj
	.globl	sha256_update
	.type	sha256_update, @function
sha256_update:
.LFB2058:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z13sha256_updateP10SHA256_CTXPhjP10SHA256_CTXPhj
	.cfi_endproc
.LFE2058:
	.size	sha256_update, .-sha256_update
	.globl	_Z45__device_stub__Z12sha256_finalP10SHA256_CTXPhP10SHA256_CTXPh
	.type	_Z45__device_stub__Z12sha256_finalP10SHA256_CTXPhP10SHA256_CTXPh, @function
_Z45__device_stub__Z12sha256_finalP10SHA256_CTXPhP10SHA256_CTXPh:
.LFB2059:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	sha256_final(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L19:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L21
	call	__stack_chk_fail@PLT
.L21:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2059:
	.size	_Z45__device_stub__Z12sha256_finalP10SHA256_CTXPhP10SHA256_CTXPh, .-_Z45__device_stub__Z12sha256_finalP10SHA256_CTXPhP10SHA256_CTXPh
	.globl	sha256_final
	.type	sha256_final, @function
sha256_final:
.LFB2060:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z12sha256_finalP10SHA256_CTXPhP10SHA256_CTXPh
	.cfi_endproc
.LFE2060:
	.size	sha256_final, .-sha256_final
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"sha256_final"
.LC1:
	.string	"sha256_update"
.LC2:
	.string	"sha256_init"
.LC3:
	.string	"k"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2062:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	sha256_final(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	sha256_update(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	sha256_init(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	movl	$256, %r9d
	leaq	_ZL1k(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2062:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	THREADS
	.data
	.align 4
	.type	THREADS, @object
	.size	THREADS, 4
THREADS:
	.long	500
	.globl	BLOCKS
	.align 4
	.type	BLOCKS, @object
	.size	BLOCKS, 4
BLOCKS:
	.long	10
	.globl	gpuSHA_CTX
	.bss
	.align 8
	.type	gpuSHA_CTX, @object
	.size	gpuSHA_CTX, 8
gpuSHA_CTX:
	.zero	8
	.globl	cpuSHA_CTX
	.align 8
	.type	cpuSHA_CTX, @object
	.size	cpuSHA_CTX, 8
cpuSHA_CTX:
	.zero	8
	.local	_ZL1k
	.comm	_ZL1k,256,32
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <time.h>   

//original c by brade conte, ported to CUDA by jody

#define uchar unsigned char // 8-bit byte
#define uint unsigned int // 32-bit word


#define DBL_INT_ADD(a,b,c) if (a > 0xffffffff - (c)) ++b; a += c;
#define ROTLEFT(a,b) (((a) << (b)) | ((a) >> (32-(b))))
#define ROTRIGHT(a,b) (((a) >> (b)) | ((a) << (32-(b))))

#define CH(x,y,z) (((x) & (y)) ^ (~(x) & (z)))
#define MAJ(x,y,z) (((x) & (y)) ^ ((x) & (z)) ^ ((y) & (z)))
#define EP0(x) (ROTRIGHT(x,2) ^ ROTRIGHT(x,13) ^ ROTRIGHT(x,22))
#define EP1(x) (ROTRIGHT(x,6) ^ ROTRIGHT(x,11) ^ ROTRIGHT(x,25))
#define SIG0(x) (ROTRIGHT(x,7) ^ ROTRIGHT(x,18) ^ ((x) >> 3))
#define SIG1(x) (ROTRIGHT(x,17) ^ ROTRIGHT(x,19) ^ ((x) >> 10))

typedef struct{
   uchar data[64];
   uint datalen;
   uint bitlen[2];
   uint state[8];
} SHA256_CTX;

__device__ uint k[64] = {
   0x428a2f98,0x71374491,0xb5c0fbcf,0xe9b5dba5,0x3956c25b,0x59f111f1,0x923f82a4,0xab1c5ed5,
   0xd807aa98,0x12835b01,0x243185be,0x550c7dc3,0x72be5d74,0x80deb1fe,0x9bdc06a7,0xc19bf174,
   0xe49b69c1,0xefbe4786,0x0fc19dc6,0x240ca1cc,0x2de92c6f,0x4a7484aa,0x5cb0a9dc,0x76f988da,
   0x983e5152,0xa831c66d,0xb00327c8,0xbf597fc7,0xc6e00bf3,0xd5a79147,0x06ca6351,0x14292967,
   0x27b70a85,0x2e1b2138,0x4d2c6dfc,0x53380d13,0x650a7354,0x766a0abb,0x81c2c92e,0x92722c85,
   0xa2bfe8a1,0xa81a664b,0xc24b8b70,0xc76c51a3,0xd192e819,0xd6990624,0xf40e3585,0x106aa070,
   0x19a4c116,0x1e376c08,0x2748774c,0x34b0bcb5,0x391c0cb3,0x4ed8aa4a,0x5b9cca4f,0x682e6ff3,
   0x748f82ee,0x78a5636f,0x84c87814,0x8cc70208,0x90befffa,0xa4506ceb,0xbef9a3f7,0xc67178f2
};

SHA256_CTX *cpuSHA_CTX;
SHA256_CTX *gpuSHA_CTX;

int BLOCKS = 10;
int THREADS = 500;

extern "C"
__global__ void sha256_init(SHA256_CTX *ctx){
  int i = blockIdx.x * blockDim.x + threadIdx.x;
   ctx[i].datalen = 0; 
   ctx[i].bitlen[0] = 0; 
   ctx[i].bitlen[1] = 0; 
   ctx[i].state[0] = 0x6a09e667;
   ctx[i].state[1] = 0xbb67ae85;
   ctx[i].state[2] = 0x3c6ef372;
   ctx[i].state[3] = 0xa54ff53a;
   ctx[i].state[4] = 0x510e527f;
   ctx[i].state[5] = 0x9b05688c;
   ctx[i].state[6] = 0x1f83d9ab;
   ctx[i].state[7] = 0x5be0cd19;
}

extern "C"
__device__ void sha256_transform(SHA256_CTX *ctx, uchar data[])
{  
   int q = blockIdx.x * blockDim.x + threadIdx.x; 
   uint a,b,c,d,e,f,g,h,i,j,t1,t2,m[64];
      
   for (i=0,j=0; i < 16; ++i, j += 4)
      m[i] = (data[j] << 24) | (data[j+1] << 16) | (data[j+2] << 8) | (data[j+3]);
   for ( ; i < 64; ++i)
      m[i] = SIG1(m[i-2]) + m[i-7] + SIG0(m[i-15]) + m[i-16];

   a = ctx[q].state[0];
   b = ctx[q].state[1];
   c = ctx[q].state[2];
   d = ctx[q].state[3];
   e = ctx[q].state[4];
   f = ctx[q].state[5];
   g = ctx[q].state[6];
   h = ctx[q].state[7];
   
   for (i = 0; i < 64; ++i) {
      t1 = h + EP1(e) + CH(e,f,g) + k[i] + m[i];
      t2 = EP0(a) + MAJ(a,b,c);
      h = g;
      g = f;
      f = e;
      e = d + t1;
      d = c;
      c = b;
      b = a;
      a = t1 + t2;
   }
   
   ctx[q].state[0] += a;
   ctx[q].state[1] += b;
   ctx[q].state[2] += c;
   ctx[q].state[3] += d;
   ctx[q].state[4] += e;
   ctx[q].state[5] += f;
   ctx[q].state[6] += g;
   ctx[q].state[7] += h;
} 

extern "C"
__global__ void sha256_update(SHA256_CTX *ctx, uchar *data, uint len)
{  
   int q = blockIdx.x * blockDim.x + threadIdx.x; 
   uint i;
    
   for (i=0; i < len; ++i) { 
      ctx[q].data[ctx[q].datalen] = data[i]; 
      ctx[q].datalen++; 
      if (ctx[q].datalen == 64) { 
         sha256_transform(ctx,ctx[q].data);
         DBL_INT_ADD(ctx[q].bitlen[0],ctx[q].bitlen[1],512); 
         ctx[q].datalen = 0; 
      }  
   }  
}  


__device__ void print_hex_memory(void *mem) {
  int i;
  unsigned char *p = (unsigned char *)mem;
  for (i=0;i<128;i++) {
    printf("0x%02x ", p[i]);
    if (i%16==0)
      printf("\n");
  }
  printf("\n");
}

extern "C"
__global__ void sha256_final(SHA256_CTX *ctx, uchar *gpuResult)
{  
   int q = blockIdx.x * blockDim.x + threadIdx.x;

   uint i; 
   
   i = ctx[q].datalen; 
   
   // Pad whatever data is left in the buffer. 
   if (ctx[q].datalen < 56) { 
      ctx[q].data[i++] = 0x80; 
      while (i < 56) 
         ctx[q].data[i++] = 0x00; 
   }  
   else { 
      ctx[q].data[i++] = 0x80; 
      while (i < 64) 
         ctx[q].data[i++] = 0x00; 
      sha256_transform(ctx,ctx[q].data);
      memset(ctx[q].data,0,56); 
   } 
   
   // Append to the padding the total message's length in bits and transform. 
   DBL_INT_ADD(ctx[q].bitlen[0],ctx[q].bitlen[1],ctx[q].datalen * 8);
   ctx[q].data[63] = ctx[q].bitlen[0]; 
   ctx[q].data[62] = ctx[q].bitlen[0] >> 8; 
   ctx[q].data[61] = ctx[q].bitlen[0] >> 16; 
   ctx[q].data[60] = ctx[q].bitlen[0] >> 24; 
   ctx[q].data[59] = ctx[q].bitlen[1]; 
   ctx[q].data[58] = ctx[q].bitlen[1] >> 8; 
   ctx[q].data[57] = ctx[q].bitlen[1] >> 16;  
   ctx[q].data[56] = ctx[q].bitlen[1] >> 24; 
   sha256_transform(ctx,ctx[q].data);

   
   // Since this implementation uses little endian byte ordering and SHA uses big endian,
   // reverse all the bytes when copying the final state to the output hash. 
   for (i=0; i < 4; ++i) { 
      gpuResult[i]    = (ctx[q].state[0] >> (24-i*8)) & 0x000000ff; 
      gpuResult[i+4]  = (ctx[q].state[1] >> (24-i*8)) & 0x000000ff; 
      gpuResult[i+8]  = (ctx[q].state[2] >> (24-i*8)) & 0x000000ff;
      gpuResult[i+12] = (ctx[q].state[3] >> (24-i*8)) & 0x000000ff;
      gpuResult[i+16] = (ctx[q].state[4] >> (24-i*8)) & 0x000000ff;
      gpuResult[i+20] = (ctx[q].state[5] >> (24-i*8)) & 0x000000ff;
      gpuResult[i+24] = (ctx[q].state[6] >> (24-i*8)) & 0x000000ff;
      gpuResult[i+28] = (ctx[q].state[7] >> (24-i*8)) & 0x000000ff;
   }  

   /*
    printf("\n");
    for(int a=0; a<32; a++){
      printf("%02x", hash[a]);
    }
    printf("\n");
    */

}  

void host_struct_to_device(){
  hipMalloc((SHA256_CTX**)&gpuSHA_CTX, THREADS * sizeof(SHA256_CTX));
}
void cudaAllocHash(){
  //cudaMalloc((uchar**)&gpuHash, THREADS * sizeof(plain));
}

	.text
	.file	"hashjcuda.hip"
	.globl	__device_stub__sha256_init      # -- Begin function __device_stub__sha256_init
	.type	__device_stub__sha256_init,@function
__device_stub__sha256_init:             # @__device_stub__sha256_init
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$sha256_init, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	__device_stub__sha256_init, .Lfunc_end0-__device_stub__sha256_init
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__sha256_update    # -- Begin function __device_stub__sha256_update
	.type	__device_stub__sha256_update,@function
__device_stub__sha256_update:           # @__device_stub__sha256_update
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$sha256_update, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	__device_stub__sha256_update, .Lfunc_end1-__device_stub__sha256_update
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__sha256_final     # -- Begin function __device_stub__sha256_final
	.type	__device_stub__sha256_final,@function
__device_stub__sha256_final:            # @__device_stub__sha256_final
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$sha256_final, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	__device_stub__sha256_final, .Lfunc_end2-__device_stub__sha256_final
	.cfi_endproc
                                        # -- End function
	.globl	_Z21host_struct_to_devicev      # -- Begin function _Z21host_struct_to_devicev
	.type	_Z21host_struct_to_devicev,@function
_Z21host_struct_to_devicev:             # @_Z21host_struct_to_devicev
	.cfi_startproc
# %bb.0:
	movslq	THREADS(%rip), %rax
	imulq	$108, %rax, %rsi
	movl	$gpuSHA_CTX, %edi
	jmp	hipMalloc                       # TAILCALL
.Lfunc_end3:
	.size	_Z21host_struct_to_devicev, .Lfunc_end3-_Z21host_struct_to_devicev
	.cfi_endproc
                                        # -- End function
	.globl	_Z13cudaAllocHashv              # -- Begin function _Z13cudaAllocHashv
	.type	_Z13cudaAllocHashv,@function
_Z13cudaAllocHashv:                     # @_Z13cudaAllocHashv
	.cfi_startproc
# %bb.0:
	retq
.Lfunc_end4:
	.size	_Z13cudaAllocHashv, .Lfunc_end4-_Z13cudaAllocHashv
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$sha256_init, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$sha256_update, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$sha256_final, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$0, 8(%rsp)
	movl	$0, (%rsp)
	movl	$k, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movl	$256, %r9d                      # imm = 0x100
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	callq	__hipRegisterVar
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	k,@object                       # @k
	.local	k
	.comm	k,256,16
	.type	cpuSHA_CTX,@object              # @cpuSHA_CTX
	.bss
	.globl	cpuSHA_CTX
	.p2align	3, 0x0
cpuSHA_CTX:
	.quad	0
	.size	cpuSHA_CTX, 8

	.type	gpuSHA_CTX,@object              # @gpuSHA_CTX
	.globl	gpuSHA_CTX
	.p2align	3, 0x0
gpuSHA_CTX:
	.quad	0
	.size	gpuSHA_CTX, 8

	.type	BLOCKS,@object                  # @BLOCKS
	.data
	.globl	BLOCKS
	.p2align	2, 0x0
BLOCKS:
	.long	10                              # 0xa
	.size	BLOCKS, 4

	.type	THREADS,@object                 # @THREADS
	.globl	THREADS
	.p2align	2, 0x0
THREADS:
	.long	500                             # 0x1f4
	.size	THREADS, 4

	.type	sha256_init,@object             # @sha256_init
	.section	.rodata,"a",@progbits
	.globl	sha256_init
	.p2align	3, 0x0
sha256_init:
	.quad	__device_stub__sha256_init
	.size	sha256_init, 8

	.type	sha256_update,@object           # @sha256_update
	.globl	sha256_update
	.p2align	3, 0x0
sha256_update:
	.quad	__device_stub__sha256_update
	.size	sha256_update, 8

	.type	sha256_final,@object            # @sha256_final
	.globl	sha256_final
	.p2align	3, 0x0
sha256_final:
	.quad	__device_stub__sha256_final
	.size	sha256_final, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"sha256_init"
	.size	.L__unnamed_1, 12

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"sha256_update"
	.size	.L__unnamed_2, 14

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"sha256_final"
	.size	.L__unnamed_3, 13

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"k"
	.size	.L__unnamed_4, 2

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __device_stub__sha256_init
	.addrsig_sym __device_stub__sha256_update
	.addrsig_sym __device_stub__sha256_final
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym k
	.addrsig_sym gpuSHA_CTX
	.addrsig_sym sha256_init
	.addrsig_sym sha256_update
	.addrsig_sym sha256_final
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	sha256_init             ; -- Begin function sha256_init
	.globl	sha256_init
	.p2align	8
	.type	sha256_init,@function
sha256_init:                            ; @sha256_init
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x14
	s_load_b64 s[0:1], s[0:1], 0x0
	v_mov_b32_e32 v6, 0xa54ff53a
	v_mov_b32_e32 v7, 0x510e527f
	v_mov_b32_e32 v8, 0x9b05688c
	v_mov_b32_e32 v9, 0x1f83d9ab
	v_mov_b32_e32 v10, 0x5be0cd19
	v_mov_b32_e32 v3, 0x6a09e667
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v4, 0xbb67ae85
	v_dual_mov_b32 v5, 0x3c6ef372 :: v_dual_mov_b32 v2, v0
	s_delay_alu instid0(VALU_DEP_4)
	v_mad_i64_i32 v[11:12], null, 0x6c, v1, s[0:1]
	v_mov_b32_e32 v1, v0
	s_clause 0x2
	global_store_b128 v[11:12], v[0:3], off offset:64
	global_store_b128 v[11:12], v[4:7], off offset:80
	global_store_b96 v[11:12], v[8:10], off offset:96
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel sha256_init
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 264
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 13
		.amdhsa_next_free_sgpr 16
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	sha256_init, .Lfunc_end0-sha256_init
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 176
; NumSgprs: 16
; NumVgprs: 13
; ScratchSize: 0
; MemoryBound: 1
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 16
; NumVGPRsForWavesPerEU: 13
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2align	2                               ; -- Begin function sha256_transform
	.type	sha256_transform,@function
sha256_transform:                       ; @sha256_transform
; %bb.0:
	s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	s_load_b32 s0, s[8:9], 0x0
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_u32 s12, s0
	s_cselect_b32 s0, 12, 18
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v4, s0
	s_mov_b32 s0, 0
	global_load_u16 v4, v4, s[8:9]
.LBB1_1:                                ; =>This Inner Loop Header: Depth=1
	s_clause 0x3
	flat_load_u8 v5, v[2:3]
	flat_load_u8 v6, v[2:3] offset:2
	flat_load_u8 v7, v[2:3] offset:1
	flat_load_u8 v8, v[2:3] offset:3
	v_add_co_u32 v2, vcc_lo, v2, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_add_i32 s1, s0, s32
	s_add_i32 s0, s0, 4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s0, 64
	s_waitcnt vmcnt(3) lgkmcnt(3)
	v_lshlrev_b32_e32 v5, 24, v5
	s_waitcnt vmcnt(2) lgkmcnt(2)
	v_lshlrev_b32_e32 v6, 8, v6
	s_waitcnt vmcnt(1) lgkmcnt(1)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshl_or_b32 v5, v7, 16, v5
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_or3_b32 v5, v5, v6, v8
	scratch_store_b32 off, v5, s1
	s_cbranch_scc0 .LBB1_1
; %bb.2:                                ; %.preheader
	scratch_load_b32 v3, off, s32
	v_mov_b32_e32 v2, s32
	s_mov_b32 s0, 0
.LBB1_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_add_i32 s1, s1, s0
	s_add_i32 s0, s0, 4
	s_add_i32 s2, s1, 56
	s_add_i32 s3, s1, 4
	scratch_load_b32 v5, off, s2
	s_add_i32 s2, s1, 36
	s_clause 0x1
	scratch_load_b32 v6, off, s3
	scratch_load_b32 v7, off, s2
	s_add_i32 s1, s1, 64
	s_cmpk_lg_i32 s0, 0xc0
	s_waitcnt vmcnt(2)
	v_alignbit_b32 v8, v5, v5, 17
	v_alignbit_b32 v9, v5, v5, 19
	v_lshrrev_b32_e32 v5, 10, v5
	s_waitcnt vmcnt(1)
	v_alignbit_b32 v10, v6, v6, 7
	v_alignbit_b32 v11, v6, v6, 18
	v_lshrrev_b32_e32 v12, 3, v6
	v_xor_b32_e32 v8, v8, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor3_b32 v9, v10, v11, v12
	s_waitcnt vmcnt(0)
	v_xad_u32 v5, v8, v5, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v5, v5, v3, v9
	v_mov_b32_e32 v3, v6
	scratch_store_b32 off, v5, s1
	s_cbranch_scc1 .LBB1_3
; %bb.4:                                ; %._crit_edge
	v_dual_mov_b32 v10, 0 :: v_dual_and_b32 v5, 0xffff, v4
	v_and_b32_e32 v2, 0x3ff, v31
	s_mov_b32 s2, 0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, k@rel32@lo+4
	s_addc_u32 s1, s1, k@rel32@hi+12
	v_mad_u64_u32 v[3:4], null, s12, v5, v[2:3]
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_i64_i32 v[8:9], null, 0x6c, v3, v[0:1]
	s_clause 0x1
	flat_load_b128 v[4:7], v[8:9] offset:76
	flat_load_b128 v[0:3], v[8:9] offset:92
	v_add_co_u32 v8, vcc_lo, 0x4c, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v9, vcc_lo
	s_waitcnt vmcnt(1) lgkmcnt(1)
	v_mov_b32_e32 v21, v4
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_dual_mov_b32 v11, v5 :: v_dual_mov_b32 v16, v3
	v_mov_b32_e32 v18, v2
	v_dual_mov_b32 v22, v1 :: v_dual_mov_b32 v19, v6
	v_mov_b32_e32 v20, v0
	v_mov_b32_e32 v12, v7
.LBB1_5:                                ; =>This Inner Loop Header: Depth=1
	s_add_i32 s3, s2, s32
	global_load_b32 v23, v10, s[0:1]
	scratch_load_b32 v24, off, s3
	v_mov_b32_e32 v15, v20
	v_dual_mov_b32 v25, v12 :: v_dual_mov_b32 v14, v22
	v_dual_mov_b32 v12, v19 :: v_dual_mov_b32 v13, v18
	s_delay_alu instid0(VALU_DEP_3)
	v_alignbit_b32 v18, v15, v15, 6
	v_alignbit_b32 v19, v15, v15, 11
	v_alignbit_b32 v20, v15, v15, 25
	v_not_b32_e32 v22, v15
	v_mov_b32_e32 v17, v11
	v_mov_b32_e32 v11, v21
	v_and_b32_e32 v21, v14, v15
	v_xor_b32_e32 v18, v18, v19
	v_and_b32_e32 v22, v13, v22
	v_xor_b32_e32 v27, v17, v12
	s_add_i32 s2, s2, 4
	s_add_u32 s0, s0, 4
	v_xad_u32 v18, v18, v20, v21
	v_and_b32_e32 v21, v17, v12
	s_addc_u32 s1, s1, 0
	s_cmpk_lg_i32 s2, 0x100
	s_delay_alu instid0(VALU_DEP_2)
	v_add3_u32 v16, v18, v16, v22
	v_mov_b32_e32 v18, v14
	v_alignbit_b32 v26, v11, v11, 2
	v_alignbit_b32 v19, v11, v11, 13
	v_alignbit_b32 v20, v11, v11, 22
	v_and_b32_e32 v27, v11, v27
	v_mov_b32_e32 v22, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor3_b32 v26, v26, v19, v20
	v_xor_b32_e32 v21, v27, v21
	s_waitcnt vmcnt(0)
	v_add3_u32 v23, v16, v23, v24
	v_mov_b32_e32 v16, v13
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_mov_b32 v19, v17 :: v_dual_add_nc_u32 v20, v23, v25
	v_add3_u32 v21, v26, v21, v23
	s_cbranch_scc1 .LBB1_5
; %bb.6:
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v4, v21, v4
	v_add_nc_u32_e32 v5, v11, v5
	v_add_nc_u32_e32 v6, v17, v6
	v_add_nc_u32_e32 v7, v12, v7
	v_add_nc_u32_e32 v0, v20, v0
	v_add_nc_u32_e32 v1, v15, v1
	v_add_nc_u32_e32 v2, v14, v2
	v_add_nc_u32_e32 v3, v13, v3
	s_clause 0x1
	flat_store_b128 v[8:9], v[4:7]
	flat_store_b128 v[8:9], v[0:3] offset:16
	s_waitcnt lgkmcnt(0)
	s_setpc_b64 s[30:31]
.Lfunc_end1:
	.size	sha256_transform, .Lfunc_end1-sha256_transform
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Function info:
; codeLenInByte = 784
; NumSgprs: 35
; NumVgprs: 32
; ScratchSize: 272
; MemoryBound: 0
	.text
	.protected	sha256_update           ; -- Begin function sha256_update
	.globl	sha256_update
	.p2align	8
	.type	sha256_update,@function
sha256_update:                          ; @sha256_update
; %bb.0:
	s_load_b32 s6, s[0:1], 0x10
	s_mov_b32 s32, 0
	s_waitcnt lgkmcnt(0)
	s_cmp_eq_u32 s6, 0
	s_cbranch_scc1 .LBB2_7
; %bb.1:                                ; %.lr.ph
	s_mov_b64 s[4:5], s[0:1]
	s_load_b32 s0, s[0:1], 0x24
	s_load_b128 s[16:19], s[4:5], 0x0
	v_dual_mov_b32 v31, v0 :: v_dual_mov_b32 v30, 0
	s_mov_b32 s12, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s0, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[0:1], null, s12, s0, v[31:32]
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_i64_i32 v[28:29], null, 0x6c, v0, s[16:17]
	global_load_b32 v0, v[28:29], off offset:64
	v_add_co_u32 v32, vcc_lo, v28, 64
	v_add_co_ci_u32_e32 v33, vcc_lo, 0, v29, vcc_lo
	v_add_co_u32 v34, vcc_lo, 0x44, v28
	v_add_co_ci_u32_e32 v35, vcc_lo, 0, v29, vcc_lo
.LBB2_2:                                ; =>This Inner Loop Header: Depth=1
	global_load_u8 v2, v30, s[18:19]
	s_waitcnt vmcnt(1)
	v_add_co_u32 v0, vcc_lo, v28, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v29, vcc_lo
	s_mov_b32 s7, exec_lo
	s_waitcnt vmcnt(0)
	global_store_b8 v[0:1], v2, off
	global_load_b32 v0, v[32:33], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v0, 1, v0
	global_store_b32 v[32:33], v0, off
	v_cmpx_eq_u32_e32 64, v0
	s_cbranch_execz .LBB2_6
; %bb.3:                                ;   in Loop: Header=BB2_2 Depth=1
	v_dual_mov_b32 v0, s16 :: v_dual_mov_b32 v1, s17
	v_dual_mov_b32 v2, v28 :: v_dual_mov_b32 v3, v29
	s_add_u32 s8, s4, 24
	s_addc_u32 s9, s5, 0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, sha256_transform@rel32@lo+4
	s_addc_u32 s1, s1, sha256_transform@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_swappc_b64 s[30:31], s[0:1]
	global_load_b32 v0, v[34:35], off
	s_mov_b32 s0, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_lt_u32_e32 0xfffffdff, v0
	s_cbranch_execz .LBB2_5
; %bb.4:                                ;   in Loop: Header=BB2_2 Depth=1
	global_load_b32 v1, v[34:35], off offset:4
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v1, 1, v1
	global_store_b32 v[34:35], v1, off offset:4
.LBB2_5:                                ;   in Loop: Header=BB2_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_dual_mov_b32 v0, 0 :: v_dual_add_nc_u32 v1, 0x200, v0
	global_store_b64 v[32:33], v[0:1], off
.LBB2_6:                                ; %Flow
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_add_i32 s6, s6, -1
	s_add_u32 s18, s18, 1
	s_addc_u32 s19, s19, 0
	s_cmp_lg_u32 s6, 0
	s_cbranch_scc1 .LBB2_2
.LBB2_7:                                ; %._crit_edge
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel sha256_update
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 272
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 36
		.amdhsa_next_free_sgpr 33
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	sha256_update, .Lfunc_end2-sha256_update
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 360
; NumSgprs: 35
; NumVgprs: 36
; ScratchSize: 272
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 35
; NumVGPRsForWavesPerEU: 36
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	sha256_final            ; -- Begin function sha256_final
	.globl	sha256_final
	.p2align	8
	.type	sha256_final,@function
sha256_final:                           ; @sha256_final
; %bb.0:
	s_mov_b64 s[4:5], s[0:1]
	s_load_b32 s0, s[0:1], 0x1c
	s_load_b128 s[16:19], s[4:5], 0x0
	v_dual_mov_b32 v31, v0 :: v_dual_mov_b32 v0, 0x80
	s_mov_b32 s12, s15
	v_mov_b32_e32 v1, 0
	s_mov_b32 s32, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s0, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[32:33], null, s12, s0, v[31:32]
	v_mad_i64_i32 v[28:29], null, 0x6c, v32, s[16:17]
	global_load_b32 v4, v[28:29], off offset:64
	v_add_co_u32 v33, vcc_lo, v28, 64
	v_add_co_ci_u32_e32 v34, vcc_lo, 0, v29, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, s0, v28, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v3, s0, 0, v29, s0
	s_mov_b32 s0, exec_lo
	global_store_b8 v[2:3], v0, off
	v_cmpx_lt_u32_e32 55, v4
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB3_6
; %bb.1:
	v_add_nc_u32_e32 v0, 1, v4
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e32 64, v0
	s_cbranch_execz .LBB3_4
; %bb.2:                                ; %.lr.ph.preheader
	v_mov_b32_e32 v1, 0
	s_mov_b32 s2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_i64_i32 v[2:3], null, 0x6c, v32, v[0:1]
	v_add_co_u32 v2, vcc_lo, s16, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s17, v3, vcc_lo
.LBB3_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v4, 1, v4
	global_store_b8 v[2:3], v1, off
	v_add_co_u32 v2, s0, v2, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e64 v3, s0, 0, v3, s0
	v_cmp_lt_u32_e32 vcc_lo, 62, v4
	s_or_b32 s2, vcc_lo, s2
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB3_3
.LBB3_4:                                ; %Flow170
	s_or_b32 exec_lo, exec_lo, s1
	v_dual_mov_b32 v0, s16 :: v_dual_mov_b32 v1, s17
	v_dual_mov_b32 v2, v28 :: v_dual_mov_b32 v3, v29
	s_add_u32 s8, s4, 16
	s_addc_u32 s9, s5, 0
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, sha256_transform@rel32@lo+4
	s_addc_u32 s1, s1, sha256_transform@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_swappc_b64 s[30:31], s[0:1]
	v_mov_b32_e32 v0, 0
	s_mov_b64 s[0:1], 0
                                        ; implicit-def: $vgpr4
.LBB3_5:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	v_add_co_u32 v2, vcc_lo, v28, s0
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v29, vcc_lo
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
                                        ; implicit-def: $vgpr0_vgpr1
	s_cmp_lg_u64 s[0:1], 56
	global_store_b32 v[2:3], v0, off
	s_cbranch_scc1 .LBB3_5
.LBB3_6:                                ; %Flow173
	s_and_not1_saveexec_b32 s1, s6
	s_cbranch_execz .LBB3_11
; %bb.7:
	s_mov_b32 s2, exec_lo
	v_cmpx_ne_u32_e32 55, v4
	s_cbranch_execz .LBB3_10
; %bb.8:                                ; %.lr.ph118.preheader
	v_add_co_u32 v0, vcc_lo, v28, 1
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v29, vcc_lo
	v_mov_b32_e32 v3, 0
	s_mov_b32 s3, 0
.LBB3_9:                                ; %.lr.ph118
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_add_co_u32 v5, vcc_lo, v0, v4
	v_add_co_u32 v4, s0, v4, 1
	v_add_co_ci_u32_e32 v6, vcc_lo, v2, v1, vcc_lo
	v_add_co_ci_u32_e64 v1, vcc_lo, 0, v1, s0
	v_add_nc_u32_e32 v7, -1, v4
	global_store_b8 v[5:6], v3, off
	v_cmp_lt_u32_e32 vcc_lo, 53, v7
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB3_9
.LBB3_10:                               ; %Flow172
	s_or_b32 exec_lo, exec_lo, s2
.LBB3_11:                               ; %_ZL6memsetPvim.exit
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s1
	global_load_b96 v[0:2], v[33:34], off
	v_mad_i64_i32 v[33:34], null, 0x6c, v32, s[16:17]
	s_mov_b32 s0, exec_lo
	v_add_co_u32 v3, vcc_lo, 0x44, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v34, vcc_lo
	s_waitcnt vmcnt(0)
	v_lshlrev_b32_e32 v0, 3, v0
	v_not_b32_e32 v5, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_u32_e64 v1, v5
	s_cbranch_execz .LBB3_13
; %bb.12:
	v_add_nc_u32_e32 v2, 1, v2
	global_store_b32 v[3:4], v2, off offset:4
.LBB3_13:                               ; %_ZL6memsetPvim.exit._crit_edge
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v5, v1, v0
	s_add_u32 s8, s4, 16
	s_addc_u32 s9, s5, 0
	s_mov_b32 s6, 24
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, sha256_transform@rel32@lo+4
	s_addc_u32 s1, s1, sha256_transform@rel32@hi+12
	v_lshrrev_b32_e32 v0, 16, v5
	v_lshrrev_b32_e32 v1, 8, v5
	v_lshrrev_b32_e32 v6, 24, v5
	v_lshlrev_b16 v7, 8, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b16 v0, 8, v0
	v_and_b32_e32 v1, 0xff, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v0, v6, v0
	v_and_b32_e32 v6, 0xffff, v0
	v_perm_b32 v0, v2, v2, 0x4050607
	v_mov_b32_e32 v2, v28
	v_or_b32_e32 v1, v1, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v1, 16, v1
	v_or_b32_e32 v1, v6, v1
	s_clause 0x1
	global_store_b32 v[3:4], v5, off
	global_store_b64 v[28:29], v[0:1], off offset:56
	v_dual_mov_b32 v1, s17 :: v_dual_mov_b32 v0, s16
	v_mov_b32_e32 v3, v29
	s_swappc_b64 s[30:31], s[0:1]
	v_add_co_u32 v0, vcc_lo, 0x4c, v33
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v34, vcc_lo
	v_mov_b32_e32 v2, 0
	s_mov_b64 s[0:1], 0
.LBB3_14:                               ; =>This Inner Loop Header: Depth=1
	global_load_b32 v3, v[0:1], off
	s_add_u32 s2, s18, s0
	s_addc_u32 s3, s19, s1
	s_add_u32 s0, s0, 1
	s_addc_u32 s1, s1, 0
	s_waitcnt vmcnt(0)
	v_lshrrev_b32_e32 v3, s6, v3
	global_store_b8 v2, v3, s[2:3]
	global_load_b32 v3, v[0:1], off offset:4
	s_waitcnt vmcnt(0)
	v_lshrrev_b32_e32 v3, s6, v3
	global_store_b8 v2, v3, s[2:3] offset:4
	global_load_b32 v3, v[0:1], off offset:8
	s_waitcnt vmcnt(0)
	v_lshrrev_b32_e32 v3, s6, v3
	global_store_b8 v2, v3, s[2:3] offset:8
	global_load_b32 v3, v[0:1], off offset:12
	s_waitcnt vmcnt(0)
	v_lshrrev_b32_e32 v3, s6, v3
	global_store_b8 v2, v3, s[2:3] offset:12
	global_load_b32 v3, v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_lshrrev_b32_e32 v3, s6, v3
	global_store_b8 v2, v3, s[2:3] offset:16
	global_load_b32 v3, v[0:1], off offset:20
	s_waitcnt vmcnt(0)
	v_lshrrev_b32_e32 v3, s6, v3
	global_store_b8 v2, v3, s[2:3] offset:20
	global_load_b32 v3, v[0:1], off offset:24
	s_waitcnt vmcnt(0)
	v_lshrrev_b32_e32 v3, s6, v3
	global_store_b8 v2, v3, s[2:3] offset:24
	global_load_b32 v3, v[0:1], off offset:28
	s_waitcnt vmcnt(0)
	v_lshrrev_b32_e32 v3, s6, v3
	s_add_i32 s6, s6, -8
	s_cmp_lg_u32 s0, 4
	global_store_b8 v2, v3, s[2:3] offset:28
	s_cbranch_scc1 .LBB3_14
; %bb.15:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel sha256_final
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 272
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 35
		.amdhsa_next_free_sgpr 33
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	sha256_final, .Lfunc_end3-sha256_final
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 972
; NumSgprs: 35
; NumVgprs: 35
; ScratchSize: 272
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 35
; NumVGPRsForWavesPerEU: 35
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.protected	k                       ; @k
	.type	k,@object
	.data
	.globl	k
	.p2align	4, 0x0
k:
	.long	1116352408                      ; 0x428a2f98
	.long	1899447441                      ; 0x71374491
	.long	3049323471                      ; 0xb5c0fbcf
	.long	3921009573                      ; 0xe9b5dba5
	.long	961987163                       ; 0x3956c25b
	.long	1508970993                      ; 0x59f111f1
	.long	2453635748                      ; 0x923f82a4
	.long	2870763221                      ; 0xab1c5ed5
	.long	3624381080                      ; 0xd807aa98
	.long	310598401                       ; 0x12835b01
	.long	607225278                       ; 0x243185be
	.long	1426881987                      ; 0x550c7dc3
	.long	1925078388                      ; 0x72be5d74
	.long	2162078206                      ; 0x80deb1fe
	.long	2614888103                      ; 0x9bdc06a7
	.long	3248222580                      ; 0xc19bf174
	.long	3835390401                      ; 0xe49b69c1
	.long	4022224774                      ; 0xefbe4786
	.long	264347078                       ; 0xfc19dc6
	.long	604807628                       ; 0x240ca1cc
	.long	770255983                       ; 0x2de92c6f
	.long	1249150122                      ; 0x4a7484aa
	.long	1555081692                      ; 0x5cb0a9dc
	.long	1996064986                      ; 0x76f988da
	.long	2554220882                      ; 0x983e5152
	.long	2821834349                      ; 0xa831c66d
	.long	2952996808                      ; 0xb00327c8
	.long	3210313671                      ; 0xbf597fc7
	.long	3336571891                      ; 0xc6e00bf3
	.long	3584528711                      ; 0xd5a79147
	.long	113926993                       ; 0x6ca6351
	.long	338241895                       ; 0x14292967
	.long	666307205                       ; 0x27b70a85
	.long	773529912                       ; 0x2e1b2138
	.long	1294757372                      ; 0x4d2c6dfc
	.long	1396182291                      ; 0x53380d13
	.long	1695183700                      ; 0x650a7354
	.long	1986661051                      ; 0x766a0abb
	.long	2177026350                      ; 0x81c2c92e
	.long	2456956037                      ; 0x92722c85
	.long	2730485921                      ; 0xa2bfe8a1
	.long	2820302411                      ; 0xa81a664b
	.long	3259730800                      ; 0xc24b8b70
	.long	3345764771                      ; 0xc76c51a3
	.long	3516065817                      ; 0xd192e819
	.long	3600352804                      ; 0xd6990624
	.long	4094571909                      ; 0xf40e3585
	.long	275423344                       ; 0x106aa070
	.long	430227734                       ; 0x19a4c116
	.long	506948616                       ; 0x1e376c08
	.long	659060556                       ; 0x2748774c
	.long	883997877                       ; 0x34b0bcb5
	.long	958139571                       ; 0x391c0cb3
	.long	1322822218                      ; 0x4ed8aa4a
	.long	1537002063                      ; 0x5b9cca4f
	.long	1747873779                      ; 0x682e6ff3
	.long	1955562222                      ; 0x748f82ee
	.long	2024104815                      ; 0x78a5636f
	.long	2227730452                      ; 0x84c87814
	.long	2361852424                      ; 0x8cc70208
	.long	2428436474                      ; 0x90befffa
	.long	2756734187                      ; 0xa4506ceb
	.long	3204031479                      ; 0xbef9a3f7
	.long	3329325298                      ; 0xc67178f2
	.size	k, 256

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym k
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         12
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         20
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         22
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         24
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         26
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         28
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         30
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         48
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         72
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 264
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           sha256_init
    .private_segment_fixed_size: 0
    .sgpr_count:     16
    .sgpr_spill_count: 0
    .symbol:         sha256_init.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     13
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           sha256_update
    .private_segment_fixed_size: 272
    .sgpr_count:     35
    .sgpr_spill_count: 0
    .symbol:         sha256_update.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     36
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           sha256_final
    .private_segment_fixed_size: 272
    .sgpr_count:     35
    .sgpr_spill_count: 0
    .symbol:         sha256_final.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     35
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
