
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <cuda.h>
#include <device_functions.h>
#include <cuda_runtime_api.h>
#include <stdio.h>      /* printf, scanf, puts, NULL */
#include <stdlib.h>     /* srand, rand */
#include <time.h>       
#include <device_functions.h>

#define SIZE 32
#define TSIZE 1024

using namespace std;


__global__ void addKernel(int *A, int *B)
{
	__shared__ int auxMatrix[SIZE][SIZE];
	int col = threadIdx.x + blockIdx.x * blockDim.x;
	int row = threadIdx.y + blockIdx.y * blockDim.y;
	int pos = col + row * SIZE;
	//if 0,0
	if (row == 0 && col == 0)
		auxMatrix[row][col] = A[pos] + A[pos + 1] + A[pos + SIZE];
	//if 0,31
	else if (row == 0 && col == 31)
		auxMatrix[row][col] = A[pos] + A[pos - 1] + A[pos + SIZE];
	//if 31,0
	else if (row == 31 && col == 0)
		auxMatrix[row][col] = A[pos] + A[pos + 1] + A[pos - SIZE];
	//if 31,31
	else if (row == 31 && col == 31)
		auxMatrix[row][col] = A[pos] + A[pos - 1] + A[pos - SIZE];
	//if row 0 only
	else if (row == 0)
		auxMatrix[row][col] = A[pos] + A[pos + 1] + A[pos - 1] + A[pos + SIZE];
	//if row 31 only
	else if (row == 31)
		auxMatrix[row][col] = A[pos] + A[pos + 1] + A[pos - 1] + A[pos - SIZE];
	//if col 0 only
	else if (col == 0)
		auxMatrix[row][col] = A[pos] + A[pos + 1] + A[pos - SIZE] + A[pos + SIZE];
	//if col 1 only
	else if (col == 31)
		auxMatrix[row][col] = A[pos] + A[pos - 1] + A[pos - SIZE] + A[pos + SIZE];
	//if central position in the matrix
	else if (row != 0 && col != 0 && row != 31 && col != 31)
		auxMatrix[row][col] = A[pos] + A[pos + 1] + A[pos - 1] + A[pos + SIZE] + A[pos - SIZE];

	__syncthreads();
	//printf("\nA[%d]=%d", pos, A[pos]);
	//printf("\nA[%d]=%d\nauxMatrix[%d][%d]=%d", pos, A[pos], row, col, auxMatrix[row][col]);
	//printf("\nCol: %d , threadIdx.x: %d, blockIdx.x: %d, blockDim.x: %d", col, threadIdx.x, blockIdx.x, blockDim.x);
	//printf("\nRow: %d , threadIdx.y: %d, blockIdx.y: %d, blockDim.y: %d", row, threadIdx.y, blockIdx.y, blockDim.y);
	B[pos] = auxMatrix[row][col];
	//printf("\nB[%d]=%d", pos, B[pos]);
}

int main()
{
	int A[SIZE][SIZE], B[SIZE][SIZE];
	srand(time(NULL));
	for (int i = 0; i < SIZE; i++)
	{
		for (int k = 0; k < SIZE; k++)
		{
			A[i][k] = rand() % 99;
		}
	}
    // Add vectors in parallel.
	int *dev_A, *dev_B;
	size_t sharedMem = 64;
	dim3 dimGrid(2, 2);
	dim3 dimBlock(16, 16);
	cudaMalloc((void**)&dev_A, SIZE * SIZE *sizeof(int));
	cudaMalloc((void**)&dev_B, SIZE * SIZE *sizeof(int));
	cudaMemcpy(dev_A, A, SIZE *SIZE *sizeof(int), cudaMemcpyHostToDevice);
	addKernel <<<dimGrid, dimBlock, sharedMem>>> (dev_A, dev_B);
	cudaDeviceSynchronize();
	cudaMemcpy(B, dev_B, 32 * 32 * sizeof(int), cudaMemcpyDeviceToHost);
	printf("\n\n--A--");
	for (int i = 0; i < SIZE; i++)
	{
		printf("\n[");
		for (int j = 0; j < SIZE; j++)
		{
			if (j != 31)
				if (A[i][j] / 10 == 0)
					printf("00%d-", A[i][j]);
				else if (A[i][j] / 100 == 0)
					printf("0%d-", A[i][j]);
				else
					printf("%d-", A[i][j]);
			else
				if (A[i][j] / 10 == 0)
					printf("00%d", A[i][j]);
				else if (A[i][j] / 100 == 0)
					printf("0%d", A[i][j]);
				else
					printf("%d", A[i][j]);
		}
		printf("]");
	}
	printf("\n\n--B--");
	for (int i = 0; i < SIZE; i++)
	{
		printf("\n[");
		for (int j = 0; j < SIZE; j++)
		{
			if(j!=31)
				if (B[i][j] / 10 == 0)
					printf("00%d-", B[i][j]);
				else if(B[i][j]/100 == 0)
					printf("0%d-", B[i][j]);
				else
					printf("%d-", B[i][j]);
			else
				if (B[i][j] / 10 == 0)
					printf("00%d", B[i][j]);
				else if (B[i][j] / 100 == 0)
					printf("0%d", B[i][j]);
				else
					printf("%d", B[i][j]);
		}
		printf("]");
	}
	// cudaMemcpy(c, dev_c, size * sizeof(int), cudaMemcpyDeviceToHost);
	cudaFree(dev_A);
	cudaFree(dev_B);

    return 0;
}

	.file	"tmpxft_0036506d_00000000-6_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z30__device_stub__Z9addKernelPiS_PiS_
	.type	_Z30__device_stub__Z9addKernelPiS_PiS_, @function
_Z30__device_stub__Z9addKernelPiS_PiS_:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z9addKernelPiS_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L2:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z30__device_stub__Z9addKernelPiS_PiS_, .-_Z30__device_stub__Z9addKernelPiS_PiS_
	.globl	_Z9addKernelPiS_
	.type	_Z9addKernelPiS_, @function
_Z9addKernelPiS_:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z9addKernelPiS_PiS_
	.cfi_endproc
.LFE2053:
	.size	_Z9addKernelPiS_, .-_Z9addKernelPiS_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"\n\n--A--"
.LC1:
	.string	"\n["
.LC2:
	.string	"00%d-"
.LC3:
	.string	"0%d-"
.LC4:
	.string	"%d-"
.LC5:
	.string	"00%d"
.LC6:
	.string	"0%d"
.LC7:
	.string	"%d"
.LC8:
	.string	"]"
.LC9:
	.string	"\n\n--B--"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$4096, %rsp
	.cfi_def_cfa_offset 4152
	orq	$0, (%rsp)
	subq	$4096, %rsp
	.cfi_def_cfa_offset 8248
	orq	$0, (%rsp)
	subq	$56, %rsp
	.cfi_def_cfa_offset 8304
	xorl	%edi, %edi
	movl	$99, %r14d
	movq	%fs:40, %rax
	movq	%rax, 8232(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rbx
	leaq	4136(%rsp), %r13
	call	time@PLT
	movq	%rbx, %r12
	movl	%eax, %edi
	call	srand@PLT
.L9:
	xorl	%ebp, %ebp
.L10:
	call	rand@PLT
	cltd
	idivl	%r14d
	movl	%edx, (%r12,%rbp,4)
	incq	%rbp
	cmpq	$32, %rbp
	jne	.L10
	subq	$-128, %r12
	cmpq	%r13, %r12
	jne	.L9
	movq	%rsp, %rdi
	movl	$4096, %esi
	movabsq	$8589934594, %rax
	movl	$1, 24(%rsp)
	movq	%rax, 16(%rsp)
	movabsq	$68719476752, %rax
	movq	%rax, 28(%rsp)
	movl	$1, 36(%rsp)
	call	cudaMalloc@PLT
	leaq	8(%rsp), %rdi
	movl	$4096, %esi
	call	cudaMalloc@PLT
	movq	(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$4096, %edx
	call	cudaMemcpy@PLT
	movl	36(%rsp), %ecx
	movl	24(%rsp), %esi
	xorl	%r9d, %r9d
	movq	28(%rsp), %rdx
	movq	16(%rsp), %rdi
	movl	$64, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdi
	call	_Z30__device_stub__Z9addKernelPiS_PiS_
.L12:
	call	cudaDeviceSynchronize@PLT
	movq	8(%rsp), %rsi
	movl	$2, %ecx
	movq	%r13, %rdi
	movl	$4096, %edx
	leaq	.LC1(%rip), %r12
	call	cudaMemcpy@PLT
	leaq	.LC0(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L20:
	movq	%r12, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	.LC4(%rip), %r14
	xorl	%eax, %eax
.L22:
	cmpq	$31, %rax
	je	.L13
	movl	(%rbx,%rax,4), %edx
	leaq	.LC2(%rip), %rsi
	leaq	1(%rax), %rbp
	leal	9(%rdx), %ecx
	cmpl	$18, %ecx
	jbe	.L38
	leal	99(%rdx), %eax
	leaq	.LC3(%rip), %rsi
	cmpl	$198, %eax
	jbe	.L38
	movq	%r14, %rsi
.L38:
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	%rbp, %rax
	jmp	.L22
.L13:
	movl	124(%rbx), %edx
	leaq	.LC5(%rip), %rsi
	leal	9(%rdx), %eax
	cmpl	$18, %eax
	jbe	.L39
	leal	99(%rdx), %eax
	leaq	.LC6(%rip), %rsi
	cmpl	$198, %eax
	jbe	.L39
	leaq	.LC7(%rip), %rsi
.L39:
	movl	$2, %edi
	xorl	%eax, %eax
	leaq	.LC8(%rip), %rbp
	subq	$-128, %rbx
	call	__printf_chk@PLT
	movq	%rbp, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	cmpq	%r13, %rbx
	jne	.L20
	leaq	.LC9(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	leaq	8232(%rsp), %r13
	leaq	.LC4(%rip), %r14
.L30:
	movq	%r12, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	xorl	%eax, %eax
.L32:
	cmpq	$31, %rax
	je	.L23
	movl	(%rbx,%rax,4), %edx
	leaq	.LC2(%rip), %rsi
	leaq	1(%rax), %r15
	leal	9(%rdx), %ecx
	cmpl	$18, %ecx
	jbe	.L40
	leal	99(%rdx), %eax
	leaq	.LC3(%rip), %rsi
	cmpl	$198, %eax
	jbe	.L40
	movq	%r14, %rsi
.L40:
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	%r15, %rax
	jmp	.L32
.L23:
	movl	124(%rbx), %edx
	leaq	.LC5(%rip), %rsi
	leal	9(%rdx), %eax
	cmpl	$18, %eax
	jbe	.L41
	leal	99(%rdx), %eax
	leaq	.LC6(%rip), %rsi
	cmpl	$198, %eax
	jbe	.L41
	leaq	.LC7(%rip), %rsi
.L41:
	movl	$2, %edi
	xorl	%eax, %eax
	subq	$-128, %rbx
	call	__printf_chk@PLT
	movq	%rbp, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	cmpq	%rbx, %r13
	jne	.L30
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	8232(%rsp), %rax
	subq	%fs:40, %rax
	je	.L33
	call	__stack_chk_fail@PLT
.L33:
	addq	$8248, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC10:
	.string	"_Z9addKernelPiS_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z9addKernelPiS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include "hip/hip_runtime.h"


#include <hip/device_functions.h>
#include <hip/hip_runtime_api.h>
#include <stdio.h>      /* printf, scanf, puts, NULL */
#include <stdlib.h>     /* srand, rand */
#include <time.h>       
#include <hip/device_functions.h>

#define SIZE 32
#define TSIZE 1024

using namespace std;


__global__ void addKernel(int *A, int *B)
{
	__shared__ int auxMatrix[SIZE][SIZE];
	int col = threadIdx.x + blockIdx.x * blockDim.x;
	int row = threadIdx.y + blockIdx.y * blockDim.y;
	int pos = col + row * SIZE;
	//if 0,0
	if (row == 0 && col == 0)
		auxMatrix[row][col] = A[pos] + A[pos + 1] + A[pos + SIZE];
	//if 0,31
	else if (row == 0 && col == 31)
		auxMatrix[row][col] = A[pos] + A[pos - 1] + A[pos + SIZE];
	//if 31,0
	else if (row == 31 && col == 0)
		auxMatrix[row][col] = A[pos] + A[pos + 1] + A[pos - SIZE];
	//if 31,31
	else if (row == 31 && col == 31)
		auxMatrix[row][col] = A[pos] + A[pos - 1] + A[pos - SIZE];
	//if row 0 only
	else if (row == 0)
		auxMatrix[row][col] = A[pos] + A[pos + 1] + A[pos - 1] + A[pos + SIZE];
	//if row 31 only
	else if (row == 31)
		auxMatrix[row][col] = A[pos] + A[pos + 1] + A[pos - 1] + A[pos - SIZE];
	//if col 0 only
	else if (col == 0)
		auxMatrix[row][col] = A[pos] + A[pos + 1] + A[pos - SIZE] + A[pos + SIZE];
	//if col 1 only
	else if (col == 31)
		auxMatrix[row][col] = A[pos] + A[pos - 1] + A[pos - SIZE] + A[pos + SIZE];
	//if central position in the matrix
	else if (row != 0 && col != 0 && row != 31 && col != 31)
		auxMatrix[row][col] = A[pos] + A[pos + 1] + A[pos - 1] + A[pos + SIZE] + A[pos - SIZE];

	__syncthreads();
	//printf("\nA[%d]=%d", pos, A[pos]);
	//printf("\nA[%d]=%d\nauxMatrix[%d][%d]=%d", pos, A[pos], row, col, auxMatrix[row][col]);
	//printf("\nCol: %d , threadIdx.x: %d, blockIdx.x: %d, blockDim.x: %d", col, threadIdx.x, blockIdx.x, blockDim.x);
	//printf("\nRow: %d , threadIdx.y: %d, blockIdx.y: %d, blockDim.y: %d", row, threadIdx.y, blockIdx.y, blockDim.y);
	B[pos] = auxMatrix[row][col];
	//printf("\nB[%d]=%d", pos, B[pos]);
}

int main()
{
	int A[SIZE][SIZE], B[SIZE][SIZE];
	srand(time(NULL));
	for (int i = 0; i < SIZE; i++)
	{
		for (int k = 0; k < SIZE; k++)
		{
			A[i][k] = rand() % 99;
		}
	}
    // Add vectors in parallel.
	int *dev_A, *dev_B;
	size_t sharedMem = 64;
	dim3 dimGrid(2, 2);
	dim3 dimBlock(16, 16);
	hipMalloc((void**)&dev_A, SIZE * SIZE *sizeof(int));
	hipMalloc((void**)&dev_B, SIZE * SIZE *sizeof(int));
	hipMemcpy(dev_A, A, SIZE *SIZE *sizeof(int), hipMemcpyHostToDevice);
	addKernel <<<dimGrid, dimBlock, sharedMem>>> (dev_A, dev_B);
	hipDeviceSynchronize();
	hipMemcpy(B, dev_B, 32 * 32 * sizeof(int), hipMemcpyDeviceToHost);
	printf("\n\n--A--");
	for (int i = 0; i < SIZE; i++)
	{
		printf("\n[");
		for (int j = 0; j < SIZE; j++)
		{
			if (j != 31)
				if (A[i][j] / 10 == 0)
					printf("00%d-", A[i][j]);
				else if (A[i][j] / 100 == 0)
					printf("0%d-", A[i][j]);
				else
					printf("%d-", A[i][j]);
			else
				if (A[i][j] / 10 == 0)
					printf("00%d", A[i][j]);
				else if (A[i][j] / 100 == 0)
					printf("0%d", A[i][j]);
				else
					printf("%d", A[i][j]);
		}
		printf("]");
	}
	printf("\n\n--B--");
	for (int i = 0; i < SIZE; i++)
	{
		printf("\n[");
		for (int j = 0; j < SIZE; j++)
		{
			if(j!=31)
				if (B[i][j] / 10 == 0)
					printf("00%d-", B[i][j]);
				else if(B[i][j]/100 == 0)
					printf("0%d-", B[i][j]);
				else
					printf("%d-", B[i][j]);
			else
				if (B[i][j] / 10 == 0)
					printf("00%d", B[i][j]);
				else if (B[i][j] / 100 == 0)
					printf("0%d", B[i][j]);
				else
					printf("%d", B[i][j]);
		}
		printf("]");
	}
	// cudaMemcpy(c, dev_c, size * sizeof(int), cudaMemcpyDeviceToHost);
	hipFree(dev_A);
	hipFree(dev_B);

    return 0;
}

	.text
	.file	"kernel.hip"
	.globl	_Z24__device_stub__addKernelPiS_ # -- Begin function _Z24__device_stub__addKernelPiS_
	.type	_Z24__device_stub__addKernelPiS_,@function
_Z24__device_stub__addKernelPiS_:       # @_Z24__device_stub__addKernelPiS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9addKernelPiS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z24__device_stub__addKernelPiS_, .Lfunc_end0-_Z24__device_stub__addKernelPiS_
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$8216, %rsp                     # imm = 0x2018
	.cfi_def_cfa_offset 8272
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	xorl	%ebx, %ebx
	xorl	%edi, %edi
	callq	time
	movl	%eax, %edi
	callq	srand
	leaq	16(%rsp), %r14
.LBB1_1:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_2 Depth 2
	xorl	%r15d, %r15d
.LBB1_2:                                #   Parent Loop BB1_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
	cltq
	imulq	$-1518422781, %rax, %rcx        # imm = 0xA57EB503
	shrq	$32, %rcx
	addl	%eax, %ecx
	movl	%ecx, %edx
	shrl	$31, %edx
	sarl	$6, %ecx
	addl	%edx, %ecx
	imull	$99, %ecx, %ecx
	subl	%ecx, %eax
	movl	%eax, (%r14,%r15,4)
	incq	%r15
	cmpq	$32, %r15
	jne	.LBB1_2
# %bb.3:                                #   in Loop: Header=BB1_1 Depth=1
	incq	%rbx
	subq	$-128, %r14
	cmpq	$32, %rbx
	jne	.LBB1_1
# %bb.4:
	leaq	8(%rsp), %rbx
	movl	$4096, %esi                     # imm = 0x1000
	movq	%rbx, %rdi
	callq	hipMalloc
	movq	%rsp, %rdi
	movl	$4096, %esi                     # imm = 0x1000
	callq	hipMalloc
	movq	(%rbx), %rdi
	leaq	16(%rsp), %r14
	movl	$4096, %edx                     # imm = 0x1000
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$8589934594, %rdi               # imm = 0x200000002
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$64, %r8d
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_6
# %bb.5:
	movq	8(%rsp), %rdi
	movq	(%rsp), %rsi
	callq	_Z24__device_stub__addKernelPiS_
.LBB1_6:
	callq	hipDeviceSynchronize
	movq	(%rsp), %rsi
	leaq	4112(%rsp), %rbx
	movl	$4096, %edx                     # imm = 0x1000
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$.L.str, %edi
	xorl	%eax, %eax
	callq	printf
	movl	$.L.str.2, %r15d
	xorl	%ebp, %ebp
.LBB1_7:                                # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_8 Depth 2
	movl	$.L.str.1, %edi
	xorl	%eax, %eax
	callq	printf
	movq	%rbp, %rax
	shlq	$7, %rax
	leaq	(%rsp,%rax), %r12
	addq	$140, %r12
	xorl	%r13d, %r13d
.LBB1_8:                                #   Parent Loop BB1_7 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	(%r14,%r13,4), %esi
	leal	99(%rsi), %eax
	movl	$.L.str.3, %edi
	cmpl	$199, %eax
	jb	.LBB1_10
# %bb.9:                                #   in Loop: Header=BB1_8 Depth=2
	movl	$.L.str.4, %edi
.LBB1_10:                               #   in Loop: Header=BB1_8 Depth=2
	leal	9(%rsi), %eax
	cmpl	$19, %eax
	cmovbq	%r15, %rdi
                                        # kill: def $esi killed $esi killed $rsi
	xorl	%eax, %eax
	callq	printf
	incq	%r13
	cmpq	$31, %r13
	jne	.LBB1_8
# %bb.11:                               #   in Loop: Header=BB1_7 Depth=1
	movl	(%r12), %esi
	leal	99(%rsi), %eax
	cmpl	$199, %eax
	movl	$.L.str.7, %edi
	movl	$.L.str.6, %eax
	cmovbq	%rax, %rdi
	leal	9(%rsi), %eax
	cmpl	$19, %eax
	movl	$.L.str.5, %eax
	cmovbq	%rax, %rdi
                                        # kill: def $esi killed $esi killed $rsi
	xorl	%eax, %eax
	callq	printf
	movl	$93, %edi
	callq	putchar@PLT
	incq	%rbp
	subq	$-128, %r14
	cmpq	$32, %rbp
	jne	.LBB1_7
# %bb.12:
	movl	$.L.str.9, %edi
	xorl	%eax, %eax
	callq	printf
	movl	$.L.str.2, %r14d
	movl	$.L.str.5, %r12d
	xorl	%r13d, %r13d
.LBB1_13:                               # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_14 Depth 2
	movl	$.L.str.1, %edi
	xorl	%eax, %eax
	callq	printf
	movq	%r13, %rax
	shlq	$7, %rax
	leaq	(%rsp,%rax), %rbp
	addq	$4236, %rbp                     # imm = 0x108C
	xorl	%r15d, %r15d
.LBB1_14:                               #   Parent Loop BB1_13 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	(%rbx,%r15,4), %esi
	leal	99(%rsi), %eax
	movl	$.L.str.3, %edi
	cmpl	$199, %eax
	jb	.LBB1_16
# %bb.15:                               #   in Loop: Header=BB1_14 Depth=2
	movl	$.L.str.4, %edi
.LBB1_16:                               #   in Loop: Header=BB1_14 Depth=2
	leal	9(%rsi), %eax
	cmpl	$19, %eax
	cmovbq	%r14, %rdi
                                        # kill: def $esi killed $esi killed $rsi
	xorl	%eax, %eax
	callq	printf
	incq	%r15
	cmpq	$31, %r15
	jne	.LBB1_14
# %bb.17:                               #   in Loop: Header=BB1_13 Depth=1
	movl	(%rbp), %esi
	leal	99(%rsi), %eax
	cmpl	$199, %eax
	movl	$.L.str.7, %edi
	movl	$.L.str.6, %eax
	cmovbq	%rax, %rdi
	leal	9(%rsi), %eax
	cmpl	$19, %eax
	cmovbq	%r12, %rdi
                                        # kill: def $esi killed $esi killed $rsi
	xorl	%eax, %eax
	callq	printf
	movl	$93, %edi
	callq	putchar@PLT
	incq	%r13
	subq	$-128, %rbx
	cmpq	$32, %r13
	jne	.LBB1_13
# %bb.18:
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$8216, %rsp                     # imm = 0x2018
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9addKernelPiS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z9addKernelPiS_,@object        # @_Z9addKernelPiS_
	.section	.rodata,"a",@progbits
	.globl	_Z9addKernelPiS_
	.p2align	3, 0x0
_Z9addKernelPiS_:
	.quad	_Z24__device_stub__addKernelPiS_
	.size	_Z9addKernelPiS_, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"\n\n--A--"
	.size	.L.str, 8

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"\n["
	.size	.L.str.1, 3

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"00%d-"
	.size	.L.str.2, 6

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"0%d-"
	.size	.L.str.3, 5

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"%d-"
	.size	.L.str.4, 4

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"00%d"
	.size	.L.str.5, 5

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"0%d"
	.size	.L.str.6, 4

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"%d"
	.size	.L.str.7, 3

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"\n\n--B--"
	.size	.L.str.9, 8

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z9addKernelPiS_"
	.size	.L__unnamed_1, 17

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z24__device_stub__addKernelPiS_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z9addKernelPiS_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z9addKernelPiS_        ; -- Begin function _Z9addKernelPiS_
	.globl	_Z9addKernelPiS_
	.p2align	8
	.type	_Z9addKernelPiS_,@function
_Z9addKernelPiS_:                       ; @_Z9addKernelPiS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x1c
	s_load_b128 s[8:11], s[0:1], 0x0
	v_bfe_u32 v2, v0, 10, 10
	v_and_b32_e32 v5, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s0, s2, 16
	s_and_b32 s1, s2, 0xffff
	v_mad_u64_u32 v[0:1], null, s15, s0, v[2:3]
	v_mad_u64_u32 v[3:4], null, s14, s1, v[5:6]
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v6, 5, v0
	v_or_b32_e32 v2, v0, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v6, v3
	v_cmpx_ne_u32_e32 0, v2
	s_xor_b32 s6, exec_lo, s0
	s_cbranch_execz .LBB0_30
; %bb.1:
	v_cmp_ne_u32_e64 s1, 0, v0
	v_cmp_ne_u32_e32 vcc_lo, 31, v3
	v_cmp_eq_u32_e64 s3, 31, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s0, vcc_lo, s1
	s_and_saveexec_b32 s2, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s7, exec_lo, s2
	s_cbranch_execz .LBB0_27
; %bb.2:
	v_cmp_ne_u32_e64 s0, 0, v3
	v_cmp_ne_u32_e64 s2, 31, v0
	v_cmp_eq_u32_e64 s4, 31, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s5, s0, s2
	s_and_saveexec_b32 s12, s5
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s12, exec_lo, s12
	s_cbranch_execz .LBB0_24
; %bb.3:
	v_ashrrev_i32_e32 v2, 31, v1
	s_and_b32 s3, s3, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_xor_b32 s3, s3, -1
	v_lshlrev_b64 v[4:5], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v4, s5, s8, v4
	v_add_co_ci_u32_e64 v5, s5, s9, v5, s5
	global_load_b32 v8, v[4:5], off
	s_and_saveexec_b32 s4, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s4
	s_cbranch_execz .LBB0_21
; %bb.4:
	s_and_saveexec_b32 s4, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s1, exec_lo, s4
	s_cbranch_execz .LBB0_18
; %bb.5:
	s_and_saveexec_b32 s4, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s4
	s_cbranch_execz .LBB0_15
; %bb.6:
	s_and_saveexec_b32 s4, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s0, exec_lo, s4
	s_cbranch_execz .LBB0_12
; %bb.7:
	global_load_b32 v6, v[4:5], off offset:128
	s_and_saveexec_b32 s4, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s4, exec_lo, s4
	s_cbranch_execz .LBB0_9
; %bb.8:
	s_clause 0x2
	global_load_b32 v7, v[4:5], off offset:4
	global_load_b32 v9, v[4:5], off offset:-4
	global_load_b32 v4, v[4:5], off offset:-128
	s_waitcnt vmcnt(1)
	v_add3_u32 v5, v7, v8, v9
	v_lshlrev_b32_e32 v7, 2, v3
                                        ; implicit-def: $vgpr8
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add3_u32 v4, v5, v6, v4
	v_lshl_add_u32 v5, v0, 7, v7
                                        ; implicit-def: $vgpr6
	ds_store_b32 v5, v4
                                        ; implicit-def: $vgpr4_vgpr5
.LBB0_9:                                ; %Flow
	s_and_not1_saveexec_b32 s4, s4
	s_cbranch_execz .LBB0_11
; %bb.10:
	s_clause 0x1
	global_load_b32 v7, v[4:5], off offset:-4
	global_load_b32 v4, v[4:5], off offset:-128
	s_waitcnt vmcnt(1)
	v_add_nc_u32_e32 v5, v7, v8
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v4, v5, v4, v6
	v_lshlrev_b32_e32 v5, 7, v0
	ds_store_b32 v5, v4 offset:124
.LBB0_11:                               ; %Flow134
	s_or_b32 exec_lo, exec_lo, s4
                                        ; implicit-def: $vgpr6
                                        ; implicit-def: $vgpr8
                                        ; implicit-def: $vgpr4_vgpr5
.LBB0_12:                               ; %Flow136
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB0_14
; %bb.13:
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_add_co_u32 v6, vcc_lo, s8, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
	s_clause 0x2
	global_load_b32 v6, v[6:7], off offset:4
	global_load_b32 v7, v[4:5], off offset:-128
	global_load_b32 v4, v[4:5], off offset:128
	s_waitcnt vmcnt(2)
	v_add_nc_u32_e32 v5, v6, v8
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v4, v5, v7, v4
	v_lshlrev_b32_e32 v5, 7, v0
	ds_store_b32 v5, v4
.LBB0_14:                               ; %Flow137
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr4_vgpr5
                                        ; implicit-def: $vgpr8
.LBB0_15:                               ; %Flow139
	s_and_not1_saveexec_b32 s0, s2
	s_cbranch_execz .LBB0_17
; %bb.16:
	s_clause 0x2
	global_load_b32 v6, v[4:5], off offset:4
	global_load_b32 v7, v[4:5], off offset:-4
	global_load_b32 v4, v[4:5], off offset:-128
	s_waitcnt vmcnt(2)
	v_add_nc_u32_e32 v5, v6, v8
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v4, v5, v7, v4
	v_lshlrev_b32_e32 v5, 2, v3
	ds_store_b32 v5, v4 offset:3968
.LBB0_17:                               ; %Flow140
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr4_vgpr5
                                        ; implicit-def: $vgpr8
.LBB0_18:                               ; %Flow142
	s_and_not1_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_20
; %bb.19:
	s_clause 0x2
	global_load_b32 v6, v[4:5], off offset:4
	global_load_b32 v7, v[4:5], off offset:128
	global_load_b32 v4, v[4:5], off offset:-4
	s_waitcnt vmcnt(2)
	v_add_nc_u32_e32 v5, v6, v8
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v4, v5, v4, v7
	v_lshlrev_b32_e32 v5, 2, v3
	ds_store_b32 v5, v4
.LBB0_20:                               ; %Flow143
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr4_vgpr5
                                        ; implicit-def: $vgpr8
.LBB0_21:                               ; %Flow144
	s_and_not1_saveexec_b32 s0, s3
	s_cbranch_execz .LBB0_23
; %bb.22:
	s_clause 0x1
	global_load_b32 v6, v[4:5], off offset:-4
	global_load_b32 v4, v[4:5], off offset:-128
	v_mov_b32_e32 v5, 0
	s_waitcnt vmcnt(0)
	v_add3_u32 v4, v6, v8, v4
	ds_store_b32 v5, v4 offset:4092
.LBB0_23:                               ; %Flow145
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_24:                               ; %Flow146
	s_and_not1_saveexec_b32 s0, s12
	s_cbranch_execz .LBB0_26
; %bb.25:
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[1:2]
	v_add_co_u32 v4, vcc_lo, s8, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
	s_clause 0x1
	global_load_b64 v[6:7], v[4:5], off
	global_load_b32 v4, v[4:5], off offset:-128
	v_mov_b32_e32 v5, 0
	s_waitcnt vmcnt(0)
	v_add3_u32 v4, v7, v6, v4
	ds_store_b32 v5, v4 offset:3968
.LBB0_26:                               ; %Flow147
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_27:                               ; %Flow148
	s_and_not1_saveexec_b32 s0, s7
	s_cbranch_execz .LBB0_29
; %bb.28:
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[1:2]
	v_add_co_u32 v4, vcc_lo, s8, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
	s_clause 0x1
	global_load_b64 v[6:7], v[4:5], off offset:-4
	global_load_b32 v4, v[4:5], off offset:128
	v_mov_b32_e32 v5, 0
	s_waitcnt vmcnt(0)
	v_add3_u32 v4, v6, v7, v4
	ds_store_b32 v5, v4 offset:124
.LBB0_29:                               ; %Flow149
	s_or_b32 exec_lo, exec_lo, s0
.LBB0_30:                               ; %Flow150
	s_and_not1_saveexec_b32 s0, s6
	s_cbranch_execz .LBB0_32
; %bb.31:
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[1:2]
	v_add_co_u32 v4, vcc_lo, s8, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v5, vcc_lo
	s_clause 0x1
	global_load_b64 v[6:7], v[4:5], off
	global_load_b32 v4, v[4:5], off offset:128
	v_mov_b32_e32 v5, 0
	s_waitcnt vmcnt(0)
	v_add3_u32 v4, v7, v6, v4
	ds_store_b32 v5, v4
.LBB0_32:
	s_or_b32 exec_lo, exec_lo, s0
	v_lshlrev_b32_e32 v3, 2, v3
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_lshl_add_u32 v0, v0, 7, v3
	ds_load_b32 v3, v0
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
	s_waitcnt lgkmcnt(0)
	global_store_b32 v[0:1], v3, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9addKernelPiS_
		.amdhsa_group_segment_fixed_size 4096
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z9addKernelPiS_, .Lfunc_end0-_Z9addKernelPiS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1148
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4096 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 4096
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9addKernelPiS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z9addKernelPiS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
