#include <stdio.h>
#include "cuda.h"
#define max(x,y)  ((x) > (y)? (x) : (y))
#define min(x,y)  ((x) < (y)? (x) : (y))
#define ceil(a,b) ((a) % (b) == 0 ? (a) / (b) : ((a) / (b)) + 1)

void check_error (const char* message) {
	cudaError_t error = cudaGetLastError ();
	if (error != cudaSuccess) {
		printf ("CUDA error : %s, %s\n", message, cudaGetErrorString (error));
		exit(-1);
	}
}

__global__ void curvi (float * __restrict__ r1, float *__restrict__ in_u1, float * __restrict__ in_u2, float *__restrict__ in_u3, float * __restrict__ in_mu, float * __restrict__ in_la, float * __restrict__ in_met1, float * __restrict__ in_met2, float * __restrict__ in_met3, float * __restrict__ in_met4, float * __restrict__ strx, float * __restrict__ stry, float c1, float c2, int N) {
	//Determing the block's indices
	int blockdim_k= (int)(blockDim.x);
	int k0 = (int)(blockIdx.x)*(blockdim_k);
	int k = max (k0, 0) + (int)(threadIdx.x);
	int blockdim_j= (int)(blockDim.y);
	int j0 = (int)(blockIdx.y)*(blockdim_j);
	int j = max (j0, 0) + (int)(threadIdx.y);

	float (*u1)[304][304] = (float (*)[304][304])in_u1;
	float (*u2)[304][304] = (float (*)[304][304])in_u2;
	float (*u3)[304][304] = (float (*)[304][304])in_u3;
	float (*mu)[304][304] = (float (*)[304][304])in_mu;
	float (*la)[304][304] = (float (*)[304][304])in_la;
	float (*met1)[304][304] = (float (*)[304][304])in_met1;
	float (*met2)[304][304] = (float (*)[304][304])in_met2;
	float (*met3)[304][304] = (float (*)[304][304])in_met3;
	float (*met4)[304][304] = (float (*)[304][304])in_met4;

	if (j>=2 & k>=2 & j<=N-3 & k<=N-3) {
		for (int i=2; i<=N-3; i++) {
		r1[i*N*N+j*N+k] +=
			c2*(  mu[i][j+2][k]*met1[i][j+2][k]*met1[i][j+2][k]*(
						c2*(u2[i+2][j+2][k]-u2[i-2][j+2][k]) +
						c1*(u2[i+1][j+2][k]-u2[i-1][j+2][k])    )
					+  mu[i][j-2][k]*met1[i][j-2][k]*met1[i][j-2][k]*(
						c2*(u2[i+2][j-2][k]-u2[i-2][j-2][k])+
						c1*(u2[i+1][j-2][k]-u2[i-1][j-2][k])     )
			   ) +
			c1*(  mu[i][j+1][k]*met1[i][j+1][k]*met1[i][j+1][k]*(
						c2*(u2[i+2][j+1][k]-u2[i-2][j+1][k]) +
						c1*(u2[i+1][j+1][k]-u2[i-1][j+1][k])  )
					+ mu[i][j-1][k]*met1[i][j-1][k]*met1[i][j-1][k]*(
						c2*(u2[i+2][j-1][k]-u2[i-2][j-1][k]) +
						c1*(u2[i+1][j-1][k]-u2[i-1][j-1][k])))
			+
			c2*(  la[i+2][j][k]*met1[i+2][j][k]*met1[i+2][j][k]*(
						c2*(u2[i+2][j+2][k]-u2[i+2][j-2][k]) +
						c1*(u2[i+2][j+1][k]-u2[i+2][j-1][k])    )
					+ la[i-2][j][k]*met1[i-2][j][k]*met1[i-2][j][k]*(
						c2*(u2[i-2][j+2][k]-u2[i-2][j-2][k])+
						c1*(u2[i-2][j+1][k]-u2[i-2][j-1][k])     )
			   ) +
			c1*(  la[i+1][j][k]*met1[i+1][j][k]*met1[i+1][j][k]*(
						c2*(u2[i+1][j+2][k]-u2[i+1][j-2][k]) +
						c1*(u2[i+1][j+1][k]-u2[i+1][j-1][k])  )
					+ la[i-1][j][k]*met1[i-1][j][k]*met1[i-1][j][k]*(
						c2*(u2[i-1][j+2][k]-u2[i-1][j-2][k]) +
						c1*(u2[i-1][j+1][k]-u2[i-1][j-1][k])));

		r1[i*N*N+j*N+k] += c2*(
				(2*mu[i][j][k+2]+la[i][j][k+2])*met2[i][j][k+2]*met1[i][j][k+2]*(
					c2*(u1[i+2][j][k+2]-u1[i-2][j][k+2]) +
					c1*(u1[i+1][j][k+2]-u1[i-1][j][k+2])   )*strx[i]*stry[j]
				+ mu[i][j][k+2]*met3[i][j][k+2]*met1[i][j][k+2]*(
					c2*(u2[i+2][j][k+2]-u2[i-2][j][k+2]) +
					c1*(u2[i+1][j][k+2]-u2[i-1][j][k+2])  )
				+ mu[i][j][k+2]*met4[i][j][k+2]*met1[i][j][k+2]*(
					c2*(u3[i+2][j][k+2]-u3[i-2][j][k+2]) +
					c1*(u3[i+1][j][k+2]-u3[i-1][j][k+2])  )*stry[j]
				+ ((2*mu[i][j][k-2]+la[i][j][k-2])*met2[i][j][k-2]*met1[i][j][k-2]*(
						c2*(u1[i+2][j][k-2]-u1[i-2][j][k-2]) +
						c1*(u1[i+1][j][k-2]-u1[i-1][j][k-2])  )*strx[i]*stry[j]
					+ mu[i][j][k-2]*met3[i][j][k-2]*met1[i][j][k-2]*(
						c2*(u2[i+2][j][k-2]-u2[i-2][j][k-2]) +
						c1*(u2[i+1][j][k-2]-u2[i-1][j][k-2])   )
					+ mu[i][j][k-2]*met4[i][j][k-2]*met1[i][j][k-2]*(
						c2*(u3[i+2][j][k-2]-u3[i-2][j][k-2]) +
						c1*(u3[i+1][j][k-2]-u3[i-1][j][k-2])   )*stry[j] )
				) + c1*(
					(2*mu[i][j][k+1]+la[i][j][k+1])*met2[i][j][k+1]*met1[i][j][k+1]*(
						c2*(u1[i+2][j][k+1]-u1[i-2][j][k+1]) +
						c1*(u1[i+1][j][k+1]-u1[i-1][j][k+1]) )*strx[i+2]*stry[j]
					+ mu[i][j][k+1]*met3[i][j][k+1]*met1[i][j][k+1]*(
						c2*(u2[i+2][j][k+1]-u2[i-2][j][k+1]) +
						c1*(u2[i+1][j][k+1]-u2[i-1][j][k+1]) )
					+ mu[i][j][k+1]*met4[i][j][k+1]*met1[i][j][k+1]*(
						c2*(u3[i+2][j][k+1]-u3[i-2][j][k+1]) +
						c1*(u3[i+1][j][k+1]-u3[i-1][j][k+1])  )*stry[j]
					+ ((2*mu[i][j][k-1]+la[i][j][k-1])*met2[i][j][k-1]*met1[i][j][k-1]*(
							c2*(u1[i+2][j][k-1]-u1[i-2][j][k-1]) +
							c1*(u1[i+1][j][k-1]-u1[i-1][j][k-1]) )*strx[i-2]*stry[j]
						+ mu[i][j][k-1]*met3[i][j][k-1]*met1[i][j][k-1]*(
							c2*(u2[i+2][j][k-1]-u2[i-2][j][k-1]) +
							c1*(u2[i+1][j][k-1]-u2[i-1][j][k-1]) )
						+ mu[i][j][k-1]*met4[i][j][k-1]*met1[i][j][k-1]*(
							c2*(u3[i+2][j][k-1]-u3[i-2][j][k-1]) +
							c1*(u3[i+1][j][k-1]-u3[i-1][j][k-1])   )*stry[j]  ) );

		r1[i*N*N+j*N+k] += ( c2*(
					(2*mu[i+2][j][k]+la[i+2][j][k])*met2[i+2][j][k]*met1[i+2][j][k]*(
						c2*(u1[i+2][j][k+2]-u1[i+2][j][k-2]) +
						c1*(u1[i+2][j][k+1]-u1[i+2][j][k-1])   )*strx[i]
					+ la[i+2][j][k]*met3[i+2][j][k]*met1[i+2][j][k]*(
						c2*(u2[i+2][j][k+2]-u2[i+2][j][k-2]) +
						c1*(u2[i+2][j][k+1]-u2[i+2][j][k-1])  )*stry[j]
					+ la[i+2][j][k]*met4[i+2][j][k]*met1[i+2][j][k]*(
						c2*(u3[i+2][j][k+2]-u3[i+2][j][k-2]) +
						c1*(u3[i+2][j][k+1]-u3[i+2][j][k-1])  )
					+ ((2*mu[i-2][j][k]+la[i-2][j][k])*met2[i-2][j][k]*met1[i-2][j][k]*(
							c2*(u1[i-2][j][k+2]-u1[i-2][j][k-2]) +
							c1*(u1[i-2][j][k+1]-u1[i-2][j][k-1])  )*strx[i]
						+ la[i-2][j][k]*met3[i-2][j][k]*met1[i-2][j][k]*(
							c2*(u2[i-2][j][k+2]-u2[i-2][j][k-2]) +
							c1*(u2[i-2][j][k+1]-u2[i-2][j][k-1])   )*stry[j]
						+ la[i-2][j][k]*met4[i-2][j][k]*met1[i-2][j][k]*(
							c2*(u3[i-2][j][k+2]-u3[i-2][j][k-2]) +
							c1*(u3[i-2][j][k+1]-u3[i-2][j][k-1])   ) )
				    ) + c1*(
					    (2*mu[i+1][j][k]+la[i+1][j][k])*met2[i+1][j][k]*met1[i+1][j][k]*(
						    c2*(u1[i+1][j][k+2]-u1[i+1][j][k-2]) +
						    c1*(u1[i+1][j][k+1]-u1[i+1][j][k-1]) )*strx[i]
					    + la[i+1][j][k]*met3[i+1][j][k]*met1[i+1][j][k]*(
						    c2*(u2[i+1][j][k+2]-u2[i+1][j][k-2]) +
						    c1*(u2[i+1][j][k+1]-u2[i+1][j][k-1]) )*stry[j]
					    + la[i+1][j][k]*met4[i+1][j][k]*met1[i+1][j][k]*(
						    c2*(u3[i+1][j][k+2]-u3[i+1][j][k-2]) +
						    c1*(u3[i+1][j][k+1]-u3[i+1][j][k-1])  )
					    + ((2*mu[i-1][j][k]+la[i-1][j][k])*met2[i-1][j][k]*met1[i-1][j][k]*(
							    c2*(u1[i-1][j][k+2]-u1[i-1][j][k-2]) +
							    c1*(u1[i-1][j][k+1]-u1[i-1][j][k-1]) )*strx[i]
						    + la[i-1][j][k]*met3[i-1][j][k]*met1[i-1][j][k]*(
							    c2*(u2[i-1][j][k+2]-u2[i-1][j][k-2]) +
							    c1*(u2[i-1][j][k+1]-u2[i-1][j][k-1]) )*stry[j]
						    + la[i-1][j][k]*met4[i-1][j][k]*met1[i-1][j][k]*(
							    c2*(u3[i-1][j][k+2]-u3[i-1][j][k-2]) +
							    c1*(u3[i-1][j][k+1]-u3[i-1][j][k-1])   )  ) ) )*stry[j];

		r1[i*N*N+j*N+k] += c2*(
				mu[i][j+2][k]*met3[i][j+2][k]*met1[i][j+2][k]*(
					c2*(u1[i][j+2][k+2]-u1[i][j+2][k-2]) +
					c1*(u1[i][j+2][k+1]-u1[i][j+2][k-1])   )*stry[j+1]*strx[i]
				+ mu[i][j+2][k]*met2[i][j+2][k]*met1[i][j+2][k]*(
					c2*(u2[i][j+2][k+2]-u2[i][j+2][k-2]) +
					c1*(u2[i][j+2][k+1]-u2[i][j+2][k-1])  )
				+ ( mu[i][j-2][k]*met3[i][j-2][k]*met1[i][j-2][k]*(
						c2*(u1[i][j-2][k+2]-u1[i][j-2][k-2]) +
						c1*(u1[i][j-2][k+1]-u1[i][j-2][k-1])  )*stry[j]*strx[i]
					+ mu[i][j-2][k]*met2[i][j-2][k]*met1[i][j-2][k]*(
						c2*(u2[i][j-2][k+2]-u2[i][j-2][k-2]) +
						c1*(u2[i][j-2][k+1]-u2[i][j-2][k-1])   ) )
				) + c1*(
					mu[i][j+1][k]*met3[i][j+1][k]*met1[i][j+1][k]*(
						c2*(u1[i][j+1][k+2]-u1[i][j+1][k-2]) +
						c1*(u1[i][j+1][k+1]-u1[i][j+1][k-1]) )*stry[j-1]*strx[i]
					+ mu[i][j+1][k]*met2[i][j+1][k]*met1[i][j+1][k]*(
						c2*(u2[i][j+1][k+2]-u2[i][j+1][k-2]) +
						c1*(u2[i][j+1][k+1]-u2[i][j+1][k-1]) )
					+ ( mu[i][j-1][k]*met3[i][j-1][k]*met1[i][j-1][k]*(
							c2*(u1[i][j-1][k+2]-u1[i][j-1][k-2]) +
							c1*(u1[i][j-1][k+1]-u1[i][j-1][k-1]) )*stry[j]*strx[i]
						+ mu[i][j-1][k]*met2[i][j-1][k]*met1[i][j-1][k]*(
							c2*(u2[i][j-1][k+2]-u2[i][j-1][k-2]) +
							c1*(u2[i][j-1][k+1]-u2[i][j-1][k-1]) ) ) );


		r1[i*N*N+j*N+k] += c2*(
				mu[i][j][k+2]*met3[i][j][k+2]*met1[i][j][k+2]*(
					c2*(u1[i][j+2][k+2]-u1[i][j-2][k+2]) +
					c1*(u1[i][j+1][k+2]-u1[i][j-1][k+2])   )*stry[j+2]*strx[i]
				+ la[i][j][k+2]*met2[i][j][k+2]*met1[i][j][k+2]*(
					c2*(u2[i][j+2][k+2]-u2[i][j-2][k+2]) +
					c1*(u2[i][j+1][k+2]-u2[i][j-1][k+2])  )
				+ ( mu[i][j][k-2]*met3[i][j][k-2]*met1[i][j][k-2]*(
						c2*(u1[i][j+2][k-2]-u1[i][j-2][k-2]) +
						c1*(u1[i][j+1][k-2]-u1[i][j-1][k-2])  )*stry[j]*strx[i]
					+ la[i][j][k-2]*met2[i][j][k-2]*met1[i][j][k-2]*(
						c2*(u2[i][j+2][k-2]-u2[i][j-2][k-2]) +
						c1*(u2[i][j+1][k-2]-u2[i][j-1][k-2])   ) )
				) + c1*(
					mu[i][j][k+1]*met3[i][j][k+1]*met1[i][j][k+1]*(
						c2*(u1[i][j+2][k+1]-u1[i][j-2][k+1]) +
						c1*(u1[i][j+1][k+1]-u1[i][j-1][k+1]) )*stry[j-2]*strx[i]
					+ la[i][j][k+1]*met2[i][j][k+1]*met1[i][j][k+1]*(
						c2*(u2[i][j+2][k+1]-u2[i][j-2][k+1]) +
						c1*(u2[i][j+1][k+1]-u2[i][j-1][k+1]) )
					+ ( mu[i][j][k-1]*met3[i][j][k-1]*met1[i][j][k-1]*(
							c2*(u1[i][j+2][k-1]-u1[i][j-2][k-1]) +
							c1*(u1[i][j+1][k-1]-u1[i][j-1][k-1]) )*stry[j]*strx[i]
						+ la[i][j][k-1]*met2[i][j][k-1]*met1[i][j][k-1]*(
							c2*(u2[i][j+2][k-1]-u2[i][j-2][k-1]) +
							c1*(u2[i][j+1][k-1]-u2[i][j-1][k-1]) ) ) );

		}
	} 
}

extern "C" void host_code (float *h_r1, float *h_u1, float *h_u2, float *h_u3,  float *h_mu, float *h_la, float *h_met1, float *h_met2, float *h_met3, float *h_met4, float *h_strx, float *h_stry, float c1, float c2, int N) {
	float *r1;
	cudaMalloc (&r1, sizeof(float)*N*N*N);
	check_error ("Failed to allocate device memory for r1\n");
	cudaMemcpy (r1, h_r1, sizeof(float)*N*N*N, cudaMemcpyHostToDevice);
	float *u1;
	cudaMalloc (&u1, sizeof(float)*N*N*N);
	check_error ("Failed to allocate device memory for u1\n");
	cudaMemcpy (u1, h_u1, sizeof(float)*N*N*N, cudaMemcpyHostToDevice);
	float *u2;
	cudaMalloc (&u2, sizeof(float)*N*N*N);
	check_error ("Failed to allocate device memory for u2\n");
	cudaMemcpy (u2, h_u2, sizeof(float)*N*N*N, cudaMemcpyHostToDevice);
	float *u3;
	cudaMalloc (&u3, sizeof(float)*N*N*N);
	check_error ("Failed to allocate device memory for u3\n");
	cudaMemcpy (u3, h_u3, sizeof(float)*N*N*N, cudaMemcpyHostToDevice);
	float *mu;
	cudaMalloc (&mu, sizeof(float)*N*N*N);
	check_error ("Failed to allocate device memory for mu\n");
	cudaMemcpy (mu, h_mu, sizeof(float)*N*N*N, cudaMemcpyHostToDevice);
	float *la;
	cudaMalloc (&la, sizeof(float)*N*N*N);
	check_error ("Failed to allocate device memory for la\n");
	cudaMemcpy (la, h_la, sizeof(float)*N*N*N, cudaMemcpyHostToDevice);
	float *met1;
	cudaMalloc (&met1, sizeof(float)*N*N*N);
	check_error ("Failed to allocate device memory for met1\n");
	cudaMemcpy (met1, h_met1, sizeof(float)*N*N*N, cudaMemcpyHostToDevice);
	float *met2;
	cudaMalloc (&met2, sizeof(float)*N*N*N);
	check_error ("Failed to allocate device memory for met2\n");
	cudaMemcpy (met2, h_met2, sizeof(float)*N*N*N, cudaMemcpyHostToDevice);
	float *met3;
	cudaMalloc (&met3, sizeof(float)*N*N*N);
	check_error ("Failed to allocate device memory for met3\n");
	cudaMemcpy (met3, h_met3, sizeof(float)*N*N*N, cudaMemcpyHostToDevice);
	float *met4;
	cudaMalloc (&met4, sizeof(float)*N*N*N);
	check_error ("Failed to allocate device memory for met4\n");
	cudaMemcpy (met4, h_met4, sizeof(float)*N*N*N, cudaMemcpyHostToDevice);
	float *strx;
	cudaMalloc (&strx, sizeof(float)*N);
	check_error ("Failed to allocate device memory for strx\n");
	cudaMemcpy (strx, h_strx, sizeof(float)*N, cudaMemcpyHostToDevice);
	float *stry;
	cudaMalloc (&stry, sizeof(float)*N);
	check_error ("Failed to allocate device memory for stry\n");
	cudaMemcpy (stry, h_stry, sizeof(float)*N, cudaMemcpyHostToDevice);

	dim3 blockconfig (32, 8);
	dim3 gridconfig (ceil(N, blockconfig.x), ceil(N, blockconfig.y), 1);

	curvi <<<gridconfig, blockconfig>>> (r1, u1, u2, u3, mu, la, met1, met2, met3, met4, strx, stry, c1, c2, N);
	cudaMemcpy (h_r1, r1, sizeof(float)*N*N*N, cudaMemcpyDeviceToHost);
}

	.file	"tmpxft_00255d38_00000000-6_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0, @function
_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0:
.LFB2173:
	.cfi_startproc
	jmp	cudaMalloc@PLT
	.cfi_endproc
.LFE2173:
	.size	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0, .-_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"CUDA error : %s, %s\n"
	.text
	.globl	_Z11check_errorPKc
	.type	_Z11check_errorPKc, @function
_Z11check_errorPKc:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movq	%rdi, %rbx
	call	cudaGetLastError@PLT
	testl	%eax, %eax
	je	.L3
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	movl	$2, %edi
	movq	%rbx, %rdx
	leaq	.LC0(%rip), %rsi
	movq	%rax, %rcx
	xorl	%eax, %eax
	call	__printf_chk@PLT
	orl	$-1, %edi
	call	exit@PLT
.L3:
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z11check_errorPKc, .-_Z11check_errorPKc
	.globl	_Z49__device_stub__Z5curviPfS_S_S_S_S_S_S_S_S_S_S_ffiPfS_S_S_S_S_S_S_S_S_S_S_ffi
	.type	_Z49__device_stub__Z5curviPfS_S_S_S_S_S_S_S_S_S_S_ffiPfS_S_S_S_S_S_S_S_S_S_S_ffi, @function
_Z49__device_stub__Z5curviPfS_S_S_S_S_S_S_S_S_S_S_ffiPfS_S_S_S_S_S_S_S_S_S_S_ffi:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$312, %rsp
	.cfi_def_cfa_offset 320
	movss	%xmm0, 12(%rsp)
	movss	%xmm1, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 296(%rsp)
	xorl	%eax, %eax
	leaq	16(%rsp), %rax
	movq	%rdi, 16(%rsp)
	leaq	128(%rsp), %rdi
	movq	%rax, 176(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 216(%rsp)
	movq	320(%rsp), %rax
	movq	%rsi, 24(%rsp)
	leaq	140(%rsp), %rsi
	movq	%rax, 64(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 224(%rsp)
	movq	328(%rsp), %rax
	movq	%rdx, 32(%rsp)
	leaq	112(%rsp), %rdx
	movq	%rax, 72(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 232(%rsp)
	movq	336(%rsp), %rax
	movq	%rcx, 40(%rsp)
	leaq	120(%rsp), %rcx
	movq	%rax, 80(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 240(%rsp)
	movq	344(%rsp), %rax
	movq	%r8, 48(%rsp)
	movq	%rax, 88(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 248(%rsp)
	movq	352(%rsp), %rax
	movq	%r9, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, 256(%rsp)
	movq	360(%rsp), %rax
	movl	$1, 136(%rsp)
	movq	%rax, 104(%rsp)
	leaq	104(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	368(%rsp), %rax
	movq	%rax, 288(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 128(%rsp)
	movq	%rax, 140(%rsp)
	movl	$1, 148(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L7
	pushq	120(%rsp)
	.cfi_def_cfa_offset 328
	leaq	_Z5curviPfS_S_S_S_S_S_S_S_S_S_S_ffi(%rip), %rdi
	pushq	120(%rsp)
	.cfi_def_cfa_offset 336
	movq	156(%rsp), %rcx
	movl	164(%rsp), %r8d
	movq	144(%rsp), %rsi
	movl	152(%rsp), %edx
	leaq	192(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 328
	popq	%rdx
	.cfi_def_cfa_offset 320
.L7:
	movq	296(%rsp), %rax
	subq	%fs:40, %rax
	je	.L9
	call	__stack_chk_fail@PLT
.L9:
	addq	$312, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z49__device_stub__Z5curviPfS_S_S_S_S_S_S_S_S_S_S_ffiPfS_S_S_S_S_S_S_S_S_S_S_ffi, .-_Z49__device_stub__Z5curviPfS_S_S_S_S_S_S_S_S_S_S_ffiPfS_S_S_S_S_S_S_S_S_S_S_ffi
	.globl	_Z5curviPfS_S_S_S_S_S_S_S_S_S_S_ffi
	.type	_Z5curviPfS_S_S_S_S_S_S_S_S_S_S_ffi, @function
_Z5curviPfS_S_S_S_S_S_S_S_S_S_S_ffi:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z49__device_stub__Z5curviPfS_S_S_S_S_S_S_S_S_S_S_ffiPfS_S_S_S_S_S_S_S_S_S_S_ffi
	.cfi_endproc
.LFE2054:
	.size	_Z5curviPfS_S_S_S_S_S_S_S_S_S_S_ffi, .-_Z5curviPfS_S_S_S_S_S_S_S_S_S_S_ffi
	.section	.rodata.str1.1
.LC1:
	.string	"Failed to allocate device memory for r1\n"
.LC2:
	.string	"Failed to allocate device memory for u1\n"
.LC3:
	.string	"Failed to allocate device memory for u2\n"
.LC4:
	.string	"Failed to allocate device memory for u3\n"
.LC5:
	.string	"Failed to allocate device memory for mu\n"
.LC6:
	.string	"Failed to allocate device memory for la\n"
.LC7:
	.string	"Failed to allocate device memory for met1\n"
.LC8:
	.string	"Failed to allocate device memory for met2\n"
.LC9:
	.string	"Failed to allocate device memory for met3\n"
.LC10:
	.string	"Failed to allocate device memory for met4\n"
.LC11:
	.string	"Failed to allocate device memory for strx\n"
.LC12:
	.string	"Failed to allocate device memory for stry\n"
	.text
	.globl	host_code
	.type	host_code, @function
host_code:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rsi, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rdx, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rcx, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%r8, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$216, %rsp
	.cfi_def_cfa_offset 272
	movq	272(%rsp), %rax
	movq	%r9, 16(%rsp)
	movq	%rdi, 8(%rsp)
	movslq	320(%rsp), %rbp
	leaq	80(%rsp), %rdi
	movq	%rax, 24(%rsp)
	movq	280(%rsp), %rax
	movss	%xmm0, 76(%rsp)
	movq	%rbp, %rbx
	movq	%rax, 32(%rsp)
	movq	288(%rsp), %rax
	movss	%xmm1, 72(%rsp)
	movq	%rax, 40(%rsp)
	movq	296(%rsp), %rax
	movq	%rax, 48(%rsp)
	movq	304(%rsp), %rax
	movq	%rax, 56(%rsp)
	movq	312(%rsp), %rax
	movq	%rax, 64(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	movq	%rbp, %rax
	imulq	%rbp, %rax
	imulq	%rbp, %rax
	salq	$2, %rax
	movq	%rax, %rsi
	movq	%rax, (%rsp)
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	.LC1(%rip), %rdi
	call	_Z11check_errorPKc
	movq	(%rsp), %rdx
	movq	8(%rsp), %rsi
	movl	$1, %ecx
	movq	80(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rsi
	leaq	88(%rsp), %rdi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	.LC2(%rip), %rdi
	call	_Z11check_errorPKc
	movq	(%rsp), %rdx
	movq	88(%rsp), %rdi
	movq	%r15, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	(%rsp), %rsi
	leaq	96(%rsp), %rdi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	.LC3(%rip), %rdi
	call	_Z11check_errorPKc
	movq	(%rsp), %rdx
	movq	96(%rsp), %rdi
	movq	%r14, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	(%rsp), %rsi
	leaq	104(%rsp), %rdi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	.LC4(%rip), %rdi
	call	_Z11check_errorPKc
	movq	(%rsp), %rdx
	movq	104(%rsp), %rdi
	movq	%r13, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	(%rsp), %rsi
	leaq	112(%rsp), %rdi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	.LC5(%rip), %rdi
	call	_Z11check_errorPKc
	movq	(%rsp), %rdx
	movq	112(%rsp), %rdi
	movq	%r12, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	(%rsp), %rsi
	leaq	120(%rsp), %rdi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	.LC6(%rip), %rdi
	call	_Z11check_errorPKc
	movq	(%rsp), %rdx
	movq	16(%rsp), %rsi
	movl	$1, %ecx
	movq	120(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rsi
	leaq	128(%rsp), %rdi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	.LC7(%rip), %rdi
	call	_Z11check_errorPKc
	movq	(%rsp), %rdx
	movq	24(%rsp), %rsi
	movl	$1, %ecx
	movq	128(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rsi
	leaq	136(%rsp), %rdi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	.LC8(%rip), %rdi
	call	_Z11check_errorPKc
	movq	(%rsp), %rdx
	movq	32(%rsp), %rsi
	movl	$1, %ecx
	movq	136(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rsi
	leaq	144(%rsp), %rdi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	.LC9(%rip), %rdi
	call	_Z11check_errorPKc
	movq	(%rsp), %rdx
	movq	40(%rsp), %rsi
	movl	$1, %ecx
	movq	144(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	(%rsp), %rsi
	leaq	152(%rsp), %rdi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	.LC10(%rip), %rdi
	salq	$2, %rbp
	call	_Z11check_errorPKc
	movq	(%rsp), %rdx
	movq	48(%rsp), %rsi
	movl	$1, %ecx
	movq	152(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	%rbp, %rsi
	leaq	160(%rsp), %rdi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	.LC11(%rip), %rdi
	call	_Z11check_errorPKc
	movq	56(%rsp), %rsi
	movl	$1, %ecx
	movq	%rbp, %rdx
	movq	160(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	%rbp, %rsi
	leaq	168(%rsp), %rdi
	call	_Z10cudaMallocIfE9cudaErrorPPT_m.isra.0
	leaq	.LC12(%rip), %rdi
	call	_Z11check_errorPKc
	movq	64(%rsp), %rsi
	movl	$1, %ecx
	movq	%rbp, %rdx
	movq	168(%rsp), %rdi
	call	cudaMemcpy@PLT
	movl	%ebx, %edx
	movl	%ebx, %eax
	movl	%ebx, %ecx
	andl	$7, %edx
	shrl	$3, %eax
	movl	$1, %esi
	cmpl	$1, %edx
	movl	%ebx, %edx
	sbbl	$-1, %eax
	andl	$31, %ecx
	shrl	$5, %edx
	cmpl	$1, %ecx
	movl	%eax, 192(%rsp)
	movl	$1, %ecx
	sbbl	$-1, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	%edx, 188(%rsp)
	movl	$1073741825, %edx
	movq	188(%rsp), %rdi
	salq	$5, %rdx
	call	__cudaPushCallConfiguration@PLT
	movss	72(%rsp), %xmm1
	movss	76(%rsp), %xmm0
	testl	%eax, %eax
	jne	.L15
	pushq	%rax
	.cfi_def_cfa_offset 280
	pushq	%rbx
	.cfi_def_cfa_offset 288
	pushq	184(%rsp)
	.cfi_def_cfa_offset 296
	pushq	184(%rsp)
	.cfi_def_cfa_offset 304
	pushq	184(%rsp)
	.cfi_def_cfa_offset 312
	pushq	184(%rsp)
	.cfi_def_cfa_offset 320
	pushq	184(%rsp)
	.cfi_def_cfa_offset 328
	pushq	184(%rsp)
	.cfi_def_cfa_offset 336
	movq	184(%rsp), %r9
	movq	176(%rsp), %r8
	movq	168(%rsp), %rcx
	movq	160(%rsp), %rdx
	movq	152(%rsp), %rsi
	movq	144(%rsp), %rdi
	call	_Z49__device_stub__Z5curviPfS_S_S_S_S_S_S_S_S_S_S_ffiPfS_S_S_S_S_S_S_S_S_S_S_ffi
	addq	$64, %rsp
	.cfi_def_cfa_offset 272
.L15:
	movq	(%rsp), %rdx
	movq	80(%rsp), %rsi
	movl	$2, %ecx
	movq	8(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L16
	call	__stack_chk_fail@PLT
.L16:
	addq	$216, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	host_code, .-host_code
	.section	.rodata.str1.1
.LC13:
	.string	"_Z5curviPfS_S_S_S_S_S_S_S_S_S_S_ffi"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC13(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z5curviPfS_S_S_S_S_S_S_S_S_S_S_ffi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2056:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include "hip/hip_runtime.h"
#define max(x,y)  ((x) > (y)? (x) : (y))
#define min(x,y)  ((x) < (y)? (x) : (y))
#define ceil(a,b) ((a) % (b) == 0 ? (a) / (b) : ((a) / (b)) + 1)

void check_error (const char* message) {
	hipError_t error = hipGetLastError ();
	if (error != hipSuccess) {
		printf ("CUDA error : %s, %s\n", message, hipGetErrorString (error));
		exit(-1);
	}
}

__global__ void curvi (float * __restrict__ r1, float *__restrict__ in_u1, float * __restrict__ in_u2, float *__restrict__ in_u3, float * __restrict__ in_mu, float * __restrict__ in_la, float * __restrict__ in_met1, float * __restrict__ in_met2, float * __restrict__ in_met3, float * __restrict__ in_met4, float * __restrict__ strx, float * __restrict__ stry, float c1, float c2, int N) {
	//Determing the block's indices
	int blockdim_k= (int)(blockDim.x);
	int k0 = (int)(blockIdx.x)*(blockdim_k);
	int k = max (k0, 0) + (int)(threadIdx.x);
	int blockdim_j= (int)(blockDim.y);
	int j0 = (int)(blockIdx.y)*(blockdim_j);
	int j = max (j0, 0) + (int)(threadIdx.y);

	float (*u1)[304][304] = (float (*)[304][304])in_u1;
	float (*u2)[304][304] = (float (*)[304][304])in_u2;
	float (*u3)[304][304] = (float (*)[304][304])in_u3;
	float (*mu)[304][304] = (float (*)[304][304])in_mu;
	float (*la)[304][304] = (float (*)[304][304])in_la;
	float (*met1)[304][304] = (float (*)[304][304])in_met1;
	float (*met2)[304][304] = (float (*)[304][304])in_met2;
	float (*met3)[304][304] = (float (*)[304][304])in_met3;
	float (*met4)[304][304] = (float (*)[304][304])in_met4;

	if (j>=2 & k>=2 & j<=N-3 & k<=N-3) {
		for (int i=2; i<=N-3; i++) {
		r1[i*N*N+j*N+k] +=
			c2*(  mu[i][j+2][k]*met1[i][j+2][k]*met1[i][j+2][k]*(
						c2*(u2[i+2][j+2][k]-u2[i-2][j+2][k]) +
						c1*(u2[i+1][j+2][k]-u2[i-1][j+2][k])    )
					+  mu[i][j-2][k]*met1[i][j-2][k]*met1[i][j-2][k]*(
						c2*(u2[i+2][j-2][k]-u2[i-2][j-2][k])+
						c1*(u2[i+1][j-2][k]-u2[i-1][j-2][k])     )
			   ) +
			c1*(  mu[i][j+1][k]*met1[i][j+1][k]*met1[i][j+1][k]*(
						c2*(u2[i+2][j+1][k]-u2[i-2][j+1][k]) +
						c1*(u2[i+1][j+1][k]-u2[i-1][j+1][k])  )
					+ mu[i][j-1][k]*met1[i][j-1][k]*met1[i][j-1][k]*(
						c2*(u2[i+2][j-1][k]-u2[i-2][j-1][k]) +
						c1*(u2[i+1][j-1][k]-u2[i-1][j-1][k])))
			+
			c2*(  la[i+2][j][k]*met1[i+2][j][k]*met1[i+2][j][k]*(
						c2*(u2[i+2][j+2][k]-u2[i+2][j-2][k]) +
						c1*(u2[i+2][j+1][k]-u2[i+2][j-1][k])    )
					+ la[i-2][j][k]*met1[i-2][j][k]*met1[i-2][j][k]*(
						c2*(u2[i-2][j+2][k]-u2[i-2][j-2][k])+
						c1*(u2[i-2][j+1][k]-u2[i-2][j-1][k])     )
			   ) +
			c1*(  la[i+1][j][k]*met1[i+1][j][k]*met1[i+1][j][k]*(
						c2*(u2[i+1][j+2][k]-u2[i+1][j-2][k]) +
						c1*(u2[i+1][j+1][k]-u2[i+1][j-1][k])  )
					+ la[i-1][j][k]*met1[i-1][j][k]*met1[i-1][j][k]*(
						c2*(u2[i-1][j+2][k]-u2[i-1][j-2][k]) +
						c1*(u2[i-1][j+1][k]-u2[i-1][j-1][k])));

		r1[i*N*N+j*N+k] += c2*(
				(2*mu[i][j][k+2]+la[i][j][k+2])*met2[i][j][k+2]*met1[i][j][k+2]*(
					c2*(u1[i+2][j][k+2]-u1[i-2][j][k+2]) +
					c1*(u1[i+1][j][k+2]-u1[i-1][j][k+2])   )*strx[i]*stry[j]
				+ mu[i][j][k+2]*met3[i][j][k+2]*met1[i][j][k+2]*(
					c2*(u2[i+2][j][k+2]-u2[i-2][j][k+2]) +
					c1*(u2[i+1][j][k+2]-u2[i-1][j][k+2])  )
				+ mu[i][j][k+2]*met4[i][j][k+2]*met1[i][j][k+2]*(
					c2*(u3[i+2][j][k+2]-u3[i-2][j][k+2]) +
					c1*(u3[i+1][j][k+2]-u3[i-1][j][k+2])  )*stry[j]
				+ ((2*mu[i][j][k-2]+la[i][j][k-2])*met2[i][j][k-2]*met1[i][j][k-2]*(
						c2*(u1[i+2][j][k-2]-u1[i-2][j][k-2]) +
						c1*(u1[i+1][j][k-2]-u1[i-1][j][k-2])  )*strx[i]*stry[j]
					+ mu[i][j][k-2]*met3[i][j][k-2]*met1[i][j][k-2]*(
						c2*(u2[i+2][j][k-2]-u2[i-2][j][k-2]) +
						c1*(u2[i+1][j][k-2]-u2[i-1][j][k-2])   )
					+ mu[i][j][k-2]*met4[i][j][k-2]*met1[i][j][k-2]*(
						c2*(u3[i+2][j][k-2]-u3[i-2][j][k-2]) +
						c1*(u3[i+1][j][k-2]-u3[i-1][j][k-2])   )*stry[j] )
				) + c1*(
					(2*mu[i][j][k+1]+la[i][j][k+1])*met2[i][j][k+1]*met1[i][j][k+1]*(
						c2*(u1[i+2][j][k+1]-u1[i-2][j][k+1]) +
						c1*(u1[i+1][j][k+1]-u1[i-1][j][k+1]) )*strx[i+2]*stry[j]
					+ mu[i][j][k+1]*met3[i][j][k+1]*met1[i][j][k+1]*(
						c2*(u2[i+2][j][k+1]-u2[i-2][j][k+1]) +
						c1*(u2[i+1][j][k+1]-u2[i-1][j][k+1]) )
					+ mu[i][j][k+1]*met4[i][j][k+1]*met1[i][j][k+1]*(
						c2*(u3[i+2][j][k+1]-u3[i-2][j][k+1]) +
						c1*(u3[i+1][j][k+1]-u3[i-1][j][k+1])  )*stry[j]
					+ ((2*mu[i][j][k-1]+la[i][j][k-1])*met2[i][j][k-1]*met1[i][j][k-1]*(
							c2*(u1[i+2][j][k-1]-u1[i-2][j][k-1]) +
							c1*(u1[i+1][j][k-1]-u1[i-1][j][k-1]) )*strx[i-2]*stry[j]
						+ mu[i][j][k-1]*met3[i][j][k-1]*met1[i][j][k-1]*(
							c2*(u2[i+2][j][k-1]-u2[i-2][j][k-1]) +
							c1*(u2[i+1][j][k-1]-u2[i-1][j][k-1]) )
						+ mu[i][j][k-1]*met4[i][j][k-1]*met1[i][j][k-1]*(
							c2*(u3[i+2][j][k-1]-u3[i-2][j][k-1]) +
							c1*(u3[i+1][j][k-1]-u3[i-1][j][k-1])   )*stry[j]  ) );

		r1[i*N*N+j*N+k] += ( c2*(
					(2*mu[i+2][j][k]+la[i+2][j][k])*met2[i+2][j][k]*met1[i+2][j][k]*(
						c2*(u1[i+2][j][k+2]-u1[i+2][j][k-2]) +
						c1*(u1[i+2][j][k+1]-u1[i+2][j][k-1])   )*strx[i]
					+ la[i+2][j][k]*met3[i+2][j][k]*met1[i+2][j][k]*(
						c2*(u2[i+2][j][k+2]-u2[i+2][j][k-2]) +
						c1*(u2[i+2][j][k+1]-u2[i+2][j][k-1])  )*stry[j]
					+ la[i+2][j][k]*met4[i+2][j][k]*met1[i+2][j][k]*(
						c2*(u3[i+2][j][k+2]-u3[i+2][j][k-2]) +
						c1*(u3[i+2][j][k+1]-u3[i+2][j][k-1])  )
					+ ((2*mu[i-2][j][k]+la[i-2][j][k])*met2[i-2][j][k]*met1[i-2][j][k]*(
							c2*(u1[i-2][j][k+2]-u1[i-2][j][k-2]) +
							c1*(u1[i-2][j][k+1]-u1[i-2][j][k-1])  )*strx[i]
						+ la[i-2][j][k]*met3[i-2][j][k]*met1[i-2][j][k]*(
							c2*(u2[i-2][j][k+2]-u2[i-2][j][k-2]) +
							c1*(u2[i-2][j][k+1]-u2[i-2][j][k-1])   )*stry[j]
						+ la[i-2][j][k]*met4[i-2][j][k]*met1[i-2][j][k]*(
							c2*(u3[i-2][j][k+2]-u3[i-2][j][k-2]) +
							c1*(u3[i-2][j][k+1]-u3[i-2][j][k-1])   ) )
				    ) + c1*(
					    (2*mu[i+1][j][k]+la[i+1][j][k])*met2[i+1][j][k]*met1[i+1][j][k]*(
						    c2*(u1[i+1][j][k+2]-u1[i+1][j][k-2]) +
						    c1*(u1[i+1][j][k+1]-u1[i+1][j][k-1]) )*strx[i]
					    + la[i+1][j][k]*met3[i+1][j][k]*met1[i+1][j][k]*(
						    c2*(u2[i+1][j][k+2]-u2[i+1][j][k-2]) +
						    c1*(u2[i+1][j][k+1]-u2[i+1][j][k-1]) )*stry[j]
					    + la[i+1][j][k]*met4[i+1][j][k]*met1[i+1][j][k]*(
						    c2*(u3[i+1][j][k+2]-u3[i+1][j][k-2]) +
						    c1*(u3[i+1][j][k+1]-u3[i+1][j][k-1])  )
					    + ((2*mu[i-1][j][k]+la[i-1][j][k])*met2[i-1][j][k]*met1[i-1][j][k]*(
							    c2*(u1[i-1][j][k+2]-u1[i-1][j][k-2]) +
							    c1*(u1[i-1][j][k+1]-u1[i-1][j][k-1]) )*strx[i]
						    + la[i-1][j][k]*met3[i-1][j][k]*met1[i-1][j][k]*(
							    c2*(u2[i-1][j][k+2]-u2[i-1][j][k-2]) +
							    c1*(u2[i-1][j][k+1]-u2[i-1][j][k-1]) )*stry[j]
						    + la[i-1][j][k]*met4[i-1][j][k]*met1[i-1][j][k]*(
							    c2*(u3[i-1][j][k+2]-u3[i-1][j][k-2]) +
							    c1*(u3[i-1][j][k+1]-u3[i-1][j][k-1])   )  ) ) )*stry[j];

		r1[i*N*N+j*N+k] += c2*(
				mu[i][j+2][k]*met3[i][j+2][k]*met1[i][j+2][k]*(
					c2*(u1[i][j+2][k+2]-u1[i][j+2][k-2]) +
					c1*(u1[i][j+2][k+1]-u1[i][j+2][k-1])   )*stry[j+1]*strx[i]
				+ mu[i][j+2][k]*met2[i][j+2][k]*met1[i][j+2][k]*(
					c2*(u2[i][j+2][k+2]-u2[i][j+2][k-2]) +
					c1*(u2[i][j+2][k+1]-u2[i][j+2][k-1])  )
				+ ( mu[i][j-2][k]*met3[i][j-2][k]*met1[i][j-2][k]*(
						c2*(u1[i][j-2][k+2]-u1[i][j-2][k-2]) +
						c1*(u1[i][j-2][k+1]-u1[i][j-2][k-1])  )*stry[j]*strx[i]
					+ mu[i][j-2][k]*met2[i][j-2][k]*met1[i][j-2][k]*(
						c2*(u2[i][j-2][k+2]-u2[i][j-2][k-2]) +
						c1*(u2[i][j-2][k+1]-u2[i][j-2][k-1])   ) )
				) + c1*(
					mu[i][j+1][k]*met3[i][j+1][k]*met1[i][j+1][k]*(
						c2*(u1[i][j+1][k+2]-u1[i][j+1][k-2]) +
						c1*(u1[i][j+1][k+1]-u1[i][j+1][k-1]) )*stry[j-1]*strx[i]
					+ mu[i][j+1][k]*met2[i][j+1][k]*met1[i][j+1][k]*(
						c2*(u2[i][j+1][k+2]-u2[i][j+1][k-2]) +
						c1*(u2[i][j+1][k+1]-u2[i][j+1][k-1]) )
					+ ( mu[i][j-1][k]*met3[i][j-1][k]*met1[i][j-1][k]*(
							c2*(u1[i][j-1][k+2]-u1[i][j-1][k-2]) +
							c1*(u1[i][j-1][k+1]-u1[i][j-1][k-1]) )*stry[j]*strx[i]
						+ mu[i][j-1][k]*met2[i][j-1][k]*met1[i][j-1][k]*(
							c2*(u2[i][j-1][k+2]-u2[i][j-1][k-2]) +
							c1*(u2[i][j-1][k+1]-u2[i][j-1][k-1]) ) ) );


		r1[i*N*N+j*N+k] += c2*(
				mu[i][j][k+2]*met3[i][j][k+2]*met1[i][j][k+2]*(
					c2*(u1[i][j+2][k+2]-u1[i][j-2][k+2]) +
					c1*(u1[i][j+1][k+2]-u1[i][j-1][k+2])   )*stry[j+2]*strx[i]
				+ la[i][j][k+2]*met2[i][j][k+2]*met1[i][j][k+2]*(
					c2*(u2[i][j+2][k+2]-u2[i][j-2][k+2]) +
					c1*(u2[i][j+1][k+2]-u2[i][j-1][k+2])  )
				+ ( mu[i][j][k-2]*met3[i][j][k-2]*met1[i][j][k-2]*(
						c2*(u1[i][j+2][k-2]-u1[i][j-2][k-2]) +
						c1*(u1[i][j+1][k-2]-u1[i][j-1][k-2])  )*stry[j]*strx[i]
					+ la[i][j][k-2]*met2[i][j][k-2]*met1[i][j][k-2]*(
						c2*(u2[i][j+2][k-2]-u2[i][j-2][k-2]) +
						c1*(u2[i][j+1][k-2]-u2[i][j-1][k-2])   ) )
				) + c1*(
					mu[i][j][k+1]*met3[i][j][k+1]*met1[i][j][k+1]*(
						c2*(u1[i][j+2][k+1]-u1[i][j-2][k+1]) +
						c1*(u1[i][j+1][k+1]-u1[i][j-1][k+1]) )*stry[j-2]*strx[i]
					+ la[i][j][k+1]*met2[i][j][k+1]*met1[i][j][k+1]*(
						c2*(u2[i][j+2][k+1]-u2[i][j-2][k+1]) +
						c1*(u2[i][j+1][k+1]-u2[i][j-1][k+1]) )
					+ ( mu[i][j][k-1]*met3[i][j][k-1]*met1[i][j][k-1]*(
							c2*(u1[i][j+2][k-1]-u1[i][j-2][k-1]) +
							c1*(u1[i][j+1][k-1]-u1[i][j-1][k-1]) )*stry[j]*strx[i]
						+ la[i][j][k-1]*met2[i][j][k-1]*met1[i][j][k-1]*(
							c2*(u2[i][j+2][k-1]-u2[i][j-2][k-1]) +
							c1*(u2[i][j+1][k-1]-u2[i][j-1][k-1]) ) ) );

		}
	} 
}

extern "C" void host_code (float *h_r1, float *h_u1, float *h_u2, float *h_u3,  float *h_mu, float *h_la, float *h_met1, float *h_met2, float *h_met3, float *h_met4, float *h_strx, float *h_stry, float c1, float c2, int N) {
	float *r1;
	hipMalloc (&r1, sizeof(float)*N*N*N);
	check_error ("Failed to allocate device memory for r1\n");
	hipMemcpy (r1, h_r1, sizeof(float)*N*N*N, hipMemcpyHostToDevice);
	float *u1;
	hipMalloc (&u1, sizeof(float)*N*N*N);
	check_error ("Failed to allocate device memory for u1\n");
	hipMemcpy (u1, h_u1, sizeof(float)*N*N*N, hipMemcpyHostToDevice);
	float *u2;
	hipMalloc (&u2, sizeof(float)*N*N*N);
	check_error ("Failed to allocate device memory for u2\n");
	hipMemcpy (u2, h_u2, sizeof(float)*N*N*N, hipMemcpyHostToDevice);
	float *u3;
	hipMalloc (&u3, sizeof(float)*N*N*N);
	check_error ("Failed to allocate device memory for u3\n");
	hipMemcpy (u3, h_u3, sizeof(float)*N*N*N, hipMemcpyHostToDevice);
	float *mu;
	hipMalloc (&mu, sizeof(float)*N*N*N);
	check_error ("Failed to allocate device memory for mu\n");
	hipMemcpy (mu, h_mu, sizeof(float)*N*N*N, hipMemcpyHostToDevice);
	float *la;
	hipMalloc (&la, sizeof(float)*N*N*N);
	check_error ("Failed to allocate device memory for la\n");
	hipMemcpy (la, h_la, sizeof(float)*N*N*N, hipMemcpyHostToDevice);
	float *met1;
	hipMalloc (&met1, sizeof(float)*N*N*N);
	check_error ("Failed to allocate device memory for met1\n");
	hipMemcpy (met1, h_met1, sizeof(float)*N*N*N, hipMemcpyHostToDevice);
	float *met2;
	hipMalloc (&met2, sizeof(float)*N*N*N);
	check_error ("Failed to allocate device memory for met2\n");
	hipMemcpy (met2, h_met2, sizeof(float)*N*N*N, hipMemcpyHostToDevice);
	float *met3;
	hipMalloc (&met3, sizeof(float)*N*N*N);
	check_error ("Failed to allocate device memory for met3\n");
	hipMemcpy (met3, h_met3, sizeof(float)*N*N*N, hipMemcpyHostToDevice);
	float *met4;
	hipMalloc (&met4, sizeof(float)*N*N*N);
	check_error ("Failed to allocate device memory for met4\n");
	hipMemcpy (met4, h_met4, sizeof(float)*N*N*N, hipMemcpyHostToDevice);
	float *strx;
	hipMalloc (&strx, sizeof(float)*N);
	check_error ("Failed to allocate device memory for strx\n");
	hipMemcpy (strx, h_strx, sizeof(float)*N, hipMemcpyHostToDevice);
	float *stry;
	hipMalloc (&stry, sizeof(float)*N);
	check_error ("Failed to allocate device memory for stry\n");
	hipMemcpy (stry, h_stry, sizeof(float)*N, hipMemcpyHostToDevice);

	dim3 blockconfig (32, 8);
	dim3 gridconfig (ceil(N, blockconfig.x), ceil(N, blockconfig.y), 1);

	curvi <<<gridconfig, blockconfig>>> (r1, u1, u2, u3, mu, la, met1, met2, met3, met4, strx, stry, c1, c2, N);
	hipMemcpy (h_r1, r1, sizeof(float)*N*N*N, hipMemcpyDeviceToHost);
}

	.text
	.file	"kernel.hip"
	.globl	_Z11check_errorPKc              # -- Begin function _Z11check_errorPKc
	.type	_Z11check_errorPKc,@function
_Z11check_errorPKc:                     # @_Z11check_errorPKc
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movq	%rdi, %rbx
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB0_2
# %bb.1:
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.LBB0_2:
	.cfi_def_cfa_offset 16
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$.L.str, %edi
	movq	%rbx, %rsi
	movq	%rax, %rdx
	xorl	%eax, %eax
	callq	printf
	movl	$-1, %edi
	callq	exit
.Lfunc_end0:
	.size	_Z11check_errorPKc, .Lfunc_end0-_Z11check_errorPKc
	.cfi_endproc
                                        # -- End function
	.globl	_Z20__device_stub__curviPfS_S_S_S_S_S_S_S_S_S_S_ffi # -- Begin function _Z20__device_stub__curviPfS_S_S_S_S_S_S_S_S_S_S_ffi
	.type	_Z20__device_stub__curviPfS_S_S_S_S_S_S_S_S_S_S_ffi,@function
_Z20__device_stub__curviPfS_S_S_S_S_S_S_S_S_S_S_ffi: # @_Z20__device_stub__curviPfS_S_S_S_S_S_S_S_S_S_S_ffi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$240, %rsp
	.cfi_def_cfa_offset 288
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	72(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	64(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	56(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	48(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	32(%rsp), %r8
	movq	%r9, (%r8)
	leaq	12(%rsp), %r9
	movss	%xmm0, (%r9)
	leaq	8(%rsp), %r10
	movss	%xmm1, (%r10)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	288(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	296(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	328(%rsp), %rax
	movq	%rax, 88(%rbx)
	movq	%r9, 96(%rbx)
	movq	%r10, 104(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z5curviPfS_S_S_S_S_S_S_S_S_S_S_ffi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$256, %rsp                      # imm = 0x100
	.cfi_adjust_cfa_offset -256
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z20__device_stub__curviPfS_S_S_S_S_S_S_S_S_S_S_ffi, .Lfunc_end1-_Z20__device_stub__curviPfS_S_S_S_S_S_S_S_S_S_S_ffi
	.cfi_endproc
                                        # -- End function
	.globl	host_code                       # -- Begin function host_code
	.type	host_code,@function
host_code:                              # @host_code
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$152, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movss	%xmm1, 12(%rsp)                 # 4-byte Spill
	movss	%xmm0, 8(%rsp)                  # 4-byte Spill
	movq	%r9, 48(%rsp)                   # 8-byte Spill
	movq	%r8, 40(%rsp)                   # 8-byte Spill
	movq	%rcx, 32(%rsp)                  # 8-byte Spill
	movq	%rdx, 24(%rsp)                  # 8-byte Spill
	movq	%rsi, %r15
	movq	%rdi, %rbx
	movslq	256(%rsp), %rbp
	leaq	(,%rbp,4), %r12
	movq	%rbp, %r14
	imulq	%rbp, %r14
	imulq	%r12, %r14
	leaq	16(%rsp), %r13
	movq	%r13, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	$.L.str.1, %edi
	callq	_Z11check_errorPKc
	movq	(%r13), %rdi
	movq	%rbx, 56(%rsp)                  # 8-byte Spill
	movq	%rbx, %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	144(%rsp), %r13
	movq	%r13, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	$.L.str.2, %edi
	callq	_Z11check_errorPKc
	movq	(%r13), %rdi
	movq	%r15, %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	136(%rsp), %r15
	movq	%r15, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	$.L.str.3, %edi
	callq	_Z11check_errorPKc
	movq	(%r15), %rdi
	movq	24(%rsp), %rsi                  # 8-byte Reload
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	128(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	$.L.str.4, %edi
	callq	_Z11check_errorPKc
	movq	(%rbx), %rdi
	movq	32(%rsp), %rsi                  # 8-byte Reload
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	120(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	$.L.str.5, %edi
	callq	_Z11check_errorPKc
	movq	(%rbx), %rdi
	movq	40(%rsp), %rsi                  # 8-byte Reload
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	112(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	$.L.str.6, %edi
	callq	_Z11check_errorPKc
	movq	(%rbx), %rdi
	movq	48(%rsp), %rsi                  # 8-byte Reload
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	104(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	$.L.str.7, %edi
	callq	_Z11check_errorPKc
	movq	(%rbx), %rdi
	movq	208(%rsp), %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	96(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	$.L.str.8, %edi
	callq	_Z11check_errorPKc
	movq	(%rbx), %rdi
	movq	216(%rsp), %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	88(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	$.L.str.9, %edi
	callq	_Z11check_errorPKc
	movq	(%rbx), %rdi
	movq	224(%rsp), %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	80(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movl	$.L.str.10, %edi
	callq	_Z11check_errorPKc
	movq	(%rbx), %rdi
	movq	232(%rsp), %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	72(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movl	$.L.str.11, %edi
	callq	_Z11check_errorPKc
	movq	(%rbx), %rdi
	movq	240(%rsp), %rsi
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	64(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movl	$.L.str.12, %edi
	callq	_Z11check_errorPKc
	movq	(%rbx), %rdi
	movq	248(%rsp), %rsi
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	%ebp, %eax
	andl	$31, %eax
	movl	%ebp, %ecx
	shrl	$5, %ecx
	cmpl	$1, %eax
	sbbl	$-1, %ecx
	movl	%ebp, %eax
	andl	$7, %eax
	movl	%ebp, %edi
	shrl	$3, %edi
	cmpl	$1, %eax
	sbbl	$-1, %edi
	shlq	$32, %rdi
	orq	%rcx, %rdi
	movabsq	$34359738400, %rdx              # imm = 0x800000020
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_2
# %bb.1:
	movq	16(%rsp), %rdi
	movq	144(%rsp), %rsi
	movq	136(%rsp), %rdx
	movq	128(%rsp), %rcx
	movq	120(%rsp), %r8
	movq	112(%rsp), %r9
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movss	16(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movss	20(%rsp), %xmm1                 # 4-byte Reload
                                        # xmm1 = mem[0],zero,zero,zero
	pushq	%rbp
	.cfi_adjust_cfa_offset 8
	pushq	80(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	96(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	112(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	128(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	144(%rsp)
	.cfi_adjust_cfa_offset 8
	pushq	160(%rsp)
	.cfi_adjust_cfa_offset 8
	callq	_Z20__device_stub__curviPfS_S_S_S_S_S_S_S_S_S_S_ffi
	addq	$64, %rsp
	.cfi_adjust_cfa_offset -64
.LBB2_2:
	movq	16(%rsp), %rsi
	movq	56(%rsp), %rdi                  # 8-byte Reload
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	addq	$152, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	host_code, .Lfunc_end2-host_code
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z5curviPfS_S_S_S_S_S_S_S_S_S_S_ffi, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"CUDA error : %s, %s\n"
	.size	.L.str, 21

	.type	_Z5curviPfS_S_S_S_S_S_S_S_S_S_S_ffi,@object # @_Z5curviPfS_S_S_S_S_S_S_S_S_S_S_ffi
	.section	.rodata,"a",@progbits
	.globl	_Z5curviPfS_S_S_S_S_S_S_S_S_S_S_ffi
	.p2align	3, 0x0
_Z5curviPfS_S_S_S_S_S_S_S_S_S_S_ffi:
	.quad	_Z20__device_stub__curviPfS_S_S_S_S_S_S_S_S_S_S_ffi
	.size	_Z5curviPfS_S_S_S_S_S_S_S_S_S_S_ffi, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"Failed to allocate device memory for r1\n"
	.size	.L.str.1, 41

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Failed to allocate device memory for u1\n"
	.size	.L.str.2, 41

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Failed to allocate device memory for u2\n"
	.size	.L.str.3, 41

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"Failed to allocate device memory for u3\n"
	.size	.L.str.4, 41

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"Failed to allocate device memory for mu\n"
	.size	.L.str.5, 41

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"Failed to allocate device memory for la\n"
	.size	.L.str.6, 41

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"Failed to allocate device memory for met1\n"
	.size	.L.str.7, 43

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"Failed to allocate device memory for met2\n"
	.size	.L.str.8, 43

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"Failed to allocate device memory for met3\n"
	.size	.L.str.9, 43

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"Failed to allocate device memory for met4\n"
	.size	.L.str.10, 43

	.type	.L.str.11,@object               # @.str.11
.L.str.11:
	.asciz	"Failed to allocate device memory for strx\n"
	.size	.L.str.11, 43

	.type	.L.str.12,@object               # @.str.12
.L.str.12:
	.asciz	"Failed to allocate device memory for stry\n"
	.size	.L.str.12, 43

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z5curviPfS_S_S_S_S_S_S_S_S_S_S_ffi"
	.size	.L__unnamed_1, 36

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z20__device_stub__curviPfS_S_S_S_S_S_S_S_S_S_S_ffi
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z5curviPfS_S_S_S_S_S_S_S_S_S_S_ffi
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z5curviPfS_S_S_S_S_S_S_S_S_S_S_ffi ; -- Begin function _Z5curviPfS_S_S_S_S_S_S_S_S_S_S_ffi
	.globl	_Z5curviPfS_S_S_S_S_S_S_S_S_S_S_ffi
	.p2align	8
	.type	_Z5curviPfS_S_S_S_S_S_S_S_S_S_S_ffi,@function
_Z5curviPfS_S_S_S_S_S_S_S_S_S_S_ffi:    ; @_Z5curviPfS_S_S_S_S_S_S_S_S_S_S_ffi
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x7c
	s_load_b128 s[28:31], s[0:1], 0x60
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s2, 0xffff
	s_lshr_b32 s2, s2, 16
	s_mul_i32 s14, s14, s3
	s_mul_i32 s15, s15, s2
	s_max_i32 s2, s14, 0
	s_max_i32 s3, s15, 0
	v_add_nc_u32_e32 v6, s2, v1
	v_add_nc_u32_e32 v4, s3, v0
	s_add_i32 s2, s30, -3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_min_u32_e32 v0, v6, v4
	v_max_i32_e32 v1, v4, v6
	v_cmp_lt_u32_e32 vcc_lo, 1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_i32_e64 s2, s2, v1
	s_and_b32 s2, s2, vcc_lo
	s_cmp_gt_i32 s30, 4
	s_cselect_b32 s3, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, s3, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_3
; %bb.1:                                ; %.lr.ph
	s_load_b256 s[12:19], s[0:1], 0x40
	v_dual_mov_b32 v7, 0 :: v_dual_add_nc_u32 v18, -2, v4
	v_add_nc_u32_e32 v12, 2, v6
	v_add_nc_u32_e32 v14, 1, v6
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_mov_b32 v15, v7 :: v_dual_add_nc_u32 v20, -1, v4
	v_mov_b32_e32 v5, v7
	v_lshlrev_b64 v[10:11], 2, v[6:7]
	v_mov_b32_e32 v13, v7
	v_lshl_add_u32 v7, s30, 1, v4
	v_add_nc_u32_e32 v19, 1, v4
	v_lshlrev_b64 v[0:1], 2, v[4:5]
	v_add_nc_u32_e32 v5, 2, v4
	s_mov_b64 s[2:3], 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[16:17], null, 0x4c0, v5, v[10:11]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v8, vcc_lo, s18, v0
	v_add_co_ci_u32_e32 v9, vcc_lo, s19, v1, vcc_lo
	s_add_i32 s18, s30, -4
	s_mul_i32 s19, s30, s30
	s_clause 0x1
	global_load_b128 v[0:3], v[8:9], off offset:-8
	global_load_b32 v51, v[8:9], off offset:8
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b256 s[20:27], s[0:1], 0x20
	v_mad_u64_u32 v[8:9], null, 0x4c0, v4, 0
	v_mad_u64_u32 v[4:5], null, s30, v7, v[6:7]
	v_mad_i64_i32 v[5:6], null, 0x4c0, v18, v[10:11]
	s_add_u32 s0, s16, 16
	s_addc_u32 s1, s17, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v21, vcc_lo, v8, v10
	v_add_co_ci_u32_e32 v22, vcc_lo, v9, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v23, vcc_lo, v21, -4
	v_add_co_ci_u32_e32 v24, vcc_lo, -1, v22, vcc_lo
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v52, vcc_lo, s10, v23
	v_add_co_ci_u32_e32 v53, vcc_lo, s11, v24, vcc_lo
	v_add_co_u32 v54, vcc_lo, s8, v16
	v_add_co_ci_u32_e32 v55, vcc_lo, s9, v17, vcc_lo
	v_mad_u64_u32 v[16:17], null, 0x4c0, v19, v[10:11]
	v_mad_i64_i32 v[18:19], null, 0x4c0, v20, v[10:11]
	v_add_co_u32 v56, vcc_lo, s8, v5
	v_add_co_ci_u32_e32 v57, vcc_lo, s9, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_add_co_u32 v58, vcc_lo, s8, v16
	v_lshlrev_b64 v[5:6], 2, v[12:13]
	v_add_co_ci_u32_e32 v59, vcc_lo, s9, v17, vcc_lo
	v_add_co_u32 v60, vcc_lo, s8, v18
	v_add_co_ci_u32_e32 v61, vcc_lo, s9, v19, vcc_lo
	v_add_co_u32 v5, vcc_lo, v8, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, v9, v6, vcc_lo
	v_add_co_u32 v62, vcc_lo, s22, v21
	v_add_co_ci_u32_e32 v63, vcc_lo, s23, v22, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v64, vcc_lo, s6, v5
	v_add_co_ci_u32_e32 v65, vcc_lo, s7, v6, vcc_lo
	v_add_co_u32 v66, vcc_lo, s8, v5
	v_add_co_ci_u32_e32 v67, vcc_lo, s9, v6, vcc_lo
	v_add_co_u32 v7, vcc_lo, v21, -8
	v_add_co_ci_u32_e32 v10, vcc_lo, -1, v22, vcc_lo
	v_add_co_u32 v68, vcc_lo, s10, v5
	v_add_co_ci_u32_e32 v69, vcc_lo, s11, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_add_co_u32 v70, vcc_lo, s6, v7
	v_lshlrev_b64 v[5:6], 2, v[14:15]
	v_add_co_ci_u32_e32 v71, vcc_lo, s7, v10, vcc_lo
	v_add_co_u32 v72, vcc_lo, s8, v7
	v_add_co_ci_u32_e32 v73, vcc_lo, s9, v10, vcc_lo
	v_add_co_u32 v5, vcc_lo, v8, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, v9, v6, vcc_lo
	v_add_co_u32 v74, vcc_lo, s10, v7
	v_add_co_ci_u32_e32 v75, vcc_lo, s11, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v76, vcc_lo, s6, v5
	v_add_co_ci_u32_e32 v77, vcc_lo, s7, v6, vcc_lo
	v_add_co_u32 v78, vcc_lo, s8, v5
	v_add_co_ci_u32_e32 v79, vcc_lo, s9, v6, vcc_lo
	v_add_co_u32 v80, vcc_lo, s10, v5
	v_add_co_ci_u32_e32 v81, vcc_lo, s11, v6, vcc_lo
	v_add_co_u32 v82, vcc_lo, s6, v23
	v_add_co_ci_u32_e32 v83, vcc_lo, s7, v24, vcc_lo
	v_add_co_u32 v84, vcc_lo, s8, v23
	v_add_co_ci_u32_e32 v85, vcc_lo, s9, v24, vcc_lo
	v_add_co_u32 v86, vcc_lo, s8, v21
	v_add_co_ci_u32_e32 v87, vcc_lo, s9, v22, vcc_lo
	v_add_co_u32 v88, vcc_lo, s6, v21
	v_add_co_ci_u32_e32 v89, vcc_lo, s7, v22, vcc_lo
	v_add_co_u32 v90, vcc_lo, s14, v21
	v_add_co_ci_u32_e32 v91, vcc_lo, s15, v22, vcc_lo
	v_add_co_u32 v92, vcc_lo, s12, v21
	v_add_co_ci_u32_e32 v93, vcc_lo, s13, v22, vcc_lo
	v_add_co_u32 v94, vcc_lo, s24, v21
	v_add_co_ci_u32_e32 v95, vcc_lo, s25, v22, vcc_lo
	v_add_co_u32 v96, vcc_lo, s26, v21
	v_add_co_ci_u32_e32 v97, vcc_lo, s27, v22, vcc_lo
	v_add_co_u32 v98, vcc_lo, s20, v21
	v_add_co_ci_u32_e32 v99, vcc_lo, s21, v22, vcc_lo
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v27, vcc_lo, v98, s2
	v_add_co_ci_u32_e32 v28, vcc_lo, s3, v99, vcc_lo
	s_add_u32 s6, s0, -8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, 0xb5000, v27
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v28, vcc_lo
	s_addc_u32 s7, s1, -1
	s_add_u32 s8, s0, -16
	s_addc_u32 s9, s1, -1
	global_load_b32 v33, v[5:6], off offset:384
	v_add_co_u32 v5, vcc_lo, v94, s2
	v_add_co_ci_u32_e32 v6, vcc_lo, s3, v95, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, 0xb5000, v5
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v6, vcc_lo
	global_load_b32 v34, v[7:8], off offset:384
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v7, v33, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v11, v34, v7
	v_add_co_u32 v7, vcc_lo, v54, s2
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v55, vcc_lo
	v_add_co_u32 v9, vcc_lo, 0x169000, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v8, vcc_lo
	s_clause 0x1
	global_load_b32 v15, v[9:10], off
	global_load_b32 v16, v[7:8], off
	v_add_co_u32 v9, vcc_lo, 0x10e000, v7
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v8, vcc_lo
	v_add_co_u32 v7, vcc_lo, 0x5a000, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
	s_clause 0x1
	global_load_b32 v17, v[9:10], off offset:3072
	global_load_b32 v18, v[7:8], off offset:1024
	s_waitcnt vmcnt(0)
	v_dual_sub_f32 v12, v15, v16 :: v_dual_sub_f32 v7, v17, v18
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v13, s28, v7
	v_add_co_u32 v7, vcc_lo, 0xb3000, v27
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v28, vcc_lo
	global_load_b32 v35, v[7:8], off offset:3712
	v_add_co_u32 v7, vcc_lo, 0xb3000, v5
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v6, vcc_lo
	global_load_b32 v36, v[7:8], off offset:3712
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v7, v35, v36
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v13, s29, v12 :: v_dual_mul_f32 v12, v36, v7
	v_add_co_u32 v7, vcc_lo, v56, s2
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v57, vcc_lo
	v_add_co_u32 v9, vcc_lo, 0x169000, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v8, vcc_lo
	s_clause 0x1
	global_load_b32 v19, v[9:10], off
	global_load_b32 v20, v[7:8], off
	v_add_co_u32 v9, vcc_lo, 0x10e000, v7
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v8, vcc_lo
	v_add_co_u32 v7, vcc_lo, 0x5a000, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
	s_clause 0x1
	global_load_b32 v21, v[9:10], off offset:3072
	global_load_b32 v22, v[7:8], off offset:1024
	s_waitcnt vmcnt(2)
	v_sub_f32_e32 v14, v19, v20
	s_waitcnt vmcnt(0)
	v_dual_sub_f32 v16, v16, v20 :: v_dual_sub_f32 v7, v21, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v7, s28, v7
	v_fmac_f32_e32 v7, s29, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v23, v12, v7
	v_add_co_u32 v7, vcc_lo, 0xb4000, v27
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v28, vcc_lo
	v_fmac_f32_e32 v23, v11, v13
	v_add_co_u32 v11, vcc_lo, 0xb4000, v5
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v6, vcc_lo
	global_load_b32 v45, v[7:8], off offset:3264
	global_load_b32 v46, v[11:12], off offset:3264
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v9, v45, v46
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v24, v46, v9
	v_add_co_u32 v9, vcc_lo, v58, s2
	v_add_co_ci_u32_e32 v10, vcc_lo, s3, v59, vcc_lo
	v_add_co_u32 v13, vcc_lo, 0x169000, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v10, vcc_lo
	s_clause 0x1
	global_load_b32 v25, v[13:14], off
	global_load_b32 v26, v[9:10], off
	v_add_co_u32 v13, vcc_lo, 0x10e000, v9
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v10, vcc_lo
	v_add_co_u32 v9, vcc_lo, 0x5a000, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_clause 0x1
	global_load_b32 v30, v[13:14], off offset:3072
	global_load_b32 v37, v[9:10], off offset:1024
	global_load_b32 v49, v[7:8], off offset:832
	global_load_b32 v50, v[11:12], off offset:832
	s_waitcnt vmcnt(4)
	v_sub_f32_e32 v29, v25, v26
	s_waitcnt vmcnt(2)
	v_sub_f32_e32 v9, v30, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v31, s28, v9
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v9, v49, v50
	v_fmac_f32_e32 v31, s29, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v29, v50, v9
	v_add_co_u32 v9, vcc_lo, v60, s2
	v_add_co_ci_u32_e32 v10, vcc_lo, s3, v61, vcc_lo
	v_add_co_u32 v13, vcc_lo, 0x169000, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v10, vcc_lo
	s_clause 0x1
	global_load_b32 v32, v[13:14], off
	global_load_b32 v38, v[9:10], off
	v_add_co_u32 v13, vcc_lo, 0x10e000, v9
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v10, vcc_lo
	v_add_co_u32 v9, vcc_lo, 0x5a000, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	s_clause 0x1
	global_load_b32 v40, v[13:14], off offset:3072
	global_load_b32 v41, v[9:10], off offset:1024
	s_waitcnt vmcnt(2)
	v_sub_f32_e32 v39, v32, v38
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v9, v40, v41
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v9, s28, v9
	v_fmac_f32_e32 v9, s29, v39
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v9, v29, v9
	v_fmac_f32_e32 v9, v24, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v24, s28, v9
	v_add_co_u32 v9, vcc_lo, v62, s2
	v_add_co_ci_u32_e32 v10, vcc_lo, s3, v63, vcc_lo
	v_fmac_f32_e32 v24, s29, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v13, vcc_lo, 0x169000, v9
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v10, vcc_lo
	global_load_b32 v44, v[13:14], off
	v_add_co_u32 v13, vcc_lo, 0x169000, v5
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v6, vcc_lo
	global_load_b32 v112, v[13:14], off
	global_load_b32 v113, v[9:10], off
	global_load_b32 v114, v[5:6], off
	v_dual_sub_f32 v14, v15, v19 :: v_dual_sub_f32 v15, v25, v32
	v_sub_f32_e32 v19, v26, v38
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v15, s28, v15
	v_mul_f32_e32 v19, s28, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v15, s29, v14
	v_fmac_f32_e32 v19, s29, v16
	s_waitcnt vmcnt(0)
	v_dual_mul_f32 v13, v44, v112 :: v_dual_mul_f32 v14, v113, v114
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v13, v112, v13 :: v_dual_mul_f32 v14, v114, v14
	v_mul_f32_e32 v14, v19, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v14, v15, v13
	v_add_co_u32 v13, vcc_lo, 0x10e000, v9
	v_fmac_f32_e32 v24, s29, v14
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v10, vcc_lo
	global_load_b32 v31, v[13:14], off offset:3072
	v_add_co_u32 v13, vcc_lo, 0x10e000, v5
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v6, vcc_lo
	global_load_b32 v32, v[13:14], off offset:3072
	v_sub_f32_e32 v14, v30, v40
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v16, s28, v14 :: v_dual_mul_f32 v13, v31, v32
	v_mul_f32_e32 v15, v32, v13
	v_sub_f32_e32 v13, v17, v21
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v16, s29, v13
	v_add_co_u32 v13, vcc_lo, 0x5a000, v9
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v10, vcc_lo
	v_add_co_u32 v5, vcc_lo, 0x5a000, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
	global_load_b32 v29, v[13:14], off offset:1024
	v_sub_f32_e32 v13, v37, v41
	global_load_b64 v[37:38], v[7:8], off offset:2052
	global_load_b32 v30, v[5:6], off offset:1024
	v_dual_sub_f32 v6, v18, v22 :: v_dual_mul_f32 v13, s28, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v13, s29, v6
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v5, v29, v30
	v_mul_f32_e32 v5, v30, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v13, v5
	v_fmac_f32_e32 v5, v16, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v24, s28, v5
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[5:6], 2, v[4:5]
	v_add_nc_u32_e32 v4, s19, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v5, vcc_lo, s4, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	v_add_co_u32 v9, vcc_lo, 0xb4000, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v10, vcc_lo
	global_load_b32 v13, v[5:6], off
	v_add_co_u32 v23, vcc_lo, v96, s2
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v115, v13, v24
	v_add_co_ci_u32_e32 v24, vcc_lo, s3, v97, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_u32 v19, vcc_lo, 0xb4000, v23
	global_load_b64 v[13:14], v[9:10], off offset:2052
	v_add_co_ci_u32_e32 v20, vcc_lo, 0, v24, vcc_lo
	global_load_b64 v[15:16], v[19:20], off offset:2052
	s_waitcnt vmcnt(1)
	v_fma_f32 v17, 2.0, v38, v14
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v21, v17, v16
	global_load_b64 v[17:18], v[11:12], off offset:2052
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v39, v21, v18
	v_add_co_u32 v21, vcc_lo, v64, s2
	v_add_co_ci_u32_e32 v22, vcc_lo, s3, v65, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v25, vcc_lo, 0x169000, v21
	v_add_co_ci_u32_e32 v26, vcc_lo, 0, v22, vcc_lo
	s_clause 0x1
	global_load_b32 v116, v[25:26], off
	global_load_b32 v117, v[21:22], off
	v_add_co_u32 v25, vcc_lo, 0x10e000, v21
	v_add_co_ci_u32_e32 v26, vcc_lo, 0, v22, vcc_lo
	v_add_co_u32 v21, vcc_lo, 0x5a000, v21
	v_add_co_ci_u32_e32 v22, vcc_lo, 0, v22, vcc_lo
	global_load_b32 v118, v[25:26], off offset:3072
	s_load_b32 s6, s[6:7], 0x0
	global_load_b32 v119, v[21:22], off offset:1024
	v_add_co_u32 v25, vcc_lo, v92, s2
	v_add_co_ci_u32_e32 v26, vcc_lo, s3, v93, vcc_lo
	s_waitcnt vmcnt(0)
	v_dual_sub_f32 v40, v116, v117 :: v_dual_sub_f32 v21, v118, v119
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v21, s28, v21
	v_fmac_f32_e32 v21, s29, v40
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v21, v39, v21
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e32 v47, s6, v21
	v_add_co_u32 v21, vcc_lo, 0xb4000, v25
	v_add_co_ci_u32_e32 v22, vcc_lo, 0, v26, vcc_lo
	global_load_b64 v[39:40], v[21:22], off offset:2052
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v40, v38, v40
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v101, v18, v40
	v_add_co_u32 v40, vcc_lo, v66, s2
	v_add_co_ci_u32_e32 v41, vcc_lo, s3, v67, vcc_lo
	v_add_co_u32 v42, vcc_lo, 0x169000, v40
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v41, vcc_lo
	s_clause 0x1
	global_load_b32 v120, v[42:43], off
	global_load_b32 v121, v[40:41], off
	v_add_co_u32 v42, vcc_lo, 0x10e000, v40
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v41, vcc_lo
	v_add_co_u32 v40, vcc_lo, 0x5a000, v40
	v_add_co_ci_u32_e32 v41, vcc_lo, 0, v41, vcc_lo
	s_clause 0x1
	global_load_b32 v122, v[42:43], off offset:3072
	global_load_b32 v123, v[40:41], off offset:1024
	s_waitcnt vmcnt(2)
	v_sub_f32_e32 v48, v120, v121
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v40, v122, v123
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v40, s28, v40
	v_fmac_f32_e32 v40, s29, v48
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v100, v101, v40
	v_add_co_u32 v40, vcc_lo, v90, s2
	v_add_co_ci_u32_e32 v41, vcc_lo, s3, v91, vcc_lo
	v_fmac_f32_e32 v100, v2, v47
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v42, vcc_lo, 0xb4000, v40
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v41, vcc_lo
	v_add_co_u32 v102, vcc_lo, v68, s2
	v_add_co_ci_u32_e32 v103, vcc_lo, s3, v69, vcc_lo
	global_load_b64 v[47:48], v[42:43], off offset:2052
	v_add_co_u32 v104, vcc_lo, 0x169000, v102
	v_add_co_ci_u32_e32 v105, vcc_lo, 0, v103, vcc_lo
	s_clause 0x1
	global_load_b32 v124, v[104:105], off
	global_load_b32 v125, v[102:103], off
	v_add_co_u32 v104, vcc_lo, 0x10e000, v102
	v_add_co_ci_u32_e32 v105, vcc_lo, 0, v103, vcc_lo
	v_add_co_u32 v102, vcc_lo, 0x5a000, v102
	v_add_co_ci_u32_e32 v103, vcc_lo, 0, v103, vcc_lo
	s_clause 0x1
	global_load_b32 v126, v[104:105], off offset:3072
	global_load_b32 v127, v[102:103], off offset:1024
	global_load_b64 v[104:105], v[7:8], off offset:2040
	global_load_b64 v[7:8], v[9:10], off offset:2040
	global_load_b64 v[9:10], v[19:20], off offset:2040
	global_load_b64 v[11:12], v[11:12], off offset:2040
	v_mul_f32_e32 v14, v14, v16
	s_waitcnt vmcnt(8)
	v_mul_f32_e32 v38, v38, v48
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v38, v18, v38
	s_waitcnt vmcnt(6)
	v_sub_f32_e32 v48, v124, v125
	s_waitcnt vmcnt(4)
	v_sub_f32_e32 v102, v126, v127
	v_mul_f32_e32 v102, s28, v102
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v102, s29, v48
	v_mul_f32_e32 v38, v38, v102
	v_add_co_u32 v102, vcc_lo, v70, s2
	v_add_co_ci_u32_e32 v103, vcc_lo, s3, v71, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v100, v2, v38
	v_add_co_u32 v106, vcc_lo, 0x169000, v102
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v107, vcc_lo, 0, v103, vcc_lo
	s_waitcnt vmcnt(2)
	v_fma_f32 v38, 2.0, v104, v7
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v7, v7, v9
	s_clause 0x1
	global_load_b32 v128, v[106:107], off
	global_load_b32 v129, v[102:103], off
	v_add_co_u32 v106, vcc_lo, 0x10e000, v102
	v_add_co_ci_u32_e32 v107, vcc_lo, 0, v103, vcc_lo
	v_add_co_u32 v102, vcc_lo, 0x5a000, v102
	v_add_co_ci_u32_e32 v103, vcc_lo, 0, v103, vcc_lo
	global_load_b32 v130, v[106:107], off offset:3072
	v_add_co_u32 v108, vcc_lo, v72, s2
	global_load_b32 v131, v[102:103], off offset:1024
	global_load_b64 v[106:107], v[21:22], off offset:2040
	v_add_co_ci_u32_e32 v109, vcc_lo, s3, v73, vcc_lo
	v_add_co_u32 v110, vcc_lo, 0x169000, v108
	v_mul_f32_e32 v38, v38, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v111, vcc_lo, 0, v109, vcc_lo
	s_waitcnt vmcnt(5)
	v_dual_mul_f32 v14, v14, v18 :: v_dual_mul_f32 v7, v7, v11
	v_mul_f32_e32 v38, v38, v11
	s_waitcnt vmcnt(3)
	v_sub_f32_e32 v48, v128, v129
	s_waitcnt vmcnt(1)
	v_sub_f32_e32 v102, v130, v131
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v102, s28, v102
	v_fmac_f32_e32 v102, s29, v48
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v48, v104, v106
	s_clause 0x1
	global_load_b32 v106, v[110:111], off
	global_load_b32 v132, v[108:109], off
	v_add_co_u32 v110, vcc_lo, 0x10e000, v108
	v_add_co_ci_u32_e32 v111, vcc_lo, 0, v109, vcc_lo
	v_add_co_u32 v108, vcc_lo, 0x5a000, v108
	v_add_co_ci_u32_e32 v109, vcc_lo, 0, v109, vcc_lo
	global_load_b32 v133, v[110:111], off offset:3072
	global_load_b64 v[42:43], v[42:43], off offset:2040
	v_mul_f32_e32 v38, v38, v102
	global_load_b32 v134, v[108:109], off offset:1024
	v_add_co_u32 v108, vcc_lo, v74, s2
	v_add_co_ci_u32_e32 v109, vcc_lo, s3, v75, vcc_lo
	v_mul_f32_e32 v38, s6, v38
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v110, vcc_lo, 0x169000, v108
	v_add_co_ci_u32_e32 v111, vcc_lo, 0, v109, vcc_lo
	s_clause 0x1
	global_load_b32 v135, v[110:111], off
	global_load_b32 v136, v[108:109], off
	v_add_co_u32 v110, vcc_lo, 0x10e000, v108
	v_add_co_ci_u32_e32 v111, vcc_lo, 0, v109, vcc_lo
	v_add_co_u32 v108, vcc_lo, 0x5a000, v108
	v_add_co_ci_u32_e32 v109, vcc_lo, 0, v109, vcc_lo
	s_clause 0x1
	global_load_b32 v137, v[110:111], off offset:3072
	global_load_b32 v138, v[108:109], off offset:1024
	v_mul_f32_e32 v103, v11, v48
	v_add_co_u32 v108, vcc_lo, v76, s2
	v_add_co_ci_u32_e32 v109, vcc_lo, s3, v77, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v110, vcc_lo, 0x169000, v108
	v_add_co_ci_u32_e32 v111, vcc_lo, 0, v109, vcc_lo
	s_waitcnt vmcnt(7)
	v_sub_f32_e32 v48, v106, v132
	s_waitcnt vmcnt(4)
	v_sub_f32_e32 v102, v133, v134
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v102, s28, v102
	v_fmac_f32_e32 v102, s29, v48
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v48, v103, v102
	v_fmac_f32_e32 v48, v2, v38
	v_mul_f32_e32 v38, v104, v42
	s_waitcnt vmcnt(2)
	v_sub_f32_e32 v42, v135, v136
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v102, v137, v138
	v_mul_f32_e32 v38, v11, v38
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v102, s28, v102
	v_fmac_f32_e32 v102, s29, v42
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v38, v38, v102
	v_fmac_f32_e32 v48, v2, v38
	v_fma_f32 v38, 2.0, v37, v13
	s_clause 0x1
	global_load_b32 v139, v[110:111], off
	global_load_b32 v140, v[108:109], off
	v_add_co_u32 v110, vcc_lo, 0x10e000, v108
	v_add_co_ci_u32_e32 v111, vcc_lo, 0, v109, vcc_lo
	v_add_co_u32 v108, vcc_lo, 0x5a000, v108
	v_add_co_ci_u32_e32 v109, vcc_lo, 0, v109, vcc_lo
	global_load_b32 v110, v[110:111], off offset:3072
	v_add_f32_e32 v104, v100, v48
	s_load_b32 s7, s[0:1], 0x0
	global_load_b32 v111, v[108:109], off offset:1024
	v_mul_f32_e32 v38, v38, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v38, v38, v17
	s_waitcnt vmcnt(2)
	v_sub_f32_e32 v42, v139, v140
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v48, v110, v111
	v_mul_f32_e32 v48, s28, v48
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v48, s29, v42
	v_mul_f32_e32 v38, v38, v48
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v42, s7, v38
	v_mul_f32_e32 v38, v37, v39
	v_mul_f32_e32 v37, v37, v47
	v_mul_f32_e32 v102, v17, v38
	v_add_co_u32 v38, vcc_lo, v78, s2
	v_add_co_ci_u32_e32 v39, vcc_lo, s3, v79, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v108, vcc_lo, 0x169000, v38
	v_add_co_ci_u32_e32 v109, vcc_lo, 0, v39, vcc_lo
	s_clause 0x1
	global_load_b32 v141, v[108:109], off
	global_load_b32 v142, v[38:39], off
	v_add_co_u32 v108, vcc_lo, 0x10e000, v38
	v_add_co_ci_u32_e32 v109, vcc_lo, 0, v39, vcc_lo
	v_add_co_u32 v38, vcc_lo, 0x5a000, v38
	v_add_co_ci_u32_e32 v39, vcc_lo, 0, v39, vcc_lo
	s_clause 0x1
	global_load_b32 v108, v[108:109], off offset:3072
	global_load_b32 v39, v[38:39], off offset:1024
	s_waitcnt vmcnt(2)
	v_sub_f32_e32 v48, v141, v142
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v38, v108, v39
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v38, s28, v38
	v_fmac_f32_e32 v38, s29, v48
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v109, v102, v38
	v_dual_fmac_f32 v109, v2, v42 :: v_dual_mul_f32 v42, v17, v37
	v_add_co_u32 v37, vcc_lo, v80, s2
	v_add_co_ci_u32_e32 v38, vcc_lo, s3, v81, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v47, vcc_lo, 0x169000, v37
	v_add_co_ci_u32_e32 v48, vcc_lo, 0, v38, vcc_lo
	s_clause 0x1
	global_load_b32 v143, v[47:48], off
	global_load_b32 v144, v[37:38], off
	v_add_co_u32 v47, vcc_lo, 0x10e000, v37
	v_add_co_ci_u32_e32 v48, vcc_lo, 0, v38, vcc_lo
	v_add_co_u32 v37, vcc_lo, 0x5a000, v37
	v_add_co_ci_u32_e32 v38, vcc_lo, 0, v38, vcc_lo
	s_clause 0x1
	global_load_b32 v145, v[47:48], off offset:3072
	global_load_b32 v146, v[37:38], off offset:1024
	s_waitcnt vmcnt(0)
	v_dual_sub_f32 v100, v143, v144 :: v_dual_sub_f32 v37, v145, v146
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v37, s28, v37
	v_fmac_f32_e32 v37, s29, v100
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v37, v42, v37
	v_fmac_f32_e32 v109, v2, v37
	v_fma_f32 v37, 2.0, v105, v8
	v_mul_f32_e32 v8, v8, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v37, v37, v10 :: v_dual_mul_f32 v8, v8, v12
	v_mul_f32_e32 v42, v37, v12
	v_add_co_u32 v37, vcc_lo, v82, s2
	v_add_co_ci_u32_e32 v38, vcc_lo, s3, v83, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v47, vcc_lo, 0x169000, v37
	v_add_co_ci_u32_e32 v48, vcc_lo, 0, v38, vcc_lo
	s_clause 0x1
	global_load_b32 v147, v[47:48], off
	global_load_b32 v148, v[37:38], off
	v_add_co_u32 v47, vcc_lo, 0x10e000, v37
	v_add_co_ci_u32_e32 v48, vcc_lo, 0, v38, vcc_lo
	v_add_co_u32 v37, vcc_lo, 0x5a000, v37
	v_add_co_ci_u32_e32 v38, vcc_lo, 0, v38, vcc_lo
	global_load_b32 v149, v[47:48], off offset:3072
	s_load_b32 s7, s[8:9], 0x0
	global_load_b32 v150, v[37:38], off offset:1024
	s_waitcnt vmcnt(0)
	v_dual_sub_f32 v100, v147, v148 :: v_dual_sub_f32 v37, v149, v150
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v37, s28, v37
	v_fmac_f32_e32 v37, s29, v100
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v37, v42, v37
	s_waitcnt lgkmcnt(0)
	v_dual_mul_f32 v42, s7, v37 :: v_dual_mul_f32 v37, v105, v107
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v100, v12, v37
	v_add_co_u32 v37, vcc_lo, v84, s2
	v_add_co_ci_u32_e32 v38, vcc_lo, s3, v85, vcc_lo
	v_add_co_u32 v47, vcc_lo, 0x169000, v37
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v48, vcc_lo, 0, v38, vcc_lo
	s_clause 0x1
	global_load_b32 v107, v[47:48], off
	global_load_b32 v151, v[37:38], off
	v_add_co_u32 v47, vcc_lo, 0x10e000, v37
	v_add_co_ci_u32_e32 v48, vcc_lo, 0, v38, vcc_lo
	v_add_co_u32 v37, vcc_lo, 0x5a000, v37
	v_add_co_ci_u32_e32 v38, vcc_lo, 0, v38, vcc_lo
	s_clause 0x1
	global_load_b32 v47, v[47:48], off offset:3072
	global_load_b32 v48, v[37:38], off offset:1024
	s_waitcnt vmcnt(2)
	v_sub_f32_e32 v152, v107, v151
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v37, v47, v48
	v_sub_f32_e32 v47, v108, v47
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v37, s28, v37
	v_mul_f32_e32 v47, s28, v47
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v37, s29, v152
	v_dual_mul_f32 v152, v100, v37 :: v_dual_mul_f32 v37, v105, v43
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v152, v2, v42 :: v_dual_mul_f32 v105, v12, v37
	v_add_co_u32 v37, vcc_lo, v52, s2
	v_add_co_ci_u32_e32 v38, vcc_lo, s3, v53, vcc_lo
	v_add_co_u32 v42, vcc_lo, 0x169000, v37
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v38, vcc_lo
	s_clause 0x1
	global_load_b32 v153, v[42:43], off
	global_load_b32 v154, v[37:38], off
	v_add_co_u32 v42, vcc_lo, 0x10e000, v37
	v_add_co_ci_u32_e32 v43, vcc_lo, 0, v38, vcc_lo
	v_add_co_u32 v37, vcc_lo, 0x5a000, v37
	v_add_co_ci_u32_e32 v38, vcc_lo, 0, v38, vcc_lo
	s_clause 0x1
	global_load_b32 v42, v[42:43], off offset:3072
	global_load_b32 v43, v[37:38], off offset:1024
	s_waitcnt vmcnt(2)
	v_sub_f32_e32 v155, v153, v154
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v37, v42, v43
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v37, s28, v37
	v_fmac_f32_e32 v37, s29, v155
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v37, v105, v37
	v_fmac_f32_e32 v152, v2, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v37, v109, v152
	v_mul_f32_e32 v37, s28, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v37, s29, v104
	v_add_f32_e32 v104, v115, v37
	v_add_co_u32 v37, vcc_lo, 0x169000, v27
	v_add_co_ci_u32_e32 v38, vcc_lo, 0, v28, vcc_lo
	global_load_b32 v37, v[37:38], off
	s_waitcnt vmcnt(0)
	v_fma_f32 v105, 2.0, v37, v44
	v_add_co_u32 v37, vcc_lo, 0x169000, v23
	v_add_co_ci_u32_e32 v38, vcc_lo, 0, v24, vcc_lo
	global_load_b32 v37, v[37:38], off
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v37, v37, v105
	v_dual_sub_f32 v105, v139, v147 :: v_dual_sub_f32 v38, v116, v128
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v37, v112, v37
	v_mul_f32_e32 v105, s28, v105
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v105, s29, v38
	v_mul_f32_e32 v105, v105, v37
	v_add_co_u32 v37, vcc_lo, 0x169000, v25
	v_add_co_ci_u32_e32 v38, vcc_lo, 0, v26, vcc_lo
	global_load_b32 v37, v[37:38], off
	v_sub_f32_e32 v38, v120, v106
	v_sub_f32_e32 v106, v141, v107
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v106, s28, v106
	s_waitcnt vmcnt(0)
	v_dual_fmac_f32 v106, s29, v38 :: v_dual_mul_f32 v37, v44, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v37, v112, v37
	v_mul_f32_e32 v37, v106, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v106, v2, v37
	v_add_co_u32 v37, vcc_lo, 0x169000, v40
	v_add_co_ci_u32_e32 v38, vcc_lo, 0, v41, vcc_lo
	v_dual_fmac_f32 v106, s6, v105 :: v_dual_sub_f32 v105, v142, v151
	global_load_b32 v37, v[37:38], off
	v_dual_sub_f32 v38, v124, v135 :: v_dual_mul_f32 v105, s28, v105
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v37, v44, v37
	v_sub_f32_e32 v44, v143, v153
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v44, s28, v44 :: v_dual_mul_f32 v37, v112, v37
	v_fmac_f32_e32 v44, s29, v38
	global_load_b32 v38, v[23:24], off
	v_fmac_f32_e32 v106, v44, v37
	global_load_b32 v37, v[27:28], off
	v_sub_f32_e32 v44, v140, v148
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v44, s28, v44
	s_waitcnt vmcnt(0)
	v_fma_f32 v37, 2.0, v37, v113
	v_mul_f32_e32 v37, v38, v37
	v_sub_f32_e32 v38, v117, v129
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v37, v114, v37 :: v_dual_fmac_f32 v44, s29, v38
	global_load_b32 v38, v[25:26], off
	v_dual_mul_f32 v37, v44, v37 :: v_dual_sub_f32 v44, v121, v132
	v_fmac_f32_e32 v105, s29, v44
	v_sub_f32_e32 v44, v125, v136
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v38, v113, v38
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v38, v114, v38
	v_mul_f32_e32 v38, v105, v38
	v_sub_f32_e32 v105, v144, v154
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v105, s28, v105 :: v_dual_mul_f32 v38, v2, v38
	v_dual_fmac_f32 v105, s29, v44 :: v_dual_fmac_f32 v38, s6, v37
	global_load_b32 v37, v[40:41], off
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v37, v113, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v37, v114, v37
	v_fmac_f32_e32 v38, v105, v37
	v_add_co_u32 v37, vcc_lo, 0x10e000, v27
	s_delay_alu instid0(VALU_DEP_2)
	v_add_f32_e32 v44, v106, v38
	v_add_co_ci_u32_e32 v38, vcc_lo, 0, v28, vcc_lo
	global_load_b32 v37, v[37:38], off offset:3072
	s_waitcnt vmcnt(0)
	v_fma_f32 v105, 2.0, v37, v31
	v_add_co_u32 v37, vcc_lo, 0x10e000, v23
	v_add_co_ci_u32_e32 v38, vcc_lo, 0, v24, vcc_lo
	global_load_b32 v37, v[37:38], off offset:3072
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v37, v37, v105
	v_sub_f32_e32 v105, v110, v149
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v37, v32, v37 :: v_dual_sub_f32 v38, v118, v130
	v_mul_f32_e32 v105, s28, v105
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v105, s29, v38
	v_mul_f32_e32 v105, v105, v37
	v_add_co_u32 v37, vcc_lo, 0x10e000, v25
	v_add_co_ci_u32_e32 v38, vcc_lo, 0, v26, vcc_lo
	global_load_b32 v37, v[37:38], off offset:3072
	v_sub_f32_e32 v38, v122, v133
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v47, s29, v38
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v37, v31, v37
	v_mul_f32_e32 v37, v32, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v37, v47, v37
	v_mul_f32_e32 v47, v2, v37
	v_add_co_u32 v37, vcc_lo, 0x10e000, v40
	v_add_co_ci_u32_e32 v38, vcc_lo, 0, v41, vcc_lo
	v_add_co_u32 v27, vcc_lo, 0x5a000, v27
	v_add_co_ci_u32_e32 v28, vcc_lo, 0, v28, vcc_lo
	global_load_b32 v37, v[37:38], off offset:3072
	global_load_b32 v27, v[27:28], off offset:1024
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v31, v31, v37
	v_sub_f32_e32 v37, v145, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v31, v32, v31 :: v_dual_sub_f32 v32, v126, v137
	v_mul_f32_e32 v37, s28, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v37, s29, v32
	v_dual_sub_f32 v32, v39, v48 :: v_dual_fmac_f32 v47, s6, v105
	v_dual_mul_f32 v32, s28, v32 :: v_dual_fmac_f32 v47, v37, v31
	s_waitcnt vmcnt(0)
	v_fma_f32 v31, 2.0, v27, v29
	v_add_co_u32 v27, vcc_lo, 0x5a000, v23
	v_add_co_ci_u32_e32 v28, vcc_lo, 0, v24, vcc_lo
	global_load_b32 v27, v[27:28], off offset:1024
	v_sub_f32_e32 v28, v119, v131
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v27, v27, v31
	v_sub_f32_e32 v31, v111, v150
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v27, v30, v27
	v_mul_f32_e32 v31, s28, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v31, s29, v28
	v_mul_f32_e32 v31, v31, v27
	v_add_co_u32 v27, vcc_lo, 0x5a000, v25
	v_add_co_ci_u32_e32 v28, vcc_lo, 0, v26, vcc_lo
	global_load_b32 v27, v[27:28], off offset:1024
	v_sub_f32_e32 v28, v123, v134
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v32, s29, v28 :: v_dual_mul_f32 v27, v29, v27
	v_mul_f32_e32 v27, v30, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v27, v32, v27
	v_mul_f32_e32 v32, v2, v27
	v_add_co_u32 v27, vcc_lo, 0x5a000, v40
	v_add_co_ci_u32_e32 v28, vcc_lo, 0, v41, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v32, s6, v31
	global_load_b32 v27, v[27:28], off offset:1024
	s_waitcnt vmcnt(0)
	v_dual_sub_f32 v28, v127, v138 :: v_dual_mul_f32 v27, v29, v27
	v_sub_f32_e32 v29, v146, v43
	v_mul_f32_e32 v27, v30, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v29, s28, v29
	v_fmac_f32_e32 v29, s29, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v32, v29, v27
	v_add_f32_e32 v27, v47, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v27, s28, v27
	v_fmac_f32_e32 v27, s29, v44
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v104, v2, v27
	v_add_co_u32 v27, vcc_lo, 0xb5000, v25
	v_add_co_ci_u32_e32 v28, vcc_lo, 0, v26, vcc_lo
	v_add_co_u32 v43, vcc_lo, v88, s2
	v_add_co_ci_u32_e32 v44, vcc_lo, s3, v89, vcc_lo
	global_load_b32 v27, v[27:28], off offset:384
	v_add_co_u32 v28, vcc_lo, 0xb5000, v43
	v_add_co_ci_u32_e32 v29, vcc_lo, 0, v44, vcc_lo
	s_clause 0x1
	global_load_b64 v[31:32], v[28:29], off offset:388
	global_load_b64 v[29:30], v[28:29], off offset:376
	s_waitcnt vmcnt(2)
	v_mul_f32_e32 v27, v33, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v27, v34, v27
	s_waitcnt vmcnt(0)
	v_dual_sub_f32 v37, v31, v30 :: v_dual_sub_f32 v28, v32, v29
	v_mul_f32_e32 v37, s28, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v37, s29, v28
	v_mul_f32_e32 v27, v27, v37
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v37, v3, v27
	v_add_co_u32 v27, vcc_lo, 0xb5000, v23
	v_add_co_ci_u32_e32 v28, vcc_lo, 0, v24, vcc_lo
	v_add_co_u32 v47, vcc_lo, v86, s2
	v_add_co_ci_u32_e32 v48, vcc_lo, s3, v87, vcc_lo
	global_load_b32 v27, v[27:28], off offset:384
	s_add_u32 s2, s2, 0x5a400
	s_addc_u32 s3, s3, 0
	s_add_i32 s18, s18, -1
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_cmp_lg_u32 s18, 0
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v27, v33, v27
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v38, v34, v27
	v_add_co_u32 v27, vcc_lo, 0xb5000, v47
	v_add_co_ci_u32_e32 v28, vcc_lo, 0, v48, vcc_lo
	s_clause 0x1
	global_load_b64 v[33:34], v[27:28], off offset:388
	global_load_b64 v[27:28], v[27:28], off offset:376
	v_add_co_u32 v25, vcc_lo, 0xb3000, v25
	v_add_co_ci_u32_e32 v26, vcc_lo, 0, v26, vcc_lo
	global_load_b32 v25, v[25:26], off offset:3712
	s_waitcnt vmcnt(1)
	v_dual_sub_f32 v40, v33, v28 :: v_dual_sub_f32 v39, v34, v27
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v40, s28, v40 :: v_dual_mul_f32 v25, v35, v25
	v_dual_fmac_f32 v40, s29, v39 :: v_dual_mul_f32 v41, v36, v25
	v_add_co_u32 v25, vcc_lo, 0xb3000, v43
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v105, v38, v40
	v_add_co_ci_u32_e32 v26, vcc_lo, 0, v44, vcc_lo
	v_add_co_u32 v23, vcc_lo, 0xb3000, v23
	v_fmac_f32_e32 v105, s6, v37
	s_clause 0x1
	global_load_b64 v[39:40], v[25:26], off offset:3716
	global_load_b64 v[37:38], v[25:26], off offset:3704
	v_add_co_ci_u32_e32 v24, vcc_lo, 0, v24, vcc_lo
	global_load_b32 v23, v[23:24], off offset:3712
	s_waitcnt vmcnt(2)
	v_sub_f32_e32 v32, v32, v40
	s_waitcnt vmcnt(1)
	v_dual_sub_f32 v26, v39, v38 :: v_dual_sub_f32 v25, v40, v37
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v26, s28, v26 :: v_dual_mul_f32 v23, v35, v23
	v_dual_fmac_f32 v26, s29, v25 :: v_dual_mul_f32 v35, v36, v23
	v_add_co_u32 v23, vcc_lo, 0xb3000, v47
	v_add_co_ci_u32_e32 v24, vcc_lo, 0, v48, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v25, v41, v26
	v_mul_f32_e32 v106, v2, v25
	s_clause 0x1
	global_load_b64 v[41:42], v[23:24], off offset:3716
	global_load_b64 v[25:26], v[23:24], off offset:3704
	s_waitcnt vmcnt(1)
	v_sub_f32_e32 v16, v34, v42
	s_waitcnt vmcnt(0)
	v_dual_sub_f32 v24, v41, v26 :: v_dual_sub_f32 v23, v42, v25
	v_dual_sub_f32 v9, v27, v25 :: v_dual_sub_f32 v10, v28, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v24, s28, v24
	v_fmac_f32_e32 v24, s29, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v23, v35, v24
	v_fmac_f32_e32 v23, s6, v106
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v109, v105, v23
	v_add_co_u32 v105, vcc_lo, 0xb4000, v43
	v_add_co_ci_u32_e32 v106, vcc_lo, 0, v44, vcc_lo
	global_load_b32 v23, v[21:22], off offset:3264
	s_clause 0x1
	global_load_b64 v[43:44], v[105:106], off offset:3268
	global_load_b64 v[35:36], v[105:106], off offset:3256
	s_waitcnt vmcnt(2)
	v_mul_f32_e32 v23, v45, v23
	s_waitcnt vmcnt(0)
	v_dual_sub_f32 v107, v43, v36 :: v_dual_sub_f32 v24, v44, v35
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v23, v46, v23
	v_mul_f32_e32 v107, s28, v107
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v107, s29, v24
	v_mul_f32_e32 v23, v23, v107
	v_add_co_u32 v107, vcc_lo, 0xb4000, v47
	v_add_co_ci_u32_e32 v108, vcc_lo, 0, v48, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v110, v1, v23
	global_load_b32 v23, v[19:20], off offset:3264
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v23, v45, v23
	v_mul_f32_e32 v111, v46, v23
	s_clause 0x1
	global_load_b64 v[45:46], v[107:108], off offset:3268
	global_load_b64 v[23:24], v[107:108], off offset:3256
	global_load_b32 v21, v[21:22], off offset:832
	s_waitcnt vmcnt(1)
	v_dual_sub_f32 v48, v45, v24 :: v_dual_sub_f32 v47, v46, v23
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v21, v49, v21 :: v_dual_mul_f32 v48, s28, v48
	v_fmac_f32_e32 v48, s29, v47
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v111, v111, v48
	v_dual_fmac_f32 v111, s6, v110 :: v_dual_mul_f32 v110, v50, v21
	s_clause 0x1
	global_load_b64 v[47:48], v[105:106], off offset:836
	global_load_b64 v[21:22], v[105:106], off offset:824
	global_load_b32 v19, v[19:20], off offset:832
	s_waitcnt vmcnt(2)
	v_sub_f32_e32 v40, v44, v48
	s_waitcnt vmcnt(1)
	v_dual_sub_f32 v106, v47, v22 :: v_dual_sub_f32 v105, v48, v21
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v19, v49, v19 :: v_dual_mul_f32 v40, s28, v40
	v_mul_f32_e32 v106, s28, v106
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v40, s29, v32
	v_fmac_f32_e32 v106, s29, v105
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mul_f32 v32, v101, v40 :: v_dual_mul_f32 v105, v110, v106
	v_mul_f32_e32 v106, v50, v19
	s_clause 0x1
	global_load_b64 v[49:50], v[107:108], off offset:836
	global_load_b64 v[19:20], v[107:108], off offset:824
	v_dual_mul_f32 v32, v32, v51 :: v_dual_mul_f32 v105, v2, v105
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v32, s6, v32
	s_waitcnt vmcnt(0)
	v_dual_sub_f32 v18, v46, v50 :: v_dual_sub_f32 v11, v23, v19
	v_sub_f32_e32 v108, v49, v20
	v_sub_f32_e32 v12, v24, v20
	v_dual_mul_f32 v18, s28, v18 :: v_dual_mul_f32 v11, s28, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v108, s28, v108
	v_dual_mul_f32 v12, s28, v12 :: v_dual_sub_f32 v107, v50, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v18, s29, v16
	v_sub_f32_e32 v16, v35, v21
	v_dual_fmac_f32 v11, s29, v9 :: v_dual_fmac_f32 v12, s29, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v9, v31, v39 :: v_dual_fmac_f32 v32, v14, v18
	v_sub_f32_e32 v14, v29, v37
	v_dual_mul_f32 v16, s28, v16 :: v_dual_mul_f32 v7, v7, v11
	v_sub_f32_e32 v11, v43, v47
	v_fmac_f32_e32 v108, s29, v107
	v_mul_f32_e32 v8, v8, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v16, s29, v14 :: v_dual_mul_f32 v11, s28, v11
	v_mul_f32_e32 v106, v106, v108
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v14, v103, v16 :: v_dual_fmac_f32 v11, s29, v9
	v_fmac_f32_e32 v106, s6, v105
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v14, v2, v14
	v_mul_f32_e32 v9, v102, v11
	v_mul_f32_e32 v11, v13, v15
	v_sub_f32_e32 v13, v33, v41
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_fmac_f32 v7, s6, v14 :: v_dual_sub_f32 v14, v45, v49
	v_mul_f32_e32 v9, v9, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v11, v11, v17
	v_dual_add_f32 v7, v7, v32 :: v_dual_mul_f32 v14, s28, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v9, s6, v9
	v_dual_fmac_f32 v14, s29, v13 :: v_dual_sub_f32 v13, v36, v22
	v_add_f32_e32 v105, v111, v106
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v9, v11, v14
	v_sub_f32_e32 v11, v30, v38
	v_mul_f32_e32 v13, s28, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v13, s29, v11
	v_mul_f32_e32 v11, v100, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v11, v2, v11
	v_dual_mul_f32 v105, s28, v105 :: v_dual_fmac_f32 v8, s6, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v8, v8, v9
	v_dual_fmac_f32 v105, s29, v109 :: v_dual_mul_f32 v8, s28, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v104, v104, v105
	v_fmac_f32_e32 v8, s29, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v7, v104, v8
	global_store_b32 v[5:6], v7, off
	s_cbranch_scc1 .LBB0_2
.LBB0_3:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z5curviPfS_S_S_S_S_S_S_S_S_S_S_ffi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 368
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 156
		.amdhsa_next_free_sgpr 32
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z5curviPfS_S_S_S_S_S_S_S_S_S_S_ffi, .Lfunc_end0-_Z5curviPfS_S_S_S_S_S_S_S_S_S_S_ffi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 6236
; NumSgprs: 34
; NumVgprs: 156
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 19
; NumSGPRsForWavesPerEU: 34
; NumVGPRsForWavesPerEU: 156
; Occupancy: 9
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         80
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         88
        .size:           8
        .value_kind:     global_buffer
      - .offset:         96
        .size:           4
        .value_kind:     by_value
      - .offset:         100
        .size:           4
        .value_kind:     by_value
      - .offset:         104
        .size:           4
        .value_kind:     by_value
      - .offset:         112
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         116
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         120
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         124
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         126
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         128
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         130
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         132
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         134
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         152
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         160
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         168
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         176
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 368
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z5curviPfS_S_S_S_S_S_S_S_S_S_S_ffi
    .private_segment_fixed_size: 0
    .sgpr_count:     34
    .sgpr_spill_count: 0
    .symbol:         _Z5curviPfS_S_S_S_S_S_S_S_S_S_S_ffi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     156
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
