#include <cstddef>
#include <stdio.h>
#include <stdlib.h>
#include <cuda_runtime.h>
#include <time.h>

#define BLOCK_SIZE 32
#define BIG_BLOCK 64

const int INF = ((1 << 30) - 1);

__global__ void cal_phase1(int* Dist, int numOfVertex, int round){
    int newDist;
    int big_ty = threadIdx.y * 2;
    int big_tx = threadIdx.x * 2;
    int i = BIG_BLOCK * round + big_ty;
    int j = BIG_BLOCK * round + big_tx;

    __shared__ int smem_pivot_dist[BIG_BLOCK][BIG_BLOCK];
    smem_pivot_dist[big_ty][big_tx] = Dist[i * numOfVertex + j];
    smem_pivot_dist[big_ty + 1][big_tx] = Dist[(i + 1) * numOfVertex + j];
    smem_pivot_dist[big_ty][big_tx + 1] = Dist[i * numOfVertex + j + 1];
    smem_pivot_dist[big_ty + 1][big_tx + 1] = Dist[(i + 1) * numOfVertex + j + 1];
    __syncthreads();

    #pragma unroll
    for(int k = 0; k < BIG_BLOCK; k++){
        newDist = smem_pivot_dist[big_ty][k] + smem_pivot_dist[k][big_tx];
        if(newDist < smem_pivot_dist[big_ty][big_tx]){
           smem_pivot_dist[big_ty][big_tx] = newDist;
        }
        newDist = smem_pivot_dist[big_ty + 1][k] + smem_pivot_dist[k][big_tx];
        if(newDist < smem_pivot_dist[big_ty + 1][big_tx]){
            smem_pivot_dist[big_ty + 1][big_tx] = newDist;
        }
        newDist = smem_pivot_dist[big_ty][k] + smem_pivot_dist[k][big_tx + 1];
        if(newDist < smem_pivot_dist[big_ty][big_tx + 1]){
           smem_pivot_dist[big_ty][big_tx + 1] = newDist;
        }
        newDist = smem_pivot_dist[big_ty + 1][k] + smem_pivot_dist[k][big_tx + 1];
        if(newDist < smem_pivot_dist[big_ty + 1][big_tx + 1]){
           smem_pivot_dist[big_ty + 1][big_tx + 1] = newDist;
        }
    }
    __syncthreads();
    
    Dist[i * numOfVertex + j] = smem_pivot_dist[big_ty][big_tx];
    Dist[(i + 1) * numOfVertex + j] = smem_pivot_dist[big_ty + 1][big_tx];
    Dist[i * numOfVertex + j + 1] = smem_pivot_dist[big_ty][big_tx + 1];
    Dist[(i + 1) * numOfVertex + j + 1] = smem_pivot_dist[big_ty + 1][big_tx + 1];
    __syncthreads();
}

__global__ void cal_phase2(int* Dist, int numOfVertex, int round){
    if(blockIdx.x == round){
        return;
    }
    int big_ty = threadIdx.y * 2;
    int big_tx = threadIdx.x * 2;
    int i = BIG_BLOCK * round + big_ty;
    int j = BIG_BLOCK * round + big_tx;
    int newDist;
    int shortestDist00;
    int shortestDist01;
    int shortestDist10;
    int shortestDist11;
    __shared__ int smem_pivot_dist[BIG_BLOCK][BIG_BLOCK];
    __shared__ int smem_current_dist[BIG_BLOCK][BIG_BLOCK];
    // const int pivotBlockIndex = i * numOfVertex + j;
    // int currentBlockIndex;
    smem_pivot_dist[big_ty][big_tx] = Dist[i * numOfVertex + j];
    smem_pivot_dist[big_ty + 1][big_tx] = Dist[(i + 1) * numOfVertex + j];
    smem_pivot_dist[big_ty][big_tx + 1] = Dist[i * numOfVertex + j + 1];
    smem_pivot_dist[big_ty + 1][big_tx + 1] = Dist[(i + 1) * numOfVertex + j + 1];
    __syncthreads();

    // Row
    if(blockIdx.y == 0){
        i = BIG_BLOCK * round + big_ty;
        j = BIG_BLOCK * blockIdx.x + big_tx;
    }
    // Column
    else{
        i = BIG_BLOCK * blockIdx.x + big_ty;
        j = BIG_BLOCK * round + big_tx;
    }

    smem_current_dist[big_ty][big_tx] = Dist[i * numOfVertex + j];
    smem_current_dist[big_ty + 1][big_tx] = Dist[(i + 1) * numOfVertex + j];
    smem_current_dist[big_ty][big_tx + 1] = Dist[i * numOfVertex + j + 1];
    smem_current_dist[big_ty + 1][big_tx + 1] = Dist[(i + 1) * numOfVertex + j + 1];

    shortestDist00 = smem_current_dist[big_ty][big_tx];
    shortestDist10 = smem_current_dist[big_ty + 1][big_tx];
    shortestDist01 = smem_current_dist[big_ty][big_tx + 1];
    shortestDist11 = smem_current_dist[big_ty + 1][big_tx + 1];

    __syncthreads();

    // Row
    if(blockIdx.y == 0){
        #pragma unroll
        for(int k = 0; k < BIG_BLOCK; k++){
            newDist = smem_pivot_dist[big_ty][k] + smem_current_dist[k][big_tx];
            shortestDist00 = min(shortestDist00, newDist);
            newDist = smem_pivot_dist[big_ty + 1][k] + smem_current_dist[k][big_tx];
            shortestDist10 = min(shortestDist10, newDist);
            newDist = smem_pivot_dist[big_ty][k] + smem_current_dist[k][big_tx + 1];
            shortestDist01 = min(shortestDist01, newDist);
            newDist = smem_pivot_dist[big_ty + 1][k] + smem_current_dist[k][big_tx + 1];
            shortestDist11 = min(shortestDist11, newDist);
        }
    }
    // Column
    else{
        #pragma unroll
        for(int k = 0; k < BIG_BLOCK; k++){
            newDist = smem_current_dist[big_ty][k] + smem_pivot_dist[k][big_tx];
            shortestDist00 = min(shortestDist00, newDist);
            newDist = smem_current_dist[big_ty + 1][k] + smem_pivot_dist[k][big_tx];
            shortestDist10 = min(shortestDist10, newDist);
            newDist = smem_current_dist[big_ty][k] + smem_pivot_dist[k][big_tx + 1];
            shortestDist01 = min(shortestDist01, newDist);
            newDist = smem_current_dist[big_ty + 1][k] + smem_pivot_dist[k][big_tx + 1];
            shortestDist11 = min(shortestDist11, newDist);
        }
    }
    __syncthreads();
    Dist[i * numOfVertex + j] = shortestDist00;
    Dist[(i + 1) * numOfVertex + j] = shortestDist10;
    Dist[i * numOfVertex + j + 1] = shortestDist01;
    Dist[(i + 1) * numOfVertex + j + 1] = shortestDist11;
    __syncthreads();
}


__global__ void cal_phase3(int* Dist, int numOfVertex, int round){

    // if(blockIdx.x == round || blockIdx.y == round){
    //     return;
    // }
    int big_ty = threadIdx.y * 2;
    int big_tx = threadIdx.x * 2;
    int i, j;
    int newDist;
    int shortestDist00;
    int shortestDist01;
    int shortestDist10;
    int shortestDist11;
    __shared__ int smem_row_pivot_dist[BIG_BLOCK][BIG_BLOCK];
    __shared__ int smem_column_pivot_dist[BIG_BLOCK][BIG_BLOCK];
    // __shared__ int smem_current_dist[BIG_BLOCK][BIG_BLOCK];

    // Load row-pivot block
    i = BIG_BLOCK * round + big_ty;
    j = BIG_BLOCK * blockIdx.x + big_tx;
    smem_row_pivot_dist[big_ty][big_tx] = Dist[i * numOfVertex + j];
    smem_row_pivot_dist[big_ty + 1][big_tx] = Dist[(i + 1) * numOfVertex + j];
    smem_row_pivot_dist[big_ty][big_tx + 1] = Dist[i * numOfVertex + j + 1];
    smem_row_pivot_dist[big_ty + 1][big_tx + 1] = Dist[(i + 1) * numOfVertex + j + 1];
    
    // Load column-pivot block
    i = BIG_BLOCK * blockIdx.y + big_ty;
    j = BIG_BLOCK * round + big_tx;
    smem_column_pivot_dist[big_ty][big_tx] = Dist[i * numOfVertex + j];
    smem_column_pivot_dist[big_ty + 1][big_tx] = Dist[(i + 1) * numOfVertex + j];
    smem_column_pivot_dist[big_ty][big_tx + 1] = Dist[i * numOfVertex + j + 1];
    smem_column_pivot_dist[big_ty + 1][big_tx + 1] = Dist[(i + 1) * numOfVertex + j + 1];

    // Load current block
    i = BIG_BLOCK * blockIdx.y + big_ty;
    j = BIG_BLOCK * blockIdx.x + big_tx;

    shortestDist00 = Dist[i * numOfVertex + j];
    shortestDist10 = Dist[(i + 1) * numOfVertex + j];
    shortestDist01 = Dist[i * numOfVertex + j + 1];
    shortestDist11 = Dist[(i + 1) * numOfVertex + j + 1];

    __syncthreads();

    #pragma unroll
    for(int k = 0; k < BIG_BLOCK; k++){
        newDist = smem_column_pivot_dist[big_ty][k] + smem_row_pivot_dist[k][big_tx];
        shortestDist00 = min(shortestDist00, newDist);
        newDist = smem_column_pivot_dist[big_ty + 1][k] + smem_row_pivot_dist[k][big_tx];
        shortestDist10 = min(shortestDist10, newDist);
        newDist = smem_column_pivot_dist[big_ty][k] + smem_row_pivot_dist[k][big_tx + 1];
        shortestDist01 = min(shortestDist01, newDist);
        newDist = smem_column_pivot_dist[big_ty + 1][k] + smem_row_pivot_dist[k][big_tx + 1];
        shortestDist11 = min(shortestDist11, newDist);
    }

    __syncthreads();
    Dist[i * numOfVertex + j] = shortestDist00;
    Dist[(i + 1) * numOfVertex + j] = shortestDist10;
    Dist[i * numOfVertex + j + 1] = shortestDist01;
    Dist[(i + 1) * numOfVertex + j + 1] = shortestDist11;
    __syncthreads();
}

void block_FW(int* Dist, int numOfVertex) {
    cudaError_t status;
    int* devMem_Dist;
    //long long dataSize = (long long)numOfVertex * (long long)numOfVertex * sizeof(int);
    status = cudaMalloc((void**)&devMem_Dist, numOfVertex *numOfVertex * sizeof(int));
    if(status != cudaSuccess){
        exit(2);
    }
    status = cudaMemcpy(devMem_Dist, Dist, numOfVertex * numOfVertex * sizeof(int), cudaMemcpyHostToDevice);
    if(status != cudaSuccess){
        exit(3);
    }

    int round = numOfVertex / BIG_BLOCK; //(numOfVertex + BIG_BLOCK - 1) / BIG_BLOCK;
    
    dim3 gridSize_phase1(1, 1);
    dim3 blockSize_phase1(BLOCK_SIZE, BLOCK_SIZE);

    dim3 gridSize_phase2(numOfVertex / BIG_BLOCK, 2);
    dim3 blockSize_phase2(BLOCK_SIZE, BLOCK_SIZE);
    
    dim3 gridSize_phase3(numOfVertex / BIG_BLOCK, numOfVertex / BIG_BLOCK);
    dim3 blockSize_phase3(BLOCK_SIZE, BLOCK_SIZE);
    for (int r = 0; r < round; ++r) {
        // status = cudaMemcpy(Dist, devMem_Dist, numOfVertex *numOfVertex * sizeof(int), cudaMemcpyDeviceToHost);
        // printf("\n-------before round: %d--------------------\n", r);
        // for(int i = 0; i < numOfVertex; i++){
        //     for(int j = 0; j < numOfVertex; j++){
        //         if(Dist[i * numOfVertex + j] == INF){
        //             printf("INF ");
        //         }
        //         else
        //             printf("%d ", Dist[i * numOfVertex + j]);
        //     }
        //     printf("\n");
        // }
        /* Phase 1*/
        cal_phase1<<<gridSize_phase1, blockSize_phase1>>>(devMem_Dist, numOfVertex, r);
        // if(r == 0){
        //     status = cudaMemcpy(Dist, devMem_Dist, numOfVertex *numOfVertex * sizeof(int), cudaMemcpyDeviceToHost);
        //     printf("\n-------after p1--------------------\n", r);
        //     for(int i = 0; i < numOfVertex; i++){
        //         for(int j = 0; j < numOfVertex; j++){
        //             if(Dist[i * numOfVertex + j] == INF){
        //                 printf("INF ");
        //             }
        //             else
        //                 printf("%d ", Dist[i * numOfVertex + j]);
        //         }
        //         printf("\n");
        //     }
        // }
        /* Phase 2*/
        cal_phase2<<<gridSize_phase2, blockSize_phase2>>>(devMem_Dist, numOfVertex, r);
        // if(r == 0){
        //     status = cudaMemcpy(Dist, devMem_Dist, numOfVertex *numOfVertex * sizeof(int), cudaMemcpyDeviceToHost);
        //     printf("\n-------after p2--------------------\n", r);
        //     for(int i = 0; i < numOfVertex; i++){
        //         for(int j = 0; j < numOfVertex; j++){
        //             if(Dist[i * numOfVertex + j] == INF){
        //                 printf("INF ");
        //             }
        //             else
        //                 printf("%d ", Dist[i * numOfVertex + j]);
        //         }
        //         printf("\n");
        //     }
        // }
        /* Phase 3*/
        cal_phase3<<<gridSize_phase3, blockSize_phase3>>>(devMem_Dist, numOfVertex, r);
        // if(r == 0){
        //     status = cudaMemcpy(Dist, devMem_Dist, numOfVertex *numOfVertex * sizeof(int), cudaMemcpyDeviceToHost);
        //     printf("\n-------after p3--------------------\n", r);
        //     for(int i = 0; i < numOfVertex; i++){
        //         for(int j = 0; j < numOfVertex; j++){
        //             if(Dist[i * numOfVertex + j] == INF){
        //                 printf("INF ");
        //             }
        //             else
        //                 printf("%d ", Dist[i * numOfVertex + j]);
        //         }
        //         printf("\n");
        //     }
        // }
    }
    status = cudaDeviceSynchronize();
    if(status != cudaSuccess){
        exit(4);
    }
    status = cudaMemcpy(Dist, devMem_Dist, numOfVertex *numOfVertex * sizeof(int), cudaMemcpyDeviceToHost);
    if(status != cudaSuccess){
        exit(5);
    }
    cudaFree(devMem_Dist);
}


int main(int argc, char* argv[]) {
    int numOfVertex, original_numOfVertex, numOfEdge, numOfPadding;
    // ///////////////////////////////////////////////////////////////
    // Input
    // ///////////////////////////////////////////////////////////////
    FILE* inFile = fopen(argv[1], "rb");
    fread(&numOfVertex, sizeof(int), 1, inFile);
    printf("The number of vertices: %d\n", numOfVertex);
    fread(&numOfEdge, sizeof(int), 1, inFile);
    numOfPadding = 0;
    if(numOfVertex % BIG_BLOCK != 0)
        numOfPadding = BIG_BLOCK - (numOfVertex % BIG_BLOCK);
    original_numOfVertex = numOfVertex;
    numOfVertex += numOfPadding;
    int* Dist = (int*)malloc(numOfVertex * numOfVertex * sizeof(int));
    int* shortestDist = (int*)malloc(original_numOfVertex * original_numOfVertex * sizeof(int));
    for (int i = 0; i < numOfVertex; ++i) {
        for (int j = 0; j < numOfVertex; ++j) {
            if (i == j && i < numOfVertex - numOfPadding) {
                Dist[i * numOfVertex + j] = 0;
            } else {
                Dist[i * numOfVertex + j] = INF;
            }
        }
    }
    
    int pair[3];
    for (int i = 0; i < numOfEdge; ++i) {
        fread(pair, sizeof(int), 3, inFile);
        Dist[pair[0] * numOfVertex + pair[1]] = pair[2];
    }
    ///////////////////////////////////////////////////////
    //// print padding
    ///////////////////////////////////////////////////////
    // printf("N: %d pad: %d blocksize: %d\n",numOfVertex,numOfPadding, BIG_BLOCK);
    // printf("=======================================\n");
    // for(int i = 0; i < numOfVertex; i++){
    //     for(int j = 0; j < numOfVertex; j++){
    //         if(Dist[i * numOfVertex + j] == INF){
    //             printf("INF ");
    //         }
    //         else
    //             printf("%d ", Dist[i * numOfVertex + j]);
    //     }
    //     printf("\n");
    // }
    /////////////////////////////////////////////////////////////
    //Calculate
    /////////////////////////////////////////////////////////////
    block_FW(Dist, numOfVertex);


    FILE* outFile = fopen(argv[2], "wb");
    for (int i = 0; i < numOfVertex; ++i) {
        for (int j = 0; j < numOfVertex; ++j) {
            if (Dist[i * numOfVertex + j] >= INF) Dist[i * numOfVertex + j] = INF;
        }    
    }

    ///////////////////////////////////////////////////////////
    //print
    ///////////////////////////////////////////////////////////
    // printf("=======================================\n");
    // for(int i = 0; i < original_numOfVertex; i++){
    //     for(int j = 0; j < original_numOfVertex; j++){
    //         if(Dist[i * numOfVertex + j] == INF){
    //             printf("INF ");
    //         }
    //         else
    //             printf("%d ", Dist[i * numOfVertex + j]);
    //     }
    //     printf("\n");
    // }
    ///////////////////////////////////////////////////////
    //// print padding
    ///////////////////////////////////////////////////////
    // printf("=======================================\n");
    // for(int i = 0; i < numOfVertex; i++){
    //     for(int j = 0; j < numOfVertex; j++){
    //         if(Dist[i * numOfVertex + j] == INF){
    //             printf("INF ");
    //         }
    //         else
    //             printf("%d ", Dist[i * numOfVertex + j]);
    //     }
    //     printf("\n");
    // }

    for(int i = 0; i < original_numOfVertex; i++){
        for(int j = 0; j < original_numOfVertex; j++){
            shortestDist[i * original_numOfVertex + j] = Dist[i * numOfVertex + j];
        }
    }

    ////////////////////////////////////////////////////////////
    // Output
    ////////////////////////////////////////////////////////////
    fwrite(shortestDist, sizeof(int), original_numOfVertex * original_numOfVertex, outFile);
    fclose(inFile);
    fclose(outFile);
    delete[]Dist;
    delete[]shortestDist;
    return 0;
}



	.file	"tmpxft_0033d805_00000000-6_blocked-fw-bigblock.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2043:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2043:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z32__device_stub__Z10cal_phase1PiiiPiii
	.type	_Z32__device_stub__Z10cal_phase1PiiiPiii, @function
_Z32__device_stub__Z10cal_phase1PiiiPiii:
.LFB2065:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	32(%rsp), %rdi
	movl	%esi, 4(%rsp)
	leaq	44(%rsp), %rsi
	movl	%edx, (%rsp)
	leaq	16(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	24(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z10cal_phase1Piii(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 144
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L2:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2065:
	.size	_Z32__device_stub__Z10cal_phase1PiiiPiii, .-_Z32__device_stub__Z10cal_phase1PiiiPiii
	.globl	_Z10cal_phase1Piii
	.type	_Z10cal_phase1Piii, @function
_Z10cal_phase1Piii:
.LFB2066:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z10cal_phase1PiiiPiii
	.cfi_endproc
.LFE2066:
	.size	_Z10cal_phase1Piii, .-_Z10cal_phase1Piii
	.globl	_Z32__device_stub__Z10cal_phase2PiiiPiii
	.type	_Z32__device_stub__Z10cal_phase2PiiiPiii, @function
_Z32__device_stub__Z10cal_phase2PiiiPiii:
.LFB2067:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	32(%rsp), %rdi
	movl	%esi, 4(%rsp)
	leaq	44(%rsp), %rsi
	movl	%edx, (%rsp)
	leaq	16(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	24(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z10cal_phase2Piii(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 144
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L8:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2067:
	.size	_Z32__device_stub__Z10cal_phase2PiiiPiii, .-_Z32__device_stub__Z10cal_phase2PiiiPiii
	.globl	_Z10cal_phase2Piii
	.type	_Z10cal_phase2Piii, @function
_Z10cal_phase2Piii:
.LFB2068:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z10cal_phase2PiiiPiii
	.cfi_endproc
.LFE2068:
	.size	_Z10cal_phase2Piii, .-_Z10cal_phase2Piii
	.globl	_Z32__device_stub__Z10cal_phase3PiiiPiii
	.type	_Z32__device_stub__Z10cal_phase3PiiiPiii, @function
_Z32__device_stub__Z10cal_phase3PiiiPiii:
.LFB2069:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	32(%rsp), %rdi
	movl	%esi, 4(%rsp)
	leaq	44(%rsp), %rsi
	movl	%edx, (%rsp)
	leaq	16(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	24(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z10cal_phase3Piii(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 144
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L13:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2069:
	.size	_Z32__device_stub__Z10cal_phase3PiiiPiii, .-_Z32__device_stub__Z10cal_phase3PiiiPiii
	.globl	_Z10cal_phase3Piii
	.type	_Z10cal_phase3Piii, @function
_Z10cal_phase3Piii:
.LFB2070:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z10cal_phase3PiiiPiii
	.cfi_endproc
.LFE2070:
	.size	_Z10cal_phase3Piii, .-_Z10cal_phase3Piii
	.globl	_Z8block_FWPii
	.type	_Z8block_FWPii, @function
_Z8block_FWPii:
.LFB2039:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	movq	%rdi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movl	%esi, %ebp
	imull	%esi, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	movl	%esi, %ebx
	movslq	%ebp, %rbp
	subq	$96, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	salq	$2, %rbp
	leaq	8(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	movl	$2, %edi
	testl	%eax, %eax
	jne	.L30
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rdx
	movq	%r13, %rsi
	call	cudaMemcpy@PLT
	testl	%eax, %eax
	je	.L20
	movl	$3, %edi
.L30:
	call	exit@PLT
.L20:
	movl	%ebx, %eax
	movl	$64, %ecx
	movl	$1, 24(%rsp)
	xorl	%r12d, %r12d
	cltd
	movl	$1, 36(%rsp)
	idivl	%ecx
	movl	$1, 60(%rsp)
	movl	$1, 72(%rsp)
	movl	$1, 84(%rsp)
	movl	$2147483649, %edx
	addq	%rdx, %rdx
	movq	%rdx, 44(%rsp)
	movl	%eax, %r14d
	movabsq	$4294967297, %rax
	movq	%rax, 16(%rsp)
	movabsq	$137438953504, %rax
	movq	%rax, 28(%rsp)
	movl	%r14d, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	%r14d, 64(%rsp)
	movl	%r14d, 68(%rsp)
	movq	%rax, 76(%rsp)
.L21:
	cmpl	%r14d, %r12d
	jge	.L31
	movl	36(%rsp), %ecx
	movq	28(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	16(%rsp), %rdi
	movl	24(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L22
	movq	8(%rsp), %rdi
	movl	%r12d, %edx
	movl	%ebx, %esi
	call	_Z32__device_stub__Z10cal_phase1PiiiPiii
.L22:
	movl	60(%rsp), %ecx
	movq	52(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	40(%rsp), %rdi
	movl	48(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	movq	8(%rsp), %rdi
	movl	%r12d, %edx
	movl	%ebx, %esi
	call	_Z32__device_stub__Z10cal_phase2PiiiPiii
.L23:
	movl	84(%rsp), %ecx
	movq	76(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	64(%rsp), %rdi
	movl	72(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	movq	8(%rsp), %rdi
	movl	%r12d, %edx
	movl	%ebx, %esi
	call	_Z32__device_stub__Z10cal_phase3PiiiPiii
.L24:
	incl	%r12d
	jmp	.L21
.L31:
	call	cudaDeviceSynchronize@PLT
	movl	$4, %edi
	testl	%eax, %eax
	jne	.L30
	movq	8(%rsp), %rsi
	movq	%r13, %rdi
	movl	$2, %ecx
	movq	%rbp, %rdx
	call	cudaMemcpy@PLT
	movl	$5, %edi
	testl	%eax, %eax
	jne	.L30
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L28
	call	__stack_chk_fail@PLT
.L28:
	addq	$96, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2039:
	.size	_Z8block_FWPii, .-_Z8block_FWPii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"rb"
.LC1:
	.string	"The number of vertices: %d\n"
.LC2:
	.string	"wb"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2040:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rsi, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	movq	8(%rsi), %rdi
	leaq	.LC0(%rip), %rsi
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	call	fopen@PLT
	movl	$1, %ecx
	leaq	20(%rsp), %rdi
	movl	$4, %edx
	movq	%rax, %r8
	movl	$4, %esi
	movq	%rax, (%rsp)
	call	__fread_chk@PLT
	movl	20(%rsp), %edx
	movl	$2, %edi
	xorl	%eax, %eax
	leaq	.LC1(%rip), %rsi
	call	__printf_chk@PLT
	movq	(%rsp), %r8
	leaq	24(%rsp), %rdi
	movl	$1, %ecx
	movl	$4, %edx
	movl	$4, %esi
	call	__fread_chk@PLT
	movl	20(%rsp), %ebx
	movl	%ebx, %r15d
	andl	$63, %r15d
	je	.L33
	movl	%ebx, %eax
	movl	$64, %r15d
	cltd
	idivl	%r15d
	subl	%edx, %r15d
.L33:
	addl	%ebx, %r15d
	movl	%ebx, %r13d
	movl	%r15d, %edi
	imull	%ebx, %r13d
	movl	%r15d, 20(%rsp)
	imull	%r15d, %edi
	movslq	%r13d, %r13
	movslq	%edi, %rdi
	salq	$2, %rdi
	call	malloc@PLT
	leaq	0(,%r13,4), %rdi
	movq	%rax, %rbp
	call	malloc@PLT
	xorl	%esi, %esi
	xorl	%edx, %edx
	movq	%rax, %r12
.L34:
	cmpl	%edx, %r15d
	jle	.L64
	xorl	%ecx, %ecx
.L37:
	leal	(%rcx,%rsi), %eax
	cmpl	%ecx, %edx
	cltq
	jne	.L35
	cmpl	%edx, %ebx
	jle	.L35
	xorl	%edi, %edi
	movl	%edi, 0(%rbp,%rax,4)
	jmp	.L36
.L35:
	movl	$1073741823, 0(%rbp,%rax,4)
.L36:
	incl	%ecx
	cmpl	%ecx, %r15d
	jne	.L37
	incl	%edx
	addl	%r15d, %esi
	jmp	.L34
.L64:
	leaq	28(%rsp), %rax
	xorl	%r15d, %r15d
	movq	%rax, 8(%rsp)
.L38:
	cmpl	%r15d, 24(%rsp)
	jle	.L65
	movq	(%rsp), %r8
	movq	8(%rsp), %rdi
	movl	$4, %edx
	incl	%r15d
	movl	$3, %ecx
	movl	$12, %esi
	call	__fread_chk@PLT
	movl	28(%rsp), %eax
	movl	36(%rsp), %edx
	imull	20(%rsp), %eax
	addl	32(%rsp), %eax
	cltq
	movl	%edx, 0(%rbp,%rax,4)
	jmp	.L38
.L65:
	movl	20(%rsp), %esi
	movq	%rbp, %rdi
	call	_Z8block_FWPii
	movq	16(%r14), %rdi
	leaq	.LC2(%rip), %rsi
	call	fopen@PLT
	movslq	20(%rsp), %r8
	movq	%rbp, %rdi
	xorl	%ecx, %ecx
	movq	%rax, %r14
	movq	%rbp, %rax
	movq	%r8, %rsi
	salq	$2, %r8
.L40:
	cmpl	%ecx, %esi
	jle	.L66
	movq	%rdi, %rdx
	xorl	%r9d, %r9d
.L42:
	cmpl	$1073741822, (%rdx)
	jle	.L41
	movl	$1073741823, (%rdx)
.L41:
	incl	%r9d
	addq	$4, %rdx
	cmpl	%r9d, %esi
	jne	.L42
	incl	%ecx
	addq	%r8, %rdi
	jmp	.L40
.L66:
	movslq	%ebx, %r10
	leal	-1(%rbx), %ecx
	movq	%r12, %rdx
	xorl	%r9d, %r9d
	salq	$2, %r10
	leaq	4(,%rcx,4), %r11
.L43:
	cmpl	%r9d, %ebx
	jle	.L67
	movq	%rdx, %rdi
	movq	%rax, %rsi
	movq	%r11, %rcx
	incl	%r9d
	rep movsb
	addq	%r10, %rdx
	addq	%r8, %rax
	jmp	.L43
.L67:
	movq	%r14, %rcx
	movq	%r13, %rdx
	movl	$4, %esi
	movq	%r12, %rdi
	call	fwrite@PLT
	movq	(%rsp), %rdi
	call	fclose@PLT
	movq	%r14, %rdi
	call	fclose@PLT
	testq	%rbp, %rbp
	je	.L45
	movq	%rbp, %rdi
	call	_ZdaPv@PLT
.L45:
	movq	%r12, %rdi
	call	_ZdaPv@PLT
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L46
	call	__stack_chk_fail@PLT
.L46:
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2040:
	.size	main, .-main
	.section	.rodata.str1.1
.LC3:
	.string	"_Z10cal_phase3Piii"
.LC4:
	.string	"_Z10cal_phase2Piii"
.LC5:
	.string	"_Z10cal_phase1Piii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2072:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z10cal_phase3Piii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z10cal_phase2Piii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z10cal_phase1Piii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2072:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <cstddef>
#include <stdio.h>
#include <stdlib.h>
#include <hip/hip_runtime.h>
#include <time.h>

#define BLOCK_SIZE 32
#define BIG_BLOCK 64

const int INF = ((1 << 30) - 1);

__global__ void cal_phase1(int* Dist, int numOfVertex, int round){
    int newDist;
    int big_ty = threadIdx.y * 2;
    int big_tx = threadIdx.x * 2;
    int i = BIG_BLOCK * round + big_ty;
    int j = BIG_BLOCK * round + big_tx;

    __shared__ int smem_pivot_dist[BIG_BLOCK][BIG_BLOCK];
    smem_pivot_dist[big_ty][big_tx] = Dist[i * numOfVertex + j];
    smem_pivot_dist[big_ty + 1][big_tx] = Dist[(i + 1) * numOfVertex + j];
    smem_pivot_dist[big_ty][big_tx + 1] = Dist[i * numOfVertex + j + 1];
    smem_pivot_dist[big_ty + 1][big_tx + 1] = Dist[(i + 1) * numOfVertex + j + 1];
    __syncthreads();

    #pragma unroll
    for(int k = 0; k < BIG_BLOCK; k++){
        newDist = smem_pivot_dist[big_ty][k] + smem_pivot_dist[k][big_tx];
        if(newDist < smem_pivot_dist[big_ty][big_tx]){
           smem_pivot_dist[big_ty][big_tx] = newDist;
        }
        newDist = smem_pivot_dist[big_ty + 1][k] + smem_pivot_dist[k][big_tx];
        if(newDist < smem_pivot_dist[big_ty + 1][big_tx]){
            smem_pivot_dist[big_ty + 1][big_tx] = newDist;
        }
        newDist = smem_pivot_dist[big_ty][k] + smem_pivot_dist[k][big_tx + 1];
        if(newDist < smem_pivot_dist[big_ty][big_tx + 1]){
           smem_pivot_dist[big_ty][big_tx + 1] = newDist;
        }
        newDist = smem_pivot_dist[big_ty + 1][k] + smem_pivot_dist[k][big_tx + 1];
        if(newDist < smem_pivot_dist[big_ty + 1][big_tx + 1]){
           smem_pivot_dist[big_ty + 1][big_tx + 1] = newDist;
        }
    }
    __syncthreads();
    
    Dist[i * numOfVertex + j] = smem_pivot_dist[big_ty][big_tx];
    Dist[(i + 1) * numOfVertex + j] = smem_pivot_dist[big_ty + 1][big_tx];
    Dist[i * numOfVertex + j + 1] = smem_pivot_dist[big_ty][big_tx + 1];
    Dist[(i + 1) * numOfVertex + j + 1] = smem_pivot_dist[big_ty + 1][big_tx + 1];
    __syncthreads();
}

__global__ void cal_phase2(int* Dist, int numOfVertex, int round){
    if(blockIdx.x == round){
        return;
    }
    int big_ty = threadIdx.y * 2;
    int big_tx = threadIdx.x * 2;
    int i = BIG_BLOCK * round + big_ty;
    int j = BIG_BLOCK * round + big_tx;
    int newDist;
    int shortestDist00;
    int shortestDist01;
    int shortestDist10;
    int shortestDist11;
    __shared__ int smem_pivot_dist[BIG_BLOCK][BIG_BLOCK];
    __shared__ int smem_current_dist[BIG_BLOCK][BIG_BLOCK];
    // const int pivotBlockIndex = i * numOfVertex + j;
    // int currentBlockIndex;
    smem_pivot_dist[big_ty][big_tx] = Dist[i * numOfVertex + j];
    smem_pivot_dist[big_ty + 1][big_tx] = Dist[(i + 1) * numOfVertex + j];
    smem_pivot_dist[big_ty][big_tx + 1] = Dist[i * numOfVertex + j + 1];
    smem_pivot_dist[big_ty + 1][big_tx + 1] = Dist[(i + 1) * numOfVertex + j + 1];
    __syncthreads();

    // Row
    if(blockIdx.y == 0){
        i = BIG_BLOCK * round + big_ty;
        j = BIG_BLOCK * blockIdx.x + big_tx;
    }
    // Column
    else{
        i = BIG_BLOCK * blockIdx.x + big_ty;
        j = BIG_BLOCK * round + big_tx;
    }

    smem_current_dist[big_ty][big_tx] = Dist[i * numOfVertex + j];
    smem_current_dist[big_ty + 1][big_tx] = Dist[(i + 1) * numOfVertex + j];
    smem_current_dist[big_ty][big_tx + 1] = Dist[i * numOfVertex + j + 1];
    smem_current_dist[big_ty + 1][big_tx + 1] = Dist[(i + 1) * numOfVertex + j + 1];

    shortestDist00 = smem_current_dist[big_ty][big_tx];
    shortestDist10 = smem_current_dist[big_ty + 1][big_tx];
    shortestDist01 = smem_current_dist[big_ty][big_tx + 1];
    shortestDist11 = smem_current_dist[big_ty + 1][big_tx + 1];

    __syncthreads();

    // Row
    if(blockIdx.y == 0){
        #pragma unroll
        for(int k = 0; k < BIG_BLOCK; k++){
            newDist = smem_pivot_dist[big_ty][k] + smem_current_dist[k][big_tx];
            shortestDist00 = min(shortestDist00, newDist);
            newDist = smem_pivot_dist[big_ty + 1][k] + smem_current_dist[k][big_tx];
            shortestDist10 = min(shortestDist10, newDist);
            newDist = smem_pivot_dist[big_ty][k] + smem_current_dist[k][big_tx + 1];
            shortestDist01 = min(shortestDist01, newDist);
            newDist = smem_pivot_dist[big_ty + 1][k] + smem_current_dist[k][big_tx + 1];
            shortestDist11 = min(shortestDist11, newDist);
        }
    }
    // Column
    else{
        #pragma unroll
        for(int k = 0; k < BIG_BLOCK; k++){
            newDist = smem_current_dist[big_ty][k] + smem_pivot_dist[k][big_tx];
            shortestDist00 = min(shortestDist00, newDist);
            newDist = smem_current_dist[big_ty + 1][k] + smem_pivot_dist[k][big_tx];
            shortestDist10 = min(shortestDist10, newDist);
            newDist = smem_current_dist[big_ty][k] + smem_pivot_dist[k][big_tx + 1];
            shortestDist01 = min(shortestDist01, newDist);
            newDist = smem_current_dist[big_ty + 1][k] + smem_pivot_dist[k][big_tx + 1];
            shortestDist11 = min(shortestDist11, newDist);
        }
    }
    __syncthreads();
    Dist[i * numOfVertex + j] = shortestDist00;
    Dist[(i + 1) * numOfVertex + j] = shortestDist10;
    Dist[i * numOfVertex + j + 1] = shortestDist01;
    Dist[(i + 1) * numOfVertex + j + 1] = shortestDist11;
    __syncthreads();
}


__global__ void cal_phase3(int* Dist, int numOfVertex, int round){

    // if(blockIdx.x == round || blockIdx.y == round){
    //     return;
    // }
    int big_ty = threadIdx.y * 2;
    int big_tx = threadIdx.x * 2;
    int i, j;
    int newDist;
    int shortestDist00;
    int shortestDist01;
    int shortestDist10;
    int shortestDist11;
    __shared__ int smem_row_pivot_dist[BIG_BLOCK][BIG_BLOCK];
    __shared__ int smem_column_pivot_dist[BIG_BLOCK][BIG_BLOCK];
    // __shared__ int smem_current_dist[BIG_BLOCK][BIG_BLOCK];

    // Load row-pivot block
    i = BIG_BLOCK * round + big_ty;
    j = BIG_BLOCK * blockIdx.x + big_tx;
    smem_row_pivot_dist[big_ty][big_tx] = Dist[i * numOfVertex + j];
    smem_row_pivot_dist[big_ty + 1][big_tx] = Dist[(i + 1) * numOfVertex + j];
    smem_row_pivot_dist[big_ty][big_tx + 1] = Dist[i * numOfVertex + j + 1];
    smem_row_pivot_dist[big_ty + 1][big_tx + 1] = Dist[(i + 1) * numOfVertex + j + 1];
    
    // Load column-pivot block
    i = BIG_BLOCK * blockIdx.y + big_ty;
    j = BIG_BLOCK * round + big_tx;
    smem_column_pivot_dist[big_ty][big_tx] = Dist[i * numOfVertex + j];
    smem_column_pivot_dist[big_ty + 1][big_tx] = Dist[(i + 1) * numOfVertex + j];
    smem_column_pivot_dist[big_ty][big_tx + 1] = Dist[i * numOfVertex + j + 1];
    smem_column_pivot_dist[big_ty + 1][big_tx + 1] = Dist[(i + 1) * numOfVertex + j + 1];

    // Load current block
    i = BIG_BLOCK * blockIdx.y + big_ty;
    j = BIG_BLOCK * blockIdx.x + big_tx;

    shortestDist00 = Dist[i * numOfVertex + j];
    shortestDist10 = Dist[(i + 1) * numOfVertex + j];
    shortestDist01 = Dist[i * numOfVertex + j + 1];
    shortestDist11 = Dist[(i + 1) * numOfVertex + j + 1];

    __syncthreads();

    #pragma unroll
    for(int k = 0; k < BIG_BLOCK; k++){
        newDist = smem_column_pivot_dist[big_ty][k] + smem_row_pivot_dist[k][big_tx];
        shortestDist00 = min(shortestDist00, newDist);
        newDist = smem_column_pivot_dist[big_ty + 1][k] + smem_row_pivot_dist[k][big_tx];
        shortestDist10 = min(shortestDist10, newDist);
        newDist = smem_column_pivot_dist[big_ty][k] + smem_row_pivot_dist[k][big_tx + 1];
        shortestDist01 = min(shortestDist01, newDist);
        newDist = smem_column_pivot_dist[big_ty + 1][k] + smem_row_pivot_dist[k][big_tx + 1];
        shortestDist11 = min(shortestDist11, newDist);
    }

    __syncthreads();
    Dist[i * numOfVertex + j] = shortestDist00;
    Dist[(i + 1) * numOfVertex + j] = shortestDist10;
    Dist[i * numOfVertex + j + 1] = shortestDist01;
    Dist[(i + 1) * numOfVertex + j + 1] = shortestDist11;
    __syncthreads();
}

void block_FW(int* Dist, int numOfVertex) {
    hipError_t status;
    int* devMem_Dist;
    //long long dataSize = (long long)numOfVertex * (long long)numOfVertex * sizeof(int);
    status = hipMalloc((void**)&devMem_Dist, numOfVertex *numOfVertex * sizeof(int));
    if(status != hipSuccess){
        exit(2);
    }
    status = hipMemcpy(devMem_Dist, Dist, numOfVertex * numOfVertex * sizeof(int), hipMemcpyHostToDevice);
    if(status != hipSuccess){
        exit(3);
    }

    int round = numOfVertex / BIG_BLOCK; //(numOfVertex + BIG_BLOCK - 1) / BIG_BLOCK;
    
    dim3 gridSize_phase1(1, 1);
    dim3 blockSize_phase1(BLOCK_SIZE, BLOCK_SIZE);

    dim3 gridSize_phase2(numOfVertex / BIG_BLOCK, 2);
    dim3 blockSize_phase2(BLOCK_SIZE, BLOCK_SIZE);
    
    dim3 gridSize_phase3(numOfVertex / BIG_BLOCK, numOfVertex / BIG_BLOCK);
    dim3 blockSize_phase3(BLOCK_SIZE, BLOCK_SIZE);
    for (int r = 0; r < round; ++r) {
        // status = cudaMemcpy(Dist, devMem_Dist, numOfVertex *numOfVertex * sizeof(int), cudaMemcpyDeviceToHost);
        // printf("\n-------before round: %d--------------------\n", r);
        // for(int i = 0; i < numOfVertex; i++){
        //     for(int j = 0; j < numOfVertex; j++){
        //         if(Dist[i * numOfVertex + j] == INF){
        //             printf("INF ");
        //         }
        //         else
        //             printf("%d ", Dist[i * numOfVertex + j]);
        //     }
        //     printf("\n");
        // }
        /* Phase 1*/
        cal_phase1<<<gridSize_phase1, blockSize_phase1>>>(devMem_Dist, numOfVertex, r);
        // if(r == 0){
        //     status = cudaMemcpy(Dist, devMem_Dist, numOfVertex *numOfVertex * sizeof(int), cudaMemcpyDeviceToHost);
        //     printf("\n-------after p1--------------------\n", r);
        //     for(int i = 0; i < numOfVertex; i++){
        //         for(int j = 0; j < numOfVertex; j++){
        //             if(Dist[i * numOfVertex + j] == INF){
        //                 printf("INF ");
        //             }
        //             else
        //                 printf("%d ", Dist[i * numOfVertex + j]);
        //         }
        //         printf("\n");
        //     }
        // }
        /* Phase 2*/
        cal_phase2<<<gridSize_phase2, blockSize_phase2>>>(devMem_Dist, numOfVertex, r);
        // if(r == 0){
        //     status = cudaMemcpy(Dist, devMem_Dist, numOfVertex *numOfVertex * sizeof(int), cudaMemcpyDeviceToHost);
        //     printf("\n-------after p2--------------------\n", r);
        //     for(int i = 0; i < numOfVertex; i++){
        //         for(int j = 0; j < numOfVertex; j++){
        //             if(Dist[i * numOfVertex + j] == INF){
        //                 printf("INF ");
        //             }
        //             else
        //                 printf("%d ", Dist[i * numOfVertex + j]);
        //         }
        //         printf("\n");
        //     }
        // }
        /* Phase 3*/
        cal_phase3<<<gridSize_phase3, blockSize_phase3>>>(devMem_Dist, numOfVertex, r);
        // if(r == 0){
        //     status = cudaMemcpy(Dist, devMem_Dist, numOfVertex *numOfVertex * sizeof(int), cudaMemcpyDeviceToHost);
        //     printf("\n-------after p3--------------------\n", r);
        //     for(int i = 0; i < numOfVertex; i++){
        //         for(int j = 0; j < numOfVertex; j++){
        //             if(Dist[i * numOfVertex + j] == INF){
        //                 printf("INF ");
        //             }
        //             else
        //                 printf("%d ", Dist[i * numOfVertex + j]);
        //         }
        //         printf("\n");
        //     }
        // }
    }
    status = hipDeviceSynchronize();
    if(status != hipSuccess){
        exit(4);
    }
    status = hipMemcpy(Dist, devMem_Dist, numOfVertex *numOfVertex * sizeof(int), hipMemcpyDeviceToHost);
    if(status != hipSuccess){
        exit(5);
    }
    hipFree(devMem_Dist);
}


int main(int argc, char* argv[]) {
    int numOfVertex, original_numOfVertex, numOfEdge, numOfPadding;
    // ///////////////////////////////////////////////////////////////
    // Input
    // ///////////////////////////////////////////////////////////////
    FILE* inFile = fopen(argv[1], "rb");
    fread(&numOfVertex, sizeof(int), 1, inFile);
    printf("The number of vertices: %d\n", numOfVertex);
    fread(&numOfEdge, sizeof(int), 1, inFile);
    numOfPadding = 0;
    if(numOfVertex % BIG_BLOCK != 0)
        numOfPadding = BIG_BLOCK - (numOfVertex % BIG_BLOCK);
    original_numOfVertex = numOfVertex;
    numOfVertex += numOfPadding;
    int* Dist = (int*)malloc(numOfVertex * numOfVertex * sizeof(int));
    int* shortestDist = (int*)malloc(original_numOfVertex * original_numOfVertex * sizeof(int));
    for (int i = 0; i < numOfVertex; ++i) {
        for (int j = 0; j < numOfVertex; ++j) {
            if (i == j && i < numOfVertex - numOfPadding) {
                Dist[i * numOfVertex + j] = 0;
            } else {
                Dist[i * numOfVertex + j] = INF;
            }
        }
    }
    
    int pair[3];
    for (int i = 0; i < numOfEdge; ++i) {
        fread(pair, sizeof(int), 3, inFile);
        Dist[pair[0] * numOfVertex + pair[1]] = pair[2];
    }
    ///////////////////////////////////////////////////////
    //// print padding
    ///////////////////////////////////////////////////////
    // printf("N: %d pad: %d blocksize: %d\n",numOfVertex,numOfPadding, BIG_BLOCK);
    // printf("=======================================\n");
    // for(int i = 0; i < numOfVertex; i++){
    //     for(int j = 0; j < numOfVertex; j++){
    //         if(Dist[i * numOfVertex + j] == INF){
    //             printf("INF ");
    //         }
    //         else
    //             printf("%d ", Dist[i * numOfVertex + j]);
    //     }
    //     printf("\n");
    // }
    /////////////////////////////////////////////////////////////
    //Calculate
    /////////////////////////////////////////////////////////////
    block_FW(Dist, numOfVertex);


    FILE* outFile = fopen(argv[2], "wb");
    for (int i = 0; i < numOfVertex; ++i) {
        for (int j = 0; j < numOfVertex; ++j) {
            if (Dist[i * numOfVertex + j] >= INF) Dist[i * numOfVertex + j] = INF;
        }    
    }

    ///////////////////////////////////////////////////////////
    //print
    ///////////////////////////////////////////////////////////
    // printf("=======================================\n");
    // for(int i = 0; i < original_numOfVertex; i++){
    //     for(int j = 0; j < original_numOfVertex; j++){
    //         if(Dist[i * numOfVertex + j] == INF){
    //             printf("INF ");
    //         }
    //         else
    //             printf("%d ", Dist[i * numOfVertex + j]);
    //     }
    //     printf("\n");
    // }
    ///////////////////////////////////////////////////////
    //// print padding
    ///////////////////////////////////////////////////////
    // printf("=======================================\n");
    // for(int i = 0; i < numOfVertex; i++){
    //     for(int j = 0; j < numOfVertex; j++){
    //         if(Dist[i * numOfVertex + j] == INF){
    //             printf("INF ");
    //         }
    //         else
    //             printf("%d ", Dist[i * numOfVertex + j]);
    //     }
    //     printf("\n");
    // }

    for(int i = 0; i < original_numOfVertex; i++){
        for(int j = 0; j < original_numOfVertex; j++){
            shortestDist[i * original_numOfVertex + j] = Dist[i * numOfVertex + j];
        }
    }

    ////////////////////////////////////////////////////////////
    // Output
    ////////////////////////////////////////////////////////////
    fwrite(shortestDist, sizeof(int), original_numOfVertex * original_numOfVertex, outFile);
    fclose(inFile);
    fclose(outFile);
    delete[]Dist;
    delete[]shortestDist;
    return 0;
}



	.text
	.file	"blocked-fw-bigblock.hip"
	.globl	_Z25__device_stub__cal_phase1Piii # -- Begin function _Z25__device_stub__cal_phase1Piii
	.type	_Z25__device_stub__cal_phase1Piii,@function
_Z25__device_stub__cal_phase1Piii:      # @_Z25__device_stub__cal_phase1Piii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$96, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	movq	%rsp, %rsi
	movl	%edx, (%rsi)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10cal_phase1Piii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$112, %rsp
	.cfi_adjust_cfa_offset -112
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z25__device_stub__cal_phase1Piii, .Lfunc_end0-_Z25__device_stub__cal_phase1Piii
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__cal_phase2Piii # -- Begin function _Z25__device_stub__cal_phase2Piii
	.type	_Z25__device_stub__cal_phase2Piii,@function
_Z25__device_stub__cal_phase2Piii:      # @_Z25__device_stub__cal_phase2Piii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$96, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	movq	%rsp, %rsi
	movl	%edx, (%rsi)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10cal_phase2Piii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$112, %rsp
	.cfi_adjust_cfa_offset -112
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z25__device_stub__cal_phase2Piii, .Lfunc_end1-_Z25__device_stub__cal_phase2Piii
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__cal_phase3Piii # -- Begin function _Z25__device_stub__cal_phase3Piii
	.type	_Z25__device_stub__cal_phase3Piii,@function
_Z25__device_stub__cal_phase3Piii:      # @_Z25__device_stub__cal_phase3Piii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$96, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	movq	%rsp, %rsi
	movl	%edx, (%rsi)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10cal_phase3Piii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$112, %rsp
	.cfi_adjust_cfa_offset -112
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z25__device_stub__cal_phase3Piii, .Lfunc_end2-_Z25__device_stub__cal_phase3Piii
	.cfi_endproc
                                        # -- End function
	.globl	_Z8block_FWPii                  # -- Begin function _Z8block_FWPii
	.type	_Z8block_FWPii,@function
_Z8block_FWPii:                         # @_Z8block_FWPii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%esi, %r15d
	movq	%rdi, %r14
	movl	%esi, %ebx
	imull	%ebx, %ebx
	shlq	$2, %rbx
	movq	%rsp, %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	testl	%eax, %eax
	jne	.LBB3_14
# %bb.1:
	movq	(%rsp), %rdi
	movq	%r14, 8(%rsp)                   # 8-byte Spill
	movq	%r14, %rsi
	movq	%rbx, 16(%rsp)                  # 8-byte Spill
	movq	%rbx, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB3_15
# %bb.2:
	leal	63(%r15), %r13d
	testl	%r15d, %r15d
	cmovnsl	%r15d, %r13d
	cmpl	$64, %r15d
	jl	.LBB3_11
# %bb.3:                                # %.lr.ph.preheader
	sarl	$6, %r13d
	movq	%r13, %r12
	btsq	$33, %r12
	movq	%r13, %rbp
	shlq	$32, %rbp
	orq	%r13, %rbp
	xorl	%r14d, %r14d
	movabsq	$137438953504, %rbx             # imm = 0x2000000020
.LBB3_4:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_6
# %bb.5:                                #   in Loop: Header=BB3_4 Depth=1
	movq	(%rsp), %rdi
	movl	%r15d, %esi
	movl	%r14d, %edx
	callq	_Z25__device_stub__cal_phase1Piii
.LBB3_6:                                #   in Loop: Header=BB3_4 Depth=1
	movq	%r12, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_8
# %bb.7:                                #   in Loop: Header=BB3_4 Depth=1
	movq	(%rsp), %rdi
	movl	%r15d, %esi
	movl	%r14d, %edx
	callq	_Z25__device_stub__cal_phase2Piii
.LBB3_8:                                #   in Loop: Header=BB3_4 Depth=1
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%rbx, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_10
# %bb.9:                                #   in Loop: Header=BB3_4 Depth=1
	movq	(%rsp), %rdi
	movl	%r15d, %esi
	movl	%r14d, %edx
	callq	_Z25__device_stub__cal_phase3Piii
.LBB3_10:                               #   in Loop: Header=BB3_4 Depth=1
	incl	%r14d
	cmpl	%r14d, %r13d
	jne	.LBB3_4
.LBB3_11:                               # %._crit_edge
	callq	hipDeviceSynchronize
	testl	%eax, %eax
	jne	.LBB3_16
# %bb.12:
	movq	(%rsp), %rsi
	movq	8(%rsp), %rdi                   # 8-byte Reload
	movq	16(%rsp), %rdx                  # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB3_17
# %bb.13:
	movq	(%rsp), %rdi
	callq	hipFree
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB3_14:
	.cfi_def_cfa_offset 80
	movl	$2, %edi
	callq	exit
.LBB3_15:
	movl	$3, %edi
	callq	exit
.LBB3_16:
	movl	$4, %edi
	callq	exit
.LBB3_17:
	movl	$5, %edi
	callq	exit
.Lfunc_end3:
	.size	_Z8block_FWPii, .Lfunc_end3-_Z8block_FWPii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsi, 16(%rsp)                  # 8-byte Spill
	movq	8(%rsi), %rdi
	movl	$.L.str, %esi
	callq	fopen
	movq	%rax, %r13
	leaq	84(%rsp), %r14
	movl	$4, %esi
	movl	$1, %edx
	movq	%r14, %rdi
	movq	%rax, %rcx
	callq	fread
	movslq	(%r14), %r14
	xorl	%r12d, %r12d
	movl	$.L.str.1, %edi
	movl	%r14d, %esi
	xorl	%eax, %eax
	callq	printf
	leaq	32(%rsp), %rdi
	movl	$4, %esi
	movl	$1, %edx
	movq	%r13, %rcx
	callq	fread
	leal	63(%r14), %eax
	testq	%r14, %r14
	cmovnsl	%r14d, %eax
	andl	$-64, %eax
	movl	%r14d, %ecx
	subl	%eax, %ecx
	movl	$64, %ebp
	subl	%ecx, %ebp
	testl	%ecx, %ecx
	cmovel	%ecx, %ebp
	addl	%r14d, %ebp
	movl	%ebp, %edi
	imull	%edi, %edi
	shlq	$2, %rdi
	callq	malloc
	movq	%rax, %r15
	movl	%r14d, %eax
	imull	%eax, %eax
	movq	%rax, 56(%rsp)                  # 8-byte Spill
	leaq	(,%rax,4), %rdi
	callq	malloc
	movq	%rax, 72(%rsp)                  # 8-byte Spill
	movl	%ebp, %ebx
	testl	%ebp, %ebp
	jle	.LBB4_6
# %bb.1:                                # %.preheader73.lr.ph
	xorl	%eax, %eax
.LBB4_2:                                # %.lr.ph
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB4_3 Depth 2
	movl	%r12d, %ecx
	leaq	(%r15,%rcx,4), %rcx
	movl	%ebp, %edx
	imull	%eax, %edx
	leaq	(%r15,%rax,4), %rsi
	xorl	%edi, %edi
.LBB4_3:                                #   Parent Loop BB4_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	cmpq	%r14, %rax
	jge	.LBB4_24
# %bb.4:                                #   in Loop: Header=BB4_3 Depth=2
	cmpq	%rdi, %rax
	jne	.LBB4_24
# %bb.5:                                #   in Loop: Header=BB4_3 Depth=2
	movl	$0, (%rsi,%rdx,4)
	jmp	.LBB4_25
.LBB4_24:                               #   in Loop: Header=BB4_3 Depth=2
	movl	$1073741823, (%rcx,%rdi,4)      # imm = 0x3FFFFFFF
.LBB4_25:                               #   in Loop: Header=BB4_3 Depth=2
	incq	%rdi
	cmpq	%rdi, %rbx
	jne	.LBB4_3
# %bb.26:                               # %._crit_edge
                                        #   in Loop: Header=BB4_2 Depth=1
	incq	%rax
	addl	%ebp, %r12d
	cmpq	%rbx, %rax
	jne	.LBB4_2
.LBB4_6:                                # %._crit_edge76
	movl	%ebp, 12(%rsp)                  # 4-byte Spill
	movl	%r14d, %ebp
	movq	%r13, %r12
	movl	32(%rsp), %r13d
	testl	%r13d, %r13d
	jle	.LBB4_9
# %bb.7:
	movslq	12(%rsp), %rax                  # 4-byte Folded Reload
	movq	%rax, 24(%rsp)                  # 8-byte Spill
.LBB4_8:                                # =>This Inner Loop Header: Depth=1
	movl	$4, %esi
	movl	$3, %edx
	leaq	36(%rsp), %rdi
	movq	%r12, %rcx
	callq	fread
	movl	44(%rsp), %eax
	movslq	36(%rsp), %rcx
	imulq	24(%rsp), %rcx                  # 8-byte Folded Reload
	movslq	40(%rsp), %rdx
	addq	%rcx, %rdx
	movl	%eax, (%r15,%rdx,4)
	decl	%r13d
	jne	.LBB4_8
.LBB4_9:                                # %._crit_edge80
	movq	%r12, 64(%rsp)                  # 8-byte Spill
	movq	%r15, %rdi
	movl	12(%rsp), %r12d                 # 4-byte Reload
	movl	%r12d, %esi
	callq	_Z8block_FWPii
	movq	16(%rsp), %rax                  # 8-byte Reload
	movq	16(%rax), %rdi
	movl	$.L.str.2, %esi
	callq	fopen
	movq	%rax, 48(%rsp)                  # 8-byte Spill
	testl	%r12d, %r12d
	jle	.LBB4_16
# %bb.10:                               # %.preheader72.lr.ph
	xorl	%eax, %eax
	xorl	%ecx, %ecx
.LBB4_11:                               # %.lr.ph82
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB4_12 Depth 2
	movl	%eax, %edx
	leaq	(%r15,%rdx,4), %rdx
	xorl	%esi, %esi
.LBB4_12:                               #   Parent Loop BB4_11 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	cmpl	$1073741823, (%rdx,%rsi,4)      # imm = 0x3FFFFFFF
	jl	.LBB4_14
# %bb.13:                               #   in Loop: Header=BB4_12 Depth=2
	movl	$1073741823, (%rdx,%rsi,4)      # imm = 0x3FFFFFFF
.LBB4_14:                               #   in Loop: Header=BB4_12 Depth=2
	incq	%rsi
	cmpq	%rsi, %rbx
	jne	.LBB4_12
# %bb.15:                               # %._crit_edge83
                                        #   in Loop: Header=BB4_11 Depth=1
	incq	%rcx
	addl	%r12d, %eax
	cmpq	%rbx, %rcx
	jne	.LBB4_11
.LBB4_16:                               # %.preheader71
	testl	%ebp, %ebp
	movq	72(%rsp), %rcx                  # 8-byte Reload
	jle	.LBB4_19
# %bb.17:                               # %.preheader.lr.ph
	leaq	(,%rbp,4), %rax
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	xorl	%ebx, %ebx
	xorl	%r13d, %r13d
.LBB4_18:                               # %._crit_edge87
                                        # =>This Inner Loop Header: Depth=1
	movq	%rbp, 24(%rsp)                  # 8-byte Spill
	movslq	%r13d, %r13
	leaq	(%r15,%r13,4), %rsi
	movl	%ebx, %eax
	movl	%r12d, %ebp
	movq	%r15, %r12
	movq	%rcx, %r15
	leaq	(%rcx,%rax,4), %rdi
	movq	16(%rsp), %rdx                  # 8-byte Reload
	callq	memcpy@PLT
	movq	%r15, %rcx
	movq	%r12, %r15
	movl	%ebp, %r12d
	movq	24(%rsp), %rbp                  # 8-byte Reload
	addl	%r12d, %r13d
	addl	%r14d, %ebx
	decq	%rbp
	jne	.LBB4_18
.LBB4_19:                               # %._crit_edge89
	movl	$4, %esi
	movq	%rcx, %rbp
	movq	%rcx, %rdi
	movq	56(%rsp), %rdx                  # 8-byte Reload
	movq	48(%rsp), %rbx                  # 8-byte Reload
	movq	%rbx, %rcx
	callq	fwrite
	movq	64(%rsp), %rdi                  # 8-byte Reload
	callq	fclose
	movq	%rbx, %rdi
	callq	fclose
	testq	%r15, %r15
	je	.LBB4_21
# %bb.20:
	movq	%r15, %rdi
	callq	_ZdaPv
.LBB4_21:
	testq	%rbp, %rbp
	je	.LBB4_23
# %bb.22:
	movq	%rbp, %rdi
	callq	_ZdaPv
.LBB4_23:
	xorl	%eax, %eax
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	main, .Lfunc_end4-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10cal_phase1Piii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10cal_phase2Piii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10cal_phase3Piii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z10cal_phase1Piii,@object      # @_Z10cal_phase1Piii
	.section	.rodata,"a",@progbits
	.globl	_Z10cal_phase1Piii
	.p2align	3, 0x0
_Z10cal_phase1Piii:
	.quad	_Z25__device_stub__cal_phase1Piii
	.size	_Z10cal_phase1Piii, 8

	.type	_Z10cal_phase2Piii,@object      # @_Z10cal_phase2Piii
	.globl	_Z10cal_phase2Piii
	.p2align	3, 0x0
_Z10cal_phase2Piii:
	.quad	_Z25__device_stub__cal_phase2Piii
	.size	_Z10cal_phase2Piii, 8

	.type	_Z10cal_phase3Piii,@object      # @_Z10cal_phase3Piii
	.globl	_Z10cal_phase3Piii
	.p2align	3, 0x0
_Z10cal_phase3Piii:
	.quad	_Z25__device_stub__cal_phase3Piii
	.size	_Z10cal_phase3Piii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"rb"
	.size	.L.str, 3

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"The number of vertices: %d\n"
	.size	.L.str.1, 28

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"wb"
	.size	.L.str.2, 3

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z10cal_phase1Piii"
	.size	.L__unnamed_1, 19

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z10cal_phase2Piii"
	.size	.L__unnamed_2, 19

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z10cal_phase3Piii"
	.size	.L__unnamed_3, 19

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub__cal_phase1Piii
	.addrsig_sym _Z25__device_stub__cal_phase2Piii
	.addrsig_sym _Z25__device_stub__cal_phase3Piii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z10cal_phase1Piii
	.addrsig_sym _Z10cal_phase2Piii
	.addrsig_sym _Z10cal_phase3Piii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z10cal_phase1Piii      ; -- Begin function _Z10cal_phase1Piii
	.globl	_Z10cal_phase1Piii
	.p2align	8
	.type	_Z10cal_phase1Piii,@function
_Z10cal_phase1Piii:                     ; @_Z10cal_phase1Piii
; %bb.0:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_bfe_u32 v8, v0, 10, 10
	v_and_b32_e32 v9, 0x3ff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_lshlrev_b32_e32 v10, 3, v9
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s3, s3, 6
	v_lshl_add_u32 v1, v8, 1, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v0, v1, s2
	v_lshlrev_b32_e32 v1, 1, v9
	v_lshlrev_b32_e32 v9, 9, v8
	v_add_nc_u32_e32 v8, v9, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add3_u32 v0, s3, v1, v0
	v_add_nc_u32_e32 v2, s2, v0
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	v_add_co_u32 v4, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
	v_add_co_u32 v6, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v3, vcc_lo
	s_mov_b32 s0, exec_lo
	s_clause 0x1
	global_load_b64 v[0:1], v[4:5], off
	global_load_b64 v[2:3], v[6:7], off
	s_waitcnt vmcnt(0)
	ds_store_2addr_b64 v8, v[0:1], v[2:3] offset1:32
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v12, v9
	ds_load_b32 v11, v10
	ds_load_2addr_b64 v[0:3], v8 offset1:32
	s_waitcnt lgkmcnt(1)
	v_add_nc_u32_e32 v12, v11, v12
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_2
; %bb.1:
	ds_store_b32 v8, v12
	ds_load_b32 v11, v10
	v_mov_b32_e32 v0, v12
.LBB0_2:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:256
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v2
	s_cbranch_execz .LBB0_4
; %bb.3:
	v_mov_b32_e32 v2, v11
	ds_store_b32 v8, v11 offset:256
.LBB0_4:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9
	ds_load_b32 v11, v10 offset:4
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v1
	s_cbranch_execz .LBB0_6
; %bb.5:
	ds_store_b32 v8, v12 offset:4
	ds_load_b32 v11, v10 offset:4
	v_mov_b32_e32 v1, v12
.LBB0_6:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:256
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_8
; %bb.7:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_8:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v11, v9 offset:4
	ds_load_b32 v13, v10 offset:256
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_10
; %bb.9:
	v_mov_b32_e32 v0, v12
	ds_store_b32 v8, v12
.LBB0_10:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:260
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v13, v13, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v13, v2
	s_cbranch_execz .LBB0_12
; %bb.11:
	v_mov_b32_e32 v2, v13
	ds_store_b32 v8, v13 offset:256
.LBB0_12:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v13, v10 offset:260
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v1
	s_cbranch_execz .LBB0_14
; %bb.13:
	ds_store_b32 v8, v11 offset:4
	ds_load_b32 v12, v9 offset:260
	v_mov_b32_e32 v1, v11
.LBB0_14:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v12
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_16
; %bb.15:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_16:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:8
	ds_load_b32 v11, v10 offset:512
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_18
; %bb.17:
	ds_store_b32 v8, v12
	ds_load_b32 v11, v10 offset:512
	v_mov_b32_e32 v0, v12
.LBB0_18:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:264
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v2
	s_cbranch_execz .LBB0_20
; %bb.19:
	v_mov_b32_e32 v2, v11
	ds_store_b32 v8, v11 offset:256
.LBB0_20:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:8
	ds_load_b32 v11, v10 offset:516
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v1
	s_cbranch_execz .LBB0_22
; %bb.21:
	ds_store_b32 v8, v12 offset:4
	ds_load_b32 v11, v10 offset:516
	v_mov_b32_e32 v1, v12
.LBB0_22:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:264
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_24
; %bb.23:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_24:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v11, v9 offset:12
	ds_load_b32 v13, v10 offset:768
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_26
; %bb.25:
	v_mov_b32_e32 v0, v12
	ds_store_b32 v8, v12
.LBB0_26:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:268
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v13, v13, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v13, v2
	s_cbranch_execz .LBB0_28
; %bb.27:
	v_mov_b32_e32 v2, v13
	ds_store_b32 v8, v13 offset:256
.LBB0_28:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v13, v10 offset:772
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v1
	s_cbranch_execz .LBB0_30
; %bb.29:
	ds_store_b32 v8, v11 offset:4
	ds_load_b32 v12, v9 offset:268
	v_mov_b32_e32 v1, v11
.LBB0_30:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v12
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_32
; %bb.31:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_32:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:16
	ds_load_b32 v11, v10 offset:1024
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_34
; %bb.33:
	ds_store_b32 v8, v12
	ds_load_b32 v11, v10 offset:1024
	v_mov_b32_e32 v0, v12
.LBB0_34:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:272
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v2
	s_cbranch_execz .LBB0_36
; %bb.35:
	v_mov_b32_e32 v2, v11
	ds_store_b32 v8, v11 offset:256
.LBB0_36:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:16
	ds_load_b32 v11, v10 offset:1028
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v1
	s_cbranch_execz .LBB0_38
; %bb.37:
	ds_store_b32 v8, v12 offset:4
	ds_load_b32 v11, v10 offset:1028
	v_mov_b32_e32 v1, v12
.LBB0_38:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:272
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_40
; %bb.39:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_40:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v11, v9 offset:20
	ds_load_b32 v13, v10 offset:1280
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_42
; %bb.41:
	v_mov_b32_e32 v0, v12
	ds_store_b32 v8, v12
.LBB0_42:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:276
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v13, v13, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v13, v2
	s_cbranch_execz .LBB0_44
; %bb.43:
	v_mov_b32_e32 v2, v13
	ds_store_b32 v8, v13 offset:256
.LBB0_44:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v13, v10 offset:1284
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v1
	s_cbranch_execz .LBB0_46
; %bb.45:
	ds_store_b32 v8, v11 offset:4
	ds_load_b32 v12, v9 offset:276
	v_mov_b32_e32 v1, v11
.LBB0_46:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v12
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_48
; %bb.47:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_48:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:24
	ds_load_b32 v11, v10 offset:1536
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_50
; %bb.49:
	ds_store_b32 v8, v12
	ds_load_b32 v11, v10 offset:1536
	v_mov_b32_e32 v0, v12
.LBB0_50:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:280
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v2
	s_cbranch_execz .LBB0_52
; %bb.51:
	v_mov_b32_e32 v2, v11
	ds_store_b32 v8, v11 offset:256
.LBB0_52:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:24
	ds_load_b32 v11, v10 offset:1540
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v1
	s_cbranch_execz .LBB0_54
; %bb.53:
	ds_store_b32 v8, v12 offset:4
	ds_load_b32 v11, v10 offset:1540
	v_mov_b32_e32 v1, v12
.LBB0_54:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:280
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_56
; %bb.55:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_56:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v11, v9 offset:28
	ds_load_b32 v13, v10 offset:1792
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_58
; %bb.57:
	v_mov_b32_e32 v0, v12
	ds_store_b32 v8, v12
.LBB0_58:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:284
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v13, v13, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v13, v2
	s_cbranch_execz .LBB0_60
; %bb.59:
	v_mov_b32_e32 v2, v13
	ds_store_b32 v8, v13 offset:256
.LBB0_60:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v13, v10 offset:1796
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v1
	s_cbranch_execz .LBB0_62
; %bb.61:
	ds_store_b32 v8, v11 offset:4
	ds_load_b32 v12, v9 offset:284
	v_mov_b32_e32 v1, v11
.LBB0_62:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v12
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_64
; %bb.63:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_64:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:32
	ds_load_b32 v11, v10 offset:2048
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_66
; %bb.65:
	ds_store_b32 v8, v12
	ds_load_b32 v11, v10 offset:2048
	v_mov_b32_e32 v0, v12
.LBB0_66:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:288
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v2
	s_cbranch_execz .LBB0_68
; %bb.67:
	v_mov_b32_e32 v2, v11
	ds_store_b32 v8, v11 offset:256
.LBB0_68:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:32
	ds_load_b32 v11, v10 offset:2052
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v1
	s_cbranch_execz .LBB0_70
; %bb.69:
	ds_store_b32 v8, v12 offset:4
	ds_load_b32 v11, v10 offset:2052
	v_mov_b32_e32 v1, v12
.LBB0_70:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:288
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_72
; %bb.71:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_72:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v11, v9 offset:36
	ds_load_b32 v13, v10 offset:2304
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_74
; %bb.73:
	v_mov_b32_e32 v0, v12
	ds_store_b32 v8, v12
.LBB0_74:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:292
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v13, v13, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v13, v2
	s_cbranch_execz .LBB0_76
; %bb.75:
	v_mov_b32_e32 v2, v13
	ds_store_b32 v8, v13 offset:256
.LBB0_76:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v13, v10 offset:2308
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v1
	s_cbranch_execz .LBB0_78
; %bb.77:
	ds_store_b32 v8, v11 offset:4
	ds_load_b32 v12, v9 offset:292
	v_mov_b32_e32 v1, v11
.LBB0_78:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v12
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_80
; %bb.79:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_80:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:40
	ds_load_b32 v11, v10 offset:2560
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_82
; %bb.81:
	ds_store_b32 v8, v12
	ds_load_b32 v11, v10 offset:2560
	v_mov_b32_e32 v0, v12
.LBB0_82:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:296
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v2
	s_cbranch_execz .LBB0_84
; %bb.83:
	v_mov_b32_e32 v2, v11
	ds_store_b32 v8, v11 offset:256
.LBB0_84:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:40
	ds_load_b32 v11, v10 offset:2564
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v1
	s_cbranch_execz .LBB0_86
; %bb.85:
	ds_store_b32 v8, v12 offset:4
	ds_load_b32 v11, v10 offset:2564
	v_mov_b32_e32 v1, v12
.LBB0_86:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:296
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_88
; %bb.87:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_88:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v11, v9 offset:44
	ds_load_b32 v13, v10 offset:2816
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_90
; %bb.89:
	v_mov_b32_e32 v0, v12
	ds_store_b32 v8, v12
.LBB0_90:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:300
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v13, v13, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v13, v2
	s_cbranch_execz .LBB0_92
; %bb.91:
	v_mov_b32_e32 v2, v13
	ds_store_b32 v8, v13 offset:256
.LBB0_92:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v13, v10 offset:2820
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v1
	s_cbranch_execz .LBB0_94
; %bb.93:
	ds_store_b32 v8, v11 offset:4
	ds_load_b32 v12, v9 offset:300
	v_mov_b32_e32 v1, v11
.LBB0_94:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v12
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_96
; %bb.95:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_96:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:48
	ds_load_b32 v11, v10 offset:3072
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_98
; %bb.97:
	ds_store_b32 v8, v12
	ds_load_b32 v11, v10 offset:3072
	v_mov_b32_e32 v0, v12
.LBB0_98:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:304
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v2
	s_cbranch_execz .LBB0_100
; %bb.99:
	v_mov_b32_e32 v2, v11
	ds_store_b32 v8, v11 offset:256
.LBB0_100:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:48
	ds_load_b32 v11, v10 offset:3076
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v1
	s_cbranch_execz .LBB0_102
; %bb.101:
	ds_store_b32 v8, v12 offset:4
	ds_load_b32 v11, v10 offset:3076
	v_mov_b32_e32 v1, v12
.LBB0_102:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:304
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_104
; %bb.103:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_104:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v11, v9 offset:52
	ds_load_b32 v13, v10 offset:3328
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_106
; %bb.105:
	v_mov_b32_e32 v0, v12
	ds_store_b32 v8, v12
.LBB0_106:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:308
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v13, v13, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v13, v2
	s_cbranch_execz .LBB0_108
; %bb.107:
	v_mov_b32_e32 v2, v13
	ds_store_b32 v8, v13 offset:256
.LBB0_108:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v13, v10 offset:3332
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v1
	s_cbranch_execz .LBB0_110
; %bb.109:
	ds_store_b32 v8, v11 offset:4
	ds_load_b32 v12, v9 offset:308
	v_mov_b32_e32 v1, v11
.LBB0_110:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v12
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_112
; %bb.111:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_112:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:56
	ds_load_b32 v11, v10 offset:3584
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_114
; %bb.113:
	ds_store_b32 v8, v12
	ds_load_b32 v11, v10 offset:3584
	v_mov_b32_e32 v0, v12
.LBB0_114:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:312
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v2
	s_cbranch_execz .LBB0_116
; %bb.115:
	v_mov_b32_e32 v2, v11
	ds_store_b32 v8, v11 offset:256
.LBB0_116:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:56
	ds_load_b32 v11, v10 offset:3588
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v1
	s_cbranch_execz .LBB0_118
; %bb.117:
	ds_store_b32 v8, v12 offset:4
	ds_load_b32 v11, v10 offset:3588
	v_mov_b32_e32 v1, v12
.LBB0_118:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:312
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_120
; %bb.119:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_120:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v11, v9 offset:60
	ds_load_b32 v13, v10 offset:3840
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_122
; %bb.121:
	v_mov_b32_e32 v0, v12
	ds_store_b32 v8, v12
.LBB0_122:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:316
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v13, v13, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v13, v2
	s_cbranch_execz .LBB0_124
; %bb.123:
	v_mov_b32_e32 v2, v13
	ds_store_b32 v8, v13 offset:256
.LBB0_124:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v13, v10 offset:3844
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v1
	s_cbranch_execz .LBB0_126
; %bb.125:
	ds_store_b32 v8, v11 offset:4
	ds_load_b32 v12, v9 offset:316
	v_mov_b32_e32 v1, v11
.LBB0_126:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v12
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_128
; %bb.127:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_128:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:64
	ds_load_b32 v11, v10 offset:4096
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_130
; %bb.129:
	ds_store_b32 v8, v12
	ds_load_b32 v11, v10 offset:4096
	v_mov_b32_e32 v0, v12
.LBB0_130:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:320
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v2
	s_cbranch_execz .LBB0_132
; %bb.131:
	v_mov_b32_e32 v2, v11
	ds_store_b32 v8, v11 offset:256
.LBB0_132:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:64
	ds_load_b32 v11, v10 offset:4100
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v1
	s_cbranch_execz .LBB0_134
; %bb.133:
	ds_store_b32 v8, v12 offset:4
	ds_load_b32 v11, v10 offset:4100
	v_mov_b32_e32 v1, v12
.LBB0_134:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:320
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_136
; %bb.135:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_136:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v11, v9 offset:68
	ds_load_b32 v13, v10 offset:4352
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_138
; %bb.137:
	v_mov_b32_e32 v0, v12
	ds_store_b32 v8, v12
.LBB0_138:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:324
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v13, v13, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v13, v2
	s_cbranch_execz .LBB0_140
; %bb.139:
	v_mov_b32_e32 v2, v13
	ds_store_b32 v8, v13 offset:256
.LBB0_140:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v13, v10 offset:4356
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v1
	s_cbranch_execz .LBB0_142
; %bb.141:
	ds_store_b32 v8, v11 offset:4
	ds_load_b32 v12, v9 offset:324
	v_mov_b32_e32 v1, v11
.LBB0_142:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v12
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_144
; %bb.143:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_144:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:72
	ds_load_b32 v11, v10 offset:4608
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_146
; %bb.145:
	ds_store_b32 v8, v12
	ds_load_b32 v11, v10 offset:4608
	v_mov_b32_e32 v0, v12
.LBB0_146:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:328
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v2
	s_cbranch_execz .LBB0_148
; %bb.147:
	v_mov_b32_e32 v2, v11
	ds_store_b32 v8, v11 offset:256
.LBB0_148:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:72
	ds_load_b32 v11, v10 offset:4612
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v1
	s_cbranch_execz .LBB0_150
; %bb.149:
	ds_store_b32 v8, v12 offset:4
	ds_load_b32 v11, v10 offset:4612
	v_mov_b32_e32 v1, v12
.LBB0_150:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:328
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_152
; %bb.151:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_152:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v11, v9 offset:76
	ds_load_b32 v13, v10 offset:4864
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_154
; %bb.153:
	v_mov_b32_e32 v0, v12
	ds_store_b32 v8, v12
.LBB0_154:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:332
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v13, v13, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v13, v2
	s_cbranch_execz .LBB0_156
; %bb.155:
	v_mov_b32_e32 v2, v13
	ds_store_b32 v8, v13 offset:256
.LBB0_156:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v13, v10 offset:4868
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v1
	s_cbranch_execz .LBB0_158
; %bb.157:
	ds_store_b32 v8, v11 offset:4
	ds_load_b32 v12, v9 offset:332
	v_mov_b32_e32 v1, v11
.LBB0_158:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v12
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_160
; %bb.159:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_160:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:80
	ds_load_b32 v11, v10 offset:5120
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_162
; %bb.161:
	ds_store_b32 v8, v12
	ds_load_b32 v11, v10 offset:5120
	v_mov_b32_e32 v0, v12
.LBB0_162:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:336
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v2
	s_cbranch_execz .LBB0_164
; %bb.163:
	v_mov_b32_e32 v2, v11
	ds_store_b32 v8, v11 offset:256
.LBB0_164:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:80
	ds_load_b32 v11, v10 offset:5124
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v1
	s_cbranch_execz .LBB0_166
; %bb.165:
	ds_store_b32 v8, v12 offset:4
	ds_load_b32 v11, v10 offset:5124
	v_mov_b32_e32 v1, v12
.LBB0_166:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:336
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_168
; %bb.167:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_168:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v11, v9 offset:84
	ds_load_b32 v13, v10 offset:5376
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_170
; %bb.169:
	v_mov_b32_e32 v0, v12
	ds_store_b32 v8, v12
.LBB0_170:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:340
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v13, v13, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v13, v2
	s_cbranch_execz .LBB0_172
; %bb.171:
	v_mov_b32_e32 v2, v13
	ds_store_b32 v8, v13 offset:256
.LBB0_172:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v13, v10 offset:5380
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v1
	s_cbranch_execz .LBB0_174
; %bb.173:
	ds_store_b32 v8, v11 offset:4
	ds_load_b32 v12, v9 offset:340
	v_mov_b32_e32 v1, v11
.LBB0_174:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v12
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_176
; %bb.175:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_176:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:88
	ds_load_b32 v11, v10 offset:5632
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_178
; %bb.177:
	ds_store_b32 v8, v12
	ds_load_b32 v11, v10 offset:5632
	v_mov_b32_e32 v0, v12
.LBB0_178:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:344
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v2
	s_cbranch_execz .LBB0_180
; %bb.179:
	v_mov_b32_e32 v2, v11
	ds_store_b32 v8, v11 offset:256
.LBB0_180:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:88
	ds_load_b32 v11, v10 offset:5636
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v1
	s_cbranch_execz .LBB0_182
; %bb.181:
	ds_store_b32 v8, v12 offset:4
	ds_load_b32 v11, v10 offset:5636
	v_mov_b32_e32 v1, v12
.LBB0_182:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:344
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_184
; %bb.183:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_184:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v11, v9 offset:92
	ds_load_b32 v13, v10 offset:5888
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_186
; %bb.185:
	v_mov_b32_e32 v0, v12
	ds_store_b32 v8, v12
.LBB0_186:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:348
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v13, v13, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v13, v2
	s_cbranch_execz .LBB0_188
; %bb.187:
	v_mov_b32_e32 v2, v13
	ds_store_b32 v8, v13 offset:256
.LBB0_188:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v13, v10 offset:5892
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v1
	s_cbranch_execz .LBB0_190
; %bb.189:
	ds_store_b32 v8, v11 offset:4
	ds_load_b32 v12, v9 offset:348
	v_mov_b32_e32 v1, v11
.LBB0_190:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v12
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_192
; %bb.191:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_192:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:96
	ds_load_b32 v11, v10 offset:6144
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_194
; %bb.193:
	ds_store_b32 v8, v12
	ds_load_b32 v11, v10 offset:6144
	v_mov_b32_e32 v0, v12
.LBB0_194:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:352
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v2
	s_cbranch_execz .LBB0_196
; %bb.195:
	v_mov_b32_e32 v2, v11
	ds_store_b32 v8, v11 offset:256
.LBB0_196:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:96
	ds_load_b32 v11, v10 offset:6148
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v1
	s_cbranch_execz .LBB0_198
; %bb.197:
	ds_store_b32 v8, v12 offset:4
	ds_load_b32 v11, v10 offset:6148
	v_mov_b32_e32 v1, v12
.LBB0_198:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:352
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_200
; %bb.199:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_200:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v11, v9 offset:100
	ds_load_b32 v13, v10 offset:6400
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_202
; %bb.201:
	v_mov_b32_e32 v0, v12
	ds_store_b32 v8, v12
.LBB0_202:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:356
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v13, v13, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v13, v2
	s_cbranch_execz .LBB0_204
; %bb.203:
	v_mov_b32_e32 v2, v13
	ds_store_b32 v8, v13 offset:256
.LBB0_204:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v13, v10 offset:6404
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v1
	s_cbranch_execz .LBB0_206
; %bb.205:
	ds_store_b32 v8, v11 offset:4
	ds_load_b32 v12, v9 offset:356
	v_mov_b32_e32 v1, v11
.LBB0_206:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v12
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_208
; %bb.207:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_208:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:104
	ds_load_b32 v11, v10 offset:6656
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_210
; %bb.209:
	ds_store_b32 v8, v12
	ds_load_b32 v11, v10 offset:6656
	v_mov_b32_e32 v0, v12
.LBB0_210:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:360
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v2
	s_cbranch_execz .LBB0_212
; %bb.211:
	v_mov_b32_e32 v2, v11
	ds_store_b32 v8, v11 offset:256
.LBB0_212:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:104
	ds_load_b32 v11, v10 offset:6660
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v1
	s_cbranch_execz .LBB0_214
; %bb.213:
	ds_store_b32 v8, v12 offset:4
	ds_load_b32 v11, v10 offset:6660
	v_mov_b32_e32 v1, v12
.LBB0_214:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:360
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_216
; %bb.215:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_216:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v11, v9 offset:108
	ds_load_b32 v13, v10 offset:6912
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_218
; %bb.217:
	v_mov_b32_e32 v0, v12
	ds_store_b32 v8, v12
.LBB0_218:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:364
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v13, v13, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v13, v2
	s_cbranch_execz .LBB0_220
; %bb.219:
	v_mov_b32_e32 v2, v13
	ds_store_b32 v8, v13 offset:256
.LBB0_220:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v13, v10 offset:6916
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v1
	s_cbranch_execz .LBB0_222
; %bb.221:
	ds_store_b32 v8, v11 offset:4
	ds_load_b32 v12, v9 offset:364
	v_mov_b32_e32 v1, v11
.LBB0_222:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v12
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_224
; %bb.223:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_224:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:112
	ds_load_b32 v11, v10 offset:7168
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_226
; %bb.225:
	ds_store_b32 v8, v12
	ds_load_b32 v11, v10 offset:7168
	v_mov_b32_e32 v0, v12
.LBB0_226:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:368
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v2
	s_cbranch_execz .LBB0_228
; %bb.227:
	v_mov_b32_e32 v2, v11
	ds_store_b32 v8, v11 offset:256
.LBB0_228:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:112
	ds_load_b32 v11, v10 offset:7172
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v1
	s_cbranch_execz .LBB0_230
; %bb.229:
	ds_store_b32 v8, v12 offset:4
	ds_load_b32 v11, v10 offset:7172
	v_mov_b32_e32 v1, v12
.LBB0_230:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:368
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_232
; %bb.231:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_232:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v11, v9 offset:116
	ds_load_b32 v13, v10 offset:7424
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_234
; %bb.233:
	v_mov_b32_e32 v0, v12
	ds_store_b32 v8, v12
.LBB0_234:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:372
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v13, v13, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v13, v2
	s_cbranch_execz .LBB0_236
; %bb.235:
	v_mov_b32_e32 v2, v13
	ds_store_b32 v8, v13 offset:256
.LBB0_236:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v13, v10 offset:7428
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v1
	s_cbranch_execz .LBB0_238
; %bb.237:
	ds_store_b32 v8, v11 offset:4
	ds_load_b32 v12, v9 offset:372
	v_mov_b32_e32 v1, v11
.LBB0_238:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v12
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_240
; %bb.239:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_240:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:120
	ds_load_b32 v11, v10 offset:7680
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_242
; %bb.241:
	ds_store_b32 v8, v12
	ds_load_b32 v11, v10 offset:7680
	v_mov_b32_e32 v0, v12
.LBB0_242:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:376
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v2
	s_cbranch_execz .LBB0_244
; %bb.243:
	v_mov_b32_e32 v2, v11
	ds_store_b32 v8, v11 offset:256
.LBB0_244:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:120
	ds_load_b32 v11, v10 offset:7684
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v1
	s_cbranch_execz .LBB0_246
; %bb.245:
	ds_store_b32 v8, v12 offset:4
	ds_load_b32 v11, v10 offset:7684
	v_mov_b32_e32 v1, v12
.LBB0_246:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:376
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_248
; %bb.247:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_248:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v11, v9 offset:124
	ds_load_b32 v13, v10 offset:7936
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_250
; %bb.249:
	v_mov_b32_e32 v0, v12
	ds_store_b32 v8, v12
.LBB0_250:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:380
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v13, v13, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v13, v2
	s_cbranch_execz .LBB0_252
; %bb.251:
	v_mov_b32_e32 v2, v13
	ds_store_b32 v8, v13 offset:256
.LBB0_252:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v13, v10 offset:7940
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v1
	s_cbranch_execz .LBB0_254
; %bb.253:
	ds_store_b32 v8, v11 offset:4
	ds_load_b32 v12, v9 offset:380
	v_mov_b32_e32 v1, v11
.LBB0_254:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v12
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_256
; %bb.255:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_256:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:128
	ds_load_b32 v11, v10 offset:8192
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_258
; %bb.257:
	ds_store_b32 v8, v12
	ds_load_b32 v11, v10 offset:8192
	v_mov_b32_e32 v0, v12
.LBB0_258:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:384
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v2
	s_cbranch_execz .LBB0_260
; %bb.259:
	v_mov_b32_e32 v2, v11
	ds_store_b32 v8, v11 offset:256
.LBB0_260:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:128
	ds_load_b32 v11, v10 offset:8196
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v1
	s_cbranch_execz .LBB0_262
; %bb.261:
	ds_store_b32 v8, v12 offset:4
	ds_load_b32 v11, v10 offset:8196
	v_mov_b32_e32 v1, v12
.LBB0_262:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:384
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_264
; %bb.263:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_264:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v11, v9 offset:132
	ds_load_b32 v13, v10 offset:8448
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_266
; %bb.265:
	v_mov_b32_e32 v0, v12
	ds_store_b32 v8, v12
.LBB0_266:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:388
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v13, v13, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v13, v2
	s_cbranch_execz .LBB0_268
; %bb.267:
	v_mov_b32_e32 v2, v13
	ds_store_b32 v8, v13 offset:256
.LBB0_268:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v13, v10 offset:8452
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v1
	s_cbranch_execz .LBB0_270
; %bb.269:
	ds_store_b32 v8, v11 offset:4
	ds_load_b32 v12, v9 offset:388
	v_mov_b32_e32 v1, v11
.LBB0_270:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v12
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_272
; %bb.271:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_272:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:136
	ds_load_b32 v11, v10 offset:8704
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_274
; %bb.273:
	ds_store_b32 v8, v12
	ds_load_b32 v11, v10 offset:8704
	v_mov_b32_e32 v0, v12
.LBB0_274:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:392
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v2
	s_cbranch_execz .LBB0_276
; %bb.275:
	v_mov_b32_e32 v2, v11
	ds_store_b32 v8, v11 offset:256
.LBB0_276:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:136
	ds_load_b32 v11, v10 offset:8708
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v1
	s_cbranch_execz .LBB0_278
; %bb.277:
	ds_store_b32 v8, v12 offset:4
	ds_load_b32 v11, v10 offset:8708
	v_mov_b32_e32 v1, v12
.LBB0_278:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:392
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_280
; %bb.279:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_280:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v11, v9 offset:140
	ds_load_b32 v13, v10 offset:8960
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_282
; %bb.281:
	v_mov_b32_e32 v0, v12
	ds_store_b32 v8, v12
.LBB0_282:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:396
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v13, v13, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v13, v2
	s_cbranch_execz .LBB0_284
; %bb.283:
	v_mov_b32_e32 v2, v13
	ds_store_b32 v8, v13 offset:256
.LBB0_284:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v13, v10 offset:8964
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v1
	s_cbranch_execz .LBB0_286
; %bb.285:
	ds_store_b32 v8, v11 offset:4
	ds_load_b32 v12, v9 offset:396
	v_mov_b32_e32 v1, v11
.LBB0_286:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v12
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_288
; %bb.287:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_288:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:144
	ds_load_b32 v11, v10 offset:9216
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_290
; %bb.289:
	ds_store_b32 v8, v12
	ds_load_b32 v11, v10 offset:9216
	v_mov_b32_e32 v0, v12
.LBB0_290:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:400
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v2
	s_cbranch_execz .LBB0_292
; %bb.291:
	v_mov_b32_e32 v2, v11
	ds_store_b32 v8, v11 offset:256
.LBB0_292:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:144
	ds_load_b32 v11, v10 offset:9220
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v1
	s_cbranch_execz .LBB0_294
; %bb.293:
	ds_store_b32 v8, v12 offset:4
	ds_load_b32 v11, v10 offset:9220
	v_mov_b32_e32 v1, v12
.LBB0_294:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:400
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_296
; %bb.295:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_296:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v11, v9 offset:148
	ds_load_b32 v13, v10 offset:9472
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_298
; %bb.297:
	v_mov_b32_e32 v0, v12
	ds_store_b32 v8, v12
.LBB0_298:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:404
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v13, v13, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v13, v2
	s_cbranch_execz .LBB0_300
; %bb.299:
	v_mov_b32_e32 v2, v13
	ds_store_b32 v8, v13 offset:256
.LBB0_300:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v13, v10 offset:9476
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v1
	s_cbranch_execz .LBB0_302
; %bb.301:
	ds_store_b32 v8, v11 offset:4
	ds_load_b32 v12, v9 offset:404
	v_mov_b32_e32 v1, v11
.LBB0_302:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v12
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_304
; %bb.303:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_304:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:152
	ds_load_b32 v11, v10 offset:9728
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_306
; %bb.305:
	ds_store_b32 v8, v12
	ds_load_b32 v11, v10 offset:9728
	v_mov_b32_e32 v0, v12
.LBB0_306:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:408
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v2
	s_cbranch_execz .LBB0_308
; %bb.307:
	v_mov_b32_e32 v2, v11
	ds_store_b32 v8, v11 offset:256
.LBB0_308:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:152
	ds_load_b32 v11, v10 offset:9732
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v1
	s_cbranch_execz .LBB0_310
; %bb.309:
	ds_store_b32 v8, v12 offset:4
	ds_load_b32 v11, v10 offset:9732
	v_mov_b32_e32 v1, v12
.LBB0_310:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:408
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_312
; %bb.311:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_312:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v11, v9 offset:156
	ds_load_b32 v13, v10 offset:9984
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_314
; %bb.313:
	v_mov_b32_e32 v0, v12
	ds_store_b32 v8, v12
.LBB0_314:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:412
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v13, v13, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v13, v2
	s_cbranch_execz .LBB0_316
; %bb.315:
	v_mov_b32_e32 v2, v13
	ds_store_b32 v8, v13 offset:256
.LBB0_316:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v13, v10 offset:9988
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v1
	s_cbranch_execz .LBB0_318
; %bb.317:
	ds_store_b32 v8, v11 offset:4
	ds_load_b32 v12, v9 offset:412
	v_mov_b32_e32 v1, v11
.LBB0_318:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v12
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_320
; %bb.319:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_320:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:160
	ds_load_b32 v11, v10 offset:10240
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_322
; %bb.321:
	ds_store_b32 v8, v12
	ds_load_b32 v11, v10 offset:10240
	v_mov_b32_e32 v0, v12
.LBB0_322:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:416
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v2
	s_cbranch_execz .LBB0_324
; %bb.323:
	v_mov_b32_e32 v2, v11
	ds_store_b32 v8, v11 offset:256
.LBB0_324:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:160
	ds_load_b32 v11, v10 offset:10244
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v1
	s_cbranch_execz .LBB0_326
; %bb.325:
	ds_store_b32 v8, v12 offset:4
	ds_load_b32 v11, v10 offset:10244
	v_mov_b32_e32 v1, v12
.LBB0_326:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:416
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_328
; %bb.327:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_328:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v11, v9 offset:164
	ds_load_b32 v13, v10 offset:10496
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_330
; %bb.329:
	v_mov_b32_e32 v0, v12
	ds_store_b32 v8, v12
.LBB0_330:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:420
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v13, v13, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v13, v2
	s_cbranch_execz .LBB0_332
; %bb.331:
	v_mov_b32_e32 v2, v13
	ds_store_b32 v8, v13 offset:256
.LBB0_332:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v13, v10 offset:10500
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v1
	s_cbranch_execz .LBB0_334
; %bb.333:
	ds_store_b32 v8, v11 offset:4
	ds_load_b32 v12, v9 offset:420
	v_mov_b32_e32 v1, v11
.LBB0_334:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v12
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_336
; %bb.335:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_336:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:168
	ds_load_b32 v11, v10 offset:10752
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_338
; %bb.337:
	ds_store_b32 v8, v12
	ds_load_b32 v11, v10 offset:10752
	v_mov_b32_e32 v0, v12
.LBB0_338:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:424
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v2
	s_cbranch_execz .LBB0_340
; %bb.339:
	v_mov_b32_e32 v2, v11
	ds_store_b32 v8, v11 offset:256
.LBB0_340:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:168
	ds_load_b32 v11, v10 offset:10756
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v1
	s_cbranch_execz .LBB0_342
; %bb.341:
	ds_store_b32 v8, v12 offset:4
	ds_load_b32 v11, v10 offset:10756
	v_mov_b32_e32 v1, v12
.LBB0_342:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:424
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_344
; %bb.343:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_344:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v11, v9 offset:172
	ds_load_b32 v13, v10 offset:11008
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_346
; %bb.345:
	v_mov_b32_e32 v0, v12
	ds_store_b32 v8, v12
.LBB0_346:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:428
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v13, v13, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v13, v2
	s_cbranch_execz .LBB0_348
; %bb.347:
	v_mov_b32_e32 v2, v13
	ds_store_b32 v8, v13 offset:256
.LBB0_348:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v13, v10 offset:11012
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v1
	s_cbranch_execz .LBB0_350
; %bb.349:
	ds_store_b32 v8, v11 offset:4
	ds_load_b32 v12, v9 offset:428
	v_mov_b32_e32 v1, v11
.LBB0_350:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v12
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_352
; %bb.351:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_352:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:176
	ds_load_b32 v11, v10 offset:11264
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_354
; %bb.353:
	ds_store_b32 v8, v12
	ds_load_b32 v11, v10 offset:11264
	v_mov_b32_e32 v0, v12
.LBB0_354:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:432
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v2
	s_cbranch_execz .LBB0_356
; %bb.355:
	v_mov_b32_e32 v2, v11
	ds_store_b32 v8, v11 offset:256
.LBB0_356:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:176
	ds_load_b32 v11, v10 offset:11268
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v1
	s_cbranch_execz .LBB0_358
; %bb.357:
	ds_store_b32 v8, v12 offset:4
	ds_load_b32 v11, v10 offset:11268
	v_mov_b32_e32 v1, v12
.LBB0_358:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:432
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_360
; %bb.359:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_360:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v11, v9 offset:180
	ds_load_b32 v13, v10 offset:11520
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_362
; %bb.361:
	v_mov_b32_e32 v0, v12
	ds_store_b32 v8, v12
.LBB0_362:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:436
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v13, v13, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v13, v2
	s_cbranch_execz .LBB0_364
; %bb.363:
	v_mov_b32_e32 v2, v13
	ds_store_b32 v8, v13 offset:256
.LBB0_364:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v13, v10 offset:11524
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v1
	s_cbranch_execz .LBB0_366
; %bb.365:
	ds_store_b32 v8, v11 offset:4
	ds_load_b32 v12, v9 offset:436
	v_mov_b32_e32 v1, v11
.LBB0_366:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v12
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_368
; %bb.367:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_368:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:184
	ds_load_b32 v11, v10 offset:11776
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_370
; %bb.369:
	ds_store_b32 v8, v12
	ds_load_b32 v11, v10 offset:11776
	v_mov_b32_e32 v0, v12
.LBB0_370:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:440
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v2
	s_cbranch_execz .LBB0_372
; %bb.371:
	v_mov_b32_e32 v2, v11
	ds_store_b32 v8, v11 offset:256
.LBB0_372:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:184
	ds_load_b32 v11, v10 offset:11780
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v1
	s_cbranch_execz .LBB0_374
; %bb.373:
	ds_store_b32 v8, v12 offset:4
	ds_load_b32 v11, v10 offset:11780
	v_mov_b32_e32 v1, v12
.LBB0_374:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:440
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_376
; %bb.375:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_376:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v11, v9 offset:188
	ds_load_b32 v13, v10 offset:12032
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_378
; %bb.377:
	v_mov_b32_e32 v0, v12
	ds_store_b32 v8, v12
.LBB0_378:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:444
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v13, v13, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v13, v2
	s_cbranch_execz .LBB0_380
; %bb.379:
	v_mov_b32_e32 v2, v13
	ds_store_b32 v8, v13 offset:256
.LBB0_380:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v13, v10 offset:12036
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v1
	s_cbranch_execz .LBB0_382
; %bb.381:
	ds_store_b32 v8, v11 offset:4
	ds_load_b32 v12, v9 offset:444
	v_mov_b32_e32 v1, v11
.LBB0_382:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v12
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_384
; %bb.383:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_384:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:192
	ds_load_b32 v11, v10 offset:12288
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_386
; %bb.385:
	ds_store_b32 v8, v12
	ds_load_b32 v11, v10 offset:12288
	v_mov_b32_e32 v0, v12
.LBB0_386:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:448
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v2
	s_cbranch_execz .LBB0_388
; %bb.387:
	v_mov_b32_e32 v2, v11
	ds_store_b32 v8, v11 offset:256
.LBB0_388:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:192
	ds_load_b32 v11, v10 offset:12292
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v1
	s_cbranch_execz .LBB0_390
; %bb.389:
	ds_store_b32 v8, v12 offset:4
	ds_load_b32 v11, v10 offset:12292
	v_mov_b32_e32 v1, v12
.LBB0_390:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:448
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_392
; %bb.391:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_392:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v11, v9 offset:196
	ds_load_b32 v13, v10 offset:12544
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_394
; %bb.393:
	v_mov_b32_e32 v0, v12
	ds_store_b32 v8, v12
.LBB0_394:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:452
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v13, v13, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v13, v2
	s_cbranch_execz .LBB0_396
; %bb.395:
	v_mov_b32_e32 v2, v13
	ds_store_b32 v8, v13 offset:256
.LBB0_396:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v13, v10 offset:12548
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v1
	s_cbranch_execz .LBB0_398
; %bb.397:
	ds_store_b32 v8, v11 offset:4
	ds_load_b32 v12, v9 offset:452
	v_mov_b32_e32 v1, v11
.LBB0_398:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v12
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_400
; %bb.399:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_400:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:200
	ds_load_b32 v11, v10 offset:12800
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_402
; %bb.401:
	ds_store_b32 v8, v12
	ds_load_b32 v11, v10 offset:12800
	v_mov_b32_e32 v0, v12
.LBB0_402:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:456
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v2
	s_cbranch_execz .LBB0_404
; %bb.403:
	v_mov_b32_e32 v2, v11
	ds_store_b32 v8, v11 offset:256
.LBB0_404:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:200
	ds_load_b32 v11, v10 offset:12804
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v1
	s_cbranch_execz .LBB0_406
; %bb.405:
	ds_store_b32 v8, v12 offset:4
	ds_load_b32 v11, v10 offset:12804
	v_mov_b32_e32 v1, v12
.LBB0_406:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:456
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_408
; %bb.407:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_408:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v11, v9 offset:204
	ds_load_b32 v13, v10 offset:13056
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_410
; %bb.409:
	v_mov_b32_e32 v0, v12
	ds_store_b32 v8, v12
.LBB0_410:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:460
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v13, v13, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v13, v2
	s_cbranch_execz .LBB0_412
; %bb.411:
	v_mov_b32_e32 v2, v13
	ds_store_b32 v8, v13 offset:256
.LBB0_412:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v13, v10 offset:13060
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v1
	s_cbranch_execz .LBB0_414
; %bb.413:
	ds_store_b32 v8, v11 offset:4
	ds_load_b32 v12, v9 offset:460
	v_mov_b32_e32 v1, v11
.LBB0_414:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v12
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_416
; %bb.415:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_416:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:208
	ds_load_b32 v11, v10 offset:13312
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_418
; %bb.417:
	ds_store_b32 v8, v12
	ds_load_b32 v11, v10 offset:13312
	v_mov_b32_e32 v0, v12
.LBB0_418:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:464
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v2
	s_cbranch_execz .LBB0_420
; %bb.419:
	v_mov_b32_e32 v2, v11
	ds_store_b32 v8, v11 offset:256
.LBB0_420:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:208
	ds_load_b32 v11, v10 offset:13316
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v1
	s_cbranch_execz .LBB0_422
; %bb.421:
	ds_store_b32 v8, v12 offset:4
	ds_load_b32 v11, v10 offset:13316
	v_mov_b32_e32 v1, v12
.LBB0_422:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:464
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_424
; %bb.423:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_424:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v11, v9 offset:212
	ds_load_b32 v13, v10 offset:13568
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_426
; %bb.425:
	v_mov_b32_e32 v0, v12
	ds_store_b32 v8, v12
.LBB0_426:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:468
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v13, v13, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v13, v2
	s_cbranch_execz .LBB0_428
; %bb.427:
	v_mov_b32_e32 v2, v13
	ds_store_b32 v8, v13 offset:256
.LBB0_428:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v13, v10 offset:13572
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v1
	s_cbranch_execz .LBB0_430
; %bb.429:
	ds_store_b32 v8, v11 offset:4
	ds_load_b32 v12, v9 offset:468
	v_mov_b32_e32 v1, v11
.LBB0_430:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v12
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_432
; %bb.431:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_432:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:216
	ds_load_b32 v11, v10 offset:13824
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_434
; %bb.433:
	ds_store_b32 v8, v12
	ds_load_b32 v11, v10 offset:13824
	v_mov_b32_e32 v0, v12
.LBB0_434:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:472
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v2
	s_cbranch_execz .LBB0_436
; %bb.435:
	v_mov_b32_e32 v2, v11
	ds_store_b32 v8, v11 offset:256
.LBB0_436:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:216
	ds_load_b32 v11, v10 offset:13828
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v1
	s_cbranch_execz .LBB0_438
; %bb.437:
	ds_store_b32 v8, v12 offset:4
	ds_load_b32 v11, v10 offset:13828
	v_mov_b32_e32 v1, v12
.LBB0_438:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:472
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_440
; %bb.439:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_440:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v11, v9 offset:220
	ds_load_b32 v13, v10 offset:14080
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_442
; %bb.441:
	v_mov_b32_e32 v0, v12
	ds_store_b32 v8, v12
.LBB0_442:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:476
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v13, v13, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v13, v2
	s_cbranch_execz .LBB0_444
; %bb.443:
	v_mov_b32_e32 v2, v13
	ds_store_b32 v8, v13 offset:256
.LBB0_444:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v13, v10 offset:14084
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v1
	s_cbranch_execz .LBB0_446
; %bb.445:
	ds_store_b32 v8, v11 offset:4
	ds_load_b32 v12, v9 offset:476
	v_mov_b32_e32 v1, v11
.LBB0_446:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v12
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_448
; %bb.447:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_448:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:224
	ds_load_b32 v11, v10 offset:14336
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_450
; %bb.449:
	ds_store_b32 v8, v12
	ds_load_b32 v11, v10 offset:14336
	v_mov_b32_e32 v0, v12
.LBB0_450:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:480
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v2
	s_cbranch_execz .LBB0_452
; %bb.451:
	v_mov_b32_e32 v2, v11
	ds_store_b32 v8, v11 offset:256
.LBB0_452:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:224
	ds_load_b32 v11, v10 offset:14340
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v1
	s_cbranch_execz .LBB0_454
; %bb.453:
	ds_store_b32 v8, v12 offset:4
	ds_load_b32 v11, v10 offset:14340
	v_mov_b32_e32 v1, v12
.LBB0_454:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:480
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_456
; %bb.455:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_456:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v11, v9 offset:228
	ds_load_b32 v13, v10 offset:14592
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_458
; %bb.457:
	v_mov_b32_e32 v0, v12
	ds_store_b32 v8, v12
.LBB0_458:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:484
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v13, v13, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v13, v2
	s_cbranch_execz .LBB0_460
; %bb.459:
	v_mov_b32_e32 v2, v13
	ds_store_b32 v8, v13 offset:256
.LBB0_460:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v13, v10 offset:14596
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v1
	s_cbranch_execz .LBB0_462
; %bb.461:
	ds_store_b32 v8, v11 offset:4
	ds_load_b32 v12, v9 offset:484
	v_mov_b32_e32 v1, v11
.LBB0_462:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v12
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_464
; %bb.463:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_464:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:232
	ds_load_b32 v11, v10 offset:14848
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_466
; %bb.465:
	ds_store_b32 v8, v12
	ds_load_b32 v11, v10 offset:14848
	v_mov_b32_e32 v0, v12
.LBB0_466:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:488
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v2
	s_cbranch_execz .LBB0_468
; %bb.467:
	v_mov_b32_e32 v2, v11
	ds_store_b32 v8, v11 offset:256
.LBB0_468:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:232
	ds_load_b32 v11, v10 offset:14852
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v1
	s_cbranch_execz .LBB0_470
; %bb.469:
	ds_store_b32 v8, v12 offset:4
	ds_load_b32 v11, v10 offset:14852
	v_mov_b32_e32 v1, v12
.LBB0_470:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:488
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_472
; %bb.471:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_472:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v11, v9 offset:236
	ds_load_b32 v13, v10 offset:15104
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_474
; %bb.473:
	v_mov_b32_e32 v0, v12
	ds_store_b32 v8, v12
.LBB0_474:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:492
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v13, v13, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v13, v2
	s_cbranch_execz .LBB0_476
; %bb.475:
	v_mov_b32_e32 v2, v13
	ds_store_b32 v8, v13 offset:256
.LBB0_476:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v13, v10 offset:15108
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v1
	s_cbranch_execz .LBB0_478
; %bb.477:
	ds_store_b32 v8, v11 offset:4
	ds_load_b32 v12, v9 offset:492
	v_mov_b32_e32 v1, v11
.LBB0_478:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v12
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_480
; %bb.479:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_480:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:240
	ds_load_b32 v11, v10 offset:15360
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_482
; %bb.481:
	ds_store_b32 v8, v12
	ds_load_b32 v11, v10 offset:15360
	v_mov_b32_e32 v0, v12
.LBB0_482:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:496
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v2
	s_cbranch_execz .LBB0_484
; %bb.483:
	v_mov_b32_e32 v2, v11
	ds_store_b32 v8, v11 offset:256
.LBB0_484:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:240
	ds_load_b32 v11, v10 offset:15364
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v1
	s_cbranch_execz .LBB0_486
; %bb.485:
	ds_store_b32 v8, v12 offset:4
	ds_load_b32 v11, v10 offset:15364
	v_mov_b32_e32 v1, v12
.LBB0_486:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:496
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_488
; %bb.487:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_488:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v11, v9 offset:244
	ds_load_b32 v13, v10 offset:15616
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_490
; %bb.489:
	v_mov_b32_e32 v0, v12
	ds_store_b32 v8, v12
.LBB0_490:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:500
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v13, v13, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v13, v2
	s_cbranch_execz .LBB0_492
; %bb.491:
	v_mov_b32_e32 v2, v13
	ds_store_b32 v8, v13 offset:256
.LBB0_492:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v13, v10 offset:15620
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v1
	s_cbranch_execz .LBB0_494
; %bb.493:
	ds_store_b32 v8, v11 offset:4
	ds_load_b32 v12, v9 offset:500
	v_mov_b32_e32 v1, v11
.LBB0_494:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v13, v12
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_496
; %bb.495:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_496:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:248
	ds_load_b32 v11, v10 offset:15872
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v0
	s_cbranch_execz .LBB0_498
; %bb.497:
	ds_store_b32 v8, v12
	ds_load_b32 v11, v10 offset:15872
	v_mov_b32_e32 v0, v12
.LBB0_498:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:504
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v2
	s_cbranch_execz .LBB0_500
; %bb.499:
	v_mov_b32_e32 v2, v11
	ds_store_b32 v8, v11 offset:256
.LBB0_500:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:248
	ds_load_b32 v11, v10 offset:15876
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v1
	s_cbranch_execz .LBB0_502
; %bb.501:
	ds_store_b32 v8, v12 offset:4
	ds_load_b32 v11, v10 offset:15876
	v_mov_b32_e32 v1, v12
.LBB0_502:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v12, v9 offset:504
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v11, v11, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v11, v3
	s_cbranch_execz .LBB0_504
; %bb.503:
	v_mov_b32_e32 v3, v11
	ds_store_b32 v8, v11 offset:260
.LBB0_504:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v11, v9 offset:252
	ds_load_b32 v12, v10 offset:16128
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v13, v12, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v13, v0
	s_cbranch_execz .LBB0_506
; %bb.505:
	ds_store_b32 v8, v13
.LBB0_506:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v0, v9 offset:508
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v12, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v12, v2
	s_cbranch_execz .LBB0_508
; %bb.507:
	ds_store_b32 v8, v12 offset:256
.LBB0_508:
	s_or_b32 exec_lo, exec_lo, s0
	ds_load_b32 v2, v10 offset:16132
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v10, v2, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v10, v1
	s_cbranch_execz .LBB0_510
; %bb.509:
	ds_store_b32 v8, v10 offset:4
	ds_load_b32 v0, v9 offset:508
.LBB0_510:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v0, v2, v0
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v0, v3
	s_cbranch_execz .LBB0_512
; %bb.511:
	ds_store_b32 v8, v0 offset:260
.LBB0_512:
	s_or_b32 exec_lo, exec_lo, s0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b64 v[0:3], v8 offset1:32
	s_waitcnt lgkmcnt(0)
	s_clause 0x3
	global_store_b32 v[4:5], v0, off
	global_store_b32 v[6:7], v2, off
	global_store_b32 v[4:5], v1, off offset:4
	global_store_b32 v[6:7], v3, off offset:4
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10cal_phase1Piii
		.amdhsa_group_segment_fixed_size 16384
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 16
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 14
		.amdhsa_next_free_sgpr 4
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z10cal_phase1Piii, .Lfunc_end0-_Z10cal_phase1Piii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 14872
; NumSgprs: 6
; NumVgprs: 14
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 16384 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 6
; NumVGPRsForWavesPerEU: 14
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z10cal_phase2Piii      ; -- Begin function _Z10cal_phase2Piii
	.globl	_Z10cal_phase2Piii
	.p2align	8
	.type	_Z10cal_phase2Piii,@function
_Z10cal_phase2Piii:                     ; @_Z10cal_phase2Piii
; %bb.0:
	s_load_b64 s[2:3], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_cmp_eq_u32 s14, s3
	s_cbranch_scc1 .LBB1_7
; %bb.1:
	v_bfe_u32 v9, v0, 10, 10
	s_lshl_b32 s3, s3, 6
	s_load_b64 s[4:5], s[0:1], 0x0
	s_cmp_eq_u32 s15, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v11, 1, v9
	v_add_nc_u32_e32 v13, s3, v11
	v_and_b32_e32 v10, 0x3ff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v12, 1, v10
	v_add_nc_u32_e32 v0, s3, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, v13, s2, v[0:1]
	v_add_nc_u32_e32 v3, s2, v1
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v1, vcc_lo, s4, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v2, vcc_lo, s5, v2, vcc_lo
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_clause 0x1
	global_load_b64 v[5:6], v[1:2], off
	global_load_b64 v[7:8], v[3:4], off
	s_lshl_b32 s0, s14, 6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, s0, v12
	v_dual_cndmask_b32 v0, v0, v2 :: v_dual_add_nc_u32 v1, s0, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v3, v1, v13 :: v_dual_lshlrev_b32 v10, 3, v10
	s_and_b32 vcc_lo, exec_lo, vcc_lo
	v_mad_u64_u32 v[1:2], null, v3, s2, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v9, v9, 9, v10
	v_add_nc_u32_e32 v10, 0x4000, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, s2, v1
	v_ashrrev_i32_e32 v2, 31, v1
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_lshlrev_b64 v[2:3], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v0, s0, s4, v0
	v_add_co_ci_u32_e64 v1, s0, s5, v1, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v2, s0, s4, v2
	v_add_co_ci_u32_e64 v3, s0, s5, v3, s0
	s_mov_b32 s0, 0
	s_waitcnt vmcnt(0)
	ds_store_2addr_b64 v9, v[5:6], v[7:8] offset1:32
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[4:5], v[0:1], off
	global_load_b64 v[6:7], v[2:3], off
	v_lshlrev_b32_e32 v8, 8, v11
	v_lshlrev_b32_e32 v9, 2, v12
	s_waitcnt vmcnt(0)
	ds_store_2addr_b64 v10, v[4:5], v[6:7] offset1:32
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_cbranch_vccnz .LBB1_3
; %bb.2:                                ; %.preheader153.preheader
	ds_load_2addr_b64 v[10:13], v9 offset1:32
	ds_load_b128 v[14:17], v8 offset:16384
	ds_load_b128 v[18:21], v8 offset:16640
	ds_load_2addr_b64 v[22:25], v9 offset0:64 offset1:96
	ds_load_b128 v[26:29], v8 offset:16400
	ds_load_b128 v[30:33], v8 offset:16416
	ds_load_b128 v[34:37], v8 offset:16432
	ds_load_2addr_b64 v[38:41], v9 offset0:128 offset1:160
	ds_load_b128 v[42:45], v8 offset:16656
	v_add_nc_u32_e32 v47, 0x800, v9
	s_waitcnt lgkmcnt(7)
	v_add_nc_u32_e32 v46, v10, v14
	s_waitcnt lgkmcnt(6)
	v_add_nc_u32_e32 v10, v18, v10
	v_add_nc_u32_e32 v14, v11, v14
	v_add_nc_u32_e32 v11, v11, v18
	v_add_nc_u32_e32 v18, v12, v15
	v_add_nc_u32_e32 v12, v19, v12
	v_add_nc_u32_e32 v15, v13, v15
	v_add_nc_u32_e32 v13, v13, v19
	s_waitcnt lgkmcnt(5)
	v_add_nc_u32_e32 v19, v22, v16
	v_add_nc_u32_e32 v22, v20, v22
	v_add_nc_u32_e32 v16, v23, v16
	v_add_nc_u32_e32 v20, v23, v20
	v_add_nc_u32_e32 v23, v24, v17
	v_add_nc_u32_e32 v24, v21, v24
	v_add_nc_u32_e32 v17, v25, v17
	v_add_nc_u32_e32 v21, v25, v21
	v_min3_i32 v25, v6, v10, v12
	v_min3_i32 v14, v5, v14, v15
	v_min3_i32 v15, v7, v11, v13
	ds_load_2addr_b64 v[10:13], v9 offset0:192 offset1:224
	v_min3_i32 v18, v4, v46, v18
	v_min3_i32 v22, v25, v22, v24
	v_min3_i32 v24, v14, v16, v17
	v_min3_i32 v25, v15, v20, v21
	s_waitcnt lgkmcnt(2)
	v_add_nc_u32_e32 v46, v38, v26
	v_min3_i32 v23, v18, v19, v23
	s_waitcnt lgkmcnt(1)
	v_add_nc_u32_e32 v38, v42, v38
	v_add_nc_u32_e32 v26, v39, v26
	v_add_nc_u32_e32 v39, v39, v42
	v_add_nc_u32_e32 v42, v40, v27
	v_add_nc_u32_e32 v40, v43, v40
	v_add_nc_u32_e32 v27, v41, v27
	ds_load_2addr_b64 v[14:17], v47 offset1:32
	v_add_nc_u32_e32 v41, v41, v43
	ds_load_b128 v[18:21], v8 offset:16672
	v_min3_i32 v22, v22, v38, v40
	v_min3_i32 v24, v24, v26, v27
	v_min3_i32 v23, v23, v46, v42
	v_min3_i32 v25, v25, v39, v41
	s_waitcnt lgkmcnt(2)
	v_add_nc_u32_e32 v26, v10, v28
	v_add_nc_u32_e32 v27, v44, v10
	v_add_nc_u32_e32 v28, v11, v28
	v_add_nc_u32_e32 v38, v11, v44
	v_add_nc_u32_e32 v39, v12, v29
	v_add_nc_u32_e32 v40, v45, v12
	v_add_nc_u32_e32 v29, v13, v29
	v_add_nc_u32_e32 v41, v13, v45
	ds_load_2addr_b64 v[10:13], v47 offset0:64 offset1:96
	v_min3_i32 v39, v23, v26, v39
	v_min3_i32 v40, v22, v27, v40
	v_min3_i32 v42, v24, v28, v29
	v_min3_i32 v38, v25, v38, v41
	ds_load_b128 v[22:25], v8 offset:16688
	s_waitcnt lgkmcnt(3)
	v_add_nc_u32_e32 v41, v14, v30
	s_waitcnt lgkmcnt(2)
	v_add_nc_u32_e32 v14, v18, v14
	v_add_nc_u32_e32 v30, v15, v30
	v_add_nc_u32_e32 v15, v15, v18
	v_add_nc_u32_e32 v18, v16, v31
	v_add_nc_u32_e32 v31, v17, v31
	v_add_nc_u32_e32 v17, v17, v19
	v_add_nc_u32_e32 v16, v19, v16
	ds_load_2addr_b64 v[26:29], v47 offset0:128 offset1:160
	v_min3_i32 v18, v39, v41, v18
	v_min3_i32 v15, v38, v15, v17
	v_min3_i32 v14, v40, v14, v16
	v_min3_i32 v16, v42, v30, v31
	s_waitcnt lgkmcnt(2)
	v_add_nc_u32_e32 v17, v10, v32
	v_add_nc_u32_e32 v19, v20, v10
	v_add_nc_u32_e32 v10, v12, v33
	v_add_nc_u32_e32 v30, v11, v32
	v_add_nc_u32_e32 v20, v11, v20
	v_add_nc_u32_e32 v31, v21, v12
	v_add_nc_u32_e32 v32, v13, v33
	v_add_nc_u32_e32 v21, v13, v21
	v_min3_i32 v33, v18, v17, v10
	ds_load_2addr_b64 v[10:13], v47 offset0:192 offset1:224
	v_add_nc_u32_e32 v40, 0x1000, v9
	v_min3_i32 v30, v16, v30, v32
	v_min3_i32 v32, v15, v20, v21
	v_min3_i32 v31, v14, v19, v31
	s_waitcnt lgkmcnt(1)
	v_add_nc_u32_e32 v38, v26, v34
	v_add_nc_u32_e32 v39, v22, v26
	v_add_nc_u32_e32 v22, v27, v22
	v_add_nc_u32_e32 v26, v28, v35
	v_add_nc_u32_e32 v41, v23, v28
	v_add_nc_u32_e32 v23, v29, v23
	v_add_nc_u32_e32 v34, v27, v34
	v_add_nc_u32_e32 v35, v29, v35
	ds_load_2addr_b64 v[14:17], v40 offset1:32
	ds_load_b128 v[18:21], v8 offset:16448
	v_min3_i32 v33, v33, v38, v26
	ds_load_b128 v[26:29], v8 offset:16704
	v_min3_i32 v22, v32, v22, v23
	v_min3_i32 v30, v30, v34, v35
	v_min3_i32 v31, v31, v39, v41
	s_waitcnt lgkmcnt(3)
	v_add_nc_u32_e32 v23, v10, v36
	v_add_nc_u32_e32 v32, v24, v10
	v_add_nc_u32_e32 v10, v12, v37
	v_add_nc_u32_e32 v34, v11, v36
	v_add_nc_u32_e32 v24, v11, v24
	v_add_nc_u32_e32 v35, v25, v12
	v_add_nc_u32_e32 v36, v13, v37
	v_add_nc_u32_e32 v25, v13, v25
	v_min3_i32 v38, v33, v23, v10
	ds_load_2addr_b64 v[10:13], v40 offset0:64 offset1:96
	v_min3_i32 v39, v31, v32, v35
	v_min3_i32 v41, v30, v34, v36
	v_min3_i32 v42, v22, v24, v25
	ds_load_b128 v[22:25], v8 offset:16464
	s_waitcnt lgkmcnt(3)
	v_add_nc_u32_e32 v43, v14, v18
	s_waitcnt lgkmcnt(2)
	v_add_nc_u32_e32 v14, v26, v14
	v_add_nc_u32_e32 v18, v15, v18
	v_add_nc_u32_e32 v15, v15, v26
	v_add_nc_u32_e32 v26, v16, v19
	v_add_nc_u32_e32 v16, v27, v16
	v_add_nc_u32_e32 v19, v17, v19
	v_add_nc_u32_e32 v17, v17, v27
	ds_load_b128 v[30:33], v8 offset:16720
	ds_load_2addr_b64 v[34:37], v40 offset0:128 offset1:160
	v_min3_i32 v26, v38, v43, v26
	v_min3_i32 v14, v39, v14, v16
	v_min3_i32 v16, v41, v18, v19
	v_min3_i32 v15, v42, v15, v17
	v_add_nc_u32_e32 v41, 0x1800, v9
	s_waitcnt lgkmcnt(3)
	v_add_nc_u32_e32 v17, v10, v20
	v_add_nc_u32_e32 v18, v28, v10
	v_add_nc_u32_e32 v10, v12, v21
	v_add_nc_u32_e32 v19, v11, v20
	v_add_nc_u32_e32 v20, v11, v28
	v_add_nc_u32_e32 v27, v29, v12
	v_add_nc_u32_e32 v21, v13, v21
	v_add_nc_u32_e32 v28, v13, v29
	v_min3_i32 v26, v26, v17, v10
	ds_load_2addr_b64 v[10:13], v40 offset0:192 offset1:224
	v_min3_i32 v38, v14, v18, v27
	v_min3_i32 v39, v16, v19, v21
	v_min3_i32 v40, v15, v20, v28
	ds_load_2addr_b64 v[14:17], v41 offset1:32
	ds_load_b128 v[18:21], v8 offset:16480
	s_waitcnt lgkmcnt(3)
	v_add_nc_u32_e32 v27, v34, v22
	v_add_nc_u32_e32 v34, v30, v34
	v_add_nc_u32_e32 v22, v35, v22
	v_add_nc_u32_e32 v30, v35, v30
	v_add_nc_u32_e32 v28, v36, v23
	v_add_nc_u32_e32 v35, v31, v36
	v_add_nc_u32_e32 v23, v37, v23
	v_add_nc_u32_e32 v31, v37, v31
	s_delay_alu instid0(VALU_DEP_4)
	v_min3_i32 v36, v26, v27, v28
	ds_load_b128 v[26:29], v8 offset:16736
	v_min3_i32 v22, v39, v22, v23
	v_min3_i32 v23, v40, v30, v31
	v_min3_i32 v34, v38, v34, v35
	s_waitcnt lgkmcnt(3)
	v_add_nc_u32_e32 v30, v10, v24
	v_add_nc_u32_e32 v31, v32, v10
	v_add_nc_u32_e32 v10, v12, v25
	v_add_nc_u32_e32 v24, v11, v24
	v_add_nc_u32_e32 v32, v11, v32
	v_add_nc_u32_e32 v35, v33, v12
	v_add_nc_u32_e32 v25, v13, v25
	v_add_nc_u32_e32 v33, v13, v33
	v_min3_i32 v38, v36, v30, v10
	ds_load_2addr_b64 v[10:13], v41 offset0:64 offset1:96
	v_min3_i32 v39, v34, v31, v35
	v_min3_i32 v40, v22, v24, v25
	v_min3_i32 v42, v23, v32, v33
	ds_load_b128 v[22:25], v8 offset:16496
	s_waitcnt lgkmcnt(3)
	v_add_nc_u32_e32 v43, v14, v18
	s_waitcnt lgkmcnt(2)
	v_add_nc_u32_e32 v14, v26, v14
	v_add_nc_u32_e32 v18, v15, v18
	v_add_nc_u32_e32 v15, v15, v26
	v_add_nc_u32_e32 v26, v16, v19
	v_add_nc_u32_e32 v16, v27, v16
	v_add_nc_u32_e32 v19, v17, v19
	v_add_nc_u32_e32 v17, v17, v27
	ds_load_b128 v[30:33], v8 offset:16752
	ds_load_2addr_b64 v[34:37], v41 offset0:128 offset1:160
	v_min3_i32 v26, v38, v43, v26
	v_min3_i32 v14, v39, v14, v16
	v_min3_i32 v16, v40, v18, v19
	v_min3_i32 v15, v42, v15, v17
	s_waitcnt lgkmcnt(3)
	v_add_nc_u32_e32 v17, v10, v20
	v_add_nc_u32_e32 v18, v28, v10
	v_add_nc_u32_e32 v10, v12, v21
	v_add_nc_u32_e32 v19, v11, v20
	v_add_nc_u32_e32 v20, v11, v28
	v_add_nc_u32_e32 v27, v29, v12
	v_add_nc_u32_e32 v21, v13, v21
	v_add_nc_u32_e32 v28, v13, v29
	v_min3_i32 v26, v26, v17, v10
	ds_load_2addr_b64 v[10:13], v41 offset0:192 offset1:224
	v_min3_i32 v38, v14, v18, v27
	v_min3_i32 v39, v16, v19, v21
	v_min3_i32 v40, v15, v20, v28
	v_add_nc_u32_e32 v41, 0x2000, v9
	s_waitcnt lgkmcnt(1)
	v_add_nc_u32_e32 v27, v34, v22
	v_add_nc_u32_e32 v34, v30, v34
	v_add_nc_u32_e32 v22, v35, v22
	v_add_nc_u32_e32 v30, v35, v30
	v_add_nc_u32_e32 v28, v36, v23
	v_add_nc_u32_e32 v35, v31, v36
	v_add_nc_u32_e32 v23, v37, v23
	v_add_nc_u32_e32 v31, v37, v31
	ds_load_2addr_b64 v[14:17], v41 offset1:32
	ds_load_b128 v[18:21], v8 offset:16512
	v_min3_i32 v36, v26, v27, v28
	ds_load_b128 v[26:29], v8 offset:16768
	v_min3_i32 v22, v39, v22, v23
	v_min3_i32 v23, v40, v30, v31
	v_min3_i32 v34, v38, v34, v35
	s_waitcnt lgkmcnt(3)
	v_add_nc_u32_e32 v30, v10, v24
	v_add_nc_u32_e32 v31, v32, v10
	v_add_nc_u32_e32 v10, v12, v25
	v_add_nc_u32_e32 v24, v11, v24
	v_add_nc_u32_e32 v32, v11, v32
	v_add_nc_u32_e32 v35, v33, v12
	v_add_nc_u32_e32 v25, v13, v25
	v_add_nc_u32_e32 v33, v13, v33
	v_min3_i32 v38, v36, v30, v10
	ds_load_2addr_b64 v[10:13], v41 offset0:64 offset1:96
	v_min3_i32 v39, v34, v31, v35
	v_min3_i32 v40, v22, v24, v25
	v_min3_i32 v42, v23, v32, v33
	ds_load_b128 v[22:25], v8 offset:16528
	s_waitcnt lgkmcnt(3)
	v_add_nc_u32_e32 v43, v14, v18
	s_waitcnt lgkmcnt(2)
	v_add_nc_u32_e32 v14, v26, v14
	v_add_nc_u32_e32 v18, v15, v18
	v_add_nc_u32_e32 v15, v15, v26
	v_add_nc_u32_e32 v26, v16, v19
	v_add_nc_u32_e32 v16, v27, v16
	v_add_nc_u32_e32 v19, v17, v19
	v_add_nc_u32_e32 v17, v17, v27
	ds_load_b128 v[30:33], v8 offset:16784
	ds_load_2addr_b64 v[34:37], v41 offset0:128 offset1:160
	v_min3_i32 v26, v38, v43, v26
	v_min3_i32 v14, v39, v14, v16
	v_min3_i32 v16, v40, v18, v19
	v_min3_i32 v15, v42, v15, v17
	s_waitcnt lgkmcnt(3)
	v_add_nc_u32_e32 v17, v10, v20
	v_add_nc_u32_e32 v18, v28, v10
	v_add_nc_u32_e32 v10, v12, v21
	v_add_nc_u32_e32 v19, v11, v20
	v_add_nc_u32_e32 v20, v11, v28
	v_add_nc_u32_e32 v27, v29, v12
	v_add_nc_u32_e32 v21, v13, v21
	v_add_nc_u32_e32 v28, v13, v29
	v_min3_i32 v26, v26, v17, v10
	ds_load_2addr_b64 v[10:13], v41 offset0:192 offset1:224
	v_min3_i32 v38, v14, v18, v27
	v_min3_i32 v39, v16, v19, v21
	v_min3_i32 v40, v15, v20, v28
	v_add_nc_u32_e32 v41, 0x2800, v9
	s_waitcnt lgkmcnt(1)
	v_add_nc_u32_e32 v27, v34, v22
	v_add_nc_u32_e32 v34, v30, v34
	v_add_nc_u32_e32 v22, v35, v22
	v_add_nc_u32_e32 v30, v35, v30
	v_add_nc_u32_e32 v28, v36, v23
	v_add_nc_u32_e32 v35, v31, v36
	v_add_nc_u32_e32 v23, v37, v23
	v_add_nc_u32_e32 v31, v37, v31
	ds_load_2addr_b64 v[14:17], v41 offset1:32
	ds_load_b128 v[18:21], v8 offset:16544
	v_min3_i32 v36, v26, v27, v28
	ds_load_b128 v[26:29], v8 offset:16800
	v_min3_i32 v22, v39, v22, v23
	v_min3_i32 v23, v40, v30, v31
	v_min3_i32 v34, v38, v34, v35
	s_waitcnt lgkmcnt(3)
	v_add_nc_u32_e32 v30, v10, v24
	v_add_nc_u32_e32 v31, v32, v10
	v_add_nc_u32_e32 v10, v12, v25
	v_add_nc_u32_e32 v24, v11, v24
	v_add_nc_u32_e32 v32, v11, v32
	v_add_nc_u32_e32 v35, v33, v12
	v_add_nc_u32_e32 v25, v13, v25
	v_add_nc_u32_e32 v33, v13, v33
	v_min3_i32 v38, v36, v30, v10
	ds_load_2addr_b64 v[10:13], v41 offset0:64 offset1:96
	v_min3_i32 v39, v34, v31, v35
	v_min3_i32 v40, v22, v24, v25
	v_min3_i32 v42, v23, v32, v33
	ds_load_b128 v[22:25], v8 offset:16560
	s_waitcnt lgkmcnt(3)
	v_add_nc_u32_e32 v43, v14, v18
	s_waitcnt lgkmcnt(2)
	v_add_nc_u32_e32 v14, v26, v14
	v_add_nc_u32_e32 v18, v15, v18
	v_add_nc_u32_e32 v15, v15, v26
	v_add_nc_u32_e32 v26, v16, v19
	v_add_nc_u32_e32 v16, v27, v16
	v_add_nc_u32_e32 v19, v17, v19
	v_add_nc_u32_e32 v17, v17, v27
	ds_load_b128 v[30:33], v8 offset:16816
	ds_load_2addr_b64 v[34:37], v41 offset0:128 offset1:160
	v_min3_i32 v26, v38, v43, v26
	v_min3_i32 v14, v39, v14, v16
	v_min3_i32 v16, v40, v18, v19
	v_min3_i32 v15, v42, v15, v17
	s_waitcnt lgkmcnt(3)
	v_add_nc_u32_e32 v17, v10, v20
	v_add_nc_u32_e32 v18, v28, v10
	v_add_nc_u32_e32 v10, v12, v21
	v_add_nc_u32_e32 v19, v11, v20
	v_add_nc_u32_e32 v20, v11, v28
	v_add_nc_u32_e32 v27, v29, v12
	v_add_nc_u32_e32 v21, v13, v21
	v_add_nc_u32_e32 v28, v13, v29
	v_min3_i32 v26, v26, v17, v10
	ds_load_2addr_b64 v[10:13], v41 offset0:192 offset1:224
	v_min3_i32 v38, v14, v18, v27
	v_min3_i32 v39, v16, v19, v21
	v_min3_i32 v40, v15, v20, v28
	v_add_nc_u32_e32 v41, 0x3000, v9
	s_waitcnt lgkmcnt(1)
	v_add_nc_u32_e32 v27, v34, v22
	v_add_nc_u32_e32 v34, v30, v34
	v_add_nc_u32_e32 v22, v35, v22
	v_add_nc_u32_e32 v30, v35, v30
	v_add_nc_u32_e32 v28, v36, v23
	v_add_nc_u32_e32 v35, v31, v36
	v_add_nc_u32_e32 v23, v37, v23
	v_add_nc_u32_e32 v31, v37, v31
	ds_load_2addr_b64 v[14:17], v41 offset1:32
	ds_load_b128 v[18:21], v8 offset:16576
	v_min3_i32 v36, v26, v27, v28
	ds_load_b128 v[26:29], v8 offset:16832
	v_min3_i32 v22, v39, v22, v23
	v_min3_i32 v23, v40, v30, v31
	v_min3_i32 v34, v38, v34, v35
	s_waitcnt lgkmcnt(3)
	v_add_nc_u32_e32 v30, v10, v24
	v_add_nc_u32_e32 v31, v32, v10
	v_add_nc_u32_e32 v10, v12, v25
	v_add_nc_u32_e32 v24, v11, v24
	v_add_nc_u32_e32 v32, v11, v32
	v_add_nc_u32_e32 v35, v33, v12
	v_add_nc_u32_e32 v25, v13, v25
	v_add_nc_u32_e32 v33, v13, v33
	v_min3_i32 v38, v36, v30, v10
	ds_load_2addr_b64 v[10:13], v41 offset0:64 offset1:96
	v_min3_i32 v39, v34, v31, v35
	v_min3_i32 v40, v22, v24, v25
	v_min3_i32 v42, v23, v32, v33
	ds_load_b128 v[22:25], v8 offset:16592
	s_waitcnt lgkmcnt(3)
	v_add_nc_u32_e32 v43, v14, v18
	s_waitcnt lgkmcnt(2)
	v_add_nc_u32_e32 v14, v26, v14
	v_add_nc_u32_e32 v18, v15, v18
	v_add_nc_u32_e32 v15, v15, v26
	v_add_nc_u32_e32 v26, v16, v19
	v_add_nc_u32_e32 v16, v27, v16
	v_add_nc_u32_e32 v19, v17, v19
	v_add_nc_u32_e32 v17, v17, v27
	ds_load_b128 v[30:33], v8 offset:16848
	ds_load_2addr_b64 v[34:37], v41 offset0:128 offset1:160
	v_min3_i32 v26, v38, v43, v26
	v_min3_i32 v14, v39, v14, v16
	v_min3_i32 v16, v40, v18, v19
	v_min3_i32 v15, v42, v15, v17
	s_waitcnt lgkmcnt(3)
	v_add_nc_u32_e32 v17, v10, v20
	v_add_nc_u32_e32 v18, v28, v10
	v_add_nc_u32_e32 v10, v12, v21
	v_add_nc_u32_e32 v19, v11, v20
	v_add_nc_u32_e32 v20, v11, v28
	v_add_nc_u32_e32 v27, v29, v12
	v_add_nc_u32_e32 v21, v13, v21
	v_add_nc_u32_e32 v28, v13, v29
	v_min3_i32 v26, v26, v17, v10
	ds_load_2addr_b64 v[10:13], v41 offset0:192 offset1:224
	v_min3_i32 v38, v14, v18, v27
	v_min3_i32 v39, v16, v19, v21
	v_min3_i32 v40, v15, v20, v28
	s_waitcnt lgkmcnt(1)
	v_add_nc_u32_e32 v27, v34, v22
	v_add_nc_u32_e32 v34, v30, v34
	v_add_nc_u32_e32 v22, v35, v22
	v_add_nc_u32_e32 v30, v35, v30
	v_add_nc_u32_e32 v35, 0x3800, v9
	v_add_nc_u32_e32 v28, v36, v23
	v_add_nc_u32_e32 v36, v31, v36
	v_add_nc_u32_e32 v23, v37, v23
	v_add_nc_u32_e32 v31, v37, v31
	ds_load_2addr_b64 v[14:17], v35 offset1:32
	ds_load_b128 v[18:21], v8 offset:16608
	v_min3_i32 v37, v26, v27, v28
	ds_load_b128 v[26:29], v8 offset:16864
	v_min3_i32 v22, v39, v22, v23
	v_min3_i32 v23, v40, v30, v31
	v_min3_i32 v34, v38, v34, v36
	s_waitcnt lgkmcnt(3)
	v_add_nc_u32_e32 v30, v10, v24
	v_add_nc_u32_e32 v31, v32, v10
	v_add_nc_u32_e32 v10, v12, v25
	v_add_nc_u32_e32 v24, v11, v24
	v_add_nc_u32_e32 v32, v11, v32
	v_add_nc_u32_e32 v36, v33, v12
	v_add_nc_u32_e32 v25, v13, v25
	v_add_nc_u32_e32 v33, v13, v33
	v_min3_i32 v37, v37, v30, v10
	ds_load_2addr_b64 v[10:13], v35 offset0:64 offset1:96
	v_min3_i32 v34, v34, v31, v36
	v_min3_i32 v36, v22, v24, v25
	v_min3_i32 v38, v23, v32, v33
	ds_load_b128 v[22:25], v8 offset:16624
	s_waitcnt lgkmcnt(3)
	v_add_nc_u32_e32 v39, v14, v18
	ds_load_b128 v[30:33], v8 offset:16880
	s_waitcnt lgkmcnt(3)
	v_add_nc_u32_e32 v40, v26, v14
	v_add_nc_u32_e32 v18, v15, v18
	v_add_nc_u32_e32 v26, v15, v26
	v_add_nc_u32_e32 v41, v16, v19
	v_add_nc_u32_e32 v42, v27, v16
	v_add_nc_u32_e32 v19, v17, v19
	v_add_nc_u32_e32 v27, v17, v27
	ds_load_2addr_b64 v[14:17], v35 offset0:128 offset1:160
	v_min3_i32 v37, v37, v39, v41
	v_min3_i32 v34, v34, v40, v42
	v_min3_i32 v36, v36, v18, v19
	v_min3_i32 v26, v38, v26, v27
	s_waitcnt lgkmcnt(3)
	v_add_nc_u32_e32 v27, v10, v20
	v_add_nc_u32_e32 v10, v28, v10
	v_add_nc_u32_e32 v38, v11, v20
	v_add_nc_u32_e32 v11, v11, v28
	v_add_nc_u32_e32 v28, v12, v21
	v_add_nc_u32_e32 v39, v13, v21
	ds_load_2addr_b64 v[18:21], v35 offset0:192 offset1:224
	v_add_nc_u32_e32 v12, v29, v12
	v_add_nc_u32_e32 v13, v13, v29
	v_min3_i32 v27, v37, v27, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_min3_i32 v10, v34, v10, v12
	v_min3_i32 v12, v36, v38, v39
	v_min3_i32 v11, v26, v11, v13
	s_waitcnt lgkmcnt(1)
	v_add_nc_u32_e32 v13, v14, v22
	v_add_nc_u32_e32 v14, v30, v14
	v_add_nc_u32_e32 v22, v15, v22
	v_add_nc_u32_e32 v15, v15, v30
	v_add_nc_u32_e32 v26, v16, v23
	v_add_nc_u32_e32 v16, v31, v16
	v_add_nc_u32_e32 v23, v17, v23
	v_add_nc_u32_e32 v17, v17, v31
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_min3_i32 v13, v27, v13, v26
	v_min3_i32 v10, v10, v14, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_min3_i32 v14, v12, v22, v23
	v_min3_i32 v11, v11, v15, v17
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v12, v18, v24
	v_add_nc_u32_e32 v15, v32, v18
	v_add_nc_u32_e32 v16, v19, v24
	v_add_nc_u32_e32 v17, v19, v32
	v_add_nc_u32_e32 v18, v20, v25
	v_add_nc_u32_e32 v19, v33, v20
	v_add_nc_u32_e32 v20, v21, v25
	v_add_nc_u32_e32 v21, v21, v33
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_min3_i32 v12, v13, v12, v18
	v_min3_i32 v10, v10, v15, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_min3_i32 v13, v14, v16, v20
	v_min3_i32 v11, v11, v17, v21
	s_branch .LBB1_4
.LBB1_3:
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr11
                                        ; implicit-def: $vgpr10
                                        ; implicit-def: $vgpr13
                                        ; implicit-def: $vgpr12
.LBB1_4:                                ; %Flow
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB1_6
; %bb.5:                                ; %.preheader.preheader
	v_add_nc_u32_e32 v46, 0x4000, v9
	ds_load_2addr_b64 v[10:13], v46 offset1:32
	ds_load_b128 v[14:17], v8
	ds_load_b128 v[18:21], v8 offset:256
	ds_load_2addr_b64 v[22:25], v46 offset0:64 offset1:96
	ds_load_b128 v[26:29], v8 offset:16
	ds_load_b128 v[30:33], v8 offset:32
	ds_load_b128 v[34:37], v8 offset:48
	ds_load_b128 v[38:41], v8 offset:272
	ds_load_2addr_b64 v[42:45], v46 offset0:128 offset1:160
	ds_load_2addr_b64 v[46:49], v46 offset0:192 offset1:224
	s_waitcnt lgkmcnt(8)
	v_add_nc_u32_e32 v50, v10, v14
	s_waitcnt lgkmcnt(7)
	v_add_nc_u32_e32 v10, v18, v10
	v_add_nc_u32_e32 v14, v11, v14
	v_add_nc_u32_e32 v11, v11, v18
	v_add_nc_u32_e32 v18, v12, v15
	v_add_nc_u32_e32 v15, v13, v15
	v_add_nc_u32_e32 v13, v13, v19
	v_add_nc_u32_e32 v12, v19, v12
	s_waitcnt lgkmcnt(6)
	v_add_nc_u32_e32 v19, v22, v16
	v_add_nc_u32_e32 v22, v20, v22
	v_add_nc_u32_e32 v16, v23, v16
	v_add_nc_u32_e32 v20, v23, v20
	v_add_nc_u32_e32 v23, v24, v17
	v_add_nc_u32_e32 v24, v21, v24
	v_add_nc_u32_e32 v17, v25, v17
	v_add_nc_u32_e32 v21, v25, v21
	v_min3_i32 v5, v5, v14, v15
	v_min3_i32 v7, v7, v11, v13
	v_min3_i32 v4, v4, v50, v18
	v_min3_i32 v6, v6, v10, v12
	s_waitcnt lgkmcnt(1)
	v_add_nc_u32_e32 v14, v42, v26
	v_min3_i32 v16, v5, v16, v17
	v_min3_i32 v17, v7, v20, v21
	v_add_nc_u32_e32 v20, v43, v26
	v_add_nc_u32_e32 v26, 0x4800, v9
	v_min3_i32 v15, v4, v19, v23
	v_min3_i32 v18, v6, v22, v24
	v_add_nc_u32_e32 v19, v38, v42
	v_add_nc_u32_e32 v21, v43, v38
	v_add_nc_u32_e32 v22, v44, v27
	v_add_nc_u32_e32 v23, v39, v44
	v_add_nc_u32_e32 v24, v45, v27
	ds_load_2addr_b64 v[4:7], v26 offset1:32
	v_add_nc_u32_e32 v25, v45, v39
	ds_load_b128 v[10:13], v8 offset:288
	v_min3_i32 v22, v15, v14, v22
	v_min3_i32 v18, v18, v19, v23
	v_min3_i32 v19, v16, v20, v24
	v_min3_i32 v20, v17, v21, v25
	ds_load_2addr_b64 v[14:17], v26 offset0:64 offset1:96
	s_waitcnt lgkmcnt(3)
	v_add_nc_u32_e32 v21, v46, v28
	v_add_nc_u32_e32 v23, v40, v46
	v_add_nc_u32_e32 v24, v47, v28
	v_add_nc_u32_e32 v25, v47, v40
	v_add_nc_u32_e32 v27, v48, v29
	v_add_nc_u32_e32 v28, v41, v48
	v_add_nc_u32_e32 v29, v49, v29
	v_add_nc_u32_e32 v38, v49, v41
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_min3_i32 v27, v22, v21, v27
	v_min3_i32 v28, v18, v23, v28
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_min3_i32 v29, v19, v24, v29
	v_min3_i32 v38, v20, v25, v38
	ds_load_b128 v[18:21], v8 offset:304
	s_waitcnt lgkmcnt(3)
	v_add_nc_u32_e32 v39, v4, v30
	s_waitcnt lgkmcnt(2)
	v_add_nc_u32_e32 v4, v10, v4
	v_add_nc_u32_e32 v30, v5, v30
	v_add_nc_u32_e32 v5, v5, v10
	v_add_nc_u32_e32 v10, v6, v31
	v_add_nc_u32_e32 v6, v11, v6
	v_add_nc_u32_e32 v31, v7, v31
	v_add_nc_u32_e32 v7, v7, v11
	ds_load_2addr_b64 v[22:25], v26 offset0:128 offset1:160
	v_min3_i32 v10, v27, v39, v10
	v_min3_i32 v11, v28, v4, v6
	s_waitcnt lgkmcnt(2)
	v_add_nc_u32_e32 v4, v14, v32
	v_min3_i32 v28, v38, v5, v7
	v_add_nc_u32_e32 v5, v16, v33
	v_min3_i32 v27, v29, v30, v31
	v_add_nc_u32_e32 v14, v12, v14
	v_add_nc_u32_e32 v29, v15, v32
	v_add_nc_u32_e32 v12, v15, v12
	v_min3_i32 v30, v10, v4, v5
	ds_load_2addr_b64 v[4:7], v26 offset0:192 offset1:224
	v_add_nc_u32_e32 v15, v13, v16
	v_add_nc_u32_e32 v16, v17, v33
	v_add_nc_u32_e32 v13, v17, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_min3_i32 v26, v11, v14, v15
	v_min3_i32 v27, v27, v29, v16
	s_delay_alu instid0(VALU_DEP_3)
	v_min3_i32 v28, v28, v12, v13
	s_waitcnt lgkmcnt(1)
	v_add_nc_u32_e32 v29, v22, v34
	v_add_nc_u32_e32 v31, v18, v22
	v_add_nc_u32_e32 v32, v23, v34
	v_add_nc_u32_e32 v18, v23, v18
	v_add_nc_u32_e32 v34, 0x5000, v9
	v_add_nc_u32_e32 v22, v24, v35
	v_add_nc_u32_e32 v33, v19, v24
	v_add_nc_u32_e32 v19, v25, v19
	v_add_nc_u32_e32 v35, v25, v35
	ds_load_2addr_b64 v[10:13], v34 offset1:32
	ds_load_b128 v[14:17], v8 offset:64
	v_min3_i32 v29, v30, v29, v22
	ds_load_b128 v[22:25], v8 offset:320
	v_min3_i32 v18, v28, v18, v19
	s_waitcnt lgkmcnt(3)
	v_add_nc_u32_e32 v19, v4, v36
	v_add_nc_u32_e32 v28, v20, v4
	v_add_nc_u32_e32 v4, v6, v37
	v_min3_i32 v26, v26, v31, v33
	v_min3_i32 v27, v27, v32, v35
	v_add_nc_u32_e32 v30, v5, v36
	v_add_nc_u32_e32 v20, v5, v20
	v_add_nc_u32_e32 v31, v21, v6
	v_add_nc_u32_e32 v32, v7, v37
	v_add_nc_u32_e32 v21, v7, v21
	v_min3_i32 v35, v29, v19, v4
	ds_load_2addr_b64 v[4:7], v34 offset0:64 offset1:96
	v_min3_i32 v36, v26, v28, v31
	v_min3_i32 v37, v27, v30, v32
	v_min3_i32 v38, v18, v20, v21
	ds_load_b128 v[18:21], v8 offset:80
	s_waitcnt lgkmcnt(3)
	v_add_nc_u32_e32 v39, v10, v14
	v_add_nc_u32_e32 v14, v11, v14
	s_waitcnt lgkmcnt(2)
	v_add_nc_u32_e32 v10, v22, v10
	v_add_nc_u32_e32 v11, v11, v22
	v_add_nc_u32_e32 v22, v12, v15
	v_add_nc_u32_e32 v12, v23, v12
	v_add_nc_u32_e32 v15, v13, v15
	v_add_nc_u32_e32 v13, v13, v23
	ds_load_b128 v[26:29], v8 offset:336
	ds_load_2addr_b64 v[30:33], v34 offset0:128 offset1:160
	v_min3_i32 v22, v35, v39, v22
	v_min3_i32 v10, v36, v10, v12
	v_min3_i32 v12, v37, v14, v15
	v_min3_i32 v11, v38, v11, v13
	v_add_nc_u32_e32 v37, 0x5800, v9
	s_waitcnt lgkmcnt(3)
	v_add_nc_u32_e32 v13, v4, v16
	v_add_nc_u32_e32 v14, v24, v4
	v_add_nc_u32_e32 v4, v6, v17
	v_add_nc_u32_e32 v15, v5, v16
	v_add_nc_u32_e32 v16, v5, v24
	v_add_nc_u32_e32 v23, v25, v6
	v_add_nc_u32_e32 v17, v7, v17
	v_add_nc_u32_e32 v24, v7, v25
	v_min3_i32 v22, v22, v13, v4
	ds_load_2addr_b64 v[4:7], v34 offset0:192 offset1:224
	v_min3_i32 v34, v10, v14, v23
	v_min3_i32 v35, v12, v15, v17
	v_min3_i32 v36, v11, v16, v24
	ds_load_2addr_b64 v[10:13], v37 offset1:32
	ds_load_b128 v[14:17], v8 offset:96
	s_waitcnt lgkmcnt(3)
	v_add_nc_u32_e32 v23, v30, v18
	v_add_nc_u32_e32 v30, v26, v30
	v_add_nc_u32_e32 v18, v31, v18
	v_add_nc_u32_e32 v26, v31, v26
	v_add_nc_u32_e32 v24, v32, v19
	v_add_nc_u32_e32 v31, v27, v32
	v_add_nc_u32_e32 v19, v33, v19
	v_add_nc_u32_e32 v27, v33, v27
	s_delay_alu instid0(VALU_DEP_4)
	v_min3_i32 v32, v22, v23, v24
	ds_load_b128 v[22:25], v8 offset:352
	v_min3_i32 v18, v35, v18, v19
	v_min3_i32 v19, v36, v26, v27
	v_min3_i32 v30, v34, v30, v31
	s_waitcnt lgkmcnt(3)
	v_add_nc_u32_e32 v26, v4, v20
	v_add_nc_u32_e32 v27, v28, v4
	v_add_nc_u32_e32 v4, v6, v21
	v_add_nc_u32_e32 v20, v5, v20
	v_add_nc_u32_e32 v28, v5, v28
	v_add_nc_u32_e32 v31, v29, v6
	v_add_nc_u32_e32 v21, v7, v21
	v_add_nc_u32_e32 v29, v7, v29
	v_min3_i32 v34, v32, v26, v4
	ds_load_2addr_b64 v[4:7], v37 offset0:64 offset1:96
	v_min3_i32 v35, v30, v27, v31
	v_min3_i32 v36, v18, v20, v21
	v_min3_i32 v38, v19, v28, v29
	ds_load_b128 v[18:21], v8 offset:112
	s_waitcnt lgkmcnt(3)
	v_add_nc_u32_e32 v39, v10, v14
	s_waitcnt lgkmcnt(2)
	v_add_nc_u32_e32 v10, v22, v10
	v_add_nc_u32_e32 v14, v11, v14
	v_add_nc_u32_e32 v11, v11, v22
	v_add_nc_u32_e32 v22, v12, v15
	v_add_nc_u32_e32 v12, v23, v12
	v_add_nc_u32_e32 v15, v13, v15
	v_add_nc_u32_e32 v13, v13, v23
	ds_load_b128 v[26:29], v8 offset:368
	ds_load_2addr_b64 v[30:33], v37 offset0:128 offset1:160
	v_min3_i32 v22, v34, v39, v22
	v_min3_i32 v10, v35, v10, v12
	v_min3_i32 v12, v36, v14, v15
	v_min3_i32 v11, v38, v11, v13
	s_waitcnt lgkmcnt(3)
	v_add_nc_u32_e32 v13, v4, v16
	v_add_nc_u32_e32 v14, v24, v4
	v_add_nc_u32_e32 v4, v6, v17
	v_add_nc_u32_e32 v15, v5, v16
	v_add_nc_u32_e32 v16, v5, v24
	v_add_nc_u32_e32 v23, v25, v6
	v_add_nc_u32_e32 v17, v7, v17
	v_add_nc_u32_e32 v24, v7, v25
	v_min3_i32 v22, v22, v13, v4
	ds_load_2addr_b64 v[4:7], v37 offset0:192 offset1:224
	v_min3_i32 v34, v10, v14, v23
	v_min3_i32 v35, v12, v15, v17
	v_min3_i32 v36, v11, v16, v24
	v_add_nc_u32_e32 v37, 0x6000, v9
	s_waitcnt lgkmcnt(1)
	v_add_nc_u32_e32 v23, v30, v18
	v_add_nc_u32_e32 v30, v26, v30
	v_add_nc_u32_e32 v18, v31, v18
	v_add_nc_u32_e32 v26, v31, v26
	v_add_nc_u32_e32 v24, v32, v19
	v_add_nc_u32_e32 v31, v27, v32
	v_add_nc_u32_e32 v19, v33, v19
	v_add_nc_u32_e32 v27, v33, v27
	ds_load_2addr_b64 v[10:13], v37 offset1:32
	ds_load_b128 v[14:17], v8 offset:128
	v_min3_i32 v32, v22, v23, v24
	ds_load_b128 v[22:25], v8 offset:384
	v_min3_i32 v18, v35, v18, v19
	v_min3_i32 v19, v36, v26, v27
	v_min3_i32 v30, v34, v30, v31
	s_waitcnt lgkmcnt(3)
	v_add_nc_u32_e32 v26, v4, v20
	v_add_nc_u32_e32 v27, v28, v4
	v_add_nc_u32_e32 v4, v6, v21
	v_add_nc_u32_e32 v20, v5, v20
	v_add_nc_u32_e32 v28, v5, v28
	v_add_nc_u32_e32 v31, v29, v6
	v_add_nc_u32_e32 v21, v7, v21
	v_add_nc_u32_e32 v29, v7, v29
	v_min3_i32 v34, v32, v26, v4
	ds_load_2addr_b64 v[4:7], v37 offset0:64 offset1:96
	v_min3_i32 v35, v30, v27, v31
	v_min3_i32 v36, v18, v20, v21
	v_min3_i32 v38, v19, v28, v29
	ds_load_b128 v[18:21], v8 offset:144
	s_waitcnt lgkmcnt(3)
	v_add_nc_u32_e32 v39, v10, v14
	s_waitcnt lgkmcnt(2)
	v_add_nc_u32_e32 v10, v22, v10
	v_add_nc_u32_e32 v14, v11, v14
	v_add_nc_u32_e32 v11, v11, v22
	v_add_nc_u32_e32 v22, v12, v15
	v_add_nc_u32_e32 v12, v23, v12
	v_add_nc_u32_e32 v15, v13, v15
	v_add_nc_u32_e32 v13, v13, v23
	ds_load_b128 v[26:29], v8 offset:400
	ds_load_2addr_b64 v[30:33], v37 offset0:128 offset1:160
	v_min3_i32 v22, v34, v39, v22
	v_min3_i32 v10, v35, v10, v12
	v_min3_i32 v12, v36, v14, v15
	v_min3_i32 v11, v38, v11, v13
	s_waitcnt lgkmcnt(3)
	v_add_nc_u32_e32 v13, v4, v16
	v_add_nc_u32_e32 v14, v24, v4
	v_add_nc_u32_e32 v4, v6, v17
	v_add_nc_u32_e32 v15, v5, v16
	v_add_nc_u32_e32 v16, v5, v24
	v_add_nc_u32_e32 v23, v25, v6
	v_add_nc_u32_e32 v17, v7, v17
	v_add_nc_u32_e32 v24, v7, v25
	v_min3_i32 v22, v22, v13, v4
	ds_load_2addr_b64 v[4:7], v37 offset0:192 offset1:224
	v_min3_i32 v34, v10, v14, v23
	v_min3_i32 v35, v12, v15, v17
	v_min3_i32 v36, v11, v16, v24
	v_add_nc_u32_e32 v37, 0x6800, v9
	s_waitcnt lgkmcnt(1)
	v_add_nc_u32_e32 v23, v30, v18
	v_add_nc_u32_e32 v30, v26, v30
	v_add_nc_u32_e32 v18, v31, v18
	v_add_nc_u32_e32 v26, v31, v26
	v_add_nc_u32_e32 v24, v32, v19
	v_add_nc_u32_e32 v31, v27, v32
	v_add_nc_u32_e32 v19, v33, v19
	v_add_nc_u32_e32 v27, v33, v27
	ds_load_2addr_b64 v[10:13], v37 offset1:32
	ds_load_b128 v[14:17], v8 offset:160
	v_min3_i32 v32, v22, v23, v24
	ds_load_b128 v[22:25], v8 offset:416
	v_min3_i32 v18, v35, v18, v19
	v_min3_i32 v19, v36, v26, v27
	v_min3_i32 v30, v34, v30, v31
	s_waitcnt lgkmcnt(3)
	v_add_nc_u32_e32 v26, v4, v20
	v_add_nc_u32_e32 v27, v28, v4
	v_add_nc_u32_e32 v4, v6, v21
	v_add_nc_u32_e32 v20, v5, v20
	v_add_nc_u32_e32 v28, v5, v28
	v_add_nc_u32_e32 v31, v29, v6
	v_add_nc_u32_e32 v21, v7, v21
	v_add_nc_u32_e32 v29, v7, v29
	v_min3_i32 v34, v32, v26, v4
	ds_load_2addr_b64 v[4:7], v37 offset0:64 offset1:96
	v_min3_i32 v35, v30, v27, v31
	v_min3_i32 v36, v18, v20, v21
	v_min3_i32 v38, v19, v28, v29
	ds_load_b128 v[18:21], v8 offset:176
	s_waitcnt lgkmcnt(3)
	v_add_nc_u32_e32 v39, v10, v14
	s_waitcnt lgkmcnt(2)
	v_add_nc_u32_e32 v10, v22, v10
	v_add_nc_u32_e32 v14, v11, v14
	v_add_nc_u32_e32 v11, v11, v22
	v_add_nc_u32_e32 v22, v12, v15
	v_add_nc_u32_e32 v12, v23, v12
	v_add_nc_u32_e32 v15, v13, v15
	v_add_nc_u32_e32 v13, v13, v23
	ds_load_b128 v[26:29], v8 offset:432
	ds_load_2addr_b64 v[30:33], v37 offset0:128 offset1:160
	v_min3_i32 v22, v34, v39, v22
	v_min3_i32 v10, v35, v10, v12
	v_min3_i32 v12, v36, v14, v15
	v_min3_i32 v11, v38, v11, v13
	s_waitcnt lgkmcnt(3)
	v_add_nc_u32_e32 v13, v4, v16
	v_add_nc_u32_e32 v14, v24, v4
	v_add_nc_u32_e32 v4, v6, v17
	v_add_nc_u32_e32 v15, v5, v16
	v_add_nc_u32_e32 v16, v5, v24
	v_add_nc_u32_e32 v23, v25, v6
	v_add_nc_u32_e32 v17, v7, v17
	v_add_nc_u32_e32 v24, v7, v25
	v_min3_i32 v22, v22, v13, v4
	ds_load_2addr_b64 v[4:7], v37 offset0:192 offset1:224
	v_min3_i32 v34, v10, v14, v23
	v_min3_i32 v35, v12, v15, v17
	v_min3_i32 v36, v11, v16, v24
	v_add_nc_u32_e32 v37, 0x7000, v9
	s_waitcnt lgkmcnt(1)
	v_add_nc_u32_e32 v23, v30, v18
	v_add_nc_u32_e32 v30, v26, v30
	v_add_nc_u32_e32 v18, v31, v18
	v_add_nc_u32_e32 v26, v31, v26
	v_add_nc_u32_e32 v24, v32, v19
	v_add_nc_u32_e32 v31, v27, v32
	v_add_nc_u32_e32 v19, v33, v19
	v_add_nc_u32_e32 v27, v33, v27
	ds_load_2addr_b64 v[10:13], v37 offset1:32
	ds_load_b128 v[14:17], v8 offset:192
	v_min3_i32 v32, v22, v23, v24
	ds_load_b128 v[22:25], v8 offset:448
	v_min3_i32 v18, v35, v18, v19
	v_min3_i32 v19, v36, v26, v27
	v_min3_i32 v30, v34, v30, v31
	s_waitcnt lgkmcnt(3)
	v_add_nc_u32_e32 v26, v4, v20
	v_add_nc_u32_e32 v27, v28, v4
	v_add_nc_u32_e32 v4, v6, v21
	v_add_nc_u32_e32 v20, v5, v20
	v_add_nc_u32_e32 v28, v5, v28
	v_add_nc_u32_e32 v31, v29, v6
	v_add_nc_u32_e32 v21, v7, v21
	v_add_nc_u32_e32 v29, v7, v29
	v_min3_i32 v34, v32, v26, v4
	ds_load_2addr_b64 v[4:7], v37 offset0:64 offset1:96
	v_min3_i32 v35, v30, v27, v31
	v_min3_i32 v36, v18, v20, v21
	v_min3_i32 v38, v19, v28, v29
	ds_load_b128 v[18:21], v8 offset:208
	s_waitcnt lgkmcnt(3)
	v_add_nc_u32_e32 v39, v10, v14
	s_waitcnt lgkmcnt(2)
	v_add_nc_u32_e32 v10, v22, v10
	v_add_nc_u32_e32 v14, v11, v14
	v_add_nc_u32_e32 v11, v11, v22
	v_add_nc_u32_e32 v22, v12, v15
	v_add_nc_u32_e32 v12, v23, v12
	v_add_nc_u32_e32 v15, v13, v15
	v_add_nc_u32_e32 v13, v13, v23
	ds_load_b128 v[26:29], v8 offset:464
	ds_load_2addr_b64 v[30:33], v37 offset0:128 offset1:160
	v_min3_i32 v22, v34, v39, v22
	v_min3_i32 v10, v35, v10, v12
	v_min3_i32 v12, v36, v14, v15
	v_min3_i32 v11, v38, v11, v13
	s_waitcnt lgkmcnt(3)
	v_add_nc_u32_e32 v13, v4, v16
	v_add_nc_u32_e32 v14, v24, v4
	v_add_nc_u32_e32 v4, v6, v17
	v_add_nc_u32_e32 v15, v5, v16
	v_add_nc_u32_e32 v16, v5, v24
	v_add_nc_u32_e32 v23, v25, v6
	v_add_nc_u32_e32 v17, v7, v17
	v_add_nc_u32_e32 v24, v7, v25
	v_min3_i32 v22, v22, v13, v4
	ds_load_2addr_b64 v[4:7], v37 offset0:192 offset1:224
	v_min3_i32 v34, v10, v14, v23
	v_min3_i32 v17, v12, v15, v17
	v_min3_i32 v35, v11, v16, v24
	s_waitcnt lgkmcnt(1)
	v_add_nc_u32_e32 v23, v30, v18
	v_add_nc_u32_e32 v30, v26, v30
	v_add_nc_u32_e32 v18, v31, v18
	v_add_nc_u32_e32 v26, v31, v26
	v_add_nc_u32_e32 v31, 0x7800, v9
	v_add_nc_u32_e32 v24, v32, v19
	v_add_nc_u32_e32 v32, v27, v32
	v_add_nc_u32_e32 v19, v33, v19
	v_add_nc_u32_e32 v27, v33, v27
	ds_load_2addr_b64 v[9:12], v31 offset1:32
	ds_load_b128 v[13:16], v8 offset:224
	v_min3_i32 v33, v22, v23, v24
	ds_load_b128 v[22:25], v8 offset:480
	v_min3_i32 v17, v17, v18, v19
	v_min3_i32 v18, v35, v26, v27
	v_min3_i32 v30, v34, v30, v32
	s_waitcnt lgkmcnt(3)
	v_add_nc_u32_e32 v19, v4, v20
	v_add_nc_u32_e32 v26, v28, v4
	v_add_nc_u32_e32 v4, v6, v21
	v_add_nc_u32_e32 v20, v5, v20
	v_add_nc_u32_e32 v27, v5, v28
	v_add_nc_u32_e32 v28, v29, v6
	v_add_nc_u32_e32 v21, v7, v21
	v_add_nc_u32_e32 v29, v7, v29
	v_min3_i32 v32, v33, v19, v4
	ds_load_2addr_b64 v[4:7], v31 offset0:64 offset1:96
	v_min3_i32 v30, v30, v26, v28
	v_min3_i32 v21, v17, v20, v21
	v_min3_i32 v33, v18, v27, v29
	ds_load_b128 v[17:20], v8 offset:240
	s_waitcnt lgkmcnt(3)
	v_add_nc_u32_e32 v34, v9, v13
	ds_load_b128 v[26:29], v8 offset:496
	s_waitcnt lgkmcnt(3)
	v_add_nc_u32_e32 v35, v22, v9
	v_add_nc_u32_e32 v13, v10, v13
	v_add_nc_u32_e32 v22, v10, v22
	v_add_nc_u32_e32 v36, v11, v14
	v_add_nc_u32_e32 v37, v23, v11
	v_add_nc_u32_e32 v14, v12, v14
	v_add_nc_u32_e32 v12, v12, v23
	ds_load_2addr_b64 v[8:11], v31 offset0:128 offset1:160
	v_min3_i32 v23, v32, v34, v36
	v_min3_i32 v30, v30, v35, v37
	v_min3_i32 v21, v21, v13, v14
	v_min3_i32 v22, v33, v22, v12
	s_waitcnt lgkmcnt(3)
	v_add_nc_u32_e32 v32, v4, v15
	v_add_nc_u32_e32 v33, v5, v15
	ds_load_2addr_b64 v[12:15], v31 offset0:192 offset1:224
	v_add_nc_u32_e32 v4, v24, v4
	v_add_nc_u32_e32 v5, v5, v24
	v_add_nc_u32_e32 v24, v6, v16
	v_add_nc_u32_e32 v6, v25, v6
	v_add_nc_u32_e32 v16, v7, v16
	v_add_nc_u32_e32 v7, v7, v25
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_min3_i32 v23, v23, v32, v24
	v_min3_i32 v4, v30, v4, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_min3_i32 v6, v21, v33, v16
	v_min3_i32 v5, v22, v5, v7
	s_waitcnt lgkmcnt(1)
	v_add_nc_u32_e32 v7, v8, v17
	v_add_nc_u32_e32 v8, v26, v8
	v_add_nc_u32_e32 v16, v9, v17
	v_add_nc_u32_e32 v9, v9, v26
	v_add_nc_u32_e32 v17, v10, v18
	v_add_nc_u32_e32 v10, v27, v10
	v_add_nc_u32_e32 v18, v11, v18
	v_add_nc_u32_e32 v11, v11, v27
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_min3_i32 v7, v23, v7, v17
	v_min3_i32 v4, v4, v8, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_min3_i32 v6, v6, v16, v18
	v_min3_i32 v5, v5, v9, v11
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v8, v12, v19
	v_add_nc_u32_e32 v9, v28, v12
	v_add_nc_u32_e32 v11, v13, v19
	v_add_nc_u32_e32 v16, v13, v28
	v_add_nc_u32_e32 v10, v14, v20
	v_add_nc_u32_e32 v13, v29, v14
	v_add_nc_u32_e32 v14, v15, v20
	v_add_nc_u32_e32 v15, v15, v29
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_min3_i32 v12, v7, v8, v10
	v_min3_i32 v10, v4, v9, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_min3_i32 v13, v6, v11, v14
	v_min3_i32 v11, v5, v16, v15
.LBB1_6:                                ; %.loopexit
	s_barrier
	buffer_gl0_inv
	s_clause 0x3
	global_store_b32 v[0:1], v12, off
	global_store_b32 v[2:3], v10, off
	global_store_b32 v[0:1], v13, off offset:4
	global_store_b32 v[2:3], v11, off offset:4
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
.LBB1_7:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10cal_phase2Piii
		.amdhsa_group_segment_fixed_size 32768
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 16
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 51
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z10cal_phase2Piii, .Lfunc_end1-_Z10cal_phase2Piii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 6136
; NumSgprs: 18
; NumVgprs: 51
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 32768 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 6
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 51
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z10cal_phase3Piii      ; -- Begin function _Z10cal_phase3Piii
	.globl	_Z10cal_phase3Piii
	.p2align	8
	.type	_Z10cal_phase3Piii,@function
_Z10cal_phase3Piii:                     ; @_Z10cal_phase3Piii
; %bb.0:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_bfe_u32 v8, v0, 10, 10
	v_and_b32_e32 v5, 0x3ff, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v9, 1, v8
	v_lshlrev_b32_e32 v10, 1, v5
	v_lshlrev_b32_e32 v5, 3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_lshl_add_u32 v2, s14, 6, v10
	s_waitcnt lgkmcnt(0)
	s_lshl_b32 s3, s3, 6
	v_add_nc_u32_e32 v3, s3, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, v3, s2, v[2:3]
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[0:1]
	v_add_nc_u32_e32 v0, s2, v0
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	global_load_b64 v[6:7], v[3:4], off
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_load_b64 v[0:1], v[0:1], off
	v_lshlrev_b32_e32 v4, 9, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v3, v4, v5
	s_waitcnt vmcnt(0)
	ds_store_2addr_b64 v3, v[6:7], v[0:1] offset1:32
	v_lshl_add_u32 v0, s15, 6, v9
	v_add_nc_u32_e32 v3, s3, v10
	v_add3_u32 v9, 0x4000, v4, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v8, v0, s2
	v_add_nc_u32_e32 v10, s2, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v0, v3, v8
	v_add_nc_u32_e32 v6, v3, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v1, 31, v0
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v6, vcc_lo, s0, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v7, vcc_lo
	s_clause 0x1
	global_load_b64 v[0:1], v[0:1], off
	global_load_b64 v[6:7], v[6:7], off
	s_waitcnt vmcnt(0)
	ds_store_2addr_b64 v9, v[0:1], v[6:7] offset1:32
	v_add_nc_u32_e32 v0, v8, v2
	v_add_nc_u32_e32 v2, v10, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v1, 31, v0
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	s_clause 0x1
	global_load_b64 v[30:31], v[0:1], off
	global_load_b64 v[32:33], v[2:3], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b128 v[6:9], v4 offset:16384
	ds_load_b128 v[10:13], v4 offset:16400
	ds_load_b128 v[14:17], v4 offset:16416
	ds_load_b128 v[18:21], v4 offset:16432
	ds_load_2addr_b64 v[22:25], v5 offset1:32
	ds_load_b128 v[26:29], v4 offset:16640
	s_waitcnt lgkmcnt(1)
	v_add_nc_u32_e32 v34, v22, v6
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v22, v26, v22
	v_add_nc_u32_e32 v6, v23, v6
	v_add_nc_u32_e32 v23, v23, v26
	v_add_nc_u32_e32 v26, v24, v7
	v_add_nc_u32_e32 v7, v25, v7
	v_add_nc_u32_e32 v24, v27, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_min3_i32 v6, v31, v6, v7
	v_add_nc_u32_e32 v7, v25, v27
	v_min3_i32 v26, v30, v34, v26
	v_min3_i32 v30, v32, v22, v24
	s_delay_alu instid0(VALU_DEP_3)
	v_min3_i32 v7, v33, v23, v7
	ds_load_2addr_b64 v[22:25], v5 offset0:64 offset1:96
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v27, v22, v8
	v_add_nc_u32_e32 v22, v28, v22
	v_add_nc_u32_e32 v8, v23, v8
	v_add_nc_u32_e32 v23, v23, v28
	v_add_nc_u32_e32 v28, v24, v9
	v_add_nc_u32_e32 v9, v25, v9
	v_add_nc_u32_e32 v24, v29, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_min3_i32 v26, v26, v27, v28
	v_min3_i32 v28, v6, v8, v9
	v_add_nc_u32_e32 v6, v25, v29
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min3_i32 v27, v30, v22, v24
	v_min3_i32 v29, v7, v23, v6
	ds_load_2addr_b64 v[6:9], v5 offset0:128 offset1:160
	ds_load_b128 v[22:25], v4 offset:16656
	s_waitcnt lgkmcnt(1)
	v_add_nc_u32_e32 v30, v6, v10
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v6, v22, v6
	v_add_nc_u32_e32 v10, v7, v10
	v_add_nc_u32_e32 v7, v7, v22
	v_add_nc_u32_e32 v22, v8, v11
	v_add_nc_u32_e32 v8, v23, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min3_i32 v22, v26, v30, v22
	v_min3_i32 v26, v27, v6, v8
	v_add_nc_u32_e32 v6, v9, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_min3_i32 v10, v28, v10, v6
	v_add_nc_u32_e32 v6, v9, v23
	v_min3_i32 v11, v29, v7, v6
	ds_load_2addr_b64 v[6:9], v5 offset0:192 offset1:224
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v23, v6, v12
	v_add_nc_u32_e32 v6, v24, v6
	v_add_nc_u32_e32 v12, v7, v12
	v_add_nc_u32_e32 v7, v7, v24
	v_add_nc_u32_e32 v24, v8, v13
	v_add_nc_u32_e32 v8, v25, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min3_i32 v22, v22, v23, v24
	v_min3_i32 v23, v26, v6, v8
	v_add_nc_u32_e32 v6, v9, v13
	v_add_nc_u32_e32 v26, 0x800, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_min3_i32 v24, v10, v12, v6
	v_add_nc_u32_e32 v6, v9, v25
	v_min3_i32 v25, v11, v7, v6
	ds_load_2addr_b64 v[6:9], v26 offset1:32
	ds_load_b128 v[10:13], v4 offset:16672
	s_waitcnt lgkmcnt(1)
	v_add_nc_u32_e32 v27, v6, v14
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v6, v10, v6
	v_add_nc_u32_e32 v14, v7, v14
	v_add_nc_u32_e32 v7, v7, v10
	v_add_nc_u32_e32 v10, v8, v15
	v_add_nc_u32_e32 v8, v11, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min3_i32 v10, v22, v27, v10
	v_min3_i32 v22, v23, v6, v8
	v_add_nc_u32_e32 v6, v9, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_min3_i32 v14, v24, v14, v6
	v_add_nc_u32_e32 v6, v9, v11
	v_min3_i32 v11, v25, v7, v6
	ds_load_2addr_b64 v[6:9], v26 offset0:64 offset1:96
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v15, v6, v16
	v_add_nc_u32_e32 v6, v12, v6
	v_add_nc_u32_e32 v16, v7, v16
	v_add_nc_u32_e32 v7, v7, v12
	v_add_nc_u32_e32 v12, v8, v17
	v_add_nc_u32_e32 v8, v13, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min3_i32 v15, v10, v15, v12
	v_min3_i32 v22, v22, v6, v8
	v_add_nc_u32_e32 v6, v9, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_min3_i32 v14, v14, v16, v6
	v_add_nc_u32_e32 v6, v9, v13
	v_min3_i32 v16, v11, v7, v6
	ds_load_2addr_b64 v[6:9], v26 offset0:128 offset1:160
	ds_load_b128 v[10:13], v4 offset:16688
	s_waitcnt lgkmcnt(1)
	v_add_nc_u32_e32 v17, v6, v18
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v6, v10, v6
	v_add_nc_u32_e32 v18, v7, v18
	v_add_nc_u32_e32 v7, v7, v10
	v_add_nc_u32_e32 v10, v8, v19
	v_add_nc_u32_e32 v8, v11, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min3_i32 v10, v15, v17, v10
	v_min3_i32 v15, v22, v6, v8
	v_add_nc_u32_e32 v6, v9, v19
	v_add_nc_u32_e32 v22, 0x1000, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_min3_i32 v14, v14, v18, v6
	v_add_nc_u32_e32 v6, v9, v11
	v_min3_i32 v11, v16, v7, v6
	ds_load_2addr_b64 v[6:9], v26 offset0:192 offset1:224
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v16, v6, v20
	v_add_nc_u32_e32 v6, v12, v6
	v_add_nc_u32_e32 v17, v7, v20
	v_add_nc_u32_e32 v7, v7, v12
	v_add_nc_u32_e32 v12, v8, v21
	v_add_nc_u32_e32 v8, v13, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min3_i32 v18, v10, v16, v12
	v_min3_i32 v19, v15, v6, v8
	v_add_nc_u32_e32 v6, v9, v21
	s_delay_alu instid0(VALU_DEP_1)
	v_min3_i32 v20, v14, v17, v6
	v_add_nc_u32_e32 v6, v9, v13
	ds_load_b128 v[14:17], v4 offset:16704
	v_min3_i32 v21, v11, v7, v6
	ds_load_b128 v[6:9], v4 offset:16448
	ds_load_2addr_b64 v[10:13], v22 offset1:32
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v23, v10, v6
	v_add_nc_u32_e32 v10, v14, v10
	v_add_nc_u32_e32 v6, v11, v6
	v_add_nc_u32_e32 v11, v11, v14
	v_add_nc_u32_e32 v14, v12, v7
	v_add_nc_u32_e32 v7, v13, v7
	v_add_nc_u32_e32 v12, v15, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_min3_i32 v14, v18, v23, v14
	v_min3_i32 v6, v20, v6, v7
	v_add_nc_u32_e32 v7, v13, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min3_i32 v18, v19, v10, v12
	v_min3_i32 v7, v21, v11, v7
	ds_load_2addr_b64 v[10:13], v22 offset0:64 offset1:96
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v15, v10, v8
	v_add_nc_u32_e32 v10, v16, v10
	v_add_nc_u32_e32 v8, v11, v8
	v_add_nc_u32_e32 v11, v11, v16
	v_add_nc_u32_e32 v16, v12, v9
	v_add_nc_u32_e32 v9, v13, v9
	v_add_nc_u32_e32 v12, v17, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_min3_i32 v19, v14, v15, v16
	v_min3_i32 v20, v6, v8, v9
	v_add_nc_u32_e32 v6, v13, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min3_i32 v18, v18, v10, v12
	v_min3_i32 v21, v7, v11, v6
	ds_load_b128 v[6:9], v4 offset:16464
	ds_load_2addr_b64 v[10:13], v22 offset0:128 offset1:160
	ds_load_b128 v[14:17], v4 offset:16720
	s_waitcnt lgkmcnt(1)
	v_add_nc_u32_e32 v23, v10, v6
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v10, v14, v10
	v_add_nc_u32_e32 v6, v11, v6
	v_add_nc_u32_e32 v11, v11, v14
	v_add_nc_u32_e32 v14, v12, v7
	v_add_nc_u32_e32 v7, v13, v7
	v_add_nc_u32_e32 v12, v15, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_min3_i32 v14, v19, v23, v14
	v_min3_i32 v6, v20, v6, v7
	v_add_nc_u32_e32 v7, v13, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min3_i32 v18, v18, v10, v12
	v_min3_i32 v7, v21, v11, v7
	ds_load_2addr_b64 v[10:13], v22 offset0:192 offset1:224
	v_add_nc_u32_e32 v22, 0x1800, v5
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v15, v10, v8
	v_add_nc_u32_e32 v10, v16, v10
	v_add_nc_u32_e32 v8, v11, v8
	v_add_nc_u32_e32 v11, v11, v16
	v_add_nc_u32_e32 v16, v12, v9
	v_add_nc_u32_e32 v9, v13, v9
	v_add_nc_u32_e32 v12, v17, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_min3_i32 v19, v14, v15, v16
	v_min3_i32 v20, v6, v8, v9
	v_add_nc_u32_e32 v6, v13, v17
	s_delay_alu instid0(VALU_DEP_4)
	v_min3_i32 v18, v18, v10, v12
	ds_load_b128 v[14:17], v4 offset:16736
	v_min3_i32 v21, v7, v11, v6
	ds_load_b128 v[6:9], v4 offset:16480
	ds_load_2addr_b64 v[10:13], v22 offset1:32
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v23, v10, v6
	v_add_nc_u32_e32 v10, v14, v10
	v_add_nc_u32_e32 v6, v11, v6
	v_add_nc_u32_e32 v11, v11, v14
	v_add_nc_u32_e32 v14, v12, v7
	v_add_nc_u32_e32 v7, v13, v7
	v_add_nc_u32_e32 v12, v15, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_min3_i32 v14, v19, v23, v14
	v_min3_i32 v6, v20, v6, v7
	v_add_nc_u32_e32 v7, v13, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min3_i32 v18, v18, v10, v12
	v_min3_i32 v7, v21, v11, v7
	ds_load_2addr_b64 v[10:13], v22 offset0:64 offset1:96
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v15, v10, v8
	v_add_nc_u32_e32 v10, v16, v10
	v_add_nc_u32_e32 v8, v11, v8
	v_add_nc_u32_e32 v11, v11, v16
	v_add_nc_u32_e32 v16, v12, v9
	v_add_nc_u32_e32 v9, v13, v9
	v_add_nc_u32_e32 v12, v17, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_min3_i32 v19, v14, v15, v16
	v_min3_i32 v20, v6, v8, v9
	v_add_nc_u32_e32 v6, v13, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min3_i32 v18, v18, v10, v12
	v_min3_i32 v21, v7, v11, v6
	ds_load_b128 v[6:9], v4 offset:16496
	ds_load_2addr_b64 v[10:13], v22 offset0:128 offset1:160
	ds_load_b128 v[14:17], v4 offset:16752
	s_waitcnt lgkmcnt(1)
	v_add_nc_u32_e32 v23, v10, v6
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v10, v14, v10
	v_add_nc_u32_e32 v6, v11, v6
	v_add_nc_u32_e32 v11, v11, v14
	v_add_nc_u32_e32 v14, v12, v7
	v_add_nc_u32_e32 v7, v13, v7
	v_add_nc_u32_e32 v12, v15, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_min3_i32 v14, v19, v23, v14
	v_min3_i32 v6, v20, v6, v7
	v_add_nc_u32_e32 v7, v13, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min3_i32 v18, v18, v10, v12
	v_min3_i32 v7, v21, v11, v7
	ds_load_2addr_b64 v[10:13], v22 offset0:192 offset1:224
	v_add_nc_u32_e32 v22, 0x2000, v5
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v15, v10, v8
	v_add_nc_u32_e32 v10, v16, v10
	v_add_nc_u32_e32 v8, v11, v8
	v_add_nc_u32_e32 v11, v11, v16
	v_add_nc_u32_e32 v16, v12, v9
	v_add_nc_u32_e32 v9, v13, v9
	v_add_nc_u32_e32 v12, v17, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_min3_i32 v19, v14, v15, v16
	v_min3_i32 v20, v6, v8, v9
	v_add_nc_u32_e32 v6, v13, v17
	s_delay_alu instid0(VALU_DEP_4)
	v_min3_i32 v18, v18, v10, v12
	ds_load_b128 v[14:17], v4 offset:16768
	v_min3_i32 v21, v7, v11, v6
	ds_load_b128 v[6:9], v4 offset:16512
	ds_load_2addr_b64 v[10:13], v22 offset1:32
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v23, v10, v6
	v_add_nc_u32_e32 v10, v14, v10
	v_add_nc_u32_e32 v6, v11, v6
	v_add_nc_u32_e32 v11, v11, v14
	v_add_nc_u32_e32 v14, v12, v7
	v_add_nc_u32_e32 v7, v13, v7
	v_add_nc_u32_e32 v12, v15, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_min3_i32 v14, v19, v23, v14
	v_min3_i32 v6, v20, v6, v7
	v_add_nc_u32_e32 v7, v13, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min3_i32 v18, v18, v10, v12
	v_min3_i32 v7, v21, v11, v7
	ds_load_2addr_b64 v[10:13], v22 offset0:64 offset1:96
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v15, v10, v8
	v_add_nc_u32_e32 v10, v16, v10
	v_add_nc_u32_e32 v8, v11, v8
	v_add_nc_u32_e32 v11, v11, v16
	v_add_nc_u32_e32 v16, v12, v9
	v_add_nc_u32_e32 v9, v13, v9
	v_add_nc_u32_e32 v12, v17, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_min3_i32 v19, v14, v15, v16
	v_min3_i32 v20, v6, v8, v9
	v_add_nc_u32_e32 v6, v13, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min3_i32 v18, v18, v10, v12
	v_min3_i32 v21, v7, v11, v6
	ds_load_b128 v[6:9], v4 offset:16528
	ds_load_2addr_b64 v[10:13], v22 offset0:128 offset1:160
	ds_load_b128 v[14:17], v4 offset:16784
	s_waitcnt lgkmcnt(1)
	v_add_nc_u32_e32 v23, v10, v6
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v10, v14, v10
	v_add_nc_u32_e32 v6, v11, v6
	v_add_nc_u32_e32 v11, v11, v14
	v_add_nc_u32_e32 v14, v12, v7
	v_add_nc_u32_e32 v7, v13, v7
	v_add_nc_u32_e32 v12, v15, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_min3_i32 v14, v19, v23, v14
	v_min3_i32 v6, v20, v6, v7
	v_add_nc_u32_e32 v7, v13, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min3_i32 v18, v18, v10, v12
	v_min3_i32 v7, v21, v11, v7
	ds_load_2addr_b64 v[10:13], v22 offset0:192 offset1:224
	v_add_nc_u32_e32 v22, 0x2800, v5
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v15, v10, v8
	v_add_nc_u32_e32 v10, v16, v10
	v_add_nc_u32_e32 v8, v11, v8
	v_add_nc_u32_e32 v11, v11, v16
	v_add_nc_u32_e32 v16, v12, v9
	v_add_nc_u32_e32 v9, v13, v9
	v_add_nc_u32_e32 v12, v17, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_min3_i32 v19, v14, v15, v16
	v_min3_i32 v20, v6, v8, v9
	v_add_nc_u32_e32 v6, v13, v17
	s_delay_alu instid0(VALU_DEP_4)
	v_min3_i32 v18, v18, v10, v12
	ds_load_b128 v[14:17], v4 offset:16800
	v_min3_i32 v21, v7, v11, v6
	ds_load_b128 v[6:9], v4 offset:16544
	ds_load_2addr_b64 v[10:13], v22 offset1:32
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v23, v10, v6
	v_add_nc_u32_e32 v10, v14, v10
	v_add_nc_u32_e32 v6, v11, v6
	v_add_nc_u32_e32 v11, v11, v14
	v_add_nc_u32_e32 v14, v12, v7
	v_add_nc_u32_e32 v7, v13, v7
	v_add_nc_u32_e32 v12, v15, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_min3_i32 v14, v19, v23, v14
	v_min3_i32 v6, v20, v6, v7
	v_add_nc_u32_e32 v7, v13, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min3_i32 v18, v18, v10, v12
	v_min3_i32 v7, v21, v11, v7
	ds_load_2addr_b64 v[10:13], v22 offset0:64 offset1:96
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v15, v10, v8
	v_add_nc_u32_e32 v10, v16, v10
	v_add_nc_u32_e32 v8, v11, v8
	v_add_nc_u32_e32 v11, v11, v16
	v_add_nc_u32_e32 v16, v12, v9
	v_add_nc_u32_e32 v9, v13, v9
	v_add_nc_u32_e32 v12, v17, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_min3_i32 v19, v14, v15, v16
	v_min3_i32 v20, v6, v8, v9
	v_add_nc_u32_e32 v6, v13, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min3_i32 v18, v18, v10, v12
	v_min3_i32 v21, v7, v11, v6
	ds_load_b128 v[6:9], v4 offset:16560
	ds_load_2addr_b64 v[10:13], v22 offset0:128 offset1:160
	ds_load_b128 v[14:17], v4 offset:16816
	s_waitcnt lgkmcnt(1)
	v_add_nc_u32_e32 v23, v10, v6
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v10, v14, v10
	v_add_nc_u32_e32 v6, v11, v6
	v_add_nc_u32_e32 v11, v11, v14
	v_add_nc_u32_e32 v14, v12, v7
	v_add_nc_u32_e32 v7, v13, v7
	v_add_nc_u32_e32 v12, v15, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_min3_i32 v14, v19, v23, v14
	v_min3_i32 v6, v20, v6, v7
	v_add_nc_u32_e32 v7, v13, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min3_i32 v18, v18, v10, v12
	v_min3_i32 v7, v21, v11, v7
	ds_load_2addr_b64 v[10:13], v22 offset0:192 offset1:224
	v_add_nc_u32_e32 v22, 0x3000, v5
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v15, v10, v8
	v_add_nc_u32_e32 v10, v16, v10
	v_add_nc_u32_e32 v8, v11, v8
	v_add_nc_u32_e32 v11, v11, v16
	v_add_nc_u32_e32 v16, v12, v9
	v_add_nc_u32_e32 v9, v13, v9
	v_add_nc_u32_e32 v12, v17, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_min3_i32 v19, v14, v15, v16
	v_min3_i32 v20, v6, v8, v9
	v_add_nc_u32_e32 v6, v13, v17
	s_delay_alu instid0(VALU_DEP_4)
	v_min3_i32 v18, v18, v10, v12
	ds_load_b128 v[14:17], v4 offset:16832
	v_min3_i32 v21, v7, v11, v6
	ds_load_b128 v[6:9], v4 offset:16576
	ds_load_2addr_b64 v[10:13], v22 offset1:32
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v23, v10, v6
	v_add_nc_u32_e32 v10, v14, v10
	v_add_nc_u32_e32 v6, v11, v6
	v_add_nc_u32_e32 v11, v11, v14
	v_add_nc_u32_e32 v14, v12, v7
	v_add_nc_u32_e32 v7, v13, v7
	v_add_nc_u32_e32 v12, v15, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_min3_i32 v14, v19, v23, v14
	v_min3_i32 v6, v20, v6, v7
	v_add_nc_u32_e32 v7, v13, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min3_i32 v18, v18, v10, v12
	v_min3_i32 v7, v21, v11, v7
	ds_load_2addr_b64 v[10:13], v22 offset0:64 offset1:96
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v15, v10, v8
	v_add_nc_u32_e32 v10, v16, v10
	v_add_nc_u32_e32 v8, v11, v8
	v_add_nc_u32_e32 v11, v11, v16
	v_add_nc_u32_e32 v16, v12, v9
	v_add_nc_u32_e32 v9, v13, v9
	v_add_nc_u32_e32 v12, v17, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_min3_i32 v19, v14, v15, v16
	v_min3_i32 v20, v6, v8, v9
	v_add_nc_u32_e32 v6, v13, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min3_i32 v18, v18, v10, v12
	v_min3_i32 v21, v7, v11, v6
	ds_load_b128 v[6:9], v4 offset:16592
	ds_load_2addr_b64 v[10:13], v22 offset0:128 offset1:160
	ds_load_b128 v[14:17], v4 offset:16848
	s_waitcnt lgkmcnt(1)
	v_add_nc_u32_e32 v23, v10, v6
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v10, v14, v10
	v_add_nc_u32_e32 v6, v11, v6
	v_add_nc_u32_e32 v11, v11, v14
	v_add_nc_u32_e32 v14, v12, v7
	v_add_nc_u32_e32 v7, v13, v7
	v_add_nc_u32_e32 v12, v15, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_min3_i32 v14, v19, v23, v14
	v_min3_i32 v6, v20, v6, v7
	v_add_nc_u32_e32 v7, v13, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min3_i32 v18, v18, v10, v12
	v_min3_i32 v7, v21, v11, v7
	ds_load_2addr_b64 v[10:13], v22 offset0:192 offset1:224
	v_add_nc_u32_e32 v22, 0x3800, v5
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v15, v10, v8
	v_add_nc_u32_e32 v10, v16, v10
	v_add_nc_u32_e32 v8, v11, v8
	v_add_nc_u32_e32 v11, v11, v16
	v_add_nc_u32_e32 v16, v12, v9
	v_add_nc_u32_e32 v9, v13, v9
	v_add_nc_u32_e32 v12, v17, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_min3_i32 v19, v14, v15, v16
	v_min3_i32 v20, v6, v8, v9
	v_add_nc_u32_e32 v6, v13, v17
	s_delay_alu instid0(VALU_DEP_4)
	v_min3_i32 v18, v18, v10, v12
	ds_load_b128 v[14:17], v4 offset:16864
	v_min3_i32 v21, v7, v11, v6
	ds_load_b128 v[6:9], v4 offset:16608
	ds_load_2addr_b64 v[10:13], v22 offset1:32
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v5, v10, v6
	v_add_nc_u32_e32 v10, v14, v10
	v_add_nc_u32_e32 v6, v11, v6
	v_add_nc_u32_e32 v11, v11, v14
	v_add_nc_u32_e32 v14, v12, v7
	v_add_nc_u32_e32 v7, v13, v7
	v_add_nc_u32_e32 v12, v15, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_min3_i32 v5, v19, v5, v14
	v_min3_i32 v6, v20, v6, v7
	v_add_nc_u32_e32 v7, v13, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min3_i32 v14, v18, v10, v12
	v_min3_i32 v7, v21, v11, v7
	ds_load_2addr_b64 v[10:13], v22 offset0:64 offset1:96
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v15, v10, v8
	v_add_nc_u32_e32 v10, v16, v10
	v_add_nc_u32_e32 v8, v11, v8
	v_add_nc_u32_e32 v11, v11, v16
	v_add_nc_u32_e32 v16, v12, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_min3_i32 v18, v5, v15, v16
	v_add_nc_u32_e32 v5, v17, v12
	v_min3_i32 v19, v14, v10, v5
	v_add_nc_u32_e32 v5, v13, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_min3_i32 v20, v6, v8, v5
	v_add_nc_u32_e32 v5, v13, v17
	v_min3_i32 v17, v7, v11, v5
	ds_load_b128 v[5:8], v4 offset:16624
	ds_load_2addr_b64 v[9:12], v22 offset0:128 offset1:160
	ds_load_b128 v[13:16], v4 offset:16880
	s_waitcnt lgkmcnt(1)
	v_add_nc_u32_e32 v21, v9, v5
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v13, v9
	v_add_nc_u32_e32 v5, v10, v5
	v_add_nc_u32_e32 v9, v10, v13
	v_add_nc_u32_e32 v10, v11, v6
	v_add_nc_u32_e32 v6, v12, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_min3_i32 v13, v18, v21, v10
	v_add_nc_u32_e32 v10, v14, v11
	v_min3_i32 v5, v20, v5, v6
	v_add_nc_u32_e32 v6, v12, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min3_i32 v4, v19, v4, v10
	v_min3_i32 v6, v17, v9, v6
	ds_load_2addr_b64 v[9:12], v22 offset0:192 offset1:224
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_add_nc_u32_e32 v14, v9, v7
	v_add_nc_u32_e32 v9, v15, v9
	v_add_nc_u32_e32 v7, v10, v7
	v_add_nc_u32_e32 v10, v10, v15
	v_add_nc_u32_e32 v15, v11, v8
	v_add_nc_u32_e32 v8, v12, v8
	v_add_nc_u32_e32 v11, v16, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_min3_i32 v13, v13, v14, v15
	v_min3_i32 v5, v5, v7, v8
	v_add_nc_u32_e32 v7, v12, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_min3_i32 v4, v4, v9, v11
	v_min3_i32 v6, v6, v10, v7
	s_clause 0x3
	global_store_b32 v[0:1], v13, off
	global_store_b32 v[2:3], v4, off
	global_store_b32 v[0:1], v5, off offset:4
	global_store_b32 v[2:3], v6, off offset:4
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10cal_phase3Piii
		.amdhsa_group_segment_fixed_size 32768
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 16
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 35
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z10cal_phase3Piii, .Lfunc_end2-_Z10cal_phase3Piii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3544
; NumSgprs: 18
; NumVgprs: 35
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 32768 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 35
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 16384
    .kernarg_segment_align: 8
    .kernarg_segment_size: 16
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10cal_phase1Piii
    .private_segment_fixed_size: 0
    .sgpr_count:     6
    .sgpr_spill_count: 0
    .symbol:         _Z10cal_phase1Piii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     14
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 32768
    .kernarg_segment_align: 8
    .kernarg_segment_size: 16
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10cal_phase2Piii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z10cal_phase2Piii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     51
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 32768
    .kernarg_segment_align: 8
    .kernarg_segment_size: 16
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10cal_phase3Piii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z10cal_phase3Piii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     35
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
