
#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <iostream>
#include <stdio.h>
using namespace std;
#define N 3 //rowsize
#define M 4 // columnsize
const int blockNUM = 4;
const int threadNUM =3;
void mxv(const int rowsize,const int columnsize,
         const float*matrix,const float*v,float*r)
         {
             for(int i=0;i<rowsize;i++)
             {
                 float re=0.0f;
                 for(int j=0;j<columnsize;j++)
                    re+=(matrix[i*columnsize+j]*v[j]);
                 r[i]=re;
             }
			 cout <<"CPU:";
             for(int i=0;i<rowsize;i++)
                cout << r[i]<< " ";
             cout <<endl;
         }

static void __global__ mxvNaive(int rowSize, int columnSize, int columnPitch,
const float *d_matrix, const float *d_vec, float *d_r)
  {
      int id = threadIdx.x+blockIdx.x*blockDim.x;
      if(id<rowSize)
      {
          float temp=0;
          for(int i=0;i<columnSize;i++)
          {
              temp+=d_matrix[id*columnPitch+i]*d_vec[i];
          }
          d_r[id]=temp;
      }
}
int main()
{
    float *matrix=(float*)malloc(N*M*sizeof(float));
	float *vec=(float*)malloc(M*sizeof(float));
	float *r =(float*)malloc(N*sizeof(float));
	float *dev_matrix,*dev_vec,*dev_r;
	cudaMalloc((void**)&dev_vec,M*sizeof(float));
	cudaMalloc((void**)&dev_matrix,M*N*sizeof(float));
	cudaMalloc((void**)&dev_r,N*sizeof(float));
	for(int i=1;i<=N*M;i++)
		matrix[i-1]=i;
		for(int i=0;i<M;i++)
            vec[i]=i+1;
	cudaMemcpy(dev_matrix,matrix,M*N*sizeof(float),cudaMemcpyHostToDevice);
	cudaMemcpy(dev_vec,vec,M*sizeof(float),cudaMemcpyHostToDevice);
	mxvNaive<<<blockNUM,threadNUM>>> (N,M,M,dev_matrix,dev_vec,dev_r);
	cudaMemcpy(r,dev_r,N*sizeof(float),cudaMemcpyDeviceToHost);
	cout << "GPU:";
	for(int i=0;i<N;i++)
		cout <<r[i]<<" ";
	cout <<endl;
	mxv(N,M,matrix,vec,r);
    return 0;
}

	.file	"tmpxft_002c0f94_00000000-6_kernel.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3639:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3639:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_ZL36__device_stub__Z8mxvNaiveiiiPKfS0_PfiiiPKfS0_Pf, @function
_ZL36__device_stub__Z8mxvNaiveiiiPKfS0_PfiiiPKfS0_Pf:
.LFB3661:
	.cfi_startproc
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movl	%edi, 44(%rsp)
	leaq	72(%rsp), %rdi
	movl	%esi, 40(%rsp)
	leaq	84(%rsp), %rsi
	movl	%edx, 36(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 24(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movq	%r9, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_ZL8mxvNaiveiiiPKfS0_Pf(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3661:
	.size	_ZL36__device_stub__Z8mxvNaiveiiiPKfS0_PfiiiPKfS0_Pf, .-_ZL36__device_stub__Z8mxvNaiveiiiPKfS0_PfiiiPKfS0_Pf
	.type	_ZL8mxvNaiveiiiPKfS0_Pf, @function
_ZL8mxvNaiveiiiPKfS0_Pf:
.LFB3662:
	.cfi_startproc
	endbr64
	jmp	_ZL36__device_stub__Z8mxvNaiveiiiPKfS0_PfiiiPKfS0_Pf
	.cfi_endproc
.LFE3662:
	.size	_ZL8mxvNaiveiiiPKfS0_Pf, .-_ZL8mxvNaiveiiiPKfS0_Pf
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"CPU:"
.LC2:
	.string	" "
	.text
	.globl	_Z3mxviiPKfS0_Pf
	.type	_Z3mxviiPKfS0_Pf, @function
_Z3mxviiPKfS0_Pf:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	movq	%r8, %r12
	xorl	%r8d, %r8d
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movl	%edi, %ebp
	movl	%esi, %edi
	xorl	%esi, %esi
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
.L9:
	cmpl	%esi, %ebp
	jle	.L11
	movslq	%r8d, %rax
	xorps	%xmm0, %xmm0
	leaq	(%rdx,%rax,4), %r9
	xorl	%eax, %eax
.L12:
	cmpl	%eax, %edi
	jle	.L16
	movss	(%r9,%rax,4), %xmm1
	mulss	(%rcx,%rax,4), %xmm1
	incq	%rax
	addss	%xmm1, %xmm0
	jmp	.L12
.L16:
	movss	%xmm0, (%r12,%rsi,4)
	addl	%edi, %r8d
	incq	%rsi
	jmp	.L9
.L11:
	leaq	_ZSt4cout(%rip), %r13
	movl	$4, %edx
	leaq	.LC1(%rip), %rsi
	xorl	%ebx, %ebx
	movq	%r13, %rdi
	leaq	.LC2(%rip), %r14
	call	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L13:
	cmpl	%ebx, %ebp
	jle	.L17
	movq	%r13, %rdi
	cvtss2sd	(%r12,%rbx,4), %xmm0
	incq	%rbx
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movl	$1, %edx
	movq	%r14, %rsi
	movq	%rax, %rdi
	call	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
	jmp	.L13
.L17:
	popq	%rbx
	.cfi_def_cfa_offset 40
	movq	%r13, %rdi
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	jmp	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	.cfi_endproc
.LFE3635:
	.size	_Z3mxviiPKfS0_Pf, .-_Z3mxviiPKfS0_Pf
	.section	.rodata.str1.1
.LC3:
	.string	"GPU:"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3636:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$48, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$16, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	movl	$12, %edi
	movq	%rax, %rbx
	call	malloc@PLT
	leaq	16(%rsp), %rdi
	movl	$16, %esi
	movq	%rax, %r12
	call	cudaMalloc@PLT
	leaq	8(%rsp), %rdi
	movl	$48, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$12, %esi
	call	cudaMalloc@PLT
	movl	$1, %eax
.L19:
	cvtsi2ssl	%eax, %xmm0
	movss	%xmm0, -4(%rbp,%rax,4)
	incq	%rax
	cmpq	$13, %rax
	jne	.L19
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movl	$48, %edx
	movq	%rbp, %rsi
	movabsq	$4611686019492741120, %rax
	movq	%rax, (%rbx)
	movabsq	$4647714816524288000, %rax
	movq	%rax, 8(%rbx)
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$16, %edx
	call	cudaMemcpy@PLT
	movl	$1073741825, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$2, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$4294967299, %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L20
	movq	24(%rsp), %r9
	movq	16(%rsp), %r8
	movl	$4, %edx
	movl	$4, %esi
	movq	8(%rsp), %rcx
	movl	$3, %edi
	call	_ZL36__device_stub__Z8mxvNaiveiiiPKfS0_PfiiiPKfS0_Pf
.L20:
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movq	%r12, %rdi
	xorl	%r13d, %r13d
	movl	$12, %edx
	leaq	_ZSt4cout(%rip), %r14
	leaq	.LC2(%rip), %r15
	call	cudaMemcpy@PLT
	movl	$4, %edx
	leaq	.LC3(%rip), %rsi
	movq	%r14, %rdi
	call	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
.L21:
	movq	%r14, %rdi
	cvtss2sd	(%r12,%r13,4), %xmm0
	incq	%r13
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movl	$1, %edx
	movq	%r15, %rsi
	movq	%rax, %rdi
	call	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
	cmpq	$3, %r13
	jne	.L21
	movq	%r14, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	%r12, %r8
	movq	%rbx, %rcx
	movq	%rbp, %rdx
	movl	$4, %esi
	movl	$3, %edi
	call	_Z3mxviiPKfS0_Pf
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L22
	call	__stack_chk_fail@PLT
.L22:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3636:
	.size	main, .-main
	.section	.rodata.str1.1
.LC4:
	.string	"_Z8mxvNaiveiiiPKfS0_Pf"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3664:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rax, %rdi
	leaq	_ZL8mxvNaiveiiiPKfS0_Pf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3664:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include "hip/hip_runtime.h"

#include <iostream>
#include <stdio.h>
using namespace std;
#define N 3 //rowsize
#define M 4 // columnsize
const int blockNUM = 4;
const int threadNUM =3;
void mxv(const int rowsize,const int columnsize,
         const float*matrix,const float*v,float*r)
         {
             for(int i=0;i<rowsize;i++)
             {
                 float re=0.0f;
                 for(int j=0;j<columnsize;j++)
                    re+=(matrix[i*columnsize+j]*v[j]);
                 r[i]=re;
             }
			 cout <<"CPU:";
             for(int i=0;i<rowsize;i++)
                cout << r[i]<< " ";
             cout <<endl;
         }

static void __global__ mxvNaive(int rowSize, int columnSize, int columnPitch,
const float *d_matrix, const float *d_vec, float *d_r)
  {
      int id = threadIdx.x+blockIdx.x*blockDim.x;
      if(id<rowSize)
      {
          float temp=0;
          for(int i=0;i<columnSize;i++)
          {
              temp+=d_matrix[id*columnPitch+i]*d_vec[i];
          }
          d_r[id]=temp;
      }
}
int main()
{
    float *matrix=(float*)malloc(N*M*sizeof(float));
	float *vec=(float*)malloc(M*sizeof(float));
	float *r =(float*)malloc(N*sizeof(float));
	float *dev_matrix,*dev_vec,*dev_r;
	hipMalloc((void**)&dev_vec,M*sizeof(float));
	hipMalloc((void**)&dev_matrix,M*N*sizeof(float));
	hipMalloc((void**)&dev_r,N*sizeof(float));
	for(int i=1;i<=N*M;i++)
		matrix[i-1]=i;
		for(int i=0;i<M;i++)
            vec[i]=i+1;
	hipMemcpy(dev_matrix,matrix,M*N*sizeof(float),hipMemcpyHostToDevice);
	hipMemcpy(dev_vec,vec,M*sizeof(float),hipMemcpyHostToDevice);
	mxvNaive<<<blockNUM,threadNUM>>> (N,M,M,dev_matrix,dev_vec,dev_r);
	hipMemcpy(r,dev_r,N*sizeof(float),hipMemcpyDeviceToHost);
	cout << "GPU:";
	for(int i=0;i<N;i++)
		cout <<r[i]<<" ";
	cout <<endl;
	mxv(N,M,matrix,vec,r);
    return 0;
}

	.text
	.file	"kernel.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z3mxviiPKfS0_Pf                # -- Begin function _Z3mxviiPKfS0_Pf
	.type	_Z3mxviiPKfS0_Pf,@function
_Z3mxviiPKfS0_Pf:                       # @_Z3mxviiPKfS0_Pf
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	testl	%edi, %edi
	jle	.LBB0_1
# %bb.3:                                # %.preheader.lr.ph
	movq	%r8, %rbx
	movl	%edi, %ebp
	movl	%edi, %r14d
	movl	%esi, %eax
	xorl	%edi, %edi
	xorl	%r8d, %r8d
.LBB0_4:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB0_10 Depth 2
	testl	%esi, %esi
	jle	.LBB0_5
# %bb.9:                                # %.lr.ph
                                        #   in Loop: Header=BB0_4 Depth=1
	movl	%edi, %r9d
	leaq	(%rdx,%r9,4), %r9
	xorps	%xmm0, %xmm0
	xorl	%r10d, %r10d
.LBB0_10:                               #   Parent Loop BB0_4 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movss	(%r9,%r10,4), %xmm1             # xmm1 = mem[0],zero,zero,zero
	mulss	(%rcx,%r10,4), %xmm1
	addss	%xmm1, %xmm0
	incq	%r10
	cmpq	%r10, %rax
	jne	.LBB0_10
	jmp	.LBB0_11
.LBB0_5:                                #   in Loop: Header=BB0_4 Depth=1
	xorps	%xmm0, %xmm0
.LBB0_11:                               # %._crit_edge
                                        #   in Loop: Header=BB0_4 Depth=1
	movss	%xmm0, (%rbx,%r8,4)
	incq	%r8
	addl	%esi, %edi
	cmpq	%r14, %r8
	jne	.LBB0_4
# %bb.6:                                # %._crit_edge28
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$4, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	testl	%ebp, %ebp
	jle	.LBB0_2
# %bb.7:                                # %.lr.ph31.preheader
	xorl	%r15d, %r15d
.LBB0_8:                                # %.lr.ph31
                                        # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rbx,%r15,4), %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movl	$.L.str.1, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	incq	%r15
	cmpq	%r15, %r14
	jne	.LBB0_8
	jmp	.LBB0_2
.LBB0_1:                                # %._crit_edge28.thread
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$4, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
.LBB0_2:                                # %._crit_edge32
	movq	_ZSt4cout(%rip), %rax
	movl	$_ZSt4cout, %ecx
	movq	-24(%rax), %rdi
	addq	%rcx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_ZNSo5flushEv                   # TAILCALL
.Lfunc_end0:
	.size	_Z3mxviiPKfS0_Pf, .Lfunc_end0-_Z3mxviiPKfS0_Pf
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$24, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	$48, %edi
	callq	malloc
	movq	%rax, %rbx
	movl	$16, %edi
	callq	malloc
	movq	%rax, %r14
	movl	$12, %edi
	callq	malloc
	movq	%rax, %r15
	leaq	8(%rsp), %rdi
	movl	$16, %esi
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movl	$48, %esi
	callq	hipMalloc
	movq	%rsp, %rdi
	movl	$12, %esi
	callq	hipMalloc
	xorl	%eax, %eax
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	leaq	1(%rax), %rcx
	xorps	%xmm0, %xmm0
	cvtsi2ss	%ecx, %xmm0
	movss	%xmm0, (%rbx,%rax,4)
	movq	%rcx, %rax
	cmpq	$12, %rcx
	jne	.LBB1_1
# %bb.2:                                # %.preheader.preheader
	xorl	%eax, %eax
.LBB1_3:                                # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	leaq	1(%rax), %rcx
	xorps	%xmm0, %xmm0
	cvtsi2ss	%ecx, %xmm0
	movss	%xmm0, (%r14,%rax,4)
	movq	%rcx, %rax
	cmpq	$4, %rcx
	jne	.LBB1_3
# %bb.4:
	movq	16(%rsp), %rdi
	movl	$48, %edx
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rdi
	movl	$16, %edx
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$4294967299, %rdx               # imm = 0x100000003
	leaq	1(%rdx), %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_6
# %bb.5:
	movq	16(%rsp), %rcx
	movq	8(%rsp), %r8
	movq	(%rsp), %r9
	movl	$3, %edi
	movl	$4, %esi
	movl	$4, %edx
	callq	_ZL23__device_stub__mxvNaiveiiiPKfS0_Pf
.LBB1_6:
	movq	(%rsp), %rsi
	movl	$12, %edx
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$_ZSt4cout, %edi
	movl	$.L.str.2, %esi
	movl	$4, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorl	%r12d, %r12d
.LBB1_7:                                # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r15,%r12,4), %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movl	$.L.str.1, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	incq	%r12
	cmpq	$3, %r12
	jne	.LBB1_7
# %bb.8:
	movq	_ZSt4cout(%rip), %rax
	movl	$_ZSt4cout, %ecx
	movq	-24(%rax), %rdi
	addq	%rcx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$3, %edi
	movl	$4, %esi
	movq	%rbx, %rdx
	movq	%r14, %rcx
	movq	%r15, %r8
	callq	_Z3mxviiPKfS0_Pf
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.type	_ZL23__device_stub__mxvNaiveiiiPKfS0_Pf,@function # -- Begin function _ZL23__device_stub__mxvNaiveiiiPKfS0_Pf
_ZL23__device_stub__mxvNaiveiiiPKfS0_Pf: # @_ZL23__device_stub__mxvNaiveiiiPKfS0_Pf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	56(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	48(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZL8mxvNaiveiiiPKfS0_Pf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_ZL23__device_stub__mxvNaiveiiiPKfS0_Pf, .Lfunc_end2-_ZL23__device_stub__mxvNaiveiiiPKfS0_Pf
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZL8mxvNaiveiiiPKfS0_Pf, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"CPU:"
	.size	.L.str, 5

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	" "
	.size	.L.str.1, 2

	.type	_ZL8mxvNaiveiiiPKfS0_Pf,@object # @_ZL8mxvNaiveiiiPKfS0_Pf
	.section	.rodata,"a",@progbits
	.p2align	3, 0x0
_ZL8mxvNaiveiiiPKfS0_Pf:
	.quad	_ZL23__device_stub__mxvNaiveiiiPKfS0_Pf
	.size	_ZL8mxvNaiveiiiPKfS0_Pf, 8

	.type	.L.str.2,@object                # @.str.2
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.2:
	.asciz	"GPU:"
	.size	.L.str.2, 5

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_ZL8mxvNaiveiiiPKfS0_Pf"
	.size	.L__unnamed_1, 24

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _ZL23__device_stub__mxvNaiveiiiPKfS0_Pf
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _ZSt4cout
	.addrsig_sym _ZL8mxvNaiveiiiPKfS0_Pf
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.section	.text._ZL8mxvNaiveiiiPKfS0_Pf,"axG",@progbits,_ZL8mxvNaiveiiiPKfS0_Pf,comdat
	.globl	_ZL8mxvNaiveiiiPKfS0_Pf         ; -- Begin function _ZL8mxvNaiveiiiPKfS0_Pf
	.p2align	8
	.type	_ZL8mxvNaiveiiiPKfS0_Pf,@function
_ZL8mxvNaiveiiiPKfS0_Pf:                ; @_ZL8mxvNaiveiiiPKfS0_Pf
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x34
	s_load_b128 s[4:7], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s4, v1
	s_cbranch_execz .LBB0_6
; %bb.1:                                ; %.preheader
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x10
	s_load_b64 s[0:1], s[0:1], 0x20
	s_cmp_lt_i32 s5, 1
	s_cbranch_scc1 .LBB0_4
; %bb.2:                                ; %.lr.ph
	v_mul_lo_u32 v2, v1, s6
	v_mov_b32_e32 v0, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
.LBB0_3:                                ; =>This Inner Loop Header: Depth=1
	global_load_b32 v4, v[2:3], off
	s_load_b32 s2, s[10:11], 0x0
	v_add_co_u32 v2, vcc_lo, v2, 4
	s_add_i32 s5, s5, -1
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_add_u32 s10, s10, 4
	s_addc_u32 s11, s11, 0
	s_cmp_eq_u32 s5, 0
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fmac_f32_e32 v0, s2, v4
	s_cbranch_scc0 .LBB0_3
	s_branch .LBB0_5
.LBB0_4:
	v_mov_b32_e32 v0, 0
.LBB0_5:                                ; %Flow42
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_store_b32 v[1:2], v0, off
.LBB0_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZL8mxvNaiveiiiPKfS0_Pf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._ZL8mxvNaiveiiiPKfS0_Pf,"axG",@progbits,_ZL8mxvNaiveiiiPKfS0_Pf,comdat
.Lfunc_end0:
	.size	_ZL8mxvNaiveiiiPKfS0_Pf, .Lfunc_end0-_ZL8mxvNaiveiiiPKfS0_Pf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 256
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZL8mxvNaiveiiiPKfS0_Pf
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _ZL8mxvNaiveiiiPKfS0_Pf.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     5
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
