__global__ void calculate_inner_grid(double* grid_0, double* grid_1, double* grid_2, int bx, int by, int bz){
    int N = (bx + 2) * (by + 2) * (bz * 2);
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    int i, j, k;
    double uijk = grid_1[idx], laplace = 0.;
    i = N % (bx + 2);
    if (i < 2 && i >= bx) return;
    j = N / (bx + 2) % (by + 2);
    if (j < 2 && j >= by) return;
    k = N / ((bx + 2) * (by + 2));
    if (k < 2 && k >= bz) return;
    grid_2[idx] = 2 * grid_1[idx] - grid_0[idx];
}

__global__ void first_step(double* grid_0, double* grid_1, \
        int bx, int by, int bz, \
        double hx, double hy, double hz, \
        double block_x_len, double block_y_len, double block_z_len, \
        int Lx, int Ly, int Lz, \
        int Nx, int Ny, int Nz, \
        int nx, int ny, int nz, \
        int block_pos_x, int block_pos_y, int block_pos_z,
        double at, double t){
    int N = (bx + 2) * (by + 2) * (bz * 2);
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    int i, j, k;
    double uijk = grid_1[idx], laplace = 0.;
    double x, y, z;
    i = N % (bx + 2);
    if (i < 1 && i > bx) return;
    j = N / (bx + 2) % (by + 2);
    if (j < 1 && j > by) return;
    k = N / ((bx + 2) * (by + 2));
    if (k < 1 && k > bz) return;
    x = (i - 1) * hx + block_pos_x * block_x_len + min(Nx % nx, block_pos_x) * hx;
    y = (j - 1) * hy + block_pos_y * block_y_len + min(Ny % ny, block_pos_y) * hy;
    z = (k - 1) * hz + block_pos_z * block_z_len + min(Nz % nz, block_pos_z) * hz;
    grid_0[idx] = sin(3.14 / Lx * x) * sin(3.14 / Ly * y) * sin(2 * 3.14 / Lz * z) * cos(at * t + 2 * 3.14);
}

	.file	"tmpxft_00353e3d_00000000-6_cuda_utils.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z47__device_stub__Z20calculate_inner_gridPdS_S_iiiPdS_S_iii
	.type	_Z47__device_stub__Z20calculate_inner_gridPdS_S_iiiPdS_S_iii, @function
_Z47__device_stub__Z20calculate_inner_gridPdS_S_iiiPdS_S_iii:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z20calculate_inner_gridPdS_S_iii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L2:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z47__device_stub__Z20calculate_inner_gridPdS_S_iiiPdS_S_iii, .-_Z47__device_stub__Z20calculate_inner_gridPdS_S_iiiPdS_S_iii
	.globl	_Z20calculate_inner_gridPdS_S_iii
	.type	_Z20calculate_inner_gridPdS_S_iii, @function
_Z20calculate_inner_gridPdS_S_iii:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z20calculate_inner_gridPdS_S_iiiPdS_S_iii
	.cfi_endproc
.LFE2033:
	.size	_Z20calculate_inner_gridPdS_S_iii, .-_Z20calculate_inner_gridPdS_S_iii
	.globl	_Z55__device_stub__Z10first_stepPdS_iiiddddddiiiiiiiiiiiiddPdS_iiiddddddiiiiiiiiiiiidd
	.type	_Z55__device_stub__Z10first_stepPdS_iiiddddddiiiiiiiiiiiiddPdS_iiiddddddiiiiiiiiiiiidd, @function
_Z55__device_stub__Z10first_stepPdS_iiiddddddiiiiiiiiiiiiddPdS_iiiddddddiiiiiiiiiiiidd:
.LFB2034:
	.cfi_startproc
	endbr64
	subq	$376, %rsp
	.cfi_def_cfa_offset 384
	movq	%rdi, 88(%rsp)
	leaq	112(%rsp), %rdi
	movq	%rsi, 80(%rsp)
	leaq	124(%rsp), %rsi
	movl	%edx, 76(%rsp)
	leaq	96(%rsp), %rdx
	movl	%ecx, 72(%rsp)
	leaq	104(%rsp), %rcx
	movl	%r8d, 68(%rsp)
	movl	%r9d, 64(%rsp)
	movsd	%xmm0, 56(%rsp)
	movsd	%xmm1, 48(%rsp)
	movsd	%xmm2, 40(%rsp)
	movsd	%xmm3, 32(%rsp)
	movsd	%xmm4, 24(%rsp)
	movsd	%xmm5, 16(%rsp)
	movsd	%xmm6, 8(%rsp)
	movsd	%xmm7, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 360(%rsp)
	xorl	%eax, %eax
	leaq	88(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	76(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	68(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	384(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	392(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	400(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	408(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	416(%rsp), %rax
	movq	%rax, 288(%rsp)
	leaq	424(%rsp), %rax
	movq	%rax, 296(%rsp)
	leaq	432(%rsp), %rax
	movq	%rax, 304(%rsp)
	leaq	440(%rsp), %rax
	movq	%rax, 312(%rsp)
	leaq	448(%rsp), %rax
	movq	%rax, 320(%rsp)
	leaq	456(%rsp), %rax
	movq	%rax, 328(%rsp)
	leaq	464(%rsp), %rax
	movq	%rax, 336(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 344(%rsp)
	movq	%rsp, %rax
	movq	%rax, 352(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 112(%rsp)
	movl	$1, 120(%rsp)
	movq	%rax, 124(%rsp)
	movl	$1, 132(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	104(%rsp)
	.cfi_def_cfa_offset 392
	leaq	_Z10first_stepPdS_iiiddddddiiiiiiiiiiiidd(%rip), %rdi
	pushq	104(%rsp)
	.cfi_def_cfa_offset 400
	movq	140(%rsp), %rcx
	movl	148(%rsp), %r8d
	movq	128(%rsp), %rsi
	movl	136(%rsp), %edx
	leaq	176(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 392
	popq	%rdx
	.cfi_def_cfa_offset 384
.L8:
	movq	360(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$376, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2034:
	.size	_Z55__device_stub__Z10first_stepPdS_iiiddddddiiiiiiiiiiiiddPdS_iiiddddddiiiiiiiiiiiidd, .-_Z55__device_stub__Z10first_stepPdS_iiiddddddiiiiiiiiiiiiddPdS_iiiddddddiiiiiiiiiiiidd
	.globl	_Z10first_stepPdS_iiiddddddiiiiiiiiiiiidd
	.type	_Z10first_stepPdS_iiiddddddiiiiiiiiiiiidd, @function
_Z10first_stepPdS_iiiddddddiiiiiiiiiiiidd:
.LFB2035:
	.cfi_startproc
	endbr64
	jmp	_Z55__device_stub__Z10first_stepPdS_iiiddddddiiiiiiiiiiiiddPdS_iiiddddddiiiiiiiiiiiidd
	.cfi_endproc
.LFE2035:
	.size	_Z10first_stepPdS_iiiddddddiiiiiiiiiiiidd, .-_Z10first_stepPdS_iiiddddddiiiiiiiiiiiidd
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z10first_stepPdS_iiiddddddiiiiiiiiiiiidd"
.LC1:
	.string	"_Z20calculate_inner_gridPdS_S_iii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2037:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z10first_stepPdS_iiiddddddiiiiiiiiiiiidd(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z20calculate_inner_gridPdS_S_iii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2037:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
__global__ void calculate_inner_grid(double* grid_0, double* grid_1, double* grid_2, int bx, int by, int bz){
    int N = (bx + 2) * (by + 2) * (bz * 2);
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    int i, j, k;
    double uijk = grid_1[idx], laplace = 0.;
    i = N % (bx + 2);
    if (i < 2 && i >= bx) return;
    j = N / (bx + 2) % (by + 2);
    if (j < 2 && j >= by) return;
    k = N / ((bx + 2) * (by + 2));
    if (k < 2 && k >= bz) return;
    grid_2[idx] = 2 * grid_1[idx] - grid_0[idx];
}

__global__ void first_step(double* grid_0, double* grid_1, \
        int bx, int by, int bz, \
        double hx, double hy, double hz, \
        double block_x_len, double block_y_len, double block_z_len, \
        int Lx, int Ly, int Lz, \
        int Nx, int Ny, int Nz, \
        int nx, int ny, int nz, \
        int block_pos_x, int block_pos_y, int block_pos_z,
        double at, double t){
    int N = (bx + 2) * (by + 2) * (bz * 2);
    int idx = blockIdx.x * blockDim.x + threadIdx.x;
    int i, j, k;
    double uijk = grid_1[idx], laplace = 0.;
    double x, y, z;
    i = N % (bx + 2);
    if (i < 1 && i > bx) return;
    j = N / (bx + 2) % (by + 2);
    if (j < 1 && j > by) return;
    k = N / ((bx + 2) * (by + 2));
    if (k < 1 && k > bz) return;
    x = (i - 1) * hx + block_pos_x * block_x_len + min(Nx % nx, block_pos_x) * hx;
    y = (j - 1) * hy + block_pos_y * block_y_len + min(Ny % ny, block_pos_y) * hy;
    z = (k - 1) * hz + block_pos_z * block_z_len + min(Nz % nz, block_pos_z) * hz;
    grid_0[idx] = sin(3.14 / Lx * x) * sin(3.14 / Ly * y) * sin(2 * 3.14 / Lz * z) * cos(at * t + 2 * 3.14);
}

	.text
	.file	"cuda_utils.hip"
	.globl	_Z35__device_stub__calculate_inner_gridPdS_S_iii # -- Begin function _Z35__device_stub__calculate_inner_gridPdS_S_iii
	.type	_Z35__device_stub__calculate_inner_gridPdS_S_iii,@function
_Z35__device_stub__calculate_inner_gridPdS_S_iii: # @_Z35__device_stub__calculate_inner_gridPdS_S_iii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z20calculate_inner_gridPdS_S_iii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z35__device_stub__calculate_inner_gridPdS_S_iii, .Lfunc_end0-_Z35__device_stub__calculate_inner_gridPdS_S_iii
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__first_stepPdS_iiiddddddiiiiiiiiiiiidd # -- Begin function _Z25__device_stub__first_stepPdS_iiiddddddiiiiiiiiiiiidd
	.type	_Z25__device_stub__first_stepPdS_iiiddddddiiiiiiiiiiiidd,@function
_Z25__device_stub__first_stepPdS_iiiddddddiiiiiiiiiiiidd: # @_Z25__device_stub__first_stepPdS_iiiddddddiiiiiiiiiiiidd
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$344, %rsp                      # imm = 0x158
	.cfi_def_cfa_offset 400
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	leaq	104(%rsp), %r10
	movq	%rdi, (%r10)
	leaq	96(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %r11
	movl	%r8d, (%r11)
	leaq	88(%rsp), %r8
	movsd	%xmm0, (%r8)
	leaq	80(%rsp), %r14
	movsd	%xmm1, (%r14)
	leaq	72(%rsp), %r15
	movsd	%xmm2, (%r15)
	leaq	64(%rsp), %r12
	movsd	%xmm3, (%r12)
	leaq	56(%rsp), %r13
	movsd	%xmm4, (%r13)
	leaq	48(%rsp), %rbp
	movsd	%xmm5, (%rbp)
	movq	%rsp, %rax
	movl	%r9d, (%rax)
	leaq	40(%rsp), %r9
	movsd	%xmm6, (%r9)
	leaq	32(%rsp), %rcx
	movsd	%xmm7, (%rcx)
	leaq	144(%rsp), %rbx
	movq	%r10, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r11, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r14, 48(%rbx)
	movq	%r15, 56(%rbx)
	movq	%r12, 64(%rbx)
	movq	%r13, 72(%rbx)
	movq	%rbp, 80(%rbx)
	movq	%rax, 88(%rbx)
	leaq	400(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	408(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	416(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	424(%rsp), %rax
	movq	%rax, 120(%rbx)
	leaq	432(%rsp), %rax
	movq	%rax, 128(%rbx)
	leaq	440(%rsp), %rax
	movq	%rax, 136(%rbx)
	leaq	448(%rsp), %rax
	movq	%rax, 144(%rbx)
	leaq	456(%rsp), %rax
	movq	%rax, 152(%rbx)
	leaq	464(%rsp), %rax
	movq	%rax, 160(%rbx)
	leaq	472(%rsp), %rax
	movq	%rax, 168(%rbx)
	leaq	480(%rsp), %rax
	movq	%rax, 176(%rbx)
	movq	%r9, 184(%rbx)
	movq	%rcx, 192(%rbx)
	leaq	128(%rsp), %r14
	leaq	112(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10first_stepPdS_iiiddddddiiiiiiiiiiiidd, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$360, %rsp                      # imm = 0x168
	.cfi_adjust_cfa_offset -360
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z25__device_stub__first_stepPdS_iiiddddddiiiiiiiiiiiidd, .Lfunc_end1-_Z25__device_stub__first_stepPdS_iiiddddddiiiiiiiiiiiidd
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z20calculate_inner_gridPdS_S_iii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10first_stepPdS_iiiddddddiiiiiiiiiiiidd, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z20calculate_inner_gridPdS_S_iii,@object # @_Z20calculate_inner_gridPdS_S_iii
	.section	.rodata,"a",@progbits
	.globl	_Z20calculate_inner_gridPdS_S_iii
	.p2align	3, 0x0
_Z20calculate_inner_gridPdS_S_iii:
	.quad	_Z35__device_stub__calculate_inner_gridPdS_S_iii
	.size	_Z20calculate_inner_gridPdS_S_iii, 8

	.type	_Z10first_stepPdS_iiiddddddiiiiiiiiiiiidd,@object # @_Z10first_stepPdS_iiiddddddiiiiiiiiiiiidd
	.globl	_Z10first_stepPdS_iiiddddddiiiiiiiiiiiidd
	.p2align	3, 0x0
_Z10first_stepPdS_iiiddddddiiiiiiiiiiiidd:
	.quad	_Z25__device_stub__first_stepPdS_iiiddddddiiiiiiiiiiiidd
	.size	_Z10first_stepPdS_iiiddddddiiiiiiiiiiiidd, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z20calculate_inner_gridPdS_S_iii"
	.size	.L__unnamed_1, 34

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z10first_stepPdS_iiiddddddiiiiiiiiiiiidd"
	.size	.L__unnamed_2, 42

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z35__device_stub__calculate_inner_gridPdS_S_iii
	.addrsig_sym _Z25__device_stub__first_stepPdS_iiiddddddiiiiiiiiiiiidd
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z20calculate_inner_gridPdS_S_iii
	.addrsig_sym _Z10first_stepPdS_iiiddddddiiiiiiiiiiiidd
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z20calculate_inner_gridPdS_S_iii ; -- Begin function _Z20calculate_inner_gridPdS_S_iii
	.globl	_Z20calculate_inner_gridPdS_S_iii
	.p2align	8
	.type	_Z20calculate_inner_gridPdS_S_iii,@function
_Z20calculate_inner_gridPdS_S_iii:      ; @_Z20calculate_inner_gridPdS_S_iii
; %bb.0:
	s_load_b128 s[4:7], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_add_i32 s2, s4, 2
	s_add_i32 s8, s5, 2
	s_ashr_i32 s3, s2, 31
	s_lshl_b32 s9, s6, 1
	s_add_i32 s7, s2, s3
	s_mul_i32 s10, s8, s2
	s_xor_b32 s7, s7, s3
	s_mul_i32 s10, s10, s9
	v_cvt_f32_u32_e32 v1, s7
	s_sub_i32 s12, 0, s7
	s_ashr_i32 s13, s10, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s14, s10, s13
	v_rcp_iflag_f32_e32 v1, v1
	s_xor_b32 s14, s14, s13
	s_xor_b32 s3, s13, s3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v1, v1
	v_readfirstlane_b32 s11, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s12, s12, s11
	s_mul_hi_u32 s12, s11, s12
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s11, s11, s12
	s_mul_hi_u32 s11, s14, s11
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_mul_i32 s12, s11, s7
	s_add_i32 s13, s11, 1
	s_sub_i32 s12, s14, s12
	s_sub_i32 s14, s12, s7
	s_cmp_ge_u32 s12, s7
	s_cselect_b32 s11, s13, s11
	s_cselect_b32 s12, s14, s12
	s_add_i32 s13, s11, 1
	s_cmp_ge_u32 s12, s7
	s_cselect_b32 s7, s13, s11
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s7, s7, s3
	s_sub_i32 s3, s7, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s2, s3, s2
	s_sub_i32 s2, s10, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_gt_i32 s2, 1
	s_cselect_b32 s7, -1, 0
	s_cmp_lt_i32 s2, s4
	s_cselect_b32 s2, -1, 0
	s_ashr_i32 s4, s8, 31
	s_ashr_i32 s11, s3, 31
	s_add_i32 s8, s8, s4
	s_add_i32 s3, s3, s11
	s_xor_b32 s4, s8, s4
	s_xor_b32 s3, s3, s11
	v_cvt_f32_u32_e32 v1, s4
	s_sub_i32 s10, 0, s4
	s_or_b32 s2, s7, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s8, v1
	s_mul_i32 s10, s10, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s10, s8, s10
	s_add_i32 s8, s8, s10
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s8, s3, s8
	s_mul_i32 s8, s8, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_sub_i32 s3, s3, s8
	s_sub_i32 s7, s3, s4
	s_cmp_ge_u32 s3, s4
	s_cselect_b32 s3, s7, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_sub_i32 s7, s3, s4
	s_cmp_ge_u32 s3, s4
	s_cselect_b32 s3, s7, s3
	s_xor_b32 s3, s3, s11
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_sub_i32 s3, s3, s11
	s_cmp_gt_i32 s3, 1
	s_cselect_b32 s4, -1, 0
	s_cmp_lt_i32 s3, s5
	s_cselect_b32 s3, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	s_or_b32 s3, s4, s3
	s_min_i32 s4, s9, 0
	s_and_b32 s2, s2, s3
	s_cmp_lt_i32 s4, s6
	s_cselect_b32 s3, -1, 0
	s_and_b32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB0_2
; %bb.1:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x34
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[1:2]
	v_add_co_u32 v2, vcc_lo, s6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	global_load_b64 v[2:3], v[2:3], off
	global_load_b64 v[4:5], v[4:5], off
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_fma_f64 v[2:3], v[2:3], 2.0, -v[4:5]
	global_store_b64 v[0:1], v[2:3], off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z20calculate_inner_gridPdS_S_iii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z20calculate_inner_gridPdS_S_iii, .Lfunc_end0-_Z20calculate_inner_gridPdS_S_iii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 568
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z10first_stepPdS_iiiddddddiiiiiiiiiiiidd ; -- Begin function _Z10first_stepPdS_iiiddddddiiiiiiiiiiiidd
	.globl	_Z10first_stepPdS_iiiddddddiiiiiiiiiiiidd
	.p2align	8
	.type	_Z10first_stepPdS_iiiddddddiiiiiiiiiiiidd,@function
_Z10first_stepPdS_iiiddddddiiiiiiiiiiiidd: ; @_Z10first_stepPdS_iiiddddddiiiiiiiiiiiidd
; %bb.0:
	s_load_b128 s[4:7], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_add_i32 s2, s4, 2
	s_add_i32 s7, s5, 2
	s_ashr_i32 s8, s2, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s3, s2, s8
	s_xor_b32 s9, s3, s8
	s_lshl_b32 s3, s6, 1
	v_cvt_f32_u32_e32 v1, s9
	s_mul_i32 s6, s7, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_mul_i32 s11, s6, s3
	s_sub_i32 s6, 0, s9
	v_rcp_iflag_f32_e32 v1, v1
	s_ashr_i32 s12, s11, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	s_add_i32 s13, s11, s12
	s_xor_b32 s8, s12, s8
	s_xor_b32 s13, s13, s12
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s10, v1
	s_mul_i32 s6, s6, s10
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s6, s10, s6
	s_add_i32 s10, s10, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s6, s13, s10
	s_mul_i32 s10, s6, s9
	s_add_i32 s12, s6, 1
	s_sub_i32 s10, s13, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s13, s10, s9
	s_cmp_ge_u32 s10, s9
	s_cselect_b32 s6, s12, s6
	s_cselect_b32 s10, s13, s10
	s_add_i32 s12, s6, 1
	s_cmp_ge_u32 s10, s9
	s_cselect_b32 s6, s12, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s6, s6, s8
	s_sub_i32 s6, s6, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s2, s6, s2
	s_sub_i32 s2, s11, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	s_cmp_lt_i32 s2, 1
	s_cselect_b32 s8, -1, 0
	s_cmp_gt_i32 s2, s4
	s_cselect_b32 s4, -1, 0
	s_and_b32 s4, s8, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccnz .LBB1_23
; %bb.1:
	s_ashr_i32 s4, s7, 31
	s_ashr_i32 s9, s6, 31
	s_add_i32 s7, s7, s4
	s_add_i32 s6, s6, s9
	s_xor_b32 s4, s7, s4
	s_xor_b32 s6, s6, s9
	v_cvt_f32_u32_e32 v1, s4
	s_sub_i32 s8, 0, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s7, v1
	s_mul_i32 s8, s8, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s8, s7, s8
	s_add_i32 s7, s7, s8
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s7, s6, s7
	s_mul_i32 s7, s7, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_sub_i32 s6, s6, s7
	s_sub_i32 s7, s6, s4
	s_cmp_ge_u32 s6, s4
	s_cselect_b32 s6, s7, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_sub_i32 s7, s6, s4
	s_cmp_ge_u32 s6, s4
	s_cselect_b32 s4, s7, s6
	s_xor_b32 s4, s4, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_sub_i32 s14, s4, s9
	s_cmp_lt_i32 s14, 1
	s_cselect_b32 s4, -1, 0
	s_cmp_gt_i32 s14, s5
	s_cselect_b32 s5, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s4, s4, s5
	s_and_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccnz .LBB1_23
; %bb.2:
	s_load_b256 s[4:11], s[0:1], 0x50
	s_mov_b32 s12, 0x51eb851f
	s_mov_b32 s13, 0x40091eb8
	s_add_i32 s2, s2, -1
	s_load_b256 s[16:23], s[0:1], 0x20
	v_cvt_f64_i32_e32 v[9:10], s2
	s_load_b128 s[24:27], s[0:1], 0x70
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_i32_e32 v[1:2], s4
	s_ashr_i32 s2, s10, 31
	s_ashr_i32 s28, s7, 31
	s_add_i32 s4, s10, s2
	s_add_i32 s7, s7, s28
	s_xor_b32 s2, s4, s2
	s_xor_b32 s7, s7, s28
	v_cvt_f32_u32_e32 v13, s2
	s_sub_i32 s10, 0, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_rcp_iflag_f32_e32 v13, v13
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v15, 0x4f7ffffe, v13
	v_mul_f64 v[9:10], v[9:10], s[16:17]
	v_cvt_u32_f32_e32 v15, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s4, v15
	s_mul_i32 s10, s10, s4
	v_div_scale_f64 v[3:4], null, v[1:2], v[1:2], s[12:13]
	s_mul_hi_u32 s10, s4, s10
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s4, s4, s10
	s_mul_hi_u32 s4, s7, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s4, s4, s2
	s_sub_i32 s4, s7, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_sub_i32 s7, s4, s2
	s_cmp_ge_u32 s4, s2
	s_cselect_b32 s4, s7, s4
	s_sub_i32 s7, s4, s2
	s_cmp_ge_u32 s4, s2
	s_cselect_b32 s2, s7, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s2, s2, s28
	s_sub_i32 s2, s2, s28
	s_load_b128 s[28:31], s[0:1], 0x40
	v_cvt_f64_i32_e32 v[13:14], s25
	s_min_i32 s2, s2, s25
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[5:6], v[3:4]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[7:8], -v[3:4], v[5:6], 1.0
	v_fma_f64 v[5:6], v[5:6], v[7:8], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], -v[3:4], v[5:6], 1.0
	v_fma_f64 v[5:6], v[5:6], v[7:8], v[5:6]
	v_div_scale_f64 v[7:8], vcc_lo, s[12:13], v[1:2], s[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[11:12], v[7:8], v[5:6]
	v_fma_f64 v[3:4], -v[3:4], v[11:12], v[7:8]
	v_fma_f64 v[7:8], v[13:14], s[22:23], v[9:10]
	v_cvt_f64_i32_e32 v[9:10], s2
	s_mov_b32 s2, -1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[3:4], v[3:4], v[5:6], v[11:12]
	v_fma_f64 v[5:6], v[9:10], s[16:17], v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[1:2], v[3:4], v[1:2], s[12:13]
	s_mov_b32 s12, 0
	v_mul_f64 v[1:2], v[1:2], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ngt_f64_e64 s4, 0x41d00000, |v[1:2]|
	s_and_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccz .LBB1_4
; %bb.3:
	v_ldexp_f64 v[3:4], |v[1:2]|, 0xffffff80
	v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[1:2]|
	v_trig_preop_f64 v[5:6], |v[1:2]|, 0
	v_and_b32_e32 v7, 0x7fffffff, v2
	v_trig_preop_f64 v[17:18], |v[1:2]|, 2
	s_mov_b32 s16, 0x33145c07
	s_mov_b32 s17, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v4, v7, v4 :: v_dual_cndmask_b32 v3, v1, v3
	v_trig_preop_f64 v[7:8], |v[1:2]|, 1
	v_mul_f64 v[9:10], v[5:6], v[3:4]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[23:24], v[17:18], v[3:4]
	v_mul_f64 v[11:12], v[7:8], v[3:4]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[5:6], v[5:6], v[3:4], -v[9:10]
	v_fma_f64 v[7:8], v[7:8], v[3:4], -v[11:12]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[3:4], v[17:18], v[3:4], -v[23:24]
	v_add_f64 v[13:14], v[11:12], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[15:16], v[13:14], -v[11:12]
	v_add_f64 v[21:22], v[9:10], v[13:14]
	v_add_f64 v[19:20], v[13:14], -v[15:16]
	v_add_f64 v[5:6], v[5:6], -v[15:16]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_ldexp_f64 v[15:16], v[21:22], -2
	v_add_f64 v[9:10], v[21:22], -v[9:10]
	v_add_f64 v[11:12], v[11:12], -v[19:20]
	v_add_f64 v[19:20], v[23:24], v[7:8]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[15:16]|
	v_add_f64 v[9:10], v[13:14], -v[9:10]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[5:6], v[5:6], v[11:12]
	v_fract_f64_e32 v[11:12], v[15:16]
	v_add_f64 v[13:14], v[19:20], v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v12, 0, v12 :: v_dual_cndmask_b32 v11, 0, v11
	v_ldexp_f64 v[11:12], v[11:12], 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[15:16], v[9:10], v[13:14]
	v_add_f64 v[25:26], v[13:14], -v[19:20]
	v_add_f64 v[21:22], v[15:16], v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_f64 v[31:32], v[13:14], -v[25:26]
	v_add_f64 v[5:6], v[5:6], -v[25:26]
	v_add_f64 v[9:10], v[15:16], -v[9:10]
	v_cmp_gt_f64_e32 vcc_lo, 0, v[21:22]
	v_add_f64 v[21:22], v[19:20], -v[23:24]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_f64 v[9:10], v[13:14], -v[9:10]
	s_and_b32 s2, vcc_lo, exec_lo
	s_cselect_b32 s13, 0x40100000, 0
	v_add_f64 v[29:30], v[19:20], -v[21:22]
	v_add_f64 v[11:12], v[11:12], s[12:13]
	v_add_f64 v[7:8], v[7:8], -v[21:22]
	v_add_f64 v[19:20], v[19:20], -v[31:32]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[21:22], v[23:24], -v[29:30]
	v_add_f64 v[27:28], v[15:16], v[11:12]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[5:6], v[5:6], v[19:20]
	v_add_f64 v[7:8], v[7:8], v[21:22]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f64_e32 v27, v[27:28]
	v_add_f64 v[5:6], v[7:8], v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_i32_e32 v[25:26], v27
	v_add_f64 v[3:4], v[3:4], v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[11:12], v[11:12], -v[25:26]
	v_add_f64 v[3:4], v[9:10], v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[7:8], v[15:16], v[11:12]
	v_add_f64 v[5:6], v[7:8], -v[11:12]
	v_cmp_le_f64_e32 vcc_lo, 0.5, v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_f64 v[5:6], v[15:16], -v[5:6]
	s_and_b32 s2, vcc_lo, exec_lo
	s_cselect_b32 s13, 0x3ff00000, 0
	v_add_co_ci_u32_e64 v25, s2, 0, v27, vcc_lo
	s_mov_b32 s2, 0
	v_add_f64 v[3:4], v[3:4], v[5:6]
	v_add_f64 v[5:6], v[7:8], -s[12:13]
	s_mov_b32 s12, 0x54442d18
	s_mov_b32 s13, 0x3ff921fb
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[7:8], v[5:6], v[3:4]
	v_mul_f64 v[9:10], v[7:8], s[12:13]
	v_add_f64 v[5:6], v[7:8], -v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[11:12], v[7:8], s[12:13], -v[9:10]
	v_add_f64 v[3:4], v[3:4], -v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], v[7:8], s[16:17], v[11:12]
	v_fma_f64 v[5:6], v[3:4], s[12:13], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[3:4], v[9:10], v[5:6]
	v_add_f64 v[7:8], v[3:4], -v[9:10]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[5:6], v[5:6], -v[7:8]
	s_branch .LBB1_5
.LBB1_4:
                                        ; implicit-def: $vgpr25
                                        ; implicit-def: $vgpr3_vgpr4
                                        ; implicit-def: $vgpr5_vgpr6
.LBB1_5:                                ; %Flow148
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB1_7
; %bb.6:
	s_mov_b32 s12, 0x6dc9c883
	s_mov_b32 s13, 0x3fe45f30
	s_mov_b32 s17, 0xbc91a626
	v_mul_f64 v[3:4], |v[1:2]|, s[12:13]
	s_mov_b32 s12, 0x54442d18
	s_mov_b32 s13, 0xbff921fb
	s_mov_b32 s16, 0x33145c00
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[7:8], v[3:4]
	v_fma_f64 v[3:4], v[7:8], s[12:13], |v[1:2]|
	v_mul_f64 v[5:6], v[7:8], s[16:17]
	s_mov_b32 s12, 0x252049c0
	s_mov_b32 s13, 0xb97b839a
	v_cvt_i32_f64_e32 v25, v[7:8]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[11:12], v[7:8], s[16:17], v[3:4]
	v_add_f64 v[9:10], v[3:4], v[5:6]
	s_mov_b32 s17, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[3:4], v[3:4], -v[9:10]
	v_add_f64 v[9:10], v[9:10], -v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[3:4], v[3:4], v[5:6]
	v_fma_f64 v[5:6], v[7:8], s[16:17], v[5:6]
	v_add_f64 v[3:4], v[9:10], v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[3:4], v[3:4], -v[5:6]
	v_fma_f64 v[5:6], v[7:8], s[12:13], v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[3:4], v[11:12], v[5:6]
	v_add_f64 v[9:10], v[3:4], -v[11:12]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[5:6], v[5:6], -v[9:10]
.LBB1_7:                                ; %_ZL3sind.exit
	v_cvt_f64_i32_e32 v[7:8], s5
	s_mov_b32 s4, 0x51eb851f
	s_mov_b32 s5, 0x40091eb8
	s_add_i32 s14, s14, -1
	s_ashr_i32 s2, s11, 31
	v_cvt_f64_i32_e32 v[15:16], s14
	s_add_i32 s7, s11, s2
	s_ashr_i32 s11, s8, 31
	s_xor_b32 s2, s7, s2
	s_add_i32 s8, s8, s11
	v_cvt_f32_u32_e32 v19, s2
	s_sub_i32 s10, 0, s2
	s_xor_b32 s8, s8, s11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_rcp_iflag_f32_e32 v19, v19
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v21, 0x4f7ffffe, v19
	v_cvt_f64_i32_e32 v[19:20], s26
	v_cvt_u32_f32_e32 v21, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s7, v21
	v_div_scale_f64 v[9:10], null, v[7:8], v[7:8], s[4:5]
	s_mul_i32 s10, s10, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_mul_hi_u32 s10, s7, s10
	v_mul_f64 v[15:16], v[15:16], s[18:19]
	s_add_i32 s7, s7, s10
	s_mul_hi_u32 s7, s8, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s7, s7, s2
	s_sub_i32 s7, s8, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_sub_i32 s8, s7, s2
	s_cmp_ge_u32 s7, s2
	s_cselect_b32 s7, s8, s7
	s_sub_i32 s8, s7, s2
	s_cmp_ge_u32 s7, s2
	s_cselect_b32 s2, s8, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s2, s2, s11
	s_sub_i32 s2, s2, s11
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_min_i32 s2, s2, s26
	v_rcp_f64_e32 v[11:12], v[9:10]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[13:14], -v[9:10], v[11:12], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], v[11:12], v[13:14], v[11:12]
	v_fma_f64 v[13:14], -v[9:10], v[11:12], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], v[11:12], v[13:14], v[11:12]
	v_div_scale_f64 v[13:14], vcc_lo, s[4:5], v[7:8], s[4:5]
	v_mul_f64 v[17:18], v[13:14], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_fma_f64 v[9:10], -v[9:10], v[17:18], v[13:14]
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[13:14], v[19:20], s[28:29], v[15:16]
	v_cvt_f64_i32_e32 v[15:16], s2
	s_mov_b32 s2, -1
	v_div_fmas_f64 v[9:10], v[9:10], v[11:12], v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[11:12], v[15:16], s[18:19], v[13:14]
	v_div_fixup_f64 v[7:8], v[9:10], v[7:8], s[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[7:8], v[7:8], v[11:12]
	v_cmp_ngt_f64_e64 s4, 0x41d00000, |v[7:8]|
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s4
	s_mov_b32 s4, 0
	s_cbranch_vccz .LBB1_9
; %bb.8:
	v_ldexp_f64 v[9:10], |v[7:8]|, 0xffffff80
	v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[7:8]|
	v_trig_preop_f64 v[11:12], |v[7:8]|, 0
	v_and_b32_e32 v13, 0x7fffffff, v8
	v_trig_preop_f64 v[23:24], |v[7:8]|, 2
	s_mov_b32 s10, 0x33145c07
	s_mov_b32 s11, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v10, v13, v10 :: v_dual_cndmask_b32 v9, v7, v9
	v_trig_preop_f64 v[13:14], |v[7:8]|, 1
	v_mul_f64 v[15:16], v[11:12], v[9:10]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[30:31], v[23:24], v[9:10]
	v_mul_f64 v[17:18], v[13:14], v[9:10]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[11:12], v[11:12], v[9:10], -v[15:16]
	v_fma_f64 v[13:14], v[13:14], v[9:10], -v[17:18]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[9:10], v[23:24], v[9:10], -v[30:31]
	v_add_f64 v[19:20], v[17:18], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[21:22], v[19:20], -v[17:18]
	v_add_f64 v[28:29], v[15:16], v[19:20]
	v_add_f64 v[26:27], v[19:20], -v[21:22]
	v_add_f64 v[11:12], v[11:12], -v[21:22]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_ldexp_f64 v[21:22], v[28:29], -2
	v_add_f64 v[15:16], v[28:29], -v[15:16]
	v_add_f64 v[17:18], v[17:18], -v[26:27]
	v_add_f64 v[26:27], v[30:31], v[13:14]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[21:22]|
	v_add_f64 v[15:16], v[19:20], -v[15:16]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[11:12], v[11:12], v[17:18]
	v_fract_f64_e32 v[17:18], v[21:22]
	v_add_f64 v[19:20], v[26:27], v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v18, 0, v18 :: v_dual_cndmask_b32 v17, 0, v17
	v_ldexp_f64 v[17:18], v[17:18], 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[21:22], v[15:16], v[19:20]
	v_add_f64 v[32:33], v[19:20], -v[26:27]
	v_add_f64 v[28:29], v[21:22], v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_f64 v[38:39], v[19:20], -v[32:33]
	v_add_f64 v[11:12], v[11:12], -v[32:33]
	v_add_f64 v[15:16], v[21:22], -v[15:16]
	v_cmp_gt_f64_e32 vcc_lo, 0, v[28:29]
	v_add_f64 v[28:29], v[26:27], -v[30:31]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_f64 v[15:16], v[19:20], -v[15:16]
	s_and_b32 s2, vcc_lo, exec_lo
	s_cselect_b32 s5, 0x40100000, 0
	v_add_f64 v[36:37], v[26:27], -v[28:29]
	v_add_f64 v[17:18], v[17:18], s[4:5]
	v_add_f64 v[13:14], v[13:14], -v[28:29]
	v_add_f64 v[26:27], v[26:27], -v[38:39]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[28:29], v[30:31], -v[36:37]
	v_add_f64 v[34:35], v[21:22], v[17:18]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[11:12], v[11:12], v[26:27]
	v_add_f64 v[13:14], v[13:14], v[28:29]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f64_e32 v34, v[34:35]
	v_add_f64 v[11:12], v[13:14], v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_i32_e32 v[32:33], v34
	v_add_f64 v[9:10], v[9:10], v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[17:18], v[17:18], -v[32:33]
	v_add_f64 v[9:10], v[15:16], v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[13:14], v[21:22], v[17:18]
	v_add_f64 v[11:12], v[13:14], -v[17:18]
	v_cmp_le_f64_e32 vcc_lo, 0.5, v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_f64 v[11:12], v[21:22], -v[11:12]
	s_and_b32 s2, vcc_lo, exec_lo
	s_cselect_b32 s5, 0x3ff00000, 0
	v_add_co_ci_u32_e64 v26, s2, 0, v34, vcc_lo
	s_mov_b32 s2, 0
	v_add_f64 v[9:10], v[9:10], v[11:12]
	v_add_f64 v[11:12], v[13:14], -s[4:5]
	s_mov_b32 s4, 0x54442d18
	s_mov_b32 s5, 0x3ff921fb
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[13:14], v[11:12], v[9:10]
	v_mul_f64 v[15:16], v[13:14], s[4:5]
	v_add_f64 v[11:12], v[13:14], -v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[17:18], v[13:14], s[4:5], -v[15:16]
	v_add_f64 v[9:10], v[9:10], -v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], v[13:14], s[10:11], v[17:18]
	v_fma_f64 v[11:12], v[9:10], s[4:5], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[9:10], v[15:16], v[11:12]
	v_add_f64 v[13:14], v[9:10], -v[15:16]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[11:12], v[11:12], -v[13:14]
	s_branch .LBB1_10
.LBB1_9:
                                        ; implicit-def: $vgpr26
                                        ; implicit-def: $vgpr9_vgpr10
                                        ; implicit-def: $vgpr11_vgpr12
.LBB1_10:                               ; %Flow147
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB1_12
; %bb.11:
	s_mov_b32 s4, 0x6dc9c883
	s_mov_b32 s5, 0x3fe45f30
	s_mov_b32 s11, 0xbc91a626
	v_mul_f64 v[9:10], |v[7:8]|, s[4:5]
	s_mov_b32 s4, 0x54442d18
	s_mov_b32 s5, 0xbff921fb
	s_mov_b32 s10, 0x33145c00
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[13:14], v[9:10]
	v_fma_f64 v[9:10], v[13:14], s[4:5], |v[7:8]|
	v_mul_f64 v[11:12], v[13:14], s[10:11]
	s_mov_b32 s4, 0x252049c0
	s_mov_b32 s5, 0xb97b839a
	v_cvt_i32_f64_e32 v26, v[13:14]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[17:18], v[13:14], s[10:11], v[9:10]
	v_add_f64 v[15:16], v[9:10], v[11:12]
	s_mov_b32 s11, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[9:10], v[9:10], -v[15:16]
	v_add_f64 v[15:16], v[15:16], -v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[9:10], v[9:10], v[11:12]
	v_fma_f64 v[11:12], v[13:14], s[10:11], v[11:12]
	v_add_f64 v[9:10], v[15:16], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[9:10], v[9:10], -v[11:12]
	v_fma_f64 v[11:12], v[13:14], s[4:5], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[9:10], v[17:18], v[11:12]
	v_add_f64 v[15:16], v[9:10], -v[17:18]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[11:12], v[11:12], -v[15:16]
.LBB1_12:                               ; %_ZL3sind.exit65
	v_cvt_f64_i32_e32 v[13:14], s6
	s_mov_b32 s4, 0x51eb851f
	s_mov_b32 s5, 0x40191eb8
	v_cvt_f64_i32_e32 v[21:22], s27
	s_ashr_i32 s2, s24, 31
	s_add_i32 s3, s3, -1
	s_add_i32 s6, s24, s2
	s_ashr_i32 s7, s9, 31
	s_xor_b32 s2, s6, s2
	s_add_i32 s8, s9, s7
	v_cvt_f32_u32_e32 v27, s2
	s_sub_i32 s6, 0, s2
	s_xor_b32 s8, s8, s7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_rcp_iflag_f32_e32 v27, v27
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v29, 0x4f7ffffe, v27
	v_cvt_f64_i32_e32 v[27:28], s3
	v_cvt_u32_f32_e32 v29, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s3, v29
	v_div_scale_f64 v[15:16], null, v[13:14], v[13:14], s[4:5]
	s_mul_i32 s6, s6, s3
	v_mul_f64 v[21:22], v[21:22], s[30:31]
	s_mul_hi_u32 s6, s3, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s3, s3, s6
	s_mul_hi_u32 s3, s8, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s3, s3, s2
	s_sub_i32 s3, s8, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_sub_i32 s6, s3, s2
	s_cmp_ge_u32 s3, s2
	s_cselect_b32 s3, s6, s3
	s_sub_i32 s6, s3, s2
	s_cmp_ge_u32 s3, s2
	s_cselect_b32 s2, s6, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s2, s2, s7
	s_sub_i32 s2, s2, s7
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_min_i32 s2, s2, s27
	v_rcp_f64_e32 v[17:18], v[15:16]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[19:20], -v[15:16], v[17:18], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[17:18], v[19:20], v[17:18]
	v_fma_f64 v[19:20], -v[15:16], v[17:18], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[17:18], v[19:20], v[17:18]
	v_div_scale_f64 v[19:20], vcc_lo, s[4:5], v[13:14], s[4:5]
	v_mul_f64 v[23:24], v[19:20], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_fma_f64 v[15:16], -v[15:16], v[23:24], v[19:20]
	v_fma_f64 v[19:20], v[27:28], s[20:21], v[21:22]
	v_cvt_f64_i32_e32 v[21:22], s2
	s_mov_b32 s2, -1
	v_div_fmas_f64 v[15:16], v[15:16], v[17:18], v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[17:18], v[21:22], s[20:21], v[19:20]
	v_div_fixup_f64 v[13:14], v[15:16], v[13:14], s[4:5]
	s_mov_b32 s4, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[13:14], v[13:14], v[17:18]
	v_cmp_ngt_f64_e64 s3, 0x41d00000, |v[13:14]|
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccz .LBB1_14
; %bb.13:
	v_ldexp_f64 v[15:16], |v[13:14]|, 0xffffff80
	v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[13:14]|
	v_trig_preop_f64 v[17:18], |v[13:14]|, 0
	v_and_b32_e32 v19, 0x7fffffff, v14
	v_trig_preop_f64 v[31:32], |v[13:14]|, 2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v16, v19, v16 :: v_dual_cndmask_b32 v15, v13, v15
	v_trig_preop_f64 v[19:20], |v[13:14]|, 1
	v_mul_f64 v[21:22], v[17:18], v[15:16]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[37:38], v[31:32], v[15:16]
	v_mul_f64 v[23:24], v[19:20], v[15:16]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[17:18], v[17:18], v[15:16], -v[21:22]
	v_fma_f64 v[19:20], v[19:20], v[15:16], -v[23:24]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[15:16], v[31:32], v[15:16], -v[37:38]
	v_add_f64 v[27:28], v[23:24], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[29:30], v[27:28], -v[23:24]
	v_add_f64 v[35:36], v[21:22], v[27:28]
	v_add_f64 v[33:34], v[27:28], -v[29:30]
	v_add_f64 v[17:18], v[17:18], -v[29:30]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_ldexp_f64 v[29:30], v[35:36], -2
	v_add_f64 v[21:22], v[35:36], -v[21:22]
	v_add_f64 v[23:24], v[23:24], -v[33:34]
	v_add_f64 v[33:34], v[37:38], v[19:20]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[29:30]|
	v_add_f64 v[21:22], v[27:28], -v[21:22]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[17:18], v[17:18], v[23:24]
	v_fract_f64_e32 v[23:24], v[29:30]
	v_add_f64 v[27:28], v[33:34], v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v24, 0, v24 :: v_dual_cndmask_b32 v23, 0, v23
	v_ldexp_f64 v[23:24], v[23:24], 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[29:30], v[21:22], v[27:28]
	v_add_f64 v[39:40], v[27:28], -v[33:34]
	v_add_f64 v[35:36], v[29:30], v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_f64 v[45:46], v[27:28], -v[39:40]
	v_add_f64 v[17:18], v[17:18], -v[39:40]
	v_add_f64 v[21:22], v[29:30], -v[21:22]
	v_cmp_gt_f64_e32 vcc_lo, 0, v[35:36]
	v_add_f64 v[35:36], v[33:34], -v[37:38]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_f64 v[21:22], v[27:28], -v[21:22]
	s_and_b32 s2, vcc_lo, exec_lo
	s_cselect_b32 s5, 0x40100000, 0
	v_add_f64 v[43:44], v[33:34], -v[35:36]
	v_add_f64 v[23:24], v[23:24], s[4:5]
	v_add_f64 v[19:20], v[19:20], -v[35:36]
	v_add_f64 v[33:34], v[33:34], -v[45:46]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[35:36], v[37:38], -v[43:44]
	v_add_f64 v[41:42], v[29:30], v[23:24]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[17:18], v[17:18], v[33:34]
	v_add_f64 v[19:20], v[19:20], v[35:36]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f64_e32 v41, v[41:42]
	v_add_f64 v[17:18], v[19:20], v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_i32_e32 v[39:40], v41
	v_add_f64 v[15:16], v[15:16], v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[23:24], v[23:24], -v[39:40]
	v_add_f64 v[15:16], v[21:22], v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[19:20], v[29:30], v[23:24]
	v_add_f64 v[17:18], v[19:20], -v[23:24]
	v_cmp_le_f64_e32 vcc_lo, 0.5, v[19:20]
	s_delay_alu instid0(VALU_DEP_2)
	v_add_f64 v[17:18], v[29:30], -v[17:18]
	s_and_b32 s2, vcc_lo, exec_lo
	s_cselect_b32 s5, 0x3ff00000, 0
	v_add_co_ci_u32_e64 v27, s2, 0, v41, vcc_lo
	s_mov_b32 s2, 0x54442d18
	s_mov_b32 s3, 0x3ff921fb
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_f64 v[15:16], v[15:16], v[17:18]
	v_add_f64 v[17:18], v[19:20], -s[4:5]
	s_mov_b32 s4, 0x33145c07
	s_mov_b32 s5, 0x3c91a626
	v_add_f64 v[19:20], v[17:18], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f64 v[21:22], v[19:20], s[2:3]
	v_add_f64 v[17:18], v[19:20], -v[17:18]
	v_fma_f64 v[23:24], v[19:20], s[2:3], -v[21:22]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[15:16], v[15:16], -v[17:18]
	v_fma_f64 v[17:18], v[19:20], s[4:5], v[23:24]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[15:16], s[2:3], v[17:18]
	s_mov_b32 s2, 0
	v_add_f64 v[15:16], v[21:22], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[19:20], v[15:16], -v[21:22]
	v_add_f64 v[19:20], v[17:18], -v[19:20]
	s_branch .LBB1_15
.LBB1_14:
                                        ; implicit-def: $vgpr27
                                        ; implicit-def: $vgpr15_vgpr16
                                        ; implicit-def: $vgpr19_vgpr20
.LBB1_15:                               ; %Flow146
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB1_17
; %bb.16:
	s_mov_b32 s2, 0x6dc9c883
	s_mov_b32 s3, 0x3fe45f30
	s_mov_b32 s5, 0xbc91a626
	v_mul_f64 v[15:16], |v[13:14]|, s[2:3]
	s_mov_b32 s2, 0x54442d18
	s_mov_b32 s3, 0xbff921fb
	s_mov_b32 s4, 0x33145c00
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[17:18], v[15:16]
	v_fma_f64 v[15:16], v[17:18], s[2:3], |v[13:14]|
	v_mul_f64 v[19:20], v[17:18], s[4:5]
	s_mov_b32 s2, 0x252049c0
	s_mov_b32 s3, 0xb97b839a
	v_cvt_i32_f64_e32 v27, v[17:18]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[23:24], v[17:18], s[4:5], v[15:16]
	v_add_f64 v[21:22], v[15:16], v[19:20]
	s_mov_b32 s5, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[15:16], v[15:16], -v[21:22]
	v_add_f64 v[21:22], v[21:22], -v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[15:16], v[15:16], v[19:20]
	v_fma_f64 v[19:20], v[17:18], s[4:5], v[19:20]
	v_add_f64 v[15:16], v[21:22], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[15:16], v[15:16], -v[19:20]
	v_fma_f64 v[19:20], v[17:18], s[2:3], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[15:16], v[23:24], v[19:20]
	v_add_f64 v[21:22], v[15:16], -v[23:24]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[19:20], v[19:20], -v[21:22]
.LBB1_17:                               ; %_ZL3sind.exit70
	s_load_b128 s[4:7], s[0:1], 0x80
	v_mov_b32_e32 v17, 0x51eb851f
	v_mov_b32_e32 v18, 0x40191eb8
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], s[4:5], s[6:7], v[17:18]
	v_cmp_ngt_f64_e64 s2, 0x41d00000, |v[17:18]|
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccz .LBB1_19
; %bb.18:
	v_ldexp_f64 v[21:22], |v[17:18]|, 0xffffff80
	v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[17:18]|
	v_trig_preop_f64 v[23:24], |v[17:18]|, 0
	v_and_b32_e32 v28, 0x7fffffff, v18
	v_trig_preop_f64 v[38:39], |v[17:18]|, 2
	s_mov_b32 s4, 0
	s_mov_b32 s6, 0x33145c07
	s_mov_b32 s7, 0x3c91a626
	v_dual_cndmask_b32 v21, v17, v21 :: v_dual_cndmask_b32 v22, v28, v22
	v_trig_preop_f64 v[28:29], |v[17:18]|, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[30:31], v[23:24], v[21:22]
	v_mul_f64 v[32:33], v[28:29], v[21:22]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[23:24], v[23:24], v[21:22], -v[30:31]
	v_fma_f64 v[28:29], v[28:29], v[21:22], -v[32:33]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[34:35], v[32:33], v[23:24]
	v_add_f64 v[36:37], v[34:35], -v[32:33]
	v_add_f64 v[42:43], v[30:31], v[34:35]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[40:41], v[34:35], -v[36:37]
	v_add_f64 v[23:24], v[23:24], -v[36:37]
	v_ldexp_f64 v[36:37], v[42:43], -2
	v_add_f64 v[30:31], v[42:43], -v[30:31]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[32:33], v[32:33], -v[40:41]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[36:37]|
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[30:31], v[34:35], -v[30:31]
	v_add_f64 v[23:24], v[23:24], v[32:33]
	v_fract_f64_e32 v[32:33], v[36:37]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v33, 0, v33, vcc_lo
	v_mul_f64 v[44:45], v[38:39], v[21:22]
	v_cndmask_b32_e32 v32, 0, v32, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ldexp_f64 v[32:33], v[32:33], 2
	v_add_f64 v[40:41], v[44:45], v[28:29]
	v_fma_f64 v[21:22], v[38:39], v[21:22], -v[44:45]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[34:35], v[40:41], v[23:24]
	v_add_f64 v[36:37], v[30:31], v[34:35]
	v_add_f64 v[46:47], v[34:35], -v[40:41]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[42:43], v[36:37], v[32:33]
	v_add_f64 v[52:53], v[34:35], -v[46:47]
	v_add_f64 v[23:24], v[23:24], -v[46:47]
	v_add_f64 v[30:31], v[36:37], -v[30:31]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e32 vcc_lo, 0, v[42:43]
	v_add_f64 v[42:43], v[40:41], -v[44:45]
	s_and_b32 s2, vcc_lo, exec_lo
	s_cselect_b32 s5, 0x40100000, 0
	v_add_f64 v[50:51], v[40:41], -v[42:43]
	v_add_f64 v[32:33], v[32:33], s[4:5]
	v_add_f64 v[28:29], v[28:29], -v[42:43]
	v_add_f64 v[40:41], v[40:41], -v[52:53]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[42:43], v[44:45], -v[50:51]
	v_add_f64 v[48:49], v[36:37], v[32:33]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[23:24], v[23:24], v[40:41]
	v_add_f64 v[28:29], v[28:29], v[42:43]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f64_e32 v48, v[48:49]
	v_add_f64 v[23:24], v[28:29], v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cvt_f64_i32_e32 v[46:47], v48
	v_add_f64 v[28:29], v[34:35], -v[30:31]
	v_add_f64 v[21:22], v[21:22], v[23:24]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[32:33], v[32:33], -v[46:47]
	v_add_f64 v[21:22], v[28:29], v[21:22]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[38:39], v[36:37], v[32:33]
	v_add_f64 v[23:24], v[38:39], -v[32:33]
	v_cmp_le_f64_e32 vcc_lo, 0.5, v[38:39]
	s_delay_alu instid0(VALU_DEP_2)
	v_add_f64 v[23:24], v[36:37], -v[23:24]
	s_and_b32 s2, vcc_lo, exec_lo
	s_cselect_b32 s5, 0x3ff00000, 0
	v_add_co_ci_u32_e64 v28, s2, 0, v48, vcc_lo
	s_mov_b32 s2, 0x54442d18
	s_mov_b32 s3, 0x3ff921fb
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[21:22], v[21:22], v[23:24]
	v_add_f64 v[23:24], v[38:39], -s[4:5]
	v_add_f64 v[29:30], v[23:24], v[21:22]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f64 v[31:32], v[29:30], s[2:3]
	v_add_f64 v[23:24], v[29:30], -v[23:24]
	v_fma_f64 v[33:34], v[29:30], s[2:3], -v[31:32]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[21:22], v[21:22], -v[23:24]
	v_fma_f64 v[23:24], v[29:30], s[6:7], v[33:34]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[23:24], v[21:22], s[2:3], v[23:24]
	v_add_f64 v[21:22], v[31:32], v[23:24]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[29:30], v[21:22], -v[31:32]
	v_add_f64 v[23:24], v[23:24], -v[29:30]
	s_branch .LBB1_20
.LBB1_19:
	s_mov_b32 s4, -1
                                        ; implicit-def: $vgpr28
                                        ; implicit-def: $vgpr21_vgpr22
                                        ; implicit-def: $vgpr23_vgpr24
.LBB1_20:                               ; %Flow
	s_load_b32 s5, s[0:1], 0x9c
	s_and_not1_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccnz .LBB1_22
; %bb.21:
	s_mov_b32 s2, 0x6dc9c883
	s_mov_b32 s3, 0x3fe45f30
	s_mov_b32 s7, 0xbc91a626
	v_mul_f64 v[21:22], |v[17:18]|, s[2:3]
	s_mov_b32 s2, 0x54442d18
	s_mov_b32 s3, 0xbff921fb
	s_mov_b32 s6, 0x33145c00
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[28:29], v[21:22]
	v_fma_f64 v[21:22], v[28:29], s[2:3], |v[17:18]|
	v_mul_f64 v[23:24], v[28:29], s[6:7]
	s_mov_b32 s2, 0x252049c0
	s_mov_b32 s3, 0xb97b839a
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[32:33], v[28:29], s[6:7], v[21:22]
	v_add_f64 v[30:31], v[21:22], v[23:24]
	s_mov_b32 s7, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[21:22], v[21:22], -v[30:31]
	v_add_f64 v[30:31], v[30:31], -v[32:33]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[21:22], v[21:22], v[23:24]
	v_fma_f64 v[23:24], v[28:29], s[6:7], v[23:24]
	v_add_f64 v[21:22], v[30:31], v[21:22]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[21:22], v[21:22], -v[23:24]
	v_fma_f64 v[23:24], v[28:29], s[2:3], v[21:22]
	v_cvt_i32_f64_e32 v28, v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[21:22], v[32:33], v[23:24]
	v_add_f64 v[30:31], v[21:22], -v[32:33]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[23:24], v[23:24], -v[30:31]
.LBB1_22:                               ; %_ZL3cosd.exit
	v_mul_f64 v[29:30], v[3:4], v[3:4]
	v_mul_f64 v[31:32], v[9:10], v[9:10]
	v_mul_f64 v[33:34], v[15:16], v[15:16]
	s_mov_b32 s2, 0xb42fdfa7
	s_mov_b32 s6, 0xf9a43bb8
	s_mov_b32 s3, 0xbe5ae600
	s_mov_b32 s7, 0x3de5e0b2
	v_mul_f64 v[39:40], v[21:22], v[21:22]
	s_mov_b32 s8, 0x9037ab78
	s_mov_b32 s10, 0x46cc5e42
	s_mov_b32 s12, 0x796cde01
	s_mov_b32 s9, 0x3e21eeb6
	s_mov_b32 s11, 0xbda907db
	s_mov_b32 s13, 0x3ec71de3
	s_mov_b32 s16, 0xa17f65f6
	s_mov_b32 s18, 0x19e83e5c
	s_mov_b32 s17, 0xbe927e4f
	s_mov_b32 s19, 0xbf2a01a0
	v_mul_f64 v[61:62], v[5:6], 0.5
	v_mul_f64 v[63:64], v[11:12], 0.5
	v_mul_f64 v[79:80], v[19:20], 0.5
	v_cmp_class_f64_e64 s4, v[7:8], 0x1f8
	s_load_b64 s[0:1], s[0:1], 0x0
	v_fma_f64 v[35:36], v[29:30], s[6:7], s[2:3]
	v_fma_f64 v[37:38], v[31:32], s[6:7], s[2:3]
	v_fma_f64 v[41:42], v[33:34], s[6:7], s[2:3]
	v_fma_f64 v[43:44], v[29:30], s[10:11], s[8:9]
	v_mul_f64 v[45:46], v[29:30], 0.5
	v_fma_f64 v[47:48], v[31:32], s[10:11], s[8:9]
	v_mul_f64 v[49:50], v[31:32], 0.5
	v_fma_f64 v[51:52], v[33:34], s[10:11], s[8:9]
	v_fma_f64 v[53:54], v[39:40], s[6:7], s[2:3]
	v_mul_f64 v[55:56], v[33:34], 0.5
	v_fma_f64 v[67:68], v[39:40], s[10:11], s[8:9]
	v_mul_f64 v[69:70], v[39:40], 0.5
	s_mov_b32 s2, 0x19f4ec90
	s_mov_b32 s6, 0x11110bb3
	s_mov_b32 s3, 0x3efa01a0
	s_mov_b32 s7, 0x3f811111
	v_mul_f64 v[65:66], v[3:4], -v[29:30]
	v_mul_f64 v[71:72], v[9:10], -v[31:32]
	v_mul_f64 v[83:84], v[15:16], -v[33:34]
	s_mov_b32 s8, 0x16c16967
	s_mov_b32 s9, 0xbf56c16c
	v_mul_f64 v[87:88], v[21:22], -v[39:40]
	s_mov_b32 s10, 0x55555555
	s_mov_b32 s11, 0x3fa55555
	v_fma_f64 v[35:36], v[29:30], v[35:36], s[12:13]
	v_fma_f64 v[37:38], v[31:32], v[37:38], s[12:13]
	v_fma_f64 v[41:42], v[33:34], v[41:42], s[12:13]
	v_fma_f64 v[43:44], v[29:30], v[43:44], s[16:17]
	v_add_f64 v[57:58], -v[45:46], 1.0
	v_fma_f64 v[47:48], v[31:32], v[47:48], s[16:17]
	v_add_f64 v[59:60], -v[49:50], 1.0
	v_fma_f64 v[51:52], v[33:34], v[51:52], s[16:17]
	v_fma_f64 v[53:54], v[39:40], v[53:54], s[12:13]
	v_add_f64 v[73:74], -v[55:56], 1.0
	v_fma_f64 v[67:68], v[39:40], v[67:68], s[16:17]
	v_add_f64 v[81:82], -v[69:70], 1.0
	v_fma_f64 v[35:36], v[29:30], v[35:36], s[18:19]
	v_fma_f64 v[37:38], v[31:32], v[37:38], s[18:19]
	v_fma_f64 v[41:42], v[33:34], v[41:42], s[18:19]
	v_fma_f64 v[43:44], v[29:30], v[43:44], s[2:3]
	v_add_f64 v[75:76], -v[57:58], 1.0
	v_fma_f64 v[47:48], v[31:32], v[47:48], s[2:3]
	v_add_f64 v[77:78], -v[59:60], 1.0
	v_fma_f64 v[51:52], v[33:34], v[51:52], s[2:3]
	v_fma_f64 v[53:54], v[39:40], v[53:54], s[18:19]
	v_add_f64 v[85:86], -v[73:74], 1.0
	v_fma_f64 v[67:68], v[39:40], v[67:68], s[2:3]
	s_mov_b32 s3, 0xbfc55555
	s_mov_b32 s2, s10
	v_fma_f64 v[35:36], v[29:30], v[35:36], s[6:7]
	v_fma_f64 v[37:38], v[31:32], v[37:38], s[6:7]
	v_fma_f64 v[41:42], v[33:34], v[41:42], s[6:7]
	v_fma_f64 v[43:44], v[29:30], v[43:44], s[8:9]
	v_add_f64 v[45:46], v[75:76], -v[45:46]
	v_fma_f64 v[47:48], v[31:32], v[47:48], s[8:9]
	v_add_f64 v[49:50], v[77:78], -v[49:50]
	v_add_f64 v[77:78], -v[81:82], 1.0
	v_fma_f64 v[51:52], v[33:34], v[51:52], s[8:9]
	v_fma_f64 v[53:54], v[39:40], v[53:54], s[6:7]
	v_add_f64 v[55:56], v[85:86], -v[55:56]
	v_mul_f64 v[75:76], v[31:32], v[31:32]
	v_fma_f64 v[35:36], v[65:66], v[35:36], v[61:62]
	v_fma_f64 v[37:38], v[71:72], v[37:38], v[63:64]
	v_mul_f64 v[61:62], v[23:24], 0.5
	v_fma_f64 v[41:42], v[83:84], v[41:42], v[79:80]
	v_mul_f64 v[63:64], v[29:30], v[29:30]
	v_fma_f64 v[43:44], v[29:30], v[43:44], s[10:11]
	v_fma_f64 v[45:46], v[3:4], -v[5:6], v[45:46]
	v_fma_f64 v[5:6], v[29:30], v[35:36], -v[5:6]
	v_fma_f64 v[29:30], v[31:32], v[47:48], s[10:11]
	v_fma_f64 v[35:36], v[9:10], -v[11:12], v[49:50]
	v_fma_f64 v[11:12], v[31:32], v[37:38], -v[11:12]
	v_fma_f64 v[31:32], v[39:40], v[67:68], s[8:9]
	v_add_f64 v[37:38], v[77:78], -v[69:70]
	v_fma_f64 v[49:50], v[33:34], v[51:52], s[10:11]
	v_fma_f64 v[51:52], v[87:88], v[53:54], v[61:62]
	v_mul_f64 v[47:48], v[33:34], v[33:34]
	v_fma_f64 v[53:54], v[15:16], -v[19:20], v[55:56]
	v_fma_f64 v[19:20], v[33:34], v[41:42], -v[19:20]
	v_fma_f64 v[33:34], v[63:64], v[43:44], v[45:46]
	v_fma_f64 v[5:6], v[65:66], s[2:3], v[5:6]
	v_fma_f64 v[29:30], v[75:76], v[29:30], v[35:36]
	v_fma_f64 v[11:12], v[71:72], s[2:3], v[11:12]
	v_mul_f64 v[35:36], v[39:40], v[39:40]
	v_fma_f64 v[31:32], v[39:40], v[31:32], s[10:11]
	v_fma_f64 v[37:38], v[21:22], -v[23:24], v[37:38]
	v_fma_f64 v[23:24], v[39:40], v[51:52], -v[23:24]
	v_fma_f64 v[39:40], v[47:48], v[49:50], v[53:54]
	v_fma_f64 v[19:20], v[83:84], s[2:3], v[19:20]
	v_add_f64 v[33:34], v[57:58], v[33:34]
	v_add_f64 v[3:4], v[3:4], -v[5:6]
	v_add_f64 v[5:6], v[59:60], v[29:30]
	v_add_f64 v[9:10], v[9:10], -v[11:12]
	v_fma_f64 v[11:12], v[35:36], v[31:32], v[37:38]
	v_fma_f64 v[23:24], v[87:88], s[2:3], v[23:24]
	v_cmp_class_f64_e64 s2, v[1:2], 0x1f8
	v_add_f64 v[29:30], v[73:74], v[39:40]
	v_add_f64 v[15:16], v[15:16], -v[19:20]
	v_and_b32_e32 v31, 1, v25
	v_lshlrev_b32_e32 v1, 30, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_eq_u32_e32 vcc_lo, 0, v31
	v_and_b32_e32 v32, 1, v26
	v_xor_b32_e32 v1, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_and_b32_e32 v7, 0x80000000, v1
	v_cndmask_b32_e32 v19, v33, v3, vcc_lo
	v_lshlrev_b32_e32 v3, 30, v26
	v_cmp_eq_u32_e64 s3, 0, v32
	v_xor_b32_e32 v2, v3, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v6, v6, v10, s3
	v_cndmask_b32_e64 v9, v5, v9, s3
	v_cmp_class_f64_e64 s3, v[13:14], 0x1f8
	v_and_b32_e32 v8, 0x80000000, v2
	v_add_f64 v[1:2], v[81:82], v[11:12]
	v_cndmask_b32_e32 v11, v34, v4, vcc_lo
	v_and_b32_e32 v5, 1, v27
	v_add_f64 v[3:4], v[21:22], -v[23:24]
	v_xor_b32_e32 v8, v6, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v11, v11, v7
	v_cmp_eq_u32_e32 vcc_lo, 0, v5
	v_cndmask_b32_e64 v5, 0, v19, s2
	v_cndmask_b32_e64 v7, 0, v9, s4
	v_cndmask_b32_e64 v8, 0x7ff80000, v8, s4
	v_cndmask_b32_e64 v6, 0x7ff80000, v11, s2
	v_cndmask_b32_e32 v10, v29, v15, vcc_lo
	v_cmp_class_f64_e64 s2, v[17:18], 0x1f8
	v_and_b32_e32 v9, 1, v28
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f64 v[5:6], v[5:6], v[7:8]
	v_dual_cndmask_b32 v8, v30, v16 :: v_dual_lshlrev_b32 v7, 30, v27
	v_cmp_eq_u32_e32 vcc_lo, 0, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v7, v7, v14
	v_and_b32_e32 v7, 0x80000000, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v8, v8, v7
	v_cndmask_b32_e64 v7, 0, v10, s3
	v_cndmask_b32_e64 v8, 0x7ff80000, v8, s3
	v_cndmask_b32_e32 v1, v3, v1, vcc_lo
	v_xor_b32_e32 v3, 0x80000000, v4
	v_lshlrev_b32_e32 v4, 30, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v2, v3, v2 :: v_dual_and_b32 v3, 0x80000000, v4
	v_cndmask_b32_e64 v1, 0, v1, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v2, v2, v3
	v_mul_f64 v[5:6], v[5:6], v[7:8]
	v_cndmask_b32_e64 v2, 0x7ff80000, v2, s2
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, 0xffff, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[1:2], v[5:6], v[1:2]
	v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	global_store_b64 v[3:4], v[1:2], off
.LBB1_23:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10first_stepPdS_iiiddddddiiiiiiiiiiiidd
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 400
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 89
		.amdhsa_next_free_sgpr 32
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z10first_stepPdS_iiiddddddiiiiiiiiiiiidd, .Lfunc_end1-_Z10first_stepPdS_iiiddddddiiiiiiiiiiiidd
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 6720
; NumSgprs: 34
; NumVgprs: 89
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 11
; NumSGPRsForWavesPerEU: 34
; NumVGPRsForWavesPerEU: 89
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z20calculate_inner_gridPdS_S_iii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z20calculate_inner_gridPdS_S_iii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           8
        .value_kind:     by_value
      - .offset:         56
        .size:           8
        .value_kind:     by_value
      - .offset:         64
        .size:           8
        .value_kind:     by_value
      - .offset:         72
        .size:           8
        .value_kind:     by_value
      - .offset:         80
        .size:           4
        .value_kind:     by_value
      - .offset:         84
        .size:           4
        .value_kind:     by_value
      - .offset:         88
        .size:           4
        .value_kind:     by_value
      - .offset:         92
        .size:           4
        .value_kind:     by_value
      - .offset:         96
        .size:           4
        .value_kind:     by_value
      - .offset:         100
        .size:           4
        .value_kind:     by_value
      - .offset:         104
        .size:           4
        .value_kind:     by_value
      - .offset:         108
        .size:           4
        .value_kind:     by_value
      - .offset:         112
        .size:           4
        .value_kind:     by_value
      - .offset:         116
        .size:           4
        .value_kind:     by_value
      - .offset:         120
        .size:           4
        .value_kind:     by_value
      - .offset:         124
        .size:           4
        .value_kind:     by_value
      - .offset:         128
        .size:           8
        .value_kind:     by_value
      - .offset:         136
        .size:           8
        .value_kind:     by_value
      - .offset:         144
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         148
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         152
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         156
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         158
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         160
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         162
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         164
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         166
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         184
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         192
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         200
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         208
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 400
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10first_stepPdS_iiiddddddiiiiiiiiiiiidd
    .private_segment_fixed_size: 0
    .sgpr_count:     34
    .sgpr_spill_count: 0
    .symbol:         _Z10first_stepPdS_iiiddddddiiiiiiiiiiiidd.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     89
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
