#include "includes.h"
extern "C" {
}



#define TB 256
#define EPS 1e-4

__device__ bool InverseMat4x4(double m_in[4][4], double inv_out[4][4]) {
double m[16], inv[16];
for (int i = 0; i < 4; i++) {
for (int j = 0; j < 4; j++) {
m[i * 4 + j] = m_in[i][j];
}
}

inv[0] = m[5]  * m[10] * m[15] -
m[5]  * m[11] * m[14] -
m[9]  * m[6]  * m[15] +
m[9]  * m[7]  * m[14] +
m[13] * m[6]  * m[11] -
m[13] * m[7]  * m[10];

inv[4] = -m[4]  * m[10] * m[15] +
m[4]  * m[11] * m[14] +
m[8]  * m[6]  * m[15] -
m[8]  * m[7]  * m[14] -
m[12] * m[6]  * m[11] +
m[12] * m[7]  * m[10];

inv[8] = m[4]  * m[9] * m[15] -
m[4]  * m[11] * m[13] -
m[8]  * m[5] * m[15] +
m[8]  * m[7] * m[13] +
m[12] * m[5] * m[11] -
m[12] * m[7] * m[9];

inv[12] = -m[4]  * m[9] * m[14] +
m[4]  * m[10] * m[13] +
m[8]  * m[5] * m[14] -
m[8]  * m[6] * m[13] -
m[12] * m[5] * m[10] +
m[12] * m[6] * m[9];

inv[1] = -m[1]  * m[10] * m[15] +
m[1]  * m[11] * m[14] +
m[9]  * m[2] * m[15] -
m[9]  * m[3] * m[14] -
m[13] * m[2] * m[11] +
m[13] * m[3] * m[10];

inv[5] = m[0]  * m[10] * m[15] -
m[0]  * m[11] * m[14] -
m[8]  * m[2] * m[15] +
m[8]  * m[3] * m[14] +
m[12] * m[2] * m[11] -
m[12] * m[3] * m[10];

inv[9] = -m[0]  * m[9] * m[15] +
m[0]  * m[11] * m[13] +
m[8]  * m[1] * m[15] -
m[8]  * m[3] * m[13] -
m[12] * m[1] * m[11] +
m[12] * m[3] * m[9];

inv[13] = m[0]  * m[9] * m[14] -
m[0]  * m[10] * m[13] -
m[8]  * m[1] * m[14] +
m[8]  * m[2] * m[13] +
m[12] * m[1] * m[10] -
m[12] * m[2] * m[9];

inv[2] = m[1]  * m[6] * m[15] -
m[1]  * m[7] * m[14] -
m[5]  * m[2] * m[15] +
m[5]  * m[3] * m[14] +
m[13] * m[2] * m[7] -
m[13] * m[3] * m[6];

inv[6] = -m[0]  * m[6] * m[15] +
m[0]  * m[7] * m[14] +
m[4]  * m[2] * m[15] -
m[4]  * m[3] * m[14] -
m[12] * m[2] * m[7] +
m[12] * m[3] * m[6];

inv[10] = m[0]  * m[5] * m[15] -
m[0]  * m[7] * m[13] -
m[4]  * m[1] * m[15] +
m[4]  * m[3] * m[13] +
m[12] * m[1] * m[7] -
m[12] * m[3] * m[5];

inv[14] = -m[0]  * m[5] * m[14] +
m[0]  * m[6] * m[13] +
m[4]  * m[1] * m[14] -
m[4]  * m[2] * m[13] -
m[12] * m[1] * m[6] +
m[12] * m[2] * m[5];

inv[3] = -m[1] * m[6] * m[11] +
m[1] * m[7] * m[10] +
m[5] * m[2] * m[11] -
m[5] * m[3] * m[10] -
m[9] * m[2] * m[7] +
m[9] * m[3] * m[6];

inv[7] = m[0] * m[6] * m[11] -
m[0] * m[7] * m[10] -
m[4] * m[2] * m[11] +
m[4] * m[3] * m[10] +
m[8] * m[2] * m[7] -
m[8] * m[3] * m[6];

inv[11] = -m[0] * m[5] * m[11] +
m[0] * m[7] * m[9] +
m[4] * m[1] * m[11] -
m[4] * m[3] * m[9] -
m[8] * m[1] * m[7] +
m[8] * m[3] * m[5];

inv[15] = m[0] * m[5] * m[10] -
m[0] * m[6] * m[9] -
m[4] * m[1] * m[10] +
m[4] * m[2] * m[9] +
m[8] * m[1] * m[6] -
m[8] * m[2] * m[5];

double det = m[0] * inv[0] + m[1] * inv[4] + m[2] * inv[8] + m[3] * inv[12];

if (abs(det) < 1e-9) {
return false;
}


det = 1.0 / det;

for (int i = 0; i < 4; i++) {
for (int j = 0; j < 4; j++) {
inv_out[i][j] = inv[i * 4 + j] * det;
}
}

return true;
}
__global__ void best_local_affine_kernel( float *output, float *input, float *affine_model, int h, int w, float epsilon, int kernel_radius )
{
int size = h * w;
int id = blockIdx.x * blockDim.x + threadIdx.x;

if (id < size) {
int x = id % w, y = id / w;

double Mt_M[4][4] = {}; // 4x4
double invMt_M[4][4] = {};
double Mt_S[3][4] = {}; // RGB -> 1x4
double A[3][4] = {};
for (int i = 0; i < 4; i++)
for (int j = 0; j < 4; j++) {
Mt_M[i][j] = 0, invMt_M[i][j] = 0;
if (i != 3) {
Mt_S[i][j] = 0, A[i][j] = 0;
if (i == j)
Mt_M[i][j] = 1e-3;
}
}

for (int dy = -kernel_radius; dy <= kernel_radius; dy++) {
for (int dx = -kernel_radius; dx <= kernel_radius; dx++) {

int xx = x + dx, yy = y + dy;
int id2 = yy * w + xx;

if (0 <= xx && xx < w && 0 <= yy && yy < h) {

Mt_M[0][0] += input[id2 + 2*size] * input[id2 + 2*size];
Mt_M[0][1] += input[id2 + 2*size] * input[id2 + size];
Mt_M[0][2] += input[id2 + 2*size] * input[id2];
Mt_M[0][3] += input[id2 + 2*size];

Mt_M[1][0] += input[id2 + size] * input[id2 + 2*size];
Mt_M[1][1] += input[id2 + size] * input[id2 + size];
Mt_M[1][2] += input[id2 + size] * input[id2];
Mt_M[1][3] += input[id2 + size];

Mt_M[2][0] += input[id2] * input[id2 + 2*size];
Mt_M[2][1] += input[id2] * input[id2 + size];
Mt_M[2][2] += input[id2] * input[id2];
Mt_M[2][3] += input[id2];

Mt_M[3][0] += input[id2 + 2*size];
Mt_M[3][1] += input[id2 + size];
Mt_M[3][2] += input[id2];
Mt_M[3][3] += 1;

Mt_S[0][0] += input[id2 + 2*size] * output[id2 + 2*size];
Mt_S[0][1] += input[id2 + size] * output[id2 + 2*size];
Mt_S[0][2] += input[id2] * output[id2 + 2*size];
Mt_S[0][3] += output[id2 + 2*size];

Mt_S[1][0] += input[id2 + 2*size] * output[id2 + size];
Mt_S[1][1] += input[id2 + size] * output[id2 + size];
Mt_S[1][2] += input[id2] * output[id2 + size];
Mt_S[1][3] += output[id2 + size];

Mt_S[2][0] += input[id2 + 2*size] * output[id2];
Mt_S[2][1] += input[id2 + size] * output[id2];
Mt_S[2][2] += input[id2] * output[id2];
Mt_S[2][3] += output[id2];
}
}
}

bool success = InverseMat4x4(Mt_M, invMt_M);

for (int i = 0; i < 3; i++) {
for (int j = 0; j < 4; j++) {
for (int k = 0; k < 4; k++) {
A[i][j] += invMt_M[j][k] * Mt_S[i][k];
}
}
}

for (int i = 0; i < 3; i++) {
for (int j = 0; j < 4; j++) {
int affine_id = i * 4 + j;
affine_model[12 * id + affine_id] = A[i][j];
}
}



}
return ;
}
	.file	"tmpxft_002fd1bd_00000000-6_best_local_affine_kernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2011:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2011:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z13InverseMat4x4PA4_dS0_
	.type	_Z13InverseMat4x4PA4_dS0_, @function
_Z13InverseMat4x4PA4_dS0_:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2008:
	.size	_Z13InverseMat4x4PA4_dS0_, .-_Z13InverseMat4x4PA4_dS0_
	.globl	_Z52__device_stub__Z24best_local_affine_kernelPfS_S_iifiPfS_S_iifi
	.type	_Z52__device_stub__Z24best_local_affine_kernelPfS_S_iifiPfS_S_iifi, @function
_Z52__device_stub__Z24best_local_affine_kernelPfS_S_iifiPfS_S_iifi:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 8(%rsp)
	movss	%xmm0, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z24best_local_affine_kernelPfS_S_iifi(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L4:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z52__device_stub__Z24best_local_affine_kernelPfS_S_iifiPfS_S_iifi, .-_Z52__device_stub__Z24best_local_affine_kernelPfS_S_iifiPfS_S_iifi
	.globl	_Z24best_local_affine_kernelPfS_S_iifi
	.type	_Z24best_local_affine_kernelPfS_S_iifi, @function
_Z24best_local_affine_kernelPfS_S_iifi:
.LFB2034:
	.cfi_startproc
	endbr64
	jmp	_Z52__device_stub__Z24best_local_affine_kernelPfS_S_iifiPfS_S_iifi
	.cfi_endproc
.LFE2034:
	.size	_Z24best_local_affine_kernelPfS_S_iifi, .-_Z24best_local_affine_kernelPfS_S_iifi
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z24best_local_affine_kernelPfS_S_iifi"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2036:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z24best_local_affine_kernelPfS_S_iifi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2036:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
extern "C" {
}



#define TB 256
#define EPS 1e-4

__device__ bool InverseMat4x4(double m_in[4][4], double inv_out[4][4]) {
double m[16], inv[16];
for (int i = 0; i < 4; i++) {
for (int j = 0; j < 4; j++) {
m[i * 4 + j] = m_in[i][j];
}
}

inv[0] = m[5]  * m[10] * m[15] -
m[5]  * m[11] * m[14] -
m[9]  * m[6]  * m[15] +
m[9]  * m[7]  * m[14] +
m[13] * m[6]  * m[11] -
m[13] * m[7]  * m[10];

inv[4] = -m[4]  * m[10] * m[15] +
m[4]  * m[11] * m[14] +
m[8]  * m[6]  * m[15] -
m[8]  * m[7]  * m[14] -
m[12] * m[6]  * m[11] +
m[12] * m[7]  * m[10];

inv[8] = m[4]  * m[9] * m[15] -
m[4]  * m[11] * m[13] -
m[8]  * m[5] * m[15] +
m[8]  * m[7] * m[13] +
m[12] * m[5] * m[11] -
m[12] * m[7] * m[9];

inv[12] = -m[4]  * m[9] * m[14] +
m[4]  * m[10] * m[13] +
m[8]  * m[5] * m[14] -
m[8]  * m[6] * m[13] -
m[12] * m[5] * m[10] +
m[12] * m[6] * m[9];

inv[1] = -m[1]  * m[10] * m[15] +
m[1]  * m[11] * m[14] +
m[9]  * m[2] * m[15] -
m[9]  * m[3] * m[14] -
m[13] * m[2] * m[11] +
m[13] * m[3] * m[10];

inv[5] = m[0]  * m[10] * m[15] -
m[0]  * m[11] * m[14] -
m[8]  * m[2] * m[15] +
m[8]  * m[3] * m[14] +
m[12] * m[2] * m[11] -
m[12] * m[3] * m[10];

inv[9] = -m[0]  * m[9] * m[15] +
m[0]  * m[11] * m[13] +
m[8]  * m[1] * m[15] -
m[8]  * m[3] * m[13] -
m[12] * m[1] * m[11] +
m[12] * m[3] * m[9];

inv[13] = m[0]  * m[9] * m[14] -
m[0]  * m[10] * m[13] -
m[8]  * m[1] * m[14] +
m[8]  * m[2] * m[13] +
m[12] * m[1] * m[10] -
m[12] * m[2] * m[9];

inv[2] = m[1]  * m[6] * m[15] -
m[1]  * m[7] * m[14] -
m[5]  * m[2] * m[15] +
m[5]  * m[3] * m[14] +
m[13] * m[2] * m[7] -
m[13] * m[3] * m[6];

inv[6] = -m[0]  * m[6] * m[15] +
m[0]  * m[7] * m[14] +
m[4]  * m[2] * m[15] -
m[4]  * m[3] * m[14] -
m[12] * m[2] * m[7] +
m[12] * m[3] * m[6];

inv[10] = m[0]  * m[5] * m[15] -
m[0]  * m[7] * m[13] -
m[4]  * m[1] * m[15] +
m[4]  * m[3] * m[13] +
m[12] * m[1] * m[7] -
m[12] * m[3] * m[5];

inv[14] = -m[0]  * m[5] * m[14] +
m[0]  * m[6] * m[13] +
m[4]  * m[1] * m[14] -
m[4]  * m[2] * m[13] -
m[12] * m[1] * m[6] +
m[12] * m[2] * m[5];

inv[3] = -m[1] * m[6] * m[11] +
m[1] * m[7] * m[10] +
m[5] * m[2] * m[11] -
m[5] * m[3] * m[10] -
m[9] * m[2] * m[7] +
m[9] * m[3] * m[6];

inv[7] = m[0] * m[6] * m[11] -
m[0] * m[7] * m[10] -
m[4] * m[2] * m[11] +
m[4] * m[3] * m[10] +
m[8] * m[2] * m[7] -
m[8] * m[3] * m[6];

inv[11] = -m[0] * m[5] * m[11] +
m[0] * m[7] * m[9] +
m[4] * m[1] * m[11] -
m[4] * m[3] * m[9] -
m[8] * m[1] * m[7] +
m[8] * m[3] * m[5];

inv[15] = m[0] * m[5] * m[10] -
m[0] * m[6] * m[9] -
m[4] * m[1] * m[10] +
m[4] * m[2] * m[9] +
m[8] * m[1] * m[6] -
m[8] * m[2] * m[5];

double det = m[0] * inv[0] + m[1] * inv[4] + m[2] * inv[8] + m[3] * inv[12];

if (abs(det) < 1e-9) {
return false;
}


det = 1.0 / det;

for (int i = 0; i < 4; i++) {
for (int j = 0; j < 4; j++) {
inv_out[i][j] = inv[i * 4 + j] * det;
}
}

return true;
}
__global__ void best_local_affine_kernel( float *output, float *input, float *affine_model, int h, int w, float epsilon, int kernel_radius )
{
int size = h * w;
int id = blockIdx.x * blockDim.x + threadIdx.x;

if (id < size) {
int x = id % w, y = id / w;

double Mt_M[4][4] = {}; // 4x4
double invMt_M[4][4] = {};
double Mt_S[3][4] = {}; // RGB -> 1x4
double A[3][4] = {};
for (int i = 0; i < 4; i++)
for (int j = 0; j < 4; j++) {
Mt_M[i][j] = 0, invMt_M[i][j] = 0;
if (i != 3) {
Mt_S[i][j] = 0, A[i][j] = 0;
if (i == j)
Mt_M[i][j] = 1e-3;
}
}

for (int dy = -kernel_radius; dy <= kernel_radius; dy++) {
for (int dx = -kernel_radius; dx <= kernel_radius; dx++) {

int xx = x + dx, yy = y + dy;
int id2 = yy * w + xx;

if (0 <= xx && xx < w && 0 <= yy && yy < h) {

Mt_M[0][0] += input[id2 + 2*size] * input[id2 + 2*size];
Mt_M[0][1] += input[id2 + 2*size] * input[id2 + size];
Mt_M[0][2] += input[id2 + 2*size] * input[id2];
Mt_M[0][3] += input[id2 + 2*size];

Mt_M[1][0] += input[id2 + size] * input[id2 + 2*size];
Mt_M[1][1] += input[id2 + size] * input[id2 + size];
Mt_M[1][2] += input[id2 + size] * input[id2];
Mt_M[1][3] += input[id2 + size];

Mt_M[2][0] += input[id2] * input[id2 + 2*size];
Mt_M[2][1] += input[id2] * input[id2 + size];
Mt_M[2][2] += input[id2] * input[id2];
Mt_M[2][3] += input[id2];

Mt_M[3][0] += input[id2 + 2*size];
Mt_M[3][1] += input[id2 + size];
Mt_M[3][2] += input[id2];
Mt_M[3][3] += 1;

Mt_S[0][0] += input[id2 + 2*size] * output[id2 + 2*size];
Mt_S[0][1] += input[id2 + size] * output[id2 + 2*size];
Mt_S[0][2] += input[id2] * output[id2 + 2*size];
Mt_S[0][3] += output[id2 + 2*size];

Mt_S[1][0] += input[id2 + 2*size] * output[id2 + size];
Mt_S[1][1] += input[id2 + size] * output[id2 + size];
Mt_S[1][2] += input[id2] * output[id2 + size];
Mt_S[1][3] += output[id2 + size];

Mt_S[2][0] += input[id2 + 2*size] * output[id2];
Mt_S[2][1] += input[id2 + size] * output[id2];
Mt_S[2][2] += input[id2] * output[id2];
Mt_S[2][3] += output[id2];
}
}
}

bool success = InverseMat4x4(Mt_M, invMt_M);

for (int i = 0; i < 3; i++) {
for (int j = 0; j < 4; j++) {
for (int k = 0; k < 4; k++) {
A[i][j] += invMt_M[j][k] * Mt_S[i][k];
}
}
}

for (int i = 0; i < 3; i++) {
for (int j = 0; j < 4; j++) {
int affine_id = i * 4 + j;
affine_model[12 * id + affine_id] = A[i][j];
}
}



}
return ;
}
	.text
	.file	"best_local_affine_kernel.hip"
	.globl	_Z39__device_stub__best_local_affine_kernelPfS_S_iifi # -- Begin function _Z39__device_stub__best_local_affine_kernelPfS_S_iifi
	.type	_Z39__device_stub__best_local_affine_kernelPfS_S_iifi,@function
_Z39__device_stub__best_local_affine_kernelPfS_S_iifi: # @_Z39__device_stub__best_local_affine_kernelPfS_S_iifi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movss	%xmm0, (%r8)
	leaq	8(%rsp), %r10
	movl	%r9d, (%r10)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	movq	%r10, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z24best_local_affine_kernelPfS_S_iifi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z39__device_stub__best_local_affine_kernelPfS_S_iifi, .Lfunc_end0-_Z39__device_stub__best_local_affine_kernelPfS_S_iifi
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z24best_local_affine_kernelPfS_S_iifi, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z24best_local_affine_kernelPfS_S_iifi,@object # @_Z24best_local_affine_kernelPfS_S_iifi
	.section	.rodata,"a",@progbits
	.globl	_Z24best_local_affine_kernelPfS_S_iifi
	.p2align	3, 0x0
_Z24best_local_affine_kernelPfS_S_iifi:
	.quad	_Z39__device_stub__best_local_affine_kernelPfS_S_iifi
	.size	_Z24best_local_affine_kernelPfS_S_iifi, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z24best_local_affine_kernelPfS_S_iifi"
	.size	.L__unnamed_1, 39

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z39__device_stub__best_local_affine_kernelPfS_S_iifi
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z24best_local_affine_kernelPfS_S_iifi
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z24best_local_affine_kernelPfS_S_iifi ; -- Begin function _Z24best_local_affine_kernelPfS_S_iifi
	.globl	_Z24best_local_affine_kernelPfS_S_iifi
	.p2align	8
	.type	_Z24best_local_affine_kernelPfS_S_iifi,@function
_Z24best_local_affine_kernelPfS_S_iifi: ; @_Z24best_local_affine_kernelPfS_S_iifi
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x34
	s_load_b64 s[8:9], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_mul_i32 s11, s9, s8
	s_mul_i32 s10, s15, s2
	s_mov_b32 s2, exec_lo
	v_add_nc_u32_e32 v59, s10, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s11, v59
	s_cbranch_execz .LBB0_38
; %bb.1:
	s_mov_b32 s4, 0
	v_mov_b32_e32 v1, 0xd2f1a9fc
	s_mov_b32 s5, s4
	s_mov_b32 s6, s4
	s_mov_b32 s7, s4
	v_dual_mov_b32 v3, s4 :: v_dual_mov_b32 v4, s5
	v_dual_mov_b32 v5, s6 :: v_dual_mov_b32 v6, s7
	v_mov_b32_e32 v2, 0x3f50624d
	s_mov_b32 s2, 0
	s_mov_b32 s3, 0
	s_clause 0x1b
	scratch_store_b128 off, v[3:6], off offset:128
	scratch_store_b128 off, v[3:6], off offset:112
	scratch_store_b128 off, v[3:6], off offset:96
	scratch_store_b128 off, v[3:6], off offset:80
	scratch_store_b128 off, v[3:6], off offset:64
	scratch_store_b128 off, v[3:6], off offset:48
	scratch_store_b128 off, v[3:6], off offset:32
	scratch_store_b128 off, v[3:6], off offset:16
	scratch_store_b128 off, v[3:6], off offset:256
	scratch_store_b128 off, v[3:6], off offset:240
	scratch_store_b128 off, v[3:6], off offset:224
	scratch_store_b128 off, v[3:6], off offset:208
	scratch_store_b128 off, v[3:6], off offset:192
	scratch_store_b128 off, v[3:6], off offset:176
	scratch_store_b128 off, v[3:6], off offset:160
	scratch_store_b128 off, v[3:6], off offset:144
	scratch_store_b128 off, v[3:6], off offset:352
	scratch_store_b128 off, v[3:6], off offset:336
	scratch_store_b128 off, v[3:6], off offset:320
	scratch_store_b128 off, v[3:6], off offset:304
	scratch_store_b128 off, v[3:6], off offset:288
	scratch_store_b128 off, v[3:6], off offset:272
	scratch_store_b128 off, v[3:6], off offset:448
	scratch_store_b128 off, v[3:6], off offset:432
	scratch_store_b128 off, v[3:6], off offset:416
	scratch_store_b128 off, v[3:6], off offset:400
	scratch_store_b128 off, v[3:6], off offset:384
	scratch_store_b128 off, v[3:6], off offset:368
.LBB0_2:                                ; %.preheader213
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_3 Depth 2
	s_cmp_lg_u32 s3, 3
	s_mov_b32 s7, s2
	s_cselect_b32 s6, -1, 0
	s_mov_b32 s12, s4
.LBB0_3:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_mov_b32 s5, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v3, s4 :: v_dual_mov_b32 v4, s5
	s_add_i32 s13, s7, 16
	s_and_not1_b32 vcc_lo, exec_lo, s6
	s_add_i32 s14, s7, 0x90
	scratch_store_b64 off, v[3:4], s13
	scratch_store_b64 off, v[3:4], s14
	s_cbranch_vccnz .LBB0_6
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=2
	v_dual_mov_b32 v3, s4 :: v_dual_mov_b32 v4, s5
	s_add_i32 s5, s7, 0x110
	s_add_i32 s13, s7, 0x170
	s_cmp_lg_u32 s3, s12
	scratch_store_b64 off, v[3:4], s5
	scratch_store_b64 off, v[3:4], s13
	s_cbranch_scc1 .LBB0_6
; %bb.5:                                ;   in Loop: Header=BB0_3 Depth=2
	v_add_nc_u32_e64 v3, s7, 16
	scratch_store_b64 v3, v[1:2], off
.LBB0_6:                                ;   in Loop: Header=BB0_3 Depth=2
	s_add_i32 s12, s12, 1
	s_add_i32 s7, s7, 8
	s_cmp_eq_u32 s12, 4
	s_cbranch_scc0 .LBB0_3
; %bb.7:                                ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s3, s3, 1
	s_add_i32 s2, s2, 32
	s_cmp_eq_u32 s3, 4
	s_cbranch_scc0 .LBB0_2
; %bb.8:
	s_clause 0x1
	scratch_load_b64 v[51:52], off, off offset:16
	scratch_load_b64 v[49:50], off, off offset:272
	s_clause 0x2
	s_load_b32 s12, s[0:1], 0x24
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s12, 0
	s_cbranch_scc1 .LBB0_19
; %bb.9:                                ; %.preheader212.lr.ph
	s_clause 0xd
	scratch_load_b128 v[1:4], off, off offset:24
	scratch_load_b128 v[5:8], off, off offset:40
	scratch_load_b128 v[9:12], off, off offset:56
	scratch_load_b128 v[13:16], off, off offset:72
	scratch_load_b128 v[17:20], off, off offset:88
	scratch_load_b128 v[21:24], off, off offset:104
	scratch_load_b128 v[25:28], off, off offset:120
	scratch_load_b64 v[53:54], off, off offset:136
	scratch_load_b128 v[29:32], off, off offset:280
	scratch_load_b128 v[33:36], off, off offset:296
	scratch_load_b128 v[37:40], off, off offset:312
	scratch_load_b128 v[41:44], off, off offset:328
	scratch_load_b128 v[45:48], off, off offset:344
	scratch_load_b64 v[55:56], off, off offset:360
	s_ashr_i32 s0, s9, 31
	v_ashrrev_i32_e32 v60, 31, v59
	s_add_i32 s1, s9, s0
	s_sub_i32 s15, 0, s12
	s_xor_b32 s1, s1, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cvt_f32_u32_e32 v57, s1
	s_sub_i32 s13, 0, s1
	v_add_nc_u32_e32 v61, v59, v60
	v_rcp_iflag_f32_e32 v57, v57
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v61, v61, v60
	v_xor_b32_e32 v60, s0, v60
	s_not_b32 s0, s9
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v57, 0x4f7ffffe, v57
	v_cvt_u32_f32_e32 v57, v57
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v58, s13, v57
	s_lshl_b32 s13, s11, 1
	v_mul_hi_u32 v58, v57, v58
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v57, v57, v58
	v_mul_hi_u32 v57, v61, v57
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v58, v57, s1
	v_sub_nc_u32_e32 v58, v61, v58
	v_add_nc_u32_e32 v61, 1, v57
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v62, s1, v58
	v_cmp_le_u32_e32 vcc_lo, s1, v58
	v_dual_cndmask_b32 v58, v58, v62 :: v_dual_cndmask_b32 v57, v57, v61
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s1, v58
	v_add_nc_u32_e32 v61, 1, v57
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v57, v57, v61, vcc_lo
	v_xor_b32_e32 v57, v57, v60
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v60, v57, v60
	v_mul_lo_u32 v57, v60, s9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v61, v59, v57
	v_mad_u64_u32 v[57:58], null, s12, s0, v[59:60]
	s_lshl_b32 s0, s12, 1
	v_subrev_nc_u32_e32 v61, s12, v61
	s_or_b32 s14, s0, 1
.LBB0_10:                               ; %.preheader212
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_11 Depth 2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v58, v57 :: v_dual_add_nc_u32 v59, s15, v60
	v_mov_b32_e32 v62, v61
	s_mov_b32 s16, s14
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_lt_i32_e32 vcc_lo, -1, v59
	v_cmp_gt_i32_e64 s0, s8, v59
.LBB0_11:                               ;   Parent Loop BB0_10 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_mov_b32 s17, exec_lo
	v_cmpx_lt_i32_e32 -1, v62
	s_cbranch_execz .LBB0_15
; %bb.12:                               ;   in Loop: Header=BB0_11 Depth=2
	v_cmp_gt_i32_e64 s1, s9, v62
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s1, s1, vcc_lo
	s_and_b32 s1, s1, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s18, s1
	s_cbranch_execz .LBB0_14
; %bb.13:                               ;   in Loop: Header=BB0_11 Depth=2
	v_add_nc_u32_e32 v63, s13, v58
	s_waitcnt vmcnt(6)
	v_add_f64 v[53:54], v[53:54], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v64, 31, v63
	v_lshlrev_b64 v[63:64], 2, v[63:64]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v65, s1, s6, v63
	v_add_co_ci_u32_e64 v66, s1, s7, v64, s1
	global_load_b32 v77, v[65:66], off
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v59, v77, v77
	v_cvt_f64_f32_e32 v[73:74], v77
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_f32_e32 v[65:66], v59
	v_add_f64 v[5:6], v[5:6], v[73:74]
	v_add_f64 v[23:24], v[23:24], v[73:74]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[51:52], v[51:52], v[65:66]
	v_add_nc_u32_e32 v65, s11, v58
	v_ashrrev_i32_e32 v66, 31, v65
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[65:66], 2, v[65:66]
	v_add_co_u32 v67, s1, s6, v65
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v68, s1, s7, v66, s1
	global_load_b32 v78, v[67:68], off
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v59, v77, v78
	v_cvt_f64_f32_e32 v[75:76], v78
	v_cvt_f64_f32_e32 v[67:68], v59
	v_ashrrev_i32_e32 v59, 31, v58
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[69:70], 2, v[58:59]
	v_add_co_u32 v71, s1, s6, v69
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v72, s1, s7, v70, s1
	v_add_co_u32 v63, s1, s4, v63
	v_add_co_ci_u32_e64 v64, s1, s5, v64, s1
	global_load_b32 v59, v[71:72], off
	v_add_f64 v[13:14], v[13:14], v[75:76]
	v_add_f64 v[25:26], v[25:26], v[75:76]
	v_add_f64 v[1:2], v[1:2], v[67:68]
	v_add_f64 v[7:8], v[7:8], v[67:68]
	v_mul_f32_e32 v67, v78, v78
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[67:68], v67
	v_add_f64 v[9:10], v[9:10], v[67:68]
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v67, v78, v59
	v_mul_f32_e32 v71, v77, v59
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_f32_e32 v[67:68], v67
	v_cvt_f64_f32_e32 v[71:72], v71
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_f64 v[11:12], v[11:12], v[67:68]
	v_add_f64 v[17:18], v[17:18], v[67:68]
	v_mul_f32_e32 v67, v59, v59
	v_add_f64 v[3:4], v[3:4], v[71:72]
	v_add_f64 v[15:16], v[15:16], v[71:72]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[67:68], v67
	v_add_f64 v[19:20], v[19:20], v[67:68]
	v_cvt_f64_f32_e32 v[67:68], v59
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_f64 v[21:22], v[21:22], v[67:68]
	v_add_f64 v[27:28], v[27:28], v[67:68]
	global_load_b32 v67, v[63:64], off
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v63, v77, v67
	v_cvt_f64_f32_e32 v[63:64], v63
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[49:50], v[49:50], v[63:64]
	v_mul_f32_e32 v63, v78, v67
	v_cvt_f64_f32_e32 v[63:64], v63
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[29:30], v[29:30], v[63:64]
	v_mul_f32_e32 v63, v59, v67
	v_cvt_f64_f32_e32 v[63:64], v63
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[31:32], v[31:32], v[63:64]
	v_cvt_f64_f32_e32 v[63:64], v67
	v_add_f64 v[33:34], v[33:34], v[63:64]
	v_add_co_u32 v63, s1, s4, v65
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v64, s1, s5, v66, s1
	global_load_b32 v65, v[63:64], off
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v63, v77, v65
	v_cvt_f64_f32_e32 v[63:64], v63
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[35:36], v[35:36], v[63:64]
	v_mul_f32_e32 v63, v78, v65
	v_cvt_f64_f32_e32 v[63:64], v63
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[37:38], v[37:38], v[63:64]
	v_mul_f32_e32 v63, v59, v65
	v_cvt_f64_f32_e32 v[63:64], v63
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[39:40], v[39:40], v[63:64]
	v_cvt_f64_f32_e32 v[63:64], v65
	v_add_f64 v[41:42], v[41:42], v[63:64]
	v_add_co_u32 v63, s1, s4, v69
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e64 v64, s1, s5, v70, s1
	global_load_b32 v65, v[63:64], off
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v63, v77, v65
	v_mul_f32_e32 v59, v59, v65
	v_cvt_f64_f32_e32 v[63:64], v63
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[43:44], v[43:44], v[63:64]
	v_mul_f32_e32 v63, v78, v65
	v_cvt_f64_f32_e32 v[63:64], v63
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[45:46], v[45:46], v[63:64]
	v_cvt_f64_f32_e32 v[63:64], v59
	v_add_f64 v[47:48], v[47:48], v[63:64]
	v_cvt_f64_f32_e32 v[63:64], v65
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[55:56], v[55:56], v[63:64]
.LBB0_14:                               ; %Flow655
                                        ;   in Loop: Header=BB0_11 Depth=2
	s_or_b32 exec_lo, exec_lo, s18
.LBB0_15:                               ;   in Loop: Header=BB0_11 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s17
	v_add_nc_u32_e32 v62, 1, v62
	v_add_nc_u32_e32 v58, 1, v58
	s_add_i32 s16, s16, -1
	s_cmp_eq_u32 s16, 0
	s_cbranch_scc0 .LBB0_11
; %bb.16:                               ; %._crit_edge
                                        ;   in Loop: Header=BB0_10 Depth=1
	v_add_nc_u32_e32 v57, s9, v57
	s_add_i32 s0, s15, 1
	s_cmp_eq_u32 s15, s12
	s_cbranch_scc1 .LBB0_18
; %bb.17:                               ;   in Loop: Header=BB0_10 Depth=1
	s_mov_b32 s15, s0
	s_branch .LBB0_10
.LBB0_18:                               ; %..preheader25.i.preheader_crit_edge
	s_waitcnt vmcnt(13)
	scratch_store_b128 off, v[1:4], off offset:24
	s_waitcnt vmcnt(12)
	scratch_store_b128 off, v[5:8], off offset:40
	s_waitcnt vmcnt(11)
	scratch_store_b128 off, v[9:12], off offset:56
	s_waitcnt vmcnt(10)
	scratch_store_b128 off, v[13:16], off offset:72
	s_waitcnt vmcnt(9)
	scratch_store_b128 off, v[17:20], off offset:88
	s_waitcnt vmcnt(8)
	scratch_store_b128 off, v[21:24], off offset:104
	s_waitcnt vmcnt(7)
	scratch_store_b128 off, v[25:28], off offset:120
	s_waitcnt vmcnt(6)
	scratch_store_b64 off, v[53:54], off offset:136
	s_waitcnt vmcnt(5)
	scratch_store_b128 off, v[29:32], off offset:280
	s_waitcnt vmcnt(4)
	scratch_store_b128 off, v[33:36], off offset:296
	s_waitcnt vmcnt(3)
	scratch_store_b128 off, v[37:40], off offset:312
	s_waitcnt vmcnt(2)
	scratch_store_b128 off, v[41:44], off offset:328
	s_waitcnt vmcnt(1)
	scratch_store_b128 off, v[45:48], off offset:344
	s_waitcnt vmcnt(0)
	scratch_store_b64 off, v[55:56], off offset:360
.LBB0_19:                               ; %.preheader25.i.preheader
	v_mov_b32_e32 v33, 16
	s_mov_b32 s0, 0
	s_mov_b32 s1, 0
	s_waitcnt vmcnt(1)
	scratch_store_b64 off, v[51:52], off offset:16
	s_waitcnt vmcnt(0)
	scratch_store_b64 off, v[49:50], off offset:272
                                        ; implicit-def: $vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32
.LBB0_20:                               ; %.preheader25.i
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_21 Depth 2
	v_mov_b32_e32 v34, v33
	s_mov_b32 s4, 0
.LBB0_21:                               ;   Parent Loop BB0_20 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	scratch_load_b64 v[35:36], v34, off
	s_add_i32 s5, s0, s4
	v_add_nc_u32_e32 v34, 8, v34
	s_lshl_b32 s5, s5, 1
	s_add_i32 s4, s4, 1
	s_mov_b32 m0, s5
	s_cmp_eq_u32 s4, 4
	s_waitcnt vmcnt(0)
	v_movreld_b32_e32 v1, v35
	v_movreld_b32_e32 v2, v36
	s_cbranch_scc0 .LBB0_21
; %bb.22:                               ;   in Loop: Header=BB0_20 Depth=1
	v_add_nc_u32_e32 v33, 32, v33
	s_add_i32 s1, s1, 1
	s_add_i32 s0, s0, 4
	s_cmp_eq_u32 s1, 4
	s_cbranch_scc0 .LBB0_20
; %bb.23:
	v_mul_f64 v[33:34], v[11:12], v[23:24]
	v_mul_f64 v[35:36], v[21:22], v[9:10]
	v_mul_f64 v[37:38], v[11:12], v[21:22]
	v_mul_f64 v[39:40], v[23:24], v[9:10]
	v_mul_f64 v[43:44], v[19:20], v[13:14]
	v_mul_f64 v[45:46], v[19:20], v[9:10]
	v_mul_f64 v[47:48], v[19:20], v[15:16]
	v_mul_f64 v[49:50], v[15:16], v[17:18]
	v_mul_f64 v[51:52], v[11:12], v[17:18]
	v_mul_f64 v[53:54], v[11:12], v[25:26]
	s_mov_b32 s0, 0xe826d695
	s_mov_b32 s1, 0x3e112e0b
	v_mul_f64 v[33:34], v[29:30], v[33:34]
	v_mul_f64 v[41:42], v[31:32], v[35:36]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[33:34], v[31:32], v[37:38], -v[33:34]
	v_mul_f64 v[37:38], v[13:14], v[17:18]
	v_fma_f64 v[41:42], v[29:30], v[39:40], -v[41:42]
	v_mul_f64 v[39:40], v[27:28], v[39:40]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f64 v[33:34], -v[31:32], v[43:44], v[33:34]
	v_mul_f64 v[43:44], v[13:14], v[27:28]
	v_fma_f64 v[41:42], v[31:32], v[37:38], v[41:42]
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f64 v[39:40], v[31:32], v[45:46], -v[39:40]
	v_mul_f64 v[45:46], v[29:30], v[45:46]
	v_fma_f64 v[33:34], v[29:30], v[47:48], v[33:34]
	v_mul_f64 v[47:48], v[13:14], v[25:26]
	v_fma_f64 v[41:42], -v[29:30], v[49:50], v[41:42]
	v_fma_f64 v[39:40], -v[31:32], v[51:52], v[39:40]
	v_fma_f64 v[35:36], v[27:28], v[35:36], -v[45:46]
	v_mul_f64 v[45:46], v[15:16], v[25:26]
	v_fma_f64 v[33:34], v[23:24], v[43:44], v[33:34]
	v_mul_f64 v[43:44], v[15:16], v[27:28]
	v_fma_f64 v[41:42], -v[23:24], v[47:48], v[41:42]
	v_fma_f64 v[39:40], v[27:28], v[49:50], v[39:40]
	v_fma_f64 v[35:36], v[29:30], v[51:52], v[35:36]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[33:34], -v[21:22], v[43:44], v[33:34]
	v_fma_f64 v[41:42], v[21:22], v[45:46], v[41:42]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[39:40], v[23:24], v[53:54], v[39:40]
	v_fma_f64 v[35:36], -v[27:28], v[37:38], v[35:36]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[37:38], v[1:2], v[33:34]
	v_fma_f64 v[49:50], -v[19:20], v[45:46], v[39:40]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[35:36], -v[21:22], v[53:54], v[35:36]
	v_fma_f64 v[37:38], v[3:4], v[41:42], v[37:38]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[57:58], v[19:20], v[47:48], v[35:36]
	v_fma_f64 v[35:36], v[5:6], v[49:50], v[37:38]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[65:66], v[7:8], v[57:58], v[35:36]
	v_cmp_nlt_f64_e64 s1, |v[65:66]|, s[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_28
; %bb.24:
	v_div_scale_f64 v[35:36], null, v[65:66], v[65:66], 1.0
	v_mul_f64 v[39:40], v[21:22], v[3:4]
	v_mul_f64 v[43:44], v[15:16], v[3:4]
	v_mul_f64 v[45:46], v[23:24], v[3:4]
	v_mul_f64 v[47:48], v[13:14], v[3:4]
	v_mul_f64 v[55:56], v[19:20], v[5:6]
	v_mul_f64 v[59:60], v[11:12], v[5:6]
	v_mul_f64 v[63:64], v[19:20], v[7:8]
	v_mul_f64 v[61:62], v[27:28], v[5:6]
	v_div_scale_f64 v[67:68], vcc_lo, 1.0, v[65:66], 1.0
	v_mul_f64 v[71:72], v[19:20], v[1:2]
	s_mov_b32 s1, 0
	s_mov_b32 s4, 0
	v_rcp_f64_e32 v[37:38], v[35:36]
	v_mul_f64 v[39:40], v[31:32], v[39:40]
	v_mul_f64 v[53:54], v[29:30], v[43:44]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[39:40], v[29:30], v[45:46], -v[39:40]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[51:52], -v[35:36], v[37:38], 1.0
	v_fma_f64 v[45:46], v[31:32], v[47:48], -v[53:54]
	v_mul_f64 v[47:48], v[23:24], v[47:48]
	v_fma_f64 v[39:40], v[31:32], v[55:56], v[39:40]
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f64 v[37:38], v[37:38], v[51:52], v[37:38]
	v_mul_f64 v[51:52], v[11:12], v[7:8]
	v_fma_f64 v[45:46], -v[31:32], v[59:60], v[45:46]
	v_fma_f64 v[43:44], v[21:22], v[43:44], -v[47:48]
	v_mul_f64 v[47:48], v[15:16], v[1:2]
	v_fma_f64 v[53:54], -v[35:36], v[37:38], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[43:44], v[23:24], v[59:60], v[43:44]
	v_mul_f64 v[73:74], v[19:20], v[47:48]
	v_mul_f64 v[75:76], v[21:22], v[47:48]
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f64 v[53:54], v[37:38], v[53:54], v[37:38]
	v_fma_f64 v[37:38], -v[29:30], v[63:64], v[39:40]
	v_fma_f64 v[39:40], v[29:30], v[51:52], v[45:46]
	v_mul_f64 v[45:46], v[27:28], v[7:8]
	v_fma_f64 v[43:44], -v[21:22], v[51:52], v[43:44]
	v_mul_f64 v[69:70], v[67:68], v[53:54]
	v_fma_f64 v[37:38], -v[23:24], v[61:62], v[37:38]
	v_fma_f64 v[39:40], v[15:16], v[61:62], v[39:40]
	v_mul_f64 v[61:62], v[23:24], v[1:2]
	v_fma_f64 v[55:56], -v[15:16], v[55:56], v[43:44]
	v_fma_f64 v[67:68], -v[35:36], v[69:70], v[67:68]
	v_fma_f64 v[35:36], v[21:22], v[45:46], v[37:38]
	v_fma_f64 v[37:38], -v[13:14], v[45:46], v[39:40]
	v_mul_f64 v[39:40], v[21:22], v[1:2]
	v_mul_f64 v[45:46], v[29:30], v[61:62]
	v_div_fmas_f64 v[67:68], v[67:68], v[53:54], v[69:70]
	v_mul_f64 v[53:54], v[31:32], v[71:72]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f64 v[69:70], v[27:28], v[39:40]
	v_fma_f64 v[39:40], v[31:32], v[39:40], -v[45:46]
	v_mul_f64 v[45:46], v[13:14], v[1:2]
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f64 v[53:54], v[27:28], v[61:62], -v[53:54]
	v_mul_f64 v[61:62], v[11:12], -v[1:2]
	v_fma_f64 v[69:70], v[29:30], v[71:72], -v[69:70]
	v_mul_f64 v[1:2], v[11:12], v[1:2]
	v_mul_f64 v[71:72], v[27:28], v[45:46]
	v_fma_f64 v[75:76], v[23:24], v[45:46], -v[75:76]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_fma_f64 v[71:72], v[29:30], v[61:62], v[71:72]
	v_fma_f64 v[61:62], v[23:24], v[61:62], v[73:74]
	v_mul_f64 v[73:74], v[31:32], v[45:46]
	v_mul_f64 v[45:46], v[19:20], v[45:46]
	v_fma_f64 v[73:74], v[29:30], v[47:48], -v[73:74]
	v_mul_f64 v[47:48], v[27:28], v[47:48]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[47:48], v[31:32], v[1:2], -v[47:48]
	v_fma_f64 v[1:2], v[21:22], v[1:2], -v[45:46]
	v_mul_f64 v[45:46], v[9:10], v[3:4]
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[47:48], -v[31:32], v[45:46], v[47:48]
	v_fma_f64 v[59:60], v[29:30], v[45:46], v[71:72]
	v_fma_f64 v[61:62], v[23:24], v[45:46], v[61:62]
	v_fma_f64 v[1:2], -v[21:22], v[45:46], v[1:2]
	v_mul_f64 v[45:46], v[9:10], v[5:6]
	v_mul_f64 v[9:10], v[9:10], v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f64 v[51:52], v[31:32], v[45:46], v[73:74]
	v_fma_f64 v[71:72], -v[23:24], v[45:46], v[75:76]
	v_fma_f64 v[1:2], v[19:20], v[45:46], v[1:2]
	v_fma_f64 v[47:48], v[27:28], v[9:10], v[47:48]
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f64 v[73:74], -v[29:30], v[9:10], v[51:52]
	v_fma_f64 v[51:52], -v[27:28], v[45:46], v[59:60]
	v_mul_f64 v[45:46], v[17:18], v[3:4]
	v_mul_f64 v[3:4], v[25:26], v[3:4]
	v_fma_f64 v[71:72], v[21:22], v[9:10], v[71:72]
	v_fma_f64 v[9:10], -v[19:20], v[9:10], v[61:62]
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f64 v[53:54], v[31:32], v[45:46], v[53:54]
	v_fma_f64 v[59:60], -v[29:30], v[45:46], v[69:70]
	v_mul_f64 v[69:70], v[17:18], v[7:8]
	v_mul_f64 v[17:18], v[17:18], v[5:6]
	v_mul_f64 v[5:6], v[25:26], v[5:6]
	v_mul_f64 v[7:8], v[25:26], v[7:8]
	v_fma_f64 v[47:48], v[15:16], v[3:4], v[47:48]
	v_fma_f64 v[9:10], -v[15:16], v[45:46], v[9:10]
	v_fma_f64 v[1:2], v[13:14], v[45:46], v[1:2]
	v_fma_f64 v[53:54], -v[27:28], v[69:70], v[53:54]
	v_fma_f64 v[27:28], v[27:28], v[17:18], v[59:60]
	v_fma_f64 v[31:32], -v[31:32], v[17:18], v[39:40]
	v_fma_f64 v[39:40], v[13:14], v[63:64], v[55:56]
	v_fma_f64 v[55:56], v[11:12], v[69:70], v[9:10]
	v_fma_f64 v[63:64], -v[11:12], v[17:18], v[1:2]
	v_div_fixup_f64 v[1:2], v[67:68], v[65:66], 1.0
	v_fma_f64 v[53:54], -v[23:24], v[3:4], v[53:54]
	v_fma_f64 v[27:28], v[21:22], v[3:4], v[27:28]
	v_fma_f64 v[29:30], v[29:30], v[69:70], v[31:32]
	v_fma_f64 v[3:4], -v[13:14], v[3:4], v[51:52]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[51:52], v[19:20], v[7:8], v[53:54]
	v_fma_f64 v[59:60], -v[19:20], v[5:6], v[27:28]
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f64 v[23:24], v[23:24], v[5:6], v[29:30]
	v_fma_f64 v[19:20], -v[15:16], v[5:6], v[73:74]
	v_fma_f64 v[15:16], v[15:16], v[17:18], v[71:72]
	v_fma_f64 v[53:54], -v[11:12], v[7:8], v[47:48]
	v_fma_f64 v[61:62], v[11:12], v[5:6], v[3:4]
	v_mov_b32_e32 v3, 0x90
	v_fma_f64 v[43:44], -v[21:22], v[7:8], v[23:24]
	v_fma_f64 v[45:46], v[13:14], v[7:8], v[19:20]
	v_fma_f64 v[47:48], -v[13:14], v[69:70], v[15:16]
.LBB0_25:                               ; %.preheader.i
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_26 Depth 2
	s_delay_alu instid0(VALU_DEP_4)
	v_mov_b32_e32 v4, v3
	s_mov_b32 s5, 0
.LBB0_26:                               ;   Parent Loop BB0_25 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_i32 s6, s1, s5
	s_add_i32 s5, s5, 1
	s_lshl_b32 s6, s6, 1
	s_cmp_eq_u32 s5, 4
	s_mov_b32 m0, s6
	v_movrels_b32_e32 v6, v34
	v_movrels_b32_e32 v5, v33
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f64 v[5:6], v[1:2], v[5:6]
	scratch_store_b64 v4, v[5:6], off
	v_add_nc_u32_e32 v4, 8, v4
	s_cbranch_scc0 .LBB0_26
; %bb.27:                               ;   in Loop: Header=BB0_25 Depth=1
	v_add_nc_u32_e32 v3, 32, v3
	s_add_i32 s4, s4, 1
	s_add_i32 s1, s1, 4
	s_cmp_eq_u32 s4, 4
	s_cbranch_scc0 .LBB0_25
.LBB0_28:                               ; %Flow654
	s_or_b32 exec_lo, exec_lo, s0
	v_mov_b32_e32 v3, 0x110
	s_mov_b32 s0, 0
.LBB0_29:                               ; %.preheader211
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_30 Depth 2
                                        ;       Child Loop BB0_31 Depth 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b32 s1, s0, 5
	v_mov_b32_e32 v4, 0x90
	v_add_nc_u32_e64 v5, 0x170, s1
	s_mov_b32 s1, 0
.LBB0_30:                               ; %.preheader210
                                        ;   Parent Loop BB0_29 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_31 Depth 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b32 s4, s1, 3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v6, s4, v5
	s_mov_b32 s4, 0
	scratch_load_b64 v[1:2], v6, off
.LBB0_31:                               ;   Parent Loop BB0_29 Depth=1
                                        ;     Parent Loop BB0_30 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_add_nc_u32_e32 v7, s4, v4
	v_add_nc_u32_e32 v9, s4, v3
	s_add_i32 s4, s4, 8
	scratch_load_b64 v[7:8], v7, off
	scratch_load_b64 v[9:10], v9, off
	s_cmp_eq_u32 s4, 32
	s_waitcnt vmcnt(0)
	v_fma_f64 v[1:2], v[7:8], v[9:10], v[1:2]
	s_cbranch_scc0 .LBB0_31
; %bb.32:                               ;   in Loop: Header=BB0_30 Depth=2
	v_add_nc_u32_e32 v4, 32, v4
	s_add_i32 s1, s1, 1
	scratch_store_b64 v6, v[1:2], off
	s_cmp_eq_u32 s1, 4
	s_cbranch_scc0 .LBB0_30
; %bb.33:                               ;   in Loop: Header=BB0_29 Depth=1
	v_add_nc_u32_e32 v3, 32, v3
	s_add_i32 s0, s0, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s0, 3
	s_cbranch_scc0 .LBB0_29
; %bb.34:                               ; %.preheader209
	s_mul_i32 s10, s10, 12
	v_mov_b32_e32 v1, 0x170
	v_mad_u32_u24 v0, v0, 12, s10
	s_mov_b32 s0, 0
.LBB0_35:                               ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_36 Depth 2
	s_delay_alu instid0(VALU_DEP_2)
	v_mov_b32_e32 v2, v1
	s_mov_b32 s1, 0
.LBB0_36:                               ;   Parent Loop BB0_35 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	scratch_load_b64 v[3:4], v2, off
	v_add_nc_u32_e32 v2, 8, v2
	s_waitcnt vmcnt(0)
	v_cvt_f32_f64_e32 v5, v[3:4]
	v_add_nc_u32_e32 v3, s1, v0
	s_add_i32 s1, s1, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s1, 4
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_add_co_u32 v3, vcc_lo, s2, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
	global_store_b32 v[3:4], v5, off
	s_cbranch_scc0 .LBB0_36
; %bb.37:                               ;   in Loop: Header=BB0_35 Depth=1
	v_add_nc_u32_e32 v1, 32, v1
	v_add_nc_u32_e32 v0, 4, v0
	s_add_i32 s0, s0, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s0, 3
	s_cbranch_scc0 .LBB0_35
.LBB0_38:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z24best_local_affine_kernelPfS_S_iifi
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 464
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 1
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 79
		.amdhsa_next_free_sgpr 19
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z24best_local_affine_kernelPfS_S_iifi, .Lfunc_end0-_Z24best_local_affine_kernelPfS_S_iifi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3768
; NumSgprs: 21
; NumVgprs: 79
; ScratchSize: 464
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 9
; NumSGPRsForWavesPerEU: 21
; NumVGPRsForWavesPerEU: 79
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 1
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z24best_local_affine_kernelPfS_S_iifi
    .private_segment_fixed_size: 464
    .sgpr_count:     21
    .sgpr_spill_count: 0
    .symbol:         _Z24best_local_affine_kernelPfS_S_iifi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     79
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
