// Corresponding header file: /include/filter_ops.h
#include <cuda_runtime.h>
#include <string>
#include <math.h>

/*
 * Contains kernels and functions for adding photo filters to the imput image.
 * apply_filter() function is called to apply the filter with image on GPU and
 * filter name as parameters. A pointer to the new image in RAM is returned to 
 * the caller. 
 */
const int BLOCK_WIDTH = 16;

// Kernel : Greyscale
__global__ void greyscale(const uchar4* const d_color, uchar4* d_grey, size_t numRows, size_t numCols)
{
  int thread_x = blockDim.x * blockIdx.x + threadIdx.x;
  int thread_y = blockDim.y * blockIdx.y + threadIdx.y;

  int myId = thread_y * numCols + thread_x;
  if(thread_x >= numCols || thread_y >= numRows) 
    return;
  
  unsigned char Y = 0.299f * d_color[myId].x + 0.587 * d_color[myId].y + 0.114 * d_color[myId].z;
  d_grey[myId] = make_uchar4(Y, Y, Y, 255);
}

__device__ double get_distance_between(double x1, double y1,
                                       double x2, double y2){
  return sqrt(pow(x1-x2, 2) + pow(y1-y2, 2));
}

// Kernel : Vignette
__global__ void vignette(const uchar4* const d_in, uchar4* d_vignette,
                         const size_t numRows, const size_t numCols)
{
  int thread_x = blockDim.x * blockIdx.x + threadIdx.x;
  int thread_y = blockDim.y * blockIdx.y + threadIdx.y;
  if(thread_x >= numCols || thread_y >= numRows)
    return;

  int myId = thread_y * numCols + thread_x; 
  
  // Generating mask
  const double max_image_radius = 1.0 * sqrt((pow((double)numRows, 2) + pow((double)numCols, 2)) / 4);
  const double power = 0.7;

  double dist_from_center = get_distance_between(numRows/2, numCols/2, thread_x, thread_y) / max_image_radius;  
  dist_from_center *= power;
  dist_from_center = pow(cos(dist_from_center), 4); 

  uchar4 rgba = d_in[myId];
  d_vignette[myId] = make_uchar4(rgba.x * dist_from_center, 
                                 rgba.y * dist_from_center,
                                 rgba.z * dist_from_center,
                                 255);
}

uchar4* apply_filter(uchar4 *d_in, const size_t numRows, const size_t numCols, std::string filtername)
{
  uchar4 *d_out;
  cudaMalloc((void **) &d_out, numRows * numCols * sizeof(uchar4));

  const dim3 block_size(BLOCK_WIDTH, BLOCK_WIDTH, 1);
  const dim3 grid_size(numCols/BLOCK_WIDTH + 1, numRows/BLOCK_WIDTH + 1, 1);

  if(filtername == "greyscale"){
    greyscale<<<grid_size, block_size>>>(d_in, d_out, numRows, numCols);
  }
  else if(filtername == "vignette"){
    vignette<<<grid_size, block_size>>>(d_in, d_out, numRows, numCols);
  }

  uchar4* h_out = new uchar4[numRows * numCols];
  cudaMemcpy(h_out, d_out, numRows * numCols * sizeof(uchar4), cudaMemcpyDeviceToHost);
  cudaFree(d_out);
  return h_out;
}

	.file	"tmpxft_003498bf_00000000-6_filter_ops.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3027:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3027:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z20get_distance_betweendddd
	.type	_Z20get_distance_betweendddd, @function
_Z20get_distance_betweendddd:
.LFB3023:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3023:
	.size	_Z20get_distance_betweendddd, .-_Z20get_distance_betweendddd
	.globl	_Z40__device_stub__Z9greyscalePK6uchar4PS_mmPK6uchar4PS_mm
	.type	_Z40__device_stub__Z9greyscalePK6uchar4PS_mmPK6uchar4PS_mm, @function
_Z40__device_stub__Z9greyscalePK6uchar4PS_mmPK6uchar4PS_mm:
.LFB3049:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z9greyscalePK6uchar4PS_mm(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L4:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3049:
	.size	_Z40__device_stub__Z9greyscalePK6uchar4PS_mmPK6uchar4PS_mm, .-_Z40__device_stub__Z9greyscalePK6uchar4PS_mmPK6uchar4PS_mm
	.globl	_Z9greyscalePK6uchar4PS_mm
	.type	_Z9greyscalePK6uchar4PS_mm, @function
_Z9greyscalePK6uchar4PS_mm:
.LFB3050:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z9greyscalePK6uchar4PS_mmPK6uchar4PS_mm
	.cfi_endproc
.LFE3050:
	.size	_Z9greyscalePK6uchar4PS_mm, .-_Z9greyscalePK6uchar4PS_mm
	.globl	_Z39__device_stub__Z8vignettePK6uchar4PS_mmPK6uchar4PS_mm
	.type	_Z39__device_stub__Z8vignettePK6uchar4PS_mmPK6uchar4PS_mm, @function
_Z39__device_stub__Z8vignettePK6uchar4PS_mmPK6uchar4PS_mm:
.LFB3051:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z8vignettePK6uchar4PS_mm(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L10:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L12
	call	__stack_chk_fail@PLT
.L12:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3051:
	.size	_Z39__device_stub__Z8vignettePK6uchar4PS_mmPK6uchar4PS_mm, .-_Z39__device_stub__Z8vignettePK6uchar4PS_mmPK6uchar4PS_mm
	.globl	_Z8vignettePK6uchar4PS_mm
	.type	_Z8vignettePK6uchar4PS_mm, @function
_Z8vignettePK6uchar4PS_mm:
.LFB3052:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z8vignettePK6uchar4PS_mmPK6uchar4PS_mm
	.cfi_endproc
.LFE3052:
	.size	_Z8vignettePK6uchar4PS_mm, .-_Z8vignettePK6uchar4PS_mm
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z8vignettePK6uchar4PS_mm"
.LC1:
	.string	"_Z9greyscalePK6uchar4PS_mm"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3054:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z8vignettePK6uchar4PS_mm(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z9greyscalePK6uchar4PS_mm(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3054:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.text._ZSteqIcSt11char_traitsIcESaIcEEbRKNSt7__cxx1112basic_stringIT_T0_T1_EEPKS5_,"axG",@progbits,_ZSteqIcSt11char_traitsIcESaIcEEbRKNSt7__cxx1112basic_stringIT_T0_T1_EEPKS5_,comdat
	.weak	_ZSteqIcSt11char_traitsIcESaIcEEbRKNSt7__cxx1112basic_stringIT_T0_T1_EEPKS5_
	.type	_ZSteqIcSt11char_traitsIcESaIcEEbRKNSt7__cxx1112basic_stringIT_T0_T1_EEPKS5_, @function
_ZSteqIcSt11char_traitsIcESaIcEEbRKNSt7__cxx1112basic_stringIT_T0_T1_EEPKS5_:
.LFB3349:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movq	%rdi, %rbx
	subq	$24, %rsp
	.cfi_def_cfa_offset 48
	movq	8(%rdi), %r12
	movq	%rsi, %rdi
	movq	%rsi, 8(%rsp)
	call	strlen@PLT
	movq	8(%rsp), %rsi
	movq	%rax, %rdx
	xorl	%eax, %eax
	cmpq	%rdx, %r12
	jne	.L17
	movb	$1, %al
	testq	%r12, %r12
	je	.L17
	movq	(%rbx), %rdi
	movq	%r12, %rdx
	call	memcmp@PLT
	testl	%eax, %eax
	sete	%al
.L17:
	addq	$24, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3349:
	.size	_ZSteqIcSt11char_traitsIcESaIcEEbRKNSt7__cxx1112basic_stringIT_T0_T1_EEPKS5_, .-_ZSteqIcSt11char_traitsIcESaIcEEbRKNSt7__cxx1112basic_stringIT_T0_T1_EEPKS5_
	.section	.rodata.str1.1
.LC2:
	.string	"greyscale"
.LC3:
	.string	"vignette"
	.text
	.globl	_Z12apply_filterP6uchar4mmNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
	.type	_Z12apply_filterP6uchar4mmNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, @function
_Z12apply_filterP6uchar4mmNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE:
.LFB3024:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rsi, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	imulq	%rdx, %r15
	movq	%rcx, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rdi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	leaq	0(,%r15,4), %r13
	movq	%rdx, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rsi, %rbx
	movq	%r13, %rsi
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	%rbp, %rax
	leaq	.LC2(%rip), %rsi
	movq	%r14, %rdi
	shrq	$4, %rax
	incl	%eax
	movl	%eax, 28(%rsp)
	movq	%rbx, %rax
	shrq	$4, %rax
	incl	%eax
	movl	%eax, 32(%rsp)
	call	_ZSteqIcSt11char_traitsIcESaIcEEbRKNSt7__cxx1112basic_stringIT_T0_T1_EEPKS5_
	testb	%al, %al
	je	.L23
	movq	28(%rsp), %rdi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$68719476752, %rdx
	movl	$1, %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L25
	movq	8(%rsp), %rsi
	movq	%rbp, %rcx
	movq	%rbx, %rdx
	movq	%r12, %rdi
	call	_Z40__device_stub__Z9greyscalePK6uchar4PS_mmPK6uchar4PS_mm
	jmp	.L25
.L23:
	leaq	.LC3(%rip), %rsi
	movq	%r14, %rdi
	call	_ZSteqIcSt11char_traitsIcESaIcEEbRKNSt7__cxx1112basic_stringIT_T0_T1_EEPKS5_
	movabsq	$68719476752, %rdx
	testb	%al, %al
	je	.L25
	movq	28(%rsp), %rdi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movl	$1, %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L25
	movq	8(%rsp), %rsi
	movq	%rbp, %rcx
	movq	%rbx, %rdx
	movq	%r12, %rdi
	call	_Z39__device_stub__Z8vignettePK6uchar4PS_mmPK6uchar4PS_mm
.L25:
	movabsq	$2305843009213693950, %rax
	cmpq	%r15, %rax
	jb	.L27
	movq	%r13, %rdi
	call	_Znam@PLT
	movq	8(%rsp), %rsi
	movl	$2, %ecx
	movq	%r13, %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L29
	jmp	.L33
.L27:
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	jne	.L33
	call	__cxa_throw_bad_array_new_length@PLT
.L33:
	call	__stack_chk_fail@PLT
.L29:
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	movq	%rbx, %rax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3024:
	.size	_Z12apply_filterP6uchar4mmNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, .-_Z12apply_filterP6uchar4mmNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

// Corresponding header file: /include/filter_ops.h
#include <hip/hip_runtime.h>
#include <string>
#include <math.h>

/*
 * Contains kernels and functions for adding photo filters to the imput image.
 * apply_filter() function is called to apply the filter with image on GPU and
 * filter name as parameters. A pointer to the new image in RAM is returned to 
 * the caller. 
 */
const int BLOCK_WIDTH = 16;

// Kernel : Greyscale
__global__ void greyscale(const uchar4* const d_color, uchar4* d_grey, size_t numRows, size_t numCols)
{
  int thread_x = blockDim.x * blockIdx.x + threadIdx.x;
  int thread_y = blockDim.y * blockIdx.y + threadIdx.y;

  int myId = thread_y * numCols + thread_x;
  if(thread_x >= numCols || thread_y >= numRows) 
    return;
  
  unsigned char Y = 0.299f * d_color[myId].x + 0.587 * d_color[myId].y + 0.114 * d_color[myId].z;
  d_grey[myId] = make_uchar4(Y, Y, Y, 255);
}

__device__ double get_distance_between(double x1, double y1,
                                       double x2, double y2){
  return sqrt(pow(x1-x2, 2) + pow(y1-y2, 2));
}

// Kernel : Vignette
__global__ void vignette(const uchar4* const d_in, uchar4* d_vignette,
                         const size_t numRows, const size_t numCols)
{
  int thread_x = blockDim.x * blockIdx.x + threadIdx.x;
  int thread_y = blockDim.y * blockIdx.y + threadIdx.y;
  if(thread_x >= numCols || thread_y >= numRows)
    return;

  int myId = thread_y * numCols + thread_x; 
  
  // Generating mask
  const double max_image_radius = 1.0 * sqrt((pow((double)numRows, 2) + pow((double)numCols, 2)) / 4);
  const double power = 0.7;

  double dist_from_center = get_distance_between(numRows/2, numCols/2, thread_x, thread_y) / max_image_radius;  
  dist_from_center *= power;
  dist_from_center = pow(cos(dist_from_center), 4); 

  uchar4 rgba = d_in[myId];
  d_vignette[myId] = make_uchar4(rgba.x * dist_from_center, 
                                 rgba.y * dist_from_center,
                                 rgba.z * dist_from_center,
                                 255);
}

uchar4* apply_filter(uchar4 *d_in, const size_t numRows, const size_t numCols, std::string filtername)
{
  uchar4 *d_out;
  hipMalloc((void **) &d_out, numRows * numCols * sizeof(uchar4));

  const dim3 block_size(BLOCK_WIDTH, BLOCK_WIDTH, 1);
  const dim3 grid_size(numCols/BLOCK_WIDTH + 1, numRows/BLOCK_WIDTH + 1, 1);

  if(filtername == "greyscale"){
    greyscale<<<grid_size, block_size>>>(d_in, d_out, numRows, numCols);
  }
  else if(filtername == "vignette"){
    vignette<<<grid_size, block_size>>>(d_in, d_out, numRows, numCols);
  }

  uchar4* h_out = new uchar4[numRows * numCols];
  hipMemcpy(h_out, d_out, numRows * numCols * sizeof(uchar4), hipMemcpyDeviceToHost);
  hipFree(d_out);
  return h_out;
}

	.text
	.file	"filter_ops.hip"
	.globl	_Z24__device_stub__greyscalePK15HIP_vector_typeIhLj4EEPS0_mm # -- Begin function _Z24__device_stub__greyscalePK15HIP_vector_typeIhLj4EEPS0_mm
	.type	_Z24__device_stub__greyscalePK15HIP_vector_typeIhLj4EEPS0_mm,@function
_Z24__device_stub__greyscalePK15HIP_vector_typeIhLj4EEPS0_mm: # @_Z24__device_stub__greyscalePK15HIP_vector_typeIhLj4EEPS0_mm
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9greyscalePK15HIP_vector_typeIhLj4EEPS0_mm, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z24__device_stub__greyscalePK15HIP_vector_typeIhLj4EEPS0_mm, .Lfunc_end0-_Z24__device_stub__greyscalePK15HIP_vector_typeIhLj4EEPS0_mm
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__vignettePK15HIP_vector_typeIhLj4EEPS0_mm # -- Begin function _Z23__device_stub__vignettePK15HIP_vector_typeIhLj4EEPS0_mm
	.type	_Z23__device_stub__vignettePK15HIP_vector_typeIhLj4EEPS0_mm,@function
_Z23__device_stub__vignettePK15HIP_vector_typeIhLj4EEPS0_mm: # @_Z23__device_stub__vignettePK15HIP_vector_typeIhLj4EEPS0_mm
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8vignettePK15HIP_vector_typeIhLj4EEPS0_mm, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z23__device_stub__vignettePK15HIP_vector_typeIhLj4EEPS0_mm, .Lfunc_end1-_Z23__device_stub__vignettePK15HIP_vector_typeIhLj4EEPS0_mm
	.cfi_endproc
                                        # -- End function
	.globl	_Z12apply_filterP15HIP_vector_typeIhLj4EEmmNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE # -- Begin function _Z12apply_filterP15HIP_vector_typeIhLj4EEmmNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
	.type	_Z12apply_filterP15HIP_vector_typeIhLj4EEmmNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE,@function
_Z12apply_filterP15HIP_vector_typeIhLj4EEmmNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE: # @_Z12apply_filterP15HIP_vector_typeIhLj4EEmmNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rcx, %r13
	movq	%rdx, %r14
	movq	%rsi, %r15
	movq	%rdi, %r12
	movq	%rdx, %rbp
	imulq	%rsi, %rbp
	leaq	(,%rbp,4), %rbx
	movq	%rsp, %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	movq	%r14, %rax
	shrq	$4, %rax
	incl	%eax
	movq	%r15, %rcx
	andq	$-16, %rcx
	shlq	$28, %rcx
	orq	%rax, %rcx
	movabsq	$4294967296, %rdi               # imm = 0x100000000
	addq	%rcx, %rdi
	movq	8(%r13), %rax
	cmpq	$8, %rax
	je	.LBB2_5
# %bb.1:
	cmpq	$9, %rax
	jne	.LBB2_8
# %bb.2:                                # %_ZSteqIcSt11char_traitsIcESaIcEEbRKNSt7__cxx1112basic_stringIT_T0_T1_EEPKS5_.exit
	movq	(%r13), %rax
	movabsq	$7809632576446231143, %rcx      # imm = 0x6C61637379657267
	xorq	(%rax), %rcx
	movzbl	8(%rax), %eax
	xorq	$101, %rax
	orq	%rcx, %rax
	jne	.LBB2_8
# %bb.3:                                # %_ZSteqIcSt11char_traitsIcESaIcEEbRKNSt7__cxx1112basic_stringIT_T0_T1_EEPKS5_.exit.thread
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_8
# %bb.4:
	movq	(%rsp), %rsi
	movq	%r12, %rdi
	movq	%r15, %rdx
	movq	%r14, %rcx
	callq	_Z24__device_stub__greyscalePK15HIP_vector_typeIhLj4EEPS0_mm
	jmp	.LBB2_8
.LBB2_5:                                # %_ZSteqIcSt11char_traitsIcESaIcEEbRKNSt7__cxx1112basic_stringIT_T0_T1_EEPKS5_.exit31
	movq	(%r13), %rax
	movabsq	$7310596074121947510, %rcx      # imm = 0x657474656E676976
	cmpq	%rcx, (%rax)
	jne	.LBB2_8
# %bb.6:                                # %_ZSteqIcSt11char_traitsIcESaIcEEbRKNSt7__cxx1112basic_stringIT_T0_T1_EEPKS5_.exit31.thread
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_8
# %bb.7:
	movq	(%rsp), %rsi
	movq	%r12, %rdi
	movq	%r15, %rdx
	movq	%r14, %rcx
	callq	_Z23__device_stub__vignettePK15HIP_vector_typeIhLj4EEPS0_mm
.LBB2_8:                                # %_ZSteqIcSt11char_traitsIcESaIcEEbRKNSt7__cxx1112basic_stringIT_T0_T1_EEPKS5_.exit31.thread39
	shrq	$62, %rbp
	xorl	%edi, %edi
	negq	%rbp
	sbbq	%rdi, %rdi
	orq	%rbx, %rdi
	callq	_Znam
	movq	%rax, %r14
	movq	(%rsp), %rsi
	movq	%rax, %rdi
	movq	%rbx, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	(%rsp), %rdi
	callq	hipFree
	movq	%r14, %rax
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z12apply_filterP15HIP_vector_typeIhLj4EEmmNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE, .Lfunc_end2-_Z12apply_filterP15HIP_vector_typeIhLj4EEmmNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEEE
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9greyscalePK15HIP_vector_typeIhLj4EEPS0_mm, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8vignettePK15HIP_vector_typeIhLj4EEPS0_mm, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z9greyscalePK15HIP_vector_typeIhLj4EEPS0_mm,@object # @_Z9greyscalePK15HIP_vector_typeIhLj4EEPS0_mm
	.section	.rodata,"a",@progbits
	.globl	_Z9greyscalePK15HIP_vector_typeIhLj4EEPS0_mm
	.p2align	3, 0x0
_Z9greyscalePK15HIP_vector_typeIhLj4EEPS0_mm:
	.quad	_Z24__device_stub__greyscalePK15HIP_vector_typeIhLj4EEPS0_mm
	.size	_Z9greyscalePK15HIP_vector_typeIhLj4EEPS0_mm, 8

	.type	_Z8vignettePK15HIP_vector_typeIhLj4EEPS0_mm,@object # @_Z8vignettePK15HIP_vector_typeIhLj4EEPS0_mm
	.globl	_Z8vignettePK15HIP_vector_typeIhLj4EEPS0_mm
	.p2align	3, 0x0
_Z8vignettePK15HIP_vector_typeIhLj4EEPS0_mm:
	.quad	_Z23__device_stub__vignettePK15HIP_vector_typeIhLj4EEPS0_mm
	.size	_Z8vignettePK15HIP_vector_typeIhLj4EEPS0_mm, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"greyscale"
	.size	.L.str, 10

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"vignette"
	.size	.L.str.1, 9

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z9greyscalePK15HIP_vector_typeIhLj4EEPS0_mm"
	.size	.L__unnamed_1, 45

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z8vignettePK15HIP_vector_typeIhLj4EEPS0_mm"
	.size	.L__unnamed_2, 44

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z24__device_stub__greyscalePK15HIP_vector_typeIhLj4EEPS0_mm
	.addrsig_sym _Z23__device_stub__vignettePK15HIP_vector_typeIhLj4EEPS0_mm
	.addrsig_sym __gxx_personality_v0
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z9greyscalePK15HIP_vector_typeIhLj4EEPS0_mm
	.addrsig_sym _Z8vignettePK15HIP_vector_typeIhLj4EEPS0_mm
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z9greyscalePK15HIP_vector_typeIhLj4EEPS0_mm ; -- Begin function _Z9greyscalePK15HIP_vector_typeIhLj4EEPS0_mm
	.globl	_Z9greyscalePK15HIP_vector_typeIhLj4EEPS0_mm
	.p2align	8
	.type	_Z9greyscalePK15HIP_vector_typeIhLj4EEPS0_mm,@function
_Z9greyscalePK15HIP_vector_typeIhLj4EEPS0_mm: ; @_Z9greyscalePK15HIP_vector_typeIhLj4EEPS0_mm
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b256 s[4:11], s[0:1], 0x0
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v4, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s0, s2, 16
	s_and_b32 s1, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[0:1], null, s14, s1, v[2:3]
	v_mad_u64_u32 v[2:3], null, s15, s0, v[4:5]
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v3, 31, v2
	v_cmp_gt_u64_e32 vcc_lo, s[10:11], v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_u64_e64 s0, s[8:9], v[2:3]
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_mad_u64_u32 v[3:4], null, v2, s10, v[0:1]
	s_mov_b32 s0, 0x39581062
	s_mov_b32 s1, 0x3fe2c8b4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[0:1], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	global_load_b32 v6, v[2:3], off
	s_waitcnt vmcnt(0)
	v_cvt_f32_ubyte0_e32 v2, v6
	v_bfe_u32 v3, v6, 8, 8
	v_bfe_u32 v6, v6, 16, 8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v4, 0x3e991687, v2
	v_cvt_f64_u32_e32 v[2:3], v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f64_u32_e32 v[6:7], v6
	v_cvt_f64_f32_e32 v[4:5], v4
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[2:3], v[2:3], s[0:1], v[4:5]
	s_mov_b32 s0, 0x9fbe76c9
	s_mov_b32 s1, 0x3fbd2f1a
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[2:3], v[6:7], s[0:1], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_i32_f64_e32 v2, v[2:3]
	v_lshlrev_b16 v3, 8, v2
	v_or_b32_e32 v4, 0xffffff00, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v2, v2, v3
	v_lshlrev_b32_e32 v3, 16, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v2, 0xffff, v2
	v_or_b32_e32 v2, v2, v3
	global_store_b32 v[0:1], v2, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9greyscalePK15HIP_vector_typeIhLj4EEPS0_mm
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z9greyscalePK15HIP_vector_typeIhLj4EEPS0_mm, .Lfunc_end0-_Z9greyscalePK15HIP_vector_typeIhLj4EEPS0_mm
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 356
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z8vignettePK15HIP_vector_typeIhLj4EEPS0_mm ; -- Begin function _Z8vignettePK15HIP_vector_typeIhLj4EEPS0_mm
	.globl	_Z8vignettePK15HIP_vector_typeIhLj4EEPS0_mm
	.p2align	8
	.type	_Z8vignettePK15HIP_vector_typeIhLj4EEPS0_mm,@function
_Z8vignettePK15HIP_vector_typeIhLj4EEPS0_mm: ; @_Z8vignettePK15HIP_vector_typeIhLj4EEPS0_mm
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b256 s[16:23], s[0:1], 0x0
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v4, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s0, s2, 16
	s_and_b32 s1, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[0:1], null, s14, s1, v[2:3]
	v_mad_u64_u32 v[2:3], null, s15, s0, v[4:5]
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v3, 31, v2
	v_cmp_gt_u64_e32 vcc_lo, s[22:23], v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_u64_e64 s0, s[20:21], v[2:3]
	s_and_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_6
; %bb.1:
	v_cvt_f64_u32_e32 v[3:4], s21
	v_cvt_f64_u32_e32 v[5:6], s23
	v_cvt_f64_u32_e32 v[7:8], s20
	v_cvt_f64_u32_e32 v[9:10], s22
	s_mov_b32 s6, 0x55555555
	s_mov_b32 s7, 0x3fe55555
	s_mov_b32 s8, 0x968915a9
	s_mov_b32 s10, 0x4222de17
	s_mov_b32 s9, 0x3fba6564
	s_mov_b32 s11, 0x3fbdee67
	s_mov_b32 s12, 0x3abe935a
	s_mov_b32 s13, 0x3fbe25e4
	s_mov_b32 s24, 0x47e6c9c2
	s_mov_b32 s25, 0x3fc110ef
	s_mov_b32 s26, 0xcfa74449
	s_mov_b32 s27, 0x3fc3b13b
	s_mov_b32 s28, 0x71bf3c30
	s_mov_b32 s29, 0x3fc745d1
	s_mov_b32 s34, 0x1c7792ce
	s_mov_b32 s35, 0x3fcc71c7
	s_mov_b32 s36, 0x924920da
	s_mov_b32 s37, 0x3fd24924
	s_mov_b32 s40, 0x9999999c
	s_mov_b32 s41, 0x3fd99999
	s_mov_b32 s39, 0xbfe55555
	s_mov_b32 s38, s6
	s_mov_b32 s42, 0xd5df274d
	s_mov_b32 s43, 0x3c8543b0
	s_mov_b32 s14, 0xfefa39ef
	s_mov_b32 s15, 0x3fe62e42
	s_mov_b32 s44, 0x3b39803f
	s_mov_b32 s45, 0x3c7abc9e
	s_mov_b32 s30, 0x652b82fe
	s_mov_b32 s31, 0x3ff71547
	s_mov_b32 s47, 0xbfe62e42
	s_mov_b32 s46, s14
	s_mov_b32 s49, 0xbc7abc9e
	s_mov_b32 s48, s44
	v_ldexp_f64 v[3:4], v[3:4], 32
	v_ldexp_f64 v[5:6], v[5:6], 32
	s_mov_b32 s50, 0xfca7ab0c
	s_mov_b32 s52, 0x6a5dcb37
	s_mov_b32 s51, 0x3e928af3
	s_mov_b32 s53, 0x3e5ade15
	s_mov_b32 s54, 0x623fde64
	s_mov_b32 s55, 0x3ec71dee
	s_mov_b32 s56, 0x7c89e6b0
	s_mov_b32 s57, 0x3efa0199
	s_mov_b32 s58, 0x14761f6e
	s_mov_b32 s59, 0x3f2a01a0
	s_mov_b32 s60, 0x1852b7b0
	s_mov_b32 s61, 0x3f56c16c
	s_mov_b32 s62, 0x11122322
	s_mov_b32 s63, 0x3f811111
	s_mov_b32 s64, 0x555502a1
	s_mov_b32 s65, 0x3fa55555
	s_mov_b32 s66, 0x55555511
	s_mov_b32 s67, 0x3fc55555
	s_mov_b32 s68, 11
	s_mov_b32 s69, 0x3fe00000
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[3:4], v[3:4], v[7:8]
	v_add_f64 v[5:6], v[5:6], v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_frexp_mant_f64_e32 v[7:8], v[3:4]
	v_frexp_mant_f64_e32 v[9:10], v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_f64_e32 vcc_lo, s[6:7], v[7:8]
	v_cmp_gt_f64_e64 s0, s[6:7], v[9:10]
	v_cndmask_b32_e64 v1, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v11, 0, 1, s0
	v_ldexp_f64 v[7:8], v[7:8], v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_ldexp_f64 v[9:10], v[9:10], v11
	v_frexp_exp_i32_f64_e32 v1, v[3:4]
	v_add_f64 v[11:12], v[7:8], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[13:14], v[9:10], 1.0
	v_add_f64 v[23:24], v[7:8], -1.0
	v_subrev_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f64_e32 v[15:16], v[11:12]
	v_rcp_f64_e32 v[17:18], v[13:14]
	v_add_f64 v[27:28], v[11:12], -1.0
	v_add_f64 v[31:32], v[13:14], -1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_f64 v[7:8], v[7:8], -v[27:28]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[19:20], -v[11:12], v[15:16], 1.0
	v_fma_f64 v[21:22], -v[13:14], v[17:18], 1.0
	v_fma_f64 v[15:16], v[19:20], v[15:16], v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[17:18], v[21:22], v[17:18], v[17:18]
	v_fma_f64 v[19:20], -v[11:12], v[15:16], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[21:22], -v[13:14], v[17:18], 1.0
	v_fma_f64 v[15:16], v[19:20], v[15:16], v[15:16]
	v_add_f64 v[19:20], v[9:10], -1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f64 v[17:18], v[21:22], v[17:18], v[17:18]
	v_add_f64 v[9:10], v[9:10], -v[31:32]
	v_mul_f64 v[21:22], v[23:24], v[15:16]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[25:26], v[19:20], v[17:18]
	v_mul_f64 v[29:30], v[11:12], v[21:22]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[33:34], v[13:14], v[25:26]
	v_fma_f64 v[11:12], v[21:22], v[11:12], -v[29:30]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[13:14], v[25:26], v[13:14], -v[33:34]
	v_fma_f64 v[7:8], v[21:22], v[7:8], v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[9:10], v[25:26], v[9:10], v[13:14]
	v_add_f64 v[11:12], v[29:30], v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[13:14], v[33:34], v[9:10]
	v_add_f64 v[27:28], v[23:24], -v[11:12]
	v_add_f64 v[29:30], v[11:12], -v[29:30]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[31:32], v[19:20], -v[13:14]
	v_add_f64 v[33:34], v[13:14], -v[33:34]
	v_add_f64 v[23:24], v[23:24], -v[27:28]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[7:8], v[29:30], -v[7:8]
	v_add_f64 v[19:20], v[19:20], -v[31:32]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[9:10], v[33:34], -v[9:10]
	v_add_f64 v[11:12], v[23:24], -v[11:12]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[13:14], v[19:20], -v[13:14]
	v_add_f64 v[7:8], v[7:8], v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[9:10], v[9:10], v[13:14]
	v_add_f64 v[7:8], v[27:28], v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[9:10], v[31:32], v[9:10]
	v_mul_f64 v[7:8], v[15:16], v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[9:10], v[17:18], v[9:10]
	v_add_f64 v[11:12], v[21:22], v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[13:14], v[25:26], v[9:10]
	v_add_f64 v[15:16], v[11:12], -v[21:22]
	v_mul_f64 v[19:20], v[11:12], v[11:12]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[17:18], v[13:14], -v[25:26]
	v_ldexp_f64 v[3:4], v[11:12], 1
	v_add_f64 v[7:8], v[7:8], -v[15:16]
	v_mul_f64 v[15:16], v[13:14], v[13:14]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[9:10], v[9:10], -v[17:18]
	v_fma_f64 v[17:18], v[11:12], v[11:12], -v[19:20]
	v_add_f64 v[21:22], v[7:8], v[7:8]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[23:24], v[13:14], v[13:14], -v[15:16]
	v_add_f64 v[25:26], v[9:10], v[9:10]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[17:18], v[11:12], v[21:22], v[17:18]
	v_fma_f64 v[21:22], v[13:14], v[25:26], v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[23:24], v[19:20], v[17:18]
	v_add_f64 v[25:26], v[15:16], v[21:22]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[27:28], v[23:24], s[10:11], s[8:9]
	v_add_f64 v[19:20], v[23:24], -v[19:20]
	v_fma_f64 v[29:30], v[25:26], s[10:11], s[8:9]
	v_add_f64 v[15:16], v[25:26], -v[15:16]
	v_mul_f64 v[37:38], v[11:12], v[23:24]
	v_mul_f64 v[41:42], v[13:14], v[25:26]
	v_fma_f64 v[27:28], v[23:24], v[27:28], s[12:13]
	v_add_f64 v[17:18], v[17:18], -v[19:20]
	v_fma_f64 v[29:30], v[25:26], v[29:30], s[12:13]
	v_add_f64 v[15:16], v[21:22], -v[15:16]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[27:28], v[23:24], v[27:28], s[24:25]
	v_fma_f64 v[29:30], v[25:26], v[29:30], s[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[27:28], v[23:24], v[27:28], s[26:27]
	v_fma_f64 v[29:30], v[25:26], v[29:30], s[26:27]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[27:28], v[23:24], v[27:28], s[28:29]
	v_fma_f64 v[29:30], v[25:26], v[29:30], s[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[27:28], v[23:24], v[27:28], s[34:35]
	v_fma_f64 v[29:30], v[25:26], v[29:30], s[34:35]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[27:28], v[23:24], v[27:28], s[36:37]
	v_fma_f64 v[29:30], v[25:26], v[29:30], s[36:37]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[27:28], v[23:24], v[27:28], s[40:41]
	v_fma_f64 v[29:30], v[25:26], v[29:30], s[40:41]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[31:32], v[23:24], v[27:28]
	v_mul_f64 v[33:34], v[25:26], v[29:30]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[19:20], v[23:24], v[27:28], -v[31:32]
	v_fma_f64 v[21:22], v[25:26], v[29:30], -v[33:34]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[19:20], v[17:18], v[27:28], v[19:20]
	v_fma_f64 v[21:22], v[15:16], v[29:30], v[21:22]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[27:28], v[31:32], v[19:20]
	v_add_f64 v[29:30], v[33:34], v[21:22]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[35:36], v[27:28], s[6:7]
	v_add_f64 v[31:32], v[27:28], -v[31:32]
	v_add_f64 v[39:40], v[29:30], s[6:7]
	v_add_f64 v[33:34], v[29:30], -v[33:34]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[43:44], v[35:36], s[38:39]
	v_add_f64 v[19:20], v[19:20], -v[31:32]
	v_fma_f64 v[31:32], v[23:24], v[11:12], -v[37:38]
	v_add_f64 v[45:46], v[39:40], s[38:39]
	v_add_f64 v[21:22], v[21:22], -v[33:34]
	v_fma_f64 v[33:34], v[25:26], v[13:14], -v[41:42]
	v_add_f64 v[27:28], v[27:28], -v[43:44]
	v_add_f64 v[19:20], v[19:20], s[42:43]
	v_fma_f64 v[23:24], v[23:24], v[7:8], v[31:32]
	v_add_f64 v[29:30], v[29:30], -v[45:46]
	v_add_f64 v[21:22], v[21:22], s[42:43]
	v_fma_f64 v[25:26], v[25:26], v[9:10], v[33:34]
	v_ldexp_f64 v[7:8], v[7:8], 1
	v_ldexp_f64 v[9:10], v[9:10], 1
	v_add_f64 v[19:20], v[19:20], v[27:28]
	v_fma_f64 v[17:18], v[17:18], v[11:12], v[23:24]
	v_ldexp_f64 v[11:12], v[13:14], 1
	v_add_f64 v[21:22], v[21:22], v[29:30]
	v_fma_f64 v[15:16], v[15:16], v[13:14], v[25:26]
	v_add_f64 v[23:24], v[35:36], v[19:20]
	v_add_f64 v[25:26], v[37:38], v[17:18]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[27:28], v[39:40], v[21:22]
	v_add_f64 v[29:30], v[41:42], v[15:16]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[31:32], v[35:36], -v[23:24]
	v_mul_f64 v[33:34], v[25:26], v[23:24]
	v_add_f64 v[37:38], v[25:26], -v[37:38]
	v_add_f64 v[35:36], v[39:40], -v[27:28]
	v_mul_f64 v[39:40], v[29:30], v[27:28]
	v_add_f64 v[41:42], v[29:30], -v[41:42]
	v_add_f64 v[19:20], v[19:20], v[31:32]
	v_fma_f64 v[31:32], v[25:26], v[23:24], -v[33:34]
	v_add_f64 v[17:18], v[17:18], -v[37:38]
	v_add_f64 v[21:22], v[21:22], v[35:36]
	v_fma_f64 v[35:36], v[29:30], v[27:28], -v[39:40]
	v_add_f64 v[15:16], v[15:16], -v[41:42]
	v_fma_f64 v[19:20], v[25:26], v[19:20], v[31:32]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[21:22], v[29:30], v[21:22], v[35:36]
	v_fma_f64 v[17:18], v[17:18], v[23:24], v[19:20]
	v_frexp_exp_i32_f64_e32 v19, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[15:16], v[15:16], v[27:28], v[21:22]
	v_add_f64 v[5:6], v[33:34], v[17:18]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e64 v25, vcc_lo, 0, v19, s0
	v_add_f64 v[13:14], v[39:40], v[15:16]
	v_cvt_f64_i32_e32 v[19:20], v1
	s_delay_alu instid0(VALU_DEP_3)
	v_cvt_f64_i32_e32 v[25:26], v25
	v_add_f64 v[21:22], v[3:4], v[5:6]
	v_add_f64 v[23:24], v[5:6], -v[33:34]
	v_add_f64 v[27:28], v[11:12], v[13:14]
	v_add_f64 v[29:30], v[13:14], -v[39:40]
	v_mul_f64 v[31:32], v[19:20], s[14:15]
	v_add_f64 v[3:4], v[21:22], -v[3:4]
	v_add_f64 v[17:18], v[17:18], -v[23:24]
	v_mul_f64 v[23:24], v[25:26], s[14:15]
	v_add_f64 v[11:12], v[27:28], -v[11:12]
	v_add_f64 v[15:16], v[15:16], -v[29:30]
	v_fma_f64 v[29:30], v[19:20], s[14:15], -v[31:32]
	v_add_f64 v[3:4], v[5:6], -v[3:4]
	v_add_f64 v[5:6], v[7:8], v[17:18]
	v_fma_f64 v[7:8], v[25:26], s[14:15], -v[23:24]
	v_add_f64 v[11:12], v[13:14], -v[11:12]
	v_add_f64 v[9:10], v[9:10], v[15:16]
	v_fma_f64 v[13:14], v[19:20], s[44:45], v[29:30]
	v_add_f64 v[3:4], v[5:6], v[3:4]
	v_fma_f64 v[5:6], v[25:26], s[44:45], v[7:8]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[7:8], v[9:10], v[11:12]
	v_add_f64 v[9:10], v[31:32], v[13:14]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[11:12], v[21:22], v[3:4]
	v_add_f64 v[15:16], v[23:24], v[5:6]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[17:18], v[27:28], v[7:8]
	v_add_f64 v[31:32], v[9:10], -v[31:32]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f64 v[19:20], v[9:10], v[11:12]
	v_add_f64 v[21:22], v[11:12], -v[21:22]
	v_add_f64 v[23:24], v[15:16], -v[23:24]
	v_add_f64 v[25:26], v[15:16], v[17:18]
	v_add_f64 v[27:28], v[17:18], -v[27:28]
	v_add_f64 v[13:14], v[13:14], -v[31:32]
	v_add_f64 v[29:30], v[19:20], -v[9:10]
	v_add_f64 v[3:4], v[3:4], -v[21:22]
	v_add_f64 v[5:6], v[5:6], -v[23:24]
	v_add_f64 v[33:34], v[25:26], -v[15:16]
	v_add_f64 v[7:8], v[7:8], -v[27:28]
	v_add_f64 v[35:36], v[19:20], -v[29:30]
	v_add_f64 v[11:12], v[11:12], -v[29:30]
	v_add_f64 v[21:22], v[13:14], v[3:4]
	v_add_f64 v[37:38], v[25:26], -v[33:34]
	v_add_f64 v[17:18], v[17:18], -v[33:34]
	v_add_f64 v[9:10], v[9:10], -v[35:36]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[15:16], v[15:16], -v[37:38]
	v_add_f64 v[9:10], v[11:12], v[9:10]
	v_add_f64 v[11:12], v[5:6], v[7:8]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[15:16], v[17:18], v[15:16]
	v_add_f64 v[17:18], v[21:22], -v[13:14]
	v_add_f64 v[9:10], v[21:22], v[9:10]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[23:24], v[11:12], -v[5:6]
	v_add_f64 v[15:16], v[11:12], v[15:16]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f64 v[21:22], v[21:22], -v[17:18]
	v_add_f64 v[3:4], v[3:4], -v[17:18]
	v_add_f64 v[27:28], v[19:20], v[9:10]
	v_add_f64 v[11:12], v[11:12], -v[23:24]
	v_add_f64 v[7:8], v[7:8], -v[23:24]
	v_add_f64 v[29:30], v[25:26], v[15:16]
	v_add_f64 v[13:14], v[13:14], -v[21:22]
	v_add_f64 v[17:18], v[27:28], -v[19:20]
	v_add_f64 v[5:6], v[5:6], -v[11:12]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[11:12], v[29:30], -v[25:26]
	v_add_f64 v[3:4], v[3:4], v[13:14]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[9:10], v[9:10], -v[17:18]
	v_add_f64 v[5:6], v[7:8], v[5:6]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[7:8], v[15:16], -v[11:12]
	v_add_f64 v[3:4], v[3:4], v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[5:6], v[5:6], v[7:8]
	v_add_f64 v[7:8], v[27:28], v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[9:10], v[29:30], v[5:6]
	v_add_f64 v[11:12], v[7:8], -v[27:28]
	v_add_f64 v[13:14], v[7:8], v[7:8]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[15:16], v[9:10], -v[29:30]
	v_add_f64 v[17:18], v[9:10], v[9:10]
	v_add_f64 v[3:4], v[3:4], -v[11:12]
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f64 v[7:8], v[7:8], 2.0, -v[13:14]
	v_cmp_class_f64_e64 vcc_lo, v[13:14], 0x204
	v_add_f64 v[5:6], v[5:6], -v[15:16]
	v_fma_f64 v[9:10], v[9:10], 2.0, -v[17:18]
	v_cmp_class_f64_e64 s0, v[17:18], 0x204
	v_fma_f64 v[3:4], v[3:4], 2.0, v[7:8]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[5:6], v[5:6], 2.0, v[9:10]
	v_add_f64 v[7:8], v[13:14], v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[9:10], v[17:18], v[5:6]
	v_dual_cndmask_b32 v12, v8, v14 :: v_dual_cndmask_b32 v11, v7, v13
	v_add_f64 v[7:8], v[7:8], -v[13:14]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v16, v10, v18, s0
	v_cndmask_b32_e64 v15, v9, v17, s0
	v_add_f64 v[9:10], v[9:10], -v[17:18]
	v_mul_f64 v[19:20], v[11:12], s[30:31]
	v_cmp_nlt_f64_e64 s1, 0x40900000, v[11:12]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[11:12]|
	v_mul_f64 v[21:22], v[15:16], s[30:31]
	v_cmp_nlt_f64_e64 s3, 0x40900000, v[15:16]
	v_cmp_ngt_f64_e64 s2, 0xc090cc00, v[11:12]
	v_cmp_ngt_f64_e64 s4, 0xc090cc00, v[15:16]
	v_cmp_neq_f64_e64 s0, 0x7ff00000, |v[15:16]|
	v_add_f64 v[3:4], v[3:4], -v[7:8]
	v_add_f64 v[5:6], v[5:6], -v[9:10]
	v_rndne_f64_e32 v[19:20], v[19:20]
	v_rndne_f64_e32 v[21:22], v[21:22]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v4, 0, v4 :: v_dual_cndmask_b32 v3, 0, v3
	s_and_b32 vcc_lo, s2, s1
	v_cndmask_b32_e64 v6, 0, v6, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fma_f64 v[23:24], v[19:20], s[46:47], v[11:12]
	v_cvt_i32_f64_e32 v1, v[19:20]
	v_cndmask_b32_e64 v5, 0, v5, s0
	v_fma_f64 v[25:26], v[21:22], s[46:47], v[15:16]
	v_fma_f64 v[23:24], v[19:20], s[48:49], v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[25:26], v[21:22], s[48:49], v[25:26]
	v_fma_f64 v[27:28], v[23:24], s[52:53], s[50:51]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[29:30], v[25:26], s[52:53], s[50:51]
	v_fma_f64 v[27:28], v[23:24], v[27:28], s[54:55]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[29:30], v[25:26], v[29:30], s[54:55]
	v_fma_f64 v[27:28], v[23:24], v[27:28], s[56:57]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[29:30], v[25:26], v[29:30], s[56:57]
	v_fma_f64 v[27:28], v[23:24], v[27:28], s[58:59]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[29:30], v[25:26], v[29:30], s[58:59]
	v_fma_f64 v[27:28], v[23:24], v[27:28], s[60:61]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[29:30], v[25:26], v[29:30], s[60:61]
	v_fma_f64 v[27:28], v[23:24], v[27:28], s[62:63]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[29:30], v[25:26], v[29:30], s[62:63]
	v_fma_f64 v[27:28], v[23:24], v[27:28], s[64:65]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[29:30], v[25:26], v[29:30], s[64:65]
	v_fma_f64 v[27:28], v[23:24], v[27:28], s[66:67]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[29:30], v[25:26], v[29:30], s[66:67]
	v_fma_f64 v[27:28], v[23:24], v[27:28], s[68:69]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[29:30], v[25:26], v[29:30], s[68:69]
	v_fma_f64 v[27:28], v[23:24], v[27:28], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[29:30], v[25:26], v[29:30], 1.0
	v_fma_f64 v[19:20], v[23:24], v[27:28], 1.0
	v_cvt_i32_f64_e32 v23, v[21:22]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[21:22], v[25:26], v[29:30], 1.0
	v_ldexp_f64 v[13:14], v[19:20], v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[17:18], v[21:22], v23
	v_cndmask_b32_e64 v1, 0x7ff00000, v14, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v7, 0x7ff00000, v18, s3
	v_cndmask_b32_e64 v8, 0, v1, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v10, 0, v7, s4
	v_cndmask_b32_e32 v7, 0, v13, vcc_lo
	s_and_b32 vcc_lo, s4, s3
	v_cvt_f64_i32_e32 v[13:14], v0
	v_cndmask_b32_e32 v9, 0, v17, vcc_lo
	v_fma_f64 v[3:4], v[7:8], v[3:4], v[7:8]
	v_cmp_class_f64_e64 vcc_lo, v[7:8], 0x204
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f64 v[5:6], v[9:10], v[5:6], v[9:10]
	v_cmp_class_f64_e64 s0, v[9:10], 0x204
	v_dual_cndmask_b32 v4, v4, v8 :: v_dual_cndmask_b32 v3, v3, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v6, v6, v10, s0
	v_cndmask_b32_e64 v5, v5, v9, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[3:4], |v[3:4]|, |v[5:6]|
	v_ldexp_f64 v[3:4], v[3:4], -2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[3:4]
	s_and_b32 s0, vcc_lo, exec_lo
	s_cselect_b32 s5, 0xffffff80, 0
	s_lshr_b64 s[0:1], s[20:21], 1
	s_lshr_b64 s[2:3], s[22:23], 1
	v_cvt_f64_u32_e32 v[5:6], s1
	v_cvt_f64_u32_e32 v[7:8], s3
	v_cvt_f64_u32_e32 v[9:10], s0
	v_cvt_f64_u32_e32 v[11:12], s2
	v_cndmask_b32_e64 v1, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v1, 8, v1
	v_ldexp_f64 v[3:4], v[3:4], v1
	v_ldexp_f64 v[5:6], v[5:6], 32
	v_ldexp_f64 v[7:8], v[7:8], 32
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[5:6], v[5:6], v[9:10]
	v_cvt_f64_i32_e32 v[9:10], v2
	v_add_f64 v[7:8], v[7:8], v[11:12]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[5:6], v[5:6], -v[13:14]
	v_add_f64 v[7:8], v[7:8], -v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_frexp_mant_f64_e64 v[9:10], |v[5:6]|
	v_frexp_mant_f64_e64 v[11:12], |v[7:8]|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_f64_e32 vcc_lo, s[6:7], v[9:10]
	v_cmp_gt_f64_e64 s0, s[6:7], v[11:12]
	v_cndmask_b32_e64 v13, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v14, 0, 1, s0
	v_ldexp_f64 v[9:10], v[9:10], v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[11:12], v[11:12], v14
	v_add_f64 v[13:14], v[9:10], 1.0
	v_add_f64 v[25:26], v[9:10], -1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[15:16], v[11:12], 1.0
	v_rcp_f64_e32 v[17:18], v[13:14]
	v_add_f64 v[29:30], v[13:14], -1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[19:20], v[15:16]
	v_add_f64 v[33:34], v[15:16], -1.0
	v_add_f64 v[9:10], v[9:10], -v[29:30]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[21:22], -v[13:14], v[17:18], 1.0
	v_fma_f64 v[23:24], -v[15:16], v[19:20], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[17:18], v[21:22], v[17:18], v[17:18]
	v_fma_f64 v[19:20], v[23:24], v[19:20], v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[21:22], -v[13:14], v[17:18], 1.0
	v_fma_f64 v[23:24], -v[15:16], v[19:20], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[17:18], v[21:22], v[17:18], v[17:18]
	v_add_f64 v[21:22], v[11:12], -1.0
	v_fma_f64 v[19:20], v[23:24], v[19:20], v[19:20]
	v_add_f64 v[11:12], v[11:12], -v[33:34]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[23:24], v[25:26], v[17:18]
	v_mul_f64 v[27:28], v[21:22], v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[31:32], v[13:14], v[23:24]
	v_mul_f64 v[35:36], v[15:16], v[27:28]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[13:14], v[23:24], v[13:14], -v[31:32]
	v_fma_f64 v[15:16], v[27:28], v[15:16], -v[35:36]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[9:10], v[23:24], v[9:10], v[13:14]
	v_fma_f64 v[11:12], v[27:28], v[11:12], v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[13:14], v[31:32], v[9:10]
	v_add_f64 v[15:16], v[35:36], v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[29:30], v[25:26], -v[13:14]
	v_add_f64 v[31:32], v[13:14], -v[31:32]
	v_add_f64 v[33:34], v[21:22], -v[15:16]
	v_add_f64 v[35:36], v[15:16], -v[35:36]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[25:26], v[25:26], -v[29:30]
	v_add_f64 v[9:10], v[31:32], -v[9:10]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[21:22], v[21:22], -v[33:34]
	v_add_f64 v[11:12], v[35:36], -v[11:12]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[13:14], v[25:26], -v[13:14]
	v_add_f64 v[15:16], v[21:22], -v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[9:10], v[9:10], v[13:14]
	v_add_f64 v[11:12], v[11:12], v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[9:10], v[29:30], v[9:10]
	v_add_f64 v[11:12], v[33:34], v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[9:10], v[17:18], v[9:10]
	v_mul_f64 v[11:12], v[19:20], v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[13:14], v[23:24], v[9:10]
	v_add_f64 v[15:16], v[27:28], v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[17:18], v[13:14], -v[23:24]
	v_mul_f64 v[21:22], v[13:14], v[13:14]
	v_add_f64 v[19:20], v[15:16], -v[27:28]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[9:10], v[9:10], -v[17:18]
	v_mul_f64 v[17:18], v[15:16], v[15:16]
	v_add_f64 v[11:12], v[11:12], -v[19:20]
	v_fma_f64 v[19:20], v[13:14], v[13:14], -v[21:22]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[23:24], v[9:10], v[9:10]
	v_fma_f64 v[25:26], v[15:16], v[15:16], -v[17:18]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[27:28], v[11:12], v[11:12]
	v_fma_f64 v[19:20], v[13:14], v[23:24], v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[23:24], v[15:16], v[27:28], v[25:26]
	v_add_f64 v[25:26], v[21:22], v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[27:28], v[17:18], v[23:24]
	v_fma_f64 v[29:30], v[25:26], s[10:11], s[8:9]
	v_add_f64 v[21:22], v[25:26], -v[21:22]
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f64 v[31:32], v[27:28], s[10:11], s[8:9]
	v_add_f64 v[17:18], v[27:28], -v[17:18]
	v_mul_f64 v[39:40], v[13:14], v[25:26]
	v_mul_f64 v[43:44], v[15:16], v[27:28]
	v_fma_f64 v[29:30], v[25:26], v[29:30], s[12:13]
	v_add_f64 v[19:20], v[19:20], -v[21:22]
	v_fma_f64 v[31:32], v[27:28], v[31:32], s[12:13]
	v_add_f64 v[17:18], v[23:24], -v[17:18]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[29:30], v[25:26], v[29:30], s[24:25]
	v_fma_f64 v[31:32], v[27:28], v[31:32], s[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[29:30], v[25:26], v[29:30], s[26:27]
	v_fma_f64 v[31:32], v[27:28], v[31:32], s[26:27]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[29:30], v[25:26], v[29:30], s[28:29]
	v_fma_f64 v[31:32], v[27:28], v[31:32], s[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[29:30], v[25:26], v[29:30], s[34:35]
	v_fma_f64 v[31:32], v[27:28], v[31:32], s[34:35]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[29:30], v[25:26], v[29:30], s[36:37]
	v_fma_f64 v[31:32], v[27:28], v[31:32], s[36:37]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[29:30], v[25:26], v[29:30], s[40:41]
	v_fma_f64 v[31:32], v[27:28], v[31:32], s[40:41]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[33:34], v[25:26], v[29:30]
	v_mul_f64 v[35:36], v[27:28], v[31:32]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[21:22], v[25:26], v[29:30], -v[33:34]
	v_fma_f64 v[23:24], v[27:28], v[31:32], -v[35:36]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[21:22], v[19:20], v[29:30], v[21:22]
	v_fma_f64 v[23:24], v[17:18], v[31:32], v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[29:30], v[33:34], v[21:22]
	v_add_f64 v[31:32], v[35:36], v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[37:38], v[29:30], s[6:7]
	v_add_f64 v[33:34], v[29:30], -v[33:34]
	v_add_f64 v[41:42], v[31:32], s[6:7]
	v_add_f64 v[35:36], v[31:32], -v[35:36]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[45:46], v[37:38], s[38:39]
	v_add_f64 v[21:22], v[21:22], -v[33:34]
	v_fma_f64 v[33:34], v[25:26], v[13:14], -v[39:40]
	v_add_f64 v[47:48], v[41:42], s[38:39]
	v_add_f64 v[23:24], v[23:24], -v[35:36]
	v_fma_f64 v[35:36], v[27:28], v[15:16], -v[43:44]
	v_add_f64 v[29:30], v[29:30], -v[45:46]
	v_add_f64 v[21:22], v[21:22], s[42:43]
	v_fma_f64 v[25:26], v[25:26], v[9:10], v[33:34]
	v_add_f64 v[31:32], v[31:32], -v[47:48]
	v_add_f64 v[23:24], v[23:24], s[42:43]
	v_fma_f64 v[27:28], v[27:28], v[11:12], v[35:36]
	v_ldexp_f64 v[9:10], v[9:10], 1
	v_ldexp_f64 v[11:12], v[11:12], 1
	v_add_f64 v[21:22], v[21:22], v[29:30]
	v_fma_f64 v[19:20], v[19:20], v[13:14], v[25:26]
	v_ldexp_f64 v[13:14], v[13:14], 1
	v_add_f64 v[23:24], v[23:24], v[31:32]
	v_fma_f64 v[17:18], v[17:18], v[15:16], v[27:28]
	v_ldexp_f64 v[15:16], v[15:16], 1
	v_add_f64 v[25:26], v[37:38], v[21:22]
	v_add_f64 v[27:28], v[39:40], v[19:20]
	v_add_f64 v[29:30], v[41:42], v[23:24]
	v_add_f64 v[31:32], v[43:44], v[17:18]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[33:34], v[37:38], -v[25:26]
	v_mul_f64 v[35:36], v[27:28], v[25:26]
	v_add_f64 v[39:40], v[27:28], -v[39:40]
	v_add_f64 v[37:38], v[41:42], -v[29:30]
	v_mul_f64 v[41:42], v[31:32], v[29:30]
	v_add_f64 v[43:44], v[31:32], -v[43:44]
	v_add_f64 v[21:22], v[21:22], v[33:34]
	v_fma_f64 v[33:34], v[27:28], v[25:26], -v[35:36]
	v_add_f64 v[19:20], v[19:20], -v[39:40]
	v_add_f64 v[23:24], v[23:24], v[37:38]
	v_fma_f64 v[37:38], v[31:32], v[29:30], -v[41:42]
	v_add_f64 v[17:18], v[17:18], -v[43:44]
	v_fma_f64 v[21:22], v[27:28], v[21:22], v[33:34]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[23:24], v[31:32], v[23:24], v[37:38]
	v_fma_f64 v[19:20], v[19:20], v[25:26], v[21:22]
	v_frexp_exp_i32_f64_e32 v25, v[5:6]
	v_frexp_exp_i32_f64_e32 v26, v[7:8]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[17:18], v[17:18], v[29:30], v[23:24]
	v_add_f64 v[21:22], v[35:36], v[19:20]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e32 v25, vcc_lo, 0, v25, vcc_lo
	v_add_f64 v[23:24], v[41:42], v[17:18]
	v_subrev_co_ci_u32_e64 v27, vcc_lo, 0, v26, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_i32_e32 v[25:26], v25
	v_cvt_f64_i32_e32 v[27:28], v27
	v_add_f64 v[29:30], v[13:14], v[21:22]
	v_add_f64 v[31:32], v[21:22], -v[35:36]
	v_add_f64 v[33:34], v[15:16], v[23:24]
	v_add_f64 v[35:36], v[23:24], -v[41:42]
	v_mul_f64 v[37:38], v[25:26], s[14:15]
	v_mul_f64 v[39:40], v[27:28], s[14:15]
	v_add_f64 v[13:14], v[29:30], -v[13:14]
	v_add_f64 v[19:20], v[19:20], -v[31:32]
	v_add_f64 v[15:16], v[33:34], -v[15:16]
	v_add_f64 v[17:18], v[17:18], -v[35:36]
	v_fma_f64 v[31:32], v[25:26], s[14:15], -v[37:38]
	v_add_f64 v[13:14], v[21:22], -v[13:14]
	v_add_f64 v[9:10], v[9:10], v[19:20]
	v_fma_f64 v[19:20], v[27:28], s[14:15], -v[39:40]
	v_add_f64 v[15:16], v[23:24], -v[15:16]
	v_add_f64 v[11:12], v[11:12], v[17:18]
	v_fma_f64 v[17:18], v[25:26], s[44:45], v[31:32]
	v_add_f64 v[9:10], v[9:10], v[13:14]
	v_fma_f64 v[13:14], v[27:28], s[44:45], v[19:20]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[11:12], v[11:12], v[15:16]
	v_add_f64 v[15:16], v[37:38], v[17:18]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[19:20], v[29:30], v[9:10]
	v_add_f64 v[21:22], v[39:40], v[13:14]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[23:24], v[33:34], v[11:12]
	v_add_f64 v[37:38], v[15:16], -v[37:38]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f64 v[25:26], v[15:16], v[19:20]
	v_add_f64 v[29:30], v[19:20], -v[29:30]
	v_add_f64 v[39:40], v[21:22], -v[39:40]
	v_add_f64 v[27:28], v[21:22], v[23:24]
	v_add_f64 v[33:34], v[23:24], -v[33:34]
	v_add_f64 v[17:18], v[17:18], -v[37:38]
	v_add_f64 v[31:32], v[25:26], -v[15:16]
	v_add_f64 v[9:10], v[9:10], -v[29:30]
	v_add_f64 v[13:14], v[13:14], -v[39:40]
	v_add_f64 v[35:36], v[27:28], -v[21:22]
	v_add_f64 v[11:12], v[11:12], -v[33:34]
	v_add_f64 v[41:42], v[25:26], -v[31:32]
	v_add_f64 v[19:20], v[19:20], -v[31:32]
	v_add_f64 v[29:30], v[17:18], v[9:10]
	v_add_f64 v[43:44], v[27:28], -v[35:36]
	v_add_f64 v[23:24], v[23:24], -v[35:36]
	v_add_f64 v[15:16], v[15:16], -v[41:42]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[21:22], v[21:22], -v[43:44]
	v_add_f64 v[15:16], v[19:20], v[15:16]
	v_add_f64 v[19:20], v[13:14], v[11:12]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[21:22], v[23:24], v[21:22]
	v_add_f64 v[23:24], v[29:30], -v[17:18]
	v_add_f64 v[15:16], v[29:30], v[15:16]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[31:32], v[19:20], -v[13:14]
	v_add_f64 v[21:22], v[19:20], v[21:22]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f64 v[29:30], v[29:30], -v[23:24]
	v_add_f64 v[9:10], v[9:10], -v[23:24]
	v_add_f64 v[33:34], v[25:26], v[15:16]
	v_add_f64 v[19:20], v[19:20], -v[31:32]
	v_add_f64 v[11:12], v[11:12], -v[31:32]
	v_add_f64 v[35:36], v[27:28], v[21:22]
	v_add_f64 v[17:18], v[17:18], -v[29:30]
	v_add_f64 v[23:24], v[33:34], -v[25:26]
	v_add_f64 v[13:14], v[13:14], -v[19:20]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[19:20], v[35:36], -v[27:28]
	v_add_f64 v[9:10], v[9:10], v[17:18]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[15:16], v[15:16], -v[23:24]
	v_add_f64 v[11:12], v[11:12], v[13:14]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[13:14], v[21:22], -v[19:20]
	v_add_f64 v[9:10], v[9:10], v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[11:12], v[11:12], v[13:14]
	v_add_f64 v[13:14], v[33:34], v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[15:16], v[35:36], v[11:12]
	v_add_f64 v[17:18], v[13:14], -v[33:34]
	v_add_f64 v[19:20], v[13:14], v[13:14]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[21:22], v[15:16], -v[35:36]
	v_add_f64 v[23:24], v[15:16], v[15:16]
	v_add_f64 v[9:10], v[9:10], -v[17:18]
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f64 v[13:14], v[13:14], 2.0, -v[19:20]
	v_cmp_class_f64_e64 vcc_lo, v[19:20], 0x204
	v_add_f64 v[11:12], v[11:12], -v[21:22]
	v_fma_f64 v[15:16], v[15:16], 2.0, -v[23:24]
	v_cmp_class_f64_e64 s0, v[23:24], 0x204
	v_fma_f64 v[9:10], v[9:10], 2.0, v[13:14]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[11:12], v[11:12], 2.0, v[15:16]
	v_add_f64 v[13:14], v[19:20], v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[15:16], v[23:24], v[11:12]
	v_dual_cndmask_b32 v18, v14, v20 :: v_dual_cndmask_b32 v17, v13, v19
	v_add_f64 v[13:14], v[13:14], -v[19:20]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v22, v16, v24, s0
	v_cndmask_b32_e64 v21, v15, v23, s0
	v_add_f64 v[15:16], v[15:16], -v[23:24]
	v_mul_f64 v[25:26], v[17:18], s[30:31]
	v_cmp_nlt_f64_e64 s1, 0x40900000, v[17:18]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[17:18]|
	v_mul_f64 v[27:28], v[21:22], s[30:31]
	v_cmp_nlt_f64_e64 s3, 0x40900000, v[21:22]
	v_cmp_ngt_f64_e64 s2, 0xc090cc00, v[17:18]
	v_cmp_ngt_f64_e64 s4, 0xc090cc00, v[21:22]
	v_cmp_neq_f64_e64 s0, 0x7ff00000, |v[21:22]|
	v_add_f64 v[9:10], v[9:10], -v[13:14]
	v_add_f64 v[11:12], v[11:12], -v[15:16]
	v_rndne_f64_e32 v[25:26], v[25:26]
	v_rndne_f64_e32 v[27:28], v[27:28]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v10, 0, v10 :: v_dual_cndmask_b32 v9, 0, v9
	s_and_b32 vcc_lo, s2, s1
	v_cndmask_b32_e64 v12, 0, v12, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fma_f64 v[29:30], v[25:26], s[46:47], v[17:18]
	v_cvt_i32_f64_e32 v37, v[25:26]
	v_cndmask_b32_e64 v11, 0, v11, s0
	v_fma_f64 v[31:32], v[27:28], s[46:47], v[21:22]
	v_fma_f64 v[29:30], v[25:26], s[48:49], v[29:30]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[31:32], v[27:28], s[48:49], v[31:32]
	v_fma_f64 v[33:34], v[29:30], s[52:53], s[50:51]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[35:36], v[31:32], s[52:53], s[50:51]
	v_fma_f64 v[33:34], v[29:30], v[33:34], s[54:55]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[35:36], v[31:32], v[35:36], s[54:55]
	v_fma_f64 v[33:34], v[29:30], v[33:34], s[56:57]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[35:36], v[31:32], v[35:36], s[56:57]
	v_fma_f64 v[33:34], v[29:30], v[33:34], s[58:59]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[35:36], v[31:32], v[35:36], s[58:59]
	v_fma_f64 v[33:34], v[29:30], v[33:34], s[60:61]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[35:36], v[31:32], v[35:36], s[60:61]
	v_fma_f64 v[33:34], v[29:30], v[33:34], s[62:63]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[35:36], v[31:32], v[35:36], s[62:63]
	v_fma_f64 v[33:34], v[29:30], v[33:34], s[64:65]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[35:36], v[31:32], v[35:36], s[64:65]
	v_fma_f64 v[33:34], v[29:30], v[33:34], s[66:67]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[35:36], v[31:32], v[35:36], s[66:67]
	v_fma_f64 v[33:34], v[29:30], v[33:34], s[68:69]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[35:36], v[31:32], v[35:36], s[68:69]
	v_fma_f64 v[33:34], v[29:30], v[33:34], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[35:36], v[31:32], v[35:36], 1.0
	v_fma_f64 v[25:26], v[29:30], v[33:34], 1.0
	v_cvt_i32_f64_e32 v29, v[27:28]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[27:28], v[31:32], v[35:36], 1.0
	v_ldexp_f64 v[19:20], v[25:26], v37
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[23:24], v[27:28], v29
	v_cndmask_b32_e64 v13, 0x7ff00000, v20, s1
	v_cmp_neq_f64_e64 s1, 0x7ff00000, |v[5:6]|
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v15, 0x7ff00000, v24, s3
	v_cndmask_b32_e64 v14, 0, v13, s2
	v_cndmask_b32_e32 v13, 0, v19, vcc_lo
	s_and_b32 vcc_lo, s4, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v16, 0, v15, s4
	v_cndmask_b32_e32 v15, 0, v23, vcc_lo
	v_cmp_neq_f64_e64 s3, 0x7ff00000, |v[7:8]|
	v_cmp_neq_f64_e64 s2, 0, v[5:6]
	v_cmp_neq_f64_e64 s4, 0, v[7:8]
	v_fma_f64 v[11:12], v[15:16], v[11:12], v[15:16]
	v_cmp_class_f64_e64 s0, v[15:16], 0x204
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v12, v12, v16, s0
	v_and_b32_e32 v12, 0x7fffffff, v12
	v_fma_f64 v[9:10], v[13:14], v[9:10], v[13:14]
	v_cmp_class_f64_e64 vcc_lo, v[13:14], 0x204
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v5, 0x7ff00000, v12, s3
	v_cndmask_b32_e64 v8, 0, v5, s4
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v10, v10, v14 :: v_dual_cndmask_b32 v7, v9, v13
	v_cndmask_b32_e64 v9, v11, v15, s0
	s_and_b32 vcc_lo, s2, s1
	v_dual_cndmask_b32 v5, 0, v7 :: v_dual_and_b32 v10, 0x7fffffff, v10
	s_and_b32 vcc_lo, s4, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v7, 0, v9, vcc_lo
	v_cndmask_b32_e64 v10, 0x7ff00000, v10, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v6, 0, v10, s2
	v_add_f64 v[5:6], v[5:6], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[5:6]
	v_cndmask_b32_e64 v7, 0, 1, vcc_lo
	v_cndmask_b32_e64 v1, 0, 0xffffff80, vcc_lo
	v_cmp_class_f64_e64 vcc_lo, v[3:4], 0x260
	v_lshlrev_b32_e32 v7, 8, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[5:6], v[5:6], v7
	v_rsq_f64_e32 v[7:8], v[3:4]
	v_rsq_f64_e32 v[9:10], v[5:6]
	v_cmp_class_f64_e64 s0, v[5:6], 0x260
	s_waitcnt_depctr 0xfff
	v_mul_f64 v[11:12], v[3:4], v[7:8]
	v_mul_f64 v[7:8], v[7:8], 0.5
	v_mul_f64 v[13:14], v[5:6], v[9:10]
	v_mul_f64 v[9:10], v[9:10], 0.5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[15:16], -v[7:8], v[11:12], 0.5
	v_fma_f64 v[17:18], -v[9:10], v[13:14], 0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[11:12], v[11:12], v[15:16], v[11:12]
	v_fma_f64 v[7:8], v[7:8], v[15:16], v[7:8]
	v_fma_f64 v[13:14], v[13:14], v[17:18], v[13:14]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[15:16], -v[11:12], v[11:12], v[3:4]
	v_fma_f64 v[9:10], v[9:10], v[17:18], v[9:10]
	v_fma_f64 v[17:18], -v[13:14], v[13:14], v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[11:12], v[15:16], v[7:8], v[11:12]
	v_fma_f64 v[13:14], v[17:18], v[9:10], v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[15:16], -v[11:12], v[11:12], v[3:4]
	v_fma_f64 v[17:18], -v[13:14], v[13:14], v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[7:8], v[15:16], v[7:8], v[11:12]
	v_fma_f64 v[9:10], v[17:18], v[9:10], v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[7:8], v[7:8], s5
	v_ldexp_f64 v[9:10], v[9:10], v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v4, v8, v4 :: v_dual_cndmask_b32 v3, v7, v3
                                        ; implicit-def: $vgpr1
	v_cndmask_b32_e64 v6, v10, v6, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v5, v9, v5, s0
	s_mov_b32 s0, 0x66666666
	s_mov_b32 s1, 0x3fe66666
	v_div_scale_f64 v[7:8], null, v[3:4], v[3:4], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[9:10], v[7:8]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
	v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
	v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
	v_div_scale_f64 v[11:12], vcc_lo, v[5:6], v[3:4], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[13:14], v[11:12], v[9:10]
	v_fma_f64 v[7:8], -v[7:8], v[13:14], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[7:8], v[7:8], v[9:10], v[13:14]
	v_div_fixup_f64 v[3:4], v[7:8], v[3:4], v[5:6]
                                        ; implicit-def: $vgpr5_vgpr6
                                        ; implicit-def: $vgpr7_vgpr8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f64 v[3:4], v[3:4], s[0:1]
	s_mov_b32 s1, exec_lo
	v_cmpx_ngt_f64_e64 0x41d00000, |v[3:4]|
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB1_3
; %bb.2:
	v_ldexp_f64 v[5:6], |v[3:4]|, 0xffffff80
	v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[3:4]|
	v_trig_preop_f64 v[7:8], |v[3:4]|, 0
	v_and_b32_e32 v1, 0x7fffffff, v4
	v_trig_preop_f64 v[9:10], |v[3:4]|, 1
	v_trig_preop_f64 v[19:20], |v[3:4]|, 2
	v_mov_b32_e32 v27, 0
	s_mov_b32 s2, 0x54442d18
	s_mov_b32 s3, 0x3ff921fb
	s_mov_b32 s4, 0x33145c07
	s_mov_b32 s5, 0x3c91a626
	v_dual_cndmask_b32 v6, v1, v6 :: v_dual_cndmask_b32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f64 v[11:12], v[7:8], v[5:6]
	v_mul_f64 v[13:14], v[9:10], v[5:6]
	v_mul_f64 v[25:26], v[19:20], v[5:6]
	v_fma_f64 v[7:8], v[7:8], v[5:6], -v[11:12]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[9:10], v[9:10], v[5:6], -v[13:14]
	v_fma_f64 v[5:6], v[19:20], v[5:6], -v[25:26]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[15:16], v[13:14], v[7:8]
	v_add_f64 v[17:18], v[15:16], -v[13:14]
	v_add_f64 v[23:24], v[11:12], v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[21:22], v[15:16], -v[17:18]
	v_add_f64 v[7:8], v[7:8], -v[17:18]
	v_ldexp_f64 v[17:18], v[23:24], -2
	v_add_f64 v[11:12], v[23:24], -v[11:12]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[13:14], v[13:14], -v[21:22]
	v_add_f64 v[21:22], v[25:26], v[9:10]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[17:18]|
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[11:12], v[15:16], -v[11:12]
	v_add_f64 v[7:8], v[7:8], v[13:14]
	v_fract_f64_e32 v[13:14], v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[15:16], v[21:22], v[7:8]
	v_dual_cndmask_b32 v14, 0, v14 :: v_dual_cndmask_b32 v13, 0, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ldexp_f64 v[13:14], v[13:14], 2
	v_add_f64 v[17:18], v[11:12], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[23:24], v[17:18], v[13:14]
	v_add_f64 v[11:12], v[17:18], -v[11:12]
	v_cmp_gt_f64_e32 vcc_lo, 0, v[23:24]
	v_add_f64 v[23:24], v[21:22], -v[25:26]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[11:12], v[15:16], -v[11:12]
	v_cndmask_b32_e64 v28, 0, 0x40100000, vcc_lo
	v_add_f64 v[32:33], v[21:22], -v[23:24]
	v_add_f64 v[9:10], v[9:10], -v[23:24]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[13:14], v[13:14], v[27:28]
	v_add_f64 v[28:29], v[15:16], -v[21:22]
	v_add_f64 v[23:24], v[25:26], -v[32:33]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[30:31], v[17:18], v[13:14]
	v_add_f64 v[34:35], v[15:16], -v[28:29]
	v_add_f64 v[7:8], v[7:8], -v[28:29]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[9:10], v[9:10], v[23:24]
	v_cvt_i32_f64_e32 v1, v[30:31]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[21:22], v[21:22], -v[34:35]
	v_cvt_f64_i32_e32 v[28:29], v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[7:8], v[7:8], v[21:22]
	v_add_f64 v[13:14], v[13:14], -v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[7:8], v[9:10], v[7:8]
	v_add_f64 v[9:10], v[17:18], v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[5:6], v[5:6], v[7:8]
	v_add_f64 v[7:8], v[9:10], -v[13:14]
	v_cmp_le_f64_e32 vcc_lo, 0.5, v[9:10]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[5:6], v[11:12], v[5:6]
	v_add_f64 v[7:8], v[17:18], -v[7:8]
	v_cndmask_b32_e64 v28, 0, 0x3ff00000, vcc_lo
	v_add_co_ci_u32_e64 v1, s0, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[5:6], v[5:6], v[7:8]
	v_add_f64 v[7:8], v[9:10], -v[27:28]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[9:10], v[7:8], v[5:6]
	v_mul_f64 v[11:12], v[9:10], s[2:3]
	v_add_f64 v[7:8], v[9:10], -v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[13:14], v[9:10], s[2:3], -v[11:12]
	v_add_f64 v[5:6], v[5:6], -v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], v[9:10], s[4:5], v[13:14]
	v_fma_f64 v[7:8], v[5:6], s[2:3], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[5:6], v[11:12], v[7:8]
	v_add_f64 v[9:10], v[5:6], -v[11:12]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[7:8], v[7:8], -v[9:10]
.LBB1_3:                                ; %Flow
	s_and_not1_saveexec_b32 s0, s1
	s_cbranch_execz .LBB1_5
; %bb.4:
	s_mov_b32 s2, 0x6dc9c883
	s_mov_b32 s3, 0x3fe45f30
	s_mov_b32 s5, 0xbc91a626
	v_mul_f64 v[5:6], |v[3:4]|, s[2:3]
	s_mov_b32 s2, 0x54442d18
	s_mov_b32 s3, 0xbff921fb
	s_mov_b32 s4, 0x33145c00
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[9:10], v[5:6]
	v_fma_f64 v[5:6], v[9:10], s[2:3], |v[3:4]|
	v_mul_f64 v[7:8], v[9:10], s[4:5]
	s_mov_b32 s2, 0x252049c0
	s_mov_b32 s3, 0xb97b839a
	v_cvt_i32_f64_e32 v1, v[9:10]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[13:14], v[9:10], s[4:5], v[5:6]
	v_add_f64 v[11:12], v[5:6], v[7:8]
	s_mov_b32 s5, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[5:6], v[5:6], -v[11:12]
	v_add_f64 v[11:12], v[11:12], -v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[5:6], v[5:6], v[7:8]
	v_fma_f64 v[7:8], v[9:10], s[4:5], v[7:8]
	v_add_f64 v[5:6], v[11:12], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[5:6], v[5:6], -v[7:8]
	v_fma_f64 v[7:8], v[9:10], s[2:3], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[5:6], v[13:14], v[7:8]
	v_add_f64 v[11:12], v[5:6], -v[13:14]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[7:8], v[7:8], -v[11:12]
.LBB1_5:                                ; %_ZL3cosd.exit
	s_or_b32 exec_lo, exec_lo, s0
	v_mul_f64 v[9:10], v[5:6], v[5:6]
	s_mov_b32 s0, 0xb42fdfa7
	s_mov_b32 s2, 0xf9a43bb8
	s_mov_b32 s1, 0xbe5ae600
	s_mov_b32 s3, 0x3de5e0b2
	s_mov_b32 s4, 0x796cde01
	s_mov_b32 s5, 0x3ec71de3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_mul_f64 v[19:20], v[7:8], 0.5
	s_mov_b32 s6, 0x968915a9
	s_mov_b32 s8, 0x4222de17
	s_mov_b32 s7, 0x3fba6564
	s_mov_b32 s9, 0x3fbdee67
	v_fma_f64 v[11:12], v[9:10], s[2:3], s[0:1]
	v_mul_f64 v[15:16], v[9:10], 0.5
	s_mov_b32 s0, 0x9037ab78
	s_mov_b32 s2, 0x46cc5e42
	s_mov_b32 s1, 0x3e21eeb6
	s_mov_b32 s3, 0xbda907db
	v_mul_f64 v[21:22], v[5:6], -v[9:10]
	v_fma_f64 v[13:14], v[9:10], s[2:3], s[0:1]
	s_mov_b32 s2, 0x19e83e5c
	s_mov_b32 s3, 0xbf2a01a0
	s_mov_b32 s0, 0xa17f65f6
	s_mov_b32 s1, 0xbe927e4f
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[11:12], v[9:10], v[11:12], s[4:5]
	v_add_f64 v[17:18], -v[15:16], 1.0
	s_mov_b32 s5, 0xbfc55555
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[13:14], v[9:10], v[13:14], s[0:1]
	s_mov_b32 s1, 0x3f811111
	s_mov_b32 s0, 0x11110bb3
	v_fma_f64 v[11:12], v[9:10], v[11:12], s[2:3]
	s_delay_alu instid0(VALU_DEP_3)
	v_add_f64 v[23:24], -v[17:18], 1.0
	s_mov_b32 s2, 0x19f4ec90
	s_mov_b32 s3, 0x3efa01a0
	s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[13:14], v[9:10], v[13:14], s[2:3]
	s_mov_b32 s2, 0x16c16967
	s_mov_b32 s3, 0xbf56c16c
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[11:12], v[9:10], v[11:12], s[0:1]
	v_add_f64 v[15:16], v[23:24], -v[15:16]
	v_cmp_class_f64_e64 s0, v[3:4], 0x1f8
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[13:14], v[9:10], v[13:14], s[2:3]
	s_mov_b32 s3, 0x3fa55555
	s_mov_b32 s2, 0x55555555
	s_mov_b32 s4, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[11:12], v[21:22], v[11:12], v[19:20]
	v_fma_f64 v[15:16], v[5:6], -v[7:8], v[15:16]
	v_mul_f64 v[19:20], v[9:10], v[9:10]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f64 v[13:14], v[9:10], v[13:14], s[2:3]
	s_mov_b32 s2, 0x555502a1
	v_fma_f64 v[7:8], v[9:10], v[11:12], -v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[9:10], v[19:20], v[13:14], v[15:16]
	v_fma_f64 v[7:8], v[21:22], s[4:5], v[7:8]
	s_mov_b32 s5, 0x3fe55555
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[9:10], v[17:18], v[9:10]
	v_add_f64 v[5:6], v[5:6], -v[7:8]
	v_and_b32_e32 v7, 1, v1
	v_lshlrev_b32_e32 v1, 30, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e32 vcc_lo, 0, v7
	v_and_b32_e32 v1, 0x80000000, v1
	v_xor_b32_e32 v3, 0x80000000, v6
	v_cndmask_b32_e32 v5, v5, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v3, v3, v10, vcc_lo
	v_xor_b32_e32 v1, v3, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v3, 0, v5, s0
	v_cndmask_b32_e64 v4, 0x7ff80000, v1, s0
	s_mov_b32 s0, 0x11122322
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_frexp_mant_f64_e64 v[5:6], |v[3:4]|
	v_cmp_gt_f64_e32 vcc_lo, s[4:5], v[5:6]
	v_cndmask_b32_e64 v1, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[5:6], v[5:6], v1
	v_frexp_exp_i32_f64_e32 v1, v[3:4]
	v_add_f64 v[7:8], v[5:6], 1.0
	v_add_f64 v[13:14], v[5:6], -1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	v_rcp_f64_e32 v[9:10], v[7:8]
	v_add_f64 v[15:16], v[7:8], -1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_f64 v[5:6], v[5:6], -v[15:16]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
	v_fma_f64 v[9:10], v[11:12], v[9:10], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], -v[7:8], v[9:10], 1.0
	v_fma_f64 v[9:10], v[11:12], v[9:10], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[11:12], v[13:14], v[9:10]
	v_mul_f64 v[17:18], v[7:8], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], v[11:12], v[7:8], -v[17:18]
	v_fma_f64 v[5:6], v[11:12], v[5:6], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[7:8], v[17:18], v[5:6]
	v_add_f64 v[15:16], v[13:14], -v[7:8]
	v_add_f64 v[17:18], v[7:8], -v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[13:14], v[13:14], -v[15:16]
	v_add_f64 v[5:6], v[17:18], -v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[7:8], v[13:14], -v[7:8]
	v_add_f64 v[5:6], v[5:6], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[5:6], v[15:16], v[5:6]
	v_mul_f64 v[5:6], v[9:10], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[7:8], v[11:12], v[5:6]
	v_add_f64 v[9:10], v[7:8], -v[11:12]
	v_mul_f64 v[11:12], v[7:8], v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[5:6], v[5:6], -v[9:10]
	v_fma_f64 v[9:10], v[7:8], v[7:8], -v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[13:14], v[5:6], v[5:6]
	v_fma_f64 v[9:10], v[7:8], v[13:14], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[13:14], v[11:12], v[9:10]
	v_fma_f64 v[15:16], v[13:14], s[8:9], s[6:7]
	s_mov_b32 s6, 0x3abe935a
	s_mov_b32 s7, 0x3fbe25e4
	v_add_f64 v[11:12], v[13:14], -v[11:12]
	v_mul_f64 v[21:22], v[7:8], v[13:14]
	s_mov_b32 s8, 0x652b82fe
	s_mov_b32 s9, 0x3ff71547
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[15:16], v[13:14], v[15:16], s[6:7]
	s_mov_b32 s6, 0x47e6c9c2
	s_mov_b32 s7, 0x3fc110ef
	v_add_f64 v[9:10], v[9:10], -v[11:12]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[15:16], v[13:14], v[15:16], s[6:7]
	s_mov_b32 s6, 0xcfa74449
	s_mov_b32 s7, 0x3fc3b13b
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[15:16], v[13:14], v[15:16], s[6:7]
	s_mov_b32 s6, 0x71bf3c30
	s_mov_b32 s7, 0x3fc745d1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[15:16], v[13:14], v[15:16], s[6:7]
	s_mov_b32 s6, 0x1c7792ce
	s_mov_b32 s7, 0x3fcc71c7
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[15:16], v[13:14], v[15:16], s[6:7]
	s_mov_b32 s6, 0x924920da
	s_mov_b32 s7, 0x3fd24924
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[15:16], v[13:14], v[15:16], s[6:7]
	s_mov_b32 s6, 0x9999999c
	s_mov_b32 s7, 0x3fd99999
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[15:16], v[13:14], v[15:16], s[6:7]
	s_mov_b32 s7, 0x3c7abc9e
	s_mov_b32 s6, 0x3b39803f
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[17:18], v[13:14], v[15:16]
	v_fma_f64 v[11:12], v[13:14], v[15:16], -v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], v[9:10], v[15:16], v[11:12]
	v_add_f64 v[15:16], v[17:18], v[11:12]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[19:20], v[15:16], s[4:5]
	v_add_f64 v[17:18], v[15:16], -v[17:18]
	s_mov_b32 s5, 0xbfe55555
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_add_f64 v[23:24], v[19:20], s[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_add_f64 v[11:12], v[11:12], -v[17:18]
	v_fma_f64 v[17:18], v[13:14], v[7:8], -v[21:22]
	s_mov_b32 s4, 0xd5df274d
	s_mov_b32 s5, 0x3c8543b0
	v_add_f64 v[15:16], v[15:16], -v[23:24]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[11:12], v[11:12], s[4:5]
	v_fma_f64 v[13:14], v[13:14], v[5:6], v[17:18]
	s_mov_b32 s5, 0x3fe62e42
	s_mov_b32 s4, 0xfefa39ef
	v_ldexp_f64 v[5:6], v[5:6], 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[11:12], v[11:12], v[15:16]
	v_fma_f64 v[9:10], v[9:10], v[7:8], v[13:14]
	v_ldexp_f64 v[7:8], v[7:8], 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[13:14], v[19:20], v[11:12]
	v_add_f64 v[15:16], v[21:22], v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[17:18], v[19:20], -v[13:14]
	v_mul_f64 v[19:20], v[15:16], v[13:14]
	v_add_f64 v[21:22], v[15:16], -v[21:22]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[11:12], v[11:12], v[17:18]
	v_fma_f64 v[17:18], v[15:16], v[13:14], -v[19:20]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[9:10], v[9:10], -v[21:22]
	v_fma_f64 v[11:12], v[15:16], v[11:12], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[9:10], v[9:10], v[13:14], v[11:12]
	v_cvt_f64_i32_e32 v[13:14], v1
	v_add_f64 v[11:12], v[19:20], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[15:16], v[7:8], v[11:12]
	v_add_f64 v[17:18], v[11:12], -v[19:20]
	v_mul_f64 v[19:20], v[13:14], s[4:5]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[7:8], v[15:16], -v[7:8]
	v_add_f64 v[9:10], v[9:10], -v[17:18]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[17:18], v[13:14], s[4:5], -v[19:20]
	s_mov_b32 s5, 0xbfe62e42
	v_add_f64 v[7:8], v[11:12], -v[7:8]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[5:6], v[5:6], v[9:10]
	v_fma_f64 v[9:10], v[13:14], s[6:7], v[17:18]
	s_mov_b32 s7, 0xbc7abc9e
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[5:6], v[5:6], v[7:8]
	v_add_f64 v[7:8], v[19:20], v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[11:12], v[15:16], v[5:6]
	v_add_f64 v[19:20], v[7:8], -v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[13:14], v[7:8], v[11:12]
	v_add_f64 v[15:16], v[11:12], -v[15:16]
	v_add_f64 v[9:10], v[9:10], -v[19:20]
	v_mad_u64_u32 v[19:20], null, v2, s22, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v20, 31, v19
	v_lshlrev_b64 v[0:1], 2, v[19:20]
	v_add_f64 v[17:18], v[13:14], -v[7:8]
	v_add_f64 v[5:6], v[5:6], -v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[21:22], v[13:14], -v[17:18]
	v_add_f64 v[11:12], v[11:12], -v[17:18]
	v_add_f64 v[15:16], v[9:10], v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[7:8], v[7:8], -v[21:22]
	v_add_f64 v[7:8], v[11:12], v[7:8]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[11:12], v[15:16], -v[9:10]
	v_add_f64 v[7:8], v[15:16], v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[15:16], v[15:16], -v[11:12]
	v_add_f64 v[5:6], v[5:6], -v[11:12]
	v_add_f64 v[17:18], v[13:14], v[7:8]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[9:10], v[9:10], -v[15:16]
	v_add_f64 v[11:12], v[17:18], -v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[5:6], v[5:6], v[9:10]
	v_add_f64 v[7:8], v[7:8], -v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[5:6], v[5:6], v[7:8]
	v_add_f64 v[7:8], v[17:18], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[9:10], v[7:8], -v[17:18]
	v_mul_f64 v[11:12], v[7:8], 4.0
	v_add_f64 v[5:6], v[5:6], -v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[7:8], v[7:8], 4.0, -v[11:12]
	v_cmp_class_f64_e64 vcc_lo, v[11:12], 0x204
	v_fma_f64 v[5:6], v[5:6], 4.0, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[7:8], v[11:12], v[5:6]
	v_dual_cndmask_b32 v10, v8, v12 :: v_dual_cndmask_b32 v9, v7, v11
	v_add_co_u32 v19, vcc_lo, s16, v0
	v_add_co_ci_u32_e32 v20, vcc_lo, s17, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_f64 v[13:14], v[9:10], s[8:9]
	v_add_f64 v[7:8], v[7:8], -v[11:12]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[9:10]|
	global_load_b32 v2, v[19:20], off
	v_rndne_f64_e32 v[13:14], v[13:14]
	v_add_f64 v[5:6], v[5:6], -v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_fma_f64 v[15:16], v[13:14], s[4:5], v[9:10]
	s_mov_b32 s4, 0xfca7ab0c
	s_mov_b32 s5, 0x3e928af3
	v_cvt_i32_f64_e32 v19, v[13:14]
	v_dual_cndmask_b32 v6, 0, v6 :: v_dual_cndmask_b32 v5, 0, v5
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f64 v[15:16], v[13:14], s[6:7], v[15:16]
	s_mov_b32 s6, 0x6a5dcb37
	s_mov_b32 s7, 0x3e5ade15
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[17:18], v[15:16], s[6:7], s[4:5]
	s_mov_b32 s4, 0x623fde64
	s_mov_b32 s5, 0x3ec71dee
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[4:5]
	s_mov_b32 s4, 0x7c89e6b0
	s_mov_b32 s5, 0x3efa0199
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[4:5]
	s_mov_b32 s4, 0x14761f6e
	s_mov_b32 s5, 0x3f2a01a0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[4:5]
	s_mov_b32 s4, 0x1852b7b0
	s_mov_b32 s5, 0x3f56c16c
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[0:1]
	s_mov_b32 s0, 0x55555511
	s_mov_b32 s1, 0x3fc55555
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[2:3]
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[0:1]
	s_mov_b32 s0, 11
	s_mov_b32 s1, 0x3fe00000
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[0:1]
	v_cmp_nlt_f64_e64 s0, 0x40900000, v[9:10]
	v_cmp_ngt_f64_e64 s1, 0xc090cc00, v[9:10]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[17:18], v[15:16], v[17:18], 1.0
	s_and_b32 vcc_lo, s1, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], v[15:16], v[17:18], 1.0
	v_ldexp_f64 v[11:12], v[13:14], v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v7, 0x7ff00000, v12, s0
	v_cmp_neq_f64_e64 s0, 0x7ff00000, |v[3:4]|
	v_cndmask_b32_e64 v8, 0, v7, s1
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e32 v7, 0, v11, vcc_lo
	v_cmp_neq_f64_e64 s1, 0, v[3:4]
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v4, 0xff, v2
	v_bfe_u32 v3, v2, 8, 8
	v_fma_f64 v[5:6], v[7:8], v[5:6], v[7:8]
	v_cmp_class_f64_e64 vcc_lo, v[7:8], 0x204
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f64_u32_e32 v[10:11], v4
	v_cndmask_b32_e32 v6, v6, v8, vcc_lo
	v_bfe_u32 v8, v2, 16, 8
	v_cvt_f64_u32_e32 v[2:3], v3
	v_cndmask_b32_e32 v4, v5, v7, vcc_lo
	s_and_b32 vcc_lo, s1, s0
	v_and_b32_e32 v6, 0x7fffffff, v6
	v_cvt_f64_u32_e32 v[8:9], v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v4, 0, v4, vcc_lo
	v_add_co_u32 v0, vcc_lo, s18, v0
	v_cndmask_b32_e64 v6, 0x7ff00000, v6, s0
	v_add_co_ci_u32_e32 v1, vcc_lo, s19, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v5, 0, v6, s1
	v_mul_f64 v[2:3], v[4:5], v[2:3]
	v_mul_f64 v[6:7], v[4:5], v[8:9]
	v_mul_f64 v[4:5], v[4:5], v[10:11]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_i32_f64_e32 v2, v[2:3]
	v_cvt_i32_f64_e32 v3, v[6:7]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_i32_f64_e32 v4, v[4:5]
	v_lshlrev_b16 v2, 8, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v3, 0xffffff00, v3
	v_or_b32_e32 v2, v4, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v3, 16, v3
	v_and_b32_e32 v2, 0xffff, v2
	s_delay_alu instid0(VALU_DEP_1)
	v_or_b32_e32 v2, v2, v3
	global_store_b32 v[0:1], v2, off
.LBB1_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8vignettePK15HIP_vector_typeIhLj4EEPS0_mm
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 49
		.amdhsa_next_free_sgpr 70
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z8vignettePK15HIP_vector_typeIhLj4EEPS0_mm, .Lfunc_end1-_Z8vignettePK15HIP_vector_typeIhLj4EEPS0_mm
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 10256
; NumSgprs: 72
; NumVgprs: 49
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 8
; VGPRBlocks: 6
; NumSGPRsForWavesPerEU: 72
; NumVGPRsForWavesPerEU: 49
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           8
        .value_kind:     by_value
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9greyscalePK15HIP_vector_typeIhLj4EEPS0_mm
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z9greyscalePK15HIP_vector_typeIhLj4EEPS0_mm.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           8
        .value_kind:     by_value
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8vignettePK15HIP_vector_typeIhLj4EEPS0_mm
    .private_segment_fixed_size: 0
    .sgpr_count:     72
    .sgpr_spill_count: 0
    .symbol:         _Z8vignettePK15HIP_vector_typeIhLj4EEPS0_mm.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     49
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
