#include <stdio.h>
#include <cuda_runtime.h>

int log2(int i)
{
    int r = 0;
    while (i >>= 1) r++;
    return r;
}

int bit_reverse(int w, int bits)
{
    int r = 0;
    for (int i = 0; i < bits; i++)
    {
        int bit = (w & (1 << i)) >> i;
        r |= bit << (bits - i - 1);
    }
    return r;
}

/*
Using device 0:
NVIDIA Tegra X1; global mem: 2076037120B; compute v5.3; clock: 921600 kHz
Running naive histo
bin 0: count 7
bin 1: count 7
bin 2: count 6
bin 3: count 6
bin 4: count 7
bin 5: count 6
bin 6: count 7
bin 7: count 6
bin 8: count 7
bin 9: count 7
bin 10: count 7
bin 11: count 7
bin 12: count 7
bin 13: count 6
bin 14: count 6
bin 15: count 8

incorrect due to race condition in d_bins[myBin]++
this does not happen in serial code as each thread runs separately
e.g. BIN with value 5, and thread 1 and 2 wants to increase it
    - thread 1 reads 5, increase to 6, write 6 back to bin
    - thread 2 reads 5, increase to 6, write 6 back to bin
    - but actual answer is 7
*/
__global__ void naive_histo(int *d_bins, const int *d_in, const int BIN_COUNT)
{
    int myId = threadIdx.x + blockDim.x * blockIdx.x;
    int myItem = d_in[myId];
    int myBin = myItem % BIN_COUNT;
    d_bins[myBin]++;
}

/*
Using device 0:
NVIDIA Tegra X1; global mem: 2076037120B; compute v5.3; clock: 921600 kHz
Running simple histo
bin 0: count 4096
bin 1: count 4096
bin 2: count 4096
bin 3: count 4096
bin 4: count 4096
bin 5: count 4096
bin 6: count 4096
bin 7: count 4096
bin 8: count 4096
bin 9: count 4096
bin 10: count 4096
bin 11: count 4096
bin 12: count 4096
bin 13: count 4096
bin 14: count 4096
bin 15: count 4096
*/
__global__ void simple_histo(int *d_bins, const int *d_in, const int BIN_COUNT)
{
    int myId = threadIdx.x + blockDim.x * blockIdx.x;
    int myItem = d_in[myId];
    int myBin = myItem % BIN_COUNT;
    atomicAdd(&(d_bins[myBin]), 1);
}


int main(int argc, char **argv)
{
    int deviceCount;
    cudaGetDeviceCount(&deviceCount);
    if (deviceCount == 0) {
        fprintf(stderr, "error: no devices supporting CUDA.\n");
        exit(EXIT_FAILURE);
    }
    int dev = 0;
    cudaSetDevice(dev);

    cudaDeviceProp devProps;
    if (cudaGetDeviceProperties(&devProps, dev) == 0)
    {
        printf("Using device %d:\n", dev);
        printf("%s; global mem: %dB; compute v%d.%d; clock: %d kHz\n",
               devProps.name, (int)devProps.totalGlobalMem, 
               (int)devProps.major, (int)devProps.minor, 
               (int)devProps.clockRate);
    }

    const int ARRAY_SIZE = 65536;
    const int ARRAY_BYTES = ARRAY_SIZE * sizeof(int);
    const int BIN_COUNT = 16;
    const int BIN_BYTES = BIN_COUNT * sizeof(int);

    // generate the input array on the host
    int h_in[ARRAY_SIZE];
    for(int i = 0; i < ARRAY_SIZE; i++) {
        h_in[i] = bit_reverse(i, log2(ARRAY_SIZE));
    }
    int h_bins[BIN_COUNT];
    for(int i = 0; i < BIN_COUNT; i++) {
        h_bins[i] = 0;
    }

    // declare GPU memory pointers
    int * d_in;
    int * d_bins;

    // allocate GPU memory
    cudaMalloc((void **) &d_in, ARRAY_BYTES);
    cudaMalloc((void **) &d_bins, BIN_BYTES);

    // transfer the arrays to the GPU
    cudaMemcpy(d_in, h_in, ARRAY_BYTES, cudaMemcpyHostToDevice); 
    cudaMemcpy(d_bins, h_bins, BIN_BYTES, cudaMemcpyHostToDevice); 

    int whichKernel = 0;
    if (argc == 2) {
        whichKernel = atoi(argv[1]);
    }
        
    // launch the kernel
    switch(whichKernel) {
    case 0:
        printf("Running naive histo\n");
        naive_histo<<<ARRAY_SIZE / 64, 64>>>(d_bins, d_in, BIN_COUNT);
        break;
    case 1:
        printf("Running simple histo\n");
        simple_histo<<<ARRAY_SIZE / 64, 64>>>(d_bins, d_in, BIN_COUNT);
        break;
    default:
        fprintf(stderr, "error: ran no kernel\n");
        exit(EXIT_FAILURE);
    }

    // copy back the sum from GPU
    cudaMemcpy(h_bins, d_bins, BIN_BYTES, cudaMemcpyDeviceToHost);

    for(int i = 0; i < BIN_COUNT; i++) {
        printf("bin %d: count %d\n", i, h_bins[i]);
    }

    // free GPU memory allocation
    cudaFree(d_in);
    cudaFree(d_bins);
        
    return 0;
}
	.file	"tmpxft_002b40d2_00000000-6_histo.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2032:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z4log2i
	.type	_Z4log2i, @function
_Z4log2i:
.LFB2027:
	.cfi_startproc
	endbr64
	xorl	%eax, %eax
.L3:
	sarl	%edi
	je	.L6
	incl	%eax
	jmp	.L3
.L6:
	ret
	.cfi_endproc
.LFE2027:
	.size	_Z4log2i, .-_Z4log2i
	.globl	_Z11bit_reverseii
	.type	_Z11bit_reverseii, @function
_Z11bit_reverseii:
.LFB2028:
	.cfi_startproc
	endbr64
	xorl	%edx, %edx
	xorl	%r8d, %r8d
	leal	-1(%rsi), %r10d
	movl	$1, %r9d
.L8:
	cmpl	%esi, %edx
	jge	.L10
	movl	%edx, %ecx
	movl	%r9d, %eax
	sall	%cl, %eax
	andl	%edi, %eax
	sarl	%cl, %eax
	movl	%r10d, %ecx
	subl	%edx, %ecx
	incl	%edx
	sall	%cl, %eax
	orl	%eax, %r8d
	jmp	.L8
.L10:
	movl	%r8d, %eax
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z11bit_reverseii, .-_Z11bit_reverseii
	.globl	_Z35__device_stub__Z11naive_histoPiPKiiPiPKii
	.type	_Z35__device_stub__Z11naive_histoPiPKiiPiPKii, @function
_Z35__device_stub__Z11naive_histoPiPKiiPiPKii:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L11
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z11naive_histoPiPKii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L11:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L13
	call	__stack_chk_fail@PLT
.L13:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z35__device_stub__Z11naive_histoPiPKiiPiPKii, .-_Z35__device_stub__Z11naive_histoPiPKiiPiPKii
	.globl	_Z11naive_histoPiPKii
	.type	_Z11naive_histoPiPKii, @function
_Z11naive_histoPiPKii:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z35__device_stub__Z11naive_histoPiPKiiPiPKii
	.cfi_endproc
.LFE2055:
	.size	_Z11naive_histoPiPKii, .-_Z11naive_histoPiPKii
	.globl	_Z36__device_stub__Z12simple_histoPiPKiiPiPKii
	.type	_Z36__device_stub__Z12simple_histoPiPKiiPiPKii, @function
_Z36__device_stub__Z12simple_histoPiPKiiPiPKii:
.LFB2056:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z12simple_histoPiPKii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L16:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L18
	call	__stack_chk_fail@PLT
.L18:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_Z36__device_stub__Z12simple_histoPiPKiiPiPKii, .-_Z36__device_stub__Z12simple_histoPiPKiiPiPKii
	.globl	_Z12simple_histoPiPKii
	.type	_Z12simple_histoPiPKii, @function
_Z12simple_histoPiPKii:
.LFB2057:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z12simple_histoPiPKiiPiPKii
	.cfi_endproc
.LFE2057:
	.size	_Z12simple_histoPiPKii, .-_Z12simple_histoPiPKii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"error: no devices supporting CUDA.\n"
.LC1:
	.string	"Using device %d:\n"
.LC2:
	.string	"%s; global mem: %dB; compute v%d.%d; clock: %d kHz\n"
.LC3:
	.string	"Running naive histo\n"
.LC4:
	.string	"Running simple histo\n"
.LC5:
	.string	"error: ran no kernel\n"
.LC6:
	.string	"bin %d: count %d\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	leaq	-262144(%rsp), %r11
	.cfi_def_cfa 11, 262184
.LPSRL0:
	subq	$4096, %rsp
	orq	$0, (%rsp)
	cmpq	%r11, %rsp
	jne	.LPSRL0
	.cfi_def_cfa_register 7
	subq	$1160, %rsp
	.cfi_def_cfa_offset 263344
	movq	%fs:40, %rax
	movq	%rax, 263288(%rsp)
	xorl	%eax, %eax
	movl	%edi, %r12d
	leaq	4(%rsp), %rdi
	movq	%rsi, %rbx
	call	cudaGetDeviceCount@PLT
	cmpl	$0, 4(%rsp)
	leaq	.LC0(%rip), %rdx
	je	.L40
	xorl	%edi, %edi
	leaq	112(%rsp), %rbp
	call	cudaSetDevice@PLT
	xorl	%esi, %esi
	movq	%rbp, %rdi
	call	cudaGetDeviceProperties_v2@PLT
	testl	%eax, %eax
	jne	.L23
	xorl	%edx, %edx
	leaq	.LC1(%rip), %rsi
	movl	$2, %edi
	call	__printf_chk@PLT
	movq	%rbp, %rdx
	movl	$2, %edi
	leaq	.LC2(%rip), %rsi
	pushq	%rax
	.cfi_def_cfa_offset 263352
	movl	468(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 263360
	movl	492(%rsp), %r9d
	xorl	%eax, %eax
	movl	488(%rsp), %r8d
	movl	416(%rsp), %ecx
	call	__printf_chk@PLT
	popq	%rdx
	.cfi_def_cfa_offset 263352
	popq	%rcx
	.cfi_def_cfa_offset 263344
.L23:
	movl	$65536, %edi
	xorl	%r11d, %r11d
	call	_Z4log2i
	movl	%eax, %esi
.L24:
	movl	%r11d, %edi
	leaq	1144(%rsp), %r13
	call	_Z11bit_reverseii
	movl	%eax, 0(%r13,%r11,4)
	incq	%r11
	cmpq	$65536, %r11
	jne	.L24
	leaq	48(%rsp), %rbp
	xorl	%eax, %eax
	movl	$16, %ecx
	movl	$262144, %esi
	movq	%rbp, %rdi
	rep stosl
	leaq	8(%rsp), %rdi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$64, %esi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%r13, %rsi
	movl	$262144, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$64, %edx
	call	cudaMemcpy@PLT
	cmpl	$2, %r12d
	jne	.L25
	movq	8(%rbx), %rdi
	call	atoi@PLT
	testl	%eax, %eax
	je	.L25
	decl	%eax
	je	.L26
	jmp	.L41
.L25:
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$67108865, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$4194305, %edi
	salq	$6, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	salq	$10, %rdi
	movq	%rdx, 36(%rsp)
	movl	$1, 44(%rsp)
	movq	%rdi, 24(%rsp)
	movl	$1, 32(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L29
	movq	8(%rsp), %rsi
	movq	16(%rsp), %rdi
	movl	$16, %edx
	call	_Z35__device_stub__Z11naive_histoPiPKiiPiPKii
	jmp	.L29
.L26:
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$67108865, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$4194305, %edi
	salq	$6, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	salq	$10, %rdi
	movq	%rdx, 36(%rsp)
	movl	$1, 44(%rsp)
	movq	%rdi, 24(%rsp)
	movl	$1, 32(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L29
	movq	8(%rsp), %rsi
	movq	16(%rsp), %rdi
	movl	$16, %edx
	call	_Z36__device_stub__Z12simple_histoPiPKiiPiPKii
	jmp	.L29
.L41:
	leaq	.LC5(%rip), %rdx
.L40:
	movq	stderr(%rip), %rdi
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	movl	$1, %edi
	call	exit@PLT
.L29:
	movq	16(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbp, %rdi
	xorl	%ebx, %ebx
	movl	$64, %edx
	leaq	.LC6(%rip), %r12
	call	cudaMemcpy@PLT
.L31:
	movl	0(%rbp,%rbx,4), %ecx
	movl	%ebx, %edx
	movq	%r12, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%rbx
	call	__printf_chk@PLT
	cmpq	$16, %rbx
	jne	.L31
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	263288(%rsp), %rax
	subq	%fs:40, %rax
	je	.L32
	call	__stack_chk_fail@PLT
.L32:
	addq	$263304, %rsp
	.cfi_def_cfa_offset 40
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	main, .-main
	.section	.rodata.str1.1
.LC7:
	.string	"_Z12simple_histoPiPKii"
.LC8:
	.string	"_Z11naive_histoPiPKii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2059:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z12simple_histoPiPKii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC8(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z11naive_histoPiPKii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2059:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <hip/hip_runtime.h>

int log2(int i)
{
    int r = 0;
    while (i >>= 1) r++;
    return r;
}

int bit_reverse(int w, int bits)
{
    int r = 0;
    for (int i = 0; i < bits; i++)
    {
        int bit = (w & (1 << i)) >> i;
        r |= bit << (bits - i - 1);
    }
    return r;
}

/*
Using device 0:
NVIDIA Tegra X1; global mem: 2076037120B; compute v5.3; clock: 921600 kHz
Running naive histo
bin 0: count 7
bin 1: count 7
bin 2: count 6
bin 3: count 6
bin 4: count 7
bin 5: count 6
bin 6: count 7
bin 7: count 6
bin 8: count 7
bin 9: count 7
bin 10: count 7
bin 11: count 7
bin 12: count 7
bin 13: count 6
bin 14: count 6
bin 15: count 8

incorrect due to race condition in d_bins[myBin]++
this does not happen in serial code as each thread runs separately
e.g. BIN with value 5, and thread 1 and 2 wants to increase it
    - thread 1 reads 5, increase to 6, write 6 back to bin
    - thread 2 reads 5, increase to 6, write 6 back to bin
    - but actual answer is 7
*/
__global__ void naive_histo(int *d_bins, const int *d_in, const int BIN_COUNT)
{
    int myId = threadIdx.x + blockDim.x * blockIdx.x;
    int myItem = d_in[myId];
    int myBin = myItem % BIN_COUNT;
    d_bins[myBin]++;
}

/*
Using device 0:
NVIDIA Tegra X1; global mem: 2076037120B; compute v5.3; clock: 921600 kHz
Running simple histo
bin 0: count 4096
bin 1: count 4096
bin 2: count 4096
bin 3: count 4096
bin 4: count 4096
bin 5: count 4096
bin 6: count 4096
bin 7: count 4096
bin 8: count 4096
bin 9: count 4096
bin 10: count 4096
bin 11: count 4096
bin 12: count 4096
bin 13: count 4096
bin 14: count 4096
bin 15: count 4096
*/
__global__ void simple_histo(int *d_bins, const int *d_in, const int BIN_COUNT)
{
    int myId = threadIdx.x + blockDim.x * blockIdx.x;
    int myItem = d_in[myId];
    int myBin = myItem % BIN_COUNT;
    atomicAdd(&(d_bins[myBin]), 1);
}


int main(int argc, char **argv)
{
    int deviceCount;
    hipGetDeviceCount(&deviceCount);
    if (deviceCount == 0) {
        fprintf(stderr, "error: no devices supporting CUDA.\n");
        exit(EXIT_FAILURE);
    }
    int dev = 0;
    hipSetDevice(dev);

    hipDeviceProp_t devProps;
    if (hipGetDeviceProperties(&devProps, dev) == 0)
    {
        printf("Using device %d:\n", dev);
        printf("%s; global mem: %dB; compute v%d.%d; clock: %d kHz\n",
               devProps.name, (int)devProps.totalGlobalMem, 
               (int)devProps.major, (int)devProps.minor, 
               (int)devProps.clockRate);
    }

    const int ARRAY_SIZE = 65536;
    const int ARRAY_BYTES = ARRAY_SIZE * sizeof(int);
    const int BIN_COUNT = 16;
    const int BIN_BYTES = BIN_COUNT * sizeof(int);

    // generate the input array on the host
    int h_in[ARRAY_SIZE];
    for(int i = 0; i < ARRAY_SIZE; i++) {
        h_in[i] = bit_reverse(i, log2(ARRAY_SIZE));
    }
    int h_bins[BIN_COUNT];
    for(int i = 0; i < BIN_COUNT; i++) {
        h_bins[i] = 0;
    }

    // declare GPU memory pointers
    int * d_in;
    int * d_bins;

    // allocate GPU memory
    hipMalloc((void **) &d_in, ARRAY_BYTES);
    hipMalloc((void **) &d_bins, BIN_BYTES);

    // transfer the arrays to the GPU
    hipMemcpy(d_in, h_in, ARRAY_BYTES, hipMemcpyHostToDevice); 
    hipMemcpy(d_bins, h_bins, BIN_BYTES, hipMemcpyHostToDevice); 

    int whichKernel = 0;
    if (argc == 2) {
        whichKernel = atoi(argv[1]);
    }
        
    // launch the kernel
    switch(whichKernel) {
    case 0:
        printf("Running naive histo\n");
        naive_histo<<<ARRAY_SIZE / 64, 64>>>(d_bins, d_in, BIN_COUNT);
        break;
    case 1:
        printf("Running simple histo\n");
        simple_histo<<<ARRAY_SIZE / 64, 64>>>(d_bins, d_in, BIN_COUNT);
        break;
    default:
        fprintf(stderr, "error: ran no kernel\n");
        exit(EXIT_FAILURE);
    }

    // copy back the sum from GPU
    hipMemcpy(h_bins, d_bins, BIN_BYTES, hipMemcpyDeviceToHost);

    for(int i = 0; i < BIN_COUNT; i++) {
        printf("bin %d: count %d\n", i, h_bins[i]);
    }

    // free GPU memory allocation
    hipFree(d_in);
    hipFree(d_bins);
        
    return 0;
}
	.text
	.file	"histo.hip"
	.globl	_Z4log2i                        # -- Begin function _Z4log2i
	.type	_Z4log2i,@function
_Z4log2i:                               # @_Z4log2i
	.cfi_startproc
# %bb.0:
	xorl	%eax, %eax
	cmpl	$2, %edi
	jb	.LBB0_3
# %bb.1:                                # %.lr.ph.preheader
	xorl	%eax, %eax
.LBB0_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	sarl	%edi
	incl	%eax
	cmpl	$1, %edi
	ja	.LBB0_2
.LBB0_3:                                # %._crit_edge
	retq
.Lfunc_end0:
	.size	_Z4log2i, .Lfunc_end0-_Z4log2i
	.cfi_endproc
                                        # -- End function
	.globl	_Z11bit_reverseii               # -- Begin function _Z11bit_reverseii
	.type	_Z11bit_reverseii,@function
_Z11bit_reverseii:                      # @_Z11bit_reverseii
	.cfi_startproc
# %bb.0:
	testl	%esi, %esi
	jle	.LBB1_1
# %bb.3:                                # %.lr.ph.preheader
	decl	%esi
	xorl	%eax, %eax
	xorl	%edx, %edx
.LBB1_4:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	$1, %r8d
	movl	%edx, %ecx
	shll	%cl, %r8d
	andl	%edi, %r8d
	sarl	%cl, %r8d
	movl	%esi, %ecx
	shll	%cl, %r8d
	orl	%r8d, %eax
	incl	%edx
	addl	$-1, %esi
	jb	.LBB1_4
# %bb.2:                                # %._crit_edge
	retq
.LBB1_1:
	xorl	%eax, %eax
	retq
.Lfunc_end1:
	.size	_Z11bit_reverseii, .Lfunc_end1-_Z11bit_reverseii
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__naive_histoPiPKii # -- Begin function _Z26__device_stub__naive_histoPiPKii
	.type	_Z26__device_stub__naive_histoPiPKii,@function
_Z26__device_stub__naive_histoPiPKii:   # @_Z26__device_stub__naive_histoPiPKii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11naive_histoPiPKii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z26__device_stub__naive_histoPiPKii, .Lfunc_end2-_Z26__device_stub__naive_histoPiPKii
	.cfi_endproc
                                        # -- End function
	.globl	_Z27__device_stub__simple_histoPiPKii # -- Begin function _Z27__device_stub__simple_histoPiPKii
	.type	_Z27__device_stub__simple_histoPiPKii,@function
_Z27__device_stub__simple_histoPiPKii:  # @_Z27__device_stub__simple_histoPiPKii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12simple_histoPiPKii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z27__device_stub__simple_histoPiPKii, .Lfunc_end3-_Z27__device_stub__simple_histoPiPKii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$263712, %rsp                   # imm = 0x40620
	.cfi_def_cfa_offset 263760
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsi, %rbx
	movl	%edi, %ebp
	leaq	28(%rsp), %r14
	movq	%r14, %rdi
	callq	hipGetDeviceCount
	cmpl	$0, (%r14)
	je	.LBB4_1
# %bb.3:
	xorl	%edi, %edi
	callq	hipSetDevice
	leaq	96(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipGetDevicePropertiesR0600
	testl	%eax, %eax
	jne	.LBB4_5
# %bb.4:
	movl	$.L.str.1, %edi
	xorl	%esi, %esi
	xorl	%eax, %eax
	callq	printf
	leaq	96(%rsp), %rsi
	movl	360(%rsi), %ecx
	movl	364(%rsi), %r8d
	movl	288(%rsi), %edx
	movl	348(%rsi), %r9d
	movl	$.L.str.2, %edi
	xorl	%eax, %eax
	callq	printf
.LBB4_5:
	xorl	%esi, %esi
.LBB4_6:                                # %.lr.ph.i.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB4_7 Depth 2
	movl	$15, %eax
	xorl	%edi, %edi
	xorl	%edx, %edx
.LBB4_7:                                # %.lr.ph.i27
                                        #   Parent Loop BB4_6 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movl	$1, %r8d
	movl	%edx, %ecx
	shll	%cl, %r8d
	andl	%esi, %r8d
	shrl	%cl, %r8d
	movl	%eax, %ecx
	shll	%cl, %r8d
	orl	%r8d, %edi
	incl	%edx
	decl	%eax
	cmpl	$16, %edx
	jne	.LBB4_7
# %bb.8:                                # %_Z11bit_reverseii.exit
                                        #   in Loop: Header=BB4_6 Depth=1
	movl	%edi, 1568(%rsp,%rsi,4)
	incq	%rsi
	cmpq	$65536, %rsi                    # imm = 0x10000
	jne	.LBB4_6
# %bb.9:
	xorps	%xmm0, %xmm0
	leaq	32(%rsp), %r14
	movaps	%xmm0, 48(%r14)
	movaps	%xmm0, 32(%r14)
	movaps	%xmm0, 16(%r14)
	movaps	%xmm0, (%r14)
	leaq	16(%rsp), %r15
	movl	$262144, %esi                   # imm = 0x40000
	movq	%r15, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %r12
	movl	$64, %esi
	movq	%r12, %rdi
	callq	hipMalloc
	movq	(%r15), %rdi
	leaq	1568(%rsp), %rsi
	movl	$262144, %edx                   # imm = 0x40000
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r12), %rdi
	movl	$64, %edx
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	cmpl	$2, %ebp
	jne	.LBB4_12
# %bb.10:
	movq	8(%rbx), %rdi
	callq	atoi
	cmpl	$1, %eax
	je	.LBB4_14
# %bb.11:
	testl	%eax, %eax
	jne	.LBB4_19
.LBB4_12:                               # %.thread
	movl	$.Lstr.1, %edi
	callq	puts@PLT
	movabsq	$4294967360, %rdx               # imm = 0x100000040
	leaq	960(%rdx), %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_16
# %bb.13:
	movq	8(%rsp), %rdi
	movq	16(%rsp), %rsi
	movl	$16, %edx
	callq	_Z26__device_stub__naive_histoPiPKii
	jmp	.LBB4_16
.LBB4_14:
	movl	$.Lstr, %edi
	callq	puts@PLT
	movabsq	$4294967360, %rdx               # imm = 0x100000040
	leaq	960(%rdx), %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_16
# %bb.15:
	movq	8(%rsp), %rdi
	movq	16(%rsp), %rsi
	movl	$16, %edx
	callq	_Z27__device_stub__simple_histoPiPKii
.LBB4_16:
	movq	8(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movl	$64, %edx
	movl	$2, %ecx
	callq	hipMemcpy
	xorl	%ebx, %ebx
.LBB4_17:                               # =>This Inner Loop Header: Depth=1
	movl	32(%rsp,%rbx,4), %edx
	movl	$.L.str.6, %edi
	movl	%ebx, %esi
	xorl	%eax, %eax
	callq	printf
	incq	%rbx
	cmpq	$16, %rbx
	jne	.LBB4_17
# %bb.18:
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$263712, %rsp                   # imm = 0x40620
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB4_1:
	.cfi_def_cfa_offset 263760
	movq	stderr(%rip), %rcx
	movl	$.L.str, %edi
	movl	$35, %esi
.LBB4_2:
	movl	$1, %edx
	callq	fwrite@PLT
	movl	$1, %edi
	callq	exit
.LBB4_19:
	movq	stderr(%rip), %rcx
	movl	$.L.str.5, %edi
	movl	$21, %esi
	jmp	.LBB4_2
.Lfunc_end4:
	.size	main, .Lfunc_end4-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11naive_histoPiPKii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12simple_histoPiPKii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z11naive_histoPiPKii,@object   # @_Z11naive_histoPiPKii
	.section	.rodata,"a",@progbits
	.globl	_Z11naive_histoPiPKii
	.p2align	3, 0x0
_Z11naive_histoPiPKii:
	.quad	_Z26__device_stub__naive_histoPiPKii
	.size	_Z11naive_histoPiPKii, 8

	.type	_Z12simple_histoPiPKii,@object  # @_Z12simple_histoPiPKii
	.globl	_Z12simple_histoPiPKii
	.p2align	3, 0x0
_Z12simple_histoPiPKii:
	.quad	_Z27__device_stub__simple_histoPiPKii
	.size	_Z12simple_histoPiPKii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"error: no devices supporting CUDA.\n"
	.size	.L.str, 36

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Using device %d:\n"
	.size	.L.str.1, 18

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"%s; global mem: %dB; compute v%d.%d; clock: %d kHz\n"
	.size	.L.str.2, 52

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"error: ran no kernel\n"
	.size	.L.str.5, 22

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"bin %d: count %d\n"
	.size	.L.str.6, 18

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z11naive_histoPiPKii"
	.size	.L__unnamed_1, 22

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z12simple_histoPiPKii"
	.size	.L__unnamed_2, 23

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Running simple histo"
	.size	.Lstr, 21

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"Running naive histo"
	.size	.Lstr.1, 20

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z26__device_stub__naive_histoPiPKii
	.addrsig_sym _Z27__device_stub__simple_histoPiPKii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z11naive_histoPiPKii
	.addrsig_sym _Z12simple_histoPiPKii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z11naive_histoPiPKii   ; -- Begin function _Z11naive_histoPiPKii
	.globl	_Z11naive_histoPiPKii
	.p2align	8
	.type	_Z11naive_histoPiPKii,@function
_Z11naive_histoPiPKii:                  ; @_Z11naive_histoPiPKii
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x24
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s0, s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_ashr_i32 s1, s0, 31
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_add_i32 s0, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s0, s0, s1
	s_sub_i32 s1, 0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	global_load_b32 v0, v[0:1], off
	v_cvt_f32_u32_e32 v1, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v3, 31, v0
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v1, 0x4f7ffffe, v1 :: v_dual_add_nc_u32 v0, v0, v3
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v0, v0, v3
	v_mul_lo_u32 v2, s1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v2, v1, v2
	v_add_nc_u32_e32 v1, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v1, v0, v1
	v_mul_lo_u32 v1, v1, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v0, v1
	v_subrev_nc_u32_e32 v1, s0, v0
	v_cmp_le_u32_e32 vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v1, vcc_lo
	v_subrev_nc_u32_e32 v1, s0, v0
	v_cmp_le_u32_e32 vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v1, vcc_lo
	v_xor_b32_e32 v0, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v0, v3
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	global_load_b32 v2, v[0:1], off
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v2, 1, v2
	global_store_b32 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11naive_histoPiPKii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z11naive_histoPiPKii, .Lfunc_end0-_Z11naive_histoPiPKii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 320
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z12simple_histoPiPKii  ; -- Begin function _Z12simple_histoPiPKii
	.globl	_Z12simple_histoPiPKii
	.p2align	8
	.type	_Z12simple_histoPiPKii,@function
_Z12simple_histoPiPKii:                 ; @_Z12simple_histoPiPKii
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x24
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s0, s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_ashr_i32 s1, s0, 31
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_add_i32 s0, s0, s1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b32 s0, s0, s1
	s_sub_i32 s1, 0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	global_load_b32 v0, v[0:1], off
	v_cvt_f32_u32_e32 v1, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v3, 31, v0
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v1, 0x4f7ffffe, v1 :: v_dual_add_nc_u32 v0, v0, v3
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v0, v0, v3
	v_mul_lo_u32 v2, s1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v2, v1, v2
	v_dual_mov_b32 v2, 1 :: v_dual_add_nc_u32 v1, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v1, v0, v1
	v_mul_lo_u32 v1, v1, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v0, v1
	v_subrev_nc_u32_e32 v1, s0, v0
	v_cmp_le_u32_e32 vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v1, vcc_lo
	v_subrev_nc_u32_e32 v1, s0, v0
	v_cmp_le_u32_e32 vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v1, vcc_lo
	v_xor_b32_e32 v0, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v0, v3
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	global_atomic_add_u32 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12simple_histoPiPKii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z12simple_histoPiPKii, .Lfunc_end1-_Z12simple_histoPiPKii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 308
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11naive_histoPiPKii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z11naive_histoPiPKii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     4
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12simple_histoPiPKii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z12simple_histoPiPKii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     4
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
