#include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <assert.h>
#include <vector>
using namespace std;

const int INF = 10000000;
const int V = 10010;
const int MAX_THREAD_DIM2 = 32;
void input(char *inFileName, int B);
void output(char *outFileName);

void block_FW_2GPU(int B);
int ceil(int a, int b);
void calAsync(int gpuId, int B, int Round, int block_start_x, int block_start_y, int block_width, int block_height);

int realn;
int n, m;	// Number of vertices, edges
int* Dist;	// n * n, on host
int* dDist[2]; // n * n, on device

int streamSize[2];
vector<cudaStream_t> streams[2];

int getGPUId ()
{
	int gpuId;
	cudaGetDevice(&gpuId);
	return gpuId;
}
cudaStream_t getIdleStream (int gpuId)
{
	cudaSetDevice(gpuId);
	if(streams[gpuId].size() == streamSize[gpuId])
	{
		cudaStream_t stm;
		cudaStreamCreate(&stm);
		streams[gpuId].push_back(stm);
		streamSize[gpuId]++;
		return stm;
	}
	else
		return streams[gpuId][streamSize[gpuId]++];
}
void syncAllStreams ()
{
	cudaThreadSynchronize();
	streamSize[0] = 0;
	streamSize[1] = 0;
}




void blockCopyAsync (int gpuId, int* dst, const int* src, cudaMemcpyKind kind, cudaStream_t stream, int B, int bi0, int bi1, int bj0, int bj1)
{
	cudaSetDevice(gpuId);
	for(int i = bi0 * B; i < bi1 * B; ++i)
	{
		int offset = i * n + bj0 * B;
		int size = (bj1 - bj0) * B * sizeof(int);
		cudaMemcpyAsync(dst + offset, src + offset, size, kind, stream);
	}
}

int main(int argc, char* argv[])
{
	int B = atoi(argv[3]);
	input(argv[1], B);
	block_FW_2GPU(B);
	output(argv[2]);
	return 0;
}

void input(char *inFileName, int B)
{
	FILE *infile = fopen(inFileName, "r");
	fscanf(infile, "%d %d", &realn, &m);
	n = ceil(realn, B) * B;
	cudaMallocManaged(&Dist, n * n * sizeof(int));

	for (int i = 0, k = 0; i < n; ++i) {
		for (int j = 0; j < n; ++j, ++k) {
			if (i == j)	Dist[k] = 0;
			else		Dist[k] = INF;
		}
	}

	while (--m >= 0) {
		int a, b, v;
		fscanf(infile, "%d %d %d", &a, &b, &v);
		--a, --b;
		Dist[a * n + b] = v;
	}
}

void output(char *outFileName)
{
	FILE *outfile = fopen(outFileName, "w");
	for (int i = 0; i < realn; ++i) {
		for (int j = 0; j < realn; ++j) {
			int d = Dist[i * n + j];
			if (d >= INF)	fprintf(outfile, "INF ");
			else			fprintf(outfile, "%d ", d);
		}
		fprintf(outfile, "\n");
	}		
	cudaFree(Dist);
}

void print ()
{
	for (int i = 0; i < realn; ++i) {
		for (int j = 0; j < realn; ++j) {
			int d = Dist[i * n + j];
			if (d >= INF)	fprintf(stderr, "INF ");
			else			fprintf(stderr, "%d ", d);
		}
		fprintf(stderr, "\n");
	}	
	fprintf(stderr, "\n");
}

int ceil(int a, int b)
{
	return (a + b -1)/b;
}

void block_FW_2GPU(int B)
{
	int round = ceil(n, B);
	for (int r = 0; r < round; ++r) {
		/* Phase 1*/
		fprintf(stderr, "Round: %d\n", r);
		calAsync(0, B,	r,	r,	r,	1,	1);
		syncAllStreams();

		/* Phase 2*/
		calAsync(0, B, r,     r,     0,             r,             1); // L 0
		calAsync(0, B, r,     r,  r +1,  round - r -1,             1); // R 0
		calAsync(1, B, r,     0,     r,             1,             r); // U 1
		calAsync(1, B, r,  r +1,     r,             1,  round - r -1); // D 1
		syncAllStreams();

		/* Phase 3*/
		calAsync(0, B, r,     0,     0,            r,             r); // <^
		calAsync(1, B, r,     0,  r +1,  round -r -1,             r); // ^>
		calAsync(1, B, r,  r +1,     0,            r,  round - r -1); // <v
		calAsync(0, B, r,  r +1,  r +1,  round -r -1,  round - r -1); // v>
		syncAllStreams();
	}
}


__global__
void Update (int k, int i0, int j0, int i1, int j1, int* dDist, int n)
{
	#define D(i,j) (dDist[(i) * n + (j)])
	int i = blockDim.x * blockIdx.x + threadIdx.x + i0;
    int j = blockDim.y * blockIdx.y + threadIdx.y + j0;
	if(i >= i1 || j >= j1)
		return;
	int Dik = D(i, k);
	int Dkj = D(k, j);
	int D1 = Dik + Dkj;
	if (D1 < D(i, j))
		D(i, j) = D1;
}

__global__
void UpdateIndependent (int k0, int k1, int i0, int j0, int i1, int j1, int* dDist, int n)
{
	#define D(i,j) (dDist[(i) * n + (j)])
	int tx = threadIdx.x;
	int ty = threadIdx.y;
	int di = blockDim.x * blockIdx.x + tx;
    int dj = blockDim.y * blockIdx.y + ty;
	int i = i0 + di;
	int j = j0 + dj;
	bool valid = i < i1 && j < j1;
	__shared__ int Si[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
	__shared__ int Sj[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
	const int cacheSize = MAX_THREAD_DIM2;
	int Dij = valid? D(i, j): 0;
	int dkmod = 0;
	for(int k = k0; k < k1; ++k)
	{
		if(dkmod == 0)
		{
			__syncthreads();
			if(i < i1 && k+ty < k1)
			Si[ty][tx] = D(i, k+ty);
			if(j < j1 && k+tx < k1)
			Sj[tx][ty] = D(k+tx, j);
			__syncthreads();		
		}
		if(valid)
		{
			// assert(Si[tx][dkmod] == D(i,k));
			// assert(Sj[dkmod][ty] == D(k,j));			
			
			// int Dik = D(i, k);
			// int Dkj = D(k, j);
			int Dik = Si[dkmod][tx];
			int Dkj = Sj[dkmod][ty];
			int D1 = Dik + Dkj;
			if (D1 < Dij)
				Dij = D1;
		}
		dkmod = (dkmod + 1) % cacheSize;
	}
	if(valid)
		D(i, j) = Dij;
}

void calAsync(int gpuId, int B, int Round, int block_start_x, int block_start_y, int block_width, int block_height)
{
	cudaSetDevice(gpuId);

	int block_end_x = block_start_x + block_height;
	int block_end_y = block_start_y + block_width;

	for (int b_i =  block_start_x; b_i < block_end_x; ++b_i) {
		for (int b_j = block_start_y; b_j < block_end_y; ++b_j) {
			// To calculate B*B elements in the block (b_i, b_j)
			// For each block, it need to compute B times
			// for (int k = Round * B; k < (Round +1) * B && k < n; ++k) {
				// To calculate original index of elements in the block (b_i, b_j)
				// For instance, original index of (0,0) in block (1,2) is (2,5) for V=6,B=2
				int i0 = b_i * B;
				int i1 = min((b_i +1) * B, n);
				int j0 = b_j * B; 
				int j1 = min((b_j +1) * B, n);
				int k0 = Round * B;
				int k1 = min((Round +1) * B, n);
				bool iDepends = i0 == k0;
				bool jDepends = j0 == k0;

				int threadDim = MAX_THREAD_DIM2;//std::min(B, MAX_THREAD_DIM2);
				int blockDim = (B + MAX_THREAD_DIM2 - 1) / MAX_THREAD_DIM2;
				dim3 grid(blockDim, blockDim), block(threadDim, threadDim);
				cudaStream_t stm = getIdleStream(gpuId);
				if(iDepends || jDepends)
				{
					for(int k=k0; k<k1; ++k)
						Update<<<grid, block, 0, stm>>>(k, i0, j0, i1, j1, Dist, n);
				}
				else
					UpdateIndependent<<<grid, block, 0, stm>>>(k0, k1, i0, j0, i1, j1, Dist, n);

				// for (int i = i0; i < i1; ++i) {
				// 	for (int j = j0; j < j1; ++j) {
				// 		if (Dist[i][k] + Dist[k][j] < Dist[i][j])
				// 			Dist[i][j] = Dist[i][k] + Dist[k][j];
				// 	}
				// }
			// }
		}
	}
}



	.file	"tmpxft_0034765f_00000000-6_HW4_x1054037_2GPU_Unified_bug.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB4021:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE4021:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	__tcf_0, @function
__tcf_0:
.LFB4736:
	.cfi_startproc
	endbr64
	movq	24+streams(%rip), %rdi
	testq	%rdi, %rdi
	je	.L9
	pushq	%rcx
	.cfi_def_cfa_offset 16
	movq	40+streams(%rip), %rsi
	subq	%rdi, %rsi
	call	_ZdlPvm@PLT
	movq	streams(%rip), %rdi
	testq	%rdi, %rdi
	je	.L2
	movq	16+streams(%rip), %rsi
	popq	%rdx
	.cfi_remember_state
	.cfi_def_cfa_offset 8
	subq	%rdi, %rsi
	jmp	.L14
.L2:
	.cfi_restore_state
	popq	%rax
	.cfi_def_cfa_offset 8
	ret
.L9:
	movq	streams(%rip), %rdi
	testq	%rdi, %rdi
	je	.L11
	movq	16+streams(%rip), %rsi
	subq	%rdi, %rsi
.L14:
	jmp	_ZdlPvm@PLT
.L11:
	ret
	.cfi_endproc
.LFE4736:
	.size	__tcf_0, .-__tcf_0
	.globl	_Z8getGPUIdv
	.type	_Z8getGPUIdv, @function
_Z8getGPUIdv:
.LFB4008:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movq	%fs:40, %rax
	movq	%rax, 8(%rsp)
	xorl	%eax, %eax
	leaq	4(%rsp), %rdi
	call	cudaGetDevice@PLT
	movl	4(%rsp), %eax
	movq	8(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L17
	call	__stack_chk_fail@PLT
.L17:
	addq	$24, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4008:
	.size	_Z8getGPUIdv, .-_Z8getGPUIdv
	.globl	_Z14syncAllStreamsv
	.type	_Z14syncAllStreamsv, @function
_Z14syncAllStreamsv:
.LFB4010:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	call	cudaThreadSynchronize@PLT
	xorl	%edx, %edx
	movq	%rdx, streamSize(%rip)
	popq	%rcx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4010:
	.size	_Z14syncAllStreamsv, .-_Z14syncAllStreamsv
	.globl	_Z14blockCopyAsynciPiPKi14cudaMemcpyKindP11CUstream_stiiiii
	.type	_Z14blockCopyAsynciPiPKi14cudaMemcpyKindP11CUstream_stiiiii, @function
_Z14blockCopyAsynciPiPKi14cudaMemcpyKindP11CUstream_stiiiii:
.LFB4011:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rdx, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rsi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%r9d, %ebx
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	movl	%ecx, 4(%rsp)
	movq	%r8, 8(%rsp)
	call	cudaSetDevice@PLT
	movl	80(%rsp), %r13d
	movl	88(%rsp), %r15d
	movl	96(%rsp), %r14d
	movl	104(%rsp), %eax
	subl	96(%rsp), %eax
	imull	%ebx, %r13d
	imull	%ebx, %r15d
	imull	%ebx, %r14d
	imull	%eax, %ebx
	sall	$2, %ebx
	movslq	%ebx, %rbx
.L22:
	cmpl	%r13d, %r15d
	jle	.L25
	movl	n(%rip), %edi
	movq	8(%rsp), %r8
	movq	%rbx, %rdx
	movl	4(%rsp), %ecx
	imull	%r13d, %edi
	incl	%r13d
	addl	%r14d, %edi
	movslq	%edi, %rdi
	salq	$2, %rdi
	leaq	(%r12,%rdi), %rsi
	addq	%rbp, %rdi
	call	cudaMemcpyAsync@PLT
	jmp	.L22
.L25:
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4011:
	.size	_Z14blockCopyAsynciPiPKi14cudaMemcpyKindP11CUstream_stiiiii, .-_Z14blockCopyAsynciPiPKi14cudaMemcpyKindP11CUstream_stiiiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"r"
.LC1:
	.string	"%d %d"
.LC2:
	.string	"%d %d %d"
	.text
	.globl	_Z5inputPci
	.type	_Z5inputPci, @function
_Z5inputPci:
.LFB4013:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movl	%esi, %ebp
	leaq	.LC0(%rip), %rsi
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	subq	$40, %rsp
	.cfi_def_cfa_offset 64
	movq	%fs:40, %rax
	movq	%rax, 24(%rsp)
	xorl	%eax, %eax
	call	fopen@PLT
	leaq	m(%rip), %rcx
	leaq	realn(%rip), %rdx
	movq	%rax, %rdi
	leaq	.LC1(%rip), %rsi
	movq	%rax, %rbx
	xorl	%eax, %eax
	call	__isoc23_fscanf@PLT
	movl	realn(%rip), %esi
	leaq	Dist(%rip), %rdi
	addl	%ebp, %esi
	decl	%esi
	movl	%esi, %eax
	cltd
	idivl	%ebp
	subl	%edx, %esi
	movl	$1, %edx
	movl	%esi, n(%rip)
	imull	%esi, %esi
	movslq	%esi, %rsi
	salq	$2, %rsi
	call	cudaMallocManaged@PLT
	movq	Dist(%rip), %rsi
	xorl	%eax, %eax
	xorl	%ecx, %ecx
	xorl	%edi, %edi
	movl	$10000000, %r8d
.L27:
	cmpl	%ecx, n(%rip)
	jg	.L36
	leaq	.LC2(%rip), %rbp
	jmp	.L30
.L36:
	cltq
	xorl	%edx, %edx
.L31:
	cmpl	%edx, n(%rip)
	jle	.L38
	cmpl	%edx, %ecx
	movl	%r8d, %r9d
	cmove	%edi, %r9d
	incl	%edx
	movl	%r9d, (%rsi,%rax,4)
	incq	%rax
	jmp	.L31
.L38:
	incl	%ecx
	jmp	.L27
.L30:
	decl	m(%rip)
	js	.L39
	leaq	16(%rsp), %rcx
	leaq	12(%rsp), %rdx
	movq	%rbp, %rsi
	movq	%rbx, %rdi
	leaq	20(%rsp), %r8
	xorl	%eax, %eax
	call	__isoc23_fscanf@PLT
	movl	12(%rsp), %eax
	movl	16(%rsp), %edx
	movl	20(%rsp), %ecx
	decl	%eax
	imull	n(%rip), %eax
	leal	-1(%rax,%rdx), %eax
	movq	Dist(%rip), %rdx
	cltq
	movl	%ecx, (%rdx,%rax,4)
	jmp	.L30
.L39:
	movq	24(%rsp), %rax
	subq	%fs:40, %rax
	je	.L33
	call	__stack_chk_fail@PLT
.L33:
	addq	$40, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4013:
	.size	_Z5inputPci, .-_Z5inputPci
	.section	.rodata.str1.1
.LC3:
	.string	"w"
.LC4:
	.string	"INF "
.LC5:
	.string	"%d "
.LC6:
	.string	"\n"
	.text
	.globl	_Z6outputPc
	.type	_Z6outputPc, @function
_Z6outputPc:
.LFB4014:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	leaq	.LC3(%rip), %rsi
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	leaq	.LC5(%rip), %r12
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	xorl	%ebp, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	pushq	%rdx
	.cfi_def_cfa_offset 48
	call	fopen@PLT
	movq	%rax, %rbx
.L41:
	cmpl	%ebp, realn(%rip)
	jle	.L48
	xorl	%r13d, %r13d
.L45:
	cmpl	%r13d, realn(%rip)
	jle	.L49
	movl	n(%rip), %eax
	movq	Dist(%rip), %rdx
	imull	%ebp, %eax
	addl	%r13d, %eax
	cltq
	movl	(%rdx,%rax,4), %ecx
	cmpl	$9999999, %ecx
	jle	.L42
	leaq	.LC4(%rip), %rdx
	movl	$2, %esi
	movq	%rbx, %rdi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	jmp	.L43
.L42:
	movq	%r12, %rdx
	movl	$2, %esi
	movq	%rbx, %rdi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
.L43:
	incl	%r13d
	jmp	.L45
.L49:
	leaq	.LC6(%rip), %rdx
	movl	$2, %esi
	xorl	%eax, %eax
	incl	%ebp
	movq	%rbx, %rdi
	call	__fprintf_chk@PLT
	jmp	.L41
.L48:
	movq	Dist(%rip), %rdi
	popq	%rax
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	cudaFree@PLT
	.cfi_endproc
.LFE4014:
	.size	_Z6outputPc, .-_Z6outputPc
	.globl	_Z5printv
	.type	_Z5printv, @function
_Z5printv:
.LFB4015:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	leaq	.LC5(%rip), %r12
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	xorl	%ebx, %ebx
.L51:
	cmpl	%ebx, realn(%rip)
	jle	.L58
	xorl	%ebp, %ebp
.L55:
	cmpl	%ebp, realn(%rip)
	movq	stderr(%rip), %rdi
	jle	.L59
	movl	n(%rip), %eax
	movq	Dist(%rip), %rdx
	imull	%ebx, %eax
	addl	%ebp, %eax
	cltq
	movl	(%rdx,%rax,4), %ecx
	cmpl	$9999999, %ecx
	jle	.L52
	leaq	.LC4(%rip), %rdx
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	jmp	.L53
.L52:
	movq	%r12, %rdx
	movl	$2, %esi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
.L53:
	incl	%ebp
	jmp	.L55
.L59:
	leaq	.LC6(%rip), %rdx
	movl	$2, %esi
	xorl	%eax, %eax
	incl	%ebx
	call	__fprintf_chk@PLT
	jmp	.L51
.L58:
	movq	stderr(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 24
	movl	$2, %esi
	xorl	%eax, %eax
	popq	%rbp
	.cfi_def_cfa_offset 16
	leaq	.LC6(%rip), %rdx
	popq	%r12
	.cfi_def_cfa_offset 8
	jmp	__fprintf_chk@PLT
	.cfi_endproc
.LFE4015:
	.size	_Z5printv, .-_Z5printv
	.globl	_Z4ceilii
	.type	_Z4ceilii, @function
_Z4ceilii:
.LFB4016:
	.cfi_startproc
	endbr64
	leal	-1(%rsi,%rdi), %eax
	cltd
	idivl	%esi
	ret
	.cfi_endproc
.LFE4016:
	.size	_Z4ceilii, .-_Z4ceilii
	.globl	_Z31__device_stub__Z6UpdateiiiiiPiiiiiiiPii
	.type	_Z31__device_stub__Z6UpdateiiiiiPiiiiiiiPii, @function
_Z31__device_stub__Z6UpdateiiiiiPiiiiiiiPii:
.LFB4043:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movl	%edi, 28(%rsp)
	leaq	48(%rsp), %rdi
	movl	%esi, 24(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 20(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 16(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movq	%r9, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 128(%rsp)
	movq	%rsp, %rax
	movq	%rax, 136(%rsp)
	leaq	176(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L61
	pushq	40(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z6UpdateiiiiiPii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 192
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L61:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L63
	call	__stack_chk_fail@PLT
.L63:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4043:
	.size	_Z31__device_stub__Z6UpdateiiiiiPiiiiiiiPii, .-_Z31__device_stub__Z6UpdateiiiiiPiiiiiiiPii
	.globl	_Z6UpdateiiiiiPii
	.type	_Z6UpdateiiiiiPii, @function
_Z6UpdateiiiiiPii:
.LFB4044:
	.cfi_startproc
	endbr64
	jmp	_Z31__device_stub__Z6UpdateiiiiiPiiiiiiiPii
	.cfi_endproc
.LFE4044:
	.size	_Z6UpdateiiiiiPii, .-_Z6UpdateiiiiiPii
	.globl	_Z44__device_stub__Z17UpdateIndependentiiiiiiPiiiiiiiiPii
	.type	_Z44__device_stub__Z17UpdateIndependentiiiiiiPiiiiiiiiPii, @function
_Z44__device_stub__Z17UpdateIndependentiiiiiiPiiiiiiiiPii:
.LFB4045:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	192(%rsp), %rax
	movl	%edi, 28(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 24(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 20(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 16(%rsp)
	leaq	48(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movl	%r9d, 8(%rsp)
	movq	%rax, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	movq	%rsp, %rax
	movq	%rax, 152(%rsp)
	leaq	200(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L66
	pushq	48(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z17UpdateIndependentiiiiiiPii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 208
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L66:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L68
	call	__stack_chk_fail@PLT
.L68:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4045:
	.size	_Z44__device_stub__Z17UpdateIndependentiiiiiiPiiiiiiiiPii, .-_Z44__device_stub__Z17UpdateIndependentiiiiiiPiiiiiiiiPii
	.globl	_Z17UpdateIndependentiiiiiiPii
	.type	_Z17UpdateIndependentiiiiiiPii, @function
_Z17UpdateIndependentiiiiiiPii:
.LFB4046:
	.cfi_startproc
	endbr64
	jmp	_Z44__device_stub__Z17UpdateIndependentiiiiiiPiiiiiiiiPii
	.cfi_endproc
.LFE4046:
	.size	_Z17UpdateIndependentiiiiiiPii, .-_Z17UpdateIndependentiiiiiiPii
	.section	.rodata.str1.1
.LC7:
	.string	"_Z17UpdateIndependentiiiiiiPii"
.LC8:
	.string	"_Z6UpdateiiiiiPii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB4048:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z17UpdateIndependentiiiiiiPii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC8(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z6UpdateiiiiiPii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE4048:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.rodata._ZNSt6vectorIP11CUstream_stSaIS1_EE17_M_realloc_insertIJRKS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_.str1.1,"aMS",@progbits,1
.LC9:
	.string	"vector::_M_realloc_insert"
	.section	.text._ZNSt6vectorIP11CUstream_stSaIS1_EE17_M_realloc_insertIJRKS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_,"axG",@progbits,_ZNSt6vectorIP11CUstream_stSaIS1_EE17_M_realloc_insertIJRKS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_,comdat
	.align 2
	.weak	_ZNSt6vectorIP11CUstream_stSaIS1_EE17_M_realloc_insertIJRKS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_
	.type	_ZNSt6vectorIP11CUstream_stSaIS1_EE17_M_realloc_insertIJRKS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_, @function
_ZNSt6vectorIP11CUstream_stSaIS1_EE17_M_realloc_insertIJRKS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_:
.LFB4519:
	.cfi_startproc
	endbr64
	movabsq	$1152921504606846975, %rcx
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	movq	8(%rdi), %rax
	movq	(%rdi), %r14
	movq	%rax, %rbx
	movq	%rax, (%rsp)
	subq	%r14, %rbx
	sarq	$3, %rbx
	cmpq	%rcx, %rbx
	jne	.L74
	leaq	.LC9(%rip), %rdi
	call	_ZSt20__throw_length_errorPKc@PLT
.L74:
	cmpq	%r14, (%rsp)
	movl	$1, %eax
	movq	%rsi, %r15
	movq	%rdi, %r13
	cmovne	%rbx, %rax
	movq	%rsi, %rbp
	addq	%rax, %rbx
	setc	%al
	subq	%r14, %r15
	movzbl	%al, %eax
	testq	%rax, %rax
	jne	.L84
	xorl	%r12d, %r12d
	testq	%rbx, %rbx
	je	.L79
	movabsq	$1152921504606846975, %rax
	cmpq	%rax, %rbx
	cmova	%rax, %rbx
	jmp	.L78
.L84:
	movq	%rcx, %rbx
.L78:
	leaq	0(,%rbx,8), %rdi
	movq	%rdx, 8(%rsp)
	call	_Znwm@PLT
	movq	8(%rsp), %rdx
	movq	%rax, %r12
.L79:
	movq	(%rdx), %rax
	movq	%rax, (%r12,%r15)
	testq	%r15, %r15
	jle	.L80
	movq	%r15, %rdx
	movq	%r14, %rsi
	movq	%r12, %rdi
	call	memmove@PLT
.L80:
	movq	(%rsp), %rax
	leaq	8(%r12,%r15), %rdx
	subq	%rbp, %rax
	testq	%rax, %rax
	jle	.L81
	movq	%rdx, %rdi
	movq	%rbp, %rsi
	movq	%rax, %rcx
	rep movsb
.L81:
	leaq	(%rdx,%rax), %rbp
	testq	%r14, %r14
	je	.L82
	movq	16(%r13), %rsi
	movq	%r14, %rdi
	subq	%r14, %rsi
	call	_ZdlPvm@PLT
.L82:
	leaq	(%r12,%rbx,8), %rax
	movq	%r12, 0(%r13)
	movq	%rbp, 8(%r13)
	movq	%rax, 16(%r13)
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4519:
	.size	_ZNSt6vectorIP11CUstream_stSaIS1_EE17_M_realloc_insertIJRKS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_, .-_ZNSt6vectorIP11CUstream_stSaIS1_EE17_M_realloc_insertIJRKS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_
	.text
	.globl	_Z13getIdleStreami
	.type	_Z13getIdleStreami, @function
_Z13getIdleStreami:
.LFB4009:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	leaq	streamSize(%rip), %r12
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	leaq	streams(%rip), %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movslq	%edi, %rbx
	movl	%ebx, %edi
	subq	$24, %rsp
	.cfi_def_cfa_offset 64
	movq	%fs:40, %rax
	movq	%rax, 8(%rsp)
	xorl	%eax, %eax
	call	cudaSetDevice@PLT
	imulq	$24, %rbx, %rax
	movslq	(%r12,%rbx,4), %rsi
	addq	%rax, %rbp
	movq	0(%rbp), %rcx
	movq	8(%rbp), %rax
	subq	%rcx, %rax
	sarq	$3, %rax
	cmpq	%rax, %rsi
	jne	.L92
	movq	%rsp, %r13
	movq	%r13, %rdi
	call	cudaStreamCreate@PLT
	movq	8(%rbp), %rsi
	cmpq	16(%rbp), %rsi
	je	.L93
	movq	(%rsp), %rax
	addq	$8, %rsi
	movq	%rax, -8(%rsi)
	movq	%rsi, 8(%rbp)
	jmp	.L94
.L93:
	movq	%r13, %rdx
	movq	%rbp, %rdi
	call	_ZNSt6vectorIP11CUstream_stSaIS1_EE17_M_realloc_insertIJRKS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_
.L94:
	incl	(%r12,%rbx,4)
	movq	(%rsp), %rax
	jmp	.L91
.L92:
	movq	%rsi, %rdx
	movq	(%rcx,%rsi,8), %rax
	incl	%edx
	movl	%edx, (%r12,%rbx,4)
.L91:
	movq	8(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L96
	call	__stack_chk_fail@PLT
.L96:
	addq	$24, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4009:
	.size	_Z13getIdleStreami, .-_Z13getIdleStreami
	.globl	_Z8calAsynciiiiiii
	.type	_Z8calAsynciiiiiii, @function
_Z8calAsynciiiiiii:
.LFB4018:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movl	%r8d, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	%r9d, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%ecx, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%esi, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%edx, %ebx
	imull	%ebp, %ebx
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	movl	%edi, 40(%rsp)
	call	cudaSetDevice@PLT
	movl	160(%rsp), %eax
	movl	$32, %ecx
	addl	%r12d, %eax
	movl	%eax, 48(%rsp)
	leal	(%r14,%r13), %eax
	movl	%r12d, %r13d
	movl	%eax, 52(%rsp)
	imull	%ebp, %r13d
	leal	0(%rbp,%rbx), %eax
	movl	%eax, 12(%rsp)
	leal	31(%rbp), %eax
	cltd
	idivl	%ecx
	movl	%eax, 44(%rsp)
	movl	%r14d, %eax
	imull	%ebp, %eax
	movl	%eax, 60(%rsp)
.L99:
	movl	48(%rsp), %eax
	cmpl	%eax, %r12d
	jge	.L98
	movl	60(%rsp), %eax
	movl	%r14d, 16(%rsp)
	movl	%r13d, 4(%rsp)
	addl	%ebp, %r13d
	cmpl	%ebx, 4(%rsp)
	movl	%eax, (%rsp)
	sete	59(%rsp)
.L108:
	movl	52(%rsp), %esi
	cmpl	%esi, 16(%rsp)
	jge	.L112
	movl	n(%rip), %eax
	movl	%r13d, %esi
	movl	(%rsp), %edx
	movl	$1, 80(%rsp)
	movl	40(%rsp), %edi
	movl	$1, 92(%rsp)
	cmpl	%r13d, %eax
	movl	%edx, 8(%rsp)
	movl	12(%rsp), %edx
	cmovle	%eax, %esi
	addl	%ebp, (%rsp)
	incl	16(%rsp)
	cmpl	%eax, (%rsp)
	movl	%esi, 20(%rsp)
	movl	(%rsp), %esi
	cmovg	%eax, %esi
	cmpl	%edx, %eax
	cmovg	%edx, %eax
	cmpl	%ebx, 8(%rsp)
	sete	%r15b
	movl	%esi, 24(%rsp)
	movl	%eax, 28(%rsp)
	movl	44(%rsp), %eax
	movl	%eax, 72(%rsp)
	movl	%eax, 76(%rsp)
	movabsq	$137438953504, %rax
	movq	%rax, 84(%rsp)
	call	_Z13getIdleStreami
	cmpb	$0, 59(%rsp)
	movq	%rax, 32(%rsp)
	jne	.L109
	testb	%r15b, %r15b
	je	.L110
.L109:
	movl	%ebx, %r15d
.L100:
	movl	28(%rsp), %eax
	cmpl	%eax, %r15d
	jge	.L108
	movl	92(%rsp), %ecx
	movq	32(%rsp), %r9
	xorl	%r8d, %r8d
	movq	84(%rsp), %rdx
	movq	72(%rsp), %rdi
	movl	80(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L102
	movl	n(%rip), %eax
	pushq	%rcx
	.cfi_def_cfa_offset 168
	movl	%r15d, %edi
	movq	Dist(%rip), %r9
	pushq	%rax
	.cfi_def_cfa_offset 176
	movl	40(%rsp), %r8d
	movl	36(%rsp), %ecx
	movl	24(%rsp), %edx
	movl	20(%rsp), %esi
	call	_Z31__device_stub__Z6UpdateiiiiiPiiiiiiiPii
	popq	%rsi
	.cfi_def_cfa_offset 168
	popq	%rdi
	.cfi_def_cfa_offset 160
.L102:
	incl	%r15d
	jmp	.L100
.L110:
	movl	92(%rsp), %ecx
	movq	32(%rsp), %r9
	xorl	%r8d, %r8d
	movq	84(%rsp), %rdx
	movq	72(%rsp), %rdi
	movl	80(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L108
	movl	n(%rip), %eax
	movl	%ebx, %edi
	pushq	%rax
	.cfi_def_cfa_offset 168
	pushq	Dist(%rip)
	.cfi_def_cfa_offset 176
	movl	40(%rsp), %r9d
	movl	36(%rsp), %r8d
	movl	24(%rsp), %ecx
	movl	20(%rsp), %edx
	movl	44(%rsp), %esi
	call	_Z44__device_stub__Z17UpdateIndependentiiiiiiPiiiiiiiiPii
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
	jmp	.L108
.L112:
	incl	%r12d
	jmp	.L99
.L98:
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4018:
	.size	_Z8calAsynciiiiiii, .-_Z8calAsynciiiiiii
	.section	.rodata.str1.1
.LC10:
	.string	"Round: %d\n"
	.text
	.globl	_Z13block_FW_2GPUi
	.type	_Z13block_FW_2GPUi, @function
_Z13block_FW_2GPUi:
.LFB4017:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	leaq	.LC10(%rip), %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	xorl	%r12d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	pushq	%rbp
	.cfi_def_cfa_offset 64
	movl	n(%rip), %eax
	movl	%edi, %ebp
	addl	%edi, %eax
	decl	%eax
	cltd
	idivl	%edi
	movl	%eax, %r13d
.L114:
	movl	%r12d, %ebx
	incl	%r12d
	cmpl	%r13d, %ebx
	jge	.L117
	movq	stderr(%rip), %rdi
	movq	%r15, %rdx
	movl	%ebx, %ecx
	xorl	%eax, %eax
	movl	$2, %esi
	movl	%r13d, %r14d
	call	__fprintf_chk@PLT
	xorl	%edi, %edi
	movl	%ebx, %r8d
	movl	$1, %r9d
	pushq	%rdx
	.cfi_def_cfa_offset 72
	movl	%ebx, %ecx
	movl	%ebx, %edx
	movl	%ebp, %esi
	pushq	$1
	.cfi_def_cfa_offset 80
	subl	%r12d, %r14d
	call	_Z8calAsynciiiiiii
	popq	%rcx
	.cfi_def_cfa_offset 72
	popq	%rsi
	.cfi_def_cfa_offset 64
	call	_Z14syncAllStreamsv
	movl	%ebx, %r9d
	xorl	%r8d, %r8d
	movl	%ebx, %ecx
	pushq	%rdi
	.cfi_def_cfa_offset 72
	movl	%ebx, %edx
	movl	%ebp, %esi
	xorl	%edi, %edi
	pushq	$1
	.cfi_def_cfa_offset 80
	call	_Z8calAsynciiiiiii
	movl	%r14d, %r9d
	movl	%r12d, %r8d
	movl	%ebx, %ecx
	movl	%ebx, %edx
	movl	%ebp, %esi
	xorl	%edi, %edi
	movl	$1, (%rsp)
	call	_Z8calAsynciiiiiii
	movl	%ebx, %r8d
	xorl	%ecx, %ecx
	movl	%ebx, %edx
	movl	%ebp, %esi
	movl	$1, %r9d
	movl	$1, %edi
	movl	%ebx, (%rsp)
	call	_Z8calAsynciiiiiii
	movl	%r12d, %ecx
	movl	%ebx, %edx
	movl	%ebp, %esi
	movl	%ebx, %r8d
	movl	$1, %edi
	movl	$1, %r9d
	movl	%r14d, (%rsp)
	call	_Z8calAsynciiiiiii
	popq	%r8
	.cfi_def_cfa_offset 72
	popq	%r9
	.cfi_def_cfa_offset 64
	call	_Z14syncAllStreamsv
	movl	%ebx, %r9d
	xorl	%r8d, %r8d
	xorl	%ecx, %ecx
	pushq	%r10
	.cfi_def_cfa_offset 72
	movl	%ebx, %edx
	movl	%ebp, %esi
	xorl	%edi, %edi
	pushq	%rbx
	.cfi_def_cfa_offset 80
	call	_Z8calAsynciiiiiii
	movl	%r14d, %r9d
	movl	%r12d, %r8d
	xorl	%ecx, %ecx
	movl	%ebx, %edx
	movl	%ebp, %esi
	movl	$1, %edi
	movl	%ebx, (%rsp)
	call	_Z8calAsynciiiiiii
	movl	%ebx, %r9d
	xorl	%r8d, %r8d
	movl	%r12d, %ecx
	movl	%ebx, %edx
	movl	%ebp, %esi
	movl	$1, %edi
	movl	%r14d, (%rsp)
	call	_Z8calAsynciiiiiii
	movl	%ebx, %edx
	movl	%r14d, %r9d
	movl	%r12d, %r8d
	movl	%r12d, %ecx
	movl	%ebp, %esi
	xorl	%edi, %edi
	movl	%r14d, (%rsp)
	call	_Z8calAsynciiiiiii
	popq	%r11
	.cfi_def_cfa_offset 72
	popq	%rbx
	.cfi_def_cfa_offset 64
	call	_Z14syncAllStreamsv
	jmp	.L114
.L117:
	popq	%rax
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4017:
	.size	_Z13block_FW_2GPUi, .-_Z13block_FW_2GPUi
	.section	.text.startup
	.globl	main
	.type	main, @function
main:
.LFB4012:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movq	%rsi, %rbx
	pushq	%rax
	.cfi_def_cfa_offset 32
	movq	24(%rsi), %rdi
	call	atoi@PLT
	movq	8(%rbx), %rdi
	movl	%eax, %ebp
	movl	%eax, %esi
	call	_Z5inputPci
	movl	%ebp, %edi
	call	_Z13block_FW_2GPUi
	movq	16(%rbx), %rdi
	call	_Z6outputPc
	popq	%rdx
	.cfi_def_cfa_offset 24
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE4012:
	.size	main, .-main
	.type	_GLOBAL__sub_I_realn, @function
_GLOBAL__sub_I_realn:
.LFB4737:
	.cfi_startproc
	endbr64
	xorl	%eax, %eax
	leaq	__dso_handle(%rip), %rdx
	xorl	%esi, %esi
	leaq	__tcf_0(%rip), %rdi
	movq	%rax, streams(%rip)
	movq	%rax, 8+streams(%rip)
	movq	%rax, 16+streams(%rip)
	movq	%rax, 24+streams(%rip)
	movq	%rax, 32+streams(%rip)
	movq	%rax, 40+streams(%rip)
	jmp	__cxa_atexit@PLT
	.cfi_endproc
.LFE4737:
	.size	_GLOBAL__sub_I_realn, .-_GLOBAL__sub_I_realn
	.section	.init_array
	.align 8
	.quad	_GLOBAL__sub_I_realn
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	streams
	.bss
	.align 32
	.type	streams, @object
	.size	streams, 48
streams:
	.zero	48
	.globl	streamSize
	.align 8
	.type	streamSize, @object
	.size	streamSize, 8
streamSize:
	.zero	8
	.globl	dDist
	.align 16
	.type	dDist, @object
	.size	dDist, 16
dDist:
	.zero	16
	.globl	Dist
	.align 8
	.type	Dist, @object
	.size	Dist, 8
Dist:
	.zero	8
	.globl	m
	.align 4
	.type	m, @object
	.size	m, 4
m:
	.zero	4
	.globl	n
	.align 4
	.type	n, @object
	.size	n, 4
n:
	.zero	4
	.globl	realn
	.align 4
	.type	realn, @object
	.size	realn, 4
realn:
	.zero	4
	.hidden	__dso_handle
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <assert.h>
#include <vector>
using namespace std;

const int INF = 10000000;
const int V = 10010;
const int MAX_THREAD_DIM2 = 32;
void input(char *inFileName, int B);
void output(char *outFileName);

void block_FW_2GPU(int B);
int ceil(int a, int b);
void calAsync(int gpuId, int B, int Round, int block_start_x, int block_start_y, int block_width, int block_height);

int realn;
int n, m;	// Number of vertices, edges
int* Dist;	// n * n, on host
int* dDist[2]; // n * n, on device

int streamSize[2];
vector<hipStream_t> streams[2];

int getGPUId ()
{
	int gpuId;
	hipGetDevice(&gpuId);
	return gpuId;
}
hipStream_t getIdleStream (int gpuId)
{
	hipSetDevice(gpuId);
	if(streams[gpuId].size() == streamSize[gpuId])
	{
		hipStream_t stm;
		hipStreamCreate(&stm);
		streams[gpuId].push_back(stm);
		streamSize[gpuId]++;
		return stm;
	}
	else
		return streams[gpuId][streamSize[gpuId]++];
}
void syncAllStreams ()
{
	hipDeviceSynchronize();
	streamSize[0] = 0;
	streamSize[1] = 0;
}




void blockCopyAsync (int gpuId, int* dst, const int* src, hipMemcpyKind kind, hipStream_t stream, int B, int bi0, int bi1, int bj0, int bj1)
{
	hipSetDevice(gpuId);
	for(int i = bi0 * B; i < bi1 * B; ++i)
	{
		int offset = i * n + bj0 * B;
		int size = (bj1 - bj0) * B * sizeof(int);
		hipMemcpyAsync(dst + offset, src + offset, size, kind, stream);
	}
}

int main(int argc, char* argv[])
{
	int B = atoi(argv[3]);
	input(argv[1], B);
	block_FW_2GPU(B);
	output(argv[2]);
	return 0;
}

void input(char *inFileName, int B)
{
	FILE *infile = fopen(inFileName, "r");
	fscanf(infile, "%d %d", &realn, &m);
	n = ceil(realn, B) * B;
	hipMallocManaged(&Dist, n * n * sizeof(int));

	for (int i = 0, k = 0; i < n; ++i) {
		for (int j = 0; j < n; ++j, ++k) {
			if (i == j)	Dist[k] = 0;
			else		Dist[k] = INF;
		}
	}

	while (--m >= 0) {
		int a, b, v;
		fscanf(infile, "%d %d %d", &a, &b, &v);
		--a, --b;
		Dist[a * n + b] = v;
	}
}

void output(char *outFileName)
{
	FILE *outfile = fopen(outFileName, "w");
	for (int i = 0; i < realn; ++i) {
		for (int j = 0; j < realn; ++j) {
			int d = Dist[i * n + j];
			if (d >= INF)	fprintf(outfile, "INF ");
			else			fprintf(outfile, "%d ", d);
		}
		fprintf(outfile, "\n");
	}		
	hipFree(Dist);
}

void print ()
{
	for (int i = 0; i < realn; ++i) {
		for (int j = 0; j < realn; ++j) {
			int d = Dist[i * n + j];
			if (d >= INF)	fprintf(stderr, "INF ");
			else			fprintf(stderr, "%d ", d);
		}
		fprintf(stderr, "\n");
	}	
	fprintf(stderr, "\n");
}

int ceil(int a, int b)
{
	return (a + b -1)/b;
}

void block_FW_2GPU(int B)
{
	int round = ceil(n, B);
	for (int r = 0; r < round; ++r) {
		/* Phase 1*/
		fprintf(stderr, "Round: %d\n", r);
		calAsync(0, B,	r,	r,	r,	1,	1);
		syncAllStreams();

		/* Phase 2*/
		calAsync(0, B, r,     r,     0,             r,             1); // L 0
		calAsync(0, B, r,     r,  r +1,  round - r -1,             1); // R 0
		calAsync(1, B, r,     0,     r,             1,             r); // U 1
		calAsync(1, B, r,  r +1,     r,             1,  round - r -1); // D 1
		syncAllStreams();

		/* Phase 3*/
		calAsync(0, B, r,     0,     0,            r,             r); // <^
		calAsync(1, B, r,     0,  r +1,  round -r -1,             r); // ^>
		calAsync(1, B, r,  r +1,     0,            r,  round - r -1); // <v
		calAsync(0, B, r,  r +1,  r +1,  round -r -1,  round - r -1); // v>
		syncAllStreams();
	}
}


__global__
void Update (int k, int i0, int j0, int i1, int j1, int* dDist, int n)
{
	#define D(i,j) (dDist[(i) * n + (j)])
	int i = blockDim.x * blockIdx.x + threadIdx.x + i0;
    int j = blockDim.y * blockIdx.y + threadIdx.y + j0;
	if(i >= i1 || j >= j1)
		return;
	int Dik = D(i, k);
	int Dkj = D(k, j);
	int D1 = Dik + Dkj;
	if (D1 < D(i, j))
		D(i, j) = D1;
}

__global__
void UpdateIndependent (int k0, int k1, int i0, int j0, int i1, int j1, int* dDist, int n)
{
	#define D(i,j) (dDist[(i) * n + (j)])
	int tx = threadIdx.x;
	int ty = threadIdx.y;
	int di = blockDim.x * blockIdx.x + tx;
    int dj = blockDim.y * blockIdx.y + ty;
	int i = i0 + di;
	int j = j0 + dj;
	bool valid = i < i1 && j < j1;
	__shared__ int Si[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
	__shared__ int Sj[MAX_THREAD_DIM2][MAX_THREAD_DIM2];
	const int cacheSize = MAX_THREAD_DIM2;
	int Dij = valid? D(i, j): 0;
	int dkmod = 0;
	for(int k = k0; k < k1; ++k)
	{
		if(dkmod == 0)
		{
			__syncthreads();
			if(i < i1 && k+ty < k1)
			Si[ty][tx] = D(i, k+ty);
			if(j < j1 && k+tx < k1)
			Sj[tx][ty] = D(k+tx, j);
			__syncthreads();		
		}
		if(valid)
		{
			// assert(Si[tx][dkmod] == D(i,k));
			// assert(Sj[dkmod][ty] == D(k,j));			
			
			// int Dik = D(i, k);
			// int Dkj = D(k, j);
			int Dik = Si[dkmod][tx];
			int Dkj = Sj[dkmod][ty];
			int D1 = Dik + Dkj;
			if (D1 < Dij)
				Dij = D1;
		}
		dkmod = (dkmod + 1) % cacheSize;
	}
	if(valid)
		D(i, j) = Dij;
}

void calAsync(int gpuId, int B, int Round, int block_start_x, int block_start_y, int block_width, int block_height)
{
	hipSetDevice(gpuId);

	int block_end_x = block_start_x + block_height;
	int block_end_y = block_start_y + block_width;

	for (int b_i =  block_start_x; b_i < block_end_x; ++b_i) {
		for (int b_j = block_start_y; b_j < block_end_y; ++b_j) {
			// To calculate B*B elements in the block (b_i, b_j)
			// For each block, it need to compute B times
			// for (int k = Round * B; k < (Round +1) * B && k < n; ++k) {
				// To calculate original index of elements in the block (b_i, b_j)
				// For instance, original index of (0,0) in block (1,2) is (2,5) for V=6,B=2
				int i0 = b_i * B;
				int i1 = min((b_i +1) * B, n);
				int j0 = b_j * B; 
				int j1 = min((b_j +1) * B, n);
				int k0 = Round * B;
				int k1 = min((Round +1) * B, n);
				bool iDepends = i0 == k0;
				bool jDepends = j0 == k0;

				int threadDim = MAX_THREAD_DIM2;//std::min(B, MAX_THREAD_DIM2);
				int blockDim = (B + MAX_THREAD_DIM2 - 1) / MAX_THREAD_DIM2;
				dim3 grid(blockDim, blockDim), block(threadDim, threadDim);
				hipStream_t stm = getIdleStream(gpuId);
				if(iDepends || jDepends)
				{
					for(int k=k0; k<k1; ++k)
						Update<<<grid, block, 0, stm>>>(k, i0, j0, i1, j1, Dist, n);
				}
				else
					UpdateIndependent<<<grid, block, 0, stm>>>(k0, k1, i0, j0, i1, j1, Dist, n);

				// for (int i = i0; i < i1; ++i) {
				// 	for (int j = j0; j < j1; ++j) {
				// 		if (Dist[i][k] + Dist[k][j] < Dist[i][j])
				// 			Dist[i][j] = Dist[i][k] + Dist[k][j];
				// 	}
				// }
			// }
		}
	}
}



	.text
	.file	"HW4_x1054037_2GPU_Unified_bug.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.section	.text.startup,"ax",@progbits
	.type	__cxx_global_array_dtor,@function # -- Begin function __cxx_global_array_dtor
__cxx_global_array_dtor:                # @__cxx_global_array_dtor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset %rbx, -16
	movl	$48, %ebx
.LBB0_1:                                # =>This Inner Loop Header: Depth=1
	movq	streams-24(%rbx), %rdi
	testq	%rdi, %rdi
	je	.LBB0_3
# %bb.2:                                #   in Loop: Header=BB0_1 Depth=1
	callq	_ZdlPv
.LBB0_3:                                # %_ZNSt6vectorIP12ihipStream_tSaIS1_EED2Ev.exit
                                        #   in Loop: Header=BB0_1 Depth=1
	addq	$-24, %rbx
	jne	.LBB0_1
# %bb.4:
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	__cxx_global_array_dtor, .Lfunc_end0-__cxx_global_array_dtor
	.cfi_endproc
                                        # -- End function
	.text
	.globl	_Z8getGPUIdv                    # -- Begin function _Z8getGPUIdv
	.type	_Z8getGPUIdv,@function
_Z8getGPUIdv:                           # @_Z8getGPUIdv
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$16, %rsp
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -16
	leaq	12(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipGetDevice
	movl	(%rbx), %eax
	addq	$16, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z8getGPUIdv, .Lfunc_end1-_Z8getGPUIdv
	.cfi_endproc
                                        # -- End function
	.globl	_Z13getIdleStreami              # -- Begin function _Z13getIdleStreami
	.type	_Z13getIdleStreami,@function
_Z13getIdleStreami:                     # @_Z13getIdleStreami
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	subq	$16, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	%edi, %ebx
	callq	hipSetDevice
	movslq	%ebx, %r15
	leaq	(,%r15,8), %rcx
	movq	streams+8(%rcx,%rcx,2), %rsi
	movq	streams(%rcx,%rcx,2), %rax
	subq	%rax, %rsi
	sarq	$3, %rsi
	movslq	streamSize(,%r15,4), %rdx
	cmpq	%rdx, %rsi
	jne	.LBB2_5
# %bb.1:
	leaq	(%rcx,%rcx,2), %rbx
	addq	$streams, %rbx
	leaq	8(%rsp), %rdi
	callq	hipStreamCreate
	movq	8(%rbx), %rsi
	cmpq	16(%rbx), %rsi
	je	.LBB2_3
# %bb.2:
	movq	8(%rsp), %rax
	movq	%rax, (%rsi)
	addq	$8, 8(%rbx)
	jmp	.LBB2_4
.LBB2_5:
	leal	1(%rdx), %ecx
	movl	%ecx, streamSize(,%r15,4)
	movq	(%rax,%rdx,8), %rax
	jmp	.LBB2_6
.LBB2_3:
	leaq	8(%rsp), %r14
	movq	%rbx, %rdi
	movq	%r14, %rdx
	callq	_ZNSt6vectorIP12ihipStream_tSaIS1_EE17_M_realloc_insertIJRKS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_
	movq	(%r14), %rax
.LBB2_4:                                # %_ZNSt6vectorIP12ihipStream_tSaIS1_EE9push_backERKS1_.exit
	incl	streamSize(,%r15,4)
.LBB2_6:
	addq	$16, %rsp
	.cfi_def_cfa_offset 32
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z13getIdleStreami, .Lfunc_end2-_Z13getIdleStreami
	.cfi_endproc
                                        # -- End function
	.globl	_Z14syncAllStreamsv             # -- Begin function _Z14syncAllStreamsv
	.type	_Z14syncAllStreamsv,@function
_Z14syncAllStreamsv:                    # @_Z14syncAllStreamsv
	.cfi_startproc
# %bb.0:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	hipDeviceSynchronize
	movq	$0, streamSize(%rip)
	popq	%rax
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z14syncAllStreamsv, .Lfunc_end3-_Z14syncAllStreamsv
	.cfi_endproc
                                        # -- End function
	.globl	_Z14blockCopyAsynciPiPKi13hipMemcpyKindP12ihipStream_tiiiii # -- Begin function _Z14blockCopyAsynciPiPKi13hipMemcpyKindP12ihipStream_tiiiii
	.type	_Z14blockCopyAsynciPiPKi13hipMemcpyKindP12ihipStream_tiiiii,@function
_Z14blockCopyAsynciPiPKi13hipMemcpyKindP12ihipStream_tiiiii: # @_Z14blockCopyAsynciPiPKi13hipMemcpyKindP12ihipStream_tiiiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, %r12d
	movq	%r8, 16(%rsp)                   # 8-byte Spill
	movl	%ecx, 12(%rsp)                  # 4-byte Spill
	movq	%rdx, %r14
	movq	%rsi, %r15
	movl	88(%rsp), %r13d
	movl	80(%rsp), %ebx
	callq	hipSetDevice
	movl	%ebx, %edx
	imull	%r12d, %ebx
	movl	%r13d, %eax
	imull	%r12d, %eax
	cmpl	%eax, %ebx
	jge	.LBB4_3
# %bb.1:                                # %.lr.ph
	movl	104(%rsp), %eax
	movl	96(%rsp), %ebp
	subl	%ebp, %eax
	imull	%r12d, %ebp
	imull	%r12d, %eax
	shll	$2, %eax
	movl	%r12d, %ecx
	movslq	%eax, %r12
	subl	%edx, %r13d
	imull	%ecx, %r13d
.LBB4_2:                                # =>This Inner Loop Header: Depth=1
	movl	n(%rip), %eax
	imull	%ebx, %eax
	addl	%ebp, %eax
	cltq
	leaq	(%r15,%rax,4), %rdi
	leaq	(%r14,%rax,4), %rsi
	movq	%r12, %rdx
	movl	12(%rsp), %ecx                  # 4-byte Reload
	movq	16(%rsp), %r8                   # 8-byte Reload
	callq	hipMemcpyAsync
	incl	%ebx
	decl	%r13d
	jne	.LBB4_2
.LBB4_3:                                # %._crit_edge
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z14blockCopyAsynciPiPKi13hipMemcpyKindP12ihipStream_tiiiii, .Lfunc_end4-_Z14blockCopyAsynciPiPKi13hipMemcpyKindP12ihipStream_tiiiii
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	pushq	%rax
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %rbp, -16
	movq	%rsi, %rbx
	movq	24(%rsi), %rdi
	callq	atoi
	movl	%eax, %ebp
	movq	8(%rbx), %rdi
	movl	%eax, %esi
	callq	_Z5inputPci
	movl	%ebp, %edi
	callq	_Z13block_FW_2GPUi
	movq	16(%rbx), %rdi
	callq	_Z6outputPc
	xorl	%eax, %eax
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	main, .Lfunc_end5-main
	.cfi_endproc
                                        # -- End function
	.globl	_Z5inputPci                     # -- Begin function _Z5inputPci
	.type	_Z5inputPci,@function
_Z5inputPci:                            # @_Z5inputPci
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$24, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	%esi, %r14d
	movl	$.L.str, %esi
	callq	fopen
	movq	%rax, %rbx
	xorl	%r15d, %r15d
	movl	$.L.str.1, %esi
	movl	$realn, %edx
	movl	$m, %ecx
	movq	%rax, %rdi
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movl	realn(%rip), %eax
	leal	(%r14,%rax), %esi
	decl	%esi
	movl	%esi, %eax
	cltd
	idivl	%r14d
	subl	%edx, %esi
	movl	%esi, n(%rip)
	imull	%esi, %esi
	shlq	$2, %rsi
	movl	$Dist, %edi
	movl	$1, %edx
	callq	hipMallocManaged
	movl	n(%rip), %edx
	testl	%edx, %edx
	jle	.LBB6_7
# %bb.1:                                # %.preheader16.preheader
	xorl	%eax, %eax
	xorl	%ecx, %ecx
.LBB6_2:                                # %.preheader16
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB6_4 Depth 2
	testl	%edx, %edx
	jle	.LBB6_6
# %bb.3:                                # %.lr.ph
                                        #   in Loop: Header=BB6_2 Depth=1
	movslq	%ecx, %rsi
	shlq	$2, %rsi
	addq	Dist(%rip), %rsi
	xorl	%edi, %edi
.LBB6_4:                                #   Parent Loop BB6_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	cmpl	%edi, %eax
	movl	$10000000, %edx                 # imm = 0x989680
	cmovel	%r15d, %edx
	movl	%edx, (%rsi,%rdi,4)
	movl	n(%rip), %edx
	incq	%rdi
	cmpl	%edx, %edi
	jl	.LBB6_4
# %bb.5:                                # %._crit_edge.loopexit
                                        #   in Loop: Header=BB6_2 Depth=1
	addl	%edi, %ecx
.LBB6_6:                                # %._crit_edge
                                        #   in Loop: Header=BB6_2 Depth=1
	incq	%rax
	cmpl	%edx, %eax
	jl	.LBB6_2
.LBB6_7:                                # %.preheader
	movl	m(%rip), %eax
	leal	-1(%rax), %ecx
	movl	%ecx, m(%rip)
	testl	%eax, %eax
	jle	.LBB6_10
# %bb.8:
	leaq	20(%rsp), %r14
	leaq	16(%rsp), %r15
	leaq	12(%rsp), %r12
.LBB6_9:                                # %.lr.ph21
                                        # =>This Inner Loop Header: Depth=1
	movl	$.L.str.2, %esi
	movq	%rbx, %rdi
	movq	%r14, %rdx
	movq	%r15, %rcx
	movq	%r12, %r8
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movslq	20(%rsp), %rax
	decq	%rax
	movslq	16(%rsp), %rcx
	movslq	n(%rip), %rdx
	imulq	%rax, %rdx
	addq	%rcx, %rdx
	movl	12(%rsp), %eax
	movq	Dist(%rip), %rcx
	movl	%eax, -4(%rcx,%rdx,4)
	movl	m(%rip), %eax
	leal	-1(%rax), %ecx
	movl	%ecx, m(%rip)
	testl	%eax, %eax
	jg	.LBB6_9
.LBB6_10:                               # %._crit_edge22
	addq	$24, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z5inputPci, .Lfunc_end6-_Z5inputPci
	.cfi_endproc
                                        # -- End function
	.globl	_Z13block_FW_2GPUi              # -- Begin function _Z13block_FW_2GPUi
	.type	_Z13block_FW_2GPUi,@function
_Z13block_FW_2GPUi:                     # @_Z13block_FW_2GPUi
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%edi, %ebx
	movl	n(%rip), %eax
	addl	%ebx, %eax
	decl	%eax
	cltd
	idivl	%edi
                                        # kill: def $eax killed $eax def $rax
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	testl	%eax, %eax
	jle	.LBB7_3
# %bb.1:                                # %.lr.ph.preheader
	movq	16(%rsp), %rax                  # 8-byte Reload
	leal	-1(%rax), %ebp
	xorl	%r15d, %r15d
	movl	$1, %r14d
.LBB7_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movq	stderr(%rip), %rdi
	movl	$.L.str.7, %esi
	movl	%r15d, %edx
	xorl	%eax, %eax
	callq	fprintf
	movl	%r14d, (%rsp)
	xorl	%edi, %edi
	movl	%ebx, %esi
	movl	%r15d, %edx
	movl	%r15d, %ecx
	movl	%r15d, %r8d
	movl	$1, %r9d
	callq	_Z8calAsynciiiiiii
	callq	hipDeviceSynchronize
	xorl	%r13d, %r13d
	movq	%r13, streamSize(%rip)
	movl	%r14d, (%rsp)
	xorl	%edi, %edi
	movl	%ebx, %esi
	movl	%r15d, %edx
	movl	%r15d, %ecx
	xorl	%r8d, %r8d
	movl	%r15d, %r9d
	callq	_Z8calAsynciiiiiii
	leal	1(%r15), %r12d
	movl	%r14d, (%rsp)
	xorl	%edi, %edi
	movl	%ebx, %esi
	movl	%r15d, %edx
	movl	%r15d, %ecx
	movl	%r12d, %r8d
	movl	%ebp, %r9d
	callq	_Z8calAsynciiiiiii
	movl	%r15d, (%rsp)
	movl	$1, %edi
	movl	%ebx, %esi
	movl	%r15d, %edx
	xorl	%ecx, %ecx
	movl	%r15d, %r8d
	movl	$1, %r9d
	callq	_Z8calAsynciiiiiii
	movl	%ebp, (%rsp)
	movl	$1, %edi
	movl	%ebx, %esi
	movl	%r15d, %edx
	movl	%r12d, %ecx
	movl	%r15d, %r8d
	movl	$1, %r9d
	callq	_Z8calAsynciiiiiii
	callq	hipDeviceSynchronize
	movq	%r13, streamSize(%rip)
	movl	%r15d, (%rsp)
	xorl	%edi, %edi
	movl	%ebx, %esi
	movl	%r15d, %edx
	xorl	%ecx, %ecx
	xorl	%r8d, %r8d
	movl	%r15d, %r9d
	callq	_Z8calAsynciiiiiii
	movl	%r15d, (%rsp)
	movl	$1, %edi
	movl	%ebx, %esi
	movl	%r15d, %edx
	xorl	%ecx, %ecx
	movl	%r12d, %r8d
	movl	%ebp, %r9d
	callq	_Z8calAsynciiiiiii
	movl	%ebp, (%rsp)
	movl	$1, %edi
	movl	%ebx, %esi
	movl	%r15d, %edx
	movl	%r12d, %ecx
	xorl	%r8d, %r8d
	movl	%r15d, %r9d
	callq	_Z8calAsynciiiiiii
	movl	%ebp, (%rsp)
	xorl	%edi, %edi
	movl	%ebx, %esi
	movl	%r15d, %edx
	movl	%r12d, %ecx
	movl	%r12d, %r8d
	movl	%ebp, %r9d
	callq	_Z8calAsynciiiiiii
	callq	hipDeviceSynchronize
	movq	%r13, streamSize(%rip)
	decl	%ebp
	movl	%r12d, %r15d
	cmpl	16(%rsp), %r12d                 # 4-byte Folded Reload
	jne	.LBB7_2
.LBB7_3:                                # %._crit_edge
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_Z13block_FW_2GPUi, .Lfunc_end7-_Z13block_FW_2GPUi
	.cfi_endproc
                                        # -- End function
	.globl	_Z6outputPc                     # -- Begin function _Z6outputPc
	.type	_Z6outputPc,@function
_Z6outputPc:                            # @_Z6outputPc
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$.L.str.3, %esi
	callq	fopen
	movq	%rax, %rbx
	movl	realn(%rip), %eax
	testl	%eax, %eax
	jle	.LBB8_7
# %bb.1:                                # %.preheader.preheader
	xorl	%ebp, %ebp
.LBB8_2:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB8_4 Depth 2
	testl	%eax, %eax
	jle	.LBB8_6
# %bb.3:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB8_2 Depth=1
	movslq	%ebp, %r14
	xorl	%r15d, %r15d
.LBB8_4:                                # %.lr.ph
                                        #   Parent Loop BB8_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	Dist(%rip), %rax
	movslq	n(%rip), %rcx
	imulq	%r14, %rcx
	addq	%r15, %rcx
	movl	(%rax,%rcx,4), %edx
	cmpl	$10000000, %edx                 # imm = 0x989680
	jl	.LBB8_8
# %bb.5:                                #   in Loop: Header=BB8_4 Depth=2
	movl	$.L.str.4, %edi
	movl	$4, %esi
	movl	$1, %edx
	movq	%rbx, %rcx
	callq	fwrite@PLT
	jmp	.LBB8_9
.LBB8_8:                                #   in Loop: Header=BB8_4 Depth=2
	movl	$.L.str.5, %esi
	movq	%rbx, %rdi
	xorl	%eax, %eax
	callq	fprintf
.LBB8_9:                                #   in Loop: Header=BB8_4 Depth=2
	incq	%r15
	cmpl	realn(%rip), %r15d
	jl	.LBB8_4
.LBB8_6:                                # %._crit_edge
                                        #   in Loop: Header=BB8_2 Depth=1
	movl	$10, %edi
	movq	%rbx, %rsi
	callq	fputc@PLT
	incl	%ebp
	movl	realn(%rip), %eax
	cmpl	%eax, %ebp
	jl	.LBB8_2
.LBB8_7:                                # %._crit_edge15
	movq	Dist(%rip), %rdi
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	hipFree                         # TAILCALL
.Lfunc_end8:
	.size	_Z6outputPc, .Lfunc_end8-_Z6outputPc
	.cfi_endproc
                                        # -- End function
	.globl	_Z4ceilii                       # -- Begin function _Z4ceilii
	.type	_Z4ceilii,@function
_Z4ceilii:                              # @_Z4ceilii
	.cfi_startproc
# %bb.0:
                                        # kill: def $esi killed $esi def $rsi
                                        # kill: def $edi killed $edi def $rdi
	leal	(%rdi,%rsi), %eax
	decl	%eax
	cltd
	idivl	%esi
	retq
.Lfunc_end9:
	.size	_Z4ceilii, .Lfunc_end9-_Z4ceilii
	.cfi_endproc
                                        # -- End function
	.globl	_Z5printv                       # -- Begin function _Z5printv
	.type	_Z5printv,@function
_Z5printv:                              # @_Z5printv
	.cfi_startproc
# %bb.0:
	movl	realn(%rip), %eax
	testl	%eax, %eax
	jle	.LBB10_10
# %bb.1:                                # %.preheader.preheader
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	xorl	%ebx, %ebx
.LBB10_2:                               # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB10_4 Depth 2
	testl	%eax, %eax
	jle	.LBB10_8
# %bb.3:                                # %.lr.ph.preheader
                                        #   in Loop: Header=BB10_2 Depth=1
	movslq	%ebx, %r14
	xorl	%r15d, %r15d
.LBB10_4:                               # %.lr.ph
                                        #   Parent Loop BB10_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	Dist(%rip), %rax
	movslq	n(%rip), %rcx
	imulq	%r14, %rcx
	addq	%r15, %rcx
	movl	(%rax,%rcx,4), %edx
	movq	stderr(%rip), %rcx
	cmpl	$10000000, %edx                 # imm = 0x989680
	jl	.LBB10_6
# %bb.5:                                #   in Loop: Header=BB10_4 Depth=2
	movl	$.L.str.4, %edi
	movl	$4, %esi
	movl	$1, %edx
	callq	fwrite@PLT
	jmp	.LBB10_7
.LBB10_6:                               #   in Loop: Header=BB10_4 Depth=2
	movl	$.L.str.5, %esi
	movq	%rcx, %rdi
	xorl	%eax, %eax
	callq	fprintf
.LBB10_7:                               #   in Loop: Header=BB10_4 Depth=2
	incq	%r15
	cmpl	realn(%rip), %r15d
	jl	.LBB10_4
.LBB10_8:                               # %._crit_edge
                                        #   in Loop: Header=BB10_2 Depth=1
	movq	stderr(%rip), %rsi
	movl	$10, %edi
	callq	fputc@PLT
	incl	%ebx
	movl	realn(%rip), %eax
	cmpl	%eax, %ebx
	jl	.LBB10_2
# %bb.9:
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	.cfi_restore %r14
	.cfi_restore %r15
.LBB10_10:                              # %._crit_edge13
	movq	stderr(%rip), %rsi
	movl	$10, %edi
	jmp	fputc@PLT                       # TAILCALL
.Lfunc_end10:
	.size	_Z5printv, .Lfunc_end10-_Z5printv
	.cfi_endproc
                                        # -- End function
	.globl	_Z8calAsynciiiiiii              # -- Begin function _Z8calAsynciiiiiii
	.type	_Z8calAsynciiiiiii,@function
_Z8calAsynciiiiiii:                     # @_Z8calAsynciiiiiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
                                        # kill: def $r9d killed $r9d def $r9
	movq	%r9, 56(%rsp)                   # 8-byte Spill
                                        # kill: def $r8d killed $r8d def $r8
	movq	%r8, 48(%rsp)                   # 8-byte Spill
	movl	%ecx, %ebx
	movl	%edx, %ebp
                                        # kill: def $esi killed $esi def $rsi
	movq	%rsi, 16(%rsp)                  # 8-byte Spill
	movl	128(%rsp), %r14d
	movl	%edi, 36(%rsp)                  # 4-byte Spill
	callq	hipSetDevice
	movl	%r14d, 12(%rsp)                 # 4-byte Spill
	testl	%r14d, %r14d
	jle	.LBB11_5
# %bb.1:                                # %.preheader79.lr.ph
	addl	%ebx, 12(%rsp)                  # 4-byte Folded Spill
	movq	56(%rsp), %rax                  # 8-byte Reload
	movq	48(%rsp), %rcx                  # 8-byte Reload
	addl	%ecx, %eax
	movl	%eax, 28(%rsp)                  # 4-byte Spill
	movl	%ebp, %eax
	movq	16(%rsp), %rcx                  # 8-byte Reload
	imull	%ecx, %eax
	movl	%eax, 4(%rsp)                   # 4-byte Spill
	incl	%ebp
	imull	%ecx, %ebp
	movl	%ebp, 32(%rsp)                  # 4-byte Spill
	leal	31(%rcx), %eax
	addl	$62, %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	sarl	$5, %ecx
	movq	%rcx, %rax
	shlq	$32, %rax
	orq	%rcx, %rax
	movq	%rax, 64(%rsp)                  # 8-byte Spill
.LBB11_2:                               # %.preheader79
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB11_7 Depth 2
                                        #       Child Loop BB11_11 Depth 3
	cmpl	$0, 56(%rsp)                    # 4-byte Folded Reload
	jle	.LBB11_3
# %bb.6:                                # %.lr.ph82
                                        #   in Loop: Header=BB11_2 Depth=1
	movl	%ebx, %ecx
	movq	16(%rsp), %rax                  # 8-byte Reload
	imull	%eax, %ecx
	movl	%ecx, 8(%rsp)                   # 4-byte Spill
	incl	%ebx
	movl	%ebx, 24(%rsp)                  # 4-byte Spill
	imull	%eax, %ebx
	movl	%ebx, 40(%rsp)                  # 4-byte Spill
	movq	48(%rsp), %rax                  # 8-byte Reload
	movl	%eax, %r14d
.LBB11_7:                               #   Parent Loop BB11_2 Depth=1
                                        # =>  This Loop Header: Depth=2
                                        #       Child Loop BB11_11 Depth 3
	movl	n(%rip), %ebx
	movl	40(%rsp), %eax                  # 4-byte Reload
	cmpl	%ebx, %eax
	movl	%ebx, %r12d
	cmovll	%eax, %r12d
	movl	%r14d, %r15d
	movq	16(%rsp), %rax                  # 8-byte Reload
	imull	%eax, %r15d
	incl	%r14d
	movl	%r14d, 44(%rsp)                 # 4-byte Spill
	imull	%eax, %r14d
	cmpl	%ebx, %r14d
	cmovgel	%ebx, %r14d
	movl	32(%rsp), %eax                  # 4-byte Reload
	cmpl	%ebx, %eax
	cmovll	%eax, %ebx
	movl	36(%rsp), %edi                  # 4-byte Reload
	callq	_Z13getIdleStreami
	movq	%rax, %r13
	movl	4(%rsp), %eax                   # 4-byte Reload
	cmpl	%eax, 8(%rsp)                   # 4-byte Folded Reload
	je	.LBB11_9
# %bb.8:                                #   in Loop: Header=BB11_7 Depth=2
	cmpl	%eax, %r15d
	je	.LBB11_9
# %bb.14:                               #   in Loop: Header=BB11_7 Depth=2
	movq	64(%rsp), %rdi                  # 8-byte Reload
	movl	$1, %esi
	movabsq	$137438953504, %rdx             # imm = 0x2000000020
	movl	$1, %ecx
	xorl	%r8d, %r8d
	movq	%r13, %r9
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB11_16
# %bb.15:                               #   in Loop: Header=BB11_7 Depth=2
	movl	n(%rip), %eax
	movl	4(%rsp), %edi                   # 4-byte Reload
	movl	%ebx, %esi
	movl	8(%rsp), %edx                   # 4-byte Reload
	movl	%r15d, %ecx
	movl	%r12d, %r8d
	movl	%r14d, %r9d
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	Dist(%rip)
	.cfi_adjust_cfa_offset 8
	callq	_Z32__device_stub__UpdateIndependentiiiiiiPii
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
	jmp	.LBB11_16
.LBB11_9:                               # %.preheader
                                        #   in Loop: Header=BB11_7 Depth=2
	cmpl	%ebx, %eax
	jge	.LBB11_16
# %bb.10:                               # %.lr.ph.preheader
                                        #   in Loop: Header=BB11_7 Depth=2
	movl	4(%rsp), %ebp                   # 4-byte Reload
.LBB11_11:                              # %.lr.ph
                                        #   Parent Loop BB11_2 Depth=1
                                        #     Parent Loop BB11_7 Depth=2
                                        # =>    This Inner Loop Header: Depth=3
	movq	64(%rsp), %rdi                  # 8-byte Reload
	movl	$1, %esi
	movabsq	$137438953504, %rdx             # imm = 0x2000000020
	movl	$1, %ecx
	xorl	%r8d, %r8d
	movq	%r13, %r9
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB11_13
# %bb.12:                               #   in Loop: Header=BB11_11 Depth=3
	movq	Dist(%rip), %r9
	movl	n(%rip), %eax
	subq	$8, %rsp
	.cfi_adjust_cfa_offset 8
	movl	%ebp, %edi
	movl	16(%rsp), %esi                  # 4-byte Reload
	movl	%r15d, %edx
	movl	%r12d, %ecx
	movl	%r14d, %r8d
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	callq	_Z21__device_stub__UpdateiiiiiPii
	addq	$16, %rsp
	.cfi_adjust_cfa_offset -16
.LBB11_13:                              #   in Loop: Header=BB11_11 Depth=3
	incl	%ebp
	cmpl	%ebp, %ebx
	jne	.LBB11_11
.LBB11_16:                              # %.loopexit
                                        #   in Loop: Header=BB11_7 Depth=2
	movl	44(%rsp), %r14d                 # 4-byte Reload
	cmpl	28(%rsp), %r14d                 # 4-byte Folded Reload
	jl	.LBB11_7
# %bb.17:                               #   in Loop: Header=BB11_2 Depth=1
	movl	24(%rsp), %ebx                  # 4-byte Reload
	jmp	.LBB11_4
.LBB11_3:                               # %.preheader79.._crit_edge_crit_edge
                                        #   in Loop: Header=BB11_2 Depth=1
	incl	%ebx
.LBB11_4:                               # %._crit_edge
                                        #   in Loop: Header=BB11_2 Depth=1
	cmpl	12(%rsp), %ebx                  # 4-byte Folded Reload
	jl	.LBB11_2
.LBB11_5:                               # %._crit_edge84
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end11:
	.size	_Z8calAsynciiiiiii, .Lfunc_end11-_Z8calAsynciiiiiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z21__device_stub__UpdateiiiiiPii # -- Begin function _Z21__device_stub__UpdateiiiiiPii
	.type	_Z21__device_stub__UpdateiiiiiPii,@function
_Z21__device_stub__UpdateiiiiiPii:      # @_Z21__device_stub__UpdateiiiiiPii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	192(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6UpdateiiiiiPii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end12:
	.size	_Z21__device_stub__UpdateiiiiiPii, .Lfunc_end12-_Z21__device_stub__UpdateiiiiiPii
	.cfi_endproc
                                        # -- End function
	.globl	_Z32__device_stub__UpdateIndependentiiiiiiPii # -- Begin function _Z32__device_stub__UpdateIndependentiiiiiiPii
	.type	_Z32__device_stub__UpdateIndependentiiiiiiPii,@function
_Z32__device_stub__UpdateIndependentiiiiiiPii: # @_Z32__device_stub__UpdateIndependentiiiiiiPii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	28(%rsp), %rax
	movl	%edi, (%rax)
	leaq	24(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	20(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	16(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	192(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	200(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17UpdateIndependentiiiiiiPii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end13:
	.size	_Z32__device_stub__UpdateIndependentiiiiiiPii, .Lfunc_end13-_Z32__device_stub__UpdateIndependentiiiiiiPii
	.cfi_endproc
                                        # -- End function
	.section	.text._ZNSt6vectorIP12ihipStream_tSaIS1_EE17_M_realloc_insertIJRKS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_,"axG",@progbits,_ZNSt6vectorIP12ihipStream_tSaIS1_EE17_M_realloc_insertIJRKS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_,comdat
	.weak	_ZNSt6vectorIP12ihipStream_tSaIS1_EE17_M_realloc_insertIJRKS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_ # -- Begin function _ZNSt6vectorIP12ihipStream_tSaIS1_EE17_M_realloc_insertIJRKS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_
	.p2align	1, 0x90
	.type	_ZNSt6vectorIP12ihipStream_tSaIS1_EE17_M_realloc_insertIJRKS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_,@function
_ZNSt6vectorIP12ihipStream_tSaIS1_EE17_M_realloc_insertIJRKS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_: # @_ZNSt6vectorIP12ihipStream_tSaIS1_EE17_M_realloc_insertIJRKS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rdx, (%rsp)                    # 8-byte Spill
	movq	%rsi, %r12
	movq	%rdi, %rbx
	movl	$1, %esi
	movl	$.L.str.8, %edx
	callq	_ZNKSt6vectorIP12ihipStream_tSaIS1_EE12_M_check_lenEmPKc
	movq	(%rbx), %r13
	movq	8(%rbx), %r15
	movq	%r12, 8(%rsp)                   # 8-byte Spill
	subq	%r13, %r12
	movq	%r12, %r14
	sarq	$3, %r14
	testq	%rax, %rax
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	je	.LBB14_1
# %bb.2:
	movq	%rbx, %rdi
	movq	%rax, %rsi
	xorl	%edx, %edx
	callq	_ZNSt15__new_allocatorIP12ihipStream_tE8allocateEmPKv
	movq	%rax, %rbp
	jmp	.LBB14_3
.LBB14_1:
	xorl	%ebp, %ebp
.LBB14_3:                               # %_ZNSt12_Vector_baseIP12ihipStream_tSaIS1_EE11_M_allocateEm.exit
	movq	(%rsp), %rax                    # 8-byte Reload
	movq	(%rax), %rax
	movq	%rax, (%rbp,%r14,8)
	testq	%r12, %r12
	jle	.LBB14_5
# %bb.4:
	movq	%rbp, %rdi
	movq	%r13, %rsi
	movq	%r12, %rdx
	callq	memmove@PLT
.LBB14_5:                               # %_ZNSt6vectorIP12ihipStream_tSaIS1_EE11_S_relocateEPS1_S4_S4_RS2_.exit
	addq	%rbp, %r12
	addq	$8, %r12
	movq	8(%rsp), %rsi                   # 8-byte Reload
	subq	%rsi, %r15
	testq	%r15, %r15
	jle	.LBB14_7
# %bb.6:
	movq	%r12, %rdi
	movq	%r15, %rdx
	callq	memmove@PLT
.LBB14_7:                               # %_ZNSt6vectorIP12ihipStream_tSaIS1_EE11_S_relocateEPS1_S4_S4_RS2_.exit16
	testq	%r13, %r13
	je	.LBB14_9
# %bb.8:
	movq	%r13, %rdi
	callq	_ZdlPv
.LBB14_9:                               # %_ZNSt12_Vector_baseIP12ihipStream_tSaIS1_EE13_M_deallocateEPS1_m.exit
	addq	%r15, %r12
	movq	%rbp, (%rbx)
	movq	%r12, 8(%rbx)
	movq	16(%rsp), %rax                  # 8-byte Reload
	leaq	(,%rax,8), %rax
	addq	%rbp, %rax
	movq	%rax, 16(%rbx)
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end14:
	.size	_ZNSt6vectorIP12ihipStream_tSaIS1_EE17_M_realloc_insertIJRKS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_, .Lfunc_end14-_ZNSt6vectorIP12ihipStream_tSaIS1_EE17_M_realloc_insertIJRKS1_EEEvN9__gnu_cxx17__normal_iteratorIPS1_S3_EEDpOT_
	.cfi_endproc
                                        # -- End function
	.section	.text._ZNKSt6vectorIP12ihipStream_tSaIS1_EE12_M_check_lenEmPKc,"axG",@progbits,_ZNKSt6vectorIP12ihipStream_tSaIS1_EE12_M_check_lenEmPKc,comdat
	.weak	_ZNKSt6vectorIP12ihipStream_tSaIS1_EE12_M_check_lenEmPKc # -- Begin function _ZNKSt6vectorIP12ihipStream_tSaIS1_EE12_M_check_lenEmPKc
	.p2align	1, 0x90
	.type	_ZNKSt6vectorIP12ihipStream_tSaIS1_EE12_M_check_lenEmPKc,@function
_ZNKSt6vectorIP12ihipStream_tSaIS1_EE12_M_check_lenEmPKc: # @_ZNKSt6vectorIP12ihipStream_tSaIS1_EE12_M_check_lenEmPKc
	.cfi_startproc
# %bb.0:
	movabsq	$1152921504606846975, %rcx      # imm = 0xFFFFFFFFFFFFFFF
	movq	8(%rdi), %r8
	subq	(%rdi), %r8
	sarq	$3, %r8
	movq	%rcx, %rax
	subq	%r8, %rax
	cmpq	%rsi, %rax
	jb	.LBB15_2
# %bb.1:
	cmpq	%rsi, %r8
	cmovaq	%r8, %rsi
	leaq	(%rsi,%r8), %rax
	cmpq	%rcx, %rax
	cmovaeq	%rcx, %rax
	addq	%r8, %rsi
	cmovbq	%rcx, %rax
	retq
.LBB15_2:
	pushq	%rax
	.cfi_def_cfa_offset 16
	movq	%rdx, %rdi
	callq	_ZSt20__throw_length_errorPKc
.Lfunc_end15:
	.size	_ZNKSt6vectorIP12ihipStream_tSaIS1_EE12_M_check_lenEmPKc, .Lfunc_end15-_ZNKSt6vectorIP12ihipStream_tSaIS1_EE12_M_check_lenEmPKc
	.cfi_endproc
                                        # -- End function
	.section	.text._ZNSt15__new_allocatorIP12ihipStream_tE8allocateEmPKv,"axG",@progbits,_ZNSt15__new_allocatorIP12ihipStream_tE8allocateEmPKv,comdat
	.weak	_ZNSt15__new_allocatorIP12ihipStream_tE8allocateEmPKv # -- Begin function _ZNSt15__new_allocatorIP12ihipStream_tE8allocateEmPKv
	.p2align	1, 0x90
	.type	_ZNSt15__new_allocatorIP12ihipStream_tE8allocateEmPKv,@function
_ZNSt15__new_allocatorIP12ihipStream_tE8allocateEmPKv: # @_ZNSt15__new_allocatorIP12ihipStream_tE8allocateEmPKv
	.cfi_startproc
# %bb.0:
	pushq	%rax
	.cfi_def_cfa_offset 16
	movq	%rsi, %rax
	shrq	$60, %rax
	jne	.LBB16_1
# %bb.3:
	shlq	$3, %rsi
	movq	%rsi, %rdi
	popq	%rax
	.cfi_def_cfa_offset 8
	jmp	_Znwm                           # TAILCALL
.LBB16_1:
	.cfi_def_cfa_offset 16
	shrq	$61, %rsi
	je	.LBB16_2
# %bb.4:
	callq	_ZSt28__throw_bad_array_new_lengthv
.LBB16_2:
	callq	_ZSt17__throw_bad_allocv
.Lfunc_end16:
	.size	_ZNSt15__new_allocatorIP12ihipStream_tE8allocateEmPKv, .Lfunc_end16-_ZNSt15__new_allocatorIP12ihipStream_tE8allocateEmPKv
	.cfi_endproc
                                        # -- End function
	.section	.text.startup,"ax",@progbits
	.type	_GLOBAL__sub_I_HW4_x1054037_2GPU_Unified_bug.hip,@function # -- Begin function _GLOBAL__sub_I_HW4_x1054037_2GPU_Unified_bug.hip
_GLOBAL__sub_I_HW4_x1054037_2GPU_Unified_bug.hip: # @_GLOBAL__sub_I_HW4_x1054037_2GPU_Unified_bug.hip
	.cfi_startproc
# %bb.0:
	xorps	%xmm0, %xmm0
	movaps	%xmm0, streams+32(%rip)
	movaps	%xmm0, streams+16(%rip)
	movaps	%xmm0, streams(%rip)
	movl	$__cxx_global_array_dtor, %edi
	movl	$__dso_handle, %edx
	xorl	%esi, %esi
	jmp	__cxa_atexit                    # TAILCALL
.Lfunc_end17:
	.size	_GLOBAL__sub_I_HW4_x1054037_2GPU_Unified_bug.hip, .Lfunc_end17-_GLOBAL__sub_I_HW4_x1054037_2GPU_Unified_bug.hip
	.cfi_endproc
                                        # -- End function
	.text
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB18_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB18_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6UpdateiiiiiPii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17UpdateIndependentiiiiiiPii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end18:
	.size	__hip_module_ctor, .Lfunc_end18-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB19_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB19_2:
	retq
.Lfunc_end19:
	.size	__hip_module_dtor, .Lfunc_end19-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	realn,@object                   # @realn
	.bss
	.globl	realn
	.p2align	2, 0x0
realn:
	.long	0                               # 0x0
	.size	realn, 4

	.type	n,@object                       # @n
	.globl	n
	.p2align	2, 0x0
n:
	.long	0                               # 0x0
	.size	n, 4

	.type	m,@object                       # @m
	.globl	m
	.p2align	2, 0x0
m:
	.long	0                               # 0x0
	.size	m, 4

	.type	Dist,@object                    # @Dist
	.globl	Dist
	.p2align	3, 0x0
Dist:
	.quad	0
	.size	Dist, 8

	.type	dDist,@object                   # @dDist
	.globl	dDist
	.p2align	4, 0x0
dDist:
	.zero	16
	.size	dDist, 16

	.type	streamSize,@object              # @streamSize
	.globl	streamSize
	.p2align	2, 0x0
streamSize:
	.zero	8
	.size	streamSize, 8

	.type	streams,@object                 # @streams
	.globl	streams
	.p2align	4, 0x0
streams:
	.zero	48
	.size	streams, 48

	.hidden	__dso_handle
	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"r"
	.size	.L.str, 2

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"%d %d"
	.size	.L.str.1, 6

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"%d %d %d"
	.size	.L.str.2, 9

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"w"
	.size	.L.str.3, 2

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"INF "
	.size	.L.str.4, 5

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"%d "
	.size	.L.str.5, 4

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"Round: %d\n"
	.size	.L.str.7, 11

	.type	_Z6UpdateiiiiiPii,@object       # @_Z6UpdateiiiiiPii
	.section	.rodata,"a",@progbits
	.globl	_Z6UpdateiiiiiPii
	.p2align	3, 0x0
_Z6UpdateiiiiiPii:
	.quad	_Z21__device_stub__UpdateiiiiiPii
	.size	_Z6UpdateiiiiiPii, 8

	.type	_Z17UpdateIndependentiiiiiiPii,@object # @_Z17UpdateIndependentiiiiiiPii
	.globl	_Z17UpdateIndependentiiiiiiPii
	.p2align	3, 0x0
_Z17UpdateIndependentiiiiiiPii:
	.quad	_Z32__device_stub__UpdateIndependentiiiiiiPii
	.size	_Z17UpdateIndependentiiiiiiPii, 8

	.type	.L.str.8,@object                # @.str.8
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.8:
	.asciz	"vector::_M_realloc_insert"
	.size	.L.str.8, 26

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z6UpdateiiiiiPii"
	.size	.L__unnamed_1, 18

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z17UpdateIndependentiiiiiiPii"
	.size	.L__unnamed_2, 31

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	_GLOBAL__sub_I_HW4_x1054037_2GPU_Unified_bug.hip
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __cxx_global_array_dtor
	.addrsig_sym _Z21__device_stub__UpdateiiiiiPii
	.addrsig_sym _Z32__device_stub__UpdateIndependentiiiiiiPii
	.addrsig_sym __gxx_personality_v0
	.addrsig_sym _GLOBAL__sub_I_HW4_x1054037_2GPU_Unified_bug.hip
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym realn
	.addrsig_sym m
	.addrsig_sym Dist
	.addrsig_sym streams
	.addrsig_sym __dso_handle
	.addrsig_sym _Z6UpdateiiiiiPii
	.addrsig_sym _Z17UpdateIndependentiiiiiiPii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z6UpdateiiiiiPii       ; -- Begin function _Z6UpdateiiiiiPii
	.globl	_Z6UpdateiiiiiPii
	.p2align	8
	.type	_Z6UpdateiiiiiPii,@function
_Z6UpdateiiiiiPii:                      ; @_Z6UpdateiiiiiPii
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x34
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s3, s[0:1], 0x10
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s8, s2, 0xffff
	s_lshr_b32 s2, s2, 16
	s_mul_i32 s14, s14, s8
	s_mul_i32 s15, s15, s2
	v_add3_u32 v1, s14, s5, v1
	v_add3_u32 v0, s15, s6, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s7, v1
	v_cmp_gt_i32_e64 s2, s3, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_3
; %bb.1:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x20
	s_load_b64 s[0:1], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	v_mul_lo_u32 v4, v1, s2
	v_mad_u64_u32 v[1:2], null, s2, s4, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, s4, v4
	v_ashrrev_i32_e32 v2, 31, v1
	v_add_nc_u32_e32 v5, v4, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v6, 31, v5
	v_lshlrev_b64 v[2:3], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[4:5], 2, v[5:6]
	v_add_co_u32 v6, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v4
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v5, vcc_lo
	s_clause 0x2
	global_load_b32 v4, v[6:7], off
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[0:1], off
	s_waitcnt vmcnt(1)
	v_add_nc_u32_e32 v2, v4, v2
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_i32_e32 vcc_lo, v2, v3
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_3
; %bb.2:
	global_store_b32 v[0:1], v2, off
.LBB0_3:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6UpdateiiiiiPii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z6UpdateiiiiiPii, .Lfunc_end0-_Z6UpdateiiiiiPii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 332
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z17UpdateIndependentiiiiiiPii ; -- Begin function _Z17UpdateIndependentiiiiiiPii
	.globl	_Z17UpdateIndependentiiiiiiPii
	.p2align	8
	.type	_Z17UpdateIndependentiiiiiiPii,@function
_Z17UpdateIndependentiiiiiiPii:         ; @_Z17UpdateIndependentiiiiiiPii
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x34
	s_load_b256 s[4:11], s[0:1], 0x0
	v_bfe_u32 v1, v0, 10, 10
	s_load_b32 s2, s[0:1], 0x20
	v_dual_mov_b32 v7, 0 :: v_dual_and_b32 v6, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s0, s3, 0xffff
	v_add_nc_u32_e32 v4, s7, v1
	s_lshr_b32 s1, s3, 16
	s_mul_i32 s14, s14, s0
	s_mul_i32 s15, s15, s1
	v_add3_u32 v5, s14, s6, v6
	v_add_nc_u32_e32 v0, s15, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s8, v5
	v_cmp_gt_i32_e64 s0, s9, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s0
	s_and_saveexec_b32 s6, s3
	s_cbranch_execz .LBB1_2
; %bb.1:
	v_mad_u64_u32 v[2:3], null, v5, s2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v2, s1, s10, v2
	v_add_co_ci_u32_e64 v3, s1, s11, v3, s1
	global_load_b32 v7, v[2:3], off
.LBB1_2:
	s_or_b32 exec_lo, exec_lo, s6
	s_cmp_ge_i32 s4, s5
	s_cbranch_scc1 .LBB1_15
; %bb.3:                                ; %.lr.ph
	v_add_nc_u32_e32 v2, s4, v6
	v_lshlrev_b32_e32 v8, 2, v6
	v_lshlrev_b32_e32 v9, 2, v1
	v_lshlrev_b32_e32 v11, 7, v6
	s_mov_b32 s6, 0
	v_mul_lo_u32 v10, s2, v2
	v_mad_u64_u32 v[2:3], null, v5, s2, v[1:2]
	v_lshl_add_u32 v8, v1, 7, v8
	v_add3_u32 v9, v11, v9, 0x1000
	s_delay_alu instid0(VALU_DEP_4)
	v_add3_u32 v3, v4, v10, s15
.LBB1_4:                                ; =>This Inner Loop Header: Depth=1
	s_cmp_lg_u32 s6, 0
	s_cbranch_scc1 .LBB1_12
; %bb.5:                                ;   in Loop: Header=BB1_4 Depth=1
	s_waitcnt vmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_and_saveexec_b32 s7, vcc_lo
	s_cbranch_execz .LBB1_8
; %bb.6:                                ;   in Loop: Header=BB1_4 Depth=1
	v_add_nc_u32_e32 v4, s4, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s1, s5, v4
	s_and_b32 exec_lo, exec_lo, s1
	s_cbranch_execz .LBB1_8
; %bb.7:                                ;   in Loop: Header=BB1_4 Depth=1
	v_add_nc_u32_e32 v10, s4, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v11, 31, v10
	v_lshlrev_b64 v[10:11], 2, v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v10, s1, s10, v10
	v_add_co_ci_u32_e64 v11, s1, s11, v11, s1
	global_load_b32 v4, v[10:11], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v8, v4
.LBB1_8:                                ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_and_saveexec_b32 s7, s0
	s_cbranch_execz .LBB1_11
; %bb.9:                                ;   in Loop: Header=BB1_4 Depth=1
	v_add_nc_u32_e32 v4, s4, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s1, s5, v4
	s_and_b32 exec_lo, exec_lo, s1
	s_cbranch_execz .LBB1_11
; %bb.10:                               ;   in Loop: Header=BB1_4 Depth=1
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[10:11], 2, v[3:4]
	v_add_co_u32 v10, s1, s10, v10
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v11, s1, s11, v11, s1
	global_load_b32 v4, v[10:11], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v9, v4
.LBB1_11:                               ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB1_12:                               ;   in Loop: Header=BB1_4 Depth=1
	s_and_saveexec_b32 s1, s3
	s_cbranch_execz .LBB1_14
; %bb.13:                               ;   in Loop: Header=BB1_4 Depth=1
	s_lshl_b32 s7, s6, 7
	s_delay_alu instid0(SALU_CYCLE_1)
	v_lshl_add_u32 v4, v6, 2, s7
	v_lshl_add_u32 v10, v1, 2, s7
	ds_load_b32 v4, v4
	ds_load_b32 v10, v10 offset:4096
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v4, v10, v4
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_min_i32_e32 v7, v4, v7
.LBB1_14:                               ;   in Loop: Header=BB1_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_add_i32 s1, s6, 1
	v_add_nc_u32_e32 v3, s2, v3
	s_ashr_i32 s6, s1, 31
	s_add_i32 s4, s4, 1
	s_lshr_b32 s6, s6, 27
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s6, s1, s6
	s_and_not1_b32 s6, s6, 31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_sub_i32 s6, s1, s6
	s_cmp_ge_i32 s4, s5
	s_cbranch_scc0 .LBB1_4
.LBB1_15:                               ; %Flow104
	s_and_saveexec_b32 s0, s3
	s_cbranch_execz .LBB1_17
; %bb.16:
	v_mad_u64_u32 v[1:2], null, v5, s2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v7, off
.LBB1_17:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17UpdateIndependentiiiiiiPii
		.amdhsa_group_segment_fixed_size 8192
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z17UpdateIndependentiiiiiiPii, .Lfunc_end1-_Z17UpdateIndependentiiiiiiPii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 672
; NumSgprs: 18
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8192 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6UpdateiiiiiPii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z6UpdateiiiiiPii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 8192
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z17UpdateIndependentiiiiiiPii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z17UpdateIndependentiiiiiiPii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
