#include <cuComplex.h>

__global__ void get_Gj(double *Fj, double *ph, cuDoubleComplex *Gj)
{
    int idx = threadIdx.x + blockIdx.x * blockDim.x;
    double s, c;
    sincos(ph[idx], &s, &c);
    Gj[idx].x = Fj[idx] * c;
    Gj[idx].y = Fj[idx] * s;
 }

__global__ void mult_complex_1to1(cuDoubleComplex *A, cuDoubleComplex *B, cuDoubleComplex *C)
{
    int idx = threadIdx.x + blockIdx.x * blockDim.x + blockIdx.y * blockDim.x * gridDim.x;
    C[idx] = cuCmul(A[idx], B[idx]);
}

__global__ void mult_complex_1ton(cuDoubleComplex *A, cuDoubleComplex *B, cuDoubleComplex *C)
{
    int tid = threadIdx.x + blockIdx.x * blockDim.x;
    int idx = tid + blockIdx.y * blockDim.x * gridDim.x;
    C[idx] = cuCmul(A[tid], B[idx]);
}

__global__ void get_E_Gwkj(double *Fk, cuDoubleComplex *Gkj, double *E, cuDoubleComplex *Gwkj)
{
    int idx = threadIdx.x + blockIdx.x * blockDim.x + blockIdx.y * blockDim.x * gridDim.x;
    double absGkj = cuCabs(Gkj[idx]);
    E[idx] = (Fk[idx] - absGkj) * (Fk[idx] - absGkj);
    cuDoubleComplex expGkj = cuCdiv(Gkj[idx], make_cuDoubleComplex(absGkj, 0));
    Gwkj[idx] = cuCsub(cuCmul(make_cuDoubleComplex(Fk[idx], 0), expGkj), Gkj[idx]);
}

__global__ void sum_E(int num, double *E)
{
    int idx = threadIdx.x + blockIdx.x * blockDim.x;
    double Esum = E[idx];
    for(int s = num-1; s > 0; s--)
        Esum += E[idx + s * blockDim.x * gridDim.x];
    E[idx] = Esum;
}

__global__ void sum_Etot(double *E, double *Ered)
{
    extern __shared__ double share[];
    int tid = threadIdx.x;
    int idx = tid + blockIdx.x * blockDim.x * 2;
    share[tid] = E[idx] + E[idx+blockDim.x];
    __syncthreads();
    for(unsigned int s = blockDim.x/2; s > 0; s >>= 1)
    {
        if(tid < s)
        {
            share[tid] += share[tid+s];
        }
       __syncthreads();
    }
    if(tid == 0)
        Ered[blockIdx.x] = share[0];
}

__global__ void get_dE(int num, cuDoubleComplex *Gj, cuDoubleComplex *Gwjk, double *dE)
{
    int idx = threadIdx.x + blockIdx.x * blockDim.x;
    double reGwjk = Gwjk[idx].x;
    double imGwjk = -Gwjk[idx].y;
    for(int s = num-1; s > 0; s--)
    {
        reGwjk += Gwjk[idx + s * blockDim.x * gridDim.x].x;
        imGwjk -= Gwjk[idx + s * blockDim.x * gridDim.x].y;
    }
    dE[idx] = (Gj[idx].x * imGwjk + Gj[idx].y * reGwjk) * 2;
}

__global__ void mult_T(int N, double z, double wl, double *r2, cuDoubleComplex *U)
{
    int idx = threadIdx.x + blockIdx.x * blockDim.x;
    double s, c;
    cuDoubleComplex u = U[idx];
    double ph = z * sqrt(1 / wl / wl - r2[idx] / N / N) * 2;
    sincospi(ph, &s, &c);
    U[idx].x = u.x * c - u.y * s;
    U[idx].y = u.x * s + u.y * c;
}

__global__ void mult_ph12(int N, double z, double wl, double *r2, cuDoubleComplex *U)
{
    int idx = threadIdx.x + blockIdx.x * blockDim.x;
    double s, c;
    cuDoubleComplex u = U[idx];
    double ph = 2 * z / wl + r2[idx] / wl / z;
    sincospi(ph, &s, &c);
    U[idx].x = (u.x * s + u.y * c) / N;
    U[idx].y = (-u.x * c + u.y * s) / N;
}

__global__ void mult_ph1(int N, double z, double wl, cuDoubleComplex *U)
{
    int idx = threadIdx.x + blockIdx.x * blockDim.x;
    double s, c;
    cuDoubleComplex u = U[idx];
    double ph = 2 * z / wl;
    sincospi(ph, &s, &c);
    U[idx].x = -(u.x * s + u.y * c) * N;
    U[idx].y = (u.x * c - u.y * s) * N;
}

__global__ void mult_ph2(int N, double z, double wl, double *r2, cuDoubleComplex *U)
{
    int idx = threadIdx.x + blockIdx.x * blockDim.x;
    double s, c;
    cuDoubleComplex u = U[idx];
    double ph = r2[idx] / wl / z;
    sincospi(ph, &s, &c);
    U[idx].x = u.x * c - u.y * s;
    U[idx].y = u.x * s + u.y * c;
}

	.file	"tmpxft_002bdceb_00000000-6_kernels.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2033:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2033:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z36__device_stub__Z6get_GjPdS_P7double2PdS_P7double2
	.type	_Z36__device_stub__Z6get_GjPdS_P7double2PdS_P7double2, @function
_Z36__device_stub__Z6get_GjPdS_P7double2PdS_P7double2:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z6get_GjPdS_P7double2(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L2:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z36__device_stub__Z6get_GjPdS_P7double2PdS_P7double2, .-_Z36__device_stub__Z6get_GjPdS_P7double2PdS_P7double2
	.globl	_Z6get_GjPdS_P7double2
	.type	_Z6get_GjPdS_P7double2, @function
_Z6get_GjPdS_P7double2:
.LFB2056:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z6get_GjPdS_P7double2PdS_P7double2
	.cfi_endproc
.LFE2056:
	.size	_Z6get_GjPdS_P7double2, .-_Z6get_GjPdS_P7double2
	.globl	_Z50__device_stub__Z17mult_complex_1to1P7double2S0_S0_P7double2S0_S0_
	.type	_Z50__device_stub__Z17mult_complex_1to1P7double2S0_S0_P7double2S0_S0_, @function
_Z50__device_stub__Z17mult_complex_1to1P7double2S0_S0_P7double2S0_S0_:
.LFB2057:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z17mult_complex_1to1P7double2S0_S0_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L8:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2057:
	.size	_Z50__device_stub__Z17mult_complex_1to1P7double2S0_S0_P7double2S0_S0_, .-_Z50__device_stub__Z17mult_complex_1to1P7double2S0_S0_P7double2S0_S0_
	.globl	_Z17mult_complex_1to1P7double2S0_S0_
	.type	_Z17mult_complex_1to1P7double2S0_S0_, @function
_Z17mult_complex_1to1P7double2S0_S0_:
.LFB2058:
	.cfi_startproc
	endbr64
	jmp	_Z50__device_stub__Z17mult_complex_1to1P7double2S0_S0_P7double2S0_S0_
	.cfi_endproc
.LFE2058:
	.size	_Z17mult_complex_1to1P7double2S0_S0_, .-_Z17mult_complex_1to1P7double2S0_S0_
	.globl	_Z50__device_stub__Z17mult_complex_1tonP7double2S0_S0_P7double2S0_S0_
	.type	_Z50__device_stub__Z17mult_complex_1tonP7double2S0_S0_P7double2S0_S0_, @function
_Z50__device_stub__Z17mult_complex_1tonP7double2S0_S0_P7double2S0_S0_:
.LFB2059:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z17mult_complex_1tonP7double2S0_S0_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L13:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2059:
	.size	_Z50__device_stub__Z17mult_complex_1tonP7double2S0_S0_P7double2S0_S0_, .-_Z50__device_stub__Z17mult_complex_1tonP7double2S0_S0_P7double2S0_S0_
	.globl	_Z17mult_complex_1tonP7double2S0_S0_
	.type	_Z17mult_complex_1tonP7double2S0_S0_, @function
_Z17mult_complex_1tonP7double2S0_S0_:
.LFB2060:
	.cfi_startproc
	endbr64
	jmp	_Z50__device_stub__Z17mult_complex_1tonP7double2S0_S0_P7double2S0_S0_
	.cfi_endproc
.LFE2060:
	.size	_Z17mult_complex_1tonP7double2S0_S0_, .-_Z17mult_complex_1tonP7double2S0_S0_
	.globl	_Z44__device_stub__Z10get_E_GwkjPdP7double2S_S1_PdP7double2S_S1_
	.type	_Z44__device_stub__Z10get_E_GwkjPdP7double2S_S1_PdP7double2S_S1_, @function
_Z44__device_stub__Z10get_E_GwkjPdP7double2S_S1_PdP7double2S_S1_:
.LFB2061:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z10get_E_GwkjPdP7double2S_S1_(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L18:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2061:
	.size	_Z44__device_stub__Z10get_E_GwkjPdP7double2S_S1_PdP7double2S_S1_, .-_Z44__device_stub__Z10get_E_GwkjPdP7double2S_S1_PdP7double2S_S1_
	.globl	_Z10get_E_GwkjPdP7double2S_S1_
	.type	_Z10get_E_GwkjPdP7double2S_S1_, @function
_Z10get_E_GwkjPdP7double2S_S1_:
.LFB2062:
	.cfi_startproc
	endbr64
	jmp	_Z44__device_stub__Z10get_E_GwkjPdP7double2S_S1_PdP7double2S_S1_
	.cfi_endproc
.LFE2062:
	.size	_Z10get_E_GwkjPdP7double2S_S1_, .-_Z10get_E_GwkjPdP7double2S_S1_
	.globl	_Z25__device_stub__Z5sum_EiPdiPd
	.type	_Z25__device_stub__Z5sum_EiPdiPd, @function
_Z25__device_stub__Z5sum_EiPdiPd:
.LFB2063:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movl	%edi, 12(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z5sum_EiPd(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L23:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L25
	call	__stack_chk_fail@PLT
.L25:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2063:
	.size	_Z25__device_stub__Z5sum_EiPdiPd, .-_Z25__device_stub__Z5sum_EiPdiPd
	.globl	_Z5sum_EiPd
	.type	_Z5sum_EiPd, @function
_Z5sum_EiPd:
.LFB2064:
	.cfi_startproc
	endbr64
	jmp	_Z25__device_stub__Z5sum_EiPdiPd
	.cfi_endproc
.LFE2064:
	.size	_Z5sum_EiPd, .-_Z5sum_EiPd
	.globl	_Z29__device_stub__Z8sum_EtotPdS_PdS_
	.type	_Z29__device_stub__Z8sum_EtotPdS_PdS_, @function
_Z29__device_stub__Z8sum_EtotPdS_PdS_:
.LFB2065:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L28
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z8sum_EtotPdS_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L28:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L30
	call	__stack_chk_fail@PLT
.L30:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2065:
	.size	_Z29__device_stub__Z8sum_EtotPdS_PdS_, .-_Z29__device_stub__Z8sum_EtotPdS_PdS_
	.globl	_Z8sum_EtotPdS_
	.type	_Z8sum_EtotPdS_, @function
_Z8sum_EtotPdS_:
.LFB2066:
	.cfi_startproc
	endbr64
	jmp	_Z29__device_stub__Z8sum_EtotPdS_PdS_
	.cfi_endproc
.LFE2066:
	.size	_Z8sum_EtotPdS_, .-_Z8sum_EtotPdS_
	.globl	_Z38__device_stub__Z6get_dEiP7double2S0_PdiP7double2S0_Pd
	.type	_Z38__device_stub__Z6get_dEiP7double2S0_PdiP7double2S0_Pd, @function
_Z38__device_stub__Z6get_dEiP7double2S0_PdiP7double2S0_Pd:
.LFB2067:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movl	%edi, 28(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L33
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z6get_dEiP7double2S0_Pd(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L33:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L35
	call	__stack_chk_fail@PLT
.L35:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2067:
	.size	_Z38__device_stub__Z6get_dEiP7double2S0_PdiP7double2S0_Pd, .-_Z38__device_stub__Z6get_dEiP7double2S0_PdiP7double2S0_Pd
	.globl	_Z6get_dEiP7double2S0_Pd
	.type	_Z6get_dEiP7double2S0_Pd, @function
_Z6get_dEiP7double2S0_Pd:
.LFB2068:
	.cfi_startproc
	endbr64
	jmp	_Z38__device_stub__Z6get_dEiP7double2S0_PdiP7double2S0_Pd
	.cfi_endproc
.LFE2068:
	.size	_Z6get_dEiP7double2S0_Pd, .-_Z6get_dEiP7double2S0_Pd
	.globl	_Z37__device_stub__Z6mult_TiddPdP7double2iddPdP7double2
	.type	_Z37__device_stub__Z6mult_TiddPdP7double2iddPdP7double2, @function
_Z37__device_stub__Z6mult_TiddPdP7double2iddPdP7double2:
.LFB2069:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movl	%edi, 44(%rsp)
	leaq	56(%rsp), %rcx
	leaq	64(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	48(%rsp), %rdx
	movsd	%xmm0, 32(%rsp)
	movsd	%xmm1, 24(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L38
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z6mult_TiddPdP7double2(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L38:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L40
	call	__stack_chk_fail@PLT
.L40:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2069:
	.size	_Z37__device_stub__Z6mult_TiddPdP7double2iddPdP7double2, .-_Z37__device_stub__Z6mult_TiddPdP7double2iddPdP7double2
	.globl	_Z6mult_TiddPdP7double2
	.type	_Z6mult_TiddPdP7double2, @function
_Z6mult_TiddPdP7double2:
.LFB2070:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z6mult_TiddPdP7double2iddPdP7double2
	.cfi_endproc
.LFE2070:
	.size	_Z6mult_TiddPdP7double2, .-_Z6mult_TiddPdP7double2
	.globl	_Z40__device_stub__Z9mult_ph12iddPdP7double2iddPdP7double2
	.type	_Z40__device_stub__Z9mult_ph12iddPdP7double2iddPdP7double2, @function
_Z40__device_stub__Z9mult_ph12iddPdP7double2iddPdP7double2:
.LFB2071:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movl	%edi, 44(%rsp)
	leaq	56(%rsp), %rcx
	leaq	64(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	48(%rsp), %rdx
	movsd	%xmm0, 32(%rsp)
	movsd	%xmm1, 24(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L43
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z9mult_ph12iddPdP7double2(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L43:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L45
	call	__stack_chk_fail@PLT
.L45:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2071:
	.size	_Z40__device_stub__Z9mult_ph12iddPdP7double2iddPdP7double2, .-_Z40__device_stub__Z9mult_ph12iddPdP7double2iddPdP7double2
	.globl	_Z9mult_ph12iddPdP7double2
	.type	_Z9mult_ph12iddPdP7double2, @function
_Z9mult_ph12iddPdP7double2:
.LFB2072:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z9mult_ph12iddPdP7double2iddPdP7double2
	.cfi_endproc
.LFE2072:
	.size	_Z9mult_ph12iddPdP7double2, .-_Z9mult_ph12iddPdP7double2
	.globl	_Z37__device_stub__Z8mult_ph1iddP7double2iddP7double2
	.type	_Z37__device_stub__Z8mult_ph1iddP7double2iddP7double2, @function
_Z37__device_stub__Z8mult_ph1iddP7double2iddP7double2:
.LFB2073:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movl	%edi, 28(%rsp)
	leaq	48(%rsp), %rcx
	leaq	40(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	56(%rsp), %rdi
	leaq	68(%rsp), %rsi
	movsd	%xmm0, 16(%rsp)
	movsd	%xmm1, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L48
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z8mult_ph1iddP7double2(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L48:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L50
	call	__stack_chk_fail@PLT
.L50:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2073:
	.size	_Z37__device_stub__Z8mult_ph1iddP7double2iddP7double2, .-_Z37__device_stub__Z8mult_ph1iddP7double2iddP7double2
	.globl	_Z8mult_ph1iddP7double2
	.type	_Z8mult_ph1iddP7double2, @function
_Z8mult_ph1iddP7double2:
.LFB2074:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z8mult_ph1iddP7double2iddP7double2
	.cfi_endproc
.LFE2074:
	.size	_Z8mult_ph1iddP7double2, .-_Z8mult_ph1iddP7double2
	.globl	_Z39__device_stub__Z8mult_ph2iddPdP7double2iddPdP7double2
	.type	_Z39__device_stub__Z8mult_ph2iddPdP7double2iddPdP7double2, @function
_Z39__device_stub__Z8mult_ph2iddPdP7double2iddPdP7double2:
.LFB2075:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movl	%edi, 44(%rsp)
	leaq	56(%rsp), %rcx
	leaq	64(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	48(%rsp), %rdx
	movsd	%xmm0, 32(%rsp)
	movsd	%xmm1, 24(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	44(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L53
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z8mult_ph2iddPdP7double2(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L53:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L55
	call	__stack_chk_fail@PLT
.L55:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2075:
	.size	_Z39__device_stub__Z8mult_ph2iddPdP7double2iddPdP7double2, .-_Z39__device_stub__Z8mult_ph2iddPdP7double2iddPdP7double2
	.globl	_Z8mult_ph2iddPdP7double2
	.type	_Z8mult_ph2iddPdP7double2, @function
_Z8mult_ph2iddPdP7double2:
.LFB2076:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z8mult_ph2iddPdP7double2iddPdP7double2
	.cfi_endproc
.LFE2076:
	.size	_Z8mult_ph2iddPdP7double2, .-_Z8mult_ph2iddPdP7double2
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z8mult_ph2iddPdP7double2"
.LC1:
	.string	"_Z8mult_ph1iddP7double2"
.LC2:
	.string	"_Z9mult_ph12iddPdP7double2"
.LC3:
	.string	"_Z6mult_TiddPdP7double2"
.LC4:
	.string	"_Z6get_dEiP7double2S0_Pd"
.LC5:
	.string	"_Z8sum_EtotPdS_"
.LC6:
	.string	"_Z5sum_EiPd"
.LC7:
	.string	"_Z10get_E_GwkjPdP7double2S_S1_"
.LC8:
	.string	"_Z17mult_complex_1tonP7double2S0_S0_"
.LC9:
	.string	"_Z17mult_complex_1to1P7double2S0_S0_"
.LC10:
	.string	"_Z6get_GjPdS_P7double2"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2078:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z8mult_ph2iddPdP7double2(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z8mult_ph1iddP7double2(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z9mult_ph12iddPdP7double2(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z6mult_TiddPdP7double2(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z6get_dEiP7double2S0_Pd(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z8sum_EtotPdS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z5sum_EiPd(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z10get_E_GwkjPdP7double2S_S1_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC8(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	movq	%rdx, %rcx
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_Z17mult_complex_1tonP7double2S0_S0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC9(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z17mult_complex_1to1P7double2S0_S0_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC10(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z6get_GjPdS_P7double2(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2078:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <hip/hip_complex.h>

__global__ void get_Gj(double *Fj, double *ph, hipDoubleComplex *Gj)
{
    int idx = threadIdx.x + blockIdx.x * blockDim.x;
    double s, c;
    sincos(ph[idx], &s, &c);
    Gj[idx].x = Fj[idx] * c;
    Gj[idx].y = Fj[idx] * s;
 }

__global__ void mult_complex_1to1(hipDoubleComplex *A, hipDoubleComplex *B, hipDoubleComplex *C)
{
    int idx = threadIdx.x + blockIdx.x * blockDim.x + blockIdx.y * blockDim.x * gridDim.x;
    C[idx] = hipCmul(A[idx], B[idx]);
}

__global__ void mult_complex_1ton(hipDoubleComplex *A, hipDoubleComplex *B, hipDoubleComplex *C)
{
    int tid = threadIdx.x + blockIdx.x * blockDim.x;
    int idx = tid + blockIdx.y * blockDim.x * gridDim.x;
    C[idx] = hipCmul(A[tid], B[idx]);
}

__global__ void get_E_Gwkj(double *Fk, hipDoubleComplex *Gkj, double *E, hipDoubleComplex *Gwkj)
{
    int idx = threadIdx.x + blockIdx.x * blockDim.x + blockIdx.y * blockDim.x * gridDim.x;
    double absGkj = hipCabs(Gkj[idx]);
    E[idx] = (Fk[idx] - absGkj) * (Fk[idx] - absGkj);
    hipDoubleComplex expGkj = hipCdiv(Gkj[idx], make_hipDoubleComplex(absGkj, 0));
    Gwkj[idx] = hipCsub(hipCmul(make_hipDoubleComplex(Fk[idx], 0), expGkj), Gkj[idx]);
}

__global__ void sum_E(int num, double *E)
{
    int idx = threadIdx.x + blockIdx.x * blockDim.x;
    double Esum = E[idx];
    for(int s = num-1; s > 0; s--)
        Esum += E[idx + s * blockDim.x * gridDim.x];
    E[idx] = Esum;
}

__global__ void sum_Etot(double *E, double *Ered)
{
    extern __shared__ double share[];
    int tid = threadIdx.x;
    int idx = tid + blockIdx.x * blockDim.x * 2;
    share[tid] = E[idx] + E[idx+blockDim.x];
    __syncthreads();
    for(unsigned int s = blockDim.x/2; s > 0; s >>= 1)
    {
        if(tid < s)
        {
            share[tid] += share[tid+s];
        }
       __syncthreads();
    }
    if(tid == 0)
        Ered[blockIdx.x] = share[0];
}

__global__ void get_dE(int num, hipDoubleComplex *Gj, hipDoubleComplex *Gwjk, double *dE)
{
    int idx = threadIdx.x + blockIdx.x * blockDim.x;
    double reGwjk = Gwjk[idx].x;
    double imGwjk = -Gwjk[idx].y;
    for(int s = num-1; s > 0; s--)
    {
        reGwjk += Gwjk[idx + s * blockDim.x * gridDim.x].x;
        imGwjk -= Gwjk[idx + s * blockDim.x * gridDim.x].y;
    }
    dE[idx] = (Gj[idx].x * imGwjk + Gj[idx].y * reGwjk) * 2;
}

__global__ void mult_T(int N, double z, double wl, double *r2, hipDoubleComplex *U)
{
    int idx = threadIdx.x + blockIdx.x * blockDim.x;
    double s, c;
    hipDoubleComplex u = U[idx];
    double ph = z * sqrt(1 / wl / wl - r2[idx] / N / N) * 2;
    sincospi(ph, &s, &c);
    U[idx].x = u.x * c - u.y * s;
    U[idx].y = u.x * s + u.y * c;
}

__global__ void mult_ph12(int N, double z, double wl, double *r2, hipDoubleComplex *U)
{
    int idx = threadIdx.x + blockIdx.x * blockDim.x;
    double s, c;
    hipDoubleComplex u = U[idx];
    double ph = 2 * z / wl + r2[idx] / wl / z;
    sincospi(ph, &s, &c);
    U[idx].x = (u.x * s + u.y * c) / N;
    U[idx].y = (-u.x * c + u.y * s) / N;
}

__global__ void mult_ph1(int N, double z, double wl, hipDoubleComplex *U)
{
    int idx = threadIdx.x + blockIdx.x * blockDim.x;
    double s, c;
    hipDoubleComplex u = U[idx];
    double ph = 2 * z / wl;
    sincospi(ph, &s, &c);
    U[idx].x = -(u.x * s + u.y * c) * N;
    U[idx].y = (u.x * c - u.y * s) * N;
}

__global__ void mult_ph2(int N, double z, double wl, double *r2, hipDoubleComplex *U)
{
    int idx = threadIdx.x + blockIdx.x * blockDim.x;
    double s, c;
    hipDoubleComplex u = U[idx];
    double ph = r2[idx] / wl / z;
    sincospi(ph, &s, &c);
    U[idx].x = u.x * c - u.y * s;
    U[idx].y = u.x * s + u.y * c;
}

	.text
	.file	"kernels.hip"
	.globl	_Z21__device_stub__get_GjPdS_P15HIP_vector_typeIdLj2EE # -- Begin function _Z21__device_stub__get_GjPdS_P15HIP_vector_typeIdLj2EE
	.type	_Z21__device_stub__get_GjPdS_P15HIP_vector_typeIdLj2EE,@function
_Z21__device_stub__get_GjPdS_P15HIP_vector_typeIdLj2EE: # @_Z21__device_stub__get_GjPdS_P15HIP_vector_typeIdLj2EE
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6get_GjPdS_P15HIP_vector_typeIdLj2EE, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z21__device_stub__get_GjPdS_P15HIP_vector_typeIdLj2EE, .Lfunc_end0-_Z21__device_stub__get_GjPdS_P15HIP_vector_typeIdLj2EE
	.cfi_endproc
                                        # -- End function
	.globl	_Z32__device_stub__mult_complex_1to1P15HIP_vector_typeIdLj2EES1_S1_ # -- Begin function _Z32__device_stub__mult_complex_1to1P15HIP_vector_typeIdLj2EES1_S1_
	.type	_Z32__device_stub__mult_complex_1to1P15HIP_vector_typeIdLj2EES1_S1_,@function
_Z32__device_stub__mult_complex_1to1P15HIP_vector_typeIdLj2EES1_S1_: # @_Z32__device_stub__mult_complex_1to1P15HIP_vector_typeIdLj2EES1_S1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17mult_complex_1to1P15HIP_vector_typeIdLj2EES1_S1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z32__device_stub__mult_complex_1to1P15HIP_vector_typeIdLj2EES1_S1_, .Lfunc_end1-_Z32__device_stub__mult_complex_1to1P15HIP_vector_typeIdLj2EES1_S1_
	.cfi_endproc
                                        # -- End function
	.globl	_Z32__device_stub__mult_complex_1tonP15HIP_vector_typeIdLj2EES1_S1_ # -- Begin function _Z32__device_stub__mult_complex_1tonP15HIP_vector_typeIdLj2EES1_S1_
	.type	_Z32__device_stub__mult_complex_1tonP15HIP_vector_typeIdLj2EES1_S1_,@function
_Z32__device_stub__mult_complex_1tonP15HIP_vector_typeIdLj2EES1_S1_: # @_Z32__device_stub__mult_complex_1tonP15HIP_vector_typeIdLj2EES1_S1_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17mult_complex_1tonP15HIP_vector_typeIdLj2EES1_S1_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z32__device_stub__mult_complex_1tonP15HIP_vector_typeIdLj2EES1_S1_, .Lfunc_end2-_Z32__device_stub__mult_complex_1tonP15HIP_vector_typeIdLj2EES1_S1_
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__get_E_GwkjPdP15HIP_vector_typeIdLj2EES_S2_ # -- Begin function _Z25__device_stub__get_E_GwkjPdP15HIP_vector_typeIdLj2EES_S2_
	.type	_Z25__device_stub__get_E_GwkjPdP15HIP_vector_typeIdLj2EES_S2_,@function
_Z25__device_stub__get_E_GwkjPdP15HIP_vector_typeIdLj2EES_S2_: # @_Z25__device_stub__get_E_GwkjPdP15HIP_vector_typeIdLj2EES_S2_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10get_E_GwkjPdP15HIP_vector_typeIdLj2EES_S2_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z25__device_stub__get_E_GwkjPdP15HIP_vector_typeIdLj2EES_S2_, .Lfunc_end3-_Z25__device_stub__get_E_GwkjPdP15HIP_vector_typeIdLj2EES_S2_
	.cfi_endproc
                                        # -- End function
	.globl	_Z20__device_stub__sum_EiPd     # -- Begin function _Z20__device_stub__sum_EiPd
	.type	_Z20__device_stub__sum_EiPd,@function
_Z20__device_stub__sum_EiPd:            # @_Z20__device_stub__sum_EiPd
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	leaq	24(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z5sum_EiPd, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z20__device_stub__sum_EiPd, .Lfunc_end4-_Z20__device_stub__sum_EiPd
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__sum_EtotPdS_ # -- Begin function _Z23__device_stub__sum_EtotPdS_
	.type	_Z23__device_stub__sum_EtotPdS_,@function
_Z23__device_stub__sum_EtotPdS_:        # @_Z23__device_stub__sum_EtotPdS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8sum_EtotPdS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z23__device_stub__sum_EtotPdS_, .Lfunc_end5-_Z23__device_stub__sum_EtotPdS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z21__device_stub__get_dEiP15HIP_vector_typeIdLj2EES1_Pd # -- Begin function _Z21__device_stub__get_dEiP15HIP_vector_typeIdLj2EES1_Pd
	.type	_Z21__device_stub__get_dEiP15HIP_vector_typeIdLj2EES1_Pd,@function
_Z21__device_stub__get_dEiP15HIP_vector_typeIdLj2EES1_Pd: # @_Z21__device_stub__get_dEiP15HIP_vector_typeIdLj2EES1_Pd
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	24(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6get_dEiP15HIP_vector_typeIdLj2EES1_Pd, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z21__device_stub__get_dEiP15HIP_vector_typeIdLj2EES1_Pd, .Lfunc_end6-_Z21__device_stub__get_dEiP15HIP_vector_typeIdLj2EES1_Pd
	.cfi_endproc
                                        # -- End function
	.globl	_Z21__device_stub__mult_TiddPdP15HIP_vector_typeIdLj2EE # -- Begin function _Z21__device_stub__mult_TiddPdP15HIP_vector_typeIdLj2EE
	.type	_Z21__device_stub__mult_TiddPdP15HIP_vector_typeIdLj2EE,@function
_Z21__device_stub__mult_TiddPdP15HIP_vector_typeIdLj2EE: # @_Z21__device_stub__mult_TiddPdP15HIP_vector_typeIdLj2EE
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	56(%rsp), %rcx
	movsd	%xmm0, (%rcx)
	leaq	48(%rsp), %rdi
	movsd	%xmm1, (%rdi)
	leaq	40(%rsp), %r8
	movq	%rsi, (%r8)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rdi, 16(%rbx)
	movq	%r8, 24(%rbx)
	movq	%rsi, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6mult_TiddPdP15HIP_vector_typeIdLj2EE, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_Z21__device_stub__mult_TiddPdP15HIP_vector_typeIdLj2EE, .Lfunc_end7-_Z21__device_stub__mult_TiddPdP15HIP_vector_typeIdLj2EE
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__mult_ph12iddPdP15HIP_vector_typeIdLj2EE # -- Begin function _Z24__device_stub__mult_ph12iddPdP15HIP_vector_typeIdLj2EE
	.type	_Z24__device_stub__mult_ph12iddPdP15HIP_vector_typeIdLj2EE,@function
_Z24__device_stub__mult_ph12iddPdP15HIP_vector_typeIdLj2EE: # @_Z24__device_stub__mult_ph12iddPdP15HIP_vector_typeIdLj2EE
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	56(%rsp), %rcx
	movsd	%xmm0, (%rcx)
	leaq	48(%rsp), %rdi
	movsd	%xmm1, (%rdi)
	leaq	40(%rsp), %r8
	movq	%rsi, (%r8)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rdi, 16(%rbx)
	movq	%r8, 24(%rbx)
	movq	%rsi, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9mult_ph12iddPdP15HIP_vector_typeIdLj2EE, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end8:
	.size	_Z24__device_stub__mult_ph12iddPdP15HIP_vector_typeIdLj2EE, .Lfunc_end8-_Z24__device_stub__mult_ph12iddPdP15HIP_vector_typeIdLj2EE
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__mult_ph1iddP15HIP_vector_typeIdLj2EE # -- Begin function _Z23__device_stub__mult_ph1iddP15HIP_vector_typeIdLj2EE
	.type	_Z23__device_stub__mult_ph1iddP15HIP_vector_typeIdLj2EE,@function
_Z23__device_stub__mult_ph1iddP15HIP_vector_typeIdLj2EE: # @_Z23__device_stub__mult_ph1iddP15HIP_vector_typeIdLj2EE
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rcx
	movsd	%xmm0, (%rcx)
	leaq	32(%rsp), %rdx
	movsd	%xmm1, (%rdx)
	leaq	24(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rdx, 16(%rbx)
	movq	%rdi, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8mult_ph1iddP15HIP_vector_typeIdLj2EE, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end9:
	.size	_Z23__device_stub__mult_ph1iddP15HIP_vector_typeIdLj2EE, .Lfunc_end9-_Z23__device_stub__mult_ph1iddP15HIP_vector_typeIdLj2EE
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__mult_ph2iddPdP15HIP_vector_typeIdLj2EE # -- Begin function _Z23__device_stub__mult_ph2iddPdP15HIP_vector_typeIdLj2EE
	.type	_Z23__device_stub__mult_ph2iddPdP15HIP_vector_typeIdLj2EE,@function
_Z23__device_stub__mult_ph2iddPdP15HIP_vector_typeIdLj2EE: # @_Z23__device_stub__mult_ph2iddPdP15HIP_vector_typeIdLj2EE
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	56(%rsp), %rcx
	movsd	%xmm0, (%rcx)
	leaq	48(%rsp), %rdi
	movsd	%xmm1, (%rdi)
	leaq	40(%rsp), %r8
	movq	%rsi, (%r8)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rdi, 16(%rbx)
	movq	%r8, 24(%rbx)
	movq	%rsi, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8mult_ph2iddPdP15HIP_vector_typeIdLj2EE, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end10:
	.size	_Z23__device_stub__mult_ph2iddPdP15HIP_vector_typeIdLj2EE, .Lfunc_end10-_Z23__device_stub__mult_ph2iddPdP15HIP_vector_typeIdLj2EE
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB11_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB11_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6get_GjPdS_P15HIP_vector_typeIdLj2EE, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17mult_complex_1to1P15HIP_vector_typeIdLj2EES1_S1_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17mult_complex_1tonP15HIP_vector_typeIdLj2EES1_S1_, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10get_E_GwkjPdP15HIP_vector_typeIdLj2EES_S2_, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z5sum_EiPd, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8sum_EtotPdS_, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6get_dEiP15HIP_vector_typeIdLj2EES1_Pd, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6mult_TiddPdP15HIP_vector_typeIdLj2EE, %esi
	movl	$.L__unnamed_8, %edx
	movl	$.L__unnamed_8, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9mult_ph12iddPdP15HIP_vector_typeIdLj2EE, %esi
	movl	$.L__unnamed_9, %edx
	movl	$.L__unnamed_9, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8mult_ph1iddP15HIP_vector_typeIdLj2EE, %esi
	movl	$.L__unnamed_10, %edx
	movl	$.L__unnamed_10, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8mult_ph2iddPdP15HIP_vector_typeIdLj2EE, %esi
	movl	$.L__unnamed_11, %edx
	movl	$.L__unnamed_11, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end11:
	.size	__hip_module_ctor, .Lfunc_end11-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB12_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB12_2:
	retq
.Lfunc_end12:
	.size	__hip_module_dtor, .Lfunc_end12-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z6get_GjPdS_P15HIP_vector_typeIdLj2EE,@object # @_Z6get_GjPdS_P15HIP_vector_typeIdLj2EE
	.section	.rodata,"a",@progbits
	.globl	_Z6get_GjPdS_P15HIP_vector_typeIdLj2EE
	.p2align	3, 0x0
_Z6get_GjPdS_P15HIP_vector_typeIdLj2EE:
	.quad	_Z21__device_stub__get_GjPdS_P15HIP_vector_typeIdLj2EE
	.size	_Z6get_GjPdS_P15HIP_vector_typeIdLj2EE, 8

	.type	_Z17mult_complex_1to1P15HIP_vector_typeIdLj2EES1_S1_,@object # @_Z17mult_complex_1to1P15HIP_vector_typeIdLj2EES1_S1_
	.globl	_Z17mult_complex_1to1P15HIP_vector_typeIdLj2EES1_S1_
	.p2align	3, 0x0
_Z17mult_complex_1to1P15HIP_vector_typeIdLj2EES1_S1_:
	.quad	_Z32__device_stub__mult_complex_1to1P15HIP_vector_typeIdLj2EES1_S1_
	.size	_Z17mult_complex_1to1P15HIP_vector_typeIdLj2EES1_S1_, 8

	.type	_Z17mult_complex_1tonP15HIP_vector_typeIdLj2EES1_S1_,@object # @_Z17mult_complex_1tonP15HIP_vector_typeIdLj2EES1_S1_
	.globl	_Z17mult_complex_1tonP15HIP_vector_typeIdLj2EES1_S1_
	.p2align	3, 0x0
_Z17mult_complex_1tonP15HIP_vector_typeIdLj2EES1_S1_:
	.quad	_Z32__device_stub__mult_complex_1tonP15HIP_vector_typeIdLj2EES1_S1_
	.size	_Z17mult_complex_1tonP15HIP_vector_typeIdLj2EES1_S1_, 8

	.type	_Z10get_E_GwkjPdP15HIP_vector_typeIdLj2EES_S2_,@object # @_Z10get_E_GwkjPdP15HIP_vector_typeIdLj2EES_S2_
	.globl	_Z10get_E_GwkjPdP15HIP_vector_typeIdLj2EES_S2_
	.p2align	3, 0x0
_Z10get_E_GwkjPdP15HIP_vector_typeIdLj2EES_S2_:
	.quad	_Z25__device_stub__get_E_GwkjPdP15HIP_vector_typeIdLj2EES_S2_
	.size	_Z10get_E_GwkjPdP15HIP_vector_typeIdLj2EES_S2_, 8

	.type	_Z5sum_EiPd,@object             # @_Z5sum_EiPd
	.globl	_Z5sum_EiPd
	.p2align	3, 0x0
_Z5sum_EiPd:
	.quad	_Z20__device_stub__sum_EiPd
	.size	_Z5sum_EiPd, 8

	.type	_Z8sum_EtotPdS_,@object         # @_Z8sum_EtotPdS_
	.globl	_Z8sum_EtotPdS_
	.p2align	3, 0x0
_Z8sum_EtotPdS_:
	.quad	_Z23__device_stub__sum_EtotPdS_
	.size	_Z8sum_EtotPdS_, 8

	.type	_Z6get_dEiP15HIP_vector_typeIdLj2EES1_Pd,@object # @_Z6get_dEiP15HIP_vector_typeIdLj2EES1_Pd
	.globl	_Z6get_dEiP15HIP_vector_typeIdLj2EES1_Pd
	.p2align	3, 0x0
_Z6get_dEiP15HIP_vector_typeIdLj2EES1_Pd:
	.quad	_Z21__device_stub__get_dEiP15HIP_vector_typeIdLj2EES1_Pd
	.size	_Z6get_dEiP15HIP_vector_typeIdLj2EES1_Pd, 8

	.type	_Z6mult_TiddPdP15HIP_vector_typeIdLj2EE,@object # @_Z6mult_TiddPdP15HIP_vector_typeIdLj2EE
	.globl	_Z6mult_TiddPdP15HIP_vector_typeIdLj2EE
	.p2align	3, 0x0
_Z6mult_TiddPdP15HIP_vector_typeIdLj2EE:
	.quad	_Z21__device_stub__mult_TiddPdP15HIP_vector_typeIdLj2EE
	.size	_Z6mult_TiddPdP15HIP_vector_typeIdLj2EE, 8

	.type	_Z9mult_ph12iddPdP15HIP_vector_typeIdLj2EE,@object # @_Z9mult_ph12iddPdP15HIP_vector_typeIdLj2EE
	.globl	_Z9mult_ph12iddPdP15HIP_vector_typeIdLj2EE
	.p2align	3, 0x0
_Z9mult_ph12iddPdP15HIP_vector_typeIdLj2EE:
	.quad	_Z24__device_stub__mult_ph12iddPdP15HIP_vector_typeIdLj2EE
	.size	_Z9mult_ph12iddPdP15HIP_vector_typeIdLj2EE, 8

	.type	_Z8mult_ph1iddP15HIP_vector_typeIdLj2EE,@object # @_Z8mult_ph1iddP15HIP_vector_typeIdLj2EE
	.globl	_Z8mult_ph1iddP15HIP_vector_typeIdLj2EE
	.p2align	3, 0x0
_Z8mult_ph1iddP15HIP_vector_typeIdLj2EE:
	.quad	_Z23__device_stub__mult_ph1iddP15HIP_vector_typeIdLj2EE
	.size	_Z8mult_ph1iddP15HIP_vector_typeIdLj2EE, 8

	.type	_Z8mult_ph2iddPdP15HIP_vector_typeIdLj2EE,@object # @_Z8mult_ph2iddPdP15HIP_vector_typeIdLj2EE
	.globl	_Z8mult_ph2iddPdP15HIP_vector_typeIdLj2EE
	.p2align	3, 0x0
_Z8mult_ph2iddPdP15HIP_vector_typeIdLj2EE:
	.quad	_Z23__device_stub__mult_ph2iddPdP15HIP_vector_typeIdLj2EE
	.size	_Z8mult_ph2iddPdP15HIP_vector_typeIdLj2EE, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z6get_GjPdS_P15HIP_vector_typeIdLj2EE"
	.size	.L__unnamed_1, 39

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z17mult_complex_1to1P15HIP_vector_typeIdLj2EES1_S1_"
	.size	.L__unnamed_2, 53

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z17mult_complex_1tonP15HIP_vector_typeIdLj2EES1_S1_"
	.size	.L__unnamed_3, 53

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z10get_E_GwkjPdP15HIP_vector_typeIdLj2EES_S2_"
	.size	.L__unnamed_4, 47

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z5sum_EiPd"
	.size	.L__unnamed_5, 12

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_Z8sum_EtotPdS_"
	.size	.L__unnamed_6, 16

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"_Z6get_dEiP15HIP_vector_typeIdLj2EES1_Pd"
	.size	.L__unnamed_7, 41

	.type	.L__unnamed_8,@object           # @7
.L__unnamed_8:
	.asciz	"_Z6mult_TiddPdP15HIP_vector_typeIdLj2EE"
	.size	.L__unnamed_8, 40

	.type	.L__unnamed_9,@object           # @8
.L__unnamed_9:
	.asciz	"_Z9mult_ph12iddPdP15HIP_vector_typeIdLj2EE"
	.size	.L__unnamed_9, 43

	.type	.L__unnamed_10,@object          # @9
.L__unnamed_10:
	.asciz	"_Z8mult_ph1iddP15HIP_vector_typeIdLj2EE"
	.size	.L__unnamed_10, 40

	.type	.L__unnamed_11,@object          # @10
.L__unnamed_11:
	.asciz	"_Z8mult_ph2iddPdP15HIP_vector_typeIdLj2EE"
	.size	.L__unnamed_11, 42

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z21__device_stub__get_GjPdS_P15HIP_vector_typeIdLj2EE
	.addrsig_sym _Z32__device_stub__mult_complex_1to1P15HIP_vector_typeIdLj2EES1_S1_
	.addrsig_sym _Z32__device_stub__mult_complex_1tonP15HIP_vector_typeIdLj2EES1_S1_
	.addrsig_sym _Z25__device_stub__get_E_GwkjPdP15HIP_vector_typeIdLj2EES_S2_
	.addrsig_sym _Z20__device_stub__sum_EiPd
	.addrsig_sym _Z23__device_stub__sum_EtotPdS_
	.addrsig_sym _Z21__device_stub__get_dEiP15HIP_vector_typeIdLj2EES1_Pd
	.addrsig_sym _Z21__device_stub__mult_TiddPdP15HIP_vector_typeIdLj2EE
	.addrsig_sym _Z24__device_stub__mult_ph12iddPdP15HIP_vector_typeIdLj2EE
	.addrsig_sym _Z23__device_stub__mult_ph1iddP15HIP_vector_typeIdLj2EE
	.addrsig_sym _Z23__device_stub__mult_ph2iddPdP15HIP_vector_typeIdLj2EE
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z6get_GjPdS_P15HIP_vector_typeIdLj2EE
	.addrsig_sym _Z17mult_complex_1to1P15HIP_vector_typeIdLj2EES1_S1_
	.addrsig_sym _Z17mult_complex_1tonP15HIP_vector_typeIdLj2EES1_S1_
	.addrsig_sym _Z10get_E_GwkjPdP15HIP_vector_typeIdLj2EES_S2_
	.addrsig_sym _Z5sum_EiPd
	.addrsig_sym _Z8sum_EtotPdS_
	.addrsig_sym _Z6get_dEiP15HIP_vector_typeIdLj2EES1_Pd
	.addrsig_sym _Z6mult_TiddPdP15HIP_vector_typeIdLj2EE
	.addrsig_sym _Z9mult_ph12iddPdP15HIP_vector_typeIdLj2EE
	.addrsig_sym _Z8mult_ph1iddP15HIP_vector_typeIdLj2EE
	.addrsig_sym _Z8mult_ph2iddPdP15HIP_vector_typeIdLj2EE
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z6get_GjPdS_P15HIP_vector_typeIdLj2EE ; -- Begin function _Z6get_GjPdS_P15HIP_vector_typeIdLj2EE
	.globl	_Z6get_GjPdS_P15HIP_vector_typeIdLj2EE
	.p2align	8
	.type	_Z6get_GjPdS_P15HIP_vector_typeIdLj2EE,@function
_Z6get_GjPdS_P15HIP_vector_typeIdLj2EE: ; @_Z6get_GjPdS_P15HIP_vector_typeIdLj2EE
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b128 s[4:7], s[0:1], 0x0
                                        ; implicit-def: $vgpr7_vgpr8
                                        ; implicit-def: $vgpr9_vgpr10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_load_b64 s[2:3], s[0:1], 0x10
	s_mov_b32 s1, exec_lo
                                        ; implicit-def: $vgpr0
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[5:6], 3, v[1:2]
	v_add_co_u32 v3, vcc_lo, s6, v5
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v6, vcc_lo
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(0)
	v_cmpx_ngt_f64_e64 0x41d00000, |v[3:4]|
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB0_2
; %bb.1:
	v_ldexp_f64 v[7:8], |v[3:4]|, 0xffffff80
	v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[3:4]|
	v_trig_preop_f64 v[9:10], |v[3:4]|, 0
	v_and_b32_e32 v0, 0x7fffffff, v4
	v_trig_preop_f64 v[11:12], |v[3:4]|, 1
	v_trig_preop_f64 v[21:22], |v[3:4]|, 2
	s_mov_b32 s6, 0x54442d18
	s_mov_b32 s7, 0x3ff921fb
	s_mov_b32 s8, 0x33145c07
	s_mov_b32 s9, 0x3c91a626
	v_mov_b32_e32 v29, 0
	v_dual_cndmask_b32 v7, v3, v7 :: v_dual_cndmask_b32 v8, v0, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f64 v[13:14], v[9:10], v[7:8]
	v_mul_f64 v[15:16], v[11:12], v[7:8]
	v_fma_f64 v[9:10], v[9:10], v[7:8], -v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[11:12], v[11:12], v[7:8], -v[15:16]
	v_add_f64 v[17:18], v[15:16], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[19:20], v[17:18], -v[15:16]
	v_add_f64 v[25:26], v[13:14], v[17:18]
	v_add_f64 v[23:24], v[17:18], -v[19:20]
	v_add_f64 v[9:10], v[9:10], -v[19:20]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_ldexp_f64 v[19:20], v[25:26], -2
	v_add_f64 v[13:14], v[25:26], -v[13:14]
	v_add_f64 v[15:16], v[15:16], -v[23:24]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[19:20]|
	v_add_f64 v[13:14], v[17:18], -v[13:14]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[9:10], v[9:10], v[15:16]
	v_fract_f64_e32 v[15:16], v[19:20]
	v_cndmask_b32_e32 v15, 0, v15, vcc_lo
	v_mul_f64 v[27:28], v[21:22], v[7:8]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v16, 0, v16, vcc_lo
	v_ldexp_f64 v[15:16], v[15:16], 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[23:24], v[27:28], v[11:12]
	v_fma_f64 v[7:8], v[21:22], v[7:8], -v[27:28]
	v_add_f64 v[17:18], v[23:24], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[19:20], v[13:14], v[17:18]
	v_add_f64 v[25:26], v[19:20], v[15:16]
	v_add_f64 v[13:14], v[19:20], -v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_gt_f64_e32 vcc_lo, 0, v[25:26]
	v_add_f64 v[25:26], v[23:24], -v[27:28]
	v_add_f64 v[13:14], v[17:18], -v[13:14]
	v_cndmask_b32_e64 v30, 0, 0x40100000, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[34:35], v[23:24], -v[25:26]
	v_add_f64 v[11:12], v[11:12], -v[25:26]
	v_add_f64 v[15:16], v[15:16], v[29:30]
	v_add_f64 v[30:31], v[17:18], -v[23:24]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[25:26], v[27:28], -v[34:35]
	v_add_f64 v[32:33], v[19:20], v[15:16]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[36:37], v[17:18], -v[30:31]
	v_add_f64 v[9:10], v[9:10], -v[30:31]
	v_add_f64 v[11:12], v[11:12], v[25:26]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_i32_f64_e32 v0, v[32:33]
	v_add_f64 v[23:24], v[23:24], -v[36:37]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_i32_e32 v[30:31], v0
	v_add_f64 v[9:10], v[9:10], v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[15:16], v[15:16], -v[30:31]
	v_add_f64 v[9:10], v[11:12], v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[11:12], v[19:20], v[15:16]
	v_add_f64 v[7:8], v[7:8], v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[9:10], v[11:12], -v[15:16]
	v_cmp_le_f64_e32 vcc_lo, 0.5, v[11:12]
	v_add_f64 v[7:8], v[13:14], v[7:8]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f64 v[9:10], v[19:20], -v[9:10]
	v_cndmask_b32_e64 v30, 0, 0x3ff00000, vcc_lo
	v_add_co_ci_u32_e64 v0, s0, 0, v0, vcc_lo
	v_add_f64 v[7:8], v[7:8], v[9:10]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[9:10], v[11:12], -v[29:30]
	v_add_f64 v[11:12], v[9:10], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f64 v[13:14], v[11:12], s[6:7]
	v_add_f64 v[9:10], v[11:12], -v[9:10]
	v_fma_f64 v[15:16], v[11:12], s[6:7], -v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[7:8], v[7:8], -v[9:10]
	v_fma_f64 v[9:10], v[11:12], s[8:9], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], v[7:8], s[6:7], v[9:10]
	v_add_f64 v[7:8], v[13:14], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[11:12], v[7:8], -v[13:14]
	v_add_f64 v[9:10], v[9:10], -v[11:12]
.LBB0_2:                                ; %Flow
	s_and_not1_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_4
; %bb.3:
	s_mov_b32 s6, 0x6dc9c883
	s_mov_b32 s7, 0x3fe45f30
	s_mov_b32 s9, 0xbc91a626
	v_mul_f64 v[7:8], |v[3:4]|, s[6:7]
	s_mov_b32 s6, 0x54442d18
	s_mov_b32 s7, 0xbff921fb
	s_mov_b32 s8, 0x33145c00
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[11:12], v[7:8]
	v_fma_f64 v[7:8], v[11:12], s[6:7], |v[3:4]|
	v_mul_f64 v[9:10], v[11:12], s[8:9]
	s_mov_b32 s6, 0x252049c0
	s_mov_b32 s7, 0xb97b839a
	v_cvt_i32_f64_e32 v0, v[11:12]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[15:16], v[11:12], s[8:9], v[7:8]
	v_add_f64 v[13:14], v[7:8], v[9:10]
	s_mov_b32 s9, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[7:8], v[7:8], -v[13:14]
	v_add_f64 v[13:14], v[13:14], -v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[7:8], v[7:8], v[9:10]
	v_fma_f64 v[9:10], v[11:12], s[8:9], v[9:10]
	v_add_f64 v[7:8], v[13:14], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[7:8], v[7:8], -v[9:10]
	v_fma_f64 v[9:10], v[11:12], s[6:7], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[7:8], v[15:16], v[9:10]
	v_add_f64 v[13:14], v[7:8], -v[15:16]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[9:10], v[9:10], -v[13:14]
.LBB0_4:                                ; %_ZL6sincosdPdS_.exit
	s_or_b32 exec_lo, exec_lo, s0
	v_mul_f64 v[11:12], v[7:8], v[7:8]
	s_mov_b32 s0, 0xb42fdfa7
	s_mov_b32 s6, 0xf9a43bb8
	v_add_co_u32 v5, vcc_lo, s4, v5
	s_mov_b32 s1, 0xbe5ae600
	s_mov_b32 s7, 0x3de5e0b2
	v_add_co_ci_u32_e32 v6, vcc_lo, s5, v6, vcc_lo
	s_mov_b32 s4, 0x46cc5e42
	s_mov_b32 s5, 0xbda907db
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_f64 v[23:24], v[9:10], 0.5
	global_load_b64 v[15:16], v[5:6], off
	v_lshlrev_b64 v[1:2], 4, v[1:2]
	v_fma_f64 v[13:14], v[11:12], s[6:7], s[0:1]
	s_mov_b32 s6, 0x796cde01
	s_mov_b32 s7, 0x3ec71de3
	v_mul_f64 v[19:20], v[11:12], 0.5
	s_mov_b32 s0, 0x9037ab78
	s_mov_b32 s1, 0x3e21eeb6
	v_mul_f64 v[25:26], v[7:8], -v[11:12]
	v_fma_f64 v[17:18], v[11:12], s[4:5], s[0:1]
	s_mov_b32 s4, 0x19e83e5c
	s_mov_b32 s5, 0xbf2a01a0
	s_mov_b32 s0, 0xa17f65f6
	s_mov_b32 s1, 0xbe927e4f
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[13:14], v[11:12], v[13:14], s[6:7]
	v_add_f64 v[21:22], -v[19:20], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[17:18], v[11:12], v[17:18], s[0:1]
	s_mov_b32 s0, 0x19f4ec90
	s_mov_b32 s1, 0x3efa01a0
	v_fma_f64 v[13:14], v[11:12], v[13:14], s[4:5]
	s_mov_b32 s4, 0x11110bb3
	s_mov_b32 s5, 0x3f811111
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[27:28], -v[21:22], 1.0
	v_fma_f64 v[17:18], v[11:12], v[17:18], s[0:1]
	s_mov_b32 s0, 0x16c16967
	s_mov_b32 s1, 0xbf56c16c
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[13:14], v[11:12], v[13:14], s[4:5]
	v_add_f64 v[19:20], v[27:28], -v[19:20]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[17:18], v[11:12], v[17:18], s[0:1]
	s_mov_b32 s1, 0x3fa55555
	s_mov_b32 s0, 0x55555555
	v_fma_f64 v[13:14], v[25:26], v[13:14], v[23:24]
	v_mul_f64 v[23:24], v[11:12], v[11:12]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[19:20], v[7:8], -v[9:10], v[19:20]
	v_fma_f64 v[17:18], v[11:12], v[17:18], s[0:1]
	s_mov_b32 s1, 0xbfc55555
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[9:10], v[11:12], v[13:14], -v[9:10]
	v_fma_f64 v[11:12], v[23:24], v[17:18], v[19:20]
	v_lshlrev_b32_e32 v17, 30, v0
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f64 v[9:10], v[25:26], s[0:1], v[9:10]
	v_cmp_class_f64_e64 s0, v[3:4], 0x1f8
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v13, s1, s2, v1
	v_xor_b32_e32 v1, v17, v4
	v_add_co_ci_u32_e64 v14, s1, s3, v2, s1
	v_add_f64 v[11:12], v[21:22], v[11:12]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_and_b32_e32 v1, 0x80000000, v1
	v_add_f64 v[7:8], v[7:8], -v[9:10]
	v_and_b32_e32 v9, 1, v0
	v_cmp_eq_u32_e32 vcc_lo, 0, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v4, v12, v8 :: v_dual_and_b32 v3, 0x80000000, v17
	v_xor_b32_e32 v0, 0x80000000, v8
	v_cndmask_b32_e32 v9, v11, v7, vcc_lo
	v_cndmask_b32_e32 v7, v7, v11, vcc_lo
	v_xor_b32_e32 v1, v4, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v0, v0, v12, vcc_lo
	v_cndmask_b32_e64 v1, 0x7ff80000, v1, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v3, v0, v3
	v_cndmask_b32_e64 v0, 0, v9, s0
	v_cndmask_b32_e64 v9, 0, v7, s0
	v_cndmask_b32_e64 v10, 0x7ff80000, v3, s0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f64 v[9:10], v[15:16], v[9:10]
	global_store_b64 v[13:14], v[9:10], off
	global_load_b64 v[2:3], v[5:6], off
	s_waitcnt vmcnt(0)
	v_mul_f64 v[0:1], v[2:3], v[0:1]
	global_store_b64 v[13:14], v[0:1], off offset:8
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6get_GjPdS_P15HIP_vector_typeIdLj2EE
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 38
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z6get_GjPdS_P15HIP_vector_typeIdLj2EE, .Lfunc_end0-_Z6get_GjPdS_P15HIP_vector_typeIdLj2EE
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1716
; NumSgprs: 18
; NumVgprs: 38
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 38
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z17mult_complex_1to1P15HIP_vector_typeIdLj2EES1_S1_ ; -- Begin function _Z17mult_complex_1to1P15HIP_vector_typeIdLj2EES1_S1_
	.globl	_Z17mult_complex_1to1P15HIP_vector_typeIdLj2EES1_S1_
	.p2align	8
	.type	_Z17mult_complex_1to1P15HIP_vector_typeIdLj2EES1_S1_,@function
_Z17mult_complex_1to1P15HIP_vector_typeIdLj2EES1_S1_: ; @_Z17mult_complex_1to1P15HIP_vector_typeIdLj2EES1_S1_
; %bb.0:
	s_clause 0x3
	s_load_b32 s2, s[0:1], 0x18
	s_load_b32 s3, s[0:1], 0x24
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s2, s15
	s_and_b32 s3, s3, 0xffff
	s_add_i32 s2, s2, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s2, s3, v[0:1]
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 4, v[1:2]
	v_add_co_u32 v0, vcc_lo, s4, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v9, vcc_lo
	v_add_co_u32 v4, vcc_lo, s6, v8
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v9, vcc_lo
	global_load_b128 v[0:3], v[0:1], off
	global_load_b128 v[4:7], v[4:5], off
	s_waitcnt vmcnt(0)
	v_mul_f64 v[10:11], v[2:3], v[6:7]
	v_mul_f64 v[6:7], v[0:1], v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[0:1], v[0:1], v[4:5], -v[10:11]
	v_fma_f64 v[2:3], v[2:3], v[4:5], v[6:7]
	v_add_co_u32 v4, vcc_lo, s0, v8
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v9, vcc_lo
	global_store_b128 v[4:5], v[0:3], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17mult_complex_1to1P15HIP_vector_typeIdLj2EES1_S1_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z17mult_complex_1to1P15HIP_vector_typeIdLj2EES1_S1_, .Lfunc_end1-_Z17mult_complex_1to1P15HIP_vector_typeIdLj2EES1_S1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 200
; NumSgprs: 18
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z17mult_complex_1tonP15HIP_vector_typeIdLj2EES1_S1_ ; -- Begin function _Z17mult_complex_1tonP15HIP_vector_typeIdLj2EES1_S1_
	.globl	_Z17mult_complex_1tonP15HIP_vector_typeIdLj2EES1_S1_
	.p2align	8
	.type	_Z17mult_complex_1tonP15HIP_vector_typeIdLj2EES1_S1_,@function
_Z17mult_complex_1tonP15HIP_vector_typeIdLj2EES1_S1_: ; @_Z17mult_complex_1tonP15HIP_vector_typeIdLj2EES1_S1_
; %bb.0:
	s_clause 0x3
	s_load_b32 s2, s[0:1], 0x24
	s_load_b32 s3, s[0:1], 0x18
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_mul_i32 s3, s3, s15
	v_mad_u64_u32 v[1:2], null, s14, s2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, s3, s2, v[1:2]
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[0:1], 4, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v4, 31, v3
	v_add_co_u32 v0, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[8:9], 4, v[3:4]
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, s6, v8
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v9, vcc_lo
	global_load_b128 v[0:3], v[0:1], off
	global_load_b128 v[4:7], v[4:5], off
	s_waitcnt vmcnt(0)
	v_mul_f64 v[10:11], v[2:3], v[6:7]
	v_mul_f64 v[6:7], v[0:1], v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[0:1], v[0:1], v[4:5], -v[10:11]
	v_fma_f64 v[2:3], v[2:3], v[4:5], v[6:7]
	v_add_co_u32 v4, vcc_lo, s0, v8
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v9, vcc_lo
	global_store_b128 v[4:5], v[0:3], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17mult_complex_1tonP15HIP_vector_typeIdLj2EES1_S1_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z17mult_complex_1tonP15HIP_vector_typeIdLj2EES1_S1_, .Lfunc_end2-_Z17mult_complex_1tonP15HIP_vector_typeIdLj2EES1_S1_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 220
; NumSgprs: 18
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z10get_E_GwkjPdP15HIP_vector_typeIdLj2EES_S2_ ; -- Begin function _Z10get_E_GwkjPdP15HIP_vector_typeIdLj2EES_S2_
	.globl	_Z10get_E_GwkjPdP15HIP_vector_typeIdLj2EES_S2_
	.p2align	8
	.type	_Z10get_E_GwkjPdP15HIP_vector_typeIdLj2EES_S2_,@function
_Z10get_E_GwkjPdP15HIP_vector_typeIdLj2EES_S2_: ; @_Z10get_E_GwkjPdP15HIP_vector_typeIdLj2EES_S2_
; %bb.0:
	s_clause 0x2
	s_load_b32 s8, s[0:1], 0x20
	s_load_b32 s9, s[0:1], 0x2c
	s_load_b256 s[0:7], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s8, s8, s15
	s_and_b32 s9, s9, 0xffff
	s_add_i32 s8, s8, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, s8, s9, v[0:1]
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[6:7], 4, v[4:5]
	v_lshlrev_b64 v[4:5], 3, v[4:5]
	v_add_co_u32 v8, vcc_lo, s2, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v9, vcc_lo, s3, v7, vcc_lo
	v_add_co_u32 v10, s0, s0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v11, s0, s1, v5, s0
	global_load_b128 v[0:3], v[8:9], off
	global_load_b64 v[12:13], v[10:11], off
	s_waitcnt vmcnt(1)
	v_mul_f64 v[2:3], v[2:3], v[2:3]
	v_fma_f64 v[0:1], v[0:1], v[0:1], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[0:1]
	v_cndmask_b32_e64 v2, 0, 1, vcc_lo
	v_lshlrev_b32_e32 v2, 8, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[0:1], v[0:1], v2
	v_rsq_f64_e32 v[2:3], v[0:1]
	s_waitcnt_depctr 0xfff
	v_mul_f64 v[14:15], v[0:1], v[2:3]
	v_mul_f64 v[2:3], v[2:3], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], -v[2:3], v[14:15], 0.5
	v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
	v_fma_f64 v[2:3], v[2:3], v[16:17], v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], -v[14:15], v[14:15], v[0:1]
	v_fma_f64 v[14:15], v[16:17], v[2:3], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], -v[14:15], v[14:15], v[0:1]
	v_fma_f64 v[2:3], v[16:17], v[2:3], v[14:15]
	v_cndmask_b32_e64 v14, 0, 0xffffff80, vcc_lo
	v_cmp_class_f64_e64 vcc_lo, v[0:1], 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[2:3], v[2:3], v14
	v_dual_cndmask_b32 v15, v3, v1 :: v_dual_cndmask_b32 v14, v2, v0
	v_add_co_u32 v2, vcc_lo, s4, v4
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v5, vcc_lo
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[0:1], v[12:13], -v[14:15]
	v_mul_f64 v[12:13], v[14:15], v[14:15]
	v_mul_f64 v[0:1], v[0:1], v[0:1]
	global_store_b64 v[2:3], v[0:1], off
	global_load_b128 v[0:3], v[8:9], off
	global_load_b64 v[10:11], v[10:11], off
	s_waitcnt vmcnt(1)
	v_mul_f64 v[4:5], v[2:3], 0
	v_mul_f64 v[8:9], v[0:1], 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[4:5], v[0:1], v[14:15], v[4:5]
	v_fma_f64 v[8:9], v[2:3], v[14:15], -v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[14:15], null, v[12:13], v[12:13], v[4:5]
	v_div_scale_f64 v[16:17], null, v[12:13], v[12:13], v[8:9]
	v_div_scale_f64 v[26:27], vcc_lo, v[4:5], v[12:13], v[4:5]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[18:19], v[14:15]
	v_rcp_f64_e32 v[20:21], v[16:17]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[22:23], -v[14:15], v[18:19], 1.0
	v_fma_f64 v[24:25], -v[16:17], v[20:21], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[18:19], v[18:19], v[22:23], v[18:19]
	v_fma_f64 v[20:21], v[20:21], v[24:25], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[22:23], -v[14:15], v[18:19], 1.0
	v_fma_f64 v[24:25], -v[16:17], v[20:21], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[18:19], v[18:19], v[22:23], v[18:19]
	v_div_scale_f64 v[22:23], s0, v[8:9], v[12:13], v[8:9]
	v_fma_f64 v[20:21], v[20:21], v[24:25], v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[24:25], v[26:27], v[18:19]
	v_mul_f64 v[28:29], v[22:23], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[14:15], -v[14:15], v[24:25], v[26:27]
	v_fma_f64 v[16:17], -v[16:17], v[28:29], v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[14:15], v[14:15], v[18:19], v[24:25]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[16:17], v[16:17], v[20:21], v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[4:5], v[14:15], v[12:13], v[4:5]
	v_div_fixup_f64 v[8:9], v[16:17], v[12:13], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_f64 v[12:13], v[8:9], 0
	s_waitcnt vmcnt(0)
	v_mul_f64 v[8:9], v[10:11], v[8:9]
	v_fma_f64 v[10:11], v[10:11], v[4:5], -v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[4:5], v[4:5], 0, v[8:9]
	v_add_f64 v[0:1], v[10:11], -v[0:1]
	s_delay_alu instid0(VALU_DEP_2)
	v_add_f64 v[2:3], v[4:5], -v[2:3]
	v_add_co_u32 v4, vcc_lo, s6, v6
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v7, vcc_lo
	global_store_b128 v[4:5], v[0:3], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10get_E_GwkjPdP15HIP_vector_typeIdLj2EES_S2_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 30
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z10get_E_GwkjPdP15HIP_vector_typeIdLj2EES_S2_, .Lfunc_end3-_Z10get_E_GwkjPdP15HIP_vector_typeIdLj2EES_S2_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 744
; NumSgprs: 18
; NumVgprs: 30
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 30
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z5sum_EiPd             ; -- Begin function _Z5sum_EiPd
	.globl	_Z5sum_EiPd
	.p2align	8
	.type	_Z5sum_EiPd,@function
_Z5sum_EiPd:                            ; @_Z5sum_EiPd
; %bb.0:
	s_clause 0x1
	s_load_b32 s6, s[0:1], 0x1c
	s_load_b64 s[2:3], s[0:1], 0x8
	s_add_u32 s4, s0, 16
	s_addc_u32 s5, s1, 0
	s_load_b32 s0, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s6, s6, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s6, v[0:1]
	s_cmp_lt_i32 s0, 2
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 3, v[1:2]
	v_add_co_u32 v1, vcc_lo, s2, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_load_b64 v[3:4], v[1:2], off
	s_cbranch_scc1 .LBB4_3
; %bb.1:                                ; %.lr.ph
	s_load_b32 s1, s[4:5], 0x0
	s_add_i32 s4, s0, -1
	s_add_i32 s0, s0, 1
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s4, s1, s4
	s_mul_i32 s1, s1, s6
	s_add_i32 s15, s15, s4
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[5:6], null, s15, s6, v[0:1]
	v_mov_b32_e32 v6, 0
.LBB4_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_lshlrev_b64 v[7:8], 3, v[5:6]
	v_subrev_nc_u32_e32 v5, s1, v5
	s_add_i32 s0, s0, -1
	s_cmp_lt_u32 s0, 3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, s2, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
	global_load_b64 v[7:8], v[7:8], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[3:4], v[3:4], v[7:8]
	s_cbranch_scc0 .LBB4_2
.LBB4_3:                                ; %Flow20
	s_waitcnt vmcnt(0)
	global_store_b64 v[1:2], v[3:4], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z5sum_EiPd
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z5sum_EiPd, .Lfunc_end4-_Z5sum_EiPd
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 244
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z8sum_EtotPdS_         ; -- Begin function _Z8sum_EtotPdS_
	.globl	_Z8sum_EtotPdS_
	.p2align	8
	.type	_Z8sum_EtotPdS_,@function
_Z8sum_EtotPdS_:                        ; @_Z8sum_EtotPdS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s4, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s5, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_mul_i32 s6, s15, s5
	s_cmp_lt_u32 s5, 2
	v_lshl_add_u32 v1, s6, 1, v0
	v_dual_mov_b32 v4, 0 :: v_dual_add_nc_u32 v3, s5, v1
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	v_lshlrev_b64 v[1:2], 3, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_clause 0x1
	global_load_b64 v[1:2], v[1:2], off
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[1:2], v[3:4]
	v_lshl_add_u32 v1, v0, 3, 0
	ds_store_b64 v1, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_barrier
.LBB5_1:                                ; =>This Inner Loop Header: Depth=1
	buffer_gl0_inv
	s_cbranch_scc1 .LBB5_5
; %bb.2:                                ; %.lr.ph
                                        ;   in Loop: Header=BB5_1 Depth=1
	s_lshr_b32 s0, s5, 1
	s_mov_b32 s1, exec_lo
	v_cmpx_gt_u32_e64 s0, v0
	s_cbranch_execz .LBB5_4
; %bb.3:                                ;   in Loop: Header=BB5_1 Depth=1
	v_lshl_add_u32 v2, s0, 3, v1
	ds_load_b64 v[2:3], v2
	ds_load_b64 v[4:5], v1
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[2:3], v[2:3], v[4:5]
	ds_store_b64 v1, v[2:3]
.LBB5_4:                                ;   in Loop: Header=BB5_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt lgkmcnt(0)
	s_barrier
	s_cmp_lt_u32 s5, 4
	s_mov_b32 s5, s0
	s_branch .LBB5_1
.LBB5_5:                                ; %._crit_edge
	s_mov_b32 s0, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB5_7
; %bb.6:
	v_mov_b32_e32 v2, 0
	s_mov_b32 s5, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[4:5], 3
	s_add_u32 s0, s2, s0
	ds_load_b64 v[0:1], v2
	s_addc_u32 s1, s3, s1
	s_waitcnt lgkmcnt(0)
	global_store_b64 v2, v[0:1], s[0:1]
.LBB5_7:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8sum_EtotPdS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	_Z8sum_EtotPdS_, .Lfunc_end5-_Z8sum_EtotPdS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 344
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z6get_dEiP15HIP_vector_typeIdLj2EES1_Pd ; -- Begin function _Z6get_dEiP15HIP_vector_typeIdLj2EES1_Pd
	.globl	_Z6get_dEiP15HIP_vector_typeIdLj2EES1_Pd
	.p2align	8
	.type	_Z6get_dEiP15HIP_vector_typeIdLj2EES1_Pd,@function
_Z6get_dEiP15HIP_vector_typeIdLj2EES1_Pd: ; @_Z6get_dEiP15HIP_vector_typeIdLj2EES1_Pd
; %bb.0:
	s_clause 0x1
	s_load_b32 s8, s[0:1], 0x2c
	s_load_b128 s[4:7], s[0:1], 0x8
	s_add_u32 s2, s0, 32
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s8, s8, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, s15, s8, v[0:1]
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 4, v[5:6]
	v_add_co_u32 v1, vcc_lo, s6, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s7, v8, vcc_lo
	global_load_b128 v[1:4], v[1:2], off
	s_clause 0x1
	s_load_b32 s9, s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s9, 2
	s_waitcnt vmcnt(0)
	v_xor_b32_e32 v4, 0x80000000, v4
	s_cbranch_scc1 .LBB6_3
; %bb.1:                                ; %.lr.ph
	s_load_b32 s3, s[2:3], 0x0
	s_add_i32 s2, s9, -1
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s3, s2
	s_mul_i32 s3, s3, s8
	s_add_i32 s15, s15, s2
	s_add_i32 s2, s9, 1
	v_mad_u64_u32 v[9:10], null, s15, s8, v[0:1]
	v_mov_b32_e32 v10, 0
.LBB6_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_lshlrev_b64 v[11:12], 4, v[9:10]
	v_subrev_nc_u32_e32 v9, s3, v9
	s_add_i32 s2, s2, -1
	s_cmp_lt_u32 s2, 3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v11, vcc_lo, s6, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
	global_load_b128 v[11:14], v[11:12], off
	s_waitcnt vmcnt(0)
	v_add_f64 v[1:2], v[1:2], v[11:12]
	v_add_f64 v[3:4], v[3:4], -v[13:14]
	s_cbranch_scc0 .LBB6_2
.LBB6_3:                                ; %Flow49
	v_add_co_u32 v7, vcc_lo, s4, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
	global_load_b128 v[7:10], v[7:8], off
	s_waitcnt vmcnt(0)
	v_mul_f64 v[0:1], v[1:2], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[0:1], v[3:4], v[7:8], v[0:1]
	v_lshlrev_b64 v[2:3], 3, v[5:6]
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	v_add_f64 v[0:1], v[0:1], v[0:1]
	global_store_b64 v[2:3], v[0:1], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6get_dEiP15HIP_vector_typeIdLj2EES1_Pd
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end6:
	.size	_Z6get_dEiP15HIP_vector_typeIdLj2EES1_Pd, .Lfunc_end6-_Z6get_dEiP15HIP_vector_typeIdLj2EES1_Pd
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 348
; NumSgprs: 18
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z6mult_TiddPdP15HIP_vector_typeIdLj2EE ; -- Begin function _Z6mult_TiddPdP15HIP_vector_typeIdLj2EE
	.globl	_Z6mult_TiddPdP15HIP_vector_typeIdLj2EE
	.p2align	8
	.type	_Z6mult_TiddPdP15HIP_vector_typeIdLj2EE,@function
_Z6mult_TiddPdP15HIP_vector_typeIdLj2EE: ; @_Z6mult_TiddPdP15HIP_vector_typeIdLj2EE
; %bb.0:
	s_clause 0x2
	s_load_b256 s[4:11], s[0:1], 0x8
	s_load_b32 s2, s[0:1], 0x34
	s_load_b32 s0, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	v_div_scale_f64 v[1:2], null, s[6:7], s[6:7], 1.0
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[3:4], v[1:2]
	v_mad_u64_u32 v[5:6], null, s15, s2, v[0:1]
	s_mov_b32 s2, 0xf99eb0bb
	s_mov_b32 s3, 0x3f3e357e
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 3, v[5:6]
	v_add_co_u32 v7, vcc_lo, s8, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v8, vcc_lo
	v_div_scale_f64 v[11:12], vcc_lo, 1.0, s[6:7], 1.0
	global_load_b64 v[7:8], v[7:8], off
	v_fma_f64 v[9:10], -v[1:2], v[3:4], 1.0
	v_fma_f64 v[3:4], v[3:4], v[9:10], v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], -v[1:2], v[3:4], 1.0
	v_fma_f64 v[3:4], v[3:4], v[9:10], v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[9:10], v[11:12], v[3:4]
	v_fma_f64 v[0:1], -v[1:2], v[9:10], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[0:1], v[0:1], v[3:4], v[9:10]
	v_cvt_f64_i32_e32 v[2:3], s0
	v_div_fixup_f64 v[0:1], v[0:1], s[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_div_scale_f64 v[9:10], null, s[6:7], s[6:7], v[0:1]
	v_div_scale_f64 v[21:22], vcc_lo, v[0:1], s[6:7], v[0:1]
	s_waitcnt vmcnt(0)
	v_div_scale_f64 v[11:12], null, v[2:3], v[2:3], v[7:8]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[13:14], v[9:10]
	v_rcp_f64_e32 v[15:16], v[11:12]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[17:18], -v[9:10], v[13:14], 1.0
	v_fma_f64 v[19:20], -v[11:12], v[15:16], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[13:14], v[13:14], v[17:18], v[13:14]
	v_fma_f64 v[15:16], v[15:16], v[19:20], v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[17:18], -v[9:10], v[13:14], 1.0
	v_fma_f64 v[19:20], -v[11:12], v[15:16], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[13:14], v[13:14], v[17:18], v[13:14]
	v_div_scale_f64 v[17:18], s0, v[7:8], v[2:3], v[7:8]
	v_fma_f64 v[15:16], v[15:16], v[19:20], v[15:16]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[19:20], v[21:22], v[13:14]
	v_mul_f64 v[23:24], v[17:18], v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[9:10], -v[9:10], v[19:20], v[21:22]
	v_fma_f64 v[11:12], -v[11:12], v[23:24], v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[9:10], v[9:10], v[13:14], v[19:20]
	s_mov_b32 vcc_lo, s0
	s_mov_b32 s0, 0x6fdffd2b
	s_mov_b32 s1, 0xbf7e2fe7
	v_div_fmas_f64 v[11:12], v[11:12], v[15:16], v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[0:1], v[9:10], s[6:7], v[0:1]
	s_mov_b32 s6, 0x2e21c33
	s_mov_b32 s7, 0xbf1b1673
	v_div_fixup_f64 v[7:8], v[11:12], v[2:3], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[11:12], null, v[2:3], v[2:3], v[7:8]
	v_div_scale_f64 v[17:18], vcc_lo, v[7:8], v[2:3], v[7:8]
	v_rcp_f64_e32 v[13:14], v[11:12]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[15:16], -v[11:12], v[13:14], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
	v_fma_f64 v[15:16], -v[11:12], v[13:14], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
	v_mul_f64 v[15:16], v[17:18], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], -v[11:12], v[15:16], v[17:18]
	v_div_fmas_f64 v[11:12], v[11:12], v[13:14], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[2:3], v[11:12], v[2:3], v[7:8]
	v_add_f64 v[0:1], v[0:1], -v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[0:1]
	v_cndmask_b32_e64 v2, 0, 1, vcc_lo
	v_cndmask_b32_e64 v4, 0, 0xffffff80, vcc_lo
	v_lshlrev_b32_e32 v2, 8, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[0:1], v[0:1], v2
	v_rsq_f64_e32 v[2:3], v[0:1]
	v_cmp_class_f64_e64 vcc_lo, v[0:1], 0x260
	s_waitcnt_depctr 0xfff
	v_mul_f64 v[7:8], v[0:1], v[2:3]
	v_mul_f64 v[2:3], v[2:3], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], -v[2:3], v[7:8], 0.5
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	v_fma_f64 v[2:3], v[2:3], v[9:10], v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], -v[7:8], v[7:8], v[0:1]
	v_fma_f64 v[7:8], v[9:10], v[2:3], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], -v[7:8], v[7:8], v[0:1]
	v_fma_f64 v[2:3], v[9:10], v[2:3], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[2:3], v[2:3], v4
	v_dual_cndmask_b32 v1, v3, v1 :: v_dual_cndmask_b32 v0, v2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_f64 v[0:1], v[0:1], s[4:5]
	s_mov_b32 s4, 0xca1d4f33
	s_mov_b32 s5, 0x3f5f9c89
	v_add_f64 v[7:8], v[0:1], v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[0:1], |v[7:8]|, 0.5
	v_fract_f64_e32 v[2:3], v[0:1]
	v_cmp_neq_f64_e32 vcc_lo, 0x7ff00000, v[0:1]
	v_and_b32_e32 v0, 0x7fffffff, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[2:3], v[2:3], v[2:3]
	v_dual_cndmask_b32 v1, 0, v3 :: v_dual_cndmask_b32 v2, 0, v2
	v_cmp_gt_f64_e64 vcc_lo, |v[7:8]|, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v1, v0, v1 :: v_dual_cndmask_b32 v0, v7, v2
	v_add_f64 v[2:3], v[0:1], v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[9:10], v[2:3]
	v_fma_f64 v[11:12], v[9:10], -0.5, v[0:1]
	v_lshlrev_b64 v[0:1], 4, v[5:6]
	v_cvt_i32_f64_e32 v6, v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v15, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v16, vcc_lo, s11, v1, vcc_lo
	global_load_b128 v[0:3], v[15:16], off
	v_mul_f64 v[13:14], v[11:12], v[11:12]
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[4:5], v[13:14], s[2:3], s[0:1]
	v_fma_f64 v[17:18], v[13:14], s[6:7], s[4:5]
	s_mov_b32 s0, 0xd5f14825
	s_mov_b32 s2, 0x7294bff9
	s_mov_b32 s1, 0x3fb50782
	s_mov_b32 s3, 0xbf9a6d1e
	v_mul_f64 v[19:20], v[11:12], v[13:14]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[4:5], v[13:14], v[4:5], s[0:1]
	v_fma_f64 v[17:18], v[13:14], v[17:18], s[2:3]
	s_mov_b32 s0, 0xcdfe9424
	s_mov_b32 s2, 0x67b90b37
	s_mov_b32 s1, 0xbfe32d2c
	s_mov_b32 s3, 0x3fce1f50
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[4:5], v[13:14], v[4:5], s[0:1]
	v_fma_f64 v[17:18], v[13:14], v[17:18], s[2:3]
	s_mov_b32 s0, 0x67754fff
	s_mov_b32 s2, 0x7e3c325b
	s_mov_b32 s1, 0x400466bc
	s_mov_b32 s3, 0xbff55d3c
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[4:5], v[13:14], v[4:5], s[0:1]
	v_fma_f64 v[17:18], v[13:14], v[17:18], s[2:3]
	s_mov_b32 s0, 0xe625be09
	s_mov_b32 s2, 0x81b5a67
	s_mov_b32 s1, 0xc014abbc
	s_mov_b32 s3, 0x40103c1f
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[4:5], v[13:14], v[4:5], s[0:1]
	v_fma_f64 v[17:18], v[13:14], v[17:18], s[2:3]
	s_mov_b32 s0, 0xc9be45de
	s_mov_b32 s1, 0xc013bd3c
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[4:5], v[19:20], v[4:5]
	v_fma_f64 v[17:18], v[13:14], v[17:18], s[0:1]
	s_mov_b32 s0, 0x54442d18
	s_mov_b32 s1, 0x400921fb
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[4:5], v[11:12], s[0:1], v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], v[13:14], v[17:18], 1.0
	v_cmp_class_f64_e64 s0, v[7:8], 0x1f8
	v_and_b32_e32 v11, 1, v6
	v_cmp_eq_u32_e32 vcc_lo, 0, v11
	v_lshlrev_b32_e32 v6, 30, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v7, v6, v8
	v_xor_b32_e32 v8, 0x80000000, v5
	v_and_b32_e32 v7, 0x80000000, v7
	v_cndmask_b32_e32 v5, v10, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v11, v9, v4 :: v_dual_cndmask_b32 v8, v8, v10
	v_xor_b32_e32 v5, v5, v7
	v_dual_cndmask_b32 v7, v4, v9 :: v_dual_and_b32 v6, 0x80000000, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v4, 0, v11, s0
	v_cndmask_b32_e64 v5, 0x7ff80000, v5, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v8, v8, v6
	v_cndmask_b32_e64 v6, 0, v7, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v7, 0x7ff80000, v8, s0
	s_waitcnt vmcnt(0)
	v_mul_f64 v[8:9], v[2:3], v[4:5]
	v_mul_f64 v[10:11], v[2:3], v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[2:3], v[0:1], v[6:7], -v[8:9]
	v_fma_f64 v[4:5], v[0:1], v[4:5], v[10:11]
	global_store_b128 v[15:16], v[2:5], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6mult_TiddPdP15HIP_vector_typeIdLj2EE
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 25
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end7:
	.size	_Z6mult_TiddPdP15HIP_vector_typeIdLj2EE, .Lfunc_end7-_Z6mult_TiddPdP15HIP_vector_typeIdLj2EE
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1428
; NumSgprs: 18
; NumVgprs: 25
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 25
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z9mult_ph12iddPdP15HIP_vector_typeIdLj2EE ; -- Begin function _Z9mult_ph12iddPdP15HIP_vector_typeIdLj2EE
	.globl	_Z9mult_ph12iddPdP15HIP_vector_typeIdLj2EE
	.p2align	8
	.type	_Z9mult_ph12iddPdP15HIP_vector_typeIdLj2EE,@function
_Z9mult_ph12iddPdP15HIP_vector_typeIdLj2EE: ; @_Z9mult_ph12iddPdP15HIP_vector_typeIdLj2EE
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x34
	s_load_b256 s[4:11], s[0:1], 0x8
	s_load_b32 s0, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	v_add_f64 v[5:6], s[4:5], s[4:5]
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[3:4], 3, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s8, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
	s_mov_b32 s8, 0x2e21c33
	s_mov_b32 s9, 0xbf1b1673
	global_load_b64 v[3:4], v[3:4], off
	v_div_scale_f64 v[7:8], null, s[6:7], s[6:7], v[5:6]
	v_div_scale_f64 v[19:20], vcc_lo, v[5:6], s[6:7], v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[11:12], v[7:8]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[15:16], -v[7:8], v[11:12], 1.0
	v_fma_f64 v[11:12], v[11:12], v[15:16], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], -v[7:8], v[11:12], 1.0
	v_fma_f64 v[11:12], v[11:12], v[15:16], v[11:12]
	s_waitcnt vmcnt(0)
	v_div_scale_f64 v[9:10], null, s[6:7], s[6:7], v[3:4]
	v_div_scale_f64 v[15:16], s2, v[3:4], s[6:7], v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[13:14], v[9:10]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[17:18], -v[9:10], v[13:14], 1.0
	v_fma_f64 v[13:14], v[13:14], v[17:18], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], -v[9:10], v[13:14], 1.0
	v_fma_f64 v[13:14], v[13:14], v[17:18], v[13:14]
	v_mul_f64 v[17:18], v[19:20], v[11:12]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[21:22], v[15:16], v[13:14]
	v_fma_f64 v[7:8], -v[7:8], v[17:18], v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[9:10], -v[9:10], v[21:22], v[15:16]
	v_div_fmas_f64 v[7:8], v[7:8], v[11:12], v[17:18]
	s_mov_b32 vcc_lo, s2
	s_mov_b32 s2, 0x6fdffd2b
	s_mov_b32 s3, 0xbf7e2fe7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[9:10], v[9:10], v[13:14], v[21:22]
	v_div_fixup_f64 v[5:6], v[7:8], s[6:7], v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[3:4], v[9:10], s[6:7], v[3:4]
	s_mov_b32 s6, 0xca1d4f33
	s_mov_b32 s7, 0x3f5f9c89
	v_div_scale_f64 v[9:10], null, s[4:5], s[4:5], v[3:4]
	v_div_scale_f64 v[15:16], vcc_lo, v[3:4], s[4:5], v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[11:12], v[9:10]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[13:14], -v[9:10], v[11:12], 1.0
	v_fma_f64 v[11:12], v[11:12], v[13:14], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], -v[9:10], v[11:12], 1.0
	v_fma_f64 v[11:12], v[11:12], v[13:14], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[13:14], v[15:16], v[11:12]
	v_fma_f64 v[9:10], -v[9:10], v[13:14], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[9:10], v[9:10], v[11:12], v[13:14]
	v_div_fixup_f64 v[3:4], v[9:10], s[4:5], v[3:4]
	s_mov_b32 s4, 0xf99eb0bb
	s_mov_b32 s5, 0x3f3e357e
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[4:5], v[5:6], v[3:4]
	v_mul_f64 v[6:7], |v[4:5]|, 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fract_f64_e32 v[8:9], v[6:7]
	v_cmp_neq_f64_e32 vcc_lo, 0x7ff00000, v[6:7]
	v_add_f64 v[8:9], v[8:9], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v3, 0, v8 :: v_dual_and_b32 v0, 0x7fffffff, v5
	v_cndmask_b32_e32 v6, 0, v9, vcc_lo
	v_cmp_gt_f64_e64 vcc_lo, |v[4:5]|, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v7, v0, v6, vcc_lo
	v_cndmask_b32_e32 v6, v4, v3, vcc_lo
	v_lshlrev_b64 v[0:1], 4, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[8:9], v[6:7], v[6:7]
	v_add_co_u32 v12, vcc_lo, s10, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v13, vcc_lo, s11, v1, vcc_lo
	global_load_b128 v[0:3], v[12:13], off
	v_rndne_f64_e32 v[8:9], v[8:9]
	v_fma_f64 v[6:7], v[8:9], -0.5, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[10:11], v[6:7], v[6:7]
	v_fma_f64 v[14:15], v[10:11], s[4:5], s[2:3]
	v_fma_f64 v[16:17], v[10:11], s[8:9], s[6:7]
	s_mov_b32 s2, 0xd5f14825
	s_mov_b32 s3, 0x3fb50782
	s_mov_b32 s4, 0x7294bff9
	s_mov_b32 s5, 0xbf9a6d1e
	v_mul_f64 v[18:19], v[6:7], v[10:11]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[14:15], v[10:11], v[14:15], s[2:3]
	v_fma_f64 v[16:17], v[10:11], v[16:17], s[4:5]
	s_mov_b32 s2, 0xcdfe9424
	s_mov_b32 s3, 0xbfe32d2c
	s_mov_b32 s4, 0x67b90b37
	s_mov_b32 s5, 0x3fce1f50
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[14:15], v[10:11], v[14:15], s[2:3]
	v_fma_f64 v[16:17], v[10:11], v[16:17], s[4:5]
	s_mov_b32 s2, 0x67754fff
	s_mov_b32 s3, 0x400466bc
	s_mov_b32 s4, 0x7e3c325b
	s_mov_b32 s5, 0xbff55d3c
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[14:15], v[10:11], v[14:15], s[2:3]
	v_fma_f64 v[16:17], v[10:11], v[16:17], s[4:5]
	s_mov_b32 s2, 0xe625be09
	s_mov_b32 s3, 0xc014abbc
	s_mov_b32 s4, 0x81b5a67
	s_mov_b32 s5, 0x40103c1f
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[14:15], v[10:11], v[14:15], s[2:3]
	v_fma_f64 v[16:17], v[10:11], v[16:17], s[4:5]
	s_mov_b32 s2, 0xc9be45de
	s_mov_b32 s3, 0xc013bd3c
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[14:15], v[18:19], v[14:15]
	v_fma_f64 v[16:17], v[10:11], v[16:17], s[2:3]
	v_cvt_i32_f64_e32 v18, v[8:9]
	s_mov_b32 s2, 0x54442d18
	s_mov_b32 s3, 0x400921fb
	s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[6:7], v[6:7], s[2:3], v[14:15]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f64 v[8:9], v[10:11], v[16:17], 1.0
	v_cmp_class_f64_e64 s2, v[4:5], 0x1f8
	v_and_b32_e32 v10, 1, v18
	v_lshlrev_b32_e32 v16, 30, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e32 vcc_lo, 0, v10
	v_and_b32_e32 v11, 0x80000000, v16
	v_xor_b32_e32 v5, v16, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_and_b32_e32 v5, 0x80000000, v5
	v_xor_b32_e32 v4, 0x80000000, v7
	v_cndmask_b32_e32 v10, v8, v6, vcc_lo
	v_cndmask_b32_e32 v6, v6, v8, vcc_lo
	v_cndmask_b32_e32 v4, v4, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v8, v4, v11
	v_cndmask_b32_e64 v4, 0, v10, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v10, 0, v6, s2
	v_cndmask_b32_e32 v6, v9, v7, vcc_lo
	v_cndmask_b32_e64 v11, 0x7ff80000, v8, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v5, v6, v5
	v_cvt_f64_i32_e32 v[6:7], s0
	s_waitcnt vmcnt(0)
	v_mul_f64 v[14:15], v[2:3], v[10:11]
	v_mul_f64 v[10:11], v[0:1], v[10:11]
	v_cndmask_b32_e64 v5, 0x7ff80000, v5, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[0:1], v[0:1], v[4:5], v[14:15]
	v_fma_f64 v[2:3], v[2:3], v[4:5], -v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[4:5], null, v[6:7], v[6:7], v[0:1]
	v_div_scale_f64 v[8:9], null, v[6:7], v[6:7], v[2:3]
	v_div_scale_f64 v[20:21], vcc_lo, v[0:1], v[6:7], v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[10:11], v[4:5]
	v_rcp_f64_e32 v[14:15], v[8:9]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[16:17], -v[4:5], v[10:11], 1.0
	v_fma_f64 v[18:19], -v[8:9], v[14:15], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[10:11], v[10:11], v[16:17], v[10:11]
	v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[16:17], -v[4:5], v[10:11], 1.0
	v_fma_f64 v[18:19], -v[8:9], v[14:15], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[10:11], v[10:11], v[16:17], v[10:11]
	v_div_scale_f64 v[16:17], s0, v[2:3], v[6:7], v[2:3]
	v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[18:19], v[20:21], v[10:11]
	v_mul_f64 v[22:23], v[16:17], v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[4:5], -v[4:5], v[18:19], v[20:21]
	v_fma_f64 v[8:9], -v[8:9], v[22:23], v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[4:5], v[4:5], v[10:11], v[18:19]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[8:9], v[8:9], v[14:15], v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[0:1], v[4:5], v[6:7], v[0:1]
	v_div_fixup_f64 v[2:3], v[8:9], v[6:7], v[2:3]
	global_store_b128 v[12:13], v[0:3], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9mult_ph12iddPdP15HIP_vector_typeIdLj2EE
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 24
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end8:
	.size	_Z9mult_ph12iddPdP15HIP_vector_typeIdLj2EE, .Lfunc_end8-_Z9mult_ph12iddPdP15HIP_vector_typeIdLj2EE
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1356
; NumSgprs: 18
; NumVgprs: 24
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 24
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z8mult_ph1iddP15HIP_vector_typeIdLj2EE ; -- Begin function _Z8mult_ph1iddP15HIP_vector_typeIdLj2EE
	.globl	_Z8mult_ph1iddP15HIP_vector_typeIdLj2EE
	.p2align	8
	.type	_Z8mult_ph1iddP15HIP_vector_typeIdLj2EE,@function
_Z8mult_ph1iddP15HIP_vector_typeIdLj2EE: ; @_Z8mult_ph1iddP15HIP_vector_typeIdLj2EE
; %bb.0:
	s_load_b128 s[4:7], s[0:1], 0x8
	s_mov_b32 s2, 8
	s_mov_b32 s8, 0x2e21c33
	s_load_b64 s[2:3], s[0:1], s2 offset:0x10
	s_mov_b32 s9, 0xbf1b1673
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[1:2], s[4:5], s[4:5]
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x2c
	s_load_b32 s0, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[3:4], null, s[6:7], s[6:7], v[1:2]
	v_div_scale_f64 v[9:10], vcc_lo, v[1:2], s[6:7], v[1:2]
	v_rcp_f64_e32 v[5:6], v[3:4]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[7:8], -v[3:4], v[5:6], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], v[5:6], v[7:8], v[5:6]
	v_fma_f64 v[7:8], -v[3:4], v[5:6], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], v[5:6], v[7:8], v[5:6]
	v_mul_f64 v[7:8], v[9:10], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[3:4], -v[3:4], v[7:8], v[9:10]
	v_div_fmas_f64 v[3:4], v[3:4], v[5:6], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[4:5], v[3:4], s[6:7], v[1:2]
	s_mov_b32 s6, 0xca1d4f33
	s_mov_b32 s7, 0x3f5f9c89
	v_mul_f64 v[1:2], |v[4:5]|, 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fract_f64_e32 v[6:7], v[1:2]
	v_cmp_neq_f64_e32 vcc_lo, 0x7ff00000, v[1:2]
	v_add_f64 v[6:7], v[6:7], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v2, 0, v7 :: v_dual_and_b32 v1, 0x7fffffff, v5
	v_cndmask_b32_e32 v3, 0, v6, vcc_lo
	v_cmp_gt_f64_e64 vcc_lo, |v[4:5]|, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v2, v1, v2 :: v_dual_cndmask_b32 v1, v4, v3
	v_add_f64 v[6:7], v[1:2], v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[6:7], v[6:7]
	v_fma_f64 v[8:9], v[6:7], -0.5, v[1:2]
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	s_mov_b32 s4, 0xf99eb0bb
	s_mov_b32 s5, 0x3f3e357e
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[0:1], 4, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v12, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v13, vcc_lo, s3, v1, vcc_lo
	s_mov_b32 s2, 0x6fdffd2b
	s_mov_b32 s3, 0xbf7e2fe7
	global_load_b128 v[0:3], v[12:13], off
	v_mul_f64 v[10:11], v[8:9], v[8:9]
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[14:15], v[10:11], s[4:5], s[2:3]
	v_fma_f64 v[16:17], v[10:11], s[8:9], s[6:7]
	s_mov_b32 s2, 0xd5f14825
	s_mov_b32 s3, 0x3fb50782
	s_mov_b32 s4, 0x7294bff9
	s_mov_b32 s5, 0xbf9a6d1e
	v_mul_f64 v[18:19], v[8:9], v[10:11]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[14:15], v[10:11], v[14:15], s[2:3]
	v_fma_f64 v[16:17], v[10:11], v[16:17], s[4:5]
	s_mov_b32 s2, 0xcdfe9424
	s_mov_b32 s3, 0xbfe32d2c
	s_mov_b32 s4, 0x67b90b37
	s_mov_b32 s5, 0x3fce1f50
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[14:15], v[10:11], v[14:15], s[2:3]
	v_fma_f64 v[16:17], v[10:11], v[16:17], s[4:5]
	s_mov_b32 s2, 0x67754fff
	s_mov_b32 s3, 0x400466bc
	s_mov_b32 s4, 0x7e3c325b
	s_mov_b32 s5, 0xbff55d3c
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[14:15], v[10:11], v[14:15], s[2:3]
	v_fma_f64 v[16:17], v[10:11], v[16:17], s[4:5]
	s_mov_b32 s2, 0xe625be09
	s_mov_b32 s3, 0xc014abbc
	s_mov_b32 s4, 0x81b5a67
	s_mov_b32 s5, 0x40103c1f
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[14:15], v[10:11], v[14:15], s[2:3]
	v_fma_f64 v[16:17], v[10:11], v[16:17], s[4:5]
	s_mov_b32 s2, 0xc9be45de
	s_mov_b32 s3, 0xc013bd3c
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[14:15], v[18:19], v[14:15]
	v_fma_f64 v[16:17], v[10:11], v[16:17], s[2:3]
	s_mov_b32 s2, 0x54442d18
	s_mov_b32 s3, 0x400921fb
	v_cvt_i32_f64_e32 v18, v[6:7]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[6:7], v[8:9], s[2:3], v[14:15]
	v_fma_f64 v[8:9], v[10:11], v[16:17], 1.0
	v_cmp_class_f64_e64 s2, v[4:5], 0x1f8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v11, 0x80000000, v7
	v_and_b32_e32 v10, 1, v18
	v_cmp_eq_u32_e32 vcc_lo, 0, v10
	v_dual_cndmask_b32 v7, v9, v7 :: v_dual_lshlrev_b32 v4, 30, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v5, v4, v5
	v_cndmask_b32_e32 v10, v8, v6, vcc_lo
	v_dual_cndmask_b32 v11, v11, v9 :: v_dual_and_b32 v4, 0x80000000, v4
	v_dual_cndmask_b32 v6, v6, v8 :: v_dual_and_b32 v5, 0x80000000, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v8, v11, v4
	v_cndmask_b32_e64 v4, 0, v10, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v5, v7, v5
	v_cndmask_b32_e64 v6, 0, v6, s2
	v_cvt_f64_i32_e32 v[10:11], s0
	v_cndmask_b32_e64 v7, 0x7ff80000, v8, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v5, 0x7ff80000, v5, s2
	s_waitcnt vmcnt(0)
	v_mul_f64 v[8:9], v[2:3], v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[2:3], v[2:3], v[4:5]
	v_fma_f64 v[4:5], v[0:1], v[4:5], v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[2:3], v[0:1], v[6:7], -v[2:3]
	v_mul_f64 v[0:1], v[10:11], -v[4:5]
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_f64 v[2:3], v[2:3], v[10:11]
	global_store_b128 v[12:13], v[0:3], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8mult_ph1iddP15HIP_vector_typeIdLj2EE
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 20
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end9:
	.size	_Z8mult_ph1iddP15HIP_vector_typeIdLj2EE, .Lfunc_end9-_Z8mult_ph1iddP15HIP_vector_typeIdLj2EE
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 924
; NumSgprs: 18
; NumVgprs: 20
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 20
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z8mult_ph2iddPdP15HIP_vector_typeIdLj2EE ; -- Begin function _Z8mult_ph2iddPdP15HIP_vector_typeIdLj2EE
	.globl	_Z8mult_ph2iddPdP15HIP_vector_typeIdLj2EE
	.p2align	8
	.type	_Z8mult_ph2iddPdP15HIP_vector_typeIdLj2EE,@function
_Z8mult_ph2iddPdP15HIP_vector_typeIdLj2EE: ; @_Z8mult_ph2iddPdP15HIP_vector_typeIdLj2EE
; %bb.0:
	s_clause 0x1
	s_load_b32 s8, s[0:1], 0x34
	s_load_b256 s[0:7], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s8, s8, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s8, v[0:1]
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 3, v[1:2]
	v_add_co_u32 v3, vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s5, v4, vcc_lo
	s_mov_b32 s4, 0xca1d4f33
	s_mov_b32 s5, 0x3f5f9c89
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(0)
	v_div_scale_f64 v[5:6], null, s[2:3], s[2:3], v[3:4]
	v_div_scale_f64 v[11:12], vcc_lo, v[3:4], s[2:3], v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[7:8], v[5:6]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[9:10], v[11:12], v[7:8]
	v_fma_f64 v[5:6], -v[5:6], v[9:10], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[5:6], v[5:6], v[7:8], v[9:10]
	v_div_fixup_f64 v[3:4], v[5:6], s[2:3], v[3:4]
	s_mov_b32 s2, 0xf99eb0bb
	s_mov_b32 s3, 0x3f3e357e
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[5:6], null, s[0:1], s[0:1], v[3:4]
	v_div_scale_f64 v[11:12], vcc_lo, v[3:4], s[0:1], v[3:4]
	v_rcp_f64_e32 v[7:8], v[5:6]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	v_mul_f64 v[9:10], v[11:12], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], -v[5:6], v[9:10], v[11:12]
	v_div_fmas_f64 v[5:6], v[5:6], v[7:8], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[4:5], v[5:6], s[0:1], v[3:4]
	s_mov_b32 s0, 0x6fdffd2b
	s_mov_b32 s1, 0xbf7e2fe7
	v_mul_f64 v[6:7], |v[4:5]|, 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fract_f64_e32 v[8:9], v[6:7]
	v_cmp_neq_f64_e32 vcc_lo, 0x7ff00000, v[6:7]
	v_add_f64 v[8:9], v[8:9], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v3, 0, v8 :: v_dual_and_b32 v0, 0x7fffffff, v5
	v_cndmask_b32_e32 v6, 0, v9, vcc_lo
	v_cmp_gt_f64_e64 vcc_lo, |v[4:5]|, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v7, v0, v6, vcc_lo
	v_cndmask_b32_e32 v6, v4, v3, vcc_lo
	v_lshlrev_b64 v[0:1], 4, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[8:9], v[6:7], v[6:7]
	v_add_co_u32 v12, vcc_lo, s6, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v13, vcc_lo, s7, v1, vcc_lo
	s_mov_b32 s6, 0x2e21c33
	s_mov_b32 s7, 0xbf1b1673
	global_load_b128 v[0:3], v[12:13], off
	v_rndne_f64_e32 v[8:9], v[8:9]
	v_fma_f64 v[6:7], v[8:9], -0.5, v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[10:11], v[6:7], v[6:7]
	v_fma_f64 v[14:15], v[10:11], s[2:3], s[0:1]
	v_fma_f64 v[16:17], v[10:11], s[6:7], s[4:5]
	s_mov_b32 s0, 0xd5f14825
	s_mov_b32 s1, 0x3fb50782
	s_mov_b32 s2, 0x7294bff9
	s_mov_b32 s3, 0xbf9a6d1e
	v_mul_f64 v[18:19], v[6:7], v[10:11]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[14:15], v[10:11], v[14:15], s[0:1]
	v_fma_f64 v[16:17], v[10:11], v[16:17], s[2:3]
	s_mov_b32 s0, 0xcdfe9424
	s_mov_b32 s1, 0xbfe32d2c
	s_mov_b32 s2, 0x67b90b37
	s_mov_b32 s3, 0x3fce1f50
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[14:15], v[10:11], v[14:15], s[0:1]
	v_fma_f64 v[16:17], v[10:11], v[16:17], s[2:3]
	s_mov_b32 s0, 0x67754fff
	s_mov_b32 s1, 0x400466bc
	s_mov_b32 s2, 0x7e3c325b
	s_mov_b32 s3, 0xbff55d3c
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[14:15], v[10:11], v[14:15], s[0:1]
	v_fma_f64 v[16:17], v[10:11], v[16:17], s[2:3]
	s_mov_b32 s0, 0xe625be09
	s_mov_b32 s1, 0xc014abbc
	s_mov_b32 s2, 0x81b5a67
	s_mov_b32 s3, 0x40103c1f
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[14:15], v[10:11], v[14:15], s[0:1]
	v_fma_f64 v[16:17], v[10:11], v[16:17], s[2:3]
	s_mov_b32 s0, 0xc9be45de
	s_mov_b32 s1, 0xc013bd3c
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[14:15], v[18:19], v[14:15]
	v_fma_f64 v[16:17], v[10:11], v[16:17], s[0:1]
	s_mov_b32 s0, 0x54442d18
	s_mov_b32 s1, 0x400921fb
	v_cvt_i32_f64_e32 v18, v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[6:7], v[6:7], s[0:1], v[14:15]
	v_fma_f64 v[8:9], v[10:11], v[16:17], 1.0
	v_cmp_class_f64_e64 s0, v[4:5], 0x1f8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v4, 30, v18
	v_xor_b32_e32 v5, v4, v5
	v_and_b32_e32 v4, 0x80000000, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_and_b32_e32 v5, 0x80000000, v5
	v_xor_b32_e32 v11, 0x80000000, v7
	v_and_b32_e32 v10, 1, v18
	v_cmp_eq_u32_e32 vcc_lo, 0, v10
	v_cndmask_b32_e32 v7, v9, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v9, v11, v9 :: v_dual_cndmask_b32 v10, v8, v6
	v_cndmask_b32_e32 v6, v6, v8, vcc_lo
	v_xor_b32_e32 v5, v7, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v7, v9, v4
	v_cndmask_b32_e64 v4, 0, v10, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v6, 0, v6, s0
	v_cndmask_b32_e64 v5, 0x7ff80000, v5, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v7, 0x7ff80000, v7, s0
	s_waitcnt vmcnt(0)
	v_mul_f64 v[8:9], v[2:3], v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[10:11], v[2:3], v[6:7]
	v_fma_f64 v[2:3], v[0:1], v[6:7], -v[8:9]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[4:5], v[0:1], v[4:5], v[10:11]
	global_store_b128 v[12:13], v[2:5], off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8mult_ph2iddPdP15HIP_vector_typeIdLj2EE
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 20
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end10:
	.size	_Z8mult_ph2iddPdP15HIP_vector_typeIdLj2EE, .Lfunc_end10-_Z8mult_ph2iddPdP15HIP_vector_typeIdLj2EE
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1016
; NumSgprs: 18
; NumVgprs: 20
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 20
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6get_GjPdS_P15HIP_vector_typeIdLj2EE
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z6get_GjPdS_P15HIP_vector_typeIdLj2EE.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     38
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
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