/*
Parallel Tile Coding Software version 3.0beta translated to C
by Jaden Travnik based on Rich Sutton's Python implementation
*/


// PARALLEL TILECODING
// A gpu kernal function which completes the hashing function started in calCoordAndHashFloat and stores it in d_hashArray on the gpu
__global__ void shiftHash(unsigned * d_hashArray, int size){
	unsigned h = d_hashArray[threadIdx.x];

	h ^= ((unsigned) h >> 20) ^ ((unsigned)h >> 12);
	h = h ^ ((unsigned)h >> 7) ^ ((unsigned)h >> 4);

	d_hashArray[threadIdx.x] = h % size;
}

// A gpu kernel function which takes the floats, and integers and finds hashes their value 
// blockIdx.x is the tile index, threadIdx.x is the index of the coordinate
// d_hashArray is an array of length numTiles, it will contain the hashed index
__global__ void calcCoordAndHashFloat(unsigned * d_hashArray, int numtilings, float * d_floats, int lenFloats, int * d_ints, int lenInts){

	float coord = 1;
	unsigned floatAsInt = 1;
	int offset = threadIdx.x - 2; // these offsets are used to get the same hash results from the serial hashFloatArray function

	if (threadIdx.x > 0){
		coord = (float) blockIdx.x;

		if (threadIdx.x > 1 && threadIdx.x <= lenFloats + 1){

			 // this is the tile mapping function of floating point numbers
			coord = floor((floor(d_floats[offset]*numtilings) + blockIdx.x + offset*blockIdx.x*2) / numtilings);

		} else if (threadIdx.x > lenFloats + 1) {

			// "append" the integers to the coordinate array
			coord = (float) d_ints[offset - lenFloats]; 

		}

		// This is where the hashing function starts. Another hashing function could be used instead and here is where it would be used.
		floatAsInt = *(int*)(&coord); 
	}

	for (int i = 0; i < lenFloats + lenInts + 1 - threadIdx.x; i++){
		floatAsInt *= 31; // cant use pow on the gpu as we want an unsigned overflow
	}

	atomicAdd(& d_hashArray[blockIdx.x], floatAsInt);
}

// returns tile indicies corresponding to the floats and ints
void parallel_tiles(int size, unsigned * d_hashArray, int numtilings, float * d_floats, float *h_floats, int lenFloats, int * d_ints, int *h_ints, int lenInts, unsigned *Tiles) {

	// reset the d_hashArray to be zero so we can add to it in calcCoordAndHashFloat
	cudaMemset(d_hashArray, 0, numtilings*sizeof(unsigned)); 

	// Copy the data from the cpu over to the gpu
	cudaMemcpy(d_floats, h_floats, lenFloats * sizeof(float), cudaMemcpyHostToDevice); 
	cudaMemcpy(d_ints, h_ints, lenInts * sizeof(int), cudaMemcpyHostToDevice);
	
	// call kernel to compute the coordinates and being the hashing function
	calcCoordAndHashFloat<<<numtilings, 2 + lenFloats + lenInts>>>(d_hashArray, numtilings, d_floats, lenFloats, d_ints, lenInts);
	
	// call a kernel to complete the hashing function
	shiftHash<<<1,numtilings>>>(d_hashArray, size);

	// copy the memory from the gpu to the cpu
	cudaMemcpy(Tiles, d_hashArray, numtilings * sizeof(int), cudaMemcpyDeviceToHost);
}
	.file	"tmpxft_002aae0f_00000000-6_parallel_tiles.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2011:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2011:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z29__device_stub__Z9shiftHashPjiPji
	.type	_Z29__device_stub__Z9shiftHashPjiPji, @function
_Z29__device_stub__Z9shiftHashPjiPji:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movl	%esi, 4(%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z9shiftHashPji(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L2:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z29__device_stub__Z9shiftHashPjiPji, .-_Z29__device_stub__Z9shiftHashPjiPji
	.globl	_Z9shiftHashPji
	.type	_Z9shiftHashPji, @function
_Z9shiftHashPji:
.LFB2034:
	.cfi_startproc
	endbr64
	jmp	_Z29__device_stub__Z9shiftHashPjiPji
	.cfi_endproc
.LFE2034:
	.size	_Z9shiftHashPji, .-_Z9shiftHashPji
	.globl	_Z48__device_stub__Z21calcCoordAndHashFloatPjiPfiPiiPjiPfiPii
	.type	_Z48__device_stub__Z21calcCoordAndHashFloatPjiPfiPiiPjiPfiPii, @function
_Z48__device_stub__Z21calcCoordAndHashFloatPjiPfiPiiPjiPfiPii:
.LFB2035:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movl	%esi, 36(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 32(%rsp)
	leaq	64(%rsp), %rcx
	movq	%r8, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	64(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z21calcCoordAndHashFloatPjiPfiPii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 208
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L8:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2035:
	.size	_Z48__device_stub__Z21calcCoordAndHashFloatPjiPfiPiiPjiPfiPii, .-_Z48__device_stub__Z21calcCoordAndHashFloatPjiPfiPiiPjiPfiPii
	.globl	_Z21calcCoordAndHashFloatPjiPfiPii
	.type	_Z21calcCoordAndHashFloatPjiPfiPii, @function
_Z21calcCoordAndHashFloatPjiPfiPii:
.LFB2036:
	.cfi_startproc
	endbr64
	jmp	_Z48__device_stub__Z21calcCoordAndHashFloatPjiPfiPiiPjiPfiPii
	.cfi_endproc
.LFE2036:
	.size	_Z21calcCoordAndHashFloatPjiPfiPii, .-_Z21calcCoordAndHashFloatPjiPfiPii
	.globl	_Z14parallel_tilesiPjiPfS0_iPiS1_iS_
	.type	_Z14parallel_tilesiPjiPfS0_iPiS1_iS_, @function
_Z14parallel_tilesiPjiPfS0_iPiS1_iS_:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%r8, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%r9d, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%edx, %ebx
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	168(%rsp), %rax
	movq	%rsi, 8(%rsp)
	xorl	%esi, %esi
	movl	%edi, 36(%rsp)
	movq	8(%rsp), %rdi
	movq	%rax, 40(%rsp)
	movslq	%edx, %rax
	movl	160(%rsp), %r12d
	salq	$2, %rax
	movq	%rcx, 24(%rsp)
	movq	144(%rsp), %r14
	movq	%rax, %rdx
	movq	152(%rsp), %r15
	movq	%rax, 16(%rsp)
	call	cudaMemset@PLT
	movq	24(%rsp), %rdi
	movslq	%ebp, %rdx
	movq	%r13, %rsi
	salq	$2, %rdx
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movslq	%r12d, %rdx
	movl	$1, %ecx
	movq	%r15, %rsi
	salq	$2, %rdx
	movq	%r14, %rdi
	call	cudaMemcpy@PLT
	leal	2(%rbp,%r12), %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	%eax, 68(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movl	76(%rsp), %ecx
	movq	%rax, 60(%rsp)
	movq	68(%rsp), %rdx
	movl	%ebx, 56(%rsp)
	movl	64(%rsp), %esi
	movq	56(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	movq	24(%rsp), %rdx
	movq	8(%rsp), %rdi
	movl	%r12d, %r9d
	movq	%r14, %r8
	movl	%ebp, %ecx
	movl	%ebx, %esi
	call	_Z48__device_stub__Z21calcCoordAndHashFloatPjiPfiPiiPjiPfiPii
.L14:
	movl	%ebx, 68(%rsp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %esi
	movabsq	$4294967297, %rdi
	movl	$1, 64(%rsp)
	movq	%rdi, 72(%rsp)
	movl	76(%rsp), %ecx
	movq	68(%rsp), %rdx
	movq	%rdi, 56(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L15
	movl	36(%rsp), %esi
	movq	8(%rsp), %rdi
	call	_Z29__device_stub__Z9shiftHashPjiPji
.L15:
	movq	16(%rsp), %rdx
	movq	8(%rsp), %rsi
	movl	$2, %ecx
	movq	40(%rsp), %rdi
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	cudaMemcpy@PLT
	.cfi_endproc
.LFE2008:
	.size	_Z14parallel_tilesiPjiPfS0_iPiS1_iS_, .-_Z14parallel_tilesiPjiPfS0_iPiS1_iS_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z21calcCoordAndHashFloatPjiPfiPii"
.LC1:
	.string	"_Z9shiftHashPji"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2038:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z21calcCoordAndHashFloatPjiPfiPii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z9shiftHashPji(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2038:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
/*
Parallel Tile Coding Software version 3.0beta translated to C
by Jaden Travnik based on Rich Sutton's Python implementation
*/


// PARALLEL TILECODING
// A gpu kernal function which completes the hashing function started in calCoordAndHashFloat and stores it in d_hashArray on the gpu
__global__ void shiftHash(unsigned * d_hashArray, int size){
	unsigned h = d_hashArray[threadIdx.x];

	h ^= ((unsigned) h >> 20) ^ ((unsigned)h >> 12);
	h = h ^ ((unsigned)h >> 7) ^ ((unsigned)h >> 4);

	d_hashArray[threadIdx.x] = h % size;
}

// A gpu kernel function which takes the floats, and integers and finds hashes their value 
// blockIdx.x is the tile index, threadIdx.x is the index of the coordinate
// d_hashArray is an array of length numTiles, it will contain the hashed index
__global__ void calcCoordAndHashFloat(unsigned * d_hashArray, int numtilings, float * d_floats, int lenFloats, int * d_ints, int lenInts){

	float coord = 1;
	unsigned floatAsInt = 1;
	int offset = threadIdx.x - 2; // these offsets are used to get the same hash results from the serial hashFloatArray function

	if (threadIdx.x > 0){
		coord = (float) blockIdx.x;

		if (threadIdx.x > 1 && threadIdx.x <= lenFloats + 1){

			 // this is the tile mapping function of floating point numbers
			coord = floor((floor(d_floats[offset]*numtilings) + blockIdx.x + offset*blockIdx.x*2) / numtilings);

		} else if (threadIdx.x > lenFloats + 1) {

			// "append" the integers to the coordinate array
			coord = (float) d_ints[offset - lenFloats]; 

		}

		// This is where the hashing function starts. Another hashing function could be used instead and here is where it would be used.
		floatAsInt = *(int*)(&coord); 
	}

	for (int i = 0; i < lenFloats + lenInts + 1 - threadIdx.x; i++){
		floatAsInt *= 31; // cant use pow on the gpu as we want an unsigned overflow
	}

	atomicAdd(& d_hashArray[blockIdx.x], floatAsInt);
}

// returns tile indicies corresponding to the floats and ints
void parallel_tiles(int size, unsigned * d_hashArray, int numtilings, float * d_floats, float *h_floats, int lenFloats, int * d_ints, int *h_ints, int lenInts, unsigned *Tiles) {

	// reset the d_hashArray to be zero so we can add to it in calcCoordAndHashFloat
	hipMemset(d_hashArray, 0, numtilings*sizeof(unsigned)); 

	// Copy the data from the cpu over to the gpu
	hipMemcpy(d_floats, h_floats, lenFloats * sizeof(float), hipMemcpyHostToDevice); 
	hipMemcpy(d_ints, h_ints, lenInts * sizeof(int), hipMemcpyHostToDevice);
	
	// call kernel to compute the coordinates and being the hashing function
	calcCoordAndHashFloat<<<numtilings, 2 + lenFloats + lenInts>>>(d_hashArray, numtilings, d_floats, lenFloats, d_ints, lenInts);
	
	// call a kernel to complete the hashing function
	shiftHash<<<1,numtilings>>>(d_hashArray, size);

	// copy the memory from the gpu to the cpu
	hipMemcpy(Tiles, d_hashArray, numtilings * sizeof(int), hipMemcpyDeviceToHost);
}
	.text
	.file	"parallel_tiles.hip"
	.globl	_Z24__device_stub__shiftHashPji # -- Begin function _Z24__device_stub__shiftHashPji
	.type	_Z24__device_stub__shiftHashPji,@function
_Z24__device_stub__shiftHashPji:        # @_Z24__device_stub__shiftHashPji
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9shiftHashPji, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z24__device_stub__shiftHashPji, .Lfunc_end0-_Z24__device_stub__shiftHashPji
	.cfi_endproc
                                        # -- End function
	.globl	_Z36__device_stub__calcCoordAndHashFloatPjiPfiPii # -- Begin function _Z36__device_stub__calcCoordAndHashFloatPjiPfiPii
	.type	_Z36__device_stub__calcCoordAndHashFloatPjiPfiPii,@function
_Z36__device_stub__calcCoordAndHashFloatPjiPfiPii: # @_Z36__device_stub__calcCoordAndHashFloatPjiPfiPii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	48(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	16(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	40(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z21calcCoordAndHashFloatPjiPfiPii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z36__device_stub__calcCoordAndHashFloatPjiPfiPii, .Lfunc_end1-_Z36__device_stub__calcCoordAndHashFloatPjiPfiPii
	.cfi_endproc
                                        # -- End function
	.globl	_Z14parallel_tilesiPjiPfS0_iPiS1_iS_ # -- Begin function _Z14parallel_tilesiPjiPfS0_iPiS1_iS_
	.type	_Z14parallel_tilesiPjiPfS0_iPiS1_iS_,@function
_Z14parallel_tilesiPjiPfS0_iPiS1_iS_:   # @_Z14parallel_tilesiPjiPfS0_iPiS1_iS_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, %ebx
	movq	%r8, (%rsp)                     # 8-byte Spill
	movq	%rcx, %r15
	movq	%rsi, %r14
	movl	%edi, 20(%rsp)                  # 4-byte Spill
	movslq	128(%rsp), %r13
	movq	136(%rsp), %rax
	movq	%rax, 48(%rsp)                  # 8-byte Spill
	movq	112(%rsp), %r12
	movq	120(%rsp), %rax
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	movl	%edx, 12(%rsp)                  # 4-byte Spill
	movslq	%edx, %rbp
	leaq	(,%rbp,4), %rdx
	movq	%rsi, %rdi
	xorl	%esi, %esi
	movq	%rdx, 40(%rsp)                  # 8-byte Spill
	callq	hipMemset
	movl	%ebx, 16(%rsp)                  # 4-byte Spill
	movslq	%ebx, %rbx
	leaq	(,%rbx,4), %rdx
	movq	%r15, 24(%rsp)                  # 8-byte Spill
	movq	%r15, %rdi
	movq	(%rsp), %rsi                    # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%r13, %rdx
	shlq	$2, %rdx
	movq	%r12, (%rsp)                    # 8-byte Spill
	movq	%r12, %rdi
	movq	32(%rsp), %rsi                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	leal	(%rbx,%r13), %edx
	addl	$2, %edx
	movl	%ebp, %r15d
	btsq	$32, %r15
	btsq	$32, %rdx
	movq	%r15, %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_2
# %bb.1:
	movq	%r14, %rdi
	movl	12(%rsp), %esi                  # 4-byte Reload
	movq	24(%rsp), %rdx                  # 8-byte Reload
	movl	16(%rsp), %ecx                  # 4-byte Reload
	movq	(%rsp), %r8                     # 8-byte Reload
	movl	%r13d, %r9d
	callq	_Z36__device_stub__calcCoordAndHashFloatPjiPfiPii
.LBB2_2:
	movabsq	$4294967296, %rdi               # imm = 0x100000000
	incq	%rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB2_4
# %bb.3:
	movq	%r14, %rdi
	movl	20(%rsp), %esi                  # 4-byte Reload
	callq	_Z24__device_stub__shiftHashPji
.LBB2_4:
	movq	48(%rsp), %rdi                  # 8-byte Reload
	movq	%r14, %rsi
	movq	40(%rsp), %rdx                  # 8-byte Reload
	movl	$2, %ecx
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	hipMemcpy                       # TAILCALL
.Lfunc_end2:
	.size	_Z14parallel_tilesiPjiPfS0_iPiS1_iS_, .Lfunc_end2-_Z14parallel_tilesiPjiPfS0_iPiS1_iS_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9shiftHashPji, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z21calcCoordAndHashFloatPjiPfiPii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z9shiftHashPji,@object         # @_Z9shiftHashPji
	.section	.rodata,"a",@progbits
	.globl	_Z9shiftHashPji
	.p2align	3, 0x0
_Z9shiftHashPji:
	.quad	_Z24__device_stub__shiftHashPji
	.size	_Z9shiftHashPji, 8

	.type	_Z21calcCoordAndHashFloatPjiPfiPii,@object # @_Z21calcCoordAndHashFloatPjiPfiPii
	.globl	_Z21calcCoordAndHashFloatPjiPfiPii
	.p2align	3, 0x0
_Z21calcCoordAndHashFloatPjiPfiPii:
	.quad	_Z36__device_stub__calcCoordAndHashFloatPjiPfiPii
	.size	_Z21calcCoordAndHashFloatPjiPfiPii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z9shiftHashPji"
	.size	.L__unnamed_1, 16

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z21calcCoordAndHashFloatPjiPfiPii"
	.size	.L__unnamed_2, 35

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z24__device_stub__shiftHashPji
	.addrsig_sym _Z36__device_stub__calcCoordAndHashFloatPjiPfiPii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z9shiftHashPji
	.addrsig_sym _Z21calcCoordAndHashFloatPjiPfiPii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z9shiftHashPji         ; -- Begin function _Z9shiftHashPji
	.globl	_Z9shiftHashPji
	.p2align	8
	.type	_Z9shiftHashPji,@function
_Z9shiftHashPji:                        ; @_Z9shiftHashPji
; %bb.0:
	s_load_b64 s[2:3], s[0:1], 0x0
	v_lshlrev_b32_e32 v0, 2, v0
	s_load_b32 s0, s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	global_load_b32 v1, v0, s[2:3]
	v_cvt_f32_u32_e32 v2, s0
	s_sub_i32 s1, 0, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v2, v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	v_cvt_u32_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v5, s1, v2
	s_waitcnt vmcnt(0)
	v_lshrrev_b32_e32 v3, 20, v1
	v_lshrrev_b32_e32 v4, 12, v1
	v_xor3_b32 v1, v4, v3, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v3, v2, v5
	v_lshrrev_b32_e32 v4, 7, v1
	v_lshrrev_b32_e32 v5, 4, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v2, v3
	v_xor3_b32 v1, v5, v4, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v2, v1, v2
	v_mul_lo_u32 v2, v2, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v1, v1, v2
	v_subrev_nc_u32_e32 v2, s0, v1
	v_cmp_le_u32_e32 vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v1, v1, v2, vcc_lo
	v_subrev_nc_u32_e32 v2, s0, v1
	v_cmp_le_u32_e32 vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v1, v2, vcc_lo
	global_store_b32 v0, v1, s[2:3]
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9shiftHashPji
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 12
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 4
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z9shiftHashPji, .Lfunc_end0-_Z9shiftHashPji
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 212
; NumSgprs: 6
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 6
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z21calcCoordAndHashFloatPjiPfiPii ; -- Begin function _Z21calcCoordAndHashFloatPjiPfiPii
	.globl	_Z21calcCoordAndHashFloatPjiPfiPii
	.p2align	8
	.type	_Z21calcCoordAndHashFloatPjiPfiPii,@function
_Z21calcCoordAndHashFloatPjiPfiPii:     ; @_Z21calcCoordAndHashFloatPjiPfiPii
; %bb.0:
	s_load_b32 s5, s[0:1], 0x18
	v_mov_b32_e32 v1, 1
	s_mov_b32 s4, s15
	s_mov_b32 s6, exec_lo
	v_cmpx_ne_u32_e32 0, v0
	s_cbranch_execz .LBB1_8
; %bb.1:
	s_waitcnt lgkmcnt(0)
	s_add_i32 s2, s5, 1
	v_cmp_ne_u32_e32 vcc_lo, 1, v0
	v_cmp_ge_u32_e64 s3, s2, v0
	v_cvt_f32_u32_e32 v1, s4
	v_cmp_lt_u32_e64 s2, s2, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s3
	s_and_saveexec_b32 s7, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s7
	s_cbranch_execz .LBB1_3
; %bb.2:
	s_clause 0x1
	s_load_b64 s[8:9], s[0:1], 0x10
	s_load_b32 s7, s[0:1], 0x8
	v_dual_mov_b32 v3, 0 :: v_dual_add_nc_u32 v2, -2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 2, v[2:3]
	v_mul_lo_u32 v2, s4, v2
	v_lshlrev_b32_e32 v2, 1, v2
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s8, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s9, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v2, v2
	global_load_b32 v3, v[3:4], off
	v_cvt_f32_i32_e32 v4, s7
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_floor_f32_e32 v3, v3
	v_add_f32_e32 v1, v3, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v1, v2
	v_div_scale_f32 v2, null, v4, v4, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v3, v2
	s_waitcnt_depctr 0xfff
	v_fma_f32 v5, -v2, v3, 1.0
	v_fmac_f32_e32 v3, v5, v3
	v_div_scale_f32 v5, vcc_lo, v1, v4, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v6, v5, v3
	v_fma_f32 v7, -v2, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, v7, v3
	v_fma_f32 v2, -v2, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v2, v2, v3, v6
	v_div_fixup_f32 v1, v2, v4, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_floor_f32_e32 v1, v1
.LBB1_3:                                ; %Flow40
	s_and_not1_saveexec_b32 s3, s3
	s_cbranch_execz .LBB1_7
; %bb.4:
	s_and_saveexec_b32 s7, s2
	s_cbranch_execz .LBB1_6
; %bb.5:
	s_load_b64 s[8:9], s[0:1], 0x20
	s_ashr_i32 s2, s5, 31
	v_sub_co_u32 v1, s10, v0, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_co_ci_u32_e64 v2, null, 0, s2, s10
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s8, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s9, v2, vcc_lo
	global_load_b32 v1, v[1:2], off offset:-8
	s_waitcnt vmcnt(0)
	v_cvt_f32_i32_e32 v1, v1
.LBB1_6:                                ; %Flow39
	s_or_b32 exec_lo, exec_lo, s7
.LBB1_7:
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_8:                                ; %Flow41
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s6
	s_load_b32 s2, s[0:1], 0x28
	s_waitcnt lgkmcnt(0)
	v_sub_nc_u32_e32 v0, s5, v0
	s_mov_b32 s3, 0
	v_add3_u32 v0, v0, s2, 1
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ne_u32_e32 0, v0
	s_cbranch_execz .LBB1_12
; %bb.9:                                ; %.lr.ph.preheader
	s_mov_b32 s5, 0
.LBB1_10:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_add_i32 s5, s5, 1
	v_mul_lo_u32 v1, v1, 31
	v_cmp_ge_u32_e32 vcc_lo, s5, v0
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_10
; %bb.11:                               ; %Flow
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_12:                               ; %Flow38
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
	s_mov_b32 s3, exec_lo
	s_mov_b32 s2, 0
.LBB1_13:                               ; %ComputeLoop
                                        ; =>This Inner Loop Header: Depth=1
	s_ctz_i32_b32 s5, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_readlane_b32 s6, v1, s5
	s_lshl_b32 s5, 1, s5
	s_and_not1_b32 s3, s3, s5
	s_delay_alu instid0(VALU_DEP_1)
	s_add_i32 s2, s2, s6
	s_cmp_lg_u32 s3, 0
	s_cbranch_scc1 .LBB1_13
; %bb.14:                               ; %ComputeEnd
	v_mbcnt_lo_u32_b32 v0, exec_lo, 0
	s_mov_b32 s5, 0
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v0
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB1_16
; %bb.15:
	s_load_b64 s[0:1], s[0:1], 0x0
	s_lshl_b64 s[4:5], s[4:5], 2
	v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s0, s4
	s_addc_u32 s1, s1, s5
	global_atomic_add_u32 v0, v1, s[0:1]
.LBB1_16:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z21calcCoordAndHashFloatPjiPfiPii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 44
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z21calcCoordAndHashFloatPjiPfiPii, .Lfunc_end1-_Z21calcCoordAndHashFloatPjiPfiPii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 644
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 12
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9shiftHashPji
    .private_segment_fixed_size: 0
    .sgpr_count:     6
    .sgpr_spill_count: 0
    .symbol:         _Z9shiftHashPji.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .offset:         40
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 44
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z21calcCoordAndHashFloatPjiPfiPii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z21calcCoordAndHashFloatPjiPfiPii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
