// Copyright 2016 Boris Dimitrov, Portola Valley, CA 94028.
// Questions? Contact http://www.facebook.com/boris
//
// This program counts all permutations of the sequence 1, 1, 2, 2, 3, 3, ..., n, n
// in which the two appearances of each m are separated by precisely m other numbers.
// These permutations are called Langford pairings.  For n=3, only one such exists,
// (modulo left-to-right reversal):  2, 3, 1, 2, 1, 3.  Pairings exist only for n
// that are congruent with 0 or 3 mod 4, and their count grows very rapidly with n.
// See http://www.dialectrix.com/langford.html or Knuth volume 4a page 1 (chapter 7).
//
// The crux of this program does not use off-chip memory;  everything fits in GPU L2
// and (I hope) in CPU L1 cache.  No floating point, just int ops and array derefs.
//
// Compile on ubuntu with cuda8rc as follows:
//
//    nvcc -o langford -std=c++11 langford.cu
//
// Comparing this same algorithm on three different processors,
//
//               22nm i7-4790K        14nm E5-2699v4     16nm TitanX Pascal GPU
//                  4c @ 4 GHz         22c @ 2.8 GHz             28c @ 1.82 GHz
//   --------------------------------------------------------------------------
//
//   n = 15       28.1 seconds           8.9 seconds               2.35 seconds
//
//   n = 16      309.1 seconds          92.4 seconds               23.5 seconds
//
//   n = 19                n/a           41.62 hours                10.72 hours
//   --------------------------------------------------------------------------
//   normalized           1.0x                 3.25x                      12.5x
//   perf units
//
//   cost per
//   unit perf            $335                $1,415                        $96
//   (fall 2016)
//
// Matching perf to hardware,
//
//      1.0x == Late-2014 iMac5k with i7-4790K CPU running all 4 cores at 4 GHz
//
//     3.25x == Early-2016 Xeon E5-2699 v4 CPU running all 22 cores at 2.8 GHz
//              (overall about 3.25x faster than the reference iMac)
//
//     12.5x == Q3-2016 Titan X Pascal GPU running all 28 SM's at 1.82 GHz
//
//       25x == dual GPU (projection)
//
// Each GPU SM is 3.05x faster than its Xeon counterpart (2.67x with Turbo Boost).
// Overall, the $1,200 Pascal GPU is 3.9x faster than the $4,600 Broadwell CPU.
// That makes GPU 15x cheaper than CPU per unit of perf.
//
// This is GPU version z3 and the comparison was to CPU version z2
// (available upon request).
//

// The value of N is the only "input" to this program.
constexpr int n = 16;
static_assert(n >= 7, "so we can unroll n <= 6");

#include <iostream>
#include <chrono>
using namespace std;
using chrono::steady_clock;

#include <cuda_runtime.h>

struct Seconds {
    chrono::duration<double> d;
    Seconds(chrono::duration<double> d_) : d(d_) {}
};

ostream& operator << (ostream& out, const Seconds& seconds) {
    return (out << seconds.d.count());
}

constexpr int n_minus_1 = n - 1;
constexpr int two_n = 2 * n;

constexpr int padded_n = ((n + 3) >> 2) << 2;

constexpr int64_t lsb = 1;
constexpr int64_t msb = lsb << (2 * n - 1);
constexpr int64_t full = msb | (msb - 1);

// Fewer threads per block => more threads can be packed in L2 => higher "occupancy",
// which would normally be a good thing, except... it causes higher power draw,
// and occupancy > 0.25 actually results in lower perf.
//
// for n=15, threads_per_block=12 is optimal, with 16, 8, and 32 all pretty close
// for n=16, threads_per_blocks=16 and 32 take 23.5 seconds;  12 takes 24.1 seconds;  8 takes 25 sec
// for n=19, threads_per_blocks=32 takes 13.13 hours; 16 takes 11 hours; 8 takes 10.7 hours
// so 8 works fine overall, but we can micro-optimize for some n
constexpr int threads_per_block = (n == 15) ? 12
                                            : (n == 16) ? 16
                                                        : 8;

constexpr int div_up(int p, int q) {
    return (p + (q - 1)) / q;
}

//  We launch (n-1) * (2*n) * (2*n) * (2*n) threads.   Each thread starts with a specific initial
//  placement of m = 1, 2, 3, 4 and its job is to extend and complete that placement in every
//  possible way for m = 5, 6, ..., 2*n.  The placement of m = 1 is restricted to positions
//  0, 1, ..., n-2 in order to avoid double-counting left-to-right reversal twins.
//
//  The threads are organized in a 3D grid of blocks, with each block comprising a small number
//  of threads, say 8 or 16 or 32.  The threads within a block share the L2 of their streaming
//  multiprocessor.  They divide that L2 into separate areas used for their stacks and heaps.
//
//  All threads in a block share the placement of m = 3 and m = 4 which is directly given by
//  the block's y and z coordinates.  The block's x coordinate and each thread's x index together
//  encode the placement of m = 1 and m = 2 in that thread.
//
//  Alternative mappings (for example, a simple 1-D mapping) are possible, with similar perf.
//  This 3-D one was chosen after the 1-D version bumped into some undocumented per-dimension
//  limits in Cuda-8rc.

constexpr int blocks_x = div_up((n-1)*(2*n), threads_per_block);
constexpr int blocks_y = 2*n;
constexpr int blocks_z = 2*n;

dim3 blocks(blocks_x, blocks_y, blocks_z);

constexpr int total_threads_padded = blocks_x * blocks_y * blocks_z * threads_per_block;

__global__ void dfs(int64_t* d_count) {
    // shared vars are per thread-block and held in L2 cache
    // local scalar vars are per thread and held in registers
    __shared__ int64_t l2_stacks[threads_per_block][padded_n << 1];
    __shared__ int64_t l2_heaps[threads_per_block][padded_n];
    int64_t a, m, pos_k, avail, cnt;
    int top;
    // Nomenclature:
    //
    //     0 <= me <= n-2 is the left pos for m = 1
    //     0 <= me2 < 2*n is the left pos for m = 2, and me2r = me2 + 3 is the right pos
    //     0 <= me3 < 2*n is the left pos for m = 3, and me3r = me3 + 4 is the right pos
    //     0 <= me4 < 2*n is the left pos for m = 4, and me4r = me4 + 5 is the right pps
    //
    // By construction,
    //
    //     me3 = blockIdx.y,
    //     me4 = blockIdx.z,
    //     me and me2 are packed, in a special way, into (blockIdx.x, threadIdx.x)
    //
    const int tmp = blockIdx.x * threads_per_block + threadIdx.x;
    const int me = tmp / two_n;
    if (me < n_minus_1) {
        const int me2r = tmp - me * two_n + 3;
        const int me3r = blockIdx.y + 4;
        const int me4r = blockIdx.z + 5;
        if (me2r < two_n && me3r < two_n && me4r < two_n) {
            const int64_t a1 = (lsb << me) | (lsb << (me + 2));
            const int64_t a2 = (lsb << (me2r - 3)) | (lsb << (me2r));
            const int64_t a3 = (lsb << blockIdx.y) | (lsb << (me3r));
            const int64_t a4 = (lsb << blockIdx.z) | (lsb << (me4r));
            a = a1 | a2 | a3 | a4;
            // are a1, a2, a3, a4 pairwise disjoint?  that means we have valid placement for m=1,2,3,4
            if (a == (a1 + a2 + a3 + a4)) {
                // compute all positions where m = 5 can be placed, given that m=1,2,3,4 have been
                // placed already in the positions given by a1, a2, a3, a4 above
                avail = a ^ full;         // invert a;  note upper bits >= pos 2*n are all 1 (important
                avail &= (avail >> 6);    // for the correctness of these two lines as a block).
                // can our valid placement for m=1,2,3,4 be continued for m=5?
                if (avail) {
                    cnt = 0;
                    m = 5;
                    top = 0;
                    // record all possible continuations for m=4 into the stack and start DFS loop
                    auto& stack = l2_stacks[threadIdx.x];
                    auto& heap = l2_heaps[threadIdx.x];
                    stack[top++] = avail;
                    stack[top++] = m;
                    heap[m-1] = a;
                    while (top) {
                        m = stack[top - 1];
                        avail = stack[top - 2];
                        // extract the lowest bit that is set to 1 in avail
                        pos_k = avail & ~(avail - 1);
                        // clear that bit
                        avail ^= pos_k;
                        // "pop" that bit from the hybrid stack s
                        if (avail) {
                            stack[top - 2] = avail;
                        } else {
                            top -= 2;
                        }
                        // place m in that position
                        a  = heap[m-1] | pos_k | (pos_k << (m + 1));
                        ++m;
                        // the "avail" computed below has bit "k" set to 1 if and only if
                        // both of the positions "k" and "k + m + 1" in "a" contain 0
                        avail = a ^ full;
                        avail &= (avail >> (m + 1));
                        if (avail) {
                            if (m == n) {
                                // we've found another langford pairing, count it
                                ++cnt;
                            } else {
                                // push all possible ways to place m, to be explored in subsequent iterations
                                stack[top++] = avail;
                                stack[top++] = m;
                                heap[m-1] = a;
                            }
                        }
                    }
                    // Write this thread's result to off-chip memory.
                    const int blid = blockIdx.x + blocks_x * (blockIdx.y + blocks_y * blockIdx.z);
                    d_count[blid * threads_per_block + threadIdx.x] = cnt;
                }
            }
        }
    }
}

void cdo(const char* txt, cudaError_t err) {
    if (err == cudaSuccess) {
        return;
    }
    cout << "Failed to " << txt << " (Error code " << cudaGetErrorString(err) << ")\n" << flush;
    exit(-1);
}

void run() {
    int64_t* count;
    int64_t* d_count;
    int64_t total;
    {
        cout << "\n";
        cout << "\n";
        cout << "------\n";
        cout << "Computing Langford number L(2,n) for n = " << n << ".\n";
        cout << "\n";
        cout << "GPU init " << flush;
    }
    auto t0 = steady_clock::now();
    auto seconds_since = [](decltype(t0) start) {
        return Seconds(steady_clock::now() - start);
    };
    cudaEvent_t start, stop;
    cdo("create start timer event",
        cudaEventCreate(&start));
    cdo("create stop timer event",
        cudaEventCreate(&stop, cudaEventBlockingSync));
    cdo("allocate host memory",
        cudaMallocHost(&count, total_threads_padded * sizeof(*count)));
    for (int i=0; i<total_threads_padded; ++i) {
        count[i] = -1;
    }
    cdo("allocate GPU memory",
        cudaMalloc(&d_count, total_threads_padded * sizeof(*count)));
    cdo("copy initial values from host to GPU",
        cudaMemcpy(d_count, count, sizeof(*count) * total_threads_padded, cudaMemcpyDeviceToHost));
    cdo("insert start event",
        cudaEventRecord(start));
    {
        cout << "took " << seconds_since(t0) << " sec.\n";
        cout << "\n";
        cout << "Dispatching " << total_threads_padded << " threads (" << threads_per_block << " per block, "
             << blocks.x << " x " << blocks.y << " x " << blocks.z << " blocks).\n" << flush;
    }
    auto t1 = steady_clock::now();
    dfs<<<blocks, threads_per_block>>>(d_count);
    cdo("DFS kernel launch",
        cudaPeekAtLastError());
    cdo("insert stop event",
        cudaEventRecord(stop));
    {
        cout << "\n";
        cout << "GPU computation " << flush;
    }
    cdo("wait for GPU computation to complete",
        cudaEventSynchronize(stop));
    float milliseconds = 0;
    cdo("compute GPU elapsed time",
        cudaEventElapsedTime(&milliseconds, start, stop));
    {
        cout << "took " << milliseconds / 1000.0 << " sec on GPU clock, "
             << seconds_since(t1) << " sec on host clock.\n";
        cout << "\n";
        cout << "CPU reduction " << flush;
    }
    auto t2 = steady_clock::now();
    cdo("copy result from GPU to host",
        cudaMemcpy(count, d_count, sizeof(*count) * total_threads_padded, cudaMemcpyDeviceToHost));
    total = 0;
    for (int i=0; i<total_threads_padded; ++i) {
        if (count[i] >= 0) {
            total += count[i];
        }
    }
    {
        int64_t known_results[64];
        memset(&known_results[0], 0, sizeof(known_results));
        known_results[3]  = 1;
        known_results[4]  = 1;
        known_results[7]  = 26;
        known_results[8]  = 150;
        known_results[11] = 17792;
        known_results[12] = 108144;
        known_results[15] = 39809640ll;
        known_results[16] = 326721800ll;
        known_results[19] = 256814891280ll;
        known_results[20] = 2636337861200ll;
        known_results[23] = 3799455942515488ll;
        known_results[24] = 46845158056515936ll;
        // beyond 23, count does not fit in 64 bits and is not definitively known!
        cout << "took " << seconds_since(t2) << " sec.\n";
        cout << "\n";
        cout << "Result " << total << " for n = " << n << " " << flush;
        cout << ((total == known_results[n]) ? "matches" : "** DOES NOT MATCH **")
             << " previously known result.\n";
        cout << "------\n";
        cout << "\n";
        cout << "\n";
    }
    cdo("free GPU memory for result",
        cudaFree(d_count));
    cdo("free host memory for result",
        cudaFreeHost(count));
}

int main(int argc, char** argv) {
    run();
    return 0;
}

	.file	"tmpxft_00328659_00000000-6_langford.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3749:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3749:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.align 2
	.type	_ZNSolsEPFRSoS_E.isra.0, @function
_ZNSolsEPFRSoS_E.isra.0:
.LFB4461:
	.cfi_startproc
	jmp	*%rsi
	.cfi_endproc
.LFE4461:
	.size	_ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0
	.align 2
	.type	_ZZ3runvENKUlNSt6chrono10time_pointINS_3_V212steady_clockENS_8durationIlSt5ratioILl1ELl1000000000EEEEEEE_clES7_.isra.0, @function
_ZZ3runvENKUlNSt6chrono10time_pointINS_3_V212steady_clockENS_8durationIlSt5ratioILl1ELl1000000000EEEEEEE_clES7_.isra.0:
.LFB4462:
	.cfi_startproc
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movq	%rdi, %rbx
	call	_ZNSt6chrono3_V212steady_clock3nowEv@PLT
	subq	%rbx, %rax
	popq	%rbx
	.cfi_def_cfa_offset 8
	cvtsi2sdq	%rax, %xmm0
	divsd	.LC0(%rip), %xmm0
	ret
	.cfi_endproc
.LFE4462:
	.size	_ZZ3runvENKUlNSt6chrono10time_pointINS_3_V212steady_clockENS_8durationIlSt5ratioILl1ELl1000000000EEEEEEE_clES7_.isra.0, .-_ZZ3runvENKUlNSt6chrono10time_pointINS_3_V212steady_clockENS_8durationIlSt5ratioILl1ELl1000000000EEEEEEE_clES7_.isra.0
	.globl	_ZlsRSoRK7Seconds
	.type	_ZlsRSoRK7Seconds, @function
_ZlsRSoRK7Seconds:
.LFB3738:
	.cfi_startproc
	endbr64
	movsd	(%rsi), %xmm0
	jmp	_ZNSo9_M_insertIdEERSoT_@PLT
	.cfi_endproc
.LFE3738:
	.size	_ZlsRSoRK7Seconds, .-_ZlsRSoRK7Seconds
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"Failed to "
.LC2:
	.string	" (Error code "
.LC3:
	.string	")\n"
	.text
	.globl	_Z3cdoPKc9cudaError
	.type	_Z3cdoPKc9cudaError, @function
_Z3cdoPKc9cudaError:
.LFB3740:
	.cfi_startproc
	endbr64
	testl	%esi, %esi
	je	.L8
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movq	%rdi, %rbp
	leaq	_ZSt4cout(%rip), %rdi
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	movl	%esi, %ebx
	leaq	.LC1(%rip), %rsi
	pushq	%rax
	.cfi_def_cfa_offset 32
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rbp, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC2(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%ebx, %edi
	movq	%rax, %rbp
	call	cudaGetErrorString@PLT
	movq	%rbp, %rdi
	movq	%rax, %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC3(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt5flushIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	orl	$-1, %edi
	call	exit@PLT
.L8:
	.cfi_def_cfa_offset 8
	.cfi_restore 3
	.cfi_restore 6
	ret
	.cfi_endproc
.LFE3740:
	.size	_Z3cdoPKc9cudaError, .-_Z3cdoPKc9cudaError
	.globl	_Z22__device_stub__Z3dfsPlPl
	.type	_Z22__device_stub__Z3dfsPlPl, @function
_Z22__device_stub__Z3dfsPlPl:
.LFB3771:
	.cfi_startproc
	endbr64
	subq	$104, %rsp
	.cfi_def_cfa_offset 112
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	16(%rsp), %rdx
	leaq	44(%rsp), %rsi
	leaq	32(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 88(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	24(%rsp)
	.cfi_def_cfa_offset 120
	leaq	_Z3dfsPl(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 128
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 120
	popq	%rdx
	.cfi_def_cfa_offset 112
.L13:
	movq	88(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$104, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3771:
	.size	_Z22__device_stub__Z3dfsPlPl, .-_Z22__device_stub__Z3dfsPlPl
	.globl	_Z3dfsPl
	.type	_Z3dfsPl, @function
_Z3dfsPl:
.LFB3772:
	.cfi_startproc
	endbr64
	jmp	_Z22__device_stub__Z3dfsPlPl
	.cfi_endproc
.LFE3772:
	.size	_Z3dfsPl, .-_Z3dfsPl
	.section	.rodata.str1.1
.LC4:
	.string	"matches"
.LC5:
	.string	"** DOES NOT MATCH **"
.LC6:
	.string	"\n"
.LC7:
	.string	"------\n"
.LC8:
	.string	"Computing Langford number L(2,n) for n = "
.LC9:
	.string	".\n"
.LC10:
	.string	"GPU init "
.LC11:
	.string	"create start timer event"
.LC12:
	.string	"create stop timer event"
.LC13:
	.string	"allocate host memory"
.LC14:
	.string	"allocate GPU memory"
.LC15:
	.string	"copy initial values from host to GPU"
.LC16:
	.string	"insert start event"
.LC17:
	.string	"took "
.LC18:
	.string	" sec.\n"
.LC19:
	.string	"Dispatching "
.LC20:
	.string	" threads ("
.LC21:
	.string	" per block, "
.LC22:
	.string	" x "
.LC23:
	.string	" blocks).\n"
.LC24:
	.string	"DFS kernel launch"
.LC25:
	.string	"insert stop event"
.LC26:
	.string	"GPU computation "
.LC27:
	.string	"wait for GPU computation to complete"
.LC29:
	.string	"compute GPU elapsed time"
.LC31:
	.string	" sec on GPU clock, "
.LC32:
	.string	" sec on host clock.\n"
.LC33:
	.string	"CPU reduction "
.LC34:
	.string	"copy result from GPU to host"
.LC35:
	.string	"Result "
.LC36:
	.string	" for n = "
.LC37:
	.string	" "
.LC38:
	.string	" previously known result.\n"
.LC39:
	.string	"free GPU memory for result"
.LC40:
	.string	"free host memory for result"
	.text
	.globl	_Z3runv
	.type	_Z3runv, @function
_Z3runv:
.LFB3741:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	leaq	.LC6(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	leaq	.LC7(%rip), %r14
	leaq	.LC18(%rip), %r15
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	leaq	.LC17(%rip), %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC6(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%r14, %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC8(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$16, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC9(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC6(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC10(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt5flushIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	call	_ZNSt6chrono3_V212steady_clock3nowEv@PLT
	leaq	24(%rsp), %rdi
	movq	%rax, %r12
	call	cudaEventCreate@PLT
	leaq	.LC11(%rip), %rdi
	movl	%eax, %esi
	call	_Z3cdoPKc9cudaError
	leaq	32(%rsp), %rdi
	movl	$1, %esi
	call	cudaEventCreateWithFlags@PLT
	leaq	.LC12(%rip), %rdi
	movl	%eax, %esi
	call	_Z3cdoPKc9cudaError
	xorl	%edx, %edx
	leaq	8(%rsp), %rdi
	movl	$3932160, %esi
	call	cudaHostAlloc@PLT
	leaq	.LC13(%rip), %rdi
	movl	%eax, %esi
	call	_Z3cdoPKc9cudaError
	movq	8(%rsp), %rdi
	movb	$-1, %al
	movl	$3932160, %ecx
	movl	$3932160, %esi
	rep stosb
	leaq	16(%rsp), %rdi
	call	cudaMalloc@PLT
	leaq	.LC14(%rip), %rdi
	movl	%eax, %esi
	call	_Z3cdoPKc9cudaError
	movq	8(%rsp), %rsi
	movq	16(%rsp), %rdi
	movl	$2, %ecx
	movl	$3932160, %edx
	call	cudaMemcpy@PLT
	leaq	.LC15(%rip), %rdi
	movl	%eax, %esi
	call	_Z3cdoPKc9cudaError
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	leaq	.LC16(%rip), %rdi
	movl	%eax, %esi
	call	_Z3cdoPKc9cudaError
	movq	%rbp, %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%r12, %rdi
	leaq	40(%rsp), %r12
	movq	%rax, %rbx
	call	_ZZ3runvENKUlNSt6chrono10time_pointINS_3_V212steady_clockENS_8durationIlSt5ratioILl1ELl1000000000EEEEEEE_clES7_.isra.0
	movq	%rbx, %rdi
	movq	%r12, %rsi
	leaq	.LC22(%rip), %rbx
	movsd	%xmm0, 40(%rsp)
	call	_ZlsRSoRK7Seconds
	movq	%r15, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC6(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC19(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$491520, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC20(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$16, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC21(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	blocks(%rip), %esi
	movq	%rax, %rdi
	call	_ZNSo9_M_insertImEERSoT_@PLT
	movq	%rbx, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	4+blocks(%rip), %esi
	movq	%rax, %rdi
	call	_ZNSo9_M_insertImEERSoT_@PLT
	movq	%rbx, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	8+blocks(%rip), %esi
	movq	%rax, %rdi
	call	_ZNSo9_M_insertImEERSoT_@PLT
	leaq	.LC23(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt5flushIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	call	_ZNSt6chrono3_V212steady_clock3nowEv@PLT
	movl	$268435457, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	blocks(%rip), %rdi
	movl	8+blocks(%rip), %esi
	movq	%rax, %r13
	salq	$4, %rdx
	movl	$1, %ecx
	movq	%rdx, 40(%rsp)
	movl	$1, 48(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	movq	16(%rsp), %rdi
	call	_Z22__device_stub__Z3dfsPlPl
.L19:
	call	cudaPeekAtLastError@PLT
	leaq	.LC24(%rip), %rdi
	movl	%eax, %esi
	call	_Z3cdoPKc9cudaError
	movq	32(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	leaq	.LC25(%rip), %rdi
	movl	%eax, %esi
	call	_Z3cdoPKc9cudaError
	leaq	.LC6(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC26(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt5flushIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movq	32(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	leaq	.LC27(%rip), %rdi
	movl	%eax, %esi
	call	_Z3cdoPKc9cudaError
	movq	32(%rsp), %rdx
	movq	24(%rsp), %rsi
	leaq	4(%rsp), %rdi
	movl	$0x00000000, 4(%rsp)
	call	cudaEventElapsedTime@PLT
	leaq	.LC29(%rip), %rdi
	movl	%eax, %esi
	call	_Z3cdoPKc9cudaError
	movq	%rbp, %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	cvtss2sd	4(%rsp), %xmm0
	divsd	.LC30(%rip), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC31(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%r13, %rdi
	movq	%rax, %rbx
	call	_ZZ3runvENKUlNSt6chrono10time_pointINS_3_V212steady_clockENS_8durationIlSt5ratioILl1ELl1000000000EEEEEEE_clES7_.isra.0
	movq	%rbx, %rdi
	movq	%r12, %rsi
	xorl	%ebx, %ebx
	movsd	%xmm0, 40(%rsp)
	call	_ZlsRSoRK7Seconds
	leaq	.LC32(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC6(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC33(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt5flushIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	call	_ZNSt6chrono3_V212steady_clock3nowEv@PLT
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	$2, %ecx
	movl	$3932160, %edx
	movq	%rax, %r13
	call	cudaMemcpy@PLT
	leaq	.LC34(%rip), %rdi
	movl	%eax, %esi
	call	_Z3cdoPKc9cudaError
	movq	8(%rsp), %rcx
	xorl	%eax, %eax
.L21:
	movq	(%rcx,%rax,8), %rdx
	testq	%rdx, %rdx
	js	.L20
	addq	%rdx, %rbx
.L20:
	incq	%rax
	cmpq	$491520, %rax
	jne	.L21
	movq	%rbp, %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%r13, %rdi
	movq	%rax, %rbp
	call	_ZZ3runvENKUlNSt6chrono10time_pointINS_3_V212steady_clockENS_8durationIlSt5ratioILl1ELl1000000000EEEEEEE_clES7_.isra.0
	movq	%r12, %rsi
	movq	%rbp, %rdi
	movsd	%xmm0, 40(%rsp)
	call	_ZlsRSoRK7Seconds
	movq	%r15, %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC6(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC35(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rbx, %rsi
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIlEERSoT_@PLT
	leaq	.LC36(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	$16, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	leaq	.LC37(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt5flushIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	cmpq	$326721800, %rbx
	leaq	.LC4(%rip), %rax
	leaq	.LC5(%rip), %rsi
	cmove	%rax, %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC38(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%r14, %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC6(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	.LC6(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	leaq	.LC39(%rip), %rdi
	movl	%eax, %esi
	call	_Z3cdoPKc9cudaError
	movq	8(%rsp), %rdi
	call	cudaFreeHost@PLT
	leaq	.LC40(%rip), %rdi
	movl	%eax, %esi
	call	_Z3cdoPKc9cudaError
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L23
	call	__stack_chk_fail@PLT
.L23:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3741:
	.size	_Z3runv, .-_Z3runv
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3746:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	call	_Z3runv
	xorl	%eax, %eax
	popq	%rdx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3746:
	.size	main, .-main
	.section	.rodata.str1.1
.LC41:
	.string	"_Z3dfsPl"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3774:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC41(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z3dfsPl(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3774:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.globl	blocks
	.data
	.align 8
	.type	blocks, @object
	.size	blocks, 12
blocks:
	.long	30
	.long	32
	.long	32
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC0:
	.long	0
	.long	1104006501
	.align 8
.LC30:
	.long	0
	.long	1083129856
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

// Copyright 2016 Boris Dimitrov, Portola Valley, CA 94028.
// Questions? Contact http://www.facebook.com/boris
//
// This program counts all permutations of the sequence 1, 1, 2, 2, 3, 3, ..., n, n
// in which the two appearances of each m are separated by precisely m other numbers.
// These permutations are called Langford pairings.  For n=3, only one such exists,
// (modulo left-to-right reversal):  2, 3, 1, 2, 1, 3.  Pairings exist only for n
// that are congruent with 0 or 3 mod 4, and their count grows very rapidly with n.
// See http://www.dialectrix.com/langford.html or Knuth volume 4a page 1 (chapter 7).
//
// The crux of this program does not use off-chip memory;  everything fits in GPU L2
// and (I hope) in CPU L1 cache.  No floating point, just int ops and array derefs.
//
// Compile on ubuntu with cuda8rc as follows:
//
//    nvcc -o langford -std=c++11 langford.cu
//
// Comparing this same algorithm on three different processors,
//
//               22nm i7-4790K        14nm E5-2699v4     16nm TitanX Pascal GPU
//                  4c @ 4 GHz         22c @ 2.8 GHz             28c @ 1.82 GHz
//   --------------------------------------------------------------------------
//
//   n = 15       28.1 seconds           8.9 seconds               2.35 seconds
//
//   n = 16      309.1 seconds          92.4 seconds               23.5 seconds
//
//   n = 19                n/a           41.62 hours                10.72 hours
//   --------------------------------------------------------------------------
//   normalized           1.0x                 3.25x                      12.5x
//   perf units
//
//   cost per
//   unit perf            $335                $1,415                        $96
//   (fall 2016)
//
// Matching perf to hardware,
//
//      1.0x == Late-2014 iMac5k with i7-4790K CPU running all 4 cores at 4 GHz
//
//     3.25x == Early-2016 Xeon E5-2699 v4 CPU running all 22 cores at 2.8 GHz
//              (overall about 3.25x faster than the reference iMac)
//
//     12.5x == Q3-2016 Titan X Pascal GPU running all 28 SM's at 1.82 GHz
//
//       25x == dual GPU (projection)
//
// Each GPU SM is 3.05x faster than its Xeon counterpart (2.67x with Turbo Boost).
// Overall, the $1,200 Pascal GPU is 3.9x faster than the $4,600 Broadwell CPU.
// That makes GPU 15x cheaper than CPU per unit of perf.
//
// This is GPU version z3 and the comparison was to CPU version z2
// (available upon request).
//

// The value of N is the only "input" to this program.
constexpr int n = 16;
static_assert(n >= 7, "so we can unroll n <= 6");

#include <iostream>
#include <chrono>
using namespace std;
using chrono::steady_clock;

#include <hip/hip_runtime.h>

struct Seconds {
    chrono::duration<double> d;
    Seconds(chrono::duration<double> d_) : d(d_) {}
};

ostream& operator << (ostream& out, const Seconds& seconds) {
    return (out << seconds.d.count());
}

constexpr int n_minus_1 = n - 1;
constexpr int two_n = 2 * n;

constexpr int padded_n = ((n + 3) >> 2) << 2;

constexpr int64_t lsb = 1;
constexpr int64_t msb = lsb << (2 * n - 1);
constexpr int64_t full = msb | (msb - 1);

// Fewer threads per block => more threads can be packed in L2 => higher "occupancy",
// which would normally be a good thing, except... it causes higher power draw,
// and occupancy > 0.25 actually results in lower perf.
//
// for n=15, threads_per_block=12 is optimal, with 16, 8, and 32 all pretty close
// for n=16, threads_per_blocks=16 and 32 take 23.5 seconds;  12 takes 24.1 seconds;  8 takes 25 sec
// for n=19, threads_per_blocks=32 takes 13.13 hours; 16 takes 11 hours; 8 takes 10.7 hours
// so 8 works fine overall, but we can micro-optimize for some n
constexpr int threads_per_block = (n == 15) ? 12
                                            : (n == 16) ? 16
                                                        : 8;

constexpr int div_up(int p, int q) {
    return (p + (q - 1)) / q;
}

//  We launch (n-1) * (2*n) * (2*n) * (2*n) threads.   Each thread starts with a specific initial
//  placement of m = 1, 2, 3, 4 and its job is to extend and complete that placement in every
//  possible way for m = 5, 6, ..., 2*n.  The placement of m = 1 is restricted to positions
//  0, 1, ..., n-2 in order to avoid double-counting left-to-right reversal twins.
//
//  The threads are organized in a 3D grid of blocks, with each block comprising a small number
//  of threads, say 8 or 16 or 32.  The threads within a block share the L2 of their streaming
//  multiprocessor.  They divide that L2 into separate areas used for their stacks and heaps.
//
//  All threads in a block share the placement of m = 3 and m = 4 which is directly given by
//  the block's y and z coordinates.  The block's x coordinate and each thread's x index together
//  encode the placement of m = 1 and m = 2 in that thread.
//
//  Alternative mappings (for example, a simple 1-D mapping) are possible, with similar perf.
//  This 3-D one was chosen after the 1-D version bumped into some undocumented per-dimension
//  limits in Cuda-8rc.

constexpr int blocks_x = div_up((n-1)*(2*n), threads_per_block);
constexpr int blocks_y = 2*n;
constexpr int blocks_z = 2*n;

dim3 blocks(blocks_x, blocks_y, blocks_z);

constexpr int total_threads_padded = blocks_x * blocks_y * blocks_z * threads_per_block;

__global__ void dfs(int64_t* d_count) {
    // shared vars are per thread-block and held in L2 cache
    // local scalar vars are per thread and held in registers
    __shared__ int64_t l2_stacks[threads_per_block][padded_n << 1];
    __shared__ int64_t l2_heaps[threads_per_block][padded_n];
    int64_t a, m, pos_k, avail, cnt;
    int top;
    // Nomenclature:
    //
    //     0 <= me <= n-2 is the left pos for m = 1
    //     0 <= me2 < 2*n is the left pos for m = 2, and me2r = me2 + 3 is the right pos
    //     0 <= me3 < 2*n is the left pos for m = 3, and me3r = me3 + 4 is the right pos
    //     0 <= me4 < 2*n is the left pos for m = 4, and me4r = me4 + 5 is the right pps
    //
    // By construction,
    //
    //     me3 = blockIdx.y,
    //     me4 = blockIdx.z,
    //     me and me2 are packed, in a special way, into (blockIdx.x, threadIdx.x)
    //
    const int tmp = blockIdx.x * threads_per_block + threadIdx.x;
    const int me = tmp / two_n;
    if (me < n_minus_1) {
        const int me2r = tmp - me * two_n + 3;
        const int me3r = blockIdx.y + 4;
        const int me4r = blockIdx.z + 5;
        if (me2r < two_n && me3r < two_n && me4r < two_n) {
            const int64_t a1 = (lsb << me) | (lsb << (me + 2));
            const int64_t a2 = (lsb << (me2r - 3)) | (lsb << (me2r));
            const int64_t a3 = (lsb << blockIdx.y) | (lsb << (me3r));
            const int64_t a4 = (lsb << blockIdx.z) | (lsb << (me4r));
            a = a1 | a2 | a3 | a4;
            // are a1, a2, a3, a4 pairwise disjoint?  that means we have valid placement for m=1,2,3,4
            if (a == (a1 + a2 + a3 + a4)) {
                // compute all positions where m = 5 can be placed, given that m=1,2,3,4 have been
                // placed already in the positions given by a1, a2, a3, a4 above
                avail = a ^ full;         // invert a;  note upper bits >= pos 2*n are all 1 (important
                avail &= (avail >> 6);    // for the correctness of these two lines as a block).
                // can our valid placement for m=1,2,3,4 be continued for m=5?
                if (avail) {
                    cnt = 0;
                    m = 5;
                    top = 0;
                    // record all possible continuations for m=4 into the stack and start DFS loop
                    auto& stack = l2_stacks[threadIdx.x];
                    auto& heap = l2_heaps[threadIdx.x];
                    stack[top++] = avail;
                    stack[top++] = m;
                    heap[m-1] = a;
                    while (top) {
                        m = stack[top - 1];
                        avail = stack[top - 2];
                        // extract the lowest bit that is set to 1 in avail
                        pos_k = avail & ~(avail - 1);
                        // clear that bit
                        avail ^= pos_k;
                        // "pop" that bit from the hybrid stack s
                        if (avail) {
                            stack[top - 2] = avail;
                        } else {
                            top -= 2;
                        }
                        // place m in that position
                        a  = heap[m-1] | pos_k | (pos_k << (m + 1));
                        ++m;
                        // the "avail" computed below has bit "k" set to 1 if and only if
                        // both of the positions "k" and "k + m + 1" in "a" contain 0
                        avail = a ^ full;
                        avail &= (avail >> (m + 1));
                        if (avail) {
                            if (m == n) {
                                // we've found another langford pairing, count it
                                ++cnt;
                            } else {
                                // push all possible ways to place m, to be explored in subsequent iterations
                                stack[top++] = avail;
                                stack[top++] = m;
                                heap[m-1] = a;
                            }
                        }
                    }
                    // Write this thread's result to off-chip memory.
                    const int blid = blockIdx.x + blocks_x * (blockIdx.y + blocks_y * blockIdx.z);
                    d_count[blid * threads_per_block + threadIdx.x] = cnt;
                }
            }
        }
    }
}

void cdo(const char* txt, hipError_t err) {
    if (err == hipSuccess) {
        return;
    }
    cout << "Failed to " << txt << " (Error code " << hipGetErrorString(err) << ")\n" << flush;
    exit(-1);
}

void run() {
    int64_t* count;
    int64_t* d_count;
    int64_t total;
    {
        cout << "\n";
        cout << "\n";
        cout << "------\n";
        cout << "Computing Langford number L(2,n) for n = " << n << ".\n";
        cout << "\n";
        cout << "GPU init " << flush;
    }
    auto t0 = steady_clock::now();
    auto seconds_since = [](decltype(t0) start) {
        return Seconds(steady_clock::now() - start);
    };
    hipEvent_t start, stop;
    cdo("create start timer event",
        hipEventCreate(&start));
    cdo("create stop timer event",
        hipEventCreateWithFlags(&stop, hipEventBlockingSync));
    cdo("allocate host memory",
        hipHostMalloc(&count, total_threads_padded * sizeof(*count), hipHostMallocDefault));
    for (int i=0; i<total_threads_padded; ++i) {
        count[i] = -1;
    }
    cdo("allocate GPU memory",
        hipMalloc(&d_count, total_threads_padded * sizeof(*count)));
    cdo("copy initial values from host to GPU",
        hipMemcpy(d_count, count, sizeof(*count) * total_threads_padded, hipMemcpyDeviceToHost));
    cdo("insert start event",
        hipEventRecord(start));
    {
        cout << "took " << seconds_since(t0) << " sec.\n";
        cout << "\n";
        cout << "Dispatching " << total_threads_padded << " threads (" << threads_per_block << " per block, "
             << blocks.x << " x " << blocks.y << " x " << blocks.z << " blocks).\n" << flush;
    }
    auto t1 = steady_clock::now();
    dfs<<<blocks, threads_per_block>>>(d_count);
    cdo("DFS kernel launch",
        hipPeekAtLastError());
    cdo("insert stop event",
        hipEventRecord(stop));
    {
        cout << "\n";
        cout << "GPU computation " << flush;
    }
    cdo("wait for GPU computation to complete",
        hipEventSynchronize(stop));
    float milliseconds = 0;
    cdo("compute GPU elapsed time",
        hipEventElapsedTime(&milliseconds, start, stop));
    {
        cout << "took " << milliseconds / 1000.0 << " sec on GPU clock, "
             << seconds_since(t1) << " sec on host clock.\n";
        cout << "\n";
        cout << "CPU reduction " << flush;
    }
    auto t2 = steady_clock::now();
    cdo("copy result from GPU to host",
        hipMemcpy(count, d_count, sizeof(*count) * total_threads_padded, hipMemcpyDeviceToHost));
    total = 0;
    for (int i=0; i<total_threads_padded; ++i) {
        if (count[i] >= 0) {
            total += count[i];
        }
    }
    {
        int64_t known_results[64];
        memset(&known_results[0], 0, sizeof(known_results));
        known_results[3]  = 1;
        known_results[4]  = 1;
        known_results[7]  = 26;
        known_results[8]  = 150;
        known_results[11] = 17792;
        known_results[12] = 108144;
        known_results[15] = 39809640ll;
        known_results[16] = 326721800ll;
        known_results[19] = 256814891280ll;
        known_results[20] = 2636337861200ll;
        known_results[23] = 3799455942515488ll;
        known_results[24] = 46845158056515936ll;
        // beyond 23, count does not fit in 64 bits and is not definitively known!
        cout << "took " << seconds_since(t2) << " sec.\n";
        cout << "\n";
        cout << "Result " << total << " for n = " << n << " " << flush;
        cout << ((total == known_results[n]) ? "matches" : "** DOES NOT MATCH **")
             << " previously known result.\n";
        cout << "------\n";
        cout << "\n";
        cout << "\n";
    }
    cdo("free GPU memory for result",
        hipFree(d_count));
    cdo("free host memory for result",
        hipHostFree(count));
}

int main(int argc, char** argv) {
    run();
    return 0;
}

	.text
	.file	"langford.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_ZlsRSoRK7Seconds               # -- Begin function _ZlsRSoRK7Seconds
	.type	_ZlsRSoRK7Seconds,@function
_ZlsRSoRK7Seconds:                      # @_ZlsRSoRK7Seconds
	.cfi_startproc
# %bb.0:
	movsd	(%rsi), %xmm0                   # xmm0 = mem[0],zero
	jmp	_ZNSo9_M_insertIdEERSoT_        # TAILCALL
.Lfunc_end0:
	.size	_ZlsRSoRK7Seconds, .Lfunc_end0-_ZlsRSoRK7Seconds
	.cfi_endproc
                                        # -- End function
	.globl	_Z18__device_stub__dfsPl        # -- Begin function _Z18__device_stub__dfsPl
	.type	_Z18__device_stub__dfsPl,@function
_Z18__device_stub__dfsPl:               # @_Z18__device_stub__dfsPl
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	movq	%rsp, %rbx
	movq	%rax, (%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z3dfsPl, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$80, %rsp
	.cfi_adjust_cfa_offset -80
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z18__device_stub__dfsPl, .Lfunc_end1-_Z18__device_stub__dfsPl
	.cfi_endproc
                                        # -- End function
	.globl	_Z3cdoPKc10hipError_t           # -- Begin function _Z3cdoPKc10hipError_t
	.type	_Z3cdoPKc10hipError_t,@function
_Z3cdoPKc10hipError_t:                  # @_Z3cdoPKc10hipError_t
	.cfi_startproc
# %bb.0:
	testl	%esi, %esi
	jne	.LBB2_2
# %bb.1:
	retq
.LBB2_2:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	pushq	%rax
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	movl	%esi, %ebx
	movq	%rdi, %r14
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	movq	%r14, %rsi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.1, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %r14
	movl	%ebx, %edi
	callq	hipGetErrorString
	movq	%r14, %rdi
	movq	%rax, %rsi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$.L.str.2, %esi
	movq	%rax, %rdi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	callq	_ZSt5flushIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
	movl	$-1, %edi
	callq	exit
.Lfunc_end2:
	.size	_Z3cdoPKc10hipError_t, .Lfunc_end2-_Z3cdoPKc10hipError_t
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z3runv
.LCPI3_0:
	.quad	0x41cdcd6500000000              # double 1.0E+9
.LCPI3_1:
	.quad	0x408f400000000000              # double 1000
	.text
	.globl	_Z3runv
	.type	_Z3runv,@function
_Z3runv:                                # @_Z3runv
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$40, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	$_ZSt4cout, %edi
	movl	$.L.str.3, %esi
	movl	$1, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	$.L.str.3, %esi
	movl	$1, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	$.L.str.4, %esi
	movl	$7, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	$.L.str.5, %esi
	movl	$41, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	$16, %esi
	callq	_ZNSolsEi
	movl	$.L.str.6, %esi
	movl	$2, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	$.L.str.3, %esi
	movl	$1, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	$.L.str.7, %esi
	movl	$9, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	callq	_ZNSo5flushEv
	callq	_ZNSt6chrono3_V212steady_clock3nowEv
	movq	%rax, %rbx
	leaq	24(%rsp), %r14
	movq	%r14, %rdi
	callq	hipEventCreate
	movl	$.L.str.8, %edi
	movl	%eax, %esi
	callq	_Z3cdoPKc10hipError_t
	movq	%rsp, %rdi
	movl	$1, %esi
	callq	hipEventCreateWithFlags
	movl	$.L.str.9, %edi
	movl	%eax, %esi
	callq	_Z3cdoPKc10hipError_t
	leaq	16(%rsp), %r15
	movl	$3932160, %esi                  # imm = 0x3C0000
	movq	%r15, %rdi
	xorl	%edx, %edx
	callq	hipHostMalloc
	movl	$.L.str.10, %edi
	movl	%eax, %esi
	callq	_Z3cdoPKc10hipError_t
	movq	(%r15), %rdi
	movl	$3932160, %edx                  # imm = 0x3C0000
	movl	$255, %esi
	callq	memset@PLT
	leaq	8(%rsp), %r12
	movl	$3932160, %esi                  # imm = 0x3C0000
	movq	%r12, %rdi
	callq	hipMalloc
	movl	$.L.str.11, %edi
	movl	%eax, %esi
	callq	_Z3cdoPKc10hipError_t
	movq	(%r12), %rdi
	movq	(%r15), %rsi
	movl	$3932160, %edx                  # imm = 0x3C0000
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$.L.str.12, %edi
	movl	%eax, %esi
	callq	_Z3cdoPKc10hipError_t
	movq	(%r14), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movl	$.L.str.13, %edi
	movl	%eax, %esi
	callq	_Z3cdoPKc10hipError_t
	movl	$_ZSt4cout, %edi
	movl	$.L.str.14, %esi
	movl	$5, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	callq	_ZNSt6chrono3_V212steady_clock3nowEv
	subq	%rbx, %rax
	cvtsi2sd	%rax, %xmm0
	divsd	.LCPI3_0(%rip), %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movl	$.L.str.15, %esi
	movl	$6, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	$.L.str.3, %esi
	movl	$1, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	$.L.str.16, %esi
	movl	$12, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	$491520, %esi                   # imm = 0x78000
	callq	_ZNSolsEi
	movq	%rax, %rbx
	movl	$.L.str.17, %esi
	movl	$10, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%rbx, %rdi
	movl	$16, %esi
	callq	_ZNSolsEi
	movq	%rax, %rbx
	movl	$.L.str.18, %esi
	movl	$12, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	blocks(%rip), %esi
	movq	%rbx, %rdi
	callq	_ZNSo9_M_insertImEERSoT_
	movq	%rax, %rbx
	movl	$.L.str.19, %esi
	movl	$3, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	blocks+4(%rip), %esi
	movq	%rbx, %rdi
	callq	_ZNSo9_M_insertImEERSoT_
	movq	%rax, %rbx
	movl	$.L.str.19, %esi
	movl	$3, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	blocks+8(%rip), %esi
	movq	%rbx, %rdi
	callq	_ZNSo9_M_insertImEERSoT_
	movq	%rax, %rbx
	movl	$.L.str.20, %esi
	movl	$10, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%rbx, %rdi
	callq	_ZNSo5flushEv
	callq	_ZNSt6chrono3_V212steady_clock3nowEv
	movq	%rax, %rbx
	movq	blocks(%rip), %rdi
	movl	blocks+8(%rip), %esi
	movabsq	$4294967312, %rdx               # imm = 0x100000010
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_2
# %bb.1:
	movq	8(%rsp), %rdi
	callq	_Z18__device_stub__dfsPl
.LBB3_2:
	callq	hipPeekAtLastError
	movl	$.L.str.21, %edi
	movl	%eax, %esi
	callq	_Z3cdoPKc10hipError_t
	movq	(%rsp), %rdi
	xorl	%r15d, %r15d
	xorl	%esi, %esi
	callq	hipEventRecord
	movl	$.L.str.22, %edi
	movl	%eax, %esi
	callq	_Z3cdoPKc10hipError_t
	movl	$_ZSt4cout, %edi
	movl	$.L.str.3, %esi
	movl	$1, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	$.L.str.23, %esi
	movl	$16, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	callq	_ZNSo5flushEv
	movq	(%rsp), %rdi
	callq	hipEventSynchronize
	movl	$.L.str.24, %edi
	movl	%eax, %esi
	callq	_Z3cdoPKc10hipError_t
	leaq	36(%rsp), %r14
	movl	$0, (%r14)
	movq	24(%rsp), %rsi
	movq	(%rsp), %rdx
	movq	%r14, %rdi
	callq	hipEventElapsedTime
	movl	$.L.str.25, %edi
	movl	%eax, %esi
	callq	_Z3cdoPKc10hipError_t
	movl	$_ZSt4cout, %edi
	movl	$.L.str.14, %esi
	movl	$5, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	cvtss2sd	(%r14), %xmm0
	divsd	.LCPI3_1(%rip), %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r14
	movl	$.L.str.26, %esi
	movl	$19, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	callq	_ZNSt6chrono3_V212steady_clock3nowEv
	subq	%rbx, %rax
	xorps	%xmm0, %xmm0
	cvtsi2sd	%rax, %xmm0
	divsd	.LCPI3_0(%rip), %xmm0
	movq	%r14, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movl	$.L.str.27, %esi
	movl	$20, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	$.L.str.3, %esi
	movl	$1, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	$.L.str.28, %esi
	movl	$14, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	callq	_ZNSo5flushEv
	callq	_ZNSt6chrono3_V212steady_clock3nowEv
	movq	%rax, %r14
	movq	16(%rsp), %rdi
	movq	8(%rsp), %rsi
	movl	$3932160, %edx                  # imm = 0x3C0000
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$.L.str.29, %edi
	movl	%eax, %esi
	callq	_Z3cdoPKc10hipError_t
	movq	16(%rsp), %rax
	xorl	%ecx, %ecx
	xorl	%ebx, %ebx
.LBB3_3:                                # =>This Inner Loop Header: Depth=1
	movq	(%rax,%rcx,8), %rdx
	testq	%rdx, %rdx
	cmovleq	%r15, %rdx
	addq	%rdx, %rbx
	incq	%rcx
	cmpq	$491520, %rcx                   # imm = 0x78000
	jne	.LBB3_3
# %bb.4:
	movl	$_ZSt4cout, %edi
	movl	$.L.str.14, %esi
	movl	$5, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	callq	_ZNSt6chrono3_V212steady_clock3nowEv
	subq	%r14, %rax
	xorps	%xmm0, %xmm0
	cvtsi2sd	%rax, %xmm0
	divsd	.LCPI3_0(%rip), %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movl	$.L.str.15, %esi
	movl	$6, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	$.L.str.3, %esi
	movl	$1, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$7, %r15d
	movl	$_ZSt4cout, %edi
	movl	$.L.str.30, %esi
	movl	$7, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movq	%rbx, %rsi
	callq	_ZNSo9_M_insertIlEERSoT_
	movq	%rax, %r14
	movl	$.L.str.31, %esi
	movl	$9, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r14, %rdi
	movl	$16, %esi
	callq	_ZNSolsEi
	movq	%rax, %r14
	movl	$.L.str.32, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r14, %rdi
	callq	_ZNSo5flushEv
	cmpq	$326721800, %rbx                # imm = 0x13796108
	movl	$.L.str.33, %eax
	movl	$.L.str.34, %esi
	cmoveq	%rax, %rsi
	movl	$20, %edx
	cmoveq	%r15, %rdx
	movl	$_ZSt4cout, %edi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	$.L.str.35, %esi
	movl	$26, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	$.L.str.4, %esi
	movl	$7, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	$.L.str.3, %esi
	movl	$1, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movl	$.L.str.3, %esi
	movl	$1, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	8(%rsp), %rdi
	callq	hipFree
	movl	$.L.str.36, %edi
	movl	%eax, %esi
	callq	_Z3cdoPKc10hipError_t
	movq	16(%rsp), %rdi
	callq	hipHostFree
	movl	$.L.str.37, %edi
	movl	%eax, %esi
	callq	_Z3cdoPKc10hipError_t
	addq	$40, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z3runv, .Lfunc_end3-_Z3runv
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	_Z3runv
	xorl	%eax, %eax
	popq	%rcx
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	main, .Lfunc_end4-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z3dfsPl, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	blocks,@object                  # @blocks
	.data
	.globl	blocks
	.p2align	3, 0x0
blocks:
	.long	30                              # 0x1e
	.long	32                              # 0x20
	.long	32                              # 0x20
	.size	blocks, 12

	.type	_Z3dfsPl,@object                # @_Z3dfsPl
	.section	.rodata,"a",@progbits
	.globl	_Z3dfsPl
	.p2align	3, 0x0
_Z3dfsPl:
	.quad	_Z18__device_stub__dfsPl
	.size	_Z3dfsPl, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Failed to "
	.size	.L.str, 11

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	" (Error code "
	.size	.L.str.1, 14

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	")\n"
	.size	.L.str.2, 3

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"\n"
	.size	.L.str.3, 2

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"------\n"
	.size	.L.str.4, 8

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"Computing Langford number L(2,n) for n = "
	.size	.L.str.5, 42

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	".\n"
	.size	.L.str.6, 3

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"GPU init "
	.size	.L.str.7, 10

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"create start timer event"
	.size	.L.str.8, 25

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"create stop timer event"
	.size	.L.str.9, 24

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"allocate host memory"
	.size	.L.str.10, 21

	.type	.L.str.11,@object               # @.str.11
.L.str.11:
	.asciz	"allocate GPU memory"
	.size	.L.str.11, 20

	.type	.L.str.12,@object               # @.str.12
.L.str.12:
	.asciz	"copy initial values from host to GPU"
	.size	.L.str.12, 37

	.type	.L.str.13,@object               # @.str.13
.L.str.13:
	.asciz	"insert start event"
	.size	.L.str.13, 19

	.type	.L.str.14,@object               # @.str.14
.L.str.14:
	.asciz	"took "
	.size	.L.str.14, 6

	.type	.L.str.15,@object               # @.str.15
.L.str.15:
	.asciz	" sec.\n"
	.size	.L.str.15, 7

	.type	.L.str.16,@object               # @.str.16
.L.str.16:
	.asciz	"Dispatching "
	.size	.L.str.16, 13

	.type	.L.str.17,@object               # @.str.17
.L.str.17:
	.asciz	" threads ("
	.size	.L.str.17, 11

	.type	.L.str.18,@object               # @.str.18
.L.str.18:
	.asciz	" per block, "
	.size	.L.str.18, 13

	.type	.L.str.19,@object               # @.str.19
.L.str.19:
	.asciz	" x "
	.size	.L.str.19, 4

	.type	.L.str.20,@object               # @.str.20
.L.str.20:
	.asciz	" blocks).\n"
	.size	.L.str.20, 11

	.type	.L.str.21,@object               # @.str.21
.L.str.21:
	.asciz	"DFS kernel launch"
	.size	.L.str.21, 18

	.type	.L.str.22,@object               # @.str.22
.L.str.22:
	.asciz	"insert stop event"
	.size	.L.str.22, 18

	.type	.L.str.23,@object               # @.str.23
.L.str.23:
	.asciz	"GPU computation "
	.size	.L.str.23, 17

	.type	.L.str.24,@object               # @.str.24
.L.str.24:
	.asciz	"wait for GPU computation to complete"
	.size	.L.str.24, 37

	.type	.L.str.25,@object               # @.str.25
.L.str.25:
	.asciz	"compute GPU elapsed time"
	.size	.L.str.25, 25

	.type	.L.str.26,@object               # @.str.26
.L.str.26:
	.asciz	" sec on GPU clock, "
	.size	.L.str.26, 20

	.type	.L.str.27,@object               # @.str.27
.L.str.27:
	.asciz	" sec on host clock.\n"
	.size	.L.str.27, 21

	.type	.L.str.28,@object               # @.str.28
.L.str.28:
	.asciz	"CPU reduction "
	.size	.L.str.28, 15

	.type	.L.str.29,@object               # @.str.29
.L.str.29:
	.asciz	"copy result from GPU to host"
	.size	.L.str.29, 29

	.type	.L.str.30,@object               # @.str.30
.L.str.30:
	.asciz	"Result "
	.size	.L.str.30, 8

	.type	.L.str.31,@object               # @.str.31
.L.str.31:
	.asciz	" for n = "
	.size	.L.str.31, 10

	.type	.L.str.32,@object               # @.str.32
.L.str.32:
	.asciz	" "
	.size	.L.str.32, 2

	.type	.L.str.33,@object               # @.str.33
.L.str.33:
	.asciz	"matches"
	.size	.L.str.33, 8

	.type	.L.str.34,@object               # @.str.34
.L.str.34:
	.asciz	"** DOES NOT MATCH **"
	.size	.L.str.34, 21

	.type	.L.str.35,@object               # @.str.35
.L.str.35:
	.asciz	" previously known result.\n"
	.size	.L.str.35, 27

	.type	.L.str.36,@object               # @.str.36
.L.str.36:
	.asciz	"free GPU memory for result"
	.size	.L.str.36, 27

	.type	.L.str.37,@object               # @.str.37
.L.str.37:
	.asciz	"free host memory for result"
	.size	.L.str.37, 28

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z3dfsPl"
	.size	.L__unnamed_1, 9

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z18__device_stub__dfsPl
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z3dfsPl
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z3dfsPl                ; -- Begin function _Z3dfsPl
	.globl	_Z3dfsPl
	.p2align	8
	.type	_Z3dfsPl,@function
_Z3dfsPl:                               ; @_Z3dfsPl
; %bb.0:
	v_lshl_add_u32 v1, s13, 4, v0
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e32 0x1e0, v1
	s_cbranch_execz .LBB0_15
; %bb.1:
	v_ashrrev_i32_e32 v2, 31, v1
	s_add_i32 s3, s14, 4
	s_add_i32 s2, s15, 5
	s_cmp_lt_i32 s3, 32
	s_cselect_b32 s4, -1, 0
	v_lshrrev_b32_e32 v2, 27, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, v1, v2
	v_and_b32_e32 v3, 0xffffffe0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v1, v1, v3
	v_cmp_gt_i32_e32 vcc_lo, 29, v1
	s_and_b32 s4, s4, vcc_lo
	s_cmp_lt_i32 s2, 32
	s_cselect_b32 s5, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s4, s5, s4
	s_and_b32 exec_lo, exec_lo, s4
	s_cbranch_execz .LBB0_15
; %bb.2:
	v_ashrrev_i32_e32 v3, 5, v2
	v_add_nc_u32_e32 v5, 3, v1
	v_lshlrev_b64 v[1:2], v1, 1
	s_lshl_b64 s[4:5], 1, s14
	s_lshl_b64 s[6:7], 1, s3
	v_add_nc_u32_e32 v7, 2, v3
	v_lshlrev_b64 v[3:4], v3, 1
	v_lshlrev_b64 v[5:6], v5, 1
	s_lshl_b64 s[8:9], 1, s15
	s_lshl_b64 s[2:3], 1, s2
	v_lshlrev_b64 v[7:8], v7, 1
	s_or_b64 s[4:5], s[6:7], s[4:5]
	s_or_b64 s[2:3], s[2:3], s[8:9]
	v_or_b32_e32 v2, v6, v2
	s_or_b64 s[6:7], s[2:3], s[4:5]
	s_add_u32 s2, s2, s4
	v_or_b32_e32 v3, v7, v3
	v_or_b32_e32 v4, v8, v4
	s_addc_u32 s3, s3, s5
	v_or_b32_e32 v1, v5, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v5, vcc_lo, s2, v3
	v_or3_b32 v8, s7, v4, v2
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_or3_b32 v7, s6, v3, v1
	v_add_co_u32 v1, vcc_lo, v5, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v2, vcc_lo, v4, v2, vcc_lo
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_15
; %bb.3:
	v_not_b32_e32 v1, v7
	v_mov_b32_e32 v2, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i64 v[3:4], 6, v[1:2]
	v_and_b32_e32 v1, v3, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v2, v4, v2
	v_cmp_ne_u64_e32 vcc_lo, 0, v[1:2]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_15
; %bb.4:
	v_mov_b32_e32 v5, 0
	v_dual_mov_b32 v4, 0 :: v_dual_lshlrev_b32 v9, 8, v0
	v_dual_mov_b32 v3, 5 :: v_dual_mov_b32 v6, 0
	v_dual_mov_b32 v10, 2 :: v_dual_lshlrev_b32 v11, 7, v0
	s_mov_b32 s2, 0
	ds_store_b128 v9, v[1:4]
	ds_store_b64 v11, v[7:8] offset:4128
.LBB0_5:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v9, -2, v10
	s_mov_b32 s3, exec_lo
	v_lshlrev_b32_e32 v1, 3, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v11, v0, 8, v1
	ds_load_2addr_b64 v[1:4], v11 offset1:1
	s_waitcnt lgkmcnt(0)
	v_sub_co_u32 v7, vcc_lo, 0, v1
	v_sub_co_ci_u32_e32 v8, vcc_lo, 0, v2, vcc_lo
	v_and_b32_e32 v7, v1, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v8, v2, v8
	v_xor_b32_e32 v1, v7, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v2, v8, v2
	v_cmpx_ne_u64_e32 0, v[1:2]
	s_cbranch_execz .LBB0_7
; %bb.6:                                ;   in Loop: Header=BB0_5 Depth=1
	v_mov_b32_e32 v9, v10
	ds_store_b64 v11, v[1:2]
.LBB0_7:                                ;   in Loop: Header=BB0_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	v_lshlrev_b32_e32 v1, 3, v3
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_lshl_add_u32 v10, v0, 7, v1
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v4, vcc_lo
	ds_load_b64 v[11:12], v10 offset:4088
	v_lshlrev_b64 v[13:14], v1, v[7:8]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or3_b32 v7, v13, v11, v7
	v_or3_b32 v8, v14, v12, v8
	v_add_nc_u32_e32 v11, 2, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_not_b32_e32 v3, v7
	v_mov_b32_e32 v4, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i64 v[11:12], v11, v[3:4]
	v_and_b32_e32 v4, v12, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v3, v11, v3
	v_cmpx_ne_u64_e32 0, v[3:4]
	s_cbranch_execz .LBB0_13
; %bb.8:                                ;   in Loop: Header=BB0_5 Depth=1
	s_mov_b32 s4, exec_lo
	v_cmpx_ne_u64_e32 16, v[1:2]
	s_xor_b32 s4, exec_lo, s4
	s_cbranch_execz .LBB0_10
; %bb.9:                                ;   in Loop: Header=BB0_5 Depth=1
	v_lshlrev_b32_e32 v11, 3, v9
	v_add_nc_u32_e32 v9, 2, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_lshl_add_u32 v11, v0, 8, v11
	ds_store_2addr_b64 v11, v[3:4], v[1:2] offset1:1
	ds_store_b64 v10, v[7:8] offset:4096
.LBB0_10:                               ; %Flow
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_and_not1_saveexec_b32 s4, s4
; %bb.11:                               ;   in Loop: Header=BB0_5 Depth=1
	v_add_co_u32 v5, vcc_lo, v5, 1
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
; %bb.12:                               ; %Flow94
                                        ;   in Loop: Header=BB0_5 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_13:                               ;   in Loop: Header=BB0_5 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_cmp_eq_u32_e32 vcc_lo, 0, v9
	v_mov_b32_e32 v10, v9
	s_or_b32 s2, vcc_lo, s2
	s_and_not1_b32 exec_lo, exec_lo, s2
	s_cbranch_execnz .LBB0_5
; %bb.14:
	s_or_b32 exec_lo, exec_lo, s2
	s_load_b64 s[0:1], s[0:1], 0x0
	s_lshl_b32 s2, s15, 5
	v_mov_b32_e32 v1, 0
	s_add_i32 s2, s2, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s2, s2, 30
	s_add_i32 s2, s2, s13
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v0, s2, 4, v0
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b64 v[0:1], v[5:6], off
.LBB0_15:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z3dfsPl
		.amdhsa_group_segment_fixed_size 6144
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 8
		.amdhsa_user_sgpr_count 13
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 1
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z3dfsPl, .Lfunc_end0-_Z3dfsPl
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 776
; NumSgprs: 18
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 6144 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 13
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
    .group_segment_fixed_size: 6144
    .kernarg_segment_align: 8
    .kernarg_segment_size: 8
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z3dfsPl
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z3dfsPl.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     15
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
