#include "includes.h"

//#define ITEM_COUNT 2
#define _PI 3.14159265358979323846
#define _PI2 1.57079632679489661923
#define _RAD 6372795





using namespace std;

cudaError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size);



__global__ void geo_invert(double2* d_dot1, double2* d_dot2, double* d_dist, double* d_azimut, long count)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < count)
{
d_dot1[idx].x = d_dot1[idx].x * _PI / 180;	//lat1
d_dot1[idx].y = d_dot1[idx].y * _PI / 180;	//lng1
d_dot2[idx].x = d_dot2[idx].x * _PI / 180;	//lat2
d_dot2[idx].y = d_dot2[idx].y * _PI / 180;	//lng2

double cl1, cl2, sl1, sl2, delta, cdelta, sdelta;
cl1 = cos(d_dot1[idx].x);
cl2 = cos(d_dot2[idx].x);
sl1 = sin(d_dot1[idx].x);
sl2 = sin(d_dot2[idx].x);
delta = d_dot2[idx].y - d_dot1[idx].y;
cdelta = cos(delta);
sdelta = sin(delta);

double x, y, z, ad, z2;
y = sqrt(pow(cl2*sdelta, 2) + pow(cl1*sl2 - sl1*cl2*cdelta, 2));
x = sl1*sl2 + cl1*cl2*cdelta;
ad = atan(y / x);
d_dist[idx] = ad * _RAD;

x = (cl1*sl2) - (sl1*cl2*cdelta);
y = sdelta*cl2;

if (x == 0)
{
if (y > 0)
z = -90;
else if (y < 0)
z = 90;
else if (y == 0)
z = 0;
}
else
{
z = atan(-y / x) * 180 / _PI;
if (x < 0)
{
z = z + 180;
}
}

z2 = z + 180.0f;

while (z2 >= 360)
{
z2 = z2 - 360;
}

z2 = z2 - 180;


z2 = -z2 * _PI / 180;
double anglerad2;
anglerad2 = z2 - ((2 * _PI) * floor(z2 / (2 * _PI)));
d_azimut[idx] = anglerad2 * 180 / _PI;


}
}
	.file	"tmpxft_00274383_00000000-6_geo_invert.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z46__device_stub__Z10geo_invertP7double2S0_PdS1_lP7double2S0_PdS1_l
	.type	_Z46__device_stub__Z10geo_invertP7double2S0_PdS1_lP7double2S0_PdS1_l, @function
_Z46__device_stub__Z10geo_invertP7double2S0_PdS1_lP7double2S0_PdS1_l:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	56(%rsp)
	.cfi_def_cfa_offset 184
	leaq	_Z10geo_invertP7double2S0_PdS1_l(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 192
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L2:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z46__device_stub__Z10geo_invertP7double2S0_PdS1_lP7double2S0_PdS1_l, .-_Z46__device_stub__Z10geo_invertP7double2S0_PdS1_lP7double2S0_PdS1_l
	.globl	_Z10geo_invertP7double2S0_PdS1_l
	.type	_Z10geo_invertP7double2S0_PdS1_l, @function
_Z10geo_invertP7double2S0_PdS1_l:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z46__device_stub__Z10geo_invertP7double2S0_PdS1_lP7double2S0_PdS1_l
	.cfi_endproc
.LFE2033:
	.size	_Z10geo_invertP7double2S0_PdS1_l, .-_Z10geo_invertP7double2S0_PdS1_l
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z10geo_invertP7double2S0_PdS1_l"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z10geo_invertP7double2S0_PdS1_l(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"

//#define ITEM_COUNT 2
#define _PI 3.14159265358979323846
#define _PI2 1.57079632679489661923
#define _RAD 6372795





using namespace std;

hipError_t addWithCuda(int *c, const int *a, const int *b, unsigned int size);



__global__ void geo_invert(double2* d_dot1, double2* d_dot2, double* d_dist, double* d_azimut, long count)
{
int idx = blockIdx.x * blockDim.x + threadIdx.x;
if (idx < count)
{
d_dot1[idx].x = d_dot1[idx].x * _PI / 180;	//lat1
d_dot1[idx].y = d_dot1[idx].y * _PI / 180;	//lng1
d_dot2[idx].x = d_dot2[idx].x * _PI / 180;	//lat2
d_dot2[idx].y = d_dot2[idx].y * _PI / 180;	//lng2

double cl1, cl2, sl1, sl2, delta, cdelta, sdelta;
cl1 = cos(d_dot1[idx].x);
cl2 = cos(d_dot2[idx].x);
sl1 = sin(d_dot1[idx].x);
sl2 = sin(d_dot2[idx].x);
delta = d_dot2[idx].y - d_dot1[idx].y;
cdelta = cos(delta);
sdelta = sin(delta);

double x, y, z, ad, z2;
y = sqrt(pow(cl2*sdelta, 2) + pow(cl1*sl2 - sl1*cl2*cdelta, 2));
x = sl1*sl2 + cl1*cl2*cdelta;
ad = atan(y / x);
d_dist[idx] = ad * _RAD;

x = (cl1*sl2) - (sl1*cl2*cdelta);
y = sdelta*cl2;

if (x == 0)
{
if (y > 0)
z = -90;
else if (y < 0)
z = 90;
else if (y == 0)
z = 0;
}
else
{
z = atan(-y / x) * 180 / _PI;
if (x < 0)
{
z = z + 180;
}
}

z2 = z + 180.0f;

while (z2 >= 360)
{
z2 = z2 - 360;
}

z2 = z2 - 180;


z2 = -z2 * _PI / 180;
double anglerad2;
anglerad2 = z2 - ((2 * _PI) * floor(z2 / (2 * _PI)));
d_azimut[idx] = anglerad2 * 180 / _PI;


}
}
	.text
	.file	"geo_invert.hip"
	.globl	_Z25__device_stub__geo_invertP15HIP_vector_typeIdLj2EES1_PdS2_l # -- Begin function _Z25__device_stub__geo_invertP15HIP_vector_typeIdLj2EES1_PdS2_l
	.type	_Z25__device_stub__geo_invertP15HIP_vector_typeIdLj2EES1_PdS2_l,@function
_Z25__device_stub__geo_invertP15HIP_vector_typeIdLj2EES1_PdS2_l: # @_Z25__device_stub__geo_invertP15HIP_vector_typeIdLj2EES1_PdS2_l
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10geo_invertP15HIP_vector_typeIdLj2EES1_PdS2_l, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z25__device_stub__geo_invertP15HIP_vector_typeIdLj2EES1_PdS2_l, .Lfunc_end0-_Z25__device_stub__geo_invertP15HIP_vector_typeIdLj2EES1_PdS2_l
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10geo_invertP15HIP_vector_typeIdLj2EES1_PdS2_l, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z10geo_invertP15HIP_vector_typeIdLj2EES1_PdS2_l,@object # @_Z10geo_invertP15HIP_vector_typeIdLj2EES1_PdS2_l
	.section	.rodata,"a",@progbits
	.globl	_Z10geo_invertP15HIP_vector_typeIdLj2EES1_PdS2_l
	.p2align	3, 0x0
_Z10geo_invertP15HIP_vector_typeIdLj2EES1_PdS2_l:
	.quad	_Z25__device_stub__geo_invertP15HIP_vector_typeIdLj2EES1_PdS2_l
	.size	_Z10geo_invertP15HIP_vector_typeIdLj2EES1_PdS2_l, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z10geo_invertP15HIP_vector_typeIdLj2EES1_PdS2_l"
	.size	.L__unnamed_1, 49

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub__geo_invertP15HIP_vector_typeIdLj2EES1_PdS2_l
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z10geo_invertP15HIP_vector_typeIdLj2EES1_PdS2_l
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z10geo_invertP15HIP_vector_typeIdLj2EES1_PdS2_l ; -- Begin function _Z10geo_invertP15HIP_vector_typeIdLj2EES1_PdS2_l
	.globl	_Z10geo_invertP15HIP_vector_typeIdLj2EES1_PdS2_l
	.p2align	8
	.type	_Z10geo_invertP15HIP_vector_typeIdLj2EES1_PdS2_l,@function
_Z10geo_invertP15HIP_vector_typeIdLj2EES1_PdS2_l: ; @_Z10geo_invertP15HIP_vector_typeIdLj2EES1_PdS2_l
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x34
	s_load_b64 s[2:3], s[0:1], 0x20
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, s15, s4, v[0:1]
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[4:5]
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB0_40
; %bb.1:
	s_load_b256 s[4:11], s[0:1], 0x0
	v_lshlrev_b64 v[6:7], 4, v[4:5]
	s_mov_b32 s3, 0x400921fb
	s_mov_b32 s2, 0x54442d18
                                        ; implicit-def: $vgpr40
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v20, vcc_lo, s4, v6
	v_add_co_ci_u32_e32 v21, vcc_lo, s5, v7, vcc_lo
	global_load_b128 v[0:3], v[20:21], off
	s_waitcnt vmcnt(0)
	v_mul_f64 v[0:1], v[0:1], s[2:3]
	v_mul_f64 v[2:3], v[2:3], s[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[8:9], null, 0x40668000, 0x40668000, v[0:1]
	v_div_scale_f64 v[10:11], null, 0x40668000, 0x40668000, v[2:3]
	v_div_scale_f64 v[22:23], vcc_lo, v[0:1], 0x40668000, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[12:13], v[8:9]
	v_rcp_f64_e32 v[14:15], v[10:11]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
	v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
	v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
	v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
	v_div_scale_f64 v[16:17], s0, v[2:3], 0x40668000, v[2:3]
	v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[18:19], v[22:23], v[12:13]
	v_mul_f64 v[24:25], v[16:17], v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[8:9], -v[8:9], v[18:19], v[22:23]
	v_fma_f64 v[10:11], -v[10:11], v[24:25], v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[18:19]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[24:25]
	v_add_co_u32 v6, vcc_lo, s6, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_fixup_f64 v[0:1], v[8:9], 0x40668000, v[0:1]
	v_div_fixup_f64 v[2:3], v[10:11], 0x40668000, v[2:3]
	global_store_b128 v[20:21], v[0:3], off
	global_load_b128 v[0:3], v[6:7], off
	s_waitcnt vmcnt(0)
	v_mul_f64 v[0:1], v[0:1], s[2:3]
	v_mul_f64 v[2:3], v[2:3], s[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[8:9], null, 0x40668000, 0x40668000, v[0:1]
	v_div_scale_f64 v[10:11], null, 0x40668000, 0x40668000, v[2:3]
	v_div_scale_f64 v[22:23], vcc_lo, v[0:1], 0x40668000, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[12:13], v[8:9]
	v_rcp_f64_e32 v[14:15], v[10:11]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
	v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
	v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[16:17], -v[8:9], v[12:13], 1.0
	v_fma_f64 v[18:19], -v[10:11], v[14:15], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[12:13], v[12:13], v[16:17], v[12:13]
	v_div_scale_f64 v[16:17], s0, v[2:3], 0x40668000, v[2:3]
	v_fma_f64 v[14:15], v[14:15], v[18:19], v[14:15]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[18:19], v[22:23], v[12:13]
	v_mul_f64 v[24:25], v[16:17], v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[8:9], -v[8:9], v[18:19], v[22:23]
	v_fma_f64 v[10:11], -v[10:11], v[24:25], v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[8:9], v[8:9], v[12:13], v[18:19]
	s_mov_b32 vcc_lo, s0
	v_div_fmas_f64 v[10:11], v[10:11], v[14:15], v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f64 v[0:1], v[8:9], 0x40668000, v[0:1]
	v_div_fixup_f64 v[2:3], v[10:11], 0x40668000, v[2:3]
                                        ; implicit-def: $vgpr10_vgpr11
	global_store_b128 v[6:7], v[0:3], off
	global_load_b64 v[8:9], v[20:21], off
                                        ; implicit-def: $vgpr6_vgpr7
	s_waitcnt vmcnt(0)
	v_cmp_ngt_f64_e64 s1, 0x41d00000, |v[8:9]|
	v_trig_preop_f64 v[30:31], |v[8:9]|, 0
	v_trig_preop_f64 v[24:25], |v[8:9]|, 1
	v_ldexp_f64 v[34:35], |v[8:9]|, 0xffffff80
	v_trig_preop_f64 v[22:23], |v[8:9]|, 2
	v_and_b32_e32 v38, 0x7fffffff, v9
	s_and_saveexec_b32 s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s4, exec_lo, s0
	s_cbranch_execz .LBB0_3
; %bb.2:
	v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[8:9]|
	v_mov_b32_e32 v41, 0
	s_mov_b32 s3, 0x3ff921fb
	s_mov_b32 s6, 0x33145c07
	s_mov_b32 s7, 0x3c91a626
	v_dual_cndmask_b32 v7, v38, v35 :: v_dual_cndmask_b32 v6, v8, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f64 v[10:11], v[30:31], v[6:7]
	v_mul_f64 v[12:13], v[24:25], v[6:7]
	v_mul_f64 v[32:33], v[22:23], v[6:7]
	v_fma_f64 v[14:15], v[30:31], v[6:7], -v[10:11]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[36:37], v[24:25], v[6:7], -v[12:13]
	v_fma_f64 v[6:7], v[22:23], v[6:7], -v[32:33]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[12:13], v[14:15]
	v_add_f64 v[18:19], v[16:17], -v[12:13]
	v_add_f64 v[28:29], v[10:11], v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[26:27], v[16:17], -v[18:19]
	v_add_f64 v[14:15], v[14:15], -v[18:19]
	v_ldexp_f64 v[18:19], v[28:29], -2
	v_add_f64 v[10:11], v[28:29], -v[10:11]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[12:13], v[12:13], -v[26:27]
	v_add_f64 v[26:27], v[32:33], v[36:37]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[18:19]|
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[10:11], v[16:17], -v[10:11]
	v_add_f64 v[12:13], v[14:15], v[12:13]
	v_fract_f64_e32 v[14:15], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[26:27], v[12:13]
	v_dual_cndmask_b32 v15, 0, v15 :: v_dual_cndmask_b32 v14, 0, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ldexp_f64 v[14:15], v[14:15], 2
	v_add_f64 v[18:19], v[10:11], v[16:17]
	v_add_f64 v[39:40], v[16:17], -v[26:27]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[28:29], v[18:19], v[14:15]
	v_add_f64 v[46:47], v[16:17], -v[39:40]
	v_add_f64 v[12:13], v[12:13], -v[39:40]
	v_add_f64 v[10:11], v[18:19], -v[10:11]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_gt_f64_e32 vcc_lo, 0, v[28:29]
	v_add_f64 v[28:29], v[26:27], -v[32:33]
	v_add_f64 v[10:11], v[16:17], -v[10:11]
	v_cndmask_b32_e64 v42, 0, 0x40100000, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_f64 v[44:45], v[26:27], -v[28:29]
	v_add_f64 v[28:29], v[36:37], -v[28:29]
	v_add_f64 v[26:27], v[26:27], -v[46:47]
	v_add_f64 v[14:15], v[14:15], v[41:42]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[36:37], v[32:33], -v[44:45]
	v_add_f64 v[12:13], v[12:13], v[26:27]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[42:43], v[18:19], v[14:15]
	v_add_f64 v[28:29], v[28:29], v[36:37]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f64_e32 v42, v[42:43]
	v_add_f64 v[12:13], v[28:29], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_i32_e32 v[39:40], v42
	v_add_f64 v[6:7], v[6:7], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[14:15], v[14:15], -v[39:40]
	v_add_f64 v[6:7], v[10:11], v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[26:27], v[18:19], v[14:15]
	v_add_f64 v[12:13], v[26:27], -v[14:15]
	v_cmp_le_f64_e32 vcc_lo, 0.5, v[26:27]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f64 v[10:11], v[18:19], -v[12:13]
	v_add_co_ci_u32_e64 v40, s0, 0, v42, vcc_lo
	v_cndmask_b32_e64 v42, 0, 0x3ff00000, vcc_lo
	v_add_f64 v[6:7], v[6:7], v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[10:11], v[26:27], -v[41:42]
	v_add_f64 v[12:13], v[10:11], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f64 v[14:15], v[12:13], s[2:3]
	v_add_f64 v[10:11], v[12:13], -v[10:11]
	v_fma_f64 v[16:17], v[12:13], s[2:3], -v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], v[6:7], -v[10:11]
	v_fma_f64 v[10:11], v[12:13], s[6:7], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[6:7], s[2:3], v[10:11]
	v_add_f64 v[6:7], v[14:15], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[12:13], v[6:7], -v[14:15]
	v_add_f64 v[10:11], v[10:11], -v[12:13]
.LBB0_3:                                ; %Flow133
	s_and_not1_saveexec_b32 s0, s4
	s_cbranch_execz .LBB0_5
; %bb.4:
	s_mov_b32 s2, 0x6dc9c883
	s_mov_b32 s3, 0x3fe45f30
	s_mov_b32 s5, 0xbc91a626
	v_mul_f64 v[6:7], |v[8:9]|, s[2:3]
	s_mov_b32 s2, 0x54442d18
	s_mov_b32 s3, 0xbff921fb
	s_mov_b32 s4, 0x33145c00
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[12:13], v[6:7]
	v_fma_f64 v[6:7], v[12:13], s[2:3], |v[8:9]|
	v_mul_f64 v[10:11], v[12:13], s[4:5]
	s_mov_b32 s2, 0x252049c0
	s_mov_b32 s3, 0xb97b839a
	v_cvt_i32_f64_e32 v40, v[12:13]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[16:17], v[12:13], s[4:5], v[6:7]
	v_add_f64 v[14:15], v[6:7], v[10:11]
	s_mov_b32 s5, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[6:7], v[6:7], -v[14:15]
	v_add_f64 v[14:15], v[14:15], -v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], v[6:7], v[10:11]
	v_fma_f64 v[10:11], v[12:13], s[4:5], v[10:11]
	v_add_f64 v[6:7], v[14:15], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[6:7], -v[10:11]
	v_fma_f64 v[10:11], v[12:13], s[2:3], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[6:7], v[16:17], v[10:11]
	v_add_f64 v[14:15], v[6:7], -v[16:17]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[10:11], v[10:11], -v[14:15]
.LBB0_5:                                ; %_ZL3cosd.exit
	s_or_b32 exec_lo, exec_lo, s0
	v_cmp_ngt_f64_e64 s2, 0x41d00000, |v[0:1]|
	v_trig_preop_f64 v[32:33], |v[0:1]|, 0
	v_trig_preop_f64 v[28:29], |v[0:1]|, 1
	v_ldexp_f64 v[36:37], |v[0:1]|, 0xffffff80
	v_trig_preop_f64 v[26:27], |v[0:1]|, 2
	v_and_b32_e32 v39, 0x7fffffff, v1
                                        ; implicit-def: $vgpr41
                                        ; implicit-def: $vgpr12_vgpr13
                                        ; implicit-def: $vgpr14_vgpr15
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s0
	s_cbranch_execz .LBB0_7
; %bb.6:
	v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[0:1]|
	v_mov_b32_e32 v53, 0
	s_mov_b32 s4, 0x54442d18
	s_mov_b32 s5, 0x3ff921fb
	s_mov_b32 s6, 0x33145c07
	s_mov_b32 s7, 0x3c91a626
	v_dual_cndmask_b32 v13, v39, v37 :: v_dual_cndmask_b32 v12, v0, v36
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f64 v[14:15], v[32:33], v[12:13]
	v_mul_f64 v[16:17], v[28:29], v[12:13]
	v_mul_f64 v[49:50], v[26:27], v[12:13]
	v_fma_f64 v[18:19], v[32:33], v[12:13], -v[14:15]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[51:52], v[28:29], v[12:13], -v[16:17]
	v_fma_f64 v[12:13], v[26:27], v[12:13], -v[49:50]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[41:42], v[16:17], v[18:19]
	v_add_f64 v[43:44], v[41:42], -v[16:17]
	v_add_f64 v[47:48], v[14:15], v[41:42]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[45:46], v[41:42], -v[43:44]
	v_add_f64 v[18:19], v[18:19], -v[43:44]
	v_ldexp_f64 v[43:44], v[47:48], -2
	v_add_f64 v[14:15], v[47:48], -v[14:15]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[16:17], v[16:17], -v[45:46]
	v_add_f64 v[45:46], v[49:50], v[51:52]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[43:44]|
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[14:15], v[41:42], -v[14:15]
	v_add_f64 v[16:17], v[18:19], v[16:17]
	v_fract_f64_e32 v[18:19], v[43:44]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[41:42], v[45:46], v[16:17]
	v_dual_cndmask_b32 v19, 0, v19 :: v_dual_cndmask_b32 v18, 0, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ldexp_f64 v[18:19], v[18:19], 2
	v_add_f64 v[43:44], v[14:15], v[41:42]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[47:48], v[43:44], v[18:19]
	v_add_f64 v[14:15], v[43:44], -v[14:15]
	v_cmp_gt_f64_e32 vcc_lo, 0, v[47:48]
	v_add_f64 v[47:48], v[45:46], -v[49:50]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[14:15], v[41:42], -v[14:15]
	v_cndmask_b32_e64 v54, 0, 0x40100000, vcc_lo
	v_add_f64 v[58:59], v[45:46], -v[47:48]
	v_add_f64 v[47:48], v[51:52], -v[47:48]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[18:19], v[18:19], v[53:54]
	v_add_f64 v[54:55], v[41:42], -v[45:46]
	v_add_f64 v[51:52], v[49:50], -v[58:59]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[56:57], v[43:44], v[18:19]
	v_add_f64 v[60:61], v[41:42], -v[54:55]
	v_add_f64 v[16:17], v[16:17], -v[54:55]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[47:48], v[47:48], v[51:52]
	v_cvt_i32_f64_e32 v56, v[56:57]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[45:46], v[45:46], -v[60:61]
	v_cvt_f64_i32_e32 v[54:55], v56
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[16:17], v[45:46]
	v_add_f64 v[18:19], v[18:19], -v[54:55]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[47:48], v[16:17]
	v_add_f64 v[45:46], v[43:44], v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[12:13], v[12:13], v[16:17]
	v_add_f64 v[16:17], v[45:46], -v[18:19]
	v_cmp_le_f64_e32 vcc_lo, 0.5, v[45:46]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[12:13], v[14:15], v[12:13]
	v_add_f64 v[14:15], v[43:44], -v[16:17]
	v_cndmask_b32_e64 v54, 0, 0x3ff00000, vcc_lo
	v_add_co_ci_u32_e64 v41, s0, 0, v56, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[12:13], v[12:13], v[14:15]
	v_add_f64 v[14:15], v[45:46], -v[53:54]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[14:15], v[12:13]
	v_mul_f64 v[18:19], v[16:17], s[4:5]
	v_add_f64 v[14:15], v[16:17], -v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[42:43], v[16:17], s[4:5], -v[18:19]
	v_add_f64 v[12:13], v[12:13], -v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[16:17], s[6:7], v[42:43]
	v_fma_f64 v[14:15], v[12:13], s[4:5], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[12:13], v[18:19], v[14:15]
	v_add_f64 v[16:17], v[12:13], -v[18:19]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[14:15], v[14:15], -v[16:17]
.LBB0_7:                                ; %Flow132
	s_and_not1_saveexec_b32 s0, s3
	s_cbranch_execz .LBB0_9
; %bb.8:
	s_mov_b32 s4, 0x6dc9c883
	s_mov_b32 s5, 0x3fe45f30
	s_mov_b32 s7, 0xbc91a626
	v_mul_f64 v[12:13], |v[0:1]|, s[4:5]
	s_mov_b32 s4, 0x54442d18
	s_mov_b32 s5, 0xbff921fb
	s_mov_b32 s6, 0x33145c00
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[16:17], v[12:13]
	v_fma_f64 v[12:13], v[16:17], s[4:5], |v[0:1]|
	v_mul_f64 v[14:15], v[16:17], s[6:7]
	s_mov_b32 s4, 0x252049c0
	s_mov_b32 s5, 0xb97b839a
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[41:42], v[16:17], s[6:7], v[12:13]
	v_add_f64 v[18:19], v[12:13], v[14:15]
	s_mov_b32 s7, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[12:13], v[12:13], -v[18:19]
	v_add_f64 v[18:19], v[18:19], -v[41:42]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[12:13], v[12:13], v[14:15]
	v_fma_f64 v[14:15], v[16:17], s[6:7], v[14:15]
	v_add_f64 v[12:13], v[18:19], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[12:13], v[12:13], -v[14:15]
	v_fma_f64 v[14:15], v[16:17], s[4:5], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[12:13], v[41:42], v[14:15]
	v_add_f64 v[18:19], v[12:13], -v[41:42]
	v_cvt_i32_f64_e32 v41, v[16:17]
	s_delay_alu instid0(VALU_DEP_2)
	v_add_f64 v[14:15], v[14:15], -v[18:19]
.LBB0_9:                                ; %_ZL3cosd.exit85
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr43
                                        ; implicit-def: $vgpr16_vgpr17
                                        ; implicit-def: $vgpr18_vgpr19
	s_and_saveexec_b32 s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s1, exec_lo, s0
	s_cbranch_execz .LBB0_11
; %bb.10:
	v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[8:9]|
	v_mov_b32_e32 v52, 0
	s_mov_b32 s4, 0x54442d18
	s_mov_b32 s5, 0x3ff921fb
	s_mov_b32 s6, 0x33145c07
	s_mov_b32 s7, 0x3c91a626
	v_dual_cndmask_b32 v17, v38, v35 :: v_dual_cndmask_b32 v16, v8, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f64 v[18:19], v[30:31], v[16:17]
	v_mul_f64 v[34:35], v[24:25], v[16:17]
	v_mul_f64 v[50:51], v[22:23], v[16:17]
	v_fma_f64 v[30:31], v[30:31], v[16:17], -v[18:19]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[24:25], v[24:25], v[16:17], -v[34:35]
	v_fma_f64 v[16:17], v[22:23], v[16:17], -v[50:51]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[42:43], v[34:35], v[30:31]
	v_add_f64 v[44:45], v[42:43], -v[34:35]
	v_add_f64 v[48:49], v[18:19], v[42:43]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[46:47], v[42:43], -v[44:45]
	v_add_f64 v[30:31], v[30:31], -v[44:45]
	v_ldexp_f64 v[44:45], v[48:49], -2
	v_add_f64 v[18:19], v[48:49], -v[18:19]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[34:35], v[34:35], -v[46:47]
	v_add_f64 v[46:47], v[50:51], v[24:25]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[44:45]|
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[18:19], v[42:43], -v[18:19]
	v_add_f64 v[30:31], v[30:31], v[34:35]
	v_fract_f64_e32 v[34:35], v[44:45]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[42:43], v[46:47], v[30:31]
	v_dual_cndmask_b32 v35, 0, v35 :: v_dual_cndmask_b32 v34, 0, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ldexp_f64 v[34:35], v[34:35], 2
	v_add_f64 v[44:45], v[18:19], v[42:43]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[48:49], v[44:45], v[34:35]
	v_add_f64 v[18:19], v[44:45], -v[18:19]
	v_cmp_gt_f64_e32 vcc_lo, 0, v[48:49]
	v_add_f64 v[48:49], v[46:47], -v[50:51]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[18:19], v[42:43], -v[18:19]
	v_cndmask_b32_e64 v53, 0, 0x40100000, vcc_lo
	v_add_f64 v[57:58], v[46:47], -v[48:49]
	v_add_f64 v[24:25], v[24:25], -v[48:49]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[34:35], v[34:35], v[52:53]
	v_add_f64 v[53:54], v[42:43], -v[46:47]
	v_add_f64 v[48:49], v[50:51], -v[57:58]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[55:56], v[44:45], v[34:35]
	v_add_f64 v[59:60], v[42:43], -v[53:54]
	v_add_f64 v[30:31], v[30:31], -v[53:54]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[24:25], v[24:25], v[48:49]
	v_cvt_i32_f64_e32 v38, v[55:56]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[46:47], v[46:47], -v[59:60]
	v_cvt_f64_i32_e32 v[53:54], v38
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[30:31], v[30:31], v[46:47]
	v_add_f64 v[34:35], v[34:35], -v[53:54]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[22:23], v[24:25], v[30:31]
	v_add_f64 v[24:25], v[44:45], v[34:35]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[16:17], v[22:23]
	v_add_f64 v[22:23], v[24:25], -v[34:35]
	v_cmp_le_f64_e32 vcc_lo, 0.5, v[24:25]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[16:17], v[18:19], v[16:17]
	v_add_f64 v[18:19], v[44:45], -v[22:23]
	v_cndmask_b32_e64 v53, 0, 0x3ff00000, vcc_lo
	v_add_co_ci_u32_e64 v43, s0, 0, v38, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[16:17], v[16:17], v[18:19]
	v_add_f64 v[18:19], v[24:25], -v[52:53]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[22:23], v[18:19], v[16:17]
	v_mul_f64 v[24:25], v[22:23], s[4:5]
	v_add_f64 v[18:19], v[22:23], -v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[30:31], v[22:23], s[4:5], -v[24:25]
	v_add_f64 v[16:17], v[16:17], -v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], v[22:23], s[6:7], v[30:31]
	v_fma_f64 v[18:19], v[16:17], s[4:5], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[24:25], v[18:19]
	v_add_f64 v[22:23], v[16:17], -v[24:25]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[18:19], v[18:19], -v[22:23]
.LBB0_11:                               ; %Flow131
	s_and_not1_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_13
; %bb.12:
	s_mov_b32 s4, 0x6dc9c883
	s_mov_b32 s5, 0x3fe45f30
	s_mov_b32 s7, 0xbc91a626
	v_mul_f64 v[16:17], |v[8:9]|, s[4:5]
	s_mov_b32 s4, 0x54442d18
	s_mov_b32 s5, 0xbff921fb
	s_mov_b32 s6, 0x33145c00
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[22:23], v[16:17]
	v_fma_f64 v[16:17], v[22:23], s[4:5], |v[8:9]|
	v_mul_f64 v[18:19], v[22:23], s[6:7]
	s_mov_b32 s4, 0x252049c0
	s_mov_b32 s5, 0xb97b839a
	v_cvt_i32_f64_e32 v43, v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[30:31], v[22:23], s[6:7], v[16:17]
	v_add_f64 v[24:25], v[16:17], v[18:19]
	s_mov_b32 s7, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[16:17], v[16:17], -v[24:25]
	v_add_f64 v[24:25], v[24:25], -v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[16:17], v[18:19]
	v_fma_f64 v[18:19], v[22:23], s[6:7], v[18:19]
	v_add_f64 v[16:17], v[24:25], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[16:17], -v[18:19]
	v_fma_f64 v[18:19], v[22:23], s[4:5], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[30:31], v[18:19]
	v_add_f64 v[24:25], v[16:17], -v[30:31]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[18:19], v[18:19], -v[24:25]
.LBB0_13:                               ; %_ZL3sind.exit
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr42
                                        ; implicit-def: $vgpr22_vgpr23
                                        ; implicit-def: $vgpr24_vgpr25
	s_and_saveexec_b32 s0, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s1, exec_lo, s0
	s_cbranch_execz .LBB0_15
; %bb.14:
	v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[0:1]|
	v_mov_b32_e32 v48, 0
	s_mov_b32 s2, 0x54442d18
	s_mov_b32 s3, 0x3ff921fb
	s_mov_b32 s4, 0x33145c07
	s_mov_b32 s5, 0x3c91a626
	v_dual_cndmask_b32 v23, v39, v37 :: v_dual_cndmask_b32 v22, v0, v36
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f64 v[24:25], v[32:33], v[22:23]
	v_mul_f64 v[30:31], v[28:29], v[22:23]
	v_mul_f64 v[46:47], v[26:27], v[22:23]
	v_fma_f64 v[32:33], v[32:33], v[22:23], -v[24:25]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[28:29], v[28:29], v[22:23], -v[30:31]
	v_fma_f64 v[22:23], v[26:27], v[22:23], -v[46:47]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[34:35], v[30:31], v[32:33]
	v_add_f64 v[36:37], v[34:35], -v[30:31]
	v_add_f64 v[44:45], v[24:25], v[34:35]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[38:39], v[34:35], -v[36:37]
	v_add_f64 v[32:33], v[32:33], -v[36:37]
	v_ldexp_f64 v[36:37], v[44:45], -2
	v_add_f64 v[24:25], v[44:45], -v[24:25]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[30:31], v[30:31], -v[38:39]
	v_add_f64 v[38:39], v[46:47], v[28:29]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[36:37]|
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[24:25], v[34:35], -v[24:25]
	v_add_f64 v[30:31], v[32:33], v[30:31]
	v_fract_f64_e32 v[32:33], v[36:37]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[34:35], v[38:39], v[30:31]
	v_dual_cndmask_b32 v33, 0, v33 :: v_dual_cndmask_b32 v32, 0, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ldexp_f64 v[32:33], v[32:33], 2
	v_add_f64 v[36:37], v[24:25], v[34:35]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[44:45], v[36:37], v[32:33]
	v_add_f64 v[24:25], v[36:37], -v[24:25]
	v_cmp_gt_f64_e32 vcc_lo, 0, v[44:45]
	v_add_f64 v[44:45], v[38:39], -v[46:47]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[24:25], v[34:35], -v[24:25]
	v_cndmask_b32_e64 v49, 0, 0x40100000, vcc_lo
	v_add_f64 v[53:54], v[38:39], -v[44:45]
	v_add_f64 v[28:29], v[28:29], -v[44:45]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[32:33], v[32:33], v[48:49]
	v_add_f64 v[49:50], v[34:35], -v[38:39]
	v_add_f64 v[44:45], v[46:47], -v[53:54]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[51:52], v[36:37], v[32:33]
	v_add_f64 v[55:56], v[34:35], -v[49:50]
	v_add_f64 v[30:31], v[30:31], -v[49:50]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[28:29], v[28:29], v[44:45]
	v_cvt_i32_f64_e32 v42, v[51:52]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[38:39], v[38:39], -v[55:56]
	v_cvt_f64_i32_e32 v[49:50], v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[30:31], v[30:31], v[38:39]
	v_add_f64 v[32:33], v[32:33], -v[49:50]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[26:27], v[28:29], v[30:31]
	v_add_f64 v[28:29], v[36:37], v[32:33]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[22:23], v[22:23], v[26:27]
	v_add_f64 v[26:27], v[28:29], -v[32:33]
	v_cmp_le_f64_e32 vcc_lo, 0.5, v[28:29]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[22:23], v[24:25], v[22:23]
	v_add_f64 v[24:25], v[36:37], -v[26:27]
	v_cndmask_b32_e64 v49, 0, 0x3ff00000, vcc_lo
	v_add_co_ci_u32_e64 v42, s0, 0, v42, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[22:23], v[22:23], v[24:25]
	v_add_f64 v[24:25], v[28:29], -v[48:49]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[26:27], v[24:25], v[22:23]
	v_mul_f64 v[28:29], v[26:27], s[2:3]
	v_add_f64 v[24:25], v[26:27], -v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[30:31], v[26:27], s[2:3], -v[28:29]
	v_add_f64 v[22:23], v[22:23], -v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[24:25], v[26:27], s[4:5], v[30:31]
	v_fma_f64 v[24:25], v[22:23], s[2:3], v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[22:23], v[28:29], v[24:25]
	v_add_f64 v[26:27], v[22:23], -v[28:29]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[24:25], v[24:25], -v[26:27]
.LBB0_15:                               ; %Flow129
	s_and_not1_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_17
; %bb.16:
	s_mov_b32 s2, 0x6dc9c883
	s_mov_b32 s3, 0x3fe45f30
	s_mov_b32 s5, 0xbc91a626
	v_mul_f64 v[22:23], |v[0:1]|, s[2:3]
	s_mov_b32 s2, 0x54442d18
	s_mov_b32 s3, 0xbff921fb
	s_mov_b32 s4, 0x33145c00
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[26:27], v[22:23]
	v_fma_f64 v[22:23], v[26:27], s[2:3], |v[0:1]|
	v_mul_f64 v[24:25], v[26:27], s[4:5]
	s_mov_b32 s2, 0x252049c0
	s_mov_b32 s3, 0xb97b839a
	v_cvt_i32_f64_e32 v42, v[26:27]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[30:31], v[26:27], s[4:5], v[22:23]
	v_add_f64 v[28:29], v[22:23], v[24:25]
	s_mov_b32 s5, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[22:23], v[22:23], -v[28:29]
	v_add_f64 v[28:29], v[28:29], -v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[22:23], v[22:23], v[24:25]
	v_fma_f64 v[24:25], v[26:27], s[4:5], v[24:25]
	v_add_f64 v[22:23], v[28:29], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[22:23], v[22:23], -v[24:25]
	v_fma_f64 v[24:25], v[26:27], s[2:3], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[22:23], v[30:31], v[24:25]
	v_add_f64 v[28:29], v[22:23], -v[30:31]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[24:25], v[24:25], -v[28:29]
.LBB0_17:                               ; %_ZL3sind.exit94
	s_or_b32 exec_lo, exec_lo, s0
	global_load_b64 v[20:21], v[20:21], off offset:8
                                        ; implicit-def: $vgpr44
                                        ; implicit-def: $vgpr26_vgpr27
                                        ; implicit-def: $vgpr28_vgpr29
	s_waitcnt vmcnt(0)
	v_add_f64 v[2:3], v[2:3], -v[20:21]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ngt_f64_e64 s1, 0x41d00000, |v[2:3]|
	v_trig_preop_f64 v[36:37], |v[2:3]|, 0
	v_trig_preop_f64 v[34:35], |v[2:3]|, 1
	v_ldexp_f64 v[38:39], |v[2:3]|, 0xffffff80
	v_trig_preop_f64 v[32:33], |v[2:3]|, 2
	v_and_b32_e32 v46, 0x7fffffff, v3
	s_and_saveexec_b32 s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s2, exec_lo, s0
	s_cbranch_execz .LBB0_19
; %bb.18:
	v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[2:3]|
	v_mov_b32_e32 v57, 0
	s_mov_b32 s4, 0x54442d18
	s_mov_b32 s5, 0x3ff921fb
	s_mov_b32 s6, 0x33145c07
	s_mov_b32 s7, 0x3c91a626
	v_cndmask_b32_e32 v21, v46, v39, vcc_lo
	v_cndmask_b32_e32 v20, v2, v38, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f64 v[26:27], v[36:37], v[20:21]
	v_mul_f64 v[28:29], v[34:35], v[20:21]
	v_fma_f64 v[30:31], v[36:37], v[20:21], -v[26:27]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[55:56], v[34:35], v[20:21], -v[28:29]
	v_add_f64 v[44:45], v[28:29], v[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[47:48], v[44:45], -v[28:29]
	v_add_f64 v[51:52], v[26:27], v[44:45]
	v_add_f64 v[49:50], v[44:45], -v[47:48]
	v_add_f64 v[30:31], v[30:31], -v[47:48]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_ldexp_f64 v[47:48], v[51:52], -2
	v_add_f64 v[26:27], v[51:52], -v[26:27]
	v_add_f64 v[28:29], v[28:29], -v[49:50]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[47:48]|
	v_add_f64 v[26:27], v[44:45], -v[26:27]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[28:29], v[30:31], v[28:29]
	v_fract_f64_e32 v[30:31], v[47:48]
	v_dual_cndmask_b32 v31, 0, v31 :: v_dual_cndmask_b32 v30, 0, v30
	v_mul_f64 v[53:54], v[32:33], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[30:31], v[30:31], 2
	v_add_f64 v[49:50], v[53:54], v[55:56]
	v_fma_f64 v[20:21], v[32:33], v[20:21], -v[53:54]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[44:45], v[49:50], v[28:29]
	v_add_f64 v[47:48], v[26:27], v[44:45]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[51:52], v[47:48], v[30:31]
	v_add_f64 v[26:27], v[47:48], -v[26:27]
	v_cmp_gt_f64_e32 vcc_lo, 0, v[51:52]
	v_add_f64 v[51:52], v[49:50], -v[53:54]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[26:27], v[44:45], -v[26:27]
	v_cndmask_b32_e64 v58, 0, 0x40100000, vcc_lo
	v_add_f64 v[62:63], v[49:50], -v[51:52]
	v_add_f64 v[51:52], v[55:56], -v[51:52]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[30:31], v[30:31], v[57:58]
	v_add_f64 v[58:59], v[44:45], -v[49:50]
	v_add_f64 v[55:56], v[53:54], -v[62:63]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[60:61], v[47:48], v[30:31]
	v_add_f64 v[64:65], v[44:45], -v[58:59]
	v_add_f64 v[28:29], v[28:29], -v[58:59]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[51:52], v[51:52], v[55:56]
	v_cvt_i32_f64_e32 v60, v[60:61]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[49:50], v[49:50], -v[64:65]
	v_cvt_f64_i32_e32 v[58:59], v60
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[28:29], v[28:29], v[49:50]
	v_add_f64 v[30:31], v[30:31], -v[58:59]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[28:29], v[51:52], v[28:29]
	v_add_f64 v[49:50], v[47:48], v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[20:21], v[28:29]
	v_add_f64 v[28:29], v[49:50], -v[30:31]
	v_cmp_le_f64_e32 vcc_lo, 0.5, v[49:50]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[20:21], v[26:27], v[20:21]
	v_add_f64 v[26:27], v[47:48], -v[28:29]
	v_cndmask_b32_e64 v58, 0, 0x3ff00000, vcc_lo
	v_add_co_ci_u32_e64 v44, s0, 0, v60, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[20:21], v[20:21], v[26:27]
	v_add_f64 v[26:27], v[49:50], -v[57:58]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[28:29], v[26:27], v[20:21]
	v_mul_f64 v[30:31], v[28:29], s[4:5]
	v_add_f64 v[26:27], v[28:29], -v[26:27]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[47:48], v[28:29], s[4:5], -v[30:31]
	v_add_f64 v[20:21], v[20:21], -v[26:27]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[26:27], v[28:29], s[6:7], v[47:48]
	v_fma_f64 v[20:21], v[20:21], s[4:5], v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[26:27], v[30:31], v[20:21]
	v_add_f64 v[28:29], v[26:27], -v[30:31]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[28:29], v[20:21], -v[28:29]
.LBB0_19:                               ; %Flow127
	s_and_not1_saveexec_b32 s0, s2
	s_cbranch_execz .LBB0_21
; %bb.20:
	s_mov_b32 s2, 0x6dc9c883
	s_mov_b32 s3, 0x3fe45f30
	s_mov_b32 s5, 0xbc91a626
	v_mul_f64 v[20:21], |v[2:3]|, s[2:3]
	s_mov_b32 s2, 0x54442d18
	s_mov_b32 s3, 0xbff921fb
	s_mov_b32 s4, 0x33145c00
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[20:21], v[20:21]
	v_fma_f64 v[26:27], v[20:21], s[2:3], |v[2:3]|
	v_mul_f64 v[28:29], v[20:21], s[4:5]
	s_mov_b32 s2, 0x252049c0
	s_mov_b32 s3, 0xb97b839a
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[44:45], v[20:21], s[4:5], v[26:27]
	v_add_f64 v[30:31], v[26:27], v[28:29]
	s_mov_b32 s5, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[26:27], v[26:27], -v[30:31]
	v_add_f64 v[30:31], v[30:31], -v[44:45]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[26:27], v[26:27], v[28:29]
	v_fma_f64 v[28:29], v[20:21], s[4:5], v[28:29]
	v_add_f64 v[26:27], v[30:31], v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[26:27], v[26:27], -v[28:29]
	v_fma_f64 v[28:29], v[20:21], s[2:3], v[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[26:27], v[44:45], v[28:29]
	v_add_f64 v[30:31], v[26:27], -v[44:45]
	v_cvt_i32_f64_e32 v44, v[20:21]
	s_delay_alu instid0(VALU_DEP_2)
	v_add_f64 v[28:29], v[28:29], -v[30:31]
.LBB0_21:                               ; %_ZL3cosd.exit99
	s_or_b32 exec_lo, exec_lo, s0
                                        ; implicit-def: $vgpr45
                                        ; implicit-def: $vgpr20_vgpr21
                                        ; implicit-def: $vgpr30_vgpr31
	s_and_saveexec_b32 s0, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s1, exec_lo, s0
	s_cbranch_execz .LBB0_23
; %bb.22:
	v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[2:3]|
	v_mov_b32_e32 v55, 0
	s_mov_b32 s2, 0x54442d18
	s_mov_b32 s3, 0x3ff921fb
	s_mov_b32 s4, 0x33145c07
	s_mov_b32 s5, 0x3c91a626
	v_cndmask_b32_e32 v21, v46, v39, vcc_lo
	v_cndmask_b32_e32 v20, v2, v38, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f64 v[30:31], v[36:37], v[20:21]
	v_mul_f64 v[38:39], v[34:35], v[20:21]
	v_fma_f64 v[36:37], v[36:37], v[20:21], -v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[34:35], v[34:35], v[20:21], -v[38:39]
	v_add_f64 v[45:46], v[38:39], v[36:37]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[47:48], v[45:46], -v[38:39]
	v_add_f64 v[51:52], v[30:31], v[45:46]
	v_add_f64 v[49:50], v[45:46], -v[47:48]
	v_add_f64 v[36:37], v[36:37], -v[47:48]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_ldexp_f64 v[47:48], v[51:52], -2
	v_add_f64 v[30:31], v[51:52], -v[30:31]
	v_add_f64 v[38:39], v[38:39], -v[49:50]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[47:48]|
	v_add_f64 v[30:31], v[45:46], -v[30:31]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[36:37], v[36:37], v[38:39]
	v_fract_f64_e32 v[38:39], v[47:48]
	v_dual_cndmask_b32 v39, 0, v39 :: v_dual_cndmask_b32 v38, 0, v38
	v_mul_f64 v[53:54], v[32:33], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[38:39], v[38:39], 2
	v_add_f64 v[49:50], v[53:54], v[34:35]
	v_fma_f64 v[20:21], v[32:33], v[20:21], -v[53:54]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[45:46], v[49:50], v[36:37]
	v_add_f64 v[47:48], v[30:31], v[45:46]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[51:52], v[47:48], v[38:39]
	v_add_f64 v[30:31], v[47:48], -v[30:31]
	v_cmp_gt_f64_e32 vcc_lo, 0, v[51:52]
	v_add_f64 v[51:52], v[49:50], -v[53:54]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[30:31], v[45:46], -v[30:31]
	v_cndmask_b32_e64 v56, 0, 0x40100000, vcc_lo
	v_add_f64 v[60:61], v[49:50], -v[51:52]
	v_add_f64 v[34:35], v[34:35], -v[51:52]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[38:39], v[38:39], v[55:56]
	v_add_f64 v[56:57], v[45:46], -v[49:50]
	v_add_f64 v[51:52], v[53:54], -v[60:61]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[58:59], v[47:48], v[38:39]
	v_add_f64 v[62:63], v[45:46], -v[56:57]
	v_add_f64 v[36:37], v[36:37], -v[56:57]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[34:35], v[34:35], v[51:52]
	v_cvt_i32_f64_e32 v58, v[58:59]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[49:50], v[49:50], -v[62:63]
	v_cvt_f64_i32_e32 v[56:57], v58
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[36:37], v[36:37], v[49:50]
	v_add_f64 v[38:39], v[38:39], -v[56:57]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[32:33], v[34:35], v[36:37]
	v_add_f64 v[34:35], v[47:48], v[38:39]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[20:21], v[32:33]
	v_add_f64 v[32:33], v[34:35], -v[38:39]
	v_cmp_le_f64_e32 vcc_lo, 0.5, v[34:35]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[20:21], v[30:31], v[20:21]
	v_add_f64 v[30:31], v[47:48], -v[32:33]
	v_cndmask_b32_e64 v56, 0, 0x3ff00000, vcc_lo
	v_add_co_ci_u32_e64 v45, s0, 0, v58, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[20:21], v[20:21], v[30:31]
	v_add_f64 v[30:31], v[34:35], -v[55:56]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[32:33], v[30:31], v[20:21]
	v_mul_f64 v[34:35], v[32:33], s[2:3]
	v_add_f64 v[30:31], v[32:33], -v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[36:37], v[32:33], s[2:3], -v[34:35]
	v_add_f64 v[20:21], v[20:21], -v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[30:31], v[32:33], s[4:5], v[36:37]
	v_fma_f64 v[30:31], v[20:21], s[2:3], v[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[34:35], v[30:31]
	v_add_f64 v[32:33], v[20:21], -v[34:35]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[30:31], v[30:31], -v[32:33]
.LBB0_23:                               ; %Flow126
	s_and_not1_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_25
; %bb.24:
	s_mov_b32 s2, 0x6dc9c883
	s_mov_b32 s3, 0x3fe45f30
	s_mov_b32 s5, 0xbc91a626
	v_mul_f64 v[20:21], |v[2:3]|, s[2:3]
	s_mov_b32 s2, 0x54442d18
	s_mov_b32 s3, 0xbff921fb
	s_mov_b32 s4, 0x33145c00
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[32:33], v[20:21]
	v_fma_f64 v[20:21], v[32:33], s[2:3], |v[2:3]|
	v_mul_f64 v[30:31], v[32:33], s[4:5]
	s_mov_b32 s2, 0x252049c0
	s_mov_b32 s3, 0xb97b839a
	v_cvt_i32_f64_e32 v45, v[32:33]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[36:37], v[32:33], s[4:5], v[20:21]
	v_add_f64 v[34:35], v[20:21], v[30:31]
	s_mov_b32 s5, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[20:21], v[20:21], -v[34:35]
	v_add_f64 v[34:35], v[34:35], -v[36:37]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[20:21], v[20:21], v[30:31]
	v_fma_f64 v[30:31], v[32:33], s[4:5], v[30:31]
	v_add_f64 v[20:21], v[34:35], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[20:21], -v[30:31]
	v_fma_f64 v[30:31], v[32:33], s[2:3], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[36:37], v[30:31]
	v_add_f64 v[34:35], v[20:21], -v[36:37]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[30:31], v[30:31], -v[34:35]
.LBB0_25:                               ; %_ZL3sind.exit104
	s_or_b32 exec_lo, exec_lo, s0
	v_mul_f64 v[34:35], v[22:23], v[22:23]
	s_mov_b32 s0, 0x9037ab78
	s_mov_b32 s2, 0x46cc5e42
	s_mov_b32 s18, 0xb42fdfa7
	s_mov_b32 s22, 0xf9a43bb8
	s_mov_b32 s1, 0x3e21eeb6
	s_mov_b32 s3, 0xbda907db
	s_mov_b32 s19, 0xbe5ae600
	s_mov_b32 s23, 0x3de5e0b2
	v_mul_f64 v[38:39], v[16:17], v[16:17]
	s_mov_b32 s12, 0xa17f65f6
	s_mov_b32 s20, 0x796cde01
	s_mov_b32 s13, 0xbe927e4f
	s_mov_b32 s21, 0x3ec71de3
	s_mov_b32 s14, 0x19f4ec90
	s_mov_b32 s24, 0x19e83e5c
	s_mov_b32 s15, 0x3efa01a0
	s_mov_b32 s25, 0xbf2a01a0
	v_mul_f64 v[60:61], v[26:27], v[26:27]
	s_mov_b32 s16, 0x16c16967
	s_mov_b32 s17, 0xbf56c16c
	s_mov_b32 s5, 0x3f811111
	s_mov_b32 s4, 0x11110bb3
	v_mul_f64 v[62:63], v[12:13], v[12:13]
	v_mul_f64 v[64:65], v[24:25], 0.5
	v_mul_f64 v[74:75], v[6:7], v[6:7]
	s_mov_b32 s7, 0x3fa55555
	s_mov_b32 s6, 0x55555555
	v_mul_f64 v[66:67], v[20:21], v[20:21]
	v_mul_f64 v[80:81], v[18:19], 0.5
	v_cmp_class_f64_e64 vcc_lo, v[8:9], 0x1f8
	v_lshlrev_b32_e32 v8, 30, v41
	s_mov_b32 s26, 0x6ef28734
	s_mov_b32 s27, 0x3fa82d5d
	s_mov_b32 s28, 0x6a214619
	s_mov_b32 s29, 0xbfaae5ce
	v_and_b32_e32 v8, 0x80000000, v8
	s_mov_b32 s30, 0x8427b883
	v_fma_f64 v[32:33], v[34:35], s[2:3], s[0:1]
	v_mul_f64 v[36:37], v[34:35], 0.5
	v_fma_f64 v[46:47], v[34:35], s[22:23], s[18:19]
	v_mul_f64 v[68:69], v[22:23], -v[34:35]
	v_mul_f64 v[78:79], v[34:35], v[34:35]
	s_mov_b32 s31, 0x3fae1bb4
	s_mov_b32 s34, 0x8b207f05
	s_mov_b32 s35, 0xbfb110e4
	s_mov_b32 s36, 0x57b87036
	v_fma_f64 v[50:51], v[38:39], s[2:3], s[0:1]
	v_mul_f64 v[52:53], v[38:39], 0.5
	v_fma_f64 v[54:55], v[38:39], s[22:23], s[18:19]
	s_mov_b32 s37, 0x3fb3b136
	s_mov_b32 s38, 0x19378e4f
	s_mov_b32 s39, 0xbfb745d1
	s_mov_b32 s40, 0x17e1913c
	s_mov_b32 s41, 0x3fbc71c7
	s_mov_b32 s42, 0x92376b7d
	v_fma_f64 v[72:73], v[60:61], s[22:23], s[18:19]
	v_mul_f64 v[70:71], v[60:61], 0.5
	s_mov_b32 s43, 0xbfc24924
	s_mov_b32 s44, 0x999952cc
	s_mov_b32 s45, 0x3fc99999
	v_fma_f64 v[76:77], v[62:63], s[22:23], s[18:19]
	v_mul_f64 v[82:83], v[62:63], 0.5
	v_fma_f64 v[86:87], v[74:75], s[22:23], s[18:19]
	s_mov_b32 s46, 0x55555523
	s_mov_b32 s47, 0xbfd55555
	v_mul_f64 v[84:85], v[66:67], 0.5
	v_fma_f64 v[88:89], v[66:67], s[22:23], s[18:19]
	s_mov_b32 s19, 0xbfc55555
	s_mov_b32 s18, s6
	s_mov_b32 s22, 0x5711927a
	s_mov_b32 s23, 0x3fa2c15b
	s_mov_b32 s48, 0xeeb562d6
	s_mov_b32 s50, 0x336a0500
	s_mov_b32 s49, 0x3ffaf154
	s_mov_b32 s51, 0x3fedd9ad
	v_fma_f64 v[32:33], v[34:35], v[32:33], s[12:13]
	v_add_f64 v[48:49], -v[36:37], 1.0
	v_fma_f64 v[46:47], v[34:35], v[46:47], s[20:21]
	s_mov_b32 s52, -2.0
	s_mov_b32 s53, 0x41584f6e
	v_fma_f64 v[50:51], v[38:39], v[50:51], s[12:13]
	v_add_f64 v[58:59], -v[52:53], 1.0
	v_fma_f64 v[54:55], v[38:39], v[54:55], s[20:21]
	v_fma_f64 v[72:73], v[60:61], v[72:73], s[20:21]
	v_fma_f64 v[76:77], v[62:63], v[76:77], s[20:21]
	v_add_f64 v[90:91], -v[82:83], 1.0
	v_fma_f64 v[32:33], v[34:35], v[32:33], s[14:15]
	v_add_f64 v[56:57], -v[48:49], 1.0
	v_fma_f64 v[46:47], v[34:35], v[46:47], s[24:25]
	v_fma_f64 v[50:51], v[38:39], v[50:51], s[14:15]
	v_fma_f64 v[54:55], v[38:39], v[54:55], s[24:25]
	v_fma_f64 v[76:77], v[62:63], v[76:77], s[24:25]
	v_fma_f64 v[32:33], v[34:35], v[32:33], s[16:17]
	v_add_f64 v[36:37], v[56:57], -v[36:37]
	v_add_f64 v[56:57], -v[58:59], 1.0
	v_fma_f64 v[46:47], v[34:35], v[46:47], s[4:5]
	v_fma_f64 v[50:51], v[38:39], v[50:51], s[16:17]
	v_fma_f64 v[54:55], v[38:39], v[54:55], s[4:5]
	v_fma_f64 v[76:77], v[62:63], v[76:77], s[4:5]
	v_fma_f64 v[32:33], v[34:35], v[32:33], s[6:7]
	v_fma_f64 v[36:37], v[22:23], -v[24:25], v[36:37]
	v_add_f64 v[52:53], v[56:57], -v[52:53]
	v_mul_f64 v[56:57], v[16:17], -v[38:39]
	v_fma_f64 v[46:47], v[68:69], v[46:47], v[64:65]
	v_add_f64 v[64:65], -v[70:71], 1.0
	v_fma_f64 v[50:51], v[38:39], v[50:51], s[6:7]
	v_fma_f64 v[36:37], v[78:79], v[32:33], v[36:37]
	v_mul_f64 v[78:79], v[38:39], v[38:39]
	v_fma_f64 v[52:53], v[16:17], -v[18:19], v[52:53]
	v_fma_f64 v[54:55], v[56:57], v[54:55], v[80:81]
	v_fma_f64 v[24:25], v[34:35], v[46:47], -v[24:25]
	v_fma_f64 v[46:47], v[60:61], v[72:73], s[24:25]
	v_fma_f64 v[72:73], v[74:75], v[86:87], s[20:21]
	v_add_f64 v[32:33], -v[84:85], 1.0
	v_add_f64 v[34:35], -v[64:65], 1.0
	v_fma_f64 v[80:81], v[66:67], v[88:89], s[20:21]
	v_mul_f64 v[86:87], v[28:29], 0.5
	s_mov_b32 s20, 0xfc27006a
	s_mov_b32 s21, 0xbf9e9ae6
	v_add_f64 v[36:37], v[48:49], v[36:37]
	v_fma_f64 v[50:51], v[78:79], v[50:51], v[52:53]
	v_add_f64 v[78:79], -v[90:91], 1.0
	v_fma_f64 v[18:19], v[38:39], v[54:55], -v[18:19]
	v_mul_f64 v[38:39], v[26:27], -v[60:61]
	v_fma_f64 v[46:47], v[60:61], v[46:47], s[4:5]
	v_fma_f64 v[72:73], v[74:75], v[72:73], s[24:25]
	v_mul_f64 v[52:53], v[14:15], 0.5
	v_add_f64 v[54:55], -v[32:33], 1.0
	v_add_f64 v[34:35], v[34:35], -v[70:71]
	v_mul_f64 v[70:71], v[12:13], -v[62:63]
	v_fma_f64 v[80:81], v[66:67], v[80:81], s[24:25]
	v_fma_f64 v[24:25], v[68:69], s[18:19], v[24:25]
	v_fma_f64 v[68:69], v[74:75], s[2:3], s[0:1]
	s_mov_b32 s24, 0xe82d3ff0
	s_mov_b32 s25, 0xbfa59976
	v_add_f64 v[78:79], v[78:79], -v[82:83]
	v_mul_f64 v[82:83], v[10:11], 0.5
	v_fma_f64 v[18:19], v[56:57], s[18:19], v[18:19]
	v_fma_f64 v[46:47], v[38:39], v[46:47], v[86:87]
	v_mul_f64 v[86:87], v[6:7], -v[74:75]
	v_fma_f64 v[72:73], v[74:75], v[72:73], s[4:5]
	v_add_f64 v[54:55], v[54:55], -v[84:85]
	v_mul_f64 v[84:85], v[30:31], 0.5
	v_fma_f64 v[52:53], v[70:71], v[76:77], v[52:53]
	v_mul_f64 v[76:77], v[20:21], -v[66:67]
	v_fma_f64 v[80:81], v[66:67], v[80:81], s[4:5]
	v_fma_f64 v[34:35], v[26:27], -v[28:29], v[34:35]
	v_fma_f64 v[68:69], v[74:75], v[68:69], s[12:13]
	v_add_f64 v[22:23], v[22:23], -v[24:25]
	v_add_f64 v[24:25], v[58:59], v[50:51]
	v_fma_f64 v[78:79], v[12:13], -v[14:15], v[78:79]
	v_add_f64 v[16:17], v[16:17], -v[18:19]
	v_fma_f64 v[28:29], v[60:61], v[46:47], -v[28:29]
	v_fma_f64 v[46:47], v[66:67], s[2:3], s[0:1]
	v_fma_f64 v[72:73], v[86:87], v[72:73], v[82:83]
	v_fma_f64 v[82:83], v[62:63], s[2:3], s[0:1]
	v_mul_f64 v[18:19], v[66:67], v[66:67]
	v_fma_f64 v[14:15], v[62:63], v[52:53], -v[14:15]
	v_mul_f64 v[52:53], v[74:75], 0.5
	v_fma_f64 v[80:81], v[76:77], v[80:81], v[84:85]
	v_fma_f64 v[84:85], v[60:61], s[2:3], s[0:1]
	v_fma_f64 v[68:69], v[74:75], v[68:69], s[14:15]
	v_cmp_class_f64_e64 s0, v[0:1], 0x1f8
	v_lshlrev_b32_e32 v0, 30, v43
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v0, v0, v9
	v_and_b32_e32 v0, 0x80000000, v0
	v_fma_f64 v[28:29], v[38:39], s[18:19], v[28:29]
	v_fma_f64 v[46:47], v[66:67], v[46:47], s[12:13]
	v_fma_f64 v[48:49], v[74:75], v[72:73], -v[10:11]
	v_fma_f64 v[82:83], v[62:63], v[82:83], s[12:13]
	v_fma_f64 v[14:15], v[70:71], s[18:19], v[14:15]
	v_add_f64 v[56:57], -v[52:53], 1.0
	v_fma_f64 v[84:85], v[60:61], v[84:85], s[12:13]
	v_fma_f64 v[68:69], v[74:75], v[68:69], s[16:17]
	s_mov_b32 s12, 0x968915a9
	s_mov_b32 s13, 0x3fba6564
	v_add_f64 v[26:27], v[26:27], -v[28:29]
	v_fma_f64 v[46:47], v[66:67], v[46:47], s[14:15]
	v_fma_f64 v[28:29], v[86:87], s[18:19], v[48:49]
	v_fma_f64 v[82:83], v[62:63], v[82:83], s[14:15]
	v_add_f64 v[12:13], v[12:13], -v[14:15]
	v_add_f64 v[70:71], -v[56:57], 1.0
	v_mul_f64 v[14:15], v[74:75], v[74:75]
	v_fma_f64 v[84:85], v[60:61], v[84:85], s[14:15]
	v_fma_f64 v[50:51], v[74:75], v[68:69], s[6:7]
	s_mov_b32 s14, 0x4222de17
	s_mov_b32 s15, 0x3fbdee67
	v_fma_f64 v[46:47], v[66:67], v[46:47], s[16:17]
	v_fma_f64 v[82:83], v[62:63], v[82:83], s[16:17]
	v_xor_b32_e32 v9, 0x80000000, v13
	v_add_f64 v[52:53], v[70:71], -v[52:53]
	v_fma_f64 v[84:85], v[60:61], v[84:85], s[16:17]
	s_mov_b32 s16, 0xa57d9582
	s_mov_b32 s17, 0xbf8c6ea4
	v_fma_f64 v[38:39], v[66:67], v[46:47], s[6:7]
	v_fma_f64 v[46:47], v[20:21], -v[30:31], v[54:55]
	v_fma_f64 v[82:83], v[62:63], v[82:83], s[6:7]
	v_mul_f64 v[62:63], v[62:63], v[62:63]
	v_fma_f64 v[30:31], v[66:67], v[80:81], -v[30:31]
	v_fma_f64 v[10:11], v[6:7], -v[10:11], v[52:53]
	v_and_b32_e32 v55, 1, v43
	v_fma_f64 v[84:85], v[60:61], v[84:85], s[6:7]
	v_mul_f64 v[60:61], v[60:61], v[60:61]
	v_add_f64 v[6:7], v[6:7], -v[28:29]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s2, 0, v55
	v_cndmask_b32_e64 v17, v25, v17, s2
	v_cndmask_b32_e64 v16, v24, v16, s2
	v_cmp_class_f64_e64 s2, v[2:3], 0x1f8
	v_and_b32_e32 v24, 1, v44
	v_lshlrev_b32_e32 v2, 30, v44
	s_delay_alu instid0(VALU_DEP_1)
	v_and_b32_e32 v2, 0x80000000, v2
	v_fma_f64 v[18:19], v[18:19], v[38:39], v[46:47]
	v_fma_f64 v[62:63], v[62:63], v[82:83], v[78:79]
	v_fma_f64 v[30:31], v[76:77], s[18:19], v[30:31]
	v_fma_f64 v[13:14], v[14:15], v[50:51], v[10:11]
	v_xor_b32_e32 v11, v17, v0
	v_and_b32_e32 v54, 1, v42
	v_fma_f64 v[34:35], v[60:61], v[84:85], v[34:35]
	s_mov_b32 s18, 0x5f08b19f
	s_mov_b32 s19, 0x3f967e29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s1, 0, v54
	v_cndmask_b32_e64 v22, v36, v22, s1
	v_and_b32_e32 v36, 1, v41
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v0, 0, v22, s0
	v_cmp_eq_u32_e64 s3, 0, v36
	v_add_f64 v[17:18], v[32:33], v[18:19]
	v_add_f64 v[52:53], v[90:91], v[62:63]
	v_add_f64 v[19:20], v[20:21], -v[30:31]
	v_add_f64 v[21:22], v[56:57], v[13:14]
	v_lshlrev_b32_e32 v14, 30, v45
	v_add_f64 v[34:35], v[64:65], v[34:35]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v3, v14, v3
	v_and_b32_e32 v14, 1, v40
	v_cmp_eq_u32_e64 s4, 0, v14
	v_cndmask_b32_e64 v9, v9, v53, s3
	v_cndmask_b32_e64 v10, v12, v52, s3
	v_cmp_eq_u32_e64 s3, 0, v24
	v_xor_b32_e32 v24, 0x80000000, v27
	v_cndmask_b32_e64 v6, v6, v21, s4
	v_xor_b32_e32 v15, v9, v8
	v_cndmask_b32_e32 v8, 0, v16, vcc_lo
	v_cndmask_b32_e32 v9, 0x7ff80000, v11, vcc_lo
	v_cndmask_b32_e64 v10, 0, v10, s0
	v_cndmask_b32_e64 v13, v24, v35, s3
	v_cndmask_b32_e64 v11, 0x7ff80000, v15, s0
	v_cndmask_b32_e64 v12, v26, v34, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v2, v13, v2
	v_mul_f64 v[15:16], v[10:11], v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v12, 0, v12, s2
	v_cndmask_b32_e64 v13, 0x7ff80000, v2, s2
	v_lshlrev_b32_e32 v2, 30, v42
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v1, v2, v1
	v_and_b32_e32 v2, 1, v45
	v_and_b32_e32 v1, 0x80000000, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cmp_eq_u32_e64 s3, 0, v2
	v_and_b32_e32 v2, 0x80000000, v3
	v_xor_b32_e32 v3, 0x80000000, v7
	v_cndmask_b32_e64 v14, v18, v20, s3
	v_cndmask_b32_e64 v7, v17, v19, s3
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e64 v3, v3, v22, s4
	s_mov_b32 s3, 0x3fe55555
	s_mov_b32 s4, 0x11122322
	v_xor_b32_e32 v14, v14, v2
	v_cndmask_b32_e64 v2, 0, v7, s2
	v_mul_f64 v[24:25], v[15:16], v[12:13]
	v_lshlrev_b32_e32 v15, 30, v40
	v_cndmask_b32_e64 v16, v37, v23, s1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v15, 0x80000000, v15
	v_xor_b32_e32 v1, v16, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v15, v3, v15
	v_cndmask_b32_e64 v3, 0x7ff80000, v14, s2
	v_cndmask_b32_e64 v1, 0x7ff80000, v1, s0
	v_cndmask_b32_e32 v14, 0, v6, vcc_lo
	s_mov_b32 s2, s6
	v_cndmask_b32_e32 v15, 0x7ff80000, v15, vcc_lo
	v_mul_f64 v[6:7], v[10:11], v[2:3]
	s_mov_b32 s6, 0x555502a1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f64 v[10:11], v[14:15], v[10:11]
	v_fma_f64 v[2:3], v[14:15], v[0:1], -v[24:25]
	v_frexp_mant_f64_e64 v[16:17], |v[6:7]|
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f64 v[10:11], v[10:11], v[12:13]
	v_frexp_mant_f64_e64 v[18:19], |v[2:3]|
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_gt_f64_e32 vcc_lo, s[2:3], v[16:17]
	v_fma_f64 v[0:1], v[8:9], v[0:1], v[10:11]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f64_e64 s0, s[2:3], v[18:19]
	v_cndmask_b32_e64 v20, 0, 1, vcc_lo
	v_ldexp_f64 v[16:17], v[16:17], v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v21, 0, 1, s0
	v_ldexp_f64 v[18:19], v[18:19], v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[20:21], v[16:17], 1.0
	v_add_f64 v[32:33], v[16:17], -1.0
	v_add_f64 v[22:23], v[18:19], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_rcp_f64_e32 v[24:25], v[20:21]
	v_add_f64 v[36:37], v[20:21], -1.0
	v_rcp_f64_e32 v[26:27], v[22:23]
	v_add_f64 v[40:41], v[22:23], -1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[16:17], -v[36:37]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[28:29], -v[20:21], v[24:25], 1.0
	v_fma_f64 v[30:31], -v[22:23], v[26:27], 1.0
	v_fma_f64 v[24:25], v[28:29], v[24:25], v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[26:27], v[30:31], v[26:27], v[26:27]
	v_fma_f64 v[28:29], -v[20:21], v[24:25], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[30:31], -v[22:23], v[26:27], 1.0
	v_fma_f64 v[24:25], v[28:29], v[24:25], v[24:25]
	v_add_f64 v[28:29], v[18:19], -1.0
	v_add_f64 v[18:19], v[18:19], -v[40:41]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[26:27], v[30:31], v[26:27], v[26:27]
	v_mul_f64 v[30:31], v[32:33], v[24:25]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[34:35], v[28:29], v[26:27]
	v_mul_f64 v[38:39], v[20:21], v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[42:43], v[22:23], v[34:35]
	v_fma_f64 v[20:21], v[30:31], v[20:21], -v[38:39]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[22:23], v[34:35], v[22:23], -v[42:43]
	v_fma_f64 v[16:17], v[30:31], v[16:17], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[18:19], v[34:35], v[18:19], v[22:23]
	v_add_f64 v[20:21], v[38:39], v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[22:23], v[42:43], v[18:19]
	v_add_f64 v[36:37], v[32:33], -v[20:21]
	v_add_f64 v[38:39], v[20:21], -v[38:39]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[40:41], v[28:29], -v[22:23]
	v_add_f64 v[42:43], v[22:23], -v[42:43]
	v_add_f64 v[32:33], v[32:33], -v[36:37]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[16:17], v[38:39], -v[16:17]
	v_add_f64 v[28:29], v[28:29], -v[40:41]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[18:19], v[42:43], -v[18:19]
	v_add_f64 v[20:21], v[32:33], -v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[22:23], v[28:29], -v[22:23]
	v_add_f64 v[16:17], v[16:17], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[18:19], v[18:19], v[22:23]
	v_add_f64 v[16:17], v[36:37], v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[18:19], v[40:41], v[18:19]
	v_mul_f64 v[16:17], v[24:25], v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[18:19], v[26:27], v[18:19]
	v_add_f64 v[20:21], v[30:31], v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[22:23], v[34:35], v[18:19]
	v_add_f64 v[24:25], v[20:21], -v[30:31]
	v_mul_f64 v[28:29], v[20:21], v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[26:27], v[22:23], -v[34:35]
	v_add_f64 v[16:17], v[16:17], -v[24:25]
	v_mul_f64 v[24:25], v[22:23], v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[18:19], v[18:19], -v[26:27]
	v_fma_f64 v[26:27], v[20:21], v[20:21], -v[28:29]
	v_add_f64 v[30:31], v[16:17], v[16:17]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[32:33], v[22:23], v[22:23], -v[24:25]
	v_add_f64 v[34:35], v[18:19], v[18:19]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[26:27], v[20:21], v[30:31], v[26:27]
	v_fma_f64 v[30:31], v[22:23], v[34:35], v[32:33]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[32:33], v[28:29], v[26:27]
	v_add_f64 v[34:35], v[24:25], v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f64 v[36:37], v[32:33], s[14:15], s[12:13]
	v_add_f64 v[28:29], v[32:33], -v[28:29]
	v_mul_f64 v[46:47], v[20:21], v[32:33]
	v_fma_f64 v[38:39], v[34:35], s[14:15], s[12:13]
	s_mov_b32 s12, 0x3abe935a
	s_mov_b32 s13, 0x3fbe25e4
	v_add_f64 v[24:25], v[34:35], -v[24:25]
	v_mul_f64 v[50:51], v[22:23], v[34:35]
	s_mov_b32 s14, 0x652b82fe
	s_mov_b32 s15, 0x3ff71547
	v_fma_f64 v[36:37], v[32:33], v[36:37], s[12:13]
	v_add_f64 v[26:27], v[26:27], -v[28:29]
	v_fma_f64 v[38:39], v[34:35], v[38:39], s[12:13]
	s_mov_b32 s12, 0x47e6c9c2
	s_mov_b32 s13, 0x3fc110ef
	v_add_f64 v[24:25], v[30:31], -v[24:25]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[36:37], v[32:33], v[36:37], s[12:13]
	v_fma_f64 v[38:39], v[34:35], v[38:39], s[12:13]
	s_mov_b32 s12, 0xcfa74449
	s_mov_b32 s13, 0x3fc3b13b
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[36:37], v[32:33], v[36:37], s[12:13]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[38:39], v[34:35], v[38:39], s[12:13]
	s_mov_b32 s12, 0x71bf3c30
	s_mov_b32 s13, 0x3fc745d1
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[36:37], v[32:33], v[36:37], s[12:13]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[38:39], v[34:35], v[38:39], s[12:13]
	s_mov_b32 s12, 0x1c7792ce
	s_mov_b32 s13, 0x3fcc71c7
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[36:37], v[32:33], v[36:37], s[12:13]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[38:39], v[34:35], v[38:39], s[12:13]
	s_mov_b32 s12, 0x924920da
	s_mov_b32 s13, 0x3fd24924
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[36:37], v[32:33], v[36:37], s[12:13]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[38:39], v[34:35], v[38:39], s[12:13]
	s_mov_b32 s12, 0x9999999c
	s_mov_b32 s13, 0x3fd99999
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[36:37], v[32:33], v[36:37], s[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f64 v[38:39], v[34:35], v[38:39], s[12:13]
	s_mov_b32 s12, 0x3b39803f
	s_mov_b32 s13, 0x3c7abc9e
	v_mul_f64 v[40:41], v[32:33], v[36:37]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[42:43], v[34:35], v[38:39]
	v_fma_f64 v[28:29], v[32:33], v[36:37], -v[40:41]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[30:31], v[34:35], v[38:39], -v[42:43]
	v_fma_f64 v[28:29], v[26:27], v[36:37], v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[30:31], v[24:25], v[38:39], v[30:31]
	v_add_f64 v[36:37], v[40:41], v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[38:39], v[42:43], v[30:31]
	v_add_f64 v[44:45], v[36:37], s[2:3]
	v_add_f64 v[40:41], v[36:37], -v[40:41]
	s_delay_alu instid0(VALU_DEP_3)
	v_add_f64 v[48:49], v[38:39], s[2:3]
	v_add_f64 v[42:43], v[38:39], -v[42:43]
	s_mov_b32 s3, 0xbfe55555
	s_delay_alu instid0(VALU_DEP_4) | instid1(SALU_CYCLE_1)
	v_add_f64 v[52:53], v[44:45], s[2:3]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f64 v[28:29], v[28:29], -v[40:41]
	v_fma_f64 v[40:41], v[32:33], v[20:21], -v[46:47]
	v_add_f64 v[54:55], v[48:49], s[2:3]
	v_add_f64 v[30:31], v[30:31], -v[42:43]
	v_fma_f64 v[42:43], v[34:35], v[22:23], -v[50:51]
	s_mov_b32 s2, 0xd5df274d
	s_mov_b32 s3, 0x3c8543b0
	v_add_f64 v[36:37], v[36:37], -v[52:53]
	v_add_f64 v[28:29], v[28:29], s[2:3]
	v_fma_f64 v[32:33], v[32:33], v[16:17], v[40:41]
	v_ldexp_f64 v[16:17], v[16:17], 1
	v_add_f64 v[38:39], v[38:39], -v[54:55]
	v_add_f64 v[30:31], v[30:31], s[2:3]
	v_fma_f64 v[34:35], v[34:35], v[18:19], v[42:43]
	s_mov_b32 s2, 0xfefa39ef
	s_mov_b32 s3, 0x3fe62e42
	v_ldexp_f64 v[18:19], v[18:19], 1
	v_add_f64 v[28:29], v[28:29], v[36:37]
	v_fma_f64 v[26:27], v[26:27], v[20:21], v[32:33]
	v_ldexp_f64 v[20:21], v[20:21], 1
	v_add_f64 v[30:31], v[30:31], v[38:39]
	v_fma_f64 v[24:25], v[24:25], v[22:23], v[34:35]
	v_ldexp_f64 v[22:23], v[22:23], 1
	v_add_f64 v[32:33], v[44:45], v[28:29]
	v_add_f64 v[34:35], v[46:47], v[26:27]
	v_add_f64 v[36:37], v[48:49], v[30:31]
	v_add_f64 v[38:39], v[50:51], v[24:25]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[40:41], v[44:45], -v[32:33]
	v_mul_f64 v[42:43], v[34:35], v[32:33]
	v_add_f64 v[46:47], v[34:35], -v[46:47]
	v_add_f64 v[44:45], v[48:49], -v[36:37]
	v_mul_f64 v[48:49], v[38:39], v[36:37]
	v_add_f64 v[50:51], v[38:39], -v[50:51]
	v_add_f64 v[28:29], v[28:29], v[40:41]
	v_fma_f64 v[40:41], v[34:35], v[32:33], -v[42:43]
	v_add_f64 v[26:27], v[26:27], -v[46:47]
	v_add_f64 v[30:31], v[30:31], v[44:45]
	v_fma_f64 v[44:45], v[38:39], v[36:37], -v[48:49]
	v_add_f64 v[24:25], v[24:25], -v[50:51]
	v_fma_f64 v[28:29], v[34:35], v[28:29], v[40:41]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[30:31], v[38:39], v[30:31], v[44:45]
	v_fma_f64 v[26:27], v[26:27], v[32:33], v[28:29]
	v_frexp_exp_i32_f64_e32 v32, v[6:7]
	v_frexp_exp_i32_f64_e32 v33, v[2:3]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[24:25], v[24:25], v[36:37], v[30:31]
	v_add_f64 v[28:29], v[42:43], v[26:27]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_subrev_co_ci_u32_e32 v32, vcc_lo, 0, v32, vcc_lo
	v_subrev_co_ci_u32_e64 v38, vcc_lo, 0, v33, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_i32_e32 v[32:33], v32
	v_cvt_f64_i32_e32 v[38:39], v38
	v_add_f64 v[30:31], v[48:49], v[24:25]
	v_add_f64 v[34:35], v[20:21], v[28:29]
	v_add_f64 v[36:37], v[28:29], -v[42:43]
	v_mul_f64 v[44:45], v[32:33], s[2:3]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f64 v[40:41], v[22:23], v[30:31]
	v_add_f64 v[42:43], v[30:31], -v[48:49]
	v_add_f64 v[20:21], v[34:35], -v[20:21]
	v_add_f64 v[26:27], v[26:27], -v[36:37]
	v_mul_f64 v[36:37], v[38:39], s[2:3]
	v_add_f64 v[22:23], v[40:41], -v[22:23]
	v_add_f64 v[24:25], v[24:25], -v[42:43]
	v_fma_f64 v[42:43], v[32:33], s[2:3], -v[44:45]
	v_add_f64 v[20:21], v[28:29], -v[20:21]
	v_add_f64 v[16:17], v[16:17], v[26:27]
	v_fma_f64 v[26:27], v[38:39], s[2:3], -v[36:37]
	s_mov_b32 s3, 0xbfe62e42
	v_add_f64 v[22:23], v[30:31], -v[22:23]
	v_add_f64 v[18:19], v[18:19], v[24:25]
	v_fma_f64 v[24:25], v[32:33], s[12:13], v[42:43]
	v_add_f64 v[16:17], v[16:17], v[20:21]
	v_fma_f64 v[20:21], v[38:39], s[12:13], v[26:27]
	s_mov_b32 s13, 0xbc7abc9e
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[18:19], v[18:19], v[22:23]
	v_add_f64 v[22:23], v[44:45], v[24:25]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[26:27], v[34:35], v[16:17]
	v_add_f64 v[28:29], v[36:37], v[20:21]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[30:31], v[40:41], v[18:19]
	v_add_f64 v[44:45], v[22:23], -v[44:45]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f64 v[32:33], v[22:23], v[26:27]
	v_add_f64 v[34:35], v[26:27], -v[34:35]
	v_add_f64 v[36:37], v[28:29], -v[36:37]
	v_add_f64 v[38:39], v[28:29], v[30:31]
	v_add_f64 v[40:41], v[30:31], -v[40:41]
	v_add_f64 v[24:25], v[24:25], -v[44:45]
	v_add_f64 v[42:43], v[32:33], -v[22:23]
	v_add_f64 v[16:17], v[16:17], -v[34:35]
	v_add_f64 v[20:21], v[20:21], -v[36:37]
	v_add_f64 v[46:47], v[38:39], -v[28:29]
	v_add_f64 v[18:19], v[18:19], -v[40:41]
	v_add_f64 v[48:49], v[32:33], -v[42:43]
	v_add_f64 v[26:27], v[26:27], -v[42:43]
	v_add_f64 v[34:35], v[24:25], v[16:17]
	v_add_f64 v[50:51], v[38:39], -v[46:47]
	v_add_f64 v[30:31], v[30:31], -v[46:47]
	v_add_f64 v[22:23], v[22:23], -v[48:49]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[28:29], v[28:29], -v[50:51]
	v_add_f64 v[22:23], v[26:27], v[22:23]
	v_add_f64 v[26:27], v[20:21], v[18:19]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[28:29], v[30:31], v[28:29]
	v_add_f64 v[30:31], v[34:35], -v[24:25]
	v_add_f64 v[22:23], v[34:35], v[22:23]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[36:37], v[26:27], -v[20:21]
	v_add_f64 v[28:29], v[26:27], v[28:29]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f64 v[34:35], v[34:35], -v[30:31]
	v_add_f64 v[16:17], v[16:17], -v[30:31]
	v_add_f64 v[40:41], v[32:33], v[22:23]
	v_add_f64 v[26:27], v[26:27], -v[36:37]
	v_add_f64 v[18:19], v[18:19], -v[36:37]
	v_add_f64 v[42:43], v[38:39], v[28:29]
	v_add_f64 v[24:25], v[24:25], -v[34:35]
	v_add_f64 v[30:31], v[40:41], -v[32:33]
	v_add_f64 v[20:21], v[20:21], -v[26:27]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[26:27], v[42:43], -v[38:39]
	v_add_f64 v[16:17], v[16:17], v[24:25]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[22:23], v[22:23], -v[30:31]
	v_add_f64 v[18:19], v[18:19], v[20:21]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[20:21], v[28:29], -v[26:27]
	v_add_f64 v[16:17], v[16:17], v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[18:19], v[18:19], v[20:21]
	v_add_f64 v[20:21], v[40:41], v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[22:23], v[42:43], v[18:19]
	v_add_f64 v[24:25], v[20:21], -v[40:41]
	v_add_f64 v[26:27], v[20:21], v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[28:29], v[22:23], -v[42:43]
	v_add_f64 v[30:31], v[22:23], v[22:23]
	v_add_f64 v[16:17], v[16:17], -v[24:25]
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f64 v[20:21], v[20:21], 2.0, -v[26:27]
	v_cmp_class_f64_e64 vcc_lo, v[26:27], 0x204
	v_add_f64 v[18:19], v[18:19], -v[28:29]
	v_fma_f64 v[22:23], v[22:23], 2.0, -v[30:31]
	v_cmp_class_f64_e64 s0, v[30:31], 0x204
	v_fma_f64 v[16:17], v[16:17], 2.0, v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[18:19], v[18:19], 2.0, v[22:23]
	v_add_f64 v[20:21], v[26:27], v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[22:23], v[30:31], v[18:19]
	v_dual_cndmask_b32 v24, v20, v26 :: v_dual_cndmask_b32 v25, v21, v27
	v_add_f64 v[20:21], v[20:21], -v[26:27]
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_f64 v[32:33], v[24:25], s[14:15]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[24:25]|
	v_cndmask_b32_e64 v29, v23, v31, s0
	v_cndmask_b32_e64 v28, v22, v30, s0
	s_mov_b32 s0, 0xfca7ab0c
	s_mov_b32 s1, 0x3e928af3
	v_add_f64 v[22:23], v[22:23], -v[30:31]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_mul_f64 v[34:35], v[28:29], s[14:15]
	s_mov_b32 s14, 0xa595c56f
	s_mov_b32 s15, 0x3f7d6d43
	v_add_f64 v[16:17], v[16:17], -v[20:21]
	v_rndne_f64_e32 v[32:33], v[32:33]
	v_add_f64 v[18:19], v[18:19], -v[22:23]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_rndne_f64_e32 v[34:35], v[34:35]
	v_dual_cndmask_b32 v17, 0, v17 :: v_dual_cndmask_b32 v16, 0, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fma_f64 v[36:37], v[32:33], s[2:3], v[24:25]
	v_cvt_i32_f64_e32 v44, v[32:33]
	v_fma_f64 v[38:39], v[34:35], s[2:3], v[28:29]
	s_mov_b32 s2, 0x6a5dcb37
	s_mov_b32 s3, 0x3e5ade15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[36:37], v[32:33], s[12:13], v[36:37]
	v_fma_f64 v[38:39], v[34:35], s[12:13], v[38:39]
	s_mov_b32 s12, 0xaf56de9b
	s_mov_b32 s13, 0xbf67952d
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[40:41], v[36:37], s[2:3], s[0:1]
	v_fma_f64 v[42:43], v[38:39], s[2:3], s[0:1]
	s_mov_b32 s0, 0x623fde64
	s_mov_b32 s1, 0x3ec71dee
	v_cmp_nlt_f64_e64 s3, 0x40900000, v[28:29]
	v_cmp_ngt_f64_e64 s2, 0xc090cc00, v[24:25]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[40:41], v[36:37], v[40:41], s[0:1]
	v_fma_f64 v[42:43], v[38:39], v[42:43], s[0:1]
	s_mov_b32 s0, 0x7c89e6b0
	s_mov_b32 s1, 0x3efa0199
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[40:41], v[36:37], v[40:41], s[0:1]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[42:43], v[38:39], v[42:43], s[0:1]
	s_mov_b32 s0, 0x14761f6e
	s_mov_b32 s1, 0x3f2a01a0
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[40:41], v[36:37], v[40:41], s[0:1]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[42:43], v[38:39], v[42:43], s[0:1]
	s_mov_b32 s0, 0x1852b7b0
	s_mov_b32 s1, 0x3f56c16c
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[40:41], v[36:37], v[40:41], s[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f64 v[42:43], v[38:39], v[42:43], s[0:1]
	s_mov_b32 s0, 0x55555511
	s_mov_b32 s1, 0x3fc55555
	v_fma_f64 v[40:41], v[36:37], v[40:41], s[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[42:43], v[38:39], v[42:43], s[4:5]
	v_cmp_ngt_f64_e64 s4, 0xc090cc00, v[28:29]
	v_fma_f64 v[40:41], v[36:37], v[40:41], s[6:7]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f64 v[42:43], v[38:39], v[42:43], s[6:7]
	s_mov_b32 s6, 0x69efb384
	s_mov_b32 s7, 0x3f4b2bb0
	v_fma_f64 v[40:41], v[36:37], v[40:41], s[0:1]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[42:43], v[38:39], v[42:43], s[0:1]
	s_mov_b32 s0, 11
	s_mov_b32 s1, 0x3fe00000
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[40:41], v[36:37], v[40:41], s[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f64 v[42:43], v[38:39], v[42:43], s[0:1]
	v_cmp_nlt_f64_e64 s1, 0x40900000, v[24:25]
	v_cmp_neq_f64_e64 s0, 0x7ff00000, |v[28:29]|
	v_fma_f64 v[40:41], v[36:37], v[40:41], 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[42:43], v[38:39], v[42:43], 1.0
	s_and_b32 vcc_lo, s2, s1
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e64 v19, 0, v19, s0
	v_cndmask_b32_e64 v18, 0, v18, s0
	v_cmp_neq_f64_e64 s0, 0, v[2:3]
	v_fma_f64 v[32:33], v[36:37], v[40:41], 1.0
	v_cvt_i32_f64_e32 v36, v[34:35]
	v_fma_f64 v[34:35], v[38:39], v[42:43], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[26:27], v[32:33], v44
	v_ldexp_f64 v[30:31], v[34:35], v36
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v20, 0x7ff00000, v27, s1
	v_cndmask_b32_e64 v21, 0, v20, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v20, 0, v26, vcc_lo
	s_and_b32 vcc_lo, s4, s3
	v_cmp_neq_f64_e64 s2, 0x7ff00000, |v[6:7]|
	v_fma_f64 v[16:17], v[20:21], v[16:17], v[20:21]
	v_cndmask_b32_e64 v22, 0x7ff00000, v31, s3
	v_cmp_neq_f64_e64 s3, 0, v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v23, 0, v22, s4
	v_cndmask_b32_e32 v22, 0, v30, vcc_lo
	v_cmp_class_f64_e64 vcc_lo, v[20:21], 0x204
	v_cmp_neq_f64_e64 s4, 0x7ff00000, |v[2:3]|
	v_fma_f64 v[18:19], v[22:23], v[18:19], v[22:23]
	v_cmp_class_f64_e64 s1, v[22:23], 0x204
	v_cndmask_b32_e32 v17, v17, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v19, v19, v23, s1
	v_dual_cndmask_b32 v16, v16, v20 :: v_dual_and_b32 v17, 0x7fffffff, v17
	s_and_b32 vcc_lo, s3, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v19, 0x7fffffff, v19
	v_cndmask_b32_e64 v17, 0x7ff00000, v17, s2
	v_cndmask_b32_e64 v18, v18, v22, s1
	v_cndmask_b32_e32 v16, 0, v16, vcc_lo
	s_and_b32 vcc_lo, s0, s4
	v_cndmask_b32_e64 v19, 0x7ff00000, v19, s4
	v_cndmask_b32_e64 v17, 0, v17, s3
	v_cndmask_b32_e32 v18, 0, v18, vcc_lo
	s_mov_b32 s2, 0xbd3237f4
	s_mov_b32 s4, 0xb5e68a13
	v_cndmask_b32_e64 v19, 0, v19, s0
	s_mov_b32 s3, 0xbf23e260
	s_mov_b32 s5, 0x3eeba404
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[18:19], v[16:17]
	v_cmp_gt_f64_e32 vcc_lo, 0x10000000, v[16:17]
	v_cndmask_b32_e64 v18, 0, 1, vcc_lo
	v_cndmask_b32_e64 v12, 0, 0xffffff80, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b32_e32 v18, 8, v18
	v_ldexp_f64 v[16:17], v[16:17], v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_rsq_f64_e32 v[18:19], v[16:17]
	v_cmp_class_f64_e64 vcc_lo, v[16:17], 0x260
	s_waitcnt_depctr 0xfff
	v_mul_f64 v[20:21], v[16:17], v[18:19]
	v_mul_f64 v[18:19], v[18:19], 0.5
	v_fma_f64 v[22:23], -v[18:19], v[20:21], 0.5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[20:21], v[20:21], v[22:23], v[20:21]
	v_fma_f64 v[18:19], v[18:19], v[22:23], v[18:19]
	v_fma_f64 v[22:23], -v[20:21], v[20:21], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[22:23], v[18:19], v[20:21]
	v_fma_f64 v[22:23], -v[20:21], v[20:21], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[22:23], v[18:19], v[20:21]
	v_ldexp_f64 v[12:13], v[14:15], v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v9, v13, v17 :: v_dual_cndmask_b32 v8, v12, v16
	v_div_scale_f64 v[10:11], null, v[0:1], v[0:1], v[8:9]
	v_div_scale_f64 v[16:17], vcc_lo, v[8:9], v[0:1], v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[12:13], v[10:11]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
	v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
	v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[14:15], v[16:17], v[12:13]
	v_fma_f64 v[10:11], -v[10:11], v[14:15], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[10:11], v[10:11], v[12:13], v[14:15]
	v_div_fixup_f64 v[0:1], v[10:11], v[0:1], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v8, v0 :: v_dual_and_b32 v9, 0x7fffffff, v1
	v_div_scale_f64 v[10:11], null, v[8:9], v[8:9], 1.0
	v_div_scale_f64 v[16:17], vcc_lo, 1.0, v[8:9], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[12:13], v[10:11]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
	v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
	v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[14:15], v[16:17], v[12:13]
	v_fma_f64 v[10:11], -v[10:11], v[14:15], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[10:11], v[10:11], v[12:13], v[14:15]
	v_cmp_gt_f64_e64 vcc_lo, |v[0:1]|, 1.0
	v_div_fixup_f64 v[10:11], v[10:11], |v[0:1]|, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v9, v9, v11 :: v_dual_cndmask_b32 v8, v8, v10
	v_mul_f64 v[10:11], v[8:9], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[10:11], s[4:5], s[2:3]
	v_fma_f64 v[12:13], v[10:11], v[12:13], s[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[10:11], v[12:13], s[12:13]
	v_fma_f64 v[12:13], v[10:11], v[12:13], s[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[10:11], v[12:13], s[16:17]
	v_fma_f64 v[12:13], v[10:11], v[12:13], s[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[10:11], v[12:13], s[20:21]
	v_fma_f64 v[12:13], v[10:11], v[12:13], s[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[10:11], v[12:13], s[24:25]
	v_fma_f64 v[12:13], v[10:11], v[12:13], s[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[10:11], v[12:13], s[28:29]
	v_fma_f64 v[12:13], v[10:11], v[12:13], s[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[10:11], v[12:13], s[34:35]
	v_fma_f64 v[12:13], v[10:11], v[12:13], s[36:37]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[10:11], v[12:13], s[38:39]
	v_fma_f64 v[12:13], v[10:11], v[12:13], s[40:41]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[10:11], v[12:13], s[42:43]
	v_fma_f64 v[12:13], v[10:11], v[12:13], s[44:45]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[10:11], v[12:13], s[46:47]
	v_mul_f64 v[10:11], v[10:11], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
	v_fma_f64 v[10:11], s[50:51], s[48:49], -v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v9, v9, v11 :: v_dual_cndmask_b32 v0, v8, v10
	v_bfi_b32 v1, 0x7fffffff, v9, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f64 v[8:9], v[0:1], s[52:53]
	v_lshlrev_b64 v[0:1], 3, v[4:5]
	v_add_co_u32 v4, vcc_lo, s8, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, s9, v1, vcc_lo
	global_store_b64 v[4:5], v[8:9], off
                                        ; implicit-def: $vgpr4_vgpr5
	s_and_saveexec_b32 s1, s0
	s_xor_b32 s0, exec_lo, s1
	s_cbranch_execz .LBB0_29
; %bb.26:
	v_div_scale_f64 v[4:5], null, v[2:3], v[2:3], -v[6:7]
	v_div_scale_f64 v[12:13], vcc_lo, -v[6:7], v[2:3], -v[6:7]
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[8:9], v[4:5]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[10:11], -v[4:5], v[8:9], 1.0
	v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], -v[4:5], v[8:9], 1.0
	v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[10:11], v[12:13], v[8:9]
	v_fma_f64 v[4:5], -v[4:5], v[10:11], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[4:5], v[4:5], v[8:9], v[10:11]
	v_div_fixup_f64 v[4:5], v[4:5], v[2:3], -v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v6, v4 :: v_dual_and_b32 v7, 0x7fffffff, v5
	v_div_scale_f64 v[8:9], null, v[6:7], v[6:7], 1.0
	v_div_scale_f64 v[14:15], vcc_lo, 1.0, v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[10:11], v[8:9]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
	v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
	v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[12:13], v[14:15], v[10:11]
	v_fma_f64 v[8:9], -v[8:9], v[12:13], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[8:9], v[8:9], v[10:11], v[12:13]
	v_cmp_gt_f64_e64 vcc_lo, |v[4:5]|, 1.0
	v_div_fixup_f64 v[8:9], v[8:9], |v[4:5]|, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v7, v7, v9 :: v_dual_cndmask_b32 v6, v6, v8
	v_mul_f64 v[8:9], v[6:7], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[8:9], s[4:5], s[2:3]
	s_mov_b32 s2, 0x54442d18
	s_mov_b32 s3, 0x400921fb
	v_fma_f64 v[10:11], v[8:9], v[10:11], s[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[8:9], v[10:11], s[12:13]
	v_fma_f64 v[10:11], v[8:9], v[10:11], s[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[8:9], v[10:11], s[16:17]
	v_fma_f64 v[10:11], v[8:9], v[10:11], s[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[8:9], v[10:11], s[20:21]
	v_fma_f64 v[10:11], v[8:9], v[10:11], s[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[8:9], v[10:11], s[24:25]
	v_fma_f64 v[10:11], v[8:9], v[10:11], s[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[8:9], v[10:11], s[28:29]
	v_fma_f64 v[10:11], v[8:9], v[10:11], s[30:31]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[8:9], v[10:11], s[34:35]
	v_fma_f64 v[10:11], v[8:9], v[10:11], s[36:37]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[8:9], v[10:11], s[38:39]
	v_fma_f64 v[10:11], v[8:9], v[10:11], s[40:41]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[8:9], v[10:11], s[42:43]
	v_fma_f64 v[10:11], v[8:9], v[10:11], s[44:45]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[8:9], v[10:11], s[46:47]
	v_mul_f64 v[8:9], v[8:9], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_fma_f64 v[8:9], s[50:51], s[48:49], -v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v7, v7, v9 :: v_dual_cndmask_b32 v4, v6, v8
	v_bfi_b32 v5, 0x7fffffff, v7, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[4:5], 0x40668000, v[4:5]
	v_div_scale_f64 v[6:7], null, s[2:3], s[2:3], v[4:5]
	v_div_scale_f64 v[12:13], vcc_lo, v[4:5], s[2:3], v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[8:9], v[6:7]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
	v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], -v[6:7], v[8:9], 1.0
	v_fma_f64 v[8:9], v[8:9], v[10:11], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[10:11], v[12:13], v[8:9]
	v_fma_f64 v[6:7], -v[6:7], v[10:11], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[6:7], v[6:7], v[8:9], v[10:11]
	v_div_fixup_f64 v[4:5], v[6:7], s[2:3], v[4:5]
	v_cmpx_gt_f64_e32 0, v[2:3]
; %bb.27:
	s_delay_alu instid0(VALU_DEP_2)
	v_add_f64 v[4:5], 0x40668000, v[4:5]
; %bb.28:                               ; %Flow121
	s_or_b32 exec_lo, exec_lo, s1
                                        ; implicit-def: $vgpr6_vgpr7
.LBB0_29:                               ; %Flow124
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB0_35
; %bb.30:
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0xc0568000
	s_mov_b32 s1, exec_lo
	v_cmpx_nlt_f64_e32 0, v[6:7]
	s_cbranch_execz .LBB0_34
; %bb.31:
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0x40568000
	s_mov_b32 s2, exec_lo
	v_cmpx_ngt_f64_e32 0, v[6:7]
; %bb.32:
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0
; %bb.33:                               ; %Flow122
	s_or_b32 exec_lo, exec_lo, s2
.LBB0_34:                               ; %Flow123
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_35:
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s0
	v_add_f64 v[2:3], 0x40668000, v[4:5]
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_le_f64_e32 0x40768000, v[2:3]
	s_cbranch_execz .LBB0_39
; %bb.36:                               ; %.lr.ph.preheader
	s_mov_b32 s1, 0
.LBB0_37:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_add_f64 v[2:3], 0xc0768000, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_nle_f64_e32 vcc_lo, 0x40768000, v[2:3]
	s_or_b32 s1, vcc_lo, s1
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB0_37
; %bb.38:                               ; %Flow
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_39:                               ; %Flow120
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s0
	v_add_f64 v[2:3], 0xc0668000, v[2:3]
	s_mov_b32 s1, 0xc00921fb
	s_mov_b32 s0, 0x54442d18
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_mul_f64 v[2:3], v[2:3], s[0:1]
	s_mov_b32 s1, 0x401921fb
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[4:5], null, 0x40668000, 0x40668000, v[2:3]
	v_div_scale_f64 v[10:11], vcc_lo, v[2:3], 0x40668000, v[2:3]
	v_rcp_f64_e32 v[6:7], v[4:5]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_mul_f64 v[8:9], v[10:11], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], -v[4:5], v[8:9], v[10:11]
	v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[2:3], v[4:5], 0x40668000, v[2:3]
	v_div_scale_f64 v[4:5], null, s[0:1], s[0:1], v[2:3]
	v_div_scale_f64 v[10:11], vcc_lo, v[2:3], s[0:1], v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[6:7], v[4:5]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[8:9], v[10:11], v[6:7]
	v_fma_f64 v[4:5], -v[4:5], v[8:9], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[8:9]
	v_div_fixup_f64 v[4:5], v[4:5], s[0:1], v[2:3]
	s_mov_b32 s1, 0xc01921fb
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_floor_f64_e32 v[4:5], v[4:5]
	v_fma_f64 v[2:3], v[4:5], s[0:1], v[2:3]
	s_mov_b32 s1, 0x400921fb
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[2:3], 0x40668000, v[2:3]
	v_div_scale_f64 v[4:5], null, s[0:1], s[0:1], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[6:7], v[4:5]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], -v[4:5], v[6:7], 1.0
	v_fma_f64 v[6:7], v[6:7], v[8:9], v[6:7]
	v_div_scale_f64 v[8:9], vcc_lo, v[2:3], s[0:1], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[10:11], v[8:9], v[6:7]
	v_fma_f64 v[4:5], -v[4:5], v[10:11], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_fmas_f64 v[4:5], v[4:5], v[6:7], v[10:11]
	v_add_co_u32 v0, vcc_lo, s10, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s11, v1, vcc_lo
	v_div_fixup_f64 v[2:3], v[4:5], s[0:1], v[2:3]
	global_store_b64 v[0:1], v[2:3], off
.LBB0_40:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10geo_invertP15HIP_vector_typeIdLj2EES1_PdS2_l
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 92
		.amdhsa_next_free_sgpr 54
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z10geo_invertP15HIP_vector_typeIdLj2EES1_PdS2_l, .Lfunc_end0-_Z10geo_invertP15HIP_vector_typeIdLj2EES1_PdS2_l
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 13852
; NumSgprs: 56
; NumVgprs: 92
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 6
; VGPRBlocks: 11
; NumSGPRsForWavesPerEU: 56
; NumVGPRsForWavesPerEU: 92
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10geo_invertP15HIP_vector_typeIdLj2EES1_PdS2_l
    .private_segment_fixed_size: 0
    .sgpr_count:     56
    .sgpr_spill_count: 0
    .symbol:         _Z10geo_invertP15HIP_vector_typeIdLj2EES1_PdS2_l.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     92
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
