#pragma once

__global__ void
OmgSin_kernel(int numElement, const float *bufferin, float *bufferout)
{
  // TODO make it u24
  int blockId = blockIdx.y * gridDim.x +  blockIdx.x;
  int tid = threadIdx.x + blockId * blockDim.x;
  int step = gridDim.x * blockDim.x;

    //blockIdx.y * step + blockIdx.x * gridDim.x * blockDim.x;
  for (int gid = tid; gid < numElement; gid += step)
    if (gid < numElement)
      bufferout[gid] = sinf(bufferin[gid]);
}


__global__ void
OmgCos_kernel(int numElement, const float *bufferin, float *bufferout)
{
  // TODO make it u24
  int blockId = blockIdx.y * gridDim.x +  blockIdx.x;
  int tid = threadIdx.x + blockId * blockDim.x;
  int step = gridDim.x * blockDim.x;

    //blockIdx.y * step + blockIdx.x * gridDim.x * blockDim.x;
  for (int gid = tid; gid < numElement; gid += step)
    if (gid < numElement)
      bufferout[gid] = cosf(bufferin[gid]);
}


__global__ void
OmgTan_kernel(int numElement, const float *bufferin, float *bufferout)
{
  // TODO make it u24
  int blockId = blockIdx.y * gridDim.x +  blockIdx.x;
  int tid = threadIdx.x + blockId * blockDim.x;
  int step = gridDim.x * blockDim.x;

    //blockIdx.y * step + blockIdx.x * gridDim.x * blockDim.x;
  for (int gid = tid; gid < numElement; gid += step)
    if (gid < numElement)
      bufferout[gid] = tanf(bufferin[gid]);
}


__global__ void
OmgCot_kernel(int numElement, const float *bufferin, float *bufferout)
{
  // TODO make it u24
  int blockId = blockIdx.y * gridDim.x +  blockIdx.x;
  int tid = threadIdx.x + blockId * blockDim.x;
  int step = gridDim.x * blockDim.x;

    //blockIdx.y * step + blockIdx.x * gridDim.x * blockDim.x;
  for (int gid = tid; gid < numElement; gid += step)
    if (gid < numElement)
      bufferout[gid] = 1.0f/tanf(bufferin[gid]);
}


__global__ void
OmgLog_kernel(int numElement, const float *bufferin, float *bufferout)
{
  // TODO make it u24
  int blockId = blockIdx.y * gridDim.x +  blockIdx.x;
  int tid = threadIdx.x + blockId * blockDim.x;
  int step = gridDim.x * blockDim.x;

    //blockIdx.y * step + blockIdx.x * gridDim.x * blockDim.x;
  for (int gid = tid; gid < numElement; gid += step)
    if (gid < numElement)
      bufferout[gid] = logf(bufferin[gid]);
}

__global__ void
OmgLog2_kernel(int numElement, const float *bufferin, float *bufferout)
{
  // TODO make it u24
  int blockId = blockIdx.y * gridDim.x +  blockIdx.x;
  int tid = threadIdx.x + blockId * blockDim.x;
  int step = gridDim.x * blockDim.x;

    //blockIdx.y * step + blockIdx.x * gridDim.x * blockDim.x;
  for (int gid = tid; gid < numElement; gid += step)
    if (gid < numElement)
      bufferout[gid] = log2f(bufferin[gid]);
}

__global__ void
OmgLog10_kernel(int numElement, const float *bufferin, float *bufferout)
{
  // TODO make it u24
  int blockId = blockIdx.y * gridDim.x +  blockIdx.x;
  int tid = threadIdx.x + blockId * blockDim.x;
  int step = gridDim.x * blockDim.x;

    //blockIdx.y * step + blockIdx.x * gridDim.x * blockDim.x;
  for (int gid = tid; gid < numElement; gid += step)
    if (gid < numElement)
      bufferout[gid] = log10f(bufferin[gid]);
}

__global__ void
OmgExp_kernel(int numElement, const float *bufferin, float *bufferout)
{
  // TODO make it u24
  int blockId = blockIdx.y * gridDim.x +  blockIdx.x;
  int tid = threadIdx.x + blockId * blockDim.x;
  int step = gridDim.x * blockDim.x;

    //blockIdx.y * step + blockIdx.x * gridDim.x * blockDim.x;
  for (int gid = tid; gid < numElement; gid += step)
    if (gid < numElement)
      bufferout[gid] = expf(bufferin[gid]);
}

__global__ void
OmgAbs_kernel(int numElement, const float *bufferin, float *bufferout)
{
  // TODO make it u24
  int blockId = blockIdx.y * gridDim.x +  blockIdx.x;
  int tid = threadIdx.x + blockId * blockDim.x;
  int step = gridDim.x * blockDim.x;

    //blockIdx.y * step + blockIdx.x * gridDim.x * blockDim.x;
  for (int gid = tid; gid < numElement; gid += step)
    if (gid < numElement)
      bufferout[gid] = fabsf(bufferin[gid]);
}

__global__ void
OmgFix_kernel(int numElement, const float *bufferin, float *bufferout)
{
  // TODO make it u24
  int blockId = blockIdx.y * gridDim.x +  blockIdx.x;
  int tid = threadIdx.x + blockId * blockDim.x;
  int step = gridDim.x * blockDim.x;

    //blockIdx.y * step + blockIdx.x * gridDim.x * blockDim.x;
  for (int gid = tid; gid < numElement; gid += step)
    if (gid < numElement)
      bufferout[gid] = truncf(bufferin[gid]);
}

__global__ void
OmgCeil_kernel(int numElement, const float *bufferin, float *bufferout)
{
  // TODO make it u24
  int blockId = blockIdx.y * gridDim.x +  blockIdx.x;
  int tid = threadIdx.x + blockId * blockDim.x;
  int step = gridDim.x * blockDim.x;

    //blockIdx.y * step + blockIdx.x * gridDim.x * blockDim.x;
  for (int gid = tid; gid < numElement; gid += step)
    if (gid < numElement)
      bufferout[gid] = ceilf(bufferin[gid]);
}

__global__ void
OmgFloor_kernel(int numElement, const float *bufferin, float *bufferout)
{
  // TODO make it u24
  int blockId = blockIdx.y * gridDim.x +  blockIdx.x;
  int tid = threadIdx.x + blockId * blockDim.x;
  int step = gridDim.x * blockDim.x;

    //blockIdx.y * step + blockIdx.x * gridDim.x * blockDim.x;
  for (int gid = tid; gid < numElement; gid += step)
    if (gid < numElement)
      bufferout[gid] = floorf(bufferin[gid]);
}

__global__ void
OmgRound_kernel(int numElement, const float *bufferin, float *bufferout)
{
  // TODO make it u24
  int blockId = blockIdx.y * gridDim.x +  blockIdx.x;
  int tid = threadIdx.x + blockId * blockDim.x;
  int step = gridDim.x * blockDim.x;

    //blockIdx.y * step + blockIdx.x * gridDim.x * blockDim.x;
  for (int gid = tid; gid < numElement; gid += step)
    if (gid < numElement)
      bufferout[gid] = rintf(bufferin[gid]);
}

	.file	"tmpxft_0037c97b_00000000-6_GpuMathKernel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0, @function
_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0:
.LFB2175:
	.cfi_startproc
	jmp	cudaLaunchKernel@PLT
	.cfi_endproc
.LFE2175:
	.size	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0, .-_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	.globl	_Z37__device_stub__Z13OmgSin_kerneliPKfPfiPKfPf
	.type	_Z37__device_stub__Z13OmgSin_kerneliPKfPfiPKfPf, @function
_Z37__device_stub__Z13OmgSin_kerneliPKfPfiPKfPf:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movl	%edi, 28(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L3
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z13OmgSin_kerneliPKfPf(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L3:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L5
	call	__stack_chk_fail@PLT
.L5:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z37__device_stub__Z13OmgSin_kerneliPKfPfiPKfPf, .-_Z37__device_stub__Z13OmgSin_kerneliPKfPfiPKfPf
	.globl	_Z13OmgSin_kerneliPKfPf
	.type	_Z13OmgSin_kerneliPKfPf, @function
_Z13OmgSin_kerneliPKfPf:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z13OmgSin_kerneliPKfPfiPKfPf
	.cfi_endproc
.LFE2033:
	.size	_Z13OmgSin_kerneliPKfPf, .-_Z13OmgSin_kerneliPKfPf
	.globl	_Z37__device_stub__Z13OmgCos_kerneliPKfPfiPKfPf
	.type	_Z37__device_stub__Z13OmgCos_kerneliPKfPfiPKfPf, @function
_Z37__device_stub__Z13OmgCos_kerneliPKfPfiPKfPf:
.LFB2034:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movl	%edi, 28(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z13OmgCos_kerneliPKfPf(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L9:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L11
	call	__stack_chk_fail@PLT
.L11:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2034:
	.size	_Z37__device_stub__Z13OmgCos_kerneliPKfPfiPKfPf, .-_Z37__device_stub__Z13OmgCos_kerneliPKfPfiPKfPf
	.globl	_Z13OmgCos_kerneliPKfPf
	.type	_Z13OmgCos_kerneliPKfPf, @function
_Z13OmgCos_kerneliPKfPf:
.LFB2035:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z13OmgCos_kerneliPKfPfiPKfPf
	.cfi_endproc
.LFE2035:
	.size	_Z13OmgCos_kerneliPKfPf, .-_Z13OmgCos_kerneliPKfPf
	.globl	_Z37__device_stub__Z13OmgTan_kerneliPKfPfiPKfPf
	.type	_Z37__device_stub__Z13OmgTan_kerneliPKfPfiPKfPf, @function
_Z37__device_stub__Z13OmgTan_kerneliPKfPfiPKfPf:
.LFB2036:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movl	%edi, 28(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L14
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z13OmgTan_kerneliPKfPf(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L14:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L16
	call	__stack_chk_fail@PLT
.L16:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2036:
	.size	_Z37__device_stub__Z13OmgTan_kerneliPKfPfiPKfPf, .-_Z37__device_stub__Z13OmgTan_kerneliPKfPfiPKfPf
	.globl	_Z13OmgTan_kerneliPKfPf
	.type	_Z13OmgTan_kerneliPKfPf, @function
_Z13OmgTan_kerneliPKfPf:
.LFB2037:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z13OmgTan_kerneliPKfPfiPKfPf
	.cfi_endproc
.LFE2037:
	.size	_Z13OmgTan_kerneliPKfPf, .-_Z13OmgTan_kerneliPKfPf
	.globl	_Z37__device_stub__Z13OmgCot_kerneliPKfPfiPKfPf
	.type	_Z37__device_stub__Z13OmgCot_kerneliPKfPfiPKfPf, @function
_Z37__device_stub__Z13OmgCot_kerneliPKfPfiPKfPf:
.LFB2038:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movl	%edi, 28(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z13OmgCot_kerneliPKfPf(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L19:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L21
	call	__stack_chk_fail@PLT
.L21:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2038:
	.size	_Z37__device_stub__Z13OmgCot_kerneliPKfPfiPKfPf, .-_Z37__device_stub__Z13OmgCot_kerneliPKfPfiPKfPf
	.globl	_Z13OmgCot_kerneliPKfPf
	.type	_Z13OmgCot_kerneliPKfPf, @function
_Z13OmgCot_kerneliPKfPf:
.LFB2039:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z13OmgCot_kerneliPKfPfiPKfPf
	.cfi_endproc
.LFE2039:
	.size	_Z13OmgCot_kerneliPKfPf, .-_Z13OmgCot_kerneliPKfPf
	.globl	_Z37__device_stub__Z13OmgLog_kerneliPKfPfiPKfPf
	.type	_Z37__device_stub__Z13OmgLog_kerneliPKfPfiPKfPf, @function
_Z37__device_stub__Z13OmgLog_kerneliPKfPfiPKfPf:
.LFB2040:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movl	%edi, 28(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z13OmgLog_kerneliPKfPf(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L24:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L26
	call	__stack_chk_fail@PLT
.L26:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2040:
	.size	_Z37__device_stub__Z13OmgLog_kerneliPKfPfiPKfPf, .-_Z37__device_stub__Z13OmgLog_kerneliPKfPfiPKfPf
	.globl	_Z13OmgLog_kerneliPKfPf
	.type	_Z13OmgLog_kerneliPKfPf, @function
_Z13OmgLog_kerneliPKfPf:
.LFB2041:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z13OmgLog_kerneliPKfPfiPKfPf
	.cfi_endproc
.LFE2041:
	.size	_Z13OmgLog_kerneliPKfPf, .-_Z13OmgLog_kerneliPKfPf
	.globl	_Z38__device_stub__Z14OmgLog2_kerneliPKfPfiPKfPf
	.type	_Z38__device_stub__Z14OmgLog2_kerneliPKfPfiPKfPf, @function
_Z38__device_stub__Z14OmgLog2_kerneliPKfPfiPKfPf:
.LFB2042:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movl	%edi, 28(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L29
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z14OmgLog2_kerneliPKfPf(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L29:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L31
	call	__stack_chk_fail@PLT
.L31:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2042:
	.size	_Z38__device_stub__Z14OmgLog2_kerneliPKfPfiPKfPf, .-_Z38__device_stub__Z14OmgLog2_kerneliPKfPfiPKfPf
	.globl	_Z14OmgLog2_kerneliPKfPf
	.type	_Z14OmgLog2_kerneliPKfPf, @function
_Z14OmgLog2_kerneliPKfPf:
.LFB2043:
	.cfi_startproc
	endbr64
	jmp	_Z38__device_stub__Z14OmgLog2_kerneliPKfPfiPKfPf
	.cfi_endproc
.LFE2043:
	.size	_Z14OmgLog2_kerneliPKfPf, .-_Z14OmgLog2_kerneliPKfPf
	.globl	_Z39__device_stub__Z15OmgLog10_kerneliPKfPfiPKfPf
	.type	_Z39__device_stub__Z15OmgLog10_kerneliPKfPfiPKfPf, @function
_Z39__device_stub__Z15OmgLog10_kerneliPKfPfiPKfPf:
.LFB2044:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movl	%edi, 28(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L34
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z15OmgLog10_kerneliPKfPf(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L34:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L36
	call	__stack_chk_fail@PLT
.L36:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2044:
	.size	_Z39__device_stub__Z15OmgLog10_kerneliPKfPfiPKfPf, .-_Z39__device_stub__Z15OmgLog10_kerneliPKfPfiPKfPf
	.globl	_Z15OmgLog10_kerneliPKfPf
	.type	_Z15OmgLog10_kerneliPKfPf, @function
_Z15OmgLog10_kerneliPKfPf:
.LFB2045:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z15OmgLog10_kerneliPKfPfiPKfPf
	.cfi_endproc
.LFE2045:
	.size	_Z15OmgLog10_kerneliPKfPf, .-_Z15OmgLog10_kerneliPKfPf
	.globl	_Z37__device_stub__Z13OmgExp_kerneliPKfPfiPKfPf
	.type	_Z37__device_stub__Z13OmgExp_kerneliPKfPfiPKfPf, @function
_Z37__device_stub__Z13OmgExp_kerneliPKfPfiPKfPf:
.LFB2046:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movl	%edi, 28(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L39
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z13OmgExp_kerneliPKfPf(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L39:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L41
	call	__stack_chk_fail@PLT
.L41:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2046:
	.size	_Z37__device_stub__Z13OmgExp_kerneliPKfPfiPKfPf, .-_Z37__device_stub__Z13OmgExp_kerneliPKfPfiPKfPf
	.globl	_Z13OmgExp_kerneliPKfPf
	.type	_Z13OmgExp_kerneliPKfPf, @function
_Z13OmgExp_kerneliPKfPf:
.LFB2047:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z13OmgExp_kerneliPKfPfiPKfPf
	.cfi_endproc
.LFE2047:
	.size	_Z13OmgExp_kerneliPKfPf, .-_Z13OmgExp_kerneliPKfPf
	.globl	_Z37__device_stub__Z13OmgAbs_kerneliPKfPfiPKfPf
	.type	_Z37__device_stub__Z13OmgAbs_kerneliPKfPfiPKfPf, @function
_Z37__device_stub__Z13OmgAbs_kerneliPKfPfiPKfPf:
.LFB2048:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movl	%edi, 28(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L44
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z13OmgAbs_kerneliPKfPf(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L44:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L46
	call	__stack_chk_fail@PLT
.L46:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2048:
	.size	_Z37__device_stub__Z13OmgAbs_kerneliPKfPfiPKfPf, .-_Z37__device_stub__Z13OmgAbs_kerneliPKfPfiPKfPf
	.globl	_Z13OmgAbs_kerneliPKfPf
	.type	_Z13OmgAbs_kerneliPKfPf, @function
_Z13OmgAbs_kerneliPKfPf:
.LFB2049:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z13OmgAbs_kerneliPKfPfiPKfPf
	.cfi_endproc
.LFE2049:
	.size	_Z13OmgAbs_kerneliPKfPf, .-_Z13OmgAbs_kerneliPKfPf
	.globl	_Z37__device_stub__Z13OmgFix_kerneliPKfPfiPKfPf
	.type	_Z37__device_stub__Z13OmgFix_kerneliPKfPfiPKfPf, @function
_Z37__device_stub__Z13OmgFix_kerneliPKfPfiPKfPf:
.LFB2050:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movl	%edi, 28(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L49
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z13OmgFix_kerneliPKfPf(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L49:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L51
	call	__stack_chk_fail@PLT
.L51:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2050:
	.size	_Z37__device_stub__Z13OmgFix_kerneliPKfPfiPKfPf, .-_Z37__device_stub__Z13OmgFix_kerneliPKfPfiPKfPf
	.globl	_Z13OmgFix_kerneliPKfPf
	.type	_Z13OmgFix_kerneliPKfPf, @function
_Z13OmgFix_kerneliPKfPf:
.LFB2051:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z13OmgFix_kerneliPKfPfiPKfPf
	.cfi_endproc
.LFE2051:
	.size	_Z13OmgFix_kerneliPKfPf, .-_Z13OmgFix_kerneliPKfPf
	.globl	_Z38__device_stub__Z14OmgCeil_kerneliPKfPfiPKfPf
	.type	_Z38__device_stub__Z14OmgCeil_kerneliPKfPfiPKfPf, @function
_Z38__device_stub__Z14OmgCeil_kerneliPKfPfiPKfPf:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movl	%edi, 28(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L54
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z14OmgCeil_kerneliPKfPf(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L54:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L56
	call	__stack_chk_fail@PLT
.L56:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z38__device_stub__Z14OmgCeil_kerneliPKfPfiPKfPf, .-_Z38__device_stub__Z14OmgCeil_kerneliPKfPfiPKfPf
	.globl	_Z14OmgCeil_kerneliPKfPf
	.type	_Z14OmgCeil_kerneliPKfPf, @function
_Z14OmgCeil_kerneliPKfPf:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z38__device_stub__Z14OmgCeil_kerneliPKfPfiPKfPf
	.cfi_endproc
.LFE2053:
	.size	_Z14OmgCeil_kerneliPKfPf, .-_Z14OmgCeil_kerneliPKfPf
	.globl	_Z39__device_stub__Z15OmgFloor_kerneliPKfPfiPKfPf
	.type	_Z39__device_stub__Z15OmgFloor_kerneliPKfPfiPKfPf, @function
_Z39__device_stub__Z15OmgFloor_kerneliPKfPfiPKfPf:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movl	%edi, 28(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L59
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z15OmgFloor_kerneliPKfPf(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L59:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L61
	call	__stack_chk_fail@PLT
.L61:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z39__device_stub__Z15OmgFloor_kerneliPKfPfiPKfPf, .-_Z39__device_stub__Z15OmgFloor_kerneliPKfPfiPKfPf
	.globl	_Z15OmgFloor_kerneliPKfPf
	.type	_Z15OmgFloor_kerneliPKfPf, @function
_Z15OmgFloor_kerneliPKfPf:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z15OmgFloor_kerneliPKfPfiPKfPf
	.cfi_endproc
.LFE2055:
	.size	_Z15OmgFloor_kerneliPKfPf, .-_Z15OmgFloor_kerneliPKfPf
	.globl	_Z39__device_stub__Z15OmgRound_kerneliPKfPfiPKfPf
	.type	_Z39__device_stub__Z15OmgRound_kerneliPKfPfiPKfPf, @function
_Z39__device_stub__Z15OmgRound_kerneliPKfPfiPKfPf:
.LFB2056:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movl	%edi, 28(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 80(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 88(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L64
	pushq	48(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z15OmgRound_kerneliPKfPf(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 144
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	96(%rsp), %r9
	call	_Z16cudaLaunchKernelIcE9cudaErrorPT_4dim3S3_PPvmP11CUstream_st.isra.0
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L64:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L66
	call	__stack_chk_fail@PLT
.L66:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_Z39__device_stub__Z15OmgRound_kerneliPKfPfiPKfPf, .-_Z39__device_stub__Z15OmgRound_kerneliPKfPfiPKfPf
	.globl	_Z15OmgRound_kerneliPKfPf
	.type	_Z15OmgRound_kerneliPKfPf, @function
_Z15OmgRound_kerneliPKfPf:
.LFB2057:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z15OmgRound_kerneliPKfPfiPKfPf
	.cfi_endproc
.LFE2057:
	.size	_Z15OmgRound_kerneliPKfPf, .-_Z15OmgRound_kerneliPKfPf
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z15OmgRound_kerneliPKfPf"
.LC1:
	.string	"_Z15OmgFloor_kerneliPKfPf"
.LC2:
	.string	"_Z14OmgCeil_kerneliPKfPf"
.LC3:
	.string	"_Z13OmgFix_kerneliPKfPf"
.LC4:
	.string	"_Z13OmgAbs_kerneliPKfPf"
.LC5:
	.string	"_Z13OmgExp_kerneliPKfPf"
.LC6:
	.string	"_Z15OmgLog10_kerneliPKfPf"
.LC7:
	.string	"_Z14OmgLog2_kerneliPKfPf"
.LC8:
	.string	"_Z13OmgLog_kerneliPKfPf"
.LC9:
	.string	"_Z13OmgCot_kerneliPKfPf"
.LC10:
	.string	"_Z13OmgTan_kerneliPKfPf"
.LC11:
	.string	"_Z13OmgCos_kerneliPKfPf"
.LC12:
	.string	"_Z13OmgSin_kerneliPKfPf"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2059:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z15OmgRound_kerneliPKfPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z15OmgFloor_kerneliPKfPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z14OmgCeil_kerneliPKfPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z13OmgFix_kerneliPKfPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC4(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z13OmgAbs_kerneliPKfPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC5(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z13OmgExp_kerneliPKfPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z15OmgLog10_kerneliPKfPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z14OmgLog2_kerneliPKfPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	leaq	.LC8(%rip), %rdx
	pushq	$0
	.cfi_def_cfa_offset 24
	movq	%rdx, %rcx
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	_Z13OmgLog_kerneliPKfPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC9(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z13OmgCot_kerneliPKfPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC10(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z13OmgTan_kerneliPKfPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC11(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z13OmgCos_kerneliPKfPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC12(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z13OmgSin_kerneliPKfPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2059:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#pragma once
#include <hip/hip_runtime.h>


__global__ void
OmgSin_kernel(int numElement, const float *bufferin, float *bufferout)
{
  // TODO make it u24
  int blockId = blockIdx.y * gridDim.x +  blockIdx.x;
  int tid = threadIdx.x + blockId * blockDim.x;
  int step = gridDim.x * blockDim.x;

    //blockIdx.y * step + blockIdx.x * gridDim.x * blockDim.x;
  for (int gid = tid; gid < numElement; gid += step)
    if (gid < numElement)
      bufferout[gid] = sinf(bufferin[gid]);
}


__global__ void
OmgCos_kernel(int numElement, const float *bufferin, float *bufferout)
{
  // TODO make it u24
  int blockId = blockIdx.y * gridDim.x +  blockIdx.x;
  int tid = threadIdx.x + blockId * blockDim.x;
  int step = gridDim.x * blockDim.x;

    //blockIdx.y * step + blockIdx.x * gridDim.x * blockDim.x;
  for (int gid = tid; gid < numElement; gid += step)
    if (gid < numElement)
      bufferout[gid] = cosf(bufferin[gid]);
}


__global__ void
OmgTan_kernel(int numElement, const float *bufferin, float *bufferout)
{
  // TODO make it u24
  int blockId = blockIdx.y * gridDim.x +  blockIdx.x;
  int tid = threadIdx.x + blockId * blockDim.x;
  int step = gridDim.x * blockDim.x;

    //blockIdx.y * step + blockIdx.x * gridDim.x * blockDim.x;
  for (int gid = tid; gid < numElement; gid += step)
    if (gid < numElement)
      bufferout[gid] = tanf(bufferin[gid]);
}


__global__ void
OmgCot_kernel(int numElement, const float *bufferin, float *bufferout)
{
  // TODO make it u24
  int blockId = blockIdx.y * gridDim.x +  blockIdx.x;
  int tid = threadIdx.x + blockId * blockDim.x;
  int step = gridDim.x * blockDim.x;

    //blockIdx.y * step + blockIdx.x * gridDim.x * blockDim.x;
  for (int gid = tid; gid < numElement; gid += step)
    if (gid < numElement)
      bufferout[gid] = 1.0f/tanf(bufferin[gid]);
}


__global__ void
OmgLog_kernel(int numElement, const float *bufferin, float *bufferout)
{
  // TODO make it u24
  int blockId = blockIdx.y * gridDim.x +  blockIdx.x;
  int tid = threadIdx.x + blockId * blockDim.x;
  int step = gridDim.x * blockDim.x;

    //blockIdx.y * step + blockIdx.x * gridDim.x * blockDim.x;
  for (int gid = tid; gid < numElement; gid += step)
    if (gid < numElement)
      bufferout[gid] = logf(bufferin[gid]);
}

__global__ void
OmgLog2_kernel(int numElement, const float *bufferin, float *bufferout)
{
  // TODO make it u24
  int blockId = blockIdx.y * gridDim.x +  blockIdx.x;
  int tid = threadIdx.x + blockId * blockDim.x;
  int step = gridDim.x * blockDim.x;

    //blockIdx.y * step + blockIdx.x * gridDim.x * blockDim.x;
  for (int gid = tid; gid < numElement; gid += step)
    if (gid < numElement)
      bufferout[gid] = log2f(bufferin[gid]);
}

__global__ void
OmgLog10_kernel(int numElement, const float *bufferin, float *bufferout)
{
  // TODO make it u24
  int blockId = blockIdx.y * gridDim.x +  blockIdx.x;
  int tid = threadIdx.x + blockId * blockDim.x;
  int step = gridDim.x * blockDim.x;

    //blockIdx.y * step + blockIdx.x * gridDim.x * blockDim.x;
  for (int gid = tid; gid < numElement; gid += step)
    if (gid < numElement)
      bufferout[gid] = log10f(bufferin[gid]);
}

__global__ void
OmgExp_kernel(int numElement, const float *bufferin, float *bufferout)
{
  // TODO make it u24
  int blockId = blockIdx.y * gridDim.x +  blockIdx.x;
  int tid = threadIdx.x + blockId * blockDim.x;
  int step = gridDim.x * blockDim.x;

    //blockIdx.y * step + blockIdx.x * gridDim.x * blockDim.x;
  for (int gid = tid; gid < numElement; gid += step)
    if (gid < numElement)
      bufferout[gid] = expf(bufferin[gid]);
}

__global__ void
OmgAbs_kernel(int numElement, const float *bufferin, float *bufferout)
{
  // TODO make it u24
  int blockId = blockIdx.y * gridDim.x +  blockIdx.x;
  int tid = threadIdx.x + blockId * blockDim.x;
  int step = gridDim.x * blockDim.x;

    //blockIdx.y * step + blockIdx.x * gridDim.x * blockDim.x;
  for (int gid = tid; gid < numElement; gid += step)
    if (gid < numElement)
      bufferout[gid] = fabsf(bufferin[gid]);
}

__global__ void
OmgFix_kernel(int numElement, const float *bufferin, float *bufferout)
{
  // TODO make it u24
  int blockId = blockIdx.y * gridDim.x +  blockIdx.x;
  int tid = threadIdx.x + blockId * blockDim.x;
  int step = gridDim.x * blockDim.x;

    //blockIdx.y * step + blockIdx.x * gridDim.x * blockDim.x;
  for (int gid = tid; gid < numElement; gid += step)
    if (gid < numElement)
      bufferout[gid] = truncf(bufferin[gid]);
}

__global__ void
OmgCeil_kernel(int numElement, const float *bufferin, float *bufferout)
{
  // TODO make it u24
  int blockId = blockIdx.y * gridDim.x +  blockIdx.x;
  int tid = threadIdx.x + blockId * blockDim.x;
  int step = gridDim.x * blockDim.x;

    //blockIdx.y * step + blockIdx.x * gridDim.x * blockDim.x;
  for (int gid = tid; gid < numElement; gid += step)
    if (gid < numElement)
      bufferout[gid] = ceilf(bufferin[gid]);
}

__global__ void
OmgFloor_kernel(int numElement, const float *bufferin, float *bufferout)
{
  // TODO make it u24
  int blockId = blockIdx.y * gridDim.x +  blockIdx.x;
  int tid = threadIdx.x + blockId * blockDim.x;
  int step = gridDim.x * blockDim.x;

    //blockIdx.y * step + blockIdx.x * gridDim.x * blockDim.x;
  for (int gid = tid; gid < numElement; gid += step)
    if (gid < numElement)
      bufferout[gid] = floorf(bufferin[gid]);
}

__global__ void
OmgRound_kernel(int numElement, const float *bufferin, float *bufferout)
{
  // TODO make it u24
  int blockId = blockIdx.y * gridDim.x +  blockIdx.x;
  int tid = threadIdx.x + blockId * blockDim.x;
  int step = gridDim.x * blockDim.x;

    //blockIdx.y * step + blockIdx.x * gridDim.x * blockDim.x;
  for (int gid = tid; gid < numElement; gid += step)
    if (gid < numElement)
      bufferout[gid] = rintf(bufferin[gid]);
}

	.text
	.file	"GpuMathKernel.hip"
	.globl	_Z28__device_stub__OmgSin_kerneliPKfPf # -- Begin function _Z28__device_stub__OmgSin_kerneliPKfPf
	.type	_Z28__device_stub__OmgSin_kerneliPKfPf,@function
_Z28__device_stub__OmgSin_kerneliPKfPf: # @_Z28__device_stub__OmgSin_kerneliPKfPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13OmgSin_kerneliPKfPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z28__device_stub__OmgSin_kerneliPKfPf, .Lfunc_end0-_Z28__device_stub__OmgSin_kerneliPKfPf
	.cfi_endproc
                                        # -- End function
	.globl	_Z28__device_stub__OmgCos_kerneliPKfPf # -- Begin function _Z28__device_stub__OmgCos_kerneliPKfPf
	.type	_Z28__device_stub__OmgCos_kerneliPKfPf,@function
_Z28__device_stub__OmgCos_kerneliPKfPf: # @_Z28__device_stub__OmgCos_kerneliPKfPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13OmgCos_kerneliPKfPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z28__device_stub__OmgCos_kerneliPKfPf, .Lfunc_end1-_Z28__device_stub__OmgCos_kerneliPKfPf
	.cfi_endproc
                                        # -- End function
	.globl	_Z28__device_stub__OmgTan_kerneliPKfPf # -- Begin function _Z28__device_stub__OmgTan_kerneliPKfPf
	.type	_Z28__device_stub__OmgTan_kerneliPKfPf,@function
_Z28__device_stub__OmgTan_kerneliPKfPf: # @_Z28__device_stub__OmgTan_kerneliPKfPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13OmgTan_kerneliPKfPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z28__device_stub__OmgTan_kerneliPKfPf, .Lfunc_end2-_Z28__device_stub__OmgTan_kerneliPKfPf
	.cfi_endproc
                                        # -- End function
	.globl	_Z28__device_stub__OmgCot_kerneliPKfPf # -- Begin function _Z28__device_stub__OmgCot_kerneliPKfPf
	.type	_Z28__device_stub__OmgCot_kerneliPKfPf,@function
_Z28__device_stub__OmgCot_kerneliPKfPf: # @_Z28__device_stub__OmgCot_kerneliPKfPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13OmgCot_kerneliPKfPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z28__device_stub__OmgCot_kerneliPKfPf, .Lfunc_end3-_Z28__device_stub__OmgCot_kerneliPKfPf
	.cfi_endproc
                                        # -- End function
	.globl	_Z28__device_stub__OmgLog_kerneliPKfPf # -- Begin function _Z28__device_stub__OmgLog_kerneliPKfPf
	.type	_Z28__device_stub__OmgLog_kerneliPKfPf,@function
_Z28__device_stub__OmgLog_kerneliPKfPf: # @_Z28__device_stub__OmgLog_kerneliPKfPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13OmgLog_kerneliPKfPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z28__device_stub__OmgLog_kerneliPKfPf, .Lfunc_end4-_Z28__device_stub__OmgLog_kerneliPKfPf
	.cfi_endproc
                                        # -- End function
	.globl	_Z29__device_stub__OmgLog2_kerneliPKfPf # -- Begin function _Z29__device_stub__OmgLog2_kerneliPKfPf
	.type	_Z29__device_stub__OmgLog2_kerneliPKfPf,@function
_Z29__device_stub__OmgLog2_kerneliPKfPf: # @_Z29__device_stub__OmgLog2_kerneliPKfPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14OmgLog2_kerneliPKfPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z29__device_stub__OmgLog2_kerneliPKfPf, .Lfunc_end5-_Z29__device_stub__OmgLog2_kerneliPKfPf
	.cfi_endproc
                                        # -- End function
	.globl	_Z30__device_stub__OmgLog10_kerneliPKfPf # -- Begin function _Z30__device_stub__OmgLog10_kerneliPKfPf
	.type	_Z30__device_stub__OmgLog10_kerneliPKfPf,@function
_Z30__device_stub__OmgLog10_kerneliPKfPf: # @_Z30__device_stub__OmgLog10_kerneliPKfPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15OmgLog10_kerneliPKfPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z30__device_stub__OmgLog10_kerneliPKfPf, .Lfunc_end6-_Z30__device_stub__OmgLog10_kerneliPKfPf
	.cfi_endproc
                                        # -- End function
	.globl	_Z28__device_stub__OmgExp_kerneliPKfPf # -- Begin function _Z28__device_stub__OmgExp_kerneliPKfPf
	.type	_Z28__device_stub__OmgExp_kerneliPKfPf,@function
_Z28__device_stub__OmgExp_kerneliPKfPf: # @_Z28__device_stub__OmgExp_kerneliPKfPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13OmgExp_kerneliPKfPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_Z28__device_stub__OmgExp_kerneliPKfPf, .Lfunc_end7-_Z28__device_stub__OmgExp_kerneliPKfPf
	.cfi_endproc
                                        # -- End function
	.globl	_Z28__device_stub__OmgAbs_kerneliPKfPf # -- Begin function _Z28__device_stub__OmgAbs_kerneliPKfPf
	.type	_Z28__device_stub__OmgAbs_kerneliPKfPf,@function
_Z28__device_stub__OmgAbs_kerneliPKfPf: # @_Z28__device_stub__OmgAbs_kerneliPKfPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13OmgAbs_kerneliPKfPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end8:
	.size	_Z28__device_stub__OmgAbs_kerneliPKfPf, .Lfunc_end8-_Z28__device_stub__OmgAbs_kerneliPKfPf
	.cfi_endproc
                                        # -- End function
	.globl	_Z28__device_stub__OmgFix_kerneliPKfPf # -- Begin function _Z28__device_stub__OmgFix_kerneliPKfPf
	.type	_Z28__device_stub__OmgFix_kerneliPKfPf,@function
_Z28__device_stub__OmgFix_kerneliPKfPf: # @_Z28__device_stub__OmgFix_kerneliPKfPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13OmgFix_kerneliPKfPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end9:
	.size	_Z28__device_stub__OmgFix_kerneliPKfPf, .Lfunc_end9-_Z28__device_stub__OmgFix_kerneliPKfPf
	.cfi_endproc
                                        # -- End function
	.globl	_Z29__device_stub__OmgCeil_kerneliPKfPf # -- Begin function _Z29__device_stub__OmgCeil_kerneliPKfPf
	.type	_Z29__device_stub__OmgCeil_kerneliPKfPf,@function
_Z29__device_stub__OmgCeil_kerneliPKfPf: # @_Z29__device_stub__OmgCeil_kerneliPKfPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14OmgCeil_kerneliPKfPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end10:
	.size	_Z29__device_stub__OmgCeil_kerneliPKfPf, .Lfunc_end10-_Z29__device_stub__OmgCeil_kerneliPKfPf
	.cfi_endproc
                                        # -- End function
	.globl	_Z30__device_stub__OmgFloor_kerneliPKfPf # -- Begin function _Z30__device_stub__OmgFloor_kerneliPKfPf
	.type	_Z30__device_stub__OmgFloor_kerneliPKfPf,@function
_Z30__device_stub__OmgFloor_kerneliPKfPf: # @_Z30__device_stub__OmgFloor_kerneliPKfPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15OmgFloor_kerneliPKfPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end11:
	.size	_Z30__device_stub__OmgFloor_kerneliPKfPf, .Lfunc_end11-_Z30__device_stub__OmgFloor_kerneliPKfPf
	.cfi_endproc
                                        # -- End function
	.globl	_Z30__device_stub__OmgRound_kerneliPKfPf # -- Begin function _Z30__device_stub__OmgRound_kerneliPKfPf
	.type	_Z30__device_stub__OmgRound_kerneliPKfPf,@function
_Z30__device_stub__OmgRound_kerneliPKfPf: # @_Z30__device_stub__OmgRound_kerneliPKfPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15OmgRound_kerneliPKfPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end12:
	.size	_Z30__device_stub__OmgRound_kerneliPKfPf, .Lfunc_end12-_Z30__device_stub__OmgRound_kerneliPKfPf
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB13_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB13_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13OmgSin_kerneliPKfPf, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13OmgCos_kerneliPKfPf, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13OmgTan_kerneliPKfPf, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13OmgCot_kerneliPKfPf, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13OmgLog_kerneliPKfPf, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14OmgLog2_kerneliPKfPf, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15OmgLog10_kerneliPKfPf, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13OmgExp_kerneliPKfPf, %esi
	movl	$.L__unnamed_8, %edx
	movl	$.L__unnamed_8, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13OmgAbs_kerneliPKfPf, %esi
	movl	$.L__unnamed_9, %edx
	movl	$.L__unnamed_9, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13OmgFix_kerneliPKfPf, %esi
	movl	$.L__unnamed_10, %edx
	movl	$.L__unnamed_10, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14OmgCeil_kerneliPKfPf, %esi
	movl	$.L__unnamed_11, %edx
	movl	$.L__unnamed_11, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15OmgFloor_kerneliPKfPf, %esi
	movl	$.L__unnamed_12, %edx
	movl	$.L__unnamed_12, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15OmgRound_kerneliPKfPf, %esi
	movl	$.L__unnamed_13, %edx
	movl	$.L__unnamed_13, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end13:
	.size	__hip_module_ctor, .Lfunc_end13-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB14_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB14_2:
	retq
.Lfunc_end14:
	.size	__hip_module_dtor, .Lfunc_end14-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z13OmgSin_kerneliPKfPf,@object # @_Z13OmgSin_kerneliPKfPf
	.section	.rodata,"a",@progbits
	.globl	_Z13OmgSin_kerneliPKfPf
	.p2align	3, 0x0
_Z13OmgSin_kerneliPKfPf:
	.quad	_Z28__device_stub__OmgSin_kerneliPKfPf
	.size	_Z13OmgSin_kerneliPKfPf, 8

	.type	_Z13OmgCos_kerneliPKfPf,@object # @_Z13OmgCos_kerneliPKfPf
	.globl	_Z13OmgCos_kerneliPKfPf
	.p2align	3, 0x0
_Z13OmgCos_kerneliPKfPf:
	.quad	_Z28__device_stub__OmgCos_kerneliPKfPf
	.size	_Z13OmgCos_kerneliPKfPf, 8

	.type	_Z13OmgTan_kerneliPKfPf,@object # @_Z13OmgTan_kerneliPKfPf
	.globl	_Z13OmgTan_kerneliPKfPf
	.p2align	3, 0x0
_Z13OmgTan_kerneliPKfPf:
	.quad	_Z28__device_stub__OmgTan_kerneliPKfPf
	.size	_Z13OmgTan_kerneliPKfPf, 8

	.type	_Z13OmgCot_kerneliPKfPf,@object # @_Z13OmgCot_kerneliPKfPf
	.globl	_Z13OmgCot_kerneliPKfPf
	.p2align	3, 0x0
_Z13OmgCot_kerneliPKfPf:
	.quad	_Z28__device_stub__OmgCot_kerneliPKfPf
	.size	_Z13OmgCot_kerneliPKfPf, 8

	.type	_Z13OmgLog_kerneliPKfPf,@object # @_Z13OmgLog_kerneliPKfPf
	.globl	_Z13OmgLog_kerneliPKfPf
	.p2align	3, 0x0
_Z13OmgLog_kerneliPKfPf:
	.quad	_Z28__device_stub__OmgLog_kerneliPKfPf
	.size	_Z13OmgLog_kerneliPKfPf, 8

	.type	_Z14OmgLog2_kerneliPKfPf,@object # @_Z14OmgLog2_kerneliPKfPf
	.globl	_Z14OmgLog2_kerneliPKfPf
	.p2align	3, 0x0
_Z14OmgLog2_kerneliPKfPf:
	.quad	_Z29__device_stub__OmgLog2_kerneliPKfPf
	.size	_Z14OmgLog2_kerneliPKfPf, 8

	.type	_Z15OmgLog10_kerneliPKfPf,@object # @_Z15OmgLog10_kerneliPKfPf
	.globl	_Z15OmgLog10_kerneliPKfPf
	.p2align	3, 0x0
_Z15OmgLog10_kerneliPKfPf:
	.quad	_Z30__device_stub__OmgLog10_kerneliPKfPf
	.size	_Z15OmgLog10_kerneliPKfPf, 8

	.type	_Z13OmgExp_kerneliPKfPf,@object # @_Z13OmgExp_kerneliPKfPf
	.globl	_Z13OmgExp_kerneliPKfPf
	.p2align	3, 0x0
_Z13OmgExp_kerneliPKfPf:
	.quad	_Z28__device_stub__OmgExp_kerneliPKfPf
	.size	_Z13OmgExp_kerneliPKfPf, 8

	.type	_Z13OmgAbs_kerneliPKfPf,@object # @_Z13OmgAbs_kerneliPKfPf
	.globl	_Z13OmgAbs_kerneliPKfPf
	.p2align	3, 0x0
_Z13OmgAbs_kerneliPKfPf:
	.quad	_Z28__device_stub__OmgAbs_kerneliPKfPf
	.size	_Z13OmgAbs_kerneliPKfPf, 8

	.type	_Z13OmgFix_kerneliPKfPf,@object # @_Z13OmgFix_kerneliPKfPf
	.globl	_Z13OmgFix_kerneliPKfPf
	.p2align	3, 0x0
_Z13OmgFix_kerneliPKfPf:
	.quad	_Z28__device_stub__OmgFix_kerneliPKfPf
	.size	_Z13OmgFix_kerneliPKfPf, 8

	.type	_Z14OmgCeil_kerneliPKfPf,@object # @_Z14OmgCeil_kerneliPKfPf
	.globl	_Z14OmgCeil_kerneliPKfPf
	.p2align	3, 0x0
_Z14OmgCeil_kerneliPKfPf:
	.quad	_Z29__device_stub__OmgCeil_kerneliPKfPf
	.size	_Z14OmgCeil_kerneliPKfPf, 8

	.type	_Z15OmgFloor_kerneliPKfPf,@object # @_Z15OmgFloor_kerneliPKfPf
	.globl	_Z15OmgFloor_kerneliPKfPf
	.p2align	3, 0x0
_Z15OmgFloor_kerneliPKfPf:
	.quad	_Z30__device_stub__OmgFloor_kerneliPKfPf
	.size	_Z15OmgFloor_kerneliPKfPf, 8

	.type	_Z15OmgRound_kerneliPKfPf,@object # @_Z15OmgRound_kerneliPKfPf
	.globl	_Z15OmgRound_kerneliPKfPf
	.p2align	3, 0x0
_Z15OmgRound_kerneliPKfPf:
	.quad	_Z30__device_stub__OmgRound_kerneliPKfPf
	.size	_Z15OmgRound_kerneliPKfPf, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z13OmgSin_kerneliPKfPf"
	.size	.L__unnamed_1, 24

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z13OmgCos_kerneliPKfPf"
	.size	.L__unnamed_2, 24

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z13OmgTan_kerneliPKfPf"
	.size	.L__unnamed_3, 24

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z13OmgCot_kerneliPKfPf"
	.size	.L__unnamed_4, 24

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z13OmgLog_kerneliPKfPf"
	.size	.L__unnamed_5, 24

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_Z14OmgLog2_kerneliPKfPf"
	.size	.L__unnamed_6, 25

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"_Z15OmgLog10_kerneliPKfPf"
	.size	.L__unnamed_7, 26

	.type	.L__unnamed_8,@object           # @7
.L__unnamed_8:
	.asciz	"_Z13OmgExp_kerneliPKfPf"
	.size	.L__unnamed_8, 24

	.type	.L__unnamed_9,@object           # @8
.L__unnamed_9:
	.asciz	"_Z13OmgAbs_kerneliPKfPf"
	.size	.L__unnamed_9, 24

	.type	.L__unnamed_10,@object          # @9
.L__unnamed_10:
	.asciz	"_Z13OmgFix_kerneliPKfPf"
	.size	.L__unnamed_10, 24

	.type	.L__unnamed_11,@object          # @10
.L__unnamed_11:
	.asciz	"_Z14OmgCeil_kerneliPKfPf"
	.size	.L__unnamed_11, 25

	.type	.L__unnamed_12,@object          # @11
.L__unnamed_12:
	.asciz	"_Z15OmgFloor_kerneliPKfPf"
	.size	.L__unnamed_12, 26

	.type	.L__unnamed_13,@object          # @12
.L__unnamed_13:
	.asciz	"_Z15OmgRound_kerneliPKfPf"
	.size	.L__unnamed_13, 26

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z28__device_stub__OmgSin_kerneliPKfPf
	.addrsig_sym _Z28__device_stub__OmgCos_kerneliPKfPf
	.addrsig_sym _Z28__device_stub__OmgTan_kerneliPKfPf
	.addrsig_sym _Z28__device_stub__OmgCot_kerneliPKfPf
	.addrsig_sym _Z28__device_stub__OmgLog_kerneliPKfPf
	.addrsig_sym _Z29__device_stub__OmgLog2_kerneliPKfPf
	.addrsig_sym _Z30__device_stub__OmgLog10_kerneliPKfPf
	.addrsig_sym _Z28__device_stub__OmgExp_kerneliPKfPf
	.addrsig_sym _Z28__device_stub__OmgAbs_kerneliPKfPf
	.addrsig_sym _Z28__device_stub__OmgFix_kerneliPKfPf
	.addrsig_sym _Z29__device_stub__OmgCeil_kerneliPKfPf
	.addrsig_sym _Z30__device_stub__OmgFloor_kerneliPKfPf
	.addrsig_sym _Z30__device_stub__OmgRound_kerneliPKfPf
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z13OmgSin_kerneliPKfPf
	.addrsig_sym _Z13OmgCos_kerneliPKfPf
	.addrsig_sym _Z13OmgTan_kerneliPKfPf
	.addrsig_sym _Z13OmgCot_kerneliPKfPf
	.addrsig_sym _Z13OmgLog_kerneliPKfPf
	.addrsig_sym _Z14OmgLog2_kerneliPKfPf
	.addrsig_sym _Z15OmgLog10_kerneliPKfPf
	.addrsig_sym _Z13OmgExp_kerneliPKfPf
	.addrsig_sym _Z13OmgAbs_kerneliPKfPf
	.addrsig_sym _Z13OmgFix_kerneliPKfPf
	.addrsig_sym _Z14OmgCeil_kerneliPKfPf
	.addrsig_sym _Z15OmgFloor_kerneliPKfPf
	.addrsig_sym _Z15OmgRound_kerneliPKfPf
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z13OmgSin_kerneliPKfPf ; -- Begin function _Z13OmgSin_kerneliPKfPf
	.globl	_Z13OmgSin_kerneliPKfPf
	.p2align	8
	.type	_Z13OmgSin_kerneliPKfPf,@function
_Z13OmgSin_kerneliPKfPf:                ; @_Z13OmgSin_kerneliPKfPf
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x18
	s_load_b32 s3, s[0:1], 0x24
	s_load_b32 s10, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s4, s2, s15
	s_and_b32 s3, s3, 0xffff
	s_add_i32 s4, s4, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s4, s3, v[0:1]
	s_mov_b32 s4, exec_lo
	v_cmpx_gt_i32_e64 s10, v1
	s_cbranch_execz .LBB0_7
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b128 s[4:7], s[0:1], 0x8
	v_ashrrev_i32_e32 v2, 31, v1
	s_mul_i32 s2, s2, s3
	v_mov_b32_e32 v5, 0
	s_ashr_i32 s3, s2, 31
	s_mov_b32 s11, 0x7fffff
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_lshl_b64 s[8:9], s[2:3], 2
	s_mov_b32 s3, 0
	s_mov_b32 s12, 0xb94c1982
	s_mov_b32 s13, 0x37d75334
.LBB0_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v6, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
                                        ; implicit-def: $vgpr4
	s_mov_b32 s1, exec_lo
	global_load_b32 v0, v[6:7], off
                                        ; implicit-def: $vgpr7
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v6, 0x7fffffff, v0
	v_cmpx_ngt_f32_e64 0x48000000, |v0|
	s_xor_b32 s14, exec_lo, s1
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_and_or_b32 v15, v6, s11, 0x800000
	v_lshrrev_b32_e32 v12, 23, v6
	v_mad_u64_u32 v[7:8], null, 0xfe5163ab, v15, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v13, 0xffffff88, v12
	v_cmp_lt_u32_e32 vcc_lo, 63, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v4, v8
	v_cndmask_b32_e64 v14, 0, 0xffffffc0, vcc_lo
	v_mad_u64_u32 v[8:9], null, 0x3c439041, v15, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v14, v14, v13
	v_mov_b32_e32 v4, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s0, 31, v14
	v_mad_u64_u32 v[9:10], null, 0xdb629599, v15, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v16, 0, 0xffffffe0, s0
	v_add_nc_u32_e32 v16, v16, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v4, v10 :: v_dual_cndmask_b32 v7, v9, v7
	v_cmp_lt_u32_e64 s1, 31, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[10:11], null, 0xf534ddc0, v15, v[4:5]
	v_mov_b32_e32 v4, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v8, v10, v8, vcc_lo
	v_mad_u64_u32 v[11:12], null, 0xfc2757d1, v15, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v7, v8, v7, s0
	v_mov_b32_e32 v4, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[12:13], null, 0x4e441529, v15, v[4:5]
	v_mov_b32_e32 v4, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[13:14], null, 0xa2f9836e, v15, v[4:5]
	v_cndmask_b32_e64 v4, 0, 0xffffffe0, s1
	v_cndmask_b32_e32 v15, v12, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v13, v13, v11 :: v_dual_add_nc_u32 v4, v4, v16
	v_dual_cndmask_b32 v12, v14, v12 :: v_dual_cndmask_b32 v11, v11, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v14, 32, v4
	v_cndmask_b32_e64 v10, v13, v15, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v12, v12, v13, s0
	v_cndmask_b32_e64 v13, v15, v11, s0
	v_cndmask_b32_e64 v11, v11, v8, s0
	v_cmp_eq_u32_e32 vcc_lo, 0, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v12, v12, v10, s1
	v_cndmask_b32_e64 v10, v10, v13, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v13, v13, v11, s1
	v_cndmask_b32_e64 v7, v11, v7, s1
	v_alignbit_b32 v15, v12, v10, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v9, v10, v13, v14
	v_cndmask_b32_e32 v4, v15, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v8, v9, v10, vcc_lo
	v_alignbit_b32 v12, v13, v7, v14
	v_bfe_u32 v9, v4, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v10, v4, v8, 30
	v_cndmask_b32_e32 v12, v12, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v11, 0, v9
	v_alignbit_b32 v8, v8, v12, 30
	v_alignbit_b32 v7, v12, v7, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v10, v10, v11
	v_xor_b32_e32 v8, v8, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v7, v7, v11
	v_lshrrev_b32_e32 v11, 29, v4
	v_clz_i32_u32_e32 v13, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v11, 31, v11
	v_min_u32_e32 v13, 32, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v14, 0.5, v11
	v_sub_nc_u32_e32 v12, 31, v13
	v_lshlrev_b32_e32 v15, 23, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v10, v10, v8, v12
	v_alignbit_b32 v7, v8, v7, v12
	v_sub_nc_u32_e32 v14, v14, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v8, v10, v7, 9
	v_lshrrev_b32_e32 v10, 9, v10
	v_clz_i32_u32_e32 v12, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v12, 32, v12
	v_sub_nc_u32_e32 v16, 31, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_alignbit_b32 v7, v8, v7, v16
	v_or_b32_e32 v8, v10, v14
	v_add_lshl_u32 v10, v12, v13, 23
	v_lshrrev_b32_e32 v7, 9, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v12, 0x3fc90fda, v8
	v_sub_nc_u32_e32 v7, v7, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v10, 0x3fc90fda, v8, -v12
	v_add_nc_u32_e32 v7, 0x33000000, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v10, 0x33a22168, v8
	v_or_b32_e32 v7, v7, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v10, 0x3fc90fda, v7
	v_lshrrev_b32_e32 v7, 30, v4
	v_dual_add_f32 v4, v12, v10 :: v_dual_add_nc_u32 v7, v9, v7
.LBB0_4:                                ; %Flow
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s0, s14
; %bb.5:                                ;   in Loop: Header=BB0_2 Depth=1
	v_mul_f32_e64 v4, 0x3f22f983, |v0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v7, v4
	v_fma_f32 v4, 0xbfc90fda, v7, |v0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, 0xb3a22168, v7
	v_fmac_f32_e32 v4, 0xa7c234c4, v7
	v_cvt_i32_f32_e32 v7, v7
; %bb.6:                                ; %_ZL4sinff.exit
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_dual_mul_f32 v8, v4, v4 :: v_dual_and_b32 v11, 1, v7
	v_xor_b32_e32 v6, v6, v0
	v_cmp_class_f32_e64 s0, v0, 0x1f8
	v_lshlrev_b32_e32 v7, 30, v7
	v_fmaak_f32 v9, s12, v8, 0x3c0881c4
	v_cmp_eq_u32_e32 vcc_lo, 0, v11
	v_add_nc_u32_e32 v1, s2, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_and_b32_e32 v7, 0x80000000, v7
	v_fmaak_f32 v9, v8, v9, 0xbe2aaa9d
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v10, s13, v8, 0xbab64f3b :: v_dual_mul_f32 v9, v8, v9
	v_fmaak_f32 v10, v8, v10, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v4, v4, v9
	v_fmaak_f32 v10, v8, v10, 0xbf000004
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v8, v8, v10, 1.0
	v_cndmask_b32_e32 v4, v8, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_xor3_b32 v4, v6, v7, v4
	v_add_co_u32 v6, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
	v_cmp_le_i32_e32 vcc_lo, s10, v1
	v_cndmask_b32_e64 v0, 0x7fc00000, v4, s0
	v_add_co_u32 v2, s0, v2, s8
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v3, s0, s9, v3, s0
	s_or_b32 s3, vcc_lo, s3
	global_store_b32 v[6:7], v0, off
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB0_2
.LBB0_7:                                ; %Flow25
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13OmgSin_kerneliPKfPf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 17
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z13OmgSin_kerneliPKfPf, .Lfunc_end0-_Z13OmgSin_kerneliPKfPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1160
; NumSgprs: 18
; NumVgprs: 17
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 17
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z13OmgCos_kerneliPKfPf ; -- Begin function _Z13OmgCos_kerneliPKfPf
	.globl	_Z13OmgCos_kerneliPKfPf
	.p2align	8
	.type	_Z13OmgCos_kerneliPKfPf,@function
_Z13OmgCos_kerneliPKfPf:                ; @_Z13OmgCos_kerneliPKfPf
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x18
	s_load_b32 s3, s[0:1], 0x24
	s_load_b32 s10, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s4, s2, s15
	s_and_b32 s3, s3, 0xffff
	s_add_i32 s4, s4, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s4, s3, v[0:1]
	s_mov_b32 s4, exec_lo
	v_cmpx_gt_i32_e64 s10, v1
	s_cbranch_execz .LBB1_7
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b128 s[4:7], s[0:1], 0x8
	v_ashrrev_i32_e32 v2, 31, v1
	s_mul_i32 s2, s2, s3
	v_mov_b32_e32 v5, 0
	s_ashr_i32 s3, s2, 31
	s_mov_b32 s11, 0x7fffff
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_lshl_b64 s[8:9], s[2:3], 2
	s_mov_b32 s3, 0
	s_mov_b32 s12, 0xb94c1982
	s_mov_b32 s13, 0x37d75334
.LBB1_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v6, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
                                        ; implicit-def: $vgpr4
	s_mov_b32 s1, exec_lo
	global_load_b32 v0, v[6:7], off
                                        ; implicit-def: $vgpr6
	s_waitcnt vmcnt(0)
	v_cmpx_ngt_f32_e64 0x48000000, |v0|
	s_xor_b32 s14, exec_lo, s1
	s_cbranch_execz .LBB1_4
; %bb.3:                                ;   in Loop: Header=BB1_2 Depth=1
	v_and_b32_e32 v11, 0x7fffffff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_or_b32 v14, v11, s11, 0x800000
	v_mad_u64_u32 v[6:7], null, 0xfe5163ab, v14, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v4, v7
	v_lshrrev_b32_e32 v11, 23, v11
	v_mad_u64_u32 v[7:8], null, 0x3c439041, v14, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v12, 0xffffff88, v11
	v_cmp_lt_u32_e32 vcc_lo, 63, v12
	v_cndmask_b32_e64 v13, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v8 :: v_dual_add_nc_u32 v13, v13, v12
	v_mad_u64_u32 v[8:9], null, 0xdb629599, v14, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s0, 31, v13
	v_cndmask_b32_e32 v6, v8, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v15, 0, 0xffffffe0, s0
	v_dual_mov_b32 v4, v9 :: v_dual_add_nc_u32 v15, v15, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[9:10], null, 0xf534ddc0, v14, v[4:5]
	v_cmp_lt_u32_e64 s1, 31, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v4, v10 :: v_dual_cndmask_b32 v7, v9, v7
	v_mad_u64_u32 v[10:11], null, 0xfc2757d1, v14, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v6, v7, v6, s0
	v_mov_b32_e32 v4, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[11:12], null, 0x4e441529, v14, v[4:5]
	v_mov_b32_e32 v4, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[12:13], null, 0xa2f9836e, v14, v[4:5]
	v_cndmask_b32_e64 v4, 0, 0xffffffe0, s1
	v_cndmask_b32_e32 v14, v11, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v4, v4, v15
	v_dual_cndmask_b32 v12, v12, v10 :: v_dual_cndmask_b32 v11, v13, v11
	v_cndmask_b32_e32 v10, v10, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v13, 32, v4
	v_cndmask_b32_e64 v9, v12, v14, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v11, v11, v12, s0
	v_cndmask_b32_e64 v12, v14, v10, s0
	v_cndmask_b32_e64 v10, v10, v7, s0
	v_cmp_eq_u32_e32 vcc_lo, 0, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v11, v11, v9, s1
	v_cndmask_b32_e64 v9, v9, v12, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v12, v12, v10, s1
	v_cndmask_b32_e64 v6, v10, v6, s1
	v_alignbit_b32 v14, v11, v9, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v8, v9, v12, v13
	v_dual_cndmask_b32 v4, v14, v11 :: v_dual_cndmask_b32 v7, v8, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v11, v12, v6, v13
	v_bfe_u32 v8, v4, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v9, v4, v7, 30
	v_cndmask_b32_e32 v11, v11, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v10, 0, v8
	v_alignbit_b32 v7, v7, v11, 30
	v_alignbit_b32 v6, v11, v6, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v9, v9, v10
	v_xor_b32_e32 v7, v7, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v6, v6, v10
	v_lshrrev_b32_e32 v10, 29, v4
	v_clz_i32_u32_e32 v12, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v10, 31, v10
	v_min_u32_e32 v12, 32, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v13, 0.5, v10
	v_sub_nc_u32_e32 v11, 31, v12
	v_lshlrev_b32_e32 v14, 23, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v9, v9, v7, v11
	v_alignbit_b32 v6, v7, v6, v11
	v_sub_nc_u32_e32 v13, v13, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v7, v9, v6, 9
	v_lshrrev_b32_e32 v9, 9, v9
	v_clz_i32_u32_e32 v11, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v11, 32, v11
	v_sub_nc_u32_e32 v15, 31, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_alignbit_b32 v6, v7, v6, v15
	v_or_b32_e32 v7, v9, v13
	v_add_lshl_u32 v9, v11, v12, 23
	v_lshrrev_b32_e32 v6, 9, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v11, 0x3fc90fda, v7
	v_sub_nc_u32_e32 v6, v6, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v9, 0x3fc90fda, v7, -v11
	v_add_nc_u32_e32 v6, 0x33000000, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v9, 0x33a22168, v7
	v_or_b32_e32 v6, v6, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v9, 0x3fc90fda, v6
	v_lshrrev_b32_e32 v6, 30, v4
	v_add_f32_e32 v4, v11, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v6, v8, v6
.LBB1_4:                                ; %Flow
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_and_not1_saveexec_b32 s0, s14
; %bb.5:                                ;   in Loop: Header=BB1_2 Depth=1
	v_mul_f32_e64 v4, 0x3f22f983, |v0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v6, v4
	v_fma_f32 v4, 0xbfc90fda, v6, |v0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, 0xb3a22168, v6
	v_fmac_f32_e32 v4, 0xa7c234c4, v6
	v_cvt_i32_f32_e32 v6, v6
; %bb.6:                                ; %_ZL4cosff.exit
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_dual_mul_f32 v7, v4, v4 :: v_dual_and_b32 v10, 1, v6
	v_cmp_class_f32_e64 s0, v0, 0x1f8
	v_add_nc_u32_e32 v1, s2, v1
	v_lshlrev_b32_e32 v6, 30, v6
	v_fmaak_f32 v8, s12, v7, 0x3c0881c4
	v_cmp_eq_u32_e32 vcc_lo, 0, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_and_b32_e32 v6, 0x80000000, v6
	v_fmaak_f32 v8, v7, v8, 0xbe2aaa9d
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v9, s13, v7, 0xbab64f3b :: v_dual_mul_f32 v8, v7, v8
	v_dual_fmaak_f32 v9, v7, v9, 0x3d2aabf7 :: v_dual_fmac_f32 v4, v4, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v9, v7, v9, 0xbf000004
	v_fma_f32 v7, v7, v9, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v4, -v4, v7, vcc_lo
	v_xor_b32_e32 v4, v6, v4
	v_add_co_u32 v6, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
	v_cmp_le_i32_e32 vcc_lo, s10, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v0, 0x7fc00000, v4, s0
	v_add_co_u32 v2, s0, v2, s8
	v_add_co_ci_u32_e64 v3, s0, s9, v3, s0
	s_or_b32 s3, vcc_lo, s3
	global_store_b32 v[6:7], v0, off
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_2
.LBB1_7:                                ; %Flow25
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13OmgCos_kerneliPKfPf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 16
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z13OmgCos_kerneliPKfPf, .Lfunc_end1-_Z13OmgCos_kerneliPKfPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1152
; NumSgprs: 18
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z13OmgTan_kerneliPKfPf ; -- Begin function _Z13OmgTan_kerneliPKfPf
	.globl	_Z13OmgTan_kerneliPKfPf
	.p2align	8
	.type	_Z13OmgTan_kerneliPKfPf,@function
_Z13OmgTan_kerneliPKfPf:                ; @_Z13OmgTan_kerneliPKfPf
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x18
	s_load_b32 s3, s[0:1], 0x24
	s_load_b32 s10, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s4, s2, s15
	s_and_b32 s3, s3, 0xffff
	s_add_i32 s4, s4, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s4, s3, v[0:1]
	s_mov_b32 s4, exec_lo
	v_cmpx_gt_i32_e64 s10, v1
	s_cbranch_execz .LBB2_7
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b128 s[4:7], s[0:1], 0x8
	v_ashrrev_i32_e32 v2, 31, v1
	s_mul_i32 s2, s2, s3
	v_mov_b32_e32 v5, 0
	s_ashr_i32 s3, s2, 31
	s_mov_b32 s11, 0x7fffff
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_lshl_b64 s[8:9], s[2:3], 2
	s_mov_b32 s3, 0
	s_mov_b32 s12, 0xbc8cedd3
	s_mov_b32 s13, 0x3c971480
.LBB2_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v6, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
                                        ; implicit-def: $vgpr4
	s_mov_b32 s1, exec_lo
	global_load_b32 v0, v[6:7], off
                                        ; implicit-def: $vgpr7
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v6, 0x7fffffff, v0
	v_cmpx_ngt_f32_e64 0x48000000, |v0|
	s_xor_b32 s14, exec_lo, s1
	s_cbranch_execz .LBB2_4
; %bb.3:                                ;   in Loop: Header=BB2_2 Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_and_or_b32 v15, v6, s11, 0x800000
	v_lshrrev_b32_e32 v12, 23, v6
	v_mad_u64_u32 v[7:8], null, 0xfe5163ab, v15, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v13, 0xffffff88, v12
	v_cmp_lt_u32_e32 vcc_lo, 63, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v4, v8
	v_cndmask_b32_e64 v14, 0, 0xffffffc0, vcc_lo
	v_mad_u64_u32 v[8:9], null, 0x3c439041, v15, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v14, v14, v13
	v_mov_b32_e32 v4, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s0, 31, v14
	v_mad_u64_u32 v[9:10], null, 0xdb629599, v15, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v16, 0, 0xffffffe0, s0
	v_add_nc_u32_e32 v16, v16, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v4, v10 :: v_dual_cndmask_b32 v7, v9, v7
	v_cmp_lt_u32_e64 s1, 31, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[10:11], null, 0xf534ddc0, v15, v[4:5]
	v_mov_b32_e32 v4, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v8, v10, v8, vcc_lo
	v_mad_u64_u32 v[11:12], null, 0xfc2757d1, v15, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v7, v8, v7, s0
	v_mov_b32_e32 v4, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[12:13], null, 0x4e441529, v15, v[4:5]
	v_mov_b32_e32 v4, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[13:14], null, 0xa2f9836e, v15, v[4:5]
	v_cndmask_b32_e64 v4, 0, 0xffffffe0, s1
	v_cndmask_b32_e32 v15, v12, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v13, v13, v11 :: v_dual_add_nc_u32 v4, v4, v16
	v_dual_cndmask_b32 v12, v14, v12 :: v_dual_cndmask_b32 v11, v11, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v14, 32, v4
	v_cndmask_b32_e64 v10, v13, v15, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v12, v12, v13, s0
	v_cndmask_b32_e64 v13, v15, v11, s0
	v_cndmask_b32_e64 v11, v11, v8, s0
	v_cmp_eq_u32_e32 vcc_lo, 0, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v12, v12, v10, s1
	v_cndmask_b32_e64 v10, v10, v13, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v13, v13, v11, s1
	v_cndmask_b32_e64 v7, v11, v7, s1
	v_alignbit_b32 v15, v12, v10, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v9, v10, v13, v14
	v_cndmask_b32_e32 v4, v15, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v8, v9, v10, vcc_lo
	v_alignbit_b32 v12, v13, v7, v14
	v_bfe_u32 v9, v4, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v10, v4, v8, 30
	v_cndmask_b32_e32 v12, v12, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v11, 0, v9
	v_alignbit_b32 v8, v8, v12, 30
	v_alignbit_b32 v7, v12, v7, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v10, v10, v11
	v_xor_b32_e32 v8, v8, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v7, v7, v11
	v_lshrrev_b32_e32 v11, 29, v4
	v_clz_i32_u32_e32 v13, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v11, 31, v11
	v_min_u32_e32 v13, 32, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v14, 0.5, v11
	v_sub_nc_u32_e32 v12, 31, v13
	v_lshlrev_b32_e32 v15, 23, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v10, v10, v8, v12
	v_alignbit_b32 v7, v8, v7, v12
	v_sub_nc_u32_e32 v14, v14, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v8, v10, v7, 9
	v_lshrrev_b32_e32 v10, 9, v10
	v_clz_i32_u32_e32 v12, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v12, 32, v12
	v_sub_nc_u32_e32 v16, 31, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_alignbit_b32 v7, v8, v7, v16
	v_or_b32_e32 v8, v10, v14
	v_add_lshl_u32 v10, v12, v13, 23
	v_lshrrev_b32_e32 v7, 9, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v12, 0x3fc90fda, v8
	v_sub_nc_u32_e32 v7, v7, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v10, 0x3fc90fda, v8, -v12
	v_add_nc_u32_e32 v7, 0x33000000, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v10, 0x33a22168, v8
	v_or_b32_e32 v7, v7, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v10, 0x3fc90fda, v7
	v_lshrrev_b32_e32 v7, 30, v4
	v_dual_add_f32 v4, v12, v10 :: v_dual_add_nc_u32 v7, v9, v7
.LBB2_4:                                ; %Flow
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_and_not1_saveexec_b32 s0, s14
; %bb.5:                                ;   in Loop: Header=BB2_2 Depth=1
	v_mul_f32_e64 v4, 0x3f22f983, |v0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v7, v4
	v_fma_f32 v4, 0xbfc90fda, v7, |v0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, 0xb3a22168, v7
	v_fmac_f32_e32 v4, 0xa7c234c4, v7
	v_cvt_i32_f32_e32 v7, v7
; %bb.6:                                ; %_ZL4tanff.exit
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v8, v4, v4 :: v_dual_add_nc_u32 v1, s2, v1
	v_cmp_class_f32_e64 s0, v0, 0x1f8
	v_and_b32_e32 v7, 1, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmaak_f32 v9, s13, v8, 0xbf039337
	v_fmaak_f32 v10, s12, v8, 0x3ec54587
	v_cmp_eq_u32_e32 vcc_lo, 0, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v9, v8, v9, 0x3f93f425
	v_rcp_f32_e32 v9, v9
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v9, v10, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v8, v8, v9
	v_fma_f32 v9, v8, v4, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v11, v9, v4
	v_rcp_f32_e32 v10, v9
	v_fma_f32 v4, v8, v4, -v11
	s_waitcnt_depctr 0xfff
	v_fma_f32 v8, v9, -v10, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v4, v4, -v10, v8
	v_fma_f32 v4, v4, -v10, -v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v4, v4, v9, vcc_lo
	v_xor3_b32 v4, v6, v0, v4
	v_add_co_u32 v6, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
	v_cmp_le_i32_e32 vcc_lo, s10, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v0, 0x7fc00000, v4, s0
	v_add_co_u32 v2, s0, v2, s8
	v_add_co_ci_u32_e64 v3, s0, s9, v3, s0
	s_or_b32 s3, vcc_lo, s3
	global_store_b32 v[6:7], v0, off
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB2_2
.LBB2_7:                                ; %Flow25
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13OmgTan_kerneliPKfPf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 17
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z13OmgTan_kerneliPKfPf, .Lfunc_end2-_Z13OmgTan_kerneliPKfPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1184
; NumSgprs: 18
; NumVgprs: 17
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 17
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z13OmgCot_kerneliPKfPf ; -- Begin function _Z13OmgCot_kerneliPKfPf
	.globl	_Z13OmgCot_kerneliPKfPf
	.p2align	8
	.type	_Z13OmgCot_kerneliPKfPf,@function
_Z13OmgCot_kerneliPKfPf:                ; @_Z13OmgCot_kerneliPKfPf
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x18
	s_load_b32 s3, s[0:1], 0x24
	s_load_b32 s10, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s4, s2, s15
	s_and_b32 s3, s3, 0xffff
	s_add_i32 s4, s4, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s4, s3, v[0:1]
	s_mov_b32 s4, exec_lo
	v_cmpx_gt_i32_e64 s10, v1
	s_cbranch_execz .LBB3_7
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b128 s[4:7], s[0:1], 0x8
	v_ashrrev_i32_e32 v2, 31, v1
	s_mul_i32 s2, s2, s3
	v_mov_b32_e32 v5, 0
	s_ashr_i32 s3, s2, 31
	s_mov_b32 s11, 0x7fffff
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_lshl_b64 s[8:9], s[2:3], 2
	s_mov_b32 s3, 0
	s_mov_b32 s12, 0xbc8cedd3
	s_mov_b32 s13, 0x3c971480
.LBB3_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v6, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v3, vcc_lo
                                        ; implicit-def: $vgpr4
	s_mov_b32 s1, exec_lo
	global_load_b32 v0, v[6:7], off
                                        ; implicit-def: $vgpr7
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v6, 0x7fffffff, v0
	v_cmpx_ngt_f32_e64 0x48000000, |v0|
	s_xor_b32 s14, exec_lo, s1
	s_cbranch_execz .LBB3_4
; %bb.3:                                ;   in Loop: Header=BB3_2 Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_and_or_b32 v15, v6, s11, 0x800000
	v_lshrrev_b32_e32 v12, 23, v6
	v_mad_u64_u32 v[7:8], null, 0xfe5163ab, v15, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v13, 0xffffff88, v12
	v_cmp_lt_u32_e32 vcc_lo, 63, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v4, v8
	v_cndmask_b32_e64 v14, 0, 0xffffffc0, vcc_lo
	v_mad_u64_u32 v[8:9], null, 0x3c439041, v15, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v14, v14, v13
	v_mov_b32_e32 v4, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s0, 31, v14
	v_mad_u64_u32 v[9:10], null, 0xdb629599, v15, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v16, 0, 0xffffffe0, s0
	v_add_nc_u32_e32 v16, v16, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v4, v10 :: v_dual_cndmask_b32 v7, v9, v7
	v_cmp_lt_u32_e64 s1, 31, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[10:11], null, 0xf534ddc0, v15, v[4:5]
	v_mov_b32_e32 v4, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v8, v10, v8, vcc_lo
	v_mad_u64_u32 v[11:12], null, 0xfc2757d1, v15, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v7, v8, v7, s0
	v_mov_b32_e32 v4, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[12:13], null, 0x4e441529, v15, v[4:5]
	v_mov_b32_e32 v4, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[13:14], null, 0xa2f9836e, v15, v[4:5]
	v_cndmask_b32_e64 v4, 0, 0xffffffe0, s1
	v_cndmask_b32_e32 v15, v12, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v13, v13, v11 :: v_dual_add_nc_u32 v4, v4, v16
	v_dual_cndmask_b32 v12, v14, v12 :: v_dual_cndmask_b32 v11, v11, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v14, 32, v4
	v_cndmask_b32_e64 v10, v13, v15, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v12, v12, v13, s0
	v_cndmask_b32_e64 v13, v15, v11, s0
	v_cndmask_b32_e64 v11, v11, v8, s0
	v_cmp_eq_u32_e32 vcc_lo, 0, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v12, v12, v10, s1
	v_cndmask_b32_e64 v10, v10, v13, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v13, v13, v11, s1
	v_cndmask_b32_e64 v7, v11, v7, s1
	v_alignbit_b32 v15, v12, v10, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v9, v10, v13, v14
	v_cndmask_b32_e32 v4, v15, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v8, v9, v10, vcc_lo
	v_alignbit_b32 v12, v13, v7, v14
	v_bfe_u32 v9, v4, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v10, v4, v8, 30
	v_cndmask_b32_e32 v12, v12, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v11, 0, v9
	v_alignbit_b32 v8, v8, v12, 30
	v_alignbit_b32 v7, v12, v7, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v10, v10, v11
	v_xor_b32_e32 v8, v8, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v7, v7, v11
	v_lshrrev_b32_e32 v11, 29, v4
	v_clz_i32_u32_e32 v13, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v11, 31, v11
	v_min_u32_e32 v13, 32, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v14, 0.5, v11
	v_sub_nc_u32_e32 v12, 31, v13
	v_lshlrev_b32_e32 v15, 23, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v10, v10, v8, v12
	v_alignbit_b32 v7, v8, v7, v12
	v_sub_nc_u32_e32 v14, v14, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v8, v10, v7, 9
	v_lshrrev_b32_e32 v10, 9, v10
	v_clz_i32_u32_e32 v12, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v12, 32, v12
	v_sub_nc_u32_e32 v16, 31, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_alignbit_b32 v7, v8, v7, v16
	v_or_b32_e32 v8, v10, v14
	v_add_lshl_u32 v10, v12, v13, 23
	v_lshrrev_b32_e32 v7, 9, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v12, 0x3fc90fda, v8
	v_sub_nc_u32_e32 v7, v7, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v10, 0x3fc90fda, v8, -v12
	v_add_nc_u32_e32 v7, 0x33000000, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v10, 0x33a22168, v8
	v_or_b32_e32 v7, v7, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v10, 0x3fc90fda, v7
	v_lshrrev_b32_e32 v7, 30, v4
	v_dual_add_f32 v4, v12, v10 :: v_dual_add_nc_u32 v7, v9, v7
.LBB3_4:                                ; %Flow
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_and_not1_saveexec_b32 s0, s14
; %bb.5:                                ;   in Loop: Header=BB3_2 Depth=1
	v_mul_f32_e64 v4, 0x3f22f983, |v0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v7, v4
	v_fma_f32 v4, 0xbfc90fda, v7, |v0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, 0xb3a22168, v7
	v_fmac_f32_e32 v4, 0xa7c234c4, v7
	v_cvt_i32_f32_e32 v7, v7
; %bb.6:                                ; %_ZL4tanff.exit
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v8, v4, v4
	v_cmp_class_f32_e64 s0, v0, 0x1f8
	v_and_b32_e32 v7, 1, v7
	v_add_nc_u32_e32 v1, s2, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmaak_f32 v9, s13, v8, 0xbf039337
	v_fmaak_f32 v10, s12, v8, 0x3ec54587
	v_cmp_eq_u32_e32 vcc_lo, 0, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v9, v8, v9, 0x3f93f425
	v_rcp_f32_e32 v9, v9
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v9, v10, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v8, v8, v9
	v_fma_f32 v9, v8, v4, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v11, v9, v4
	v_rcp_f32_e32 v10, v9
	v_fma_f32 v4, v8, v4, -v11
	s_waitcnt_depctr 0xfff
	v_fma_f32 v8, v9, -v10, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v4, v4, -v10, v8
	v_fma_f32 v4, v4, -v10, -v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v4, v4, v9, vcc_lo
	v_xor3_b32 v4, v6, v0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v6, null, v4, v4, 1.0
	v_div_scale_f32 v9, vcc_lo, 1.0, v4, 1.0
	v_rcp_f32_e32 v7, v6
	s_waitcnt_depctr 0xfff
	v_fma_f32 v8, -v6, v7, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v7, v8, v7
	v_mul_f32_e32 v8, v9, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v10, -v6, v8, v9
	v_fmac_f32_e32 v8, v10, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v6, -v6, v8, v9
	v_div_fmas_f32 v6, v6, v7, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_div_fixup_f32 v4, v6, v4, 1.0
	v_add_co_u32 v6, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
	v_cmp_le_i32_e32 vcc_lo, s10, v1
	v_cndmask_b32_e64 v0, 0x7fc00000, v4, s0
	v_add_co_u32 v2, s0, v2, s8
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v3, s0, s9, v3, s0
	s_or_b32 s3, vcc_lo, s3
	global_store_b32 v[6:7], v0, off
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB3_2
.LBB3_7:                                ; %Flow25
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13OmgCot_kerneliPKfPf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 17
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z13OmgCot_kerneliPKfPf, .Lfunc_end3-_Z13OmgCot_kerneliPKfPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1280
; NumSgprs: 18
; NumVgprs: 17
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 17
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z13OmgLog_kerneliPKfPf ; -- Begin function _Z13OmgLog_kerneliPKfPf
	.globl	_Z13OmgLog_kerneliPKfPf
	.p2align	8
	.type	_Z13OmgLog_kerneliPKfPf,@function
_Z13OmgLog_kerneliPKfPf:                ; @_Z13OmgLog_kerneliPKfPf
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x18
	s_load_b32 s3, s[0:1], 0x24
	s_load_b32 s10, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s4, s2, s15
	s_and_b32 s3, s3, 0xffff
	s_add_i32 s4, s4, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s4, s3, v[0:1]
	s_mov_b32 s4, exec_lo
	v_cmpx_gt_i32_e64 s10, v1
	s_cbranch_execz .LBB4_3
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b128 s[4:7], s[0:1], 0x8
	v_ashrrev_i32_e32 v2, 31, v1
	s_mul_i32 s2, s2, s3
	s_mov_b32 s1, 0
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_lshl_b64 s[8:9], s[2:3], 2
.LBB4_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	v_add_nc_u32_e32 v1, s2, v1
	global_load_b32 v0, v[4:5], off
	s_waitcnt vmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
	v_cndmask_b32_e64 v4, 1.0, 0x4f800000, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v0, v0, v4
	v_add_co_u32 v4, s0, s6, v2
	v_add_co_ci_u32_e64 v5, s0, s7, v3, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_log_f32_e32 v0, v0
	v_cmp_le_i32_e64 s0, s10, v1
	s_or_b32 s1, s0, s1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v6, 0x3f317217, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v7, 0x3f317217, v0, -v6
	v_fmac_f32_e32 v7, 0x3377d1cf, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f32_e32 v6, v6, v7
	v_cndmask_b32_e64 v7, 0, 0x41b17218, vcc_lo
	v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
	v_cndmask_b32_e32 v0, v0, v6, vcc_lo
	v_add_co_u32 v2, vcc_lo, v2, s8
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_sub_f32_e32 v0, v0, v7
	global_store_b32 v[4:5], v0, off
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB4_2
.LBB4_3:                                ; %Flow22
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13OmgLog_kerneliPKfPf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z13OmgLog_kerneliPKfPf, .Lfunc_end4-_Z13OmgLog_kerneliPKfPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 336
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z14OmgLog2_kerneliPKfPf ; -- Begin function _Z14OmgLog2_kerneliPKfPf
	.globl	_Z14OmgLog2_kerneliPKfPf
	.p2align	8
	.type	_Z14OmgLog2_kerneliPKfPf,@function
_Z14OmgLog2_kerneliPKfPf:               ; @_Z14OmgLog2_kerneliPKfPf
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x18
	s_load_b32 s3, s[0:1], 0x24
	s_load_b32 s10, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s4, s2, s15
	s_and_b32 s3, s3, 0xffff
	s_add_i32 s4, s4, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s4, s3, v[0:1]
	s_mov_b32 s4, exec_lo
	v_cmpx_gt_i32_e64 s10, v1
	s_cbranch_execz .LBB5_3
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b128 s[4:7], s[0:1], 0x8
	v_ashrrev_i32_e32 v2, 31, v1
	s_mul_i32 s2, s2, s3
	s_mov_b32 s1, 0
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_lshl_b64 s[8:9], s[2:3], 2
.LBB5_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	v_add_nc_u32_e32 v1, s2, v1
	global_load_b32 v0, v[4:5], off
	s_waitcnt vmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
	v_cndmask_b32_e64 v4, 1.0, 0x4f800000, vcc_lo
	v_cndmask_b32_e64 v6, 0, 0x42000000, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v0, v0, v4
	v_add_co_u32 v4, s0, s6, v2
	v_add_co_ci_u32_e64 v5, s0, s7, v3, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_log_f32_e32 v0, v0
	v_add_co_u32 v2, vcc_lo, v2, s8
	v_cmp_le_i32_e64 s0, s10, v1
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	s_or_b32 s1, s0, s1
	s_waitcnt_depctr 0xfff
	v_sub_f32_e32 v0, v0, v6
	global_store_b32 v[4:5], v0, off
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB5_2
.LBB5_3:                                ; %Flow22
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14OmgLog2_kerneliPKfPf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	_Z14OmgLog2_kerneliPKfPf, .Lfunc_end5-_Z14OmgLog2_kerneliPKfPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 276
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z15OmgLog10_kerneliPKfPf ; -- Begin function _Z15OmgLog10_kerneliPKfPf
	.globl	_Z15OmgLog10_kerneliPKfPf
	.p2align	8
	.type	_Z15OmgLog10_kerneliPKfPf,@function
_Z15OmgLog10_kerneliPKfPf:              ; @_Z15OmgLog10_kerneliPKfPf
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x18
	s_load_b32 s3, s[0:1], 0x24
	s_load_b32 s10, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s4, s2, s15
	s_and_b32 s3, s3, 0xffff
	s_add_i32 s4, s4, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s4, s3, v[0:1]
	s_mov_b32 s4, exec_lo
	v_cmpx_gt_i32_e64 s10, v1
	s_cbranch_execz .LBB6_3
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b128 s[4:7], s[0:1], 0x8
	v_ashrrev_i32_e32 v2, 31, v1
	s_mul_i32 s2, s2, s3
	s_mov_b32 s1, 0
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_lshl_b64 s[8:9], s[2:3], 2
.LBB6_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	v_add_nc_u32_e32 v1, s2, v1
	global_load_b32 v0, v[4:5], off
	s_waitcnt vmcnt(0)
	v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
	v_cndmask_b32_e64 v4, 1.0, 0x4f800000, vcc_lo
	v_cndmask_b32_e64 v7, 0, 0x411a209b, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v0, v0, v4
	v_log_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v4, 0x3e9a209a, v0
	v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f32 v6, 0x3e9a209a, v0, -v4
	v_add_co_u32 v4, s0, s6, v2
	v_add_co_ci_u32_e64 v5, s0, s7, v3, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v6, 0x3284fbcf, v0
	v_cmp_le_i32_e64 s0, s10, v1
	v_fmac_f32_e32 v6, 0x3e9a209a, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_or_b32 s1, s0, s1
	v_cndmask_b32_e32 v0, v0, v6, vcc_lo
	v_add_co_u32 v2, vcc_lo, v2, s8
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_sub_f32_e32 v0, v0, v7
	global_store_b32 v[4:5], v0, off
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB6_2
.LBB6_3:                                ; %Flow22
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15OmgLog10_kerneliPKfPf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end6:
	.size	_Z15OmgLog10_kerneliPKfPf, .Lfunc_end6-_Z15OmgLog10_kerneliPKfPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 340
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z13OmgExp_kerneliPKfPf ; -- Begin function _Z13OmgExp_kerneliPKfPf
	.globl	_Z13OmgExp_kerneliPKfPf
	.p2align	8
	.type	_Z13OmgExp_kerneliPKfPf,@function
_Z13OmgExp_kerneliPKfPf:                ; @_Z13OmgExp_kerneliPKfPf
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x18
	s_load_b32 s3, s[0:1], 0x24
	s_load_b32 s10, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s4, s2, s15
	s_and_b32 s3, s3, 0xffff
	s_add_i32 s4, s4, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s4, s3, v[0:1]
	s_mov_b32 s4, exec_lo
	v_cmpx_gt_i32_e64 s10, v1
	s_cbranch_execz .LBB7_3
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b128 s[4:7], s[0:1], 0x8
	v_ashrrev_i32_e32 v2, 31, v1
	s_mul_i32 s2, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_ashr_i32 s3, s2, 31
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_lshl_b64 s[8:9], s[2:3], 2
	s_mov_b32 s3, 0
.LBB7_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	v_add_nc_u32_e32 v1, s2, v1
	global_load_b32 v0, v[4:5], off
	v_cmp_le_i32_e64 s0, s10, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	s_or_b32 s3, s0, s3
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v4, 0x3fb8aa3b, v0
	v_cmp_nlt_f32_e64 s1, 0x42b17218, v0
	v_fma_f32 v5, 0x3fb8aa3b, v0, -v4
	v_rndne_f32_e32 v6, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v5, 0x32a5705f, v0 :: v_dual_sub_f32 v4, v4, v6
	v_cvt_i32_f32_e32 v6, v6
	v_add_f32_e32 v4, v4, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_exp_f32_e32 v5, v4
	v_add_co_u32 v4, vcc_lo, s6, v2
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v6, v5, v6
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v6, 0, v6, vcc_lo
	v_add_co_u32 v2, vcc_lo, v2, s8
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	v_cndmask_b32_e64 v0, 0x7f800000, v6, s1
	global_store_b32 v[4:5], v0, off
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB7_2
.LBB7_3:                                ; %Flow22
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13OmgExp_kerneliPKfPf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end7:
	.size	_Z13OmgExp_kerneliPKfPf, .Lfunc_end7-_Z13OmgExp_kerneliPKfPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 328
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z13OmgAbs_kerneliPKfPf ; -- Begin function _Z13OmgAbs_kerneliPKfPf
	.globl	_Z13OmgAbs_kerneliPKfPf
	.p2align	8
	.type	_Z13OmgAbs_kerneliPKfPf,@function
_Z13OmgAbs_kerneliPKfPf:                ; @_Z13OmgAbs_kerneliPKfPf
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x18
	s_load_b32 s3, s[0:1], 0x24
	s_load_b32 s10, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s4, s2, s15
	s_and_b32 s3, s3, 0xffff
	s_add_i32 s4, s4, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s4, s3, v[0:1]
	s_mov_b32 s4, exec_lo
	v_cmpx_gt_i32_e64 s10, v1
	s_cbranch_execz .LBB8_3
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b128 s[4:7], s[0:1], 0x8
	v_ashrrev_i32_e32 v2, 31, v1
	s_mul_i32 s2, s2, s3
	s_mov_b32 s1, 0
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_lshl_b64 s[8:9], s[2:3], 2
.LBB8_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	v_add_nc_u32_e32 v1, s2, v1
	global_load_b32 v0, v[4:5], off
	v_add_co_u32 v4, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, v2, s8
	v_cmp_le_i32_e64 s0, s10, v1
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	s_or_b32 s1, s0, s1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v0, 0x7fffffff, v0
	global_store_b32 v[4:5], v0, off
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB8_2
.LBB8_3:                                ; %Flow22
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13OmgAbs_kerneliPKfPf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end8:
	.size	_Z13OmgAbs_kerneliPKfPf, .Lfunc_end8-_Z13OmgAbs_kerneliPKfPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 228
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z13OmgFix_kerneliPKfPf ; -- Begin function _Z13OmgFix_kerneliPKfPf
	.globl	_Z13OmgFix_kerneliPKfPf
	.p2align	8
	.type	_Z13OmgFix_kerneliPKfPf,@function
_Z13OmgFix_kerneliPKfPf:                ; @_Z13OmgFix_kerneliPKfPf
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x18
	s_load_b32 s3, s[0:1], 0x24
	s_load_b32 s10, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s4, s2, s15
	s_and_b32 s3, s3, 0xffff
	s_add_i32 s4, s4, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s4, s3, v[0:1]
	s_mov_b32 s4, exec_lo
	v_cmpx_gt_i32_e64 s10, v1
	s_cbranch_execz .LBB9_3
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b128 s[4:7], s[0:1], 0x8
	v_ashrrev_i32_e32 v2, 31, v1
	s_mul_i32 s2, s2, s3
	s_mov_b32 s1, 0
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_lshl_b64 s[8:9], s[2:3], 2
.LBB9_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	v_add_nc_u32_e32 v1, s2, v1
	global_load_b32 v0, v[4:5], off
	v_add_co_u32 v4, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, v2, s8
	v_cmp_le_i32_e64 s0, s10, v1
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	s_or_b32 s1, s0, s1
	s_waitcnt vmcnt(0)
	v_trunc_f32_e32 v0, v0
	global_store_b32 v[4:5], v0, off
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB9_2
.LBB9_3:                                ; %Flow22
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13OmgFix_kerneliPKfPf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end9:
	.size	_Z13OmgFix_kerneliPKfPf, .Lfunc_end9-_Z13OmgFix_kerneliPKfPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 224
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z14OmgCeil_kerneliPKfPf ; -- Begin function _Z14OmgCeil_kerneliPKfPf
	.globl	_Z14OmgCeil_kerneliPKfPf
	.p2align	8
	.type	_Z14OmgCeil_kerneliPKfPf,@function
_Z14OmgCeil_kerneliPKfPf:               ; @_Z14OmgCeil_kerneliPKfPf
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x18
	s_load_b32 s3, s[0:1], 0x24
	s_load_b32 s10, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s4, s2, s15
	s_and_b32 s3, s3, 0xffff
	s_add_i32 s4, s4, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s4, s3, v[0:1]
	s_mov_b32 s4, exec_lo
	v_cmpx_gt_i32_e64 s10, v1
	s_cbranch_execz .LBB10_3
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b128 s[4:7], s[0:1], 0x8
	v_ashrrev_i32_e32 v2, 31, v1
	s_mul_i32 s2, s2, s3
	s_mov_b32 s1, 0
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_lshl_b64 s[8:9], s[2:3], 2
.LBB10_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	v_add_nc_u32_e32 v1, s2, v1
	global_load_b32 v0, v[4:5], off
	v_add_co_u32 v4, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, v2, s8
	v_cmp_le_i32_e64 s0, s10, v1
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	s_or_b32 s1, s0, s1
	s_waitcnt vmcnt(0)
	v_ceil_f32_e32 v0, v0
	global_store_b32 v[4:5], v0, off
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB10_2
.LBB10_3:                               ; %Flow22
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14OmgCeil_kerneliPKfPf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end10:
	.size	_Z14OmgCeil_kerneliPKfPf, .Lfunc_end10-_Z14OmgCeil_kerneliPKfPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 224
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z15OmgFloor_kerneliPKfPf ; -- Begin function _Z15OmgFloor_kerneliPKfPf
	.globl	_Z15OmgFloor_kerneliPKfPf
	.p2align	8
	.type	_Z15OmgFloor_kerneliPKfPf,@function
_Z15OmgFloor_kerneliPKfPf:              ; @_Z15OmgFloor_kerneliPKfPf
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x18
	s_load_b32 s3, s[0:1], 0x24
	s_load_b32 s10, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s4, s2, s15
	s_and_b32 s3, s3, 0xffff
	s_add_i32 s4, s4, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s4, s3, v[0:1]
	s_mov_b32 s4, exec_lo
	v_cmpx_gt_i32_e64 s10, v1
	s_cbranch_execz .LBB11_3
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b128 s[4:7], s[0:1], 0x8
	v_ashrrev_i32_e32 v2, 31, v1
	s_mul_i32 s2, s2, s3
	s_mov_b32 s1, 0
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_lshl_b64 s[8:9], s[2:3], 2
.LBB11_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	v_add_nc_u32_e32 v1, s2, v1
	global_load_b32 v0, v[4:5], off
	v_add_co_u32 v4, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, v2, s8
	v_cmp_le_i32_e64 s0, s10, v1
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	s_or_b32 s1, s0, s1
	s_waitcnt vmcnt(0)
	v_floor_f32_e32 v0, v0
	global_store_b32 v[4:5], v0, off
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB11_2
.LBB11_3:                               ; %Flow22
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15OmgFloor_kerneliPKfPf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end11:
	.size	_Z15OmgFloor_kerneliPKfPf, .Lfunc_end11-_Z15OmgFloor_kerneliPKfPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 224
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z15OmgRound_kerneliPKfPf ; -- Begin function _Z15OmgRound_kerneliPKfPf
	.globl	_Z15OmgRound_kerneliPKfPf
	.p2align	8
	.type	_Z15OmgRound_kerneliPKfPf,@function
_Z15OmgRound_kerneliPKfPf:              ; @_Z15OmgRound_kerneliPKfPf
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x18
	s_load_b32 s3, s[0:1], 0x24
	s_load_b32 s10, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s4, s2, s15
	s_and_b32 s3, s3, 0xffff
	s_add_i32 s4, s4, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s4, s3, v[0:1]
	s_mov_b32 s4, exec_lo
	v_cmpx_gt_i32_e64 s10, v1
	s_cbranch_execz .LBB12_3
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b128 s[4:7], s[0:1], 0x8
	v_ashrrev_i32_e32 v2, 31, v1
	s_mul_i32 s2, s2, s3
	s_mov_b32 s1, 0
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_lshl_b64 s[8:9], s[2:3], 2
.LBB12_2:                               ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	v_add_nc_u32_e32 v1, s2, v1
	global_load_b32 v0, v[4:5], off
	v_add_co_u32 v4, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, v2, s8
	v_cmp_le_i32_e64 s0, s10, v1
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	s_or_b32 s1, s0, s1
	s_waitcnt vmcnt(0)
	v_rndne_f32_e32 v0, v0
	global_store_b32 v[4:5], v0, off
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB12_2
.LBB12_3:                               ; %Flow22
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15OmgRound_kerneliPKfPf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end12:
	.size	_Z15OmgRound_kerneliPKfPf, .Lfunc_end12-_Z15OmgRound_kerneliPKfPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 224
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
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        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15OmgFloor_kerneliPKfPf
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z15OmgFloor_kerneliPKfPf.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
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        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
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        .size:           8
        .value_kind:     global_buffer
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        .value_kind:     hidden_block_count_x
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        .value_kind:     hidden_grid_dims
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    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15OmgRound_kerneliPKfPf
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z15OmgRound_kerneliPKfPf.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
