#include <iostream>
#include <cuda_runtime.h>
#include <stdlib.h>
#include <time.h>

// Variables globales GPU y CPU
#define l_kernel 3
#define stride 3

/******************************
 *  Procesamiento Matriz CPU  *
 ******************************/

/*
 *  Funcion Max
 */
float MaxCPU(float A, float B){
	float result = A > B ? A : B;
	return result;
}

/*
 *  Lectura Archivo
*/
void Read(float** R, float** G, float** B, int *M, int *N, const char *filename, int tipo) {
    FILE *fp;
    fp = fopen(filename, "r");
    fscanf(fp, "%d %d\n", M, N);

    int imsize = (*M) * (*N);
    float* R1 = new float[imsize];
    float* G1 = new float[imsize];
    float* B1 = new float[imsize];

    if (tipo == 0){ // Lectura normal
		for(int i = 0; i < imsize; i++)
		    fscanf(fp, "%f ", &(R1[i]));
		for(int i = 0; i < imsize; i++)
		    fscanf(fp, "%f ", &(G1[i]));
		for(int i = 0; i < imsize; i++)
		    fscanf(fp, "%f ", &(B1[i]));
	}
    fclose(fp);
    *R = R1; *G = G1; *B = B1;
}

/*
 *  Escritura Archivo
 */
void Write(float* R, float* G, float* B, 
	int M, int N, const char *filename) {
    FILE *fp;
    fp = fopen(filename, "w");
    fprintf(fp, "%d %d\n", M, N);
    for(int i = 0; i < M*N-1; i++)
        fprintf(fp, "%f ", R[i]);
    fprintf(fp, "%f\n", R[M*N-1]);
    for(int i = 0; i < M*N-1; i++)
        fprintf(fp, "%f ", G[i]);
    fprintf(fp, "%f\n", G[M*N-1]);
    for(int i = 0; i < M*N-1; i++)
        fprintf(fp, "%f ", B[i]);
    fprintf(fp, "%f\n", B[M*N-1]);
    fclose(fp);
}


/*
 *  Imprimir Array como matriz
 */
void ShowMatrix(float *matrix, int N, int M) {
    for(int i = 0; i < N; i++){
    	for(int j = 0; j < M; j++)
    		printf("%.1f ", matrix[j + i*M]);
    	printf("\n");
    }
    printf("\n");
}

/*
 *  "Producto" Matricial sub_A * kernel = C
 *  id: id del primer elemento de la submatriz, N: ancho matriz R,G,B
 */
float Product_Matrix(float *A, float *B, int N, int id){
	int col, row, idx_kernel;
	float count;
	col = id%N;
	row = id/N;
	count = 0.0;
	// Recorremos stride
	idx_kernel = 0;
	for(int i=row; i < row+l_kernel; i++){
		for(int j=col; j< col+l_kernel; j++){
			int id_casilla = j + i*N;
			// printf("%.1f x %.1f\n", A[id_casilla], B[idx_kernel]);
			count += A[id_casilla] * B[idx_kernel];
			idx_kernel += 1;
		}
	}
	return count;
}

__global__ void convolucion(float *f, float *f_out ,float* kernel, int N, int Nres){
	int tid = threadIdx.x + blockDim.x * blockIdx.x;
	int x,y; 
	if(tid < 800*800){ //1 thread para cada pixel de salida
	  x = 1 +  (tid%Nres)*stride; //coordenaas del centro de cada sub_matriz
		y = 1 + (tid/Nres)*stride;

		float suma = 0;
		int indice_sub_matriz, indice_kernel;
		for (int i = -1; i<=1 ; i++){
				for (int j = -1; j <= 1; j++){
						indice_sub_matriz = (x+i) + (y+j)*N;
						indice_kernel = (1+i) + (1+j)*3;
						suma += f[indice_sub_matriz] * kernel[indice_kernel];
				}
		}
		printf("%f\n", suma);
	  f_out[tid] = suma;
	}
}


__device__ float max_pool(float *f, int N, int x, int y){
		//recorre una sub matriz de 2x2 y encuentra el valor máximo 
		float valores[4] = {
				f[(x+0) + (y+0)*N],
				f[(x+1) + (y+0)*N],
				f[(x+0) + (y+1)*N],
				f[(x+1) + (y+1)*N]
		};
		int max = 0;
		for (int i = 0; i< 4; i++){
				if (valores[i] > max){
						max = valores[i];  
				}
		}
		return max;
}
__global__ void pooling(float *f, float *f_out, int N){
	int tid = threadIdx.x + blockDim.x * blockIdx.x;
	int x,y;
	if(tid < 400*400){ //1 thread para cada pixel de salida
	  x = 1 +  (tid%N)*stride;
		y = 1 + (tid/N)*stride;
	  f_out[tid] = max_pool(f, N , x, y);
	}
}


/*
 *  Codigo Principal
 */
int main(int argc, char **argv){

    /*
     *  Inicializacion
     */
	int M, N;
	
	float kernel[l_kernel*l_kernel] = {-1, 1, 0, -1, 1, 0 ,-1, 1, 0}; // filtro a usar
  float *Rhost, *Ghost, *Bhost;
  float *Rhostout, *Ghostout, *Bhostout;

  float *R, *G, *B;
  float *Rout, *Gout, *Bout;
	int gs, bs = 256;
  float dt;
  cudaEvent_t ct1, ct2;

  // Lectura de archivo
	Read(&Rhost, &Ghost, &Bhost, &M, &N, "img_test.txt", 0);
	int Mres = M/l_kernel;
	int Nres = N/l_kernel;
	Rhostout = new float[Mres*Nres];
	Ghostout = new float[Mres*Nres];
	Bhostout = new float[Mres*Nres];
	
	/*
	 *  Parte GPU
	 */

    gs = (int)ceil((float) Mres*Nres / bs);    
    cudaMalloc((void**)&R, M * N * sizeof(float));
    cudaMalloc((void**)&G, M * N * sizeof(float));
    cudaMalloc((void**)&B, M * N * sizeof(float));
    cudaMemcpy(R, Rhost, M * N * sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(G, Ghost, M * N * sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(B, Bhost, M * N * sizeof(float), cudaMemcpyHostToDevice);
        
    cudaMalloc((void**)&Rout, Mres * Nres * sizeof(float));
    cudaMalloc((void**)&Gout, Mres * Nres * sizeof(float));
    cudaMalloc((void**)&Bout, Mres * Nres * sizeof(float));
    
    cudaEventCreate(&ct1);
    cudaEventCreate(&ct2);
    cudaEventRecord(ct1);

    convolucion<<<gs, bs>>>(R, Rout, kernel, N, Nres);
		convolucion<<<gs, bs>>>(G, Gout, kernel, N, Nres);
		convolucion<<<gs, bs>>>(B, Bout, kernel, N, Nres);

    cudaEventRecord(ct2);
    cudaEventSynchronize(ct2);
    cudaEventElapsedTime(&dt, ct1, ct2);

		cudaMemcpy(Rhostout, Rout, M * N * sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(Ghostout, Gout, M * N * sizeof(float), cudaMemcpyHostToDevice);
    cudaMemcpy(Bhostout, Bout, M * N * sizeof(float), cudaMemcpyHostToDevice);

		std::cout << "Tiempo: " << dt << "[ms]" << std::endl;

		Write(Rhostout, Ghostout, Bhostout, Mres, Nres, "resultado.txt");


	/*
	 *  Memoria Global
	 */
	

	/*
	 *  Memoria Compartida
	 */

	cudaFree(R); cudaFree(G); cudaFree(B);
	cudaFree(Rout); cudaFree(Gout); cudaFree(Bout);
	delete[] Rhost; delete[] Ghost; delete[] Bhost;
	delete[] Rhostout; delete[] Ghostout; delete[] Bhostout;
	return 0;
}
	.file	"tmpxft_0028103d_00000000-6_streams.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3644:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3644:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z6MaxCPUff
	.type	_Z6MaxCPUff, @function
_Z6MaxCPUff:
.LFB3635:
	.cfi_startproc
	endbr64
	maxss	%xmm1, %xmm0
	ret
	.cfi_endproc
.LFE3635:
	.size	_Z6MaxCPUff, .-_Z6MaxCPUff
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"r"
.LC2:
	.string	"%d %d\n"
.LC3:
	.string	"%f "
	.text
	.globl	_Z4ReadPPfS0_S0_PiS1_PKci
	.type	_Z4ReadPPfS0_S0_PiS1_PKci, @function
_Z4ReadPPfS0_S0_PiS1_PKci:
.LFB3636:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%rdx, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%r8, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rcx, %rbx
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	movq	%rdi, 8(%rsp)
	movq	%r9, %rdi
	movq	%rsi, 16(%rsp)
	leaq	.LC1(%rip), %rsi
	call	fopen@PLT
	movq	%rbx, %rdx
	movq	%rbp, %rcx
	leaq	.LC2(%rip), %rsi
	movq	%rax, (%rsp)
	movq	%rax, %rdi
	xorl	%eax, %eax
	call	__isoc23_fscanf@PLT
	movl	(%rbx), %ebx
	imull	0(%rbp), %ebx
	movabsq	$2305843009213693950, %rax
	movslq	%ebx, %r13
	cmpq	%r13, %rax
	jb	.L7
	salq	$2, %r13
	movq	%r13, %rdi
	call	_Znam@PLT
	movq	%r13, %rdi
	movq	%rax, %rbp
	call	_Znam@PLT
	movq	%r13, %rdi
	movq	%rax, %r12
	call	_Znam@PLT
	cmpl	$0, 96(%rsp)
	movq	%rax, %r13
	jne	.L8
	movq	%rbp, %rdx
	xorl	%r15d, %r15d
	jmp	.L9
.L8:
	movq	(%rsp), %rdi
	call	fclose@PLT
	movq	8(%rsp), %rax
	movq	%rbp, (%rax)
	movq	16(%rsp), %rax
	movq	%r12, (%rax)
	movq	%r13, (%r14)
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
.L7:
	.cfi_restore_state
	call	__cxa_throw_bad_array_new_length@PLT
.L9:
	cmpl	%ebx, %r15d
	jge	.L18
	movq	(%rsp), %rdi
	leaq	.LC3(%rip), %rsi
	xorl	%eax, %eax
	incl	%r15d
	movq	%rdx, 24(%rsp)
	call	__isoc23_fscanf@PLT
	movq	24(%rsp), %rdx
	addq	$4, %rdx
	jmp	.L9
.L18:
	movq	%r12, %rdx
	xorl	%r15d, %r15d
.L11:
	cmpl	%ebx, %r15d
	jge	.L19
	movq	(%rsp), %rdi
	leaq	.LC3(%rip), %rsi
	xorl	%eax, %eax
	incl	%r15d
	movq	%rdx, 24(%rsp)
	call	__isoc23_fscanf@PLT
	movq	24(%rsp), %rdx
	addq	$4, %rdx
	jmp	.L11
.L19:
	movq	%r13, %r15
.L13:
	cmpl	%ebx, 96(%rsp)
	jge	.L8
	movq	(%rsp), %rdi
	movq	%r15, %rdx
	leaq	.LC3(%rip), %rsi
	xorl	%eax, %eax
	addq	$4, %r15
	call	__isoc23_fscanf@PLT
	incl	96(%rsp)
	jmp	.L13
	.cfi_endproc
.LFE3636:
	.size	_Z4ReadPPfS0_S0_PiS1_PKci, .-_Z4ReadPPfS0_S0_PiS1_PKci
	.section	.rodata.str1.1
.LC4:
	.string	"w"
.LC5:
	.string	"%f\n"
	.text
	.globl	_Z5WritePfS_S_iiPKc
	.type	_Z5WritePfS_S_iiPKc, @function
_Z5WritePfS_S_iiPKc:
.LFB3637:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	%r8d, %r15d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	xorl	%r14d, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	%ecx, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rdi, %r12
	movq	%r9, %rdi
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rsi, %rbp
	leaq	.LC4(%rip), %rsi
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rdx, %rbx
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	call	fopen@PLT
	movl	%r15d, %r8d
	imull	%r13d, %r15d
	movl	%r13d, %ecx
	movq	%rax, 8(%rsp)
	movq	%rax, %rdi
	movl	$2, %esi
	xorl	%eax, %eax
	leaq	.LC2(%rip), %rdx
	call	__fprintf_chk@PLT
	leal	-1(%r15), %r13d
.L21:
	cmpl	%r14d, %r13d
	jle	.L28
	movq	8(%rsp), %rdi
	leaq	.LC3(%rip), %rdx
	movl	$2, %esi
	movb	$1, %al
	cvtss2sd	(%r12,%r14,4), %xmm0
	incq	%r14
	call	__fprintf_chk@PLT
	jmp	.L21
.L28:
	movq	8(%rsp), %rdi
	movslq	%r15d, %r15
	movl	$2, %esi
	movb	$1, %al
	leaq	.LC5(%rip), %rdx
	cvtss2sd	-4(%r12,%r15,4), %xmm0
	leaq	0(,%r15,4), %r14
	xorl	%r12d, %r12d
	call	__fprintf_chk@PLT
	leaq	.LC3(%rip), %r15
.L23:
	cmpl	%r12d, %r13d
	jle	.L29
	movq	8(%rsp), %rdi
	movq	%r15, %rdx
	movl	$2, %esi
	movb	$1, %al
	cvtss2sd	0(%rbp,%r12,4), %xmm0
	incq	%r12
	call	__fprintf_chk@PLT
	jmp	.L23
.L29:
	movq	8(%rsp), %rdi
	movl	$2, %esi
	movb	$1, %al
	xorl	%r15d, %r15d
	leaq	.LC5(%rip), %rdx
	cvtss2sd	-4(%rbp,%r14), %xmm0
	leaq	.LC3(%rip), %rbp
	call	__fprintf_chk@PLT
.L25:
	cmpl	%r15d, %r13d
	jle	.L30
	movq	8(%rsp), %rdi
	movq	%rbp, %rdx
	movl	$2, %esi
	movb	$1, %al
	cvtss2sd	(%rbx,%r15,4), %xmm0
	incq	%r15
	call	__fprintf_chk@PLT
	jmp	.L25
.L30:
	movq	8(%rsp), %rdi
	leaq	.LC5(%rip), %rdx
	movl	$2, %esi
	movb	$1, %al
	cvtss2sd	-4(%rbx,%r14), %xmm0
	call	__fprintf_chk@PLT
	movq	8(%rsp), %rdi
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	fclose@PLT
	.cfi_endproc
.LFE3637:
	.size	_Z5WritePfS_S_iiPKc, .-_Z5WritePfS_S_iiPKc
	.section	.rodata.str1.1
.LC6:
	.string	"%.1f "
.LC7:
	.string	"\n"
	.text
	.globl	_Z10ShowMatrixPfii
	.type	_Z10ShowMatrixPfii, @function
_Z10ShowMatrixPfii:
.LFB3638:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movl	%esi, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	xorl	%r13d, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	xorl	%r12d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rdi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%edx, %ebx
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
.L32:
	cmpl	%r14d, %r13d
	jge	.L34
	movslq	%r12d, %rax
	xorl	%r15d, %r15d
	leaq	0(%rbp,%rax,4), %rcx
.L35:
	cmpl	%r15d, %ebx
	jle	.L37
	leaq	.LC6(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	(%rcx,%r15,4), %xmm0
	movq	%rcx, 8(%rsp)
	incq	%r15
	call	__printf_chk@PLT
	movq	8(%rsp), %rcx
	jmp	.L35
.L37:
	leaq	.LC7(%rip), %rsi
	xorl	%eax, %eax
	incl	%r13d
	addl	%ebx, %r12d
	movl	$2, %edi
	call	__printf_chk@PLT
	jmp	.L32
.L34:
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	leaq	.LC7(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	__printf_chk@PLT
	.cfi_endproc
.LFE3638:
	.size	_Z10ShowMatrixPfii, .-_Z10ShowMatrixPfii
	.globl	_Z14Product_MatrixPfS_ii
	.type	_Z14Product_MatrixPfS_ii, @function
_Z14Product_MatrixPfS_ii:
.LFB3639:
	.cfi_startproc
	endbr64
	movl	%ecx, %eax
	movq	%rdi, %r9
	movslq	%edx, %rdi
	movq	%rsi, %r8
	cltd
	movq	%rdi, %rsi
	xorps	%xmm0, %xmm0
	idivl	%edi
	salq	$2, %rdi
	movl	%eax, %ecx
	imull	%esi, %ecx
	movslq	%ecx, %rcx
	leaq	(%r9,%rcx,4), %r9
	xorl	%ecx, %ecx
.L39:
	movslq	%edx, %rax
	movq	%rcx, %rsi
	leaq	3(%rax), %r10
.L40:
	movss	(%r9,%rax,4), %xmm1
	mulss	(%r8,%rsi,4), %xmm1
	incq	%rax
	incq	%rsi
	addss	%xmm1, %xmm0
	cmpq	%rax, %r10
	jne	.L40
	addq	$3, %rcx
	addq	%rdi, %r9
	cmpq	$9, %rcx
	jne	.L39
	ret
	.cfi_endproc
.LFE3639:
	.size	_Z14Product_MatrixPfS_ii, .-_Z14Product_MatrixPfS_ii
	.globl	_Z8max_poolPfiii
	.type	_Z8max_poolPfiii, @function
_Z8max_poolPfiii:
.LFB3640:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3640:
	.size	_Z8max_poolPfiii, .-_Z8max_poolPfiii
	.globl	_Z37__device_stub__Z11convolucionPfS_S_iiPfS_S_ii
	.type	_Z37__device_stub__Z11convolucionPfS_S_iiPfS_S_ii, @function
_Z37__device_stub__Z11convolucionPfS_S_iiPfS_S_ii:
.LFB3666:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L45
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z11convolucionPfS_S_ii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L45:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L47
	call	__stack_chk_fail@PLT
.L47:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3666:
	.size	_Z37__device_stub__Z11convolucionPfS_S_iiPfS_S_ii, .-_Z37__device_stub__Z11convolucionPfS_S_iiPfS_S_ii
	.globl	_Z11convolucionPfS_S_ii
	.type	_Z11convolucionPfS_S_ii, @function
_Z11convolucionPfS_S_ii:
.LFB3667:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z11convolucionPfS_S_iiPfS_S_ii
	.cfi_endproc
.LFE3667:
	.size	_Z11convolucionPfS_S_ii, .-_Z11convolucionPfS_S_ii
	.section	.rodata.str1.1
.LC9:
	.string	"img_test.txt"
.LC11:
	.string	"Tiempo: "
.LC12:
	.string	"[ms]"
.LC13:
	.string	"resultado.txt"
	.section	.rodata
	.align 32
.LC0:
	.long	-1082130432
	.long	1065353216
	.long	0
	.long	-1082130432
	.long	1065353216
	.long	0
	.long	-1082130432
	.long	1065353216
	.long	0
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3641:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	leaq	.LC0(%rip), %rsi
	movl	$9, %ecx
	leaq	.LC9(%rip), %r9
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$216, %rsp
	.cfi_def_cfa_offset 272
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	64(%rsp), %rdx
	leaq	164(%rsp), %rdi
	rep movsl
	leaq	40(%rsp), %rcx
	leaq	56(%rsp), %rsi
	leaq	48(%rsp), %rdi
	pushq	%rax
	.cfi_def_cfa_offset 280
	pushq	$0
	.cfi_def_cfa_offset 288
	leaq	60(%rsp), %r8
	call	_Z4ReadPPfS0_S0_PiS1_PKci
	movl	56(%rsp), %eax
	movl	$3, %ecx
	cltd
	idivl	%ecx
	movl	%eax, %ebp
	movl	60(%rsp), %eax
	cltd
	idivl	%ecx
	popq	%rdx
	.cfi_def_cfa_offset 280
	popq	%rcx
	.cfi_def_cfa_offset 272
	movabsq	$2305843009213693950, %rdx
	movl	%eax, %ebx
	movl	%ebp, %eax
	imull	%ebx, %eax
	cltq
	cmpq	%rax, %rdx
	jb	.L51
	leaq	0(,%rax,4), %r15
	movq	%r15, %rdi
	call	_Znam@PLT
	movq	%r15, %rdi
	movq	%rax, (%rsp)
	call	_Znam@PLT
	movq	%r15, %rdi
	movq	%rax, 8(%rsp)
	call	_Znam@PLT
	cvtsi2ssl	%ebx, %xmm1
	cvtsi2ssl	%ebp, %xmm0
	movq	%rax, 16(%rsp)
	mulss	%xmm1, %xmm0
	mulss	.LC10(%rip), %xmm0
	call	ceilf@PLT
	movl	40(%rsp), %esi
	imull	44(%rsp), %esi
	leaq	72(%rsp), %rdi
	movss	%xmm0, 28(%rsp)
	movslq	%esi, %rsi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movl	40(%rsp), %esi
	imull	44(%rsp), %esi
	leaq	80(%rsp), %rdi
	movslq	%esi, %rsi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movl	40(%rsp), %esi
	imull	44(%rsp), %esi
	leaq	88(%rsp), %rdi
	movslq	%esi, %rsi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movl	40(%rsp), %edx
	imull	44(%rsp), %edx
	movl	$1, %ecx
	movq	48(%rsp), %r14
	movq	72(%rsp), %rdi
	movslq	%edx, %rdx
	movq	%r14, %rsi
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movl	40(%rsp), %edx
	imull	44(%rsp), %edx
	movl	$1, %ecx
	movq	56(%rsp), %r13
	movq	80(%rsp), %rdi
	movslq	%edx, %rdx
	movq	%r13, %rsi
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movl	40(%rsp), %edx
	imull	44(%rsp), %edx
	movl	$1, %ecx
	movq	64(%rsp), %r12
	movq	88(%rsp), %rdi
	movslq	%edx, %rdx
	movq	%r12, %rsi
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movq	%r15, %rsi
	leaq	96(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	%r15, %rsi
	leaq	104(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	%r15, %rsi
	leaq	112(%rsp), %rdi
	call	cudaMalloc@PLT
	leaq	120(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	128(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	120(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	$16777217, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movss	28(%rsp), %xmm0
	salq	$8, %rdx
	movl	$1, %ecx
	movabsq	$4294967297, %rax
	movq	%rax, 144(%rsp)
	movl	148(%rsp), %esi
	cvttss2sil	%xmm0, %r15d
	movq	%rdx, 152(%rsp)
	movl	$1, 160(%rsp)
	movl	%r15d, 140(%rsp)
	movq	140(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L52
	movl	44(%rsp), %ecx
	movq	96(%rsp), %rsi
	movl	%ebx, %r8d
	leaq	164(%rsp), %rdx
	movq	72(%rsp), %rdi
	call	_Z37__device_stub__Z11convolucionPfS_S_iiPfS_S_ii
	jmp	.L52
.L51:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	jne	.L72
	call	__cxa_throw_bad_array_new_length@PLT
.L52:
	movl	$16777217, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$4294967297, %rax
	salq	$8, %rdx
	movl	%r15d, 140(%rsp)
	movq	%rax, 144(%rsp)
	movq	140(%rsp), %rdi
	movl	148(%rsp), %esi
	movq	%rdx, 152(%rsp)
	movl	$1, 160(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L55
	movl	44(%rsp), %ecx
	movq	104(%rsp), %rsi
	movl	%ebx, %r8d
	leaq	164(%rsp), %rdx
	movq	80(%rsp), %rdi
	call	_Z37__device_stub__Z11convolucionPfS_S_iiPfS_S_ii
.L55:
	movl	$16777217, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$4294967297, %rax
	salq	$8, %rdx
	movl	%r15d, 140(%rsp)
	movq	%rax, 144(%rsp)
	movq	140(%rsp), %rdi
	movl	148(%rsp), %esi
	movq	%rdx, 152(%rsp)
	movl	$1, 160(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L56
	movl	44(%rsp), %ecx
	movq	112(%rsp), %rsi
	movl	%ebx, %r8d
	leaq	164(%rsp), %rdx
	movq	88(%rsp), %rdi
	call	_Z37__device_stub__Z11convolucionPfS_S_iiPfS_S_ii
.L56:
	movq	128(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	128(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	128(%rsp), %rdx
	movq	120(%rsp), %rsi
	leaq	152(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movl	40(%rsp), %edx
	imull	44(%rsp), %edx
	movl	$1, %ecx
	movq	96(%rsp), %rsi
	movq	(%rsp), %rdi
	movslq	%edx, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movl	40(%rsp), %edx
	imull	44(%rsp), %edx
	movl	$1, %ecx
	movq	104(%rsp), %rsi
	movq	8(%rsp), %rdi
	movslq	%edx, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	movl	40(%rsp), %edx
	imull	44(%rsp), %edx
	movl	$1, %ecx
	movq	112(%rsp), %rsi
	movq	16(%rsp), %rdi
	movslq	%edx, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	leaq	.LC11(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	cvtss2sd	152(%rsp), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC12(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	16(%rsp), %rdx
	movq	(%rsp), %rdi
	movl	%ebp, %ecx
	movq	8(%rsp), %rsi
	leaq	.LC13(%rip), %r9
	movl	%ebx, %r8d
	call	_Z5WritePfS_S_iiPKc
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movq	80(%rsp), %rdi
	call	cudaFree@PLT
	movq	88(%rsp), %rdi
	call	cudaFree@PLT
	movq	96(%rsp), %rdi
	call	cudaFree@PLT
	movq	104(%rsp), %rdi
	call	cudaFree@PLT
	movq	112(%rsp), %rdi
	call	cudaFree@PLT
	testq	%r14, %r14
	je	.L57
	movq	%r14, %rdi
	call	_ZdaPv@PLT
.L57:
	testq	%r13, %r13
	je	.L58
	movq	%r13, %rdi
	call	_ZdaPv@PLT
.L58:
	testq	%r12, %r12
	je	.L59
	movq	%r12, %rdi
	call	_ZdaPv@PLT
.L59:
	movq	(%rsp), %rdi
	call	_ZdaPv@PLT
	movq	8(%rsp), %rdi
	call	_ZdaPv@PLT
	movq	16(%rsp), %rdi
	call	_ZdaPv@PLT
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L60
.L72:
	call	__stack_chk_fail@PLT
.L60:
	addq	$216, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3641:
	.size	main, .-main
	.text
	.globl	_Z29__device_stub__Z7poolingPfS_iPfS_i
	.type	_Z29__device_stub__Z7poolingPfS_iPfS_i, @function
_Z29__device_stub__Z7poolingPfS_iPfS_i:
.LFB3668:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L73
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z7poolingPfS_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L73:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L75
	call	__stack_chk_fail@PLT
.L75:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3668:
	.size	_Z29__device_stub__Z7poolingPfS_iPfS_i, .-_Z29__device_stub__Z7poolingPfS_iPfS_i
	.globl	_Z7poolingPfS_i
	.type	_Z7poolingPfS_i, @function
_Z7poolingPfS_i:
.LFB3669:
	.cfi_startproc
	endbr64
	jmp	_Z29__device_stub__Z7poolingPfS_iPfS_i
	.cfi_endproc
.LFE3669:
	.size	_Z7poolingPfS_i, .-_Z7poolingPfS_i
	.section	.rodata.str1.1
.LC15:
	.string	"_Z7poolingPfS_i"
.LC16:
	.string	"_Z11convolucionPfS_S_ii"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3671:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC15(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z7poolingPfS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC16(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z11convolucionPfS_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3671:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC10:
	.long	998244352
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <iostream>
#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <time.h>

// Variables globales GPU y CPU
#define l_kernel 3
#define stride 3

/******************************
 *  Procesamiento Matriz CPU  *
 ******************************/

/*
 *  Funcion Max
 */
float MaxCPU(float A, float B){
	float result = A > B ? A : B;
	return result;
}

/*
 *  Lectura Archivo
*/
void Read(float** R, float** G, float** B, int *M, int *N, const char *filename, int tipo) {
    FILE *fp;
    fp = fopen(filename, "r");
    fscanf(fp, "%d %d\n", M, N);

    int imsize = (*M) * (*N);
    float* R1 = new float[imsize];
    float* G1 = new float[imsize];
    float* B1 = new float[imsize];

    if (tipo == 0){ // Lectura normal
		for(int i = 0; i < imsize; i++)
		    fscanf(fp, "%f ", &(R1[i]));
		for(int i = 0; i < imsize; i++)
		    fscanf(fp, "%f ", &(G1[i]));
		for(int i = 0; i < imsize; i++)
		    fscanf(fp, "%f ", &(B1[i]));
	}
    fclose(fp);
    *R = R1; *G = G1; *B = B1;
}

/*
 *  Escritura Archivo
 */
void Write(float* R, float* G, float* B, 
	int M, int N, const char *filename) {
    FILE *fp;
    fp = fopen(filename, "w");
    fprintf(fp, "%d %d\n", M, N);
    for(int i = 0; i < M*N-1; i++)
        fprintf(fp, "%f ", R[i]);
    fprintf(fp, "%f\n", R[M*N-1]);
    for(int i = 0; i < M*N-1; i++)
        fprintf(fp, "%f ", G[i]);
    fprintf(fp, "%f\n", G[M*N-1]);
    for(int i = 0; i < M*N-1; i++)
        fprintf(fp, "%f ", B[i]);
    fprintf(fp, "%f\n", B[M*N-1]);
    fclose(fp);
}


/*
 *  Imprimir Array como matriz
 */
void ShowMatrix(float *matrix, int N, int M) {
    for(int i = 0; i < N; i++){
    	for(int j = 0; j < M; j++)
    		printf("%.1f ", matrix[j + i*M]);
    	printf("\n");
    }
    printf("\n");
}

/*
 *  "Producto" Matricial sub_A * kernel = C
 *  id: id del primer elemento de la submatriz, N: ancho matriz R,G,B
 */
float Product_Matrix(float *A, float *B, int N, int id){
	int col, row, idx_kernel;
	float count;
	col = id%N;
	row = id/N;
	count = 0.0;
	// Recorremos stride
	idx_kernel = 0;
	for(int i=row; i < row+l_kernel; i++){
		for(int j=col; j< col+l_kernel; j++){
			int id_casilla = j + i*N;
			// printf("%.1f x %.1f\n", A[id_casilla], B[idx_kernel]);
			count += A[id_casilla] * B[idx_kernel];
			idx_kernel += 1;
		}
	}
	return count;
}

__global__ void convolucion(float *f, float *f_out ,float* kernel, int N, int Nres){
	int tid = threadIdx.x + blockDim.x * blockIdx.x;
	int x,y; 
	if(tid < 800*800){ //1 thread para cada pixel de salida
	  x = 1 +  (tid%Nres)*stride; //coordenaas del centro de cada sub_matriz
		y = 1 + (tid/Nres)*stride;

		float suma = 0;
		int indice_sub_matriz, indice_kernel;
		for (int i = -1; i<=1 ; i++){
				for (int j = -1; j <= 1; j++){
						indice_sub_matriz = (x+i) + (y+j)*N;
						indice_kernel = (1+i) + (1+j)*3;
						suma += f[indice_sub_matriz] * kernel[indice_kernel];
				}
		}
		printf("%f\n", suma);
	  f_out[tid] = suma;
	}
}


__device__ float max_pool(float *f, int N, int x, int y){
		//recorre una sub matriz de 2x2 y encuentra el valor máximo 
		float valores[4] = {
				f[(x+0) + (y+0)*N],
				f[(x+1) + (y+0)*N],
				f[(x+0) + (y+1)*N],
				f[(x+1) + (y+1)*N]
		};
		int max = 0;
		for (int i = 0; i< 4; i++){
				if (valores[i] > max){
						max = valores[i];  
				}
		}
		return max;
}
__global__ void pooling(float *f, float *f_out, int N){
	int tid = threadIdx.x + blockDim.x * blockIdx.x;
	int x,y;
	if(tid < 400*400){ //1 thread para cada pixel de salida
	  x = 1 +  (tid%N)*stride;
		y = 1 + (tid/N)*stride;
	  f_out[tid] = max_pool(f, N , x, y);
	}
}


/*
 *  Codigo Principal
 */
int main(int argc, char **argv){

    /*
     *  Inicializacion
     */
	int M, N;
	
	float kernel[l_kernel*l_kernel] = {-1, 1, 0, -1, 1, 0 ,-1, 1, 0}; // filtro a usar
  float *Rhost, *Ghost, *Bhost;
  float *Rhostout, *Ghostout, *Bhostout;

  float *R, *G, *B;
  float *Rout, *Gout, *Bout;
	int gs, bs = 256;
  float dt;
  hipEvent_t ct1, ct2;

  // Lectura de archivo
	Read(&Rhost, &Ghost, &Bhost, &M, &N, "img_test.txt", 0);
	int Mres = M/l_kernel;
	int Nres = N/l_kernel;
	Rhostout = new float[Mres*Nres];
	Ghostout = new float[Mres*Nres];
	Bhostout = new float[Mres*Nres];
	
	/*
	 *  Parte GPU
	 */

    gs = (int)ceil((float) Mres*Nres / bs);    
    hipMalloc((void**)&R, M * N * sizeof(float));
    hipMalloc((void**)&G, M * N * sizeof(float));
    hipMalloc((void**)&B, M * N * sizeof(float));
    hipMemcpy(R, Rhost, M * N * sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(G, Ghost, M * N * sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(B, Bhost, M * N * sizeof(float), hipMemcpyHostToDevice);
        
    hipMalloc((void**)&Rout, Mres * Nres * sizeof(float));
    hipMalloc((void**)&Gout, Mres * Nres * sizeof(float));
    hipMalloc((void**)&Bout, Mres * Nres * sizeof(float));
    
    hipEventCreate(&ct1);
    hipEventCreate(&ct2);
    hipEventRecord(ct1);

    convolucion<<<gs, bs>>>(R, Rout, kernel, N, Nres);
		convolucion<<<gs, bs>>>(G, Gout, kernel, N, Nres);
		convolucion<<<gs, bs>>>(B, Bout, kernel, N, Nres);

    hipEventRecord(ct2);
    hipEventSynchronize(ct2);
    hipEventElapsedTime(&dt, ct1, ct2);

		hipMemcpy(Rhostout, Rout, M * N * sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(Ghostout, Gout, M * N * sizeof(float), hipMemcpyHostToDevice);
    hipMemcpy(Bhostout, Bout, M * N * sizeof(float), hipMemcpyHostToDevice);

		std::cout << "Tiempo: " << dt << "[ms]" << std::endl;

		Write(Rhostout, Ghostout, Bhostout, Mres, Nres, "resultado.txt");


	/*
	 *  Memoria Global
	 */
	

	/*
	 *  Memoria Compartida
	 */

	hipFree(R); hipFree(G); hipFree(B);
	hipFree(Rout); hipFree(Gout); hipFree(Bout);
	delete[] Rhost; delete[] Ghost; delete[] Bhost;
	delete[] Rhostout; delete[] Ghostout; delete[] Bhostout;
	return 0;
}
	.text
	.file	"streams.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z6MaxCPUff                     # -- Begin function _Z6MaxCPUff
	.type	_Z6MaxCPUff,@function
_Z6MaxCPUff:                            # @_Z6MaxCPUff
	.cfi_startproc
# %bb.0:
	maxss	%xmm1, %xmm0
	retq
.Lfunc_end0:
	.size	_Z6MaxCPUff, .Lfunc_end0-_Z6MaxCPUff
	.cfi_endproc
                                        # -- End function
	.globl	_Z4ReadPPfS0_S0_PiS1_PKci       # -- Begin function _Z4ReadPPfS0_S0_PiS1_PKci
	.type	_Z4ReadPPfS0_S0_PiS1_PKci,@function
_Z4ReadPPfS0_S0_PiS1_PKci:              # @_Z4ReadPPfS0_S0_PiS1_PKci
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r8, %rbx
	movq	%rcx, %r14
	movq	%rdx, %rbp
	movq	%rsi, 32(%rsp)                  # 8-byte Spill
	movq	%rdi, 24(%rsp)                  # 8-byte Spill
	movl	$.L.str, %esi
	movq	%r9, %rdi
	callq	fopen
	movq	%rax, %r12
	movl	$.L.str.1, %esi
	movq	%rax, %rdi
	movq	%r14, %rdx
	movq	%rbx, %rcx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	movslq	(%r14), %rax
	movslq	(%rbx), %r15
	imulq	%rax, %r15
	movq	%r15, %rax
	shlq	$2, %rax
	testl	%r15d, %r15d
	movq	$-1, %rbx
	cmovnsq	%rax, %rbx
	movq	%rbx, %rdi
	callq	_Znam
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	movq	%rbx, %rdi
	callq	_Znam
	movq	%rax, 8(%rsp)                   # 8-byte Spill
	movq	%rbx, %rdi
	callq	_Znam
	movq	%rax, %rbx
	cmpl	$0, 96(%rsp)
	je	.LBB1_1
.LBB1_10:                               # %.loopexit
	movq	%r12, %rdi
	callq	fclose
	movq	24(%rsp), %rax                  # 8-byte Reload
	movq	16(%rsp), %rcx                  # 8-byte Reload
	movq	%rcx, (%rax)
	movq	32(%rsp), %rax                  # 8-byte Reload
	movq	8(%rsp), %rcx                   # 8-byte Reload
	movq	%rcx, (%rax)
	movq	%rbx, (%rbp)
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB1_1:                                # %.preheader38
	.cfi_def_cfa_offset 96
	testl	%r15d, %r15d
	jle	.LBB1_10
# %bb.2:                                # %.lr.ph.preheader
	movq	%rbp, (%rsp)                    # 8-byte Spill
	movl	%r15d, %r14d
	movq	%r14, %rbp
	movq	16(%rsp), %r13                  # 8-byte Reload
.LBB1_3:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	$.L.str.2, %esi
	movq	%r12, %rdi
	movq	%r13, %rdx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	addq	$4, %r13
	decq	%rbp
	jne	.LBB1_3
# %bb.4:                                # %.preheader37
	testl	%r15d, %r15d
	movq	(%rsp), %rbp                    # 8-byte Reload
	jle	.LBB1_10
# %bb.5:
	movq	%r14, %rbp
	movq	8(%rsp), %r13                   # 8-byte Reload
.LBB1_6:                                # %.lr.ph41
                                        # =>This Inner Loop Header: Depth=1
	movl	$.L.str.2, %esi
	movq	%r12, %rdi
	movq	%r13, %rdx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	addq	$4, %r13
	decq	%rbp
	jne	.LBB1_6
# %bb.7:                                # %.preheader
	testl	%r15d, %r15d
	movq	(%rsp), %rbp                    # 8-byte Reload
	jle	.LBB1_10
# %bb.8:                                # %.lr.ph43.preheader
	movq	%rbx, %r13
.LBB1_9:                                # %.lr.ph43
                                        # =>This Inner Loop Header: Depth=1
	movl	$.L.str.2, %esi
	movq	%r12, %rdi
	movq	%r13, %rdx
	xorl	%eax, %eax
	callq	__isoc23_fscanf
	addq	$4, %r13
	decq	%r14
	jne	.LBB1_9
	jmp	.LBB1_10
.Lfunc_end1:
	.size	_Z4ReadPPfS0_S0_PiS1_PKci, .Lfunc_end1-_Z4ReadPPfS0_S0_PiS1_PKci
	.cfi_endproc
                                        # -- End function
	.globl	_Z5WritePfS_S_iiPKc             # -- Begin function _Z5WritePfS_S_iiPKc
	.type	_Z5WritePfS_S_iiPKc,@function
_Z5WritePfS_S_iiPKc:                    # @_Z5WritePfS_S_iiPKc
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r8d, %r15d
	movl	%ecx, %ebp
	movq	%rdx, %r14
	movq	%rsi, %r12
	movq	%rdi, %r13
	movl	$.L.str.3, %esi
	movq	%r9, %rdi
	callq	fopen
	movq	%rax, %rbx
	movl	$.L.str.1, %esi
	movq	%rax, %rdi
	movl	%ebp, %edx
	movl	%r15d, %ecx
	xorl	%eax, %eax
	callq	fprintf
	imull	%ebp, %r15d
	leal	-1(%r15), %eax
	movl	%eax, 8(%rsp)                   # 4-byte Spill
	movl	%eax, %ebp
	movq	%r15, 16(%rsp)                  # 8-byte Spill
	cmpl	$2, %r15d
	jl	.LBB2_3
# %bb.1:                                # %.lr.ph.preheader
	xorl	%r15d, %r15d
.LBB2_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r13,%r15,4), %xmm0
	movl	$.L.str.2, %esi
	movq	%rbx, %rdi
	movb	$1, %al
	callq	fprintf
	incq	%r15
	cmpq	%r15, %rbp
	jne	.LBB2_2
.LBB2_3:                                # %._crit_edge
	movslq	8(%rsp), %r15                   # 4-byte Folded Reload
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r13,%r15,4), %xmm0
	movl	$.L.str.4, %esi
	movq	%rbx, %rdi
	movb	$1, %al
	callq	fprintf
	movq	16(%rsp), %r13                  # 8-byte Reload
	cmpl	$1, %r13d
	jle	.LBB2_4
# %bb.9:                                # %.lr.ph43.preheader
	movq	%r15, 8(%rsp)                   # 8-byte Spill
	xorl	%r15d, %r15d
.LBB2_10:                               # %.lr.ph43
                                        # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r12,%r15,4), %xmm0
	movl	$.L.str.2, %esi
	movq	%rbx, %rdi
	movb	$1, %al
	callq	fprintf
	incq	%r15
	cmpq	%r15, %rbp
	jne	.LBB2_10
# %bb.6:                                # %._crit_edge44
	movq	8(%rsp), %rax                   # 8-byte Reload
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r12,%rax,4), %xmm0
	movq	%rax, %r12
	movl	$.L.str.4, %esi
	movq	%rbx, %rdi
	movb	$1, %al
	callq	fprintf
	cmpl	$2, %r13d
	jl	.LBB2_5
# %bb.7:                                # %.lr.ph47.preheader
	xorl	%r15d, %r15d
.LBB2_8:                                # %.lr.ph47
                                        # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r14,%r15,4), %xmm0
	movl	$.L.str.2, %esi
	movq	%rbx, %rdi
	movb	$1, %al
	callq	fprintf
	incq	%r15
	cmpq	%r15, %rbp
	jne	.LBB2_8
	jmp	.LBB2_5
.LBB2_4:                                # %._crit_edge44.thread
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r12,%r15,4), %xmm0
	movl	$.L.str.4, %esi
	movq	%rbx, %rdi
	movb	$1, %al
	callq	fprintf
	movq	%r15, %r12
.LBB2_5:                                # %._crit_edge48
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r14,%r12,4), %xmm0
	movl	$.L.str.4, %esi
	movq	%rbx, %rdi
	movb	$1, %al
	callq	fprintf
	movq	%rbx, %rdi
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	fclose                          # TAILCALL
.Lfunc_end2:
	.size	_Z5WritePfS_S_iiPKc, .Lfunc_end2-_Z5WritePfS_S_iiPKc
	.cfi_endproc
                                        # -- End function
	.globl	_Z10ShowMatrixPfii              # -- Begin function _Z10ShowMatrixPfii
	.type	_Z10ShowMatrixPfii,@function
_Z10ShowMatrixPfii:                     # @_Z10ShowMatrixPfii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rdi, 8(%rsp)                   # 8-byte Spill
	testl	%esi, %esi
	jle	.LBB3_6
# %bb.1:                                # %.preheader.lr.ph
	movl	%edx, %ebx
	movl	%esi, %eax
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	movl	%edx, %r12d
	xorl	%r13d, %r13d
	xorl	%ebp, %ebp
.LBB3_2:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_4 Depth 2
	testl	%ebx, %ebx
	jle	.LBB3_5
# %bb.3:                                # %.lr.ph
                                        #   in Loop: Header=BB3_2 Depth=1
	movl	%r13d, %eax
	movq	8(%rsp), %rcx                   # 8-byte Reload
	leaq	(%rcx,%rax,4), %r14
	xorl	%r15d, %r15d
.LBB3_4:                                #   Parent Loop BB3_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r14,%r15,4), %xmm0
	movl	$.L.str.5, %edi
	movb	$1, %al
	callq	printf
	incq	%r15
	cmpq	%r15, %r12
	jne	.LBB3_4
.LBB3_5:                                # %._crit_edge
                                        #   in Loop: Header=BB3_2 Depth=1
	movl	$10, %edi
	callq	putchar@PLT
	incq	%rbp
	addl	%ebx, %r13d
	cmpq	16(%rsp), %rbp                  # 8-byte Folded Reload
	jne	.LBB3_2
.LBB3_6:                                # %._crit_edge14
	movl	$10, %edi
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	putchar@PLT                     # TAILCALL
.Lfunc_end3:
	.size	_Z10ShowMatrixPfii, .Lfunc_end3-_Z10ShowMatrixPfii
	.cfi_endproc
                                        # -- End function
	.globl	_Z14Product_MatrixPfS_ii        # -- Begin function _Z14Product_MatrixPfS_ii
	.type	_Z14Product_MatrixPfS_ii,@function
_Z14Product_MatrixPfS_ii:               # @_Z14Product_MatrixPfS_ii
	.cfi_startproc
# %bb.0:
	movl	%ecx, %eax
	movl	%edx, %ecx
	cltd
	idivl	%ecx
	movslq	%edx, %rdx
	movslq	%eax, %r8
	movslq	%ecx, %rax
	leal	2(%rdx), %ecx
	movslq	%ecx, %rcx
	leal	2(%r8), %r9d
	movslq	%r9d, %r9
	movq	%r8, %r10
	imulq	%rax, %r10
	leaq	(%rdi,%r10,4), %rdi
	shlq	$2, %rax
	decq	%rdx
	xorps	%xmm0, %xmm0
	xorl	%r10d, %r10d
.LBB4_1:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB4_2 Depth 2
	movslq	%r10d, %r10
	movq	%rdx, %r11
.LBB4_2:                                #   Parent Loop BB4_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movss	4(%rdi,%r11,4), %xmm1           # xmm1 = mem[0],zero,zero,zero
	mulss	(%rsi,%r10,4), %xmm1
	addss	%xmm1, %xmm0
	incq	%r10
	incq	%r11
	cmpq	%rcx, %r11
	jl	.LBB4_2
# %bb.3:                                #   in Loop: Header=BB4_1 Depth=1
	leaq	1(%r8), %r11
	addq	%rax, %rdi
	cmpq	%r9, %r8
	movq	%r11, %r8
	jl	.LBB4_1
# %bb.4:
	retq
.Lfunc_end4:
	.size	_Z14Product_MatrixPfS_ii, .Lfunc_end4-_Z14Product_MatrixPfS_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z26__device_stub__convolucionPfS_S_ii # -- Begin function _Z26__device_stub__convolucionPfS_S_ii
	.type	_Z26__device_stub__convolucionPfS_S_ii,@function
_Z26__device_stub__convolucionPfS_S_ii: # @_Z26__device_stub__convolucionPfS_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11convolucionPfS_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z26__device_stub__convolucionPfS_S_ii, .Lfunc_end5-_Z26__device_stub__convolucionPfS_S_ii
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__poolingPfS_i # -- Begin function _Z22__device_stub__poolingPfS_i
	.type	_Z22__device_stub__poolingPfS_i,@function
_Z22__device_stub__poolingPfS_i:        # @_Z22__device_stub__poolingPfS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7poolingPfS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z22__device_stub__poolingPfS_i, .Lfunc_end6-_Z22__device_stub__poolingPfS_i
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI7_0:
	.long	0x3b800000                      # float 0.00390625
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$216, %rsp
	.cfi_def_cfa_offset 272
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	xorps	%xmm0, %xmm0
	movaps	%xmm0, 80(%rsp)
	movaps	%xmm0, 96(%rsp)
	xorl	%eax, %eax
	movl	%eax, 112(%rsp)
	movabsq	$4575657224621260800, %rcx      # imm = 0x3F800000BF800000
	movq	%rcx, 80(%rsp)
	movl	$-1082130432, 92(%rsp)          # imm = 0xBF800000
	movl	$1065353216, 96(%rsp)           # imm = 0x3F800000
	movq	%rcx, 104(%rsp)
	movl	%eax, (%rsp)
	leaq	200(%rsp), %rdi
	leaq	192(%rsp), %rsi
	leaq	184(%rsp), %rdx
	leaq	20(%rsp), %rbx
	leaq	16(%rsp), %r8
	movl	$.L.str.7, %r9d
	movq	%rbx, %rcx
	movq	%r8, %r14
	callq	_Z4ReadPPfS0_S0_PiS1_PKci
	movslq	(%rbx), %r15
	imulq	$1431655766, %r15, %rbp         # imm = 0x55555556
	movq	%rbp, %rax
	shrq	$63, %rax
	shrq	$32, %rbp
	addl	%eax, %ebp
	movslq	(%r14), %r12
	imulq	$1431655766, %r12, %r13         # imm = 0x55555556
	movq	%r13, %rax
	shrq	$63, %rax
	shrq	$32, %r13
	addl	%eax, %r13d
	movl	%r13d, %eax
	imull	%ebp, %eax
	cltq
	leaq	(,%rax,4), %rbx
	testl	%eax, %eax
	movq	$-1, %r14
	cmovnsq	%rbx, %r14
	movq	%r14, %rdi
	callq	_Znam
	movq	%rax, 168(%rsp)                 # 8-byte Spill
	movq	%r14, %rdi
	callq	_Znam
	movq	%rax, 160(%rsp)                 # 8-byte Spill
	movq	%r14, %rdi
	callq	_Znam
	movq	%rbp, 144(%rsp)                 # 8-byte Spill
	cvtsi2ss	%ebp, %xmm1
	xorps	%xmm0, %xmm0
	cvtsi2ss	%r13d, %xmm0
	movq	%rax, 152(%rsp)                 # 8-byte Spill
	mulss	%xmm1, %xmm0
	mulss	.LCPI7_0(%rip), %xmm0
	callq	ceilf@PLT
	cvttss2si	%xmm0, %eax
	movq	%rax, 120(%rsp)                 # 8-byte Spill
	imull	%r15d, %r12d
	movslq	%r12d, %rsi
	shlq	$2, %rsi
	leaq	72(%rsp), %r15
	movq	%r15, %rdi
	callq	hipMalloc
	leaq	20(%rsp), %rbp
	movslq	(%rbp), %rax
	leaq	16(%rsp), %r14
	movslq	(%r14), %rsi
	imulq	%rax, %rsi
	shlq	$2, %rsi
	leaq	64(%rsp), %r12
	movq	%r12, %rdi
	callq	hipMalloc
	movslq	(%rbp), %rax
	movslq	(%r14), %rsi
	imulq	%rax, %rsi
	shlq	$2, %rsi
	leaq	56(%rsp), %rdi
	callq	hipMalloc
	movq	(%r15), %rdi
	movabsq	$4294967552, %r15               # imm = 0x100000100
	leaq	200(%rsp), %rax
	movq	(%rax), %rsi
	movslq	(%rbp), %rax
	movslq	(%r14), %rdx
	imulq	%rax, %rdx
	shlq	$2, %rdx
	movq	%rsi, 136(%rsp)                 # 8-byte Spill
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r12), %rdi
	leaq	192(%rsp), %rax
	movq	(%rax), %rsi
	movslq	(%rbp), %rax
	movslq	(%r14), %rdx
	imulq	%rax, %rdx
	shlq	$2, %rdx
	movq	%rsi, 128(%rsp)                 # 8-byte Spill
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	56(%rsp), %rax
	movq	(%rax), %rdi
	leaq	184(%rsp), %rax
	movq	(%rax), %rcx
	movslq	(%rbp), %rax
	movslq	(%r14), %rdx
	movq	%rcx, %r14
	imulq	%rax, %rdx
	shlq	$2, %rdx
	movq	%rcx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	48(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	leaq	40(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	leaq	32(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	leaq	176(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventCreate
	leaq	24(%rsp), %rdi
	callq	hipEventCreate
	movq	(%rbx), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	120(%rsp), %rax                 # 8-byte Reload
	leaq	(%rax,%r15), %rbx
	addq	$-256, %rbx
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_2
# %bb.1:
	movq	72(%rsp), %rdi
	movq	48(%rsp), %rsi
	movl	16(%rsp), %ecx
	leaq	80(%rsp), %rdx
	movl	%r13d, %r8d
	callq	_Z26__device_stub__convolucionPfS_S_ii
.LBB7_2:
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB7_4
# %bb.3:
	movq	64(%rsp), %rdi
	movq	40(%rsp), %rsi
	movl	16(%rsp), %ecx
	leaq	80(%rsp), %rdx
	movl	%r13d, %r8d
	callq	_Z26__device_stub__convolucionPfS_S_ii
.LBB7_4:
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	movq	168(%rsp), %r15                 # 8-byte Reload
	movq	160(%rsp), %r12                 # 8-byte Reload
	movq	152(%rsp), %rbp                 # 8-byte Reload
	jne	.LBB7_6
# %bb.5:
	movq	56(%rsp), %rdi
	movq	32(%rsp), %rsi
	movl	16(%rsp), %ecx
	leaq	80(%rsp), %rdx
	movl	%r13d, %r8d
	callq	_Z26__device_stub__convolucionPfS_S_ii
.LBB7_6:
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	24(%rsp), %rdi
	callq	hipEventSynchronize
	movq	176(%rsp), %rsi
	movq	24(%rsp), %rdx
	leaq	212(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	movq	48(%rsp), %rsi
	movslq	20(%rsp), %rax
	movslq	16(%rsp), %rdx
	imulq	%rax, %rdx
	shlq	$2, %rdx
	movq	%r15, %rdi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	40(%rsp), %rsi
	movslq	20(%rsp), %rax
	movslq	16(%rsp), %rdx
	imulq	%rax, %rdx
	shlq	$2, %rdx
	movq	%r12, %rdi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	32(%rsp), %rsi
	movslq	20(%rsp), %rax
	movslq	16(%rsp), %rdx
	imulq	%rax, %rdx
	shlq	$2, %rdx
	movq	%rbp, %rdi
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$_ZSt4cout, %edi
	movl	$.L.str.8, %esi
	movl	$8, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	cvtss2sd	(%rbx), %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movl	$.L.str.9, %esi
	movl	$4, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	(%rbx), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$.L.str.10, %r9d
	movq	%r15, %rdi
	movq	%r12, %rsi
	movq	%rbp, %rdx
	movq	144(%rsp), %rcx                 # 8-byte Reload
                                        # kill: def $ecx killed $ecx killed $rcx
	movl	%r13d, %r8d
	callq	_Z5WritePfS_S_iiPKc
	movq	72(%rsp), %rdi
	callq	hipFree
	movq	64(%rsp), %rdi
	callq	hipFree
	movq	56(%rsp), %rdi
	callq	hipFree
	movq	48(%rsp), %rdi
	callq	hipFree
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	136(%rsp), %rdi                 # 8-byte Reload
	testq	%rdi, %rdi
	je	.LBB7_8
# %bb.7:
	callq	_ZdaPv
.LBB7_8:
	movq	128(%rsp), %rdi                 # 8-byte Reload
	testq	%rdi, %rdi
	je	.LBB7_10
# %bb.9:
	callq	_ZdaPv
.LBB7_10:
	testq	%r14, %r14
	je	.LBB7_12
# %bb.11:
	movq	%r14, %rdi
	callq	_ZdaPv
.LBB7_12:
	movq	%r15, %rdi
	callq	_ZdaPv
	movq	%r12, %rdi
	callq	_ZdaPv
	movq	%rbp, %rdi
	callq	_ZdaPv
	xorl	%eax, %eax
	addq	$216, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	main, .Lfunc_end7-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB8_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB8_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11convolucionPfS_S_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7poolingPfS_i, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end8:
	.size	__hip_module_ctor, .Lfunc_end8-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB9_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB9_2:
	retq
.Lfunc_end9:
	.size	__hip_module_dtor, .Lfunc_end9-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"r"
	.size	.L.str, 2

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"%d %d\n"
	.size	.L.str.1, 7

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"%f "
	.size	.L.str.2, 4

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"w"
	.size	.L.str.3, 2

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"%f\n"
	.size	.L.str.4, 4

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"%.1f "
	.size	.L.str.5, 6

	.type	_Z11convolucionPfS_S_ii,@object # @_Z11convolucionPfS_S_ii
	.section	.rodata,"a",@progbits
	.globl	_Z11convolucionPfS_S_ii
	.p2align	3, 0x0
_Z11convolucionPfS_S_ii:
	.quad	_Z26__device_stub__convolucionPfS_S_ii
	.size	_Z11convolucionPfS_S_ii, 8

	.type	_Z7poolingPfS_i,@object         # @_Z7poolingPfS_i
	.globl	_Z7poolingPfS_i
	.p2align	3, 0x0
_Z7poolingPfS_i:
	.quad	_Z22__device_stub__poolingPfS_i
	.size	_Z7poolingPfS_i, 8

	.type	.L.str.7,@object                # @.str.7
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.7:
	.asciz	"img_test.txt"
	.size	.L.str.7, 13

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"Tiempo: "
	.size	.L.str.8, 9

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"[ms]"
	.size	.L.str.9, 5

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"resultado.txt"
	.size	.L.str.10, 14

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z11convolucionPfS_S_ii"
	.size	.L__unnamed_1, 24

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z7poolingPfS_i"
	.size	.L__unnamed_2, 16

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z26__device_stub__convolucionPfS_S_ii
	.addrsig_sym _Z22__device_stub__poolingPfS_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z11convolucionPfS_S_ii
	.addrsig_sym _Z7poolingPfS_i
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z11convolucionPfS_S_ii ; -- Begin function _Z11convolucionPfS_S_ii
	.globl	_Z11convolucionPfS_S_ii
	.p2align	8
	.type	_Z11convolucionPfS_S_ii,@function
_Z11convolucionPfS_S_ii:                ; @_Z11convolucionPfS_S_ii
; %bb.0:
	s_load_b32 s2, s[0:1], 0x2c
	s_add_u32 s8, s0, 32
	s_addc_u32 s9, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[28:29], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e32 0x9c400, v28
	s_cbranch_execz .LBB0_175
; %bb.1:
	s_load_b256 s[0:7], s[0:1], 0x0
	v_ashrrev_i32_e32 v29, 31, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v33, 0 :: v_dual_add_nc_u32 v2, v28, v29
	v_xor_b32_e32 v2, v2, v29
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s10, s7, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s11, s7, s10
	s_xor_b32 s11, s11, s10
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v0, s11
	s_sub_i32 s12, 0, s11
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_mul_lo_u32 v1, s12, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v1, v0, v1
	v_add_nc_u32_e32 v0, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v0, v2, v0
	v_mul_lo_u32 v1, v0, s11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v1, v2, v1
	v_add_nc_u32_e32 v2, 1, v0
	v_subrev_nc_u32_e32 v3, s11, v1
	v_cmp_le_u32_e32 vcc_lo, s11, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v1, v1, v3 :: v_dual_cndmask_b32 v0, v0, v2
	v_xor_b32_e32 v3, s10, v29
	v_cmp_le_u32_e32 vcc_lo, s11, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v2, 1, v0
	s_mov_b32 s11, -1
	v_cndmask_b32_e32 v0, v0, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v0, v0, v3
	v_sub_nc_u32_e32 v0, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v0, s7
	v_mul_lo_u32 v2, v0, s6
	s_add_u32 s7, s0, 4
	s_addc_u32 s10, s1, 0
	v_sub_nc_u32_e32 v1, v28, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshl_add_u32 v0, v1, 1, v1
	v_lshl_add_u32 v1, v2, 1, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_ashrrev_i32_e32 v2, 31, v0
.LBB0_2:                                ; %.preheader43
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_3 Depth 2
	s_ashr_i32 s0, s11, 31
	v_add_co_u32 v3, vcc_lo, v0, s11
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, s0, v2, vcc_lo
	v_mov_b32_e32 v5, v1
	s_mov_b64 s[0:1], 0
.LBB0_3:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v7, 31, v5
	v_add_co_u32 v6, vcc_lo, v3, v5
	s_add_u32 s12, s4, s0
	s_addc_u32 s13, s5, s1
	v_add_co_ci_u32_e32 v7, vcc_lo, v4, v7, vcc_lo
	s_load_b32 s12, s[12:13], 0x0
	v_add_nc_u32_e32 v5, s6, v5
	s_add_u32 s0, s0, 12
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	s_addc_u32 s1, s1, 0
	s_cmp_eq_u32 s0, 36
	v_add_co_u32 v6, vcc_lo, s7, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s10, v7, vcc_lo
	global_load_b32 v6, v[6:7], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fmac_f32_e32 v33, s12, v6
	s_cbranch_scc0 .LBB0_3
; %bb.4:                                ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s11, s11, 1
	s_add_u32 s4, s4, 4
	s_addc_u32 s5, s5, 0
	s_cmp_eq_u32 s11, 2
	s_cbranch_scc0 .LBB0_2
; %bb.5:
	s_load_b64 s[4:5], s[8:9], 0x50
	v_mbcnt_lo_u32_b32 v30, -1, 0
	v_mov_b32_e32 v6, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v7, 0 :: v_dual_mov_b32 v4, v30
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v4
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_11
; %bb.6:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s6, exec_lo
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[8:9], v0, s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[1:2], v0, s[4:5] offset:40
	global_load_b64 v[5:6], v0, s[4:5]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v8
	v_and_b32_e32 v2, v2, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v3, v1, 24
	v_mul_lo_u32 v2, v2, 24
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v3, v2
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v5, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
	global_load_b64 v[6:7], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[6:7], v[8:9]
	s_cbranch_execz .LBB0_10
; %bb.7:                                ; %.preheader3.i.i.i.preheader
	s_mov_b32 s7, 0
.LBB0_8:                                ; %.preheader3.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[1:2], v0, s[4:5] offset:40
	global_load_b64 v[10:11], v0, s[4:5]
	v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v1, v1, v8
	v_and_b32_e32 v7, v2, v9
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
	v_mov_b32_e32 v1, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
	v_mov_b32_e32 v6, v2
	global_load_b64 v[6:7], v[5:6], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_8
; %bb.9:                                ; %Flow380
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_10:                               ; %Flow382
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_11:                               ; %.loopexit4.i.i.i
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v5, 0
	v_readfirstlane_b32 s6, v6
	v_readfirstlane_b32 s7, v7
	s_mov_b32 s12, exec_lo
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[8:9], v5, s[4:5] offset:40
	global_load_b128 v[0:3], v5, s[4:5]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s8, v8
	v_readfirstlane_b32 s9, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[6:7], s[8:9]
	s_mul_i32 s1, s9, 24
	s_mul_hi_u32 s10, s8, 24
	s_mul_i32 s11, s8, 24
	s_and_saveexec_b32 s13, s0
	s_cbranch_execz .LBB0_13
; %bb.12:
	v_dual_mov_b32 v6, s12 :: v_dual_mov_b32 v7, v5
	s_add_i32 s12, s10, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v10, vcc_lo, v0, s11
	v_add_co_ci_u32_e32 v11, vcc_lo, s12, v1, vcc_lo
	v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
	global_store_b128 v[10:11], v[6:9], off offset:8
.LBB0_13:
	s_or_b32 exec_lo, exec_lo, s13
	s_lshl_b64 s[8:9], s[8:9], 12
	v_lshlrev_b64 v[6:7], 6, v[4:5]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v2, s8
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v2, v6
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_add_co_ci_u32_e32 v9, vcc_lo, v3, v7, vcc_lo
	v_dual_mov_b32 v4, 33 :: v_dual_mov_b32 v7, v5
	v_mov_b32_e32 v6, v5
	v_dual_mov_b32 v10, s12 :: v_dual_mov_b32 v13, s15
	v_dual_mov_b32 v11, s13 :: v_dual_mov_b32 v12, s14
	s_clause 0x3
	global_store_b128 v[8:9], v[4:7], off
	global_store_b128 v[8:9], v[10:13], off offset:16
	global_store_b128 v[8:9], v[10:13], off offset:32
	global_store_b128 v[8:9], v[10:13], off offset:48
	s_and_saveexec_b32 s8, s0
	s_cbranch_execz .LBB0_20
; %bb.14:
	v_mov_b32_e32 v10, 0
	s_mov_b32 s9, exec_lo
	s_clause 0x1
	global_load_b64 v[13:14], v10, s[4:5] offset:32 glc
	global_load_b64 v[2:3], v10, s[4:5] offset:40
	v_dual_mov_b32 v11, s6 :: v_dual_mov_b32 v12, s7
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v3, s7, v3
	v_and_b32_e32 v2, s6, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v4, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v4, v3
	v_add_co_u32 v6, vcc_lo, v0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, v1, v3, vcc_lo
	global_store_b64 v[6:7], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[13:14]
	s_cbranch_execz .LBB0_16
.LBB0_15:                               ; %.preheader1.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s12, vcc_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB0_15
.LBB0_16:                               ; %Flow378
	s_or_b32 exec_lo, exec_lo, s9
	v_mov_b32_e32 v5, 0
	s_mov_b32 s12, exec_lo
	s_mov_b32 s9, exec_lo
	v_mbcnt_lo_u32_b32 v4, s12, 0
	global_load_b64 v[2:3], v5, s[4:5] offset:16
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB0_18
; %bb.17:
	s_bcnt1_i32_b32 s12, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v4, s12
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB0_18:
	s_or_b32 exec_lo, exec_lo, s9
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB0_20
; %bb.19:
	global_load_b32 v2, v[2:3], off offset:24
	v_mov_b32_e32 v3, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s9, v2
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[2:3], off
	s_and_b32 m0, s9, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_20:                               ; %Flow379
	s_or_b32 exec_lo, exec_lo, s8
	s_add_i32 s10, s10, s1
	v_add_co_u32 v0, vcc_lo, v0, s11
	v_add_co_ci_u32_e32 v1, vcc_lo, s10, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB0_21:                               ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_23
; %bb.22:                               ;   in Loop: Header=BB0_21 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB0_23:                               ;   in Loop: Header=BB0_21 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_25
; %bb.24:                               ;   in Loop: Header=BB0_21 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_26
.LBB0_25:                               ;   in Loop: Header=BB0_21 Depth=1
	s_mov_b32 s1, -1
.LBB0_26:                               ; %Flow373
                                        ;   in Loop: Header=BB0_21 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_21
; %bb.27:
	global_load_b64 v[0:1], v[8:9], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_31
; %bb.28:
	v_mov_b32_e32 v8, 0
	s_clause 0x2
	global_load_b64 v[4:5], v8, s[4:5] offset:40
	global_load_b64 v[9:10], v8, s[4:5] offset:24 glc
	global_load_b64 v[6:7], v8, s[4:5]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v11, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v11, s6
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v12 :: v_dual_cndmask_b32 v2, v2, v11
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v2, v4
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v4, 24
	v_mul_lo_u32 v4, v4, 24
	v_add_nc_u32_e32 v5, v11, v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v9
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v10
	global_store_b64 v[6:7], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v8, v[2:5], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_31
; %bb.29:                               ; %.preheader.i.i.i.preheader
	s_mov_b32 s0, 0
.LBB0_30:                               ; %.preheader.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v8, v[2:5], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[4:5]
	v_dual_mov_b32 v4, v9 :: v_dual_mov_b32 v5, v10
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_30
.LBB0_31:                               ; %__ockl_printf_begin.exit
	s_or_b32 exec_lo, exec_lo, s1
	s_getpc_b64 s[6:7]
	s_add_u32 s6, s6, .str@rel32@lo+4
	s_addc_u32 s7, s7, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u64 s[6:7], 0
	s_cbranch_scc0 .LBB0_117
; %bb.32:
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v3, v1 :: v_dual_and_b32 v34, 2, v0
	v_dual_mov_b32 v32, 0 :: v_dual_mov_b32 v7, 1
	v_and_b32_e32 v2, -3, v0
	v_mov_b32_e32 v6, 2
	s_mov_b64 s[8:9], 4
.LBB0_33:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_36 Depth 2
                                        ;     Child Loop BB0_43 Depth 2
                                        ;     Child Loop BB0_51 Depth 2
                                        ;     Child Loop BB0_59 Depth 2
                                        ;     Child Loop BB0_67 Depth 2
                                        ;     Child Loop BB0_75 Depth 2
                                        ;     Child Loop BB0_83 Depth 2
                                        ;     Child Loop BB0_91 Depth 2
                                        ;     Child Loop BB0_99 Depth 2
                                        ;     Child Loop BB0_105 Depth 2
                                        ;     Child Loop BB0_114 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s0, s[8:9], 56
                                        ; implicit-def: $vgpr10_vgpr11
                                        ; implicit-def: $sgpr17
	s_and_b32 s0, s0, exec_lo
	s_cselect_b32 s10, s8, 56
	s_cselect_b32 s11, s9, 0
	s_cmp_gt_u32 s10, 7
	s_mov_b32 s0, -1
	s_cbranch_scc1 .LBB0_38
; %bb.34:                               ;   in Loop: Header=BB0_33 Depth=1
	v_mov_b32_e32 v10, 0
	v_mov_b32_e32 v11, 0
	s_cmp_eq_u32 s10, 0
	s_cbranch_scc1 .LBB0_37
; %bb.35:                               ; %.preheader31.i.preheader
                                        ;   in Loop: Header=BB0_33 Depth=1
	s_lshl_b64 s[0:1], s[10:11], 3
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[14:15], s[6:7]
.LBB0_36:                               ; %.preheader31.i
                                        ;   Parent Loop BB0_33 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_u8 v4, v32, s[14:15]
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v31, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s12, v[31:32]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_add_u32 s14, s14, 1
	s_addc_u32 s15, s15, 0
	s_cmp_lg_u32 s0, s12
	v_or_b32_e32 v10, v4, v10
	v_or_b32_e32 v11, v5, v11
	s_cbranch_scc1 .LBB0_36
.LBB0_37:                               ; %Flow349
                                        ;   in Loop: Header=BB0_33 Depth=1
	s_mov_b32 s0, 0
	s_mov_b32 s17, 0
.LBB0_38:                               ; %Flow351
                                        ;   in Loop: Header=BB0_33 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_mov_b64 s[0:1], s[6:7]
	s_cbranch_vccnz .LBB0_40
; %bb.39:                               ;   in Loop: Header=BB0_33 Depth=1
	global_load_b64 v[10:11], v32, s[6:7]
	s_add_i32 s17, s10, -8
	s_add_u32 s0, s6, 8
	s_addc_u32 s1, s7, 0
.LBB0_40:                               ; %.loopexit32.i
                                        ;   in Loop: Header=BB0_33 Depth=1
	s_cmp_gt_u32 s17, 7
	s_cbranch_scc1 .LBB0_45
; %bb.41:                               ;   in Loop: Header=BB0_33 Depth=1
	v_mov_b32_e32 v12, 0
	v_mov_b32_e32 v13, 0
	s_cmp_eq_u32 s17, 0
	s_cbranch_scc1 .LBB0_44
; %bb.42:                               ; %.preheader29.i.preheader
                                        ;   in Loop: Header=BB0_33 Depth=1
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[14:15], 0
.LBB0_43:                               ; %.preheader29.i
                                        ;   Parent Loop BB0_33 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s18, s0, s14
	s_addc_u32 s19, s1, s15
	s_add_u32 s14, s14, 1
	global_load_u8 v4, v32, s[18:19]
	s_addc_u32 s15, s15, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v31, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s12, v[31:32]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s17, s14
	v_or_b32_e32 v12, v4, v12
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v13, v5, v13
	s_cbranch_scc1 .LBB0_43
.LBB0_44:                               ; %Flow344
                                        ;   in Loop: Header=BB0_33 Depth=1
	s_mov_b32 s12, 0
	s_mov_b32 s16, 0
	s_branch .LBB0_46
.LBB0_45:                               ;   in Loop: Header=BB0_33 Depth=1
	s_mov_b32 s12, -1
                                        ; implicit-def: $vgpr12_vgpr13
                                        ; implicit-def: $sgpr16
.LBB0_46:                               ; %Flow346
                                        ;   in Loop: Header=BB0_33 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB0_48
; %bb.47:                               ;   in Loop: Header=BB0_33 Depth=1
	global_load_b64 v[12:13], v32, s[0:1]
	s_add_i32 s16, s17, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_48:                               ; %.loopexit30.i
                                        ;   in Loop: Header=BB0_33 Depth=1
	s_cmp_gt_u32 s16, 7
	s_cbranch_scc1 .LBB0_53
; %bb.49:                               ;   in Loop: Header=BB0_33 Depth=1
	v_mov_b32_e32 v14, 0
	v_mov_b32_e32 v15, 0
	s_cmp_eq_u32 s16, 0
	s_cbranch_scc1 .LBB0_52
; %bb.50:                               ; %.preheader27.i.preheader
                                        ;   in Loop: Header=BB0_33 Depth=1
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[14:15], 0
.LBB0_51:                               ; %.preheader27.i
                                        ;   Parent Loop BB0_33 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s18, s0, s14
	s_addc_u32 s19, s1, s15
	s_add_u32 s14, s14, 1
	global_load_u8 v4, v32, s[18:19]
	s_addc_u32 s15, s15, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v31, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s12, v[31:32]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s16, s14
	v_or_b32_e32 v14, v4, v14
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v15, v5, v15
	s_cbranch_scc1 .LBB0_51
.LBB0_52:                               ; %Flow339
                                        ;   in Loop: Header=BB0_33 Depth=1
	s_mov_b32 s12, 0
	s_mov_b32 s17, 0
	s_branch .LBB0_54
.LBB0_53:                               ;   in Loop: Header=BB0_33 Depth=1
	s_mov_b32 s12, -1
                                        ; implicit-def: $sgpr17
.LBB0_54:                               ; %Flow341
                                        ;   in Loop: Header=BB0_33 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB0_56
; %bb.55:                               ;   in Loop: Header=BB0_33 Depth=1
	global_load_b64 v[14:15], v32, s[0:1]
	s_add_i32 s17, s16, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_56:                               ; %.loopexit28.i
                                        ;   in Loop: Header=BB0_33 Depth=1
	s_cmp_gt_u32 s17, 7
	s_cbranch_scc1 .LBB0_61
; %bb.57:                               ;   in Loop: Header=BB0_33 Depth=1
	v_mov_b32_e32 v16, 0
	v_mov_b32_e32 v17, 0
	s_cmp_eq_u32 s17, 0
	s_cbranch_scc1 .LBB0_60
; %bb.58:                               ; %.preheader25.i.preheader
                                        ;   in Loop: Header=BB0_33 Depth=1
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[14:15], 0
.LBB0_59:                               ; %.preheader25.i
                                        ;   Parent Loop BB0_33 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s18, s0, s14
	s_addc_u32 s19, s1, s15
	s_add_u32 s14, s14, 1
	global_load_u8 v4, v32, s[18:19]
	s_addc_u32 s15, s15, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v31, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s12, v[31:32]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s17, s14
	v_or_b32_e32 v16, v4, v16
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v17, v5, v17
	s_cbranch_scc1 .LBB0_59
.LBB0_60:                               ; %Flow334
                                        ;   in Loop: Header=BB0_33 Depth=1
	s_mov_b32 s12, 0
	s_mov_b32 s16, 0
	s_branch .LBB0_62
.LBB0_61:                               ;   in Loop: Header=BB0_33 Depth=1
	s_mov_b32 s12, -1
                                        ; implicit-def: $vgpr16_vgpr17
                                        ; implicit-def: $sgpr16
.LBB0_62:                               ; %Flow336
                                        ;   in Loop: Header=BB0_33 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB0_64
; %bb.63:                               ;   in Loop: Header=BB0_33 Depth=1
	global_load_b64 v[16:17], v32, s[0:1]
	s_add_i32 s16, s17, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_64:                               ; %.loopexit26.i
                                        ;   in Loop: Header=BB0_33 Depth=1
	s_cmp_gt_u32 s16, 7
	s_cbranch_scc1 .LBB0_69
; %bb.65:                               ;   in Loop: Header=BB0_33 Depth=1
	v_mov_b32_e32 v18, 0
	v_mov_b32_e32 v19, 0
	s_cmp_eq_u32 s16, 0
	s_cbranch_scc1 .LBB0_68
; %bb.66:                               ; %.preheader23.i.preheader
                                        ;   in Loop: Header=BB0_33 Depth=1
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[14:15], 0
.LBB0_67:                               ; %.preheader23.i
                                        ;   Parent Loop BB0_33 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s18, s0, s14
	s_addc_u32 s19, s1, s15
	s_add_u32 s14, s14, 1
	global_load_u8 v4, v32, s[18:19]
	s_addc_u32 s15, s15, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v31, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s12, v[31:32]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s16, s14
	v_or_b32_e32 v18, v4, v18
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v19, v5, v19
	s_cbranch_scc1 .LBB0_67
.LBB0_68:                               ; %Flow329
                                        ;   in Loop: Header=BB0_33 Depth=1
	s_mov_b32 s12, 0
	s_mov_b32 s17, 0
	s_branch .LBB0_70
.LBB0_69:                               ;   in Loop: Header=BB0_33 Depth=1
	s_mov_b32 s12, -1
                                        ; implicit-def: $sgpr17
.LBB0_70:                               ; %Flow331
                                        ;   in Loop: Header=BB0_33 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB0_72
; %bb.71:                               ;   in Loop: Header=BB0_33 Depth=1
	global_load_b64 v[18:19], v32, s[0:1]
	s_add_i32 s17, s16, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_72:                               ; %.loopexit24.i
                                        ;   in Loop: Header=BB0_33 Depth=1
	s_cmp_gt_u32 s17, 7
	s_cbranch_scc1 .LBB0_77
; %bb.73:                               ;   in Loop: Header=BB0_33 Depth=1
	v_mov_b32_e32 v20, 0
	v_mov_b32_e32 v21, 0
	s_cmp_eq_u32 s17, 0
	s_cbranch_scc1 .LBB0_76
; %bb.74:                               ; %.preheader21.i.preheader
                                        ;   in Loop: Header=BB0_33 Depth=1
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[14:15], 0
.LBB0_75:                               ; %.preheader21.i
                                        ;   Parent Loop BB0_33 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s18, s0, s14
	s_addc_u32 s19, s1, s15
	s_add_u32 s14, s14, 1
	global_load_u8 v4, v32, s[18:19]
	s_addc_u32 s15, s15, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v31, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s12, v[31:32]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s17, s14
	v_or_b32_e32 v20, v4, v20
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v21, v5, v21
	s_cbranch_scc1 .LBB0_75
.LBB0_76:                               ; %Flow324
                                        ;   in Loop: Header=BB0_33 Depth=1
	s_mov_b32 s12, 0
	s_mov_b32 s16, 0
	s_branch .LBB0_78
.LBB0_77:                               ;   in Loop: Header=BB0_33 Depth=1
	s_mov_b32 s12, -1
                                        ; implicit-def: $vgpr20_vgpr21
                                        ; implicit-def: $sgpr16
.LBB0_78:                               ; %Flow326
                                        ;   in Loop: Header=BB0_33 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB0_80
; %bb.79:                               ;   in Loop: Header=BB0_33 Depth=1
	global_load_b64 v[20:21], v32, s[0:1]
	s_add_i32 s16, s17, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_80:                               ; %.loopexit22.i
                                        ;   in Loop: Header=BB0_33 Depth=1
	s_cmp_gt_u32 s16, 7
	s_cbranch_scc1 .LBB0_85
; %bb.81:                               ;   in Loop: Header=BB0_33 Depth=1
	v_mov_b32_e32 v22, 0
	v_mov_b32_e32 v23, 0
	s_cmp_eq_u32 s16, 0
	s_cbranch_scc1 .LBB0_84
; %bb.82:                               ; %.preheader.i.preheader
                                        ;   in Loop: Header=BB0_33 Depth=1
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[14:15], s[0:1]
.LBB0_83:                               ; %.preheader.i
                                        ;   Parent Loop BB0_33 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_u8 v4, v32, s[14:15]
	s_add_i32 s16, s16, -1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v31, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s12, v[31:32]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_add_u32 s14, s14, 1
	s_addc_u32 s15, s15, 0
	s_cmp_lg_u32 s16, 0
	v_or_b32_e32 v22, v4, v22
	v_or_b32_e32 v23, v5, v23
	s_cbranch_scc1 .LBB0_83
.LBB0_84:                               ; %Flow319
                                        ;   in Loop: Header=BB0_33 Depth=1
	s_mov_b32 s12, 0
	s_branch .LBB0_86
.LBB0_85:                               ;   in Loop: Header=BB0_33 Depth=1
	s_mov_b32 s12, -1
.LBB0_86:                               ; %Flow321
                                        ;   in Loop: Header=BB0_33 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB0_88
; %bb.87:                               ;   in Loop: Header=BB0_33 Depth=1
	global_load_b64 v[22:23], v32, s[0:1]
.LBB0_88:                               ; %.loopexit.i
                                        ;   in Loop: Header=BB0_33 Depth=1
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v31, v30 :: v_dual_mov_b32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v31
	v_mov_b32_e32 v5, 0
	v_cmp_eq_u32_e64 s0, s0, v31
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_94
; %bb.89:                               ;   in Loop: Header=BB0_33 Depth=1
	global_load_b64 v[26:27], v32, s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[4:5], v32, s[4:5] offset:40
	global_load_b64 v[8:9], v32, s[4:5]
	s_mov_b32 s12, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v5, v5, v27
	v_and_b32_e32 v4, v4, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v5, v5, 24
	v_mul_hi_u32 v24, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v24, v5
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v8, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v9, v5, vcc_lo
	global_load_b64 v[24:25], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v32, v[24:27], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[4:5], v[26:27]
	s_cbranch_execz .LBB0_93
; %bb.90:                               ; %.preheader3.i.i19.i.preheader
                                        ;   in Loop: Header=BB0_33 Depth=1
	s_mov_b32 s13, 0
.LBB0_91:                               ; %.preheader3.i.i19.i
                                        ;   Parent Loop BB0_33 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[8:9], v32, s[4:5] offset:40
	global_load_b64 v[24:25], v32, s[4:5]
	v_dual_mov_b32 v27, v5 :: v_dual_mov_b32 v26, v4
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v8, v8, v26
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[4:5], null, v8, 24, v[24:25]
	v_and_b32_e32 v24, v9, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v24, 24, v[5:6]
	v_mov_b32_e32 v5, v8
	global_load_b64 v[24:25], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v32, v[24:27], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[26:27]
	s_or_b32 s13, vcc_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_91
; %bb.92:                               ; %Flow314
                                        ;   in Loop: Header=BB0_33 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
.LBB0_93:                               ; %Flow316
                                        ;   in Loop: Header=BB0_33 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s12
.LBB0_94:                               ; %.loopexit4.i.i14.i
                                        ;   in Loop: Header=BB0_33 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[8:9], v32, s[4:5] offset:40
	global_load_b128 v[24:27], v32, s[4:5]
	v_readfirstlane_b32 s12, v4
	v_readfirstlane_b32 s13, v5
	s_mov_b32 s18, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s14, v8
	v_readfirstlane_b32 s15, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[14:15], s[12:13], s[14:15]
	s_mul_i32 s1, s15, 24
	s_mul_hi_u32 s16, s14, 24
	s_mul_i32 s17, s14, 24
	s_and_saveexec_b32 s19, s0
	s_cbranch_execz .LBB0_96
; %bb.95:                               ;   in Loop: Header=BB0_33 Depth=1
	v_dual_mov_b32 v4, s18 :: v_dual_mov_b32 v5, v32
	s_add_i32 s18, s16, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v8, vcc_lo, v24, s17
	v_add_co_ci_u32_e32 v9, vcc_lo, s18, v25, vcc_lo
	global_store_b128 v[8:9], v[4:7], off offset:8
.LBB0_96:                               ;   in Loop: Header=BB0_33 Depth=1
	s_or_b32 exec_lo, exec_lo, s19
	v_cmp_gt_u64_e64 vcc_lo, s[8:9], 56
	v_or_b32_e32 v4, 0, v3
	v_or_b32_e32 v5, v2, v34
	s_lshl_b64 s[14:15], s[14:15], 12
	s_lshl_b32 s18, s10, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s18, s18, 28
	v_dual_cndmask_b32 v9, v4, v3 :: v_dual_cndmask_b32 v4, v5, v2
	v_lshlrev_b64 v[2:3], 6, v[31:32]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v26, s14
	v_add_co_ci_u32_e32 v27, vcc_lo, s15, v27, vcc_lo
	s_and_b32 s18, s18, 0x1e0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v26, vcc_lo, v5, v2
	v_and_or_b32 v8, 0xffffff1f, v4, s18
	v_add_co_ci_u32_e32 v27, vcc_lo, v27, v3, vcc_lo
	s_clause 0x3
	global_store_b128 v[26:27], v[8:11], off
	global_store_b128 v[26:27], v[12:15], off offset:16
	global_store_b128 v[26:27], v[16:19], off offset:32
	global_store_b128 v[26:27], v[20:23], off offset:48
	s_and_saveexec_b32 s14, s0
	s_cbranch_execz .LBB0_104
; %bb.97:                               ;   in Loop: Header=BB0_33 Depth=1
	s_clause 0x1
	global_load_b64 v[12:13], v32, s[4:5] offset:32 glc
	global_load_b64 v[2:3], v32, s[4:5] offset:40
	v_dual_mov_b32 v10, s12 :: v_dual_mov_b32 v11, s13
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s18, v2
	v_readfirstlane_b32 s19, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[18:19], s[18:19], s[12:13]
	s_mul_i32 s15, s19, 24
	s_mul_hi_u32 s19, s18, 24
	s_mul_i32 s18, s18, 24
	s_add_i32 s19, s19, s15
	v_add_co_u32 v8, vcc_lo, v24, s18
	v_add_co_ci_u32_e32 v9, vcc_lo, s19, v25, vcc_lo
	s_mov_b32 s15, exec_lo
	global_store_b64 v[8:9], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v32, v[10:13], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[12:13]
	s_cbranch_execz .LBB0_100
; %bb.98:                               ; %.preheader1.i.i17.i.preheader
                                        ;   in Loop: Header=BB0_33 Depth=1
	s_mov_b32 s18, 0
.LBB0_99:                               ; %.preheader1.i.i17.i
                                        ;   Parent Loop BB0_33 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v2, s12 :: v_dual_mov_b32 v3, s13
	s_sleep 1
	global_store_b64 v[8:9], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v32, v[2:5], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s18, vcc_lo, s18
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s18
	s_cbranch_execnz .LBB0_99
.LBB0_100:                              ; %Flow312
                                        ;   in Loop: Header=BB0_33 Depth=1
	s_or_b32 exec_lo, exec_lo, s15
	global_load_b64 v[2:3], v32, s[4:5] offset:16
	s_mov_b32 s18, exec_lo
	s_mov_b32 s15, exec_lo
	v_mbcnt_lo_u32_b32 v4, s18, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB0_102
; %bb.101:                              ;   in Loop: Header=BB0_33 Depth=1
	s_bcnt1_i32_b32 s18, s18
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v31, s18
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[31:32], off offset:8
.LBB0_102:                              ;   in Loop: Header=BB0_33 Depth=1
	s_or_b32 exec_lo, exec_lo, s15
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB0_104
; %bb.103:                              ;   in Loop: Header=BB0_33 Depth=1
	global_load_b32 v31, v[2:3], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s15, v31
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[31:32], off
	s_and_b32 m0, s15, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_104:                              ; %Flow313
                                        ;   in Loop: Header=BB0_33 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	s_add_i32 s16, s16, s1
	v_add_co_u32 v2, vcc_lo, v24, s17
	v_add_co_ci_u32_e32 v3, vcc_lo, s16, v25, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v2, 20
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
.LBB0_105:                              ;   Parent Loop BB0_33 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v4, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_107
; %bb.106:                              ;   in Loop: Header=BB0_105 Depth=2
	global_load_b32 v4, v[2:3], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v4, 1, v4
.LBB0_107:                              ;   in Loop: Header=BB0_105 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v4
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_109
; %bb.108:                              ;   in Loop: Header=BB0_105 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_110
.LBB0_109:                              ;   in Loop: Header=BB0_105 Depth=2
	s_mov_b32 s1, -1
.LBB0_110:                              ; %Flow307
                                        ;   in Loop: Header=BB0_105 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_105
; %bb.111:                              ;   in Loop: Header=BB0_33 Depth=1
	global_load_b128 v[2:5], v[26:27], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_115
; %bb.112:                              ;   in Loop: Header=BB0_33 Depth=1
	s_clause 0x2
	global_load_b64 v[4:5], v32, s[4:5] offset:40
	global_load_b64 v[12:13], v32, s[4:5] offset:24 glc
	global_load_b64 v[10:11], v32, s[4:5]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v14, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v14, s12
	v_add_co_ci_u32_e32 v9, vcc_lo, s13, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[8:9]
	v_dual_cndmask_b32 v9, v9, v15 :: v_dual_cndmask_b32 v8, v8, v14
	v_and_b32_e32 v5, v9, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, v8, v4
	v_mul_hi_u32 v14, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v4, vcc_lo, v10, v4
	v_mov_b32_e32 v10, v12
	v_mul_lo_u32 v5, v5, 24
	v_add_nc_u32_e32 v5, v14, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, v11, v5, vcc_lo
	v_mov_b32_e32 v11, v13
	global_store_b64 v[4:5], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v32, v[8:11], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[10:11], v[12:13]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_115
; %bb.113:                              ; %.preheader.i.i16.i.preheader
                                        ;   in Loop: Header=BB0_33 Depth=1
	s_mov_b32 s0, 0
.LBB0_114:                              ; %.preheader.i.i16.i
                                        ;   Parent Loop BB0_33 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[4:5], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[12:13], v32, v[8:11], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[12:13], v[10:11]
	v_dual_mov_b32 v10, v12 :: v_dual_mov_b32 v11, v13
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_114
.LBB0_115:                              ; %__ockl_hostcall_preview.exit20.i
                                        ;   in Loop: Header=BB0_33 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_sub_u32 s8, s8, s10
	s_subb_u32 s9, s9, s11
	s_add_u32 s6, s6, s10
	s_addc_u32 s7, s7, s11
	s_cmp_lg_u64 s[8:9], 0
	s_cbranch_scc1 .LBB0_33
; %bb.116:                              ; %Flow352
	s_mov_b32 s0, 0
	s_branch .LBB0_118
.LBB0_117:
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr2_vgpr3
.LBB0_118:                              ; %Flow367
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB0_147
; %bb.119:
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v2, v30
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v2
	v_cmp_eq_u32_e64 s0, s0, v2
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_125
; %bb.120:
	v_mov_b32_e32 v3, 0
	s_mov_b32 s6, exec_lo
	global_load_b64 v[6:7], v3, s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[4:5] offset:40
	global_load_b64 v[8:9], v3, s[4:5]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v6
	v_and_b32_e32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v10, v4, 24
	v_mul_lo_u32 v5, v5, 24
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v10, v5
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v8, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v9, v5, vcc_lo
	global_load_b64 v[4:5], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v3, v[4:7], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[8:9], v[6:7]
	s_cbranch_execz .LBB0_124
; %bb.121:                              ; %.preheader3.i.i.i35.preheader
	s_mov_b32 s7, 0
.LBB0_122:                              ; %.preheader3.i.i.i35
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[4:5] offset:40
	global_load_b64 v[10:11], v3, s[4:5]
	v_dual_mov_b32 v6, v8 :: v_dual_mov_b32 v7, v9
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v4, v6
	v_and_b32_e32 v5, v5, v7
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v4, 24, v[10:11]
	v_mov_b32_e32 v4, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, v5, 24, v[4:5]
	global_load_b64 v[4:5], v[8:9], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v3, v[4:7], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[6:7]
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_122
; %bb.123:                              ; %Flow364
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_124:                              ; %Flow366
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_125:                              ; %.loopexit4.i.i.i30
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v3, 0
	v_readfirstlane_b32 s6, v8
	v_readfirstlane_b32 s7, v9
	s_mov_b32 s12, exec_lo
	s_clause 0x1
	global_load_b64 v[10:11], v3, s[4:5] offset:40
	global_load_b128 v[4:7], v3, s[4:5]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s8, v10
	v_readfirstlane_b32 s9, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[6:7], s[8:9]
	s_mul_i32 s1, s9, 24
	s_mul_hi_u32 s10, s8, 24
	s_mul_i32 s11, s8, 24
	s_and_saveexec_b32 s13, s0
	s_cbranch_execz .LBB0_127
; %bb.126:
	v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v9, v3
	s_add_i32 s12, s10, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v12, vcc_lo, v4, s11
	v_add_co_ci_u32_e32 v13, vcc_lo, s12, v5, vcc_lo
	v_dual_mov_b32 v10, 2 :: v_dual_mov_b32 v11, 1
	global_store_b128 v[12:13], v[8:11], off offset:8
.LBB0_127:
	s_or_b32 exec_lo, exec_lo, s13
	s_lshl_b64 s[8:9], s[8:9], 12
	v_lshlrev_b64 v[8:9], 6, v[2:3]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v6, s8
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v2, v8
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_and_or_b32 v0, 0xffffff1f, v0, 32
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v9, vcc_lo
	v_mov_b32_e32 v2, v3
	v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v11, s15
	v_dual_mov_b32 v9, s13 :: v_dual_mov_b32 v10, s14
	s_clause 0x3
	global_store_b128 v[6:7], v[0:3], off
	global_store_b128 v[6:7], v[8:11], off offset:16
	global_store_b128 v[6:7], v[8:11], off offset:32
	global_store_b128 v[6:7], v[8:11], off offset:48
	s_and_saveexec_b32 s8, s0
	s_cbranch_execz .LBB0_135
; %bb.128:
	v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s6
	v_mov_b32_e32 v12, s7
	s_clause 0x1
	global_load_b64 v[13:14], v10, s[4:5] offset:32 glc
	global_load_b64 v[0:1], v10, s[4:5] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s12, v0
	v_readfirstlane_b32 s13, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[12:13], s[12:13], s[6:7]
	s_mul_i32 s9, s13, 24
	s_mul_hi_u32 s13, s12, 24
	s_mul_i32 s12, s12, 24
	s_add_i32 s13, s13, s9
	v_add_co_u32 v8, vcc_lo, v4, s12
	v_add_co_ci_u32_e32 v9, vcc_lo, s13, v5, vcc_lo
	s_mov_b32 s9, exec_lo
	global_store_b64 v[8:9], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v10, v[11:14], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[13:14]
	s_cbranch_execz .LBB0_131
; %bb.129:                              ; %.preheader1.i.i.i33.preheader
	s_mov_b32 s12, 0
.LBB0_130:                              ; %.preheader1.i.i.i33
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
	s_sleep 1
	global_store_b64 v[8:9], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v10, v[0:3], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s12, vcc_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB0_130
.LBB0_131:                              ; %Flow362
	s_or_b32 exec_lo, exec_lo, s9
	v_mov_b32_e32 v3, 0
	s_mov_b32 s12, exec_lo
	s_mov_b32 s9, exec_lo
	v_mbcnt_lo_u32_b32 v2, s12, 0
	global_load_b64 v[0:1], v3, s[4:5] offset:16
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB0_133
; %bb.132:
	s_bcnt1_i32_b32 s12, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s12
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_133:
	s_or_b32 exec_lo, exec_lo, s9
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB0_135
; %bb.134:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s9, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[0:1], off
	s_and_b32 m0, s9, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_135:                              ; %Flow363
	s_or_b32 exec_lo, exec_lo, s8
	s_add_i32 s10, s10, s1
	v_add_co_u32 v0, vcc_lo, v4, s11
	v_add_co_ci_u32_e32 v1, vcc_lo, s10, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB0_136:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_138
; %bb.137:                              ;   in Loop: Header=BB0_136 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB0_138:                              ;   in Loop: Header=BB0_136 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_140
; %bb.139:                              ;   in Loop: Header=BB0_136 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_141
.LBB0_140:                              ;   in Loop: Header=BB0_136 Depth=1
	s_mov_b32 s1, -1
.LBB0_141:                              ; %Flow357
                                        ;   in Loop: Header=BB0_136 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_136
; %bb.142:
	global_load_b128 v[2:5], v[6:7], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_146
; %bb.143:
	v_mov_b32_e32 v8, 0
	s_clause 0x2
	global_load_b64 v[0:1], v8, s[4:5] offset:40
	global_load_b64 v[9:10], v8, s[4:5] offset:24 glc
	global_load_b64 v[6:7], v8, s[4:5]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v11, vcc_lo, v0, 1
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v11, s6
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	v_dual_cndmask_b32 v5, v5, v12 :: v_dual_cndmask_b32 v4, v4, v11
	v_and_b32_e32 v1, v5, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v4, v0
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v0, 24
	v_mul_lo_u32 v0, v0, 24
	v_add_nc_u32_e32 v1, v11, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v6, v0
	v_mov_b32_e32 v6, v9
	v_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo
	v_mov_b32_e32 v7, v10
	global_store_b64 v[0:1], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v8, v[4:7], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[6:7], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_146
; %bb.144:                              ; %.preheader.i.i.i32.preheader
	s_mov_b32 s0, 0
.LBB0_145:                              ; %.preheader.i.i.i32
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[0:1], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v8, v[4:7], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[6:7]
	v_dual_mov_b32 v6, v9 :: v_dual_mov_b32 v7, v10
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_145
.LBB0_146:                              ; %__ockl_hostcall_preview.exit.i
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_147:                              ; %__ockl_printf_append_string_n.exit
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v30
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v30
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_153
; %bb.148:
	v_mov_b32_e32 v4, 0
	s_mov_b32 s6, exec_lo
	global_load_b64 v[7:8], v4, s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v4, s[4:5] offset:40
	global_load_b64 v[5:6], v4, s[4:5]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v8
	v_and_b32_e32 v0, v0, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v9, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v9, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v5, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v6, v1, vcc_lo
	global_load_b64 v[5:6], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v4, v[5:8], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[0:1], v[7:8]
	s_cbranch_execz .LBB0_152
; %bb.149:                              ; %.preheader3.i.i.i42.preheader
	s_mov_b32 s7, 0
.LBB0_150:                              ; %.preheader3.i.i.i42
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[5:6], v4, s[4:5] offset:40
	global_load_b64 v[9:10], v4, s[4:5]
	v_dual_mov_b32 v8, v1 :: v_dual_mov_b32 v7, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v5, v5, v7
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[0:1], null, v5, 24, v[9:10]
	v_and_b32_e32 v9, v6, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v9, 24, v[1:2]
	v_mov_b32_e32 v1, v5
	global_load_b64 v[5:6], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v4, v[5:8], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[7:8]
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB0_150
; %bb.151:                              ; %Flow300
	s_or_b32 exec_lo, exec_lo, s7
.LBB0_152:                              ; %Flow302
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
.LBB0_153:                              ; %.loopexit4.i.i.i36
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v31, 0
	v_readfirstlane_b32 s6, v0
	v_readfirstlane_b32 s7, v1
	s_mov_b32 s12, exec_lo
	s_clause 0x1
	global_load_b64 v[4:5], v31, s[4:5] offset:40
	global_load_b128 v[6:9], v31, s[4:5]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s8, v4
	v_readfirstlane_b32 s9, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[6:7], s[8:9]
	s_mul_i32 s1, s9, 24
	s_mul_hi_u32 s10, s8, 24
	s_mul_i32 s11, s8, 24
	s_and_saveexec_b32 s13, s0
	s_cbranch_execz .LBB0_155
; %bb.154:
	v_dual_mov_b32 v10, s12 :: v_dual_mov_b32 v11, v31
	s_add_i32 s12, s10, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v6, s11
	v_add_co_ci_u32_e32 v1, vcc_lo, s12, v7, vcc_lo
	v_dual_mov_b32 v12, 2 :: v_dual_mov_b32 v13, 1
	global_store_b128 v[0:1], v[10:13], off offset:8
.LBB0_155:
	s_or_b32 exec_lo, exec_lo, s13
	v_cvt_f64_f32_e32 v[4:5], v33
	s_lshl_b64 s[8:9], s[8:9], 12
	v_lshlrev_b64 v[0:1], 6, v[30:31]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v8, vcc_lo, v8, s8
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v8, v0
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_and_or_b32 v2, 0xffffff1d, v2, 34
	v_add_co_ci_u32_e32 v1, vcc_lo, v9, v1, vcc_lo
	v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v9, s13
	v_dual_mov_b32 v10, s14 :: v_dual_mov_b32 v11, s15
	s_clause 0x3
	global_store_b128 v[0:1], v[2:5], off
	global_store_b128 v[0:1], v[8:11], off offset:16
	global_store_b128 v[0:1], v[8:11], off offset:32
	global_store_b128 v[0:1], v[8:11], off offset:48
	s_and_saveexec_b32 s8, s0
	s_cbranch_execz .LBB0_163
; %bb.156:
	v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s6
	v_mov_b32_e32 v10, s7
	s_clause 0x1
	global_load_b64 v[11:12], v8, s[4:5] offset:32 glc
	global_load_b64 v[0:1], v8, s[4:5] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s12, v0
	v_readfirstlane_b32 s13, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[12:13], s[12:13], s[6:7]
	s_mul_i32 s9, s13, 24
	s_mul_hi_u32 s13, s12, 24
	s_mul_i32 s12, s12, 24
	s_add_i32 s13, s13, s9
	v_add_co_u32 v4, vcc_lo, v6, s12
	v_add_co_ci_u32_e32 v5, vcc_lo, s13, v7, vcc_lo
	s_mov_b32 s9, exec_lo
	global_store_b64 v[4:5], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v8, v[9:12], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[11:12]
	s_cbranch_execz .LBB0_159
; %bb.157:                              ; %.preheader1.i.i.i40.preheader
	s_mov_b32 s12, 0
.LBB0_158:                              ; %.preheader1.i.i.i40
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v8, v[0:3], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s12, vcc_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB0_158
.LBB0_159:                              ; %Flow298
	s_or_b32 exec_lo, exec_lo, s9
	v_mov_b32_e32 v3, 0
	s_mov_b32 s12, exec_lo
	s_mov_b32 s9, exec_lo
	v_mbcnt_lo_u32_b32 v2, s12, 0
	global_load_b64 v[0:1], v3, s[4:5] offset:16
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB0_161
; %bb.160:
	s_bcnt1_i32_b32 s12, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s12
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB0_161:
	s_or_b32 exec_lo, exec_lo, s9
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB0_163
; %bb.162:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s9, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[0:1], off
	s_and_b32 m0, s9, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_163:                              ; %Flow299
	s_or_b32 exec_lo, exec_lo, s8
	s_add_i32 s10, s10, s1
	v_add_co_u32 v0, vcc_lo, v6, s11
	v_add_co_ci_u32_e32 v1, vcc_lo, s10, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB0_164:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_166
; %bb.165:                              ;   in Loop: Header=BB0_164 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB0_166:                              ;   in Loop: Header=BB0_164 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_168
; %bb.167:                              ;   in Loop: Header=BB0_164 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_169
.LBB0_168:                              ;   in Loop: Header=BB0_164 Depth=1
	s_mov_b32 s1, -1
.LBB0_169:                              ; %Flow293
                                        ;   in Loop: Header=BB0_164 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_164
; %bb.170:
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_174
; %bb.171:
	v_mov_b32_e32 v6, 0
	s_clause 0x2
	global_load_b64 v[2:3], v6, s[4:5] offset:40
	global_load_b64 v[7:8], v6, s[4:5] offset:24 glc
	global_load_b64 v[4:5], v6, s[4:5]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v9, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v9, s6
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
	v_and_b32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v2, v0, v2
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v9, v2, 24
	v_mul_lo_u32 v2, v2, 24
	v_add_nc_u32_e32 v3, v9, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, v4, v2
	v_mov_b32_e32 v2, v7
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
	v_mov_b32_e32 v3, v8
	global_store_b64 v[4:5], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_174
; %bb.172:                              ; %.preheader.i.i.i39.preheader
	s_mov_b32 s0, 0
.LBB0_173:                              ; %.preheader.i.i.i39
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
	v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_173
.LBB0_174:                              ; %__ockl_printf_append_args.exit
	s_or_b32 exec_lo, exec_lo, s1
	v_lshlrev_b64 v[0:1], 2, v[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_store_b32 v[0:1], v33, off
.LBB0_175:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11convolucionPfS_S_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 35
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z11convolucionPfS_S_ii, .Lfunc_end0-_Z11convolucionPfS_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 7160
; NumSgprs: 22
; NumVgprs: 35
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 35
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z7poolingPfS_i         ; -- Begin function _Z7poolingPfS_i
	.globl	_Z7poolingPfS_i
	.p2align	8
	.type	_Z7poolingPfS_i,@function
_Z7poolingPfS_i:                        ; @_Z7poolingPfS_i
; %bb.0:
	s_load_b32 s2, s[0:1], 0x24
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e32 0x27100, v1
	s_cbranch_execz .LBB1_4
; %bb.1:
	s_load_b32 s4, s[0:1], 0x10
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, v1, v2
	v_xor_b32_e32 v4, v4, v2
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s2, s4, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s3, s4, s2
	s_xor_b32 s3, s3, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v0, s3
	s_sub_i32 s5, 0, s3
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_mul_lo_u32 v3, s5, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v0, v3
	v_add_nc_u32_e32 v0, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v0, v4, v0
	v_mul_lo_u32 v3, v0, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v3, v4, v3
	v_add_nc_u32_e32 v4, 1, v0
	v_subrev_nc_u32_e32 v5, s3, v3
	v_cmp_le_u32_e32 vcc_lo, s3, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
	v_xor_b32_e32 v5, s2, v2
	v_cmp_le_u32_e32 vcc_lo, s3, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, 1, v0
	s_load_b128 s[0:3], s[0:1], 0x0
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v0, v0, v5
	v_sub_nc_u32_e32 v0, v0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v0, v0, s4
	v_mad_u64_u32 v[3:4], null, v0, 3, s[4:5]
	v_sub_nc_u32_e32 v0, v1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshl_add_u32 v0, v0, 1, v0
	v_add_nc_u32_e32 v5, s4, v3
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v6, 31, v0
	v_ashrrev_i32_e32 v7, 31, v5
	v_add_co_u32 v3, vcc_lo, v3, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v4, vcc_lo, v4, v6, vcc_lo
	v_add_co_u32 v5, vcc_lo, v5, v0
	v_add_co_ci_u32_e32 v6, vcc_lo, v7, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	v_mov_b32_e32 v0, 0
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, s0, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s1, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s0, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
	s_clause 0x1
	global_load_b64 v[3:4], v[3:4], off offset:4
	global_load_b64 v[5:6], v[5:6], off offset:4
	s_mov_b64 s[0:1], 0
.LBB1_2:                                ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_eq_u32 s0, 1
	v_cvt_f32_i32_e32 v8, v0
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 2
	s_waitcnt vmcnt(1)
	v_cndmask_b32_e32 v7, v3, v4, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_cmp_eq_u32 s0, 3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e32 v7, v7, v5, vcc_lo
	s_cselect_b32 vcc_lo, -1, 0
	s_add_u32 s0, s0, 1
	s_addc_u32 s1, s1, 0
	s_cmp_lg_u32 s0, 4
	v_cndmask_b32_e32 v7, v7, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_i32_f32_e32 v9, v7
	v_cmp_gt_f32_e32 vcc_lo, v7, v8
	v_cndmask_b32_e32 v0, v0, v9, vcc_lo
	s_cbranch_scc1 .LBB1_2
; %bb.3:                                ; %_Z8max_poolPfiii.exit
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f32_i32_e32 v3, v0
	v_add_co_u32 v0, vcc_lo, s2, v1
	s_delay_alu instid0(VALU_DEP_3)
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v2, vcc_lo
	global_store_b32 v[0:1], v3, off
.LBB1_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7poolingPfS_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z7poolingPfS_i, .Lfunc_end1-_Z7poolingPfS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 552
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	.str,@object                    ; @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.str:
	.asciz	"%f\n"
	.size	.str, 4

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
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    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
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    .max_flat_workgroup_size: 1024
    .name:           _Z11convolucionPfS_S_ii
    .private_segment_fixed_size: 0
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    .sgpr_spill_count: 0
    .symbol:         _Z11convolucionPfS_S_ii.kd
    .uniform_work_group_size: 1
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    .vgpr_count:     35
    .vgpr_spill_count: 0
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amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
