/***************************************************************************//**
 * \file initialise.cu
 * \author Christopher Minar (minarc@oregonstate.edu)
 */

#include "initialise.h"

namespace kernels
{
/*
 * sets all the initial u values
 * param u u velocities
 * param xu x locations of where u is stored
 * param yu y locations of where u is stored
 * param uInitial initial u velocity
 * param uPerturb perturbation coefficient
 * param pi... //flag
 * param xmax highest x value in the domain
 * param xmin lowest x value in the domain
 * param ymax highest y value in the domain
 * param ymin lowest yvalue in the domain
 * nx number of nodes in the x direction
 * ny number of nodes in the y direction
 */
__global__
void initialiseU(double *u, double *xu, double *yu, double uInitial, double uPerturb, double pi, double xmax, double xmin,double ymax,double ymin, int nx, int ny)
{
	if (threadIdx.x + (blockDim.x * blockIdx.x) >= (nx-1)*ny)
			return;
	int 	idx 	= threadIdx.x + (blockDim.x * blockIdx.x),
			i = idx%(nx-1),
			j = idx/(nx-1);

	u[idx] = uInitial + uPerturb * cos(0.5*pi*(2*xu[i]-xmax-xmin)/(xmax-xmin)) * sin( pi * (2*yu[j]-ymax-ymin)/(ymax-ymin));
}

/*
 * sets all the initial v values
 * param u v velocities
 * param xv x locations of where v is stored
 * param yv y locations of where v is stored
 * param vInitial initial v velocity
 * param vPerturb perturbation coefficient
 * param pi... //flag
 * param xmax highest x value in the domain
 * param xmin lowest x value in the domain
 * param ymax highest y value in the domain
 * param ymin lowest yvalue in the domain
 * nx number of nodes in the x direction
 * ny number of nodes in the y direction
 */
__global__
void initialiseV(double *u, double *xv, double *yv, double vInitial, double vPerturb, double pi, double xmax, double xmin,double ymax,double ymin, int nx, int ny)
{
	if (threadIdx.x + (blockDim.x * blockIdx.x) >= nx*(ny-1))
		return;
	int 	idx 	= threadIdx.x + (blockDim.x * blockIdx.x),
			i = idx%nx,
			j = idx/nx;
	idx +=  (nx-1)*ny;

	u[idx] = vInitial + vPerturb * cos(0.5*pi*(2*yv[j]-ymax-ymin)/(ymax-ymin)) * sin( pi * (2*xv[i]-xmax-xmin)/(xmax-xmin));
}
}

	.file	"tmpxft_002e5be3_00000000-6_initialise.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z56__device_stub__ZN7kernels11initialiseUEPdS0_S0_dddddddiiPdS_S_dddddddii
	.type	_Z56__device_stub__ZN7kernels11initialiseUEPdS0_S0_dddddddiiPdS_S_dddddddii, @function
_Z56__device_stub__ZN7kernels11initialiseUEPdS0_S0_dddddddiiPdS_S_dddddddii:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$280, %rsp
	.cfi_def_cfa_offset 288
	movq	%rdi, 88(%rsp)
	leaq	120(%rsp), %rdi
	movq	%rsi, 80(%rsp)
	leaq	132(%rsp), %rsi
	movq	%rdx, 72(%rsp)
	leaq	104(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	112(%rsp), %rcx
	movl	%r8d, 8(%rsp)
	movsd	%xmm0, 64(%rsp)
	movsd	%xmm1, 56(%rsp)
	movsd	%xmm2, 48(%rsp)
	movsd	%xmm3, 40(%rsp)
	movsd	%xmm4, 32(%rsp)
	movsd	%xmm5, 24(%rsp)
	movsd	%xmm6, 16(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 264(%rsp)
	xorl	%eax, %eax
	leaq	88(%rsp), %rax
	movl	$1, 128(%rsp)
	movq	%rax, 168(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 256(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 120(%rsp)
	movq	%rax, 132(%rsp)
	movl	$1, 140(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	112(%rsp)
	.cfi_def_cfa_offset 296
	leaq	_ZN7kernels11initialiseUEPdS0_S0_dddddddii(%rip), %rdi
	pushq	112(%rsp)
	.cfi_def_cfa_offset 304
	movq	148(%rsp), %rcx
	movl	156(%rsp), %r8d
	movq	136(%rsp), %rsi
	movl	144(%rsp), %edx
	leaq	184(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 296
	popq	%rdx
	.cfi_def_cfa_offset 288
.L2:
	movq	264(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$280, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z56__device_stub__ZN7kernels11initialiseUEPdS0_S0_dddddddiiPdS_S_dddddddii, .-_Z56__device_stub__ZN7kernels11initialiseUEPdS0_S0_dddddddiiPdS_S_dddddddii
	.globl	_ZN7kernels11initialiseUEPdS0_S0_dddddddii
	.type	_ZN7kernels11initialiseUEPdS0_S0_dddddddii, @function
_ZN7kernels11initialiseUEPdS0_S0_dddddddii:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z56__device_stub__ZN7kernels11initialiseUEPdS0_S0_dddddddiiPdS_S_dddddddii
	.cfi_endproc
.LFE2033:
	.size	_ZN7kernels11initialiseUEPdS0_S0_dddddddii, .-_ZN7kernels11initialiseUEPdS0_S0_dddddddii
	.globl	_Z56__device_stub__ZN7kernels11initialiseVEPdS0_S0_dddddddiiPdS_S_dddddddii
	.type	_Z56__device_stub__ZN7kernels11initialiseVEPdS0_S0_dddddddiiPdS_S_dddddddii, @function
_Z56__device_stub__ZN7kernels11initialiseVEPdS0_S0_dddddddiiPdS_S_dddddddii:
.LFB2034:
	.cfi_startproc
	endbr64
	subq	$280, %rsp
	.cfi_def_cfa_offset 288
	movq	%rdi, 88(%rsp)
	leaq	120(%rsp), %rdi
	movq	%rsi, 80(%rsp)
	leaq	132(%rsp), %rsi
	movq	%rdx, 72(%rsp)
	leaq	104(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	112(%rsp), %rcx
	movl	%r8d, 8(%rsp)
	movsd	%xmm0, 64(%rsp)
	movsd	%xmm1, 56(%rsp)
	movsd	%xmm2, 48(%rsp)
	movsd	%xmm3, 40(%rsp)
	movsd	%xmm4, 32(%rsp)
	movsd	%xmm5, 24(%rsp)
	movsd	%xmm6, 16(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 264(%rsp)
	xorl	%eax, %eax
	leaq	88(%rsp), %rax
	movl	$1, 128(%rsp)
	movq	%rax, 168(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 256(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 120(%rsp)
	movq	%rax, 132(%rsp)
	movl	$1, 140(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	112(%rsp)
	.cfi_def_cfa_offset 296
	leaq	_ZN7kernels11initialiseVEPdS0_S0_dddddddii(%rip), %rdi
	pushq	112(%rsp)
	.cfi_def_cfa_offset 304
	movq	148(%rsp), %rcx
	movl	156(%rsp), %r8d
	movq	136(%rsp), %rsi
	movl	144(%rsp), %edx
	leaq	184(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 296
	popq	%rdx
	.cfi_def_cfa_offset 288
.L8:
	movq	264(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$280, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2034:
	.size	_Z56__device_stub__ZN7kernels11initialiseVEPdS0_S0_dddddddiiPdS_S_dddddddii, .-_Z56__device_stub__ZN7kernels11initialiseVEPdS0_S0_dddddddiiPdS_S_dddddddii
	.globl	_ZN7kernels11initialiseVEPdS0_S0_dddddddii
	.type	_ZN7kernels11initialiseVEPdS0_S0_dddddddii, @function
_ZN7kernels11initialiseVEPdS0_S0_dddddddii:
.LFB2035:
	.cfi_startproc
	endbr64
	jmp	_Z56__device_stub__ZN7kernels11initialiseVEPdS0_S0_dddddddiiPdS_S_dddddddii
	.cfi_endproc
.LFE2035:
	.size	_ZN7kernels11initialiseVEPdS0_S0_dddddddii, .-_ZN7kernels11initialiseVEPdS0_S0_dddddddii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_ZN7kernels11initialiseVEPdS0_S0_dddddddii"
.LC1:
	.string	"_ZN7kernels11initialiseUEPdS0_S0_dddddddii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2037:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_ZN7kernels11initialiseVEPdS0_S0_dddddddii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_ZN7kernels11initialiseUEPdS0_S0_dddddddii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2037:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/***************************************************************************//**
 * \file initialise.cu
 * \author Christopher Minar (minarc@oregonstate.edu)
 */


#include <hip/hip_runtime.h>
#include "initialise.h"

namespace kernels
{
/*
 * sets all the initial u values
 * param u u velocities
 * param xu x locations of where u is stored
 * param yu y locations of where u is stored
 * param uInitial initial u velocity
 * param uPerturb perturbation coefficient
 * param pi... //flag
 * param xmax highest x value in the domain
 * param xmin lowest x value in the domain
 * param ymax highest y value in the domain
 * param ymin lowest yvalue in the domain
 * nx number of nodes in the x direction
 * ny number of nodes in the y direction
 */
__global__
void initialiseU(double *u, double *xu, double *yu, double uInitial, double uPerturb, double pi, double xmax, double xmin,double ymax,double ymin, int nx, int ny)
{
	if (threadIdx.x + (blockDim.x * blockIdx.x) >= (nx-1)*ny)
			return;
	int 	idx 	= threadIdx.x + (blockDim.x * blockIdx.x),
			i = idx%(nx-1),
			j = idx/(nx-1);

	u[idx] = uInitial + uPerturb * cos(0.5*pi*(2*xu[i]-xmax-xmin)/(xmax-xmin)) * sin( pi * (2*yu[j]-ymax-ymin)/(ymax-ymin));
}

/*
 * sets all the initial v values
 * param u v velocities
 * param xv x locations of where v is stored
 * param yv y locations of where v is stored
 * param vInitial initial v velocity
 * param vPerturb perturbation coefficient
 * param pi... //flag
 * param xmax highest x value in the domain
 * param xmin lowest x value in the domain
 * param ymax highest y value in the domain
 * param ymin lowest yvalue in the domain
 * nx number of nodes in the x direction
 * ny number of nodes in the y direction
 */
__global__
void initialiseV(double *u, double *xv, double *yv, double vInitial, double vPerturb, double pi, double xmax, double xmin,double ymax,double ymin, int nx, int ny)
{
	if (threadIdx.x + (blockDim.x * blockIdx.x) >= nx*(ny-1))
		return;
	int 	idx 	= threadIdx.x + (blockDim.x * blockIdx.x),
			i = idx%nx,
			j = idx/nx;
	idx +=  (nx-1)*ny;

	u[idx] = vInitial + vPerturb * cos(0.5*pi*(2*yv[j]-ymax-ymin)/(ymax-ymin)) * sin( pi * (2*xv[i]-xmax-xmin)/(xmax-xmin));
}
}

	.text
	.file	"initialise.hip"
	.globl	_ZN7kernels26__device_stub__initialiseUEPdS0_S0_dddddddii # -- Begin function _ZN7kernels26__device_stub__initialiseUEPdS0_S0_dddddddii
	.type	_ZN7kernels26__device_stub__initialiseUEPdS0_S0_dddddddii,@function
_ZN7kernels26__device_stub__initialiseUEPdS0_S0_dddddddii: # @_ZN7kernels26__device_stub__initialiseUEPdS0_S0_dddddddii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$240, %rsp
	.cfi_def_cfa_offset 288
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	104(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	96(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	88(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rdx
	movsd	%xmm0, (%rdx)
	leaq	72(%rsp), %r9
	movsd	%xmm1, (%r9)
	leaq	64(%rsp), %r10
	movsd	%xmm2, (%r10)
	leaq	56(%rsp), %r11
	movsd	%xmm3, (%r11)
	leaq	48(%rsp), %r14
	movsd	%xmm4, (%r14)
	leaq	40(%rsp), %r15
	movsd	%xmm5, (%r15)
	leaq	32(%rsp), %r12
	movsd	%xmm6, (%r12)
	leaq	12(%rsp), %r13
	movl	%ecx, (%r13)
	leaq	8(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	144(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r9, 32(%rbx)
	movq	%r10, 40(%rbx)
	movq	%r11, 48(%rbx)
	movq	%r14, 56(%rbx)
	movq	%r15, 64(%rbx)
	movq	%r12, 72(%rbx)
	movq	%r13, 80(%rbx)
	movq	%rcx, 88(%rbx)
	leaq	128(%rsp), %r14
	leaq	112(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZN7kernels11initialiseUEPdS0_S0_dddddddii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$256, %rsp                      # imm = 0x100
	.cfi_adjust_cfa_offset -256
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_ZN7kernels26__device_stub__initialiseUEPdS0_S0_dddddddii, .Lfunc_end0-_ZN7kernels26__device_stub__initialiseUEPdS0_S0_dddddddii
	.cfi_endproc
                                        # -- End function
	.globl	_ZN7kernels26__device_stub__initialiseVEPdS0_S0_dddddddii # -- Begin function _ZN7kernels26__device_stub__initialiseVEPdS0_S0_dddddddii
	.type	_ZN7kernels26__device_stub__initialiseVEPdS0_S0_dddddddii,@function
_ZN7kernels26__device_stub__initialiseVEPdS0_S0_dddddddii: # @_ZN7kernels26__device_stub__initialiseVEPdS0_S0_dddddddii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$240, %rsp
	.cfi_def_cfa_offset 288
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	104(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	96(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	88(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rdx
	movsd	%xmm0, (%rdx)
	leaq	72(%rsp), %r9
	movsd	%xmm1, (%r9)
	leaq	64(%rsp), %r10
	movsd	%xmm2, (%r10)
	leaq	56(%rsp), %r11
	movsd	%xmm3, (%r11)
	leaq	48(%rsp), %r14
	movsd	%xmm4, (%r14)
	leaq	40(%rsp), %r15
	movsd	%xmm5, (%r15)
	leaq	32(%rsp), %r12
	movsd	%xmm6, (%r12)
	leaq	12(%rsp), %r13
	movl	%ecx, (%r13)
	leaq	8(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	144(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r9, 32(%rbx)
	movq	%r10, 40(%rbx)
	movq	%r11, 48(%rbx)
	movq	%r14, 56(%rbx)
	movq	%r15, 64(%rbx)
	movq	%r12, 72(%rbx)
	movq	%r13, 80(%rbx)
	movq	%rcx, 88(%rbx)
	leaq	128(%rsp), %r14
	leaq	112(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_ZN7kernels11initialiseVEPdS0_S0_dddddddii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$256, %rsp                      # imm = 0x100
	.cfi_adjust_cfa_offset -256
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_ZN7kernels26__device_stub__initialiseVEPdS0_S0_dddddddii, .Lfunc_end1-_ZN7kernels26__device_stub__initialiseVEPdS0_S0_dddddddii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZN7kernels11initialiseUEPdS0_S0_dddddddii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_ZN7kernels11initialiseVEPdS0_S0_dddddddii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_ZN7kernels11initialiseUEPdS0_S0_dddddddii,@object # @_ZN7kernels11initialiseUEPdS0_S0_dddddddii
	.section	.rodata,"a",@progbits
	.globl	_ZN7kernels11initialiseUEPdS0_S0_dddddddii
	.p2align	3, 0x0
_ZN7kernels11initialiseUEPdS0_S0_dddddddii:
	.quad	_ZN7kernels26__device_stub__initialiseUEPdS0_S0_dddddddii
	.size	_ZN7kernels11initialiseUEPdS0_S0_dddddddii, 8

	.type	_ZN7kernels11initialiseVEPdS0_S0_dddddddii,@object # @_ZN7kernels11initialiseVEPdS0_S0_dddddddii
	.globl	_ZN7kernels11initialiseVEPdS0_S0_dddddddii
	.p2align	3, 0x0
_ZN7kernels11initialiseVEPdS0_S0_dddddddii:
	.quad	_ZN7kernels26__device_stub__initialiseVEPdS0_S0_dddddddii
	.size	_ZN7kernels11initialiseVEPdS0_S0_dddddddii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_ZN7kernels11initialiseUEPdS0_S0_dddddddii"
	.size	.L__unnamed_1, 43

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_ZN7kernels11initialiseVEPdS0_S0_dddddddii"
	.size	.L__unnamed_2, 43

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _ZN7kernels26__device_stub__initialiseUEPdS0_S0_dddddddii
	.addrsig_sym _ZN7kernels26__device_stub__initialiseVEPdS0_S0_dddddddii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _ZN7kernels11initialiseUEPdS0_S0_dddddddii
	.addrsig_sym _ZN7kernels11initialiseVEPdS0_S0_dddddddii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_ZN7kernels11initialiseUEPdS0_S0_dddddddii ; -- Begin function _ZN7kernels11initialiseUEPdS0_S0_dddddddii
	.globl	_ZN7kernels11initialiseUEPdS0_S0_dddddddii
	.p2align	8
	.type	_ZN7kernels11initialiseUEPdS0_S0_dddddddii,@function
_ZN7kernels11initialiseUEPdS0_S0_dddddddii: ; @_ZN7kernels11initialiseUEPdS0_S0_dddddddii
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x64
	s_load_b64 s[2:3], s[0:1], 0x50
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_add_i32 s2, s2, -1
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	s_mul_i32 s3, s2, s3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_u32_e32 vcc_lo, s3, v1
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB0_10
; %bb.1:
	s_ashr_i32 s3, s2, 31
	v_ashrrev_i32_e32 v2, 31, v1
	s_add_i32 s4, s2, s3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_xor_b32 s4, s4, s3
	v_add_nc_u32_e32 v4, v1, v2
	v_cvt_f32_u32_e32 v0, s4
	s_sub_i32 s5, 0, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v4, v4, v2
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_mul_lo_u32 v3, s5, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v0, v3
	v_add_nc_u32_e32 v0, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v0, v4, v0
	v_mul_lo_u32 v3, v0, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v3, v4, v3
	v_add_nc_u32_e32 v4, 1, v0
	v_subrev_nc_u32_e32 v5, s4, v3
	v_cmp_le_u32_e32 vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v3, v3, v5 :: v_dual_cndmask_b32 v0, v0, v4
	v_xor_b32_e32 v5, s3, v2
	s_mov_b32 s3, exec_lo
	v_cmp_le_u32_e32 vcc_lo, s4, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, 1, v0
	s_load_b512 s[4:19], s[0:1], 0x0
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v0, v0, v5
	v_sub_nc_u32_e32 v9, v0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v0, v9, s2
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[5:6], s[14:15], 0.5
	v_add_f64 v[7:8], s[16:17], -s[18:19]
	v_sub_nc_u32_e32 v3, v1, v0
                                        ; implicit-def: $vgpr0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[3:4], 3, v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, s6, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s7, v4, vcc_lo
	global_load_b64 v[3:4], v[3:4], off
	s_waitcnt vmcnt(0)
	v_fma_f64 v[3:4], v[3:4], 2.0, -s[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[3:4], v[3:4], -s[18:19]
	v_mul_f64 v[3:4], v[5:6], v[3:4]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[5:6], null, v[7:8], v[7:8], v[3:4]
	v_rcp_f64_e32 v[10:11], v[5:6]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[12:13], -v[5:6], v[10:11], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
	v_fma_f64 v[12:13], -v[5:6], v[10:11], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[10:11], v[12:13], v[10:11]
	v_div_scale_f64 v[12:13], vcc_lo, v[3:4], v[7:8], v[3:4]
	v_mul_f64 v[14:15], v[12:13], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[5:6], -v[5:6], v[14:15], v[12:13]
	v_div_fmas_f64 v[5:6], v[5:6], v[10:11], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[3:4], v[5:6], v[7:8], v[3:4]
                                        ; implicit-def: $vgpr5_vgpr6
                                        ; implicit-def: $vgpr7_vgpr8
	v_cmpx_ngt_f64_e64 0x41d00000, |v[3:4]|
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB0_3
; %bb.2:
	v_ldexp_f64 v[5:6], |v[3:4]|, 0xffffff80
	v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[3:4]|
	v_trig_preop_f64 v[7:8], |v[3:4]|, 0
	v_and_b32_e32 v0, 0x7fffffff, v4
	v_trig_preop_f64 v[10:11], |v[3:4]|, 1
	v_trig_preop_f64 v[20:21], |v[3:4]|, 2
	v_mov_b32_e32 v28, 0
	s_mov_b32 s6, 0x54442d18
	s_mov_b32 s7, 0x3ff921fb
	s_mov_b32 s16, 0x33145c07
	s_mov_b32 s17, 0x3c91a626
	v_dual_cndmask_b32 v5, v3, v5 :: v_dual_cndmask_b32 v6, v0, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f64 v[12:13], v[7:8], v[5:6]
	v_mul_f64 v[14:15], v[10:11], v[5:6]
	v_fma_f64 v[7:8], v[7:8], v[5:6], -v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[10:11], v[10:11], v[5:6], -v[14:15]
	v_add_f64 v[16:17], v[14:15], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[18:19], v[16:17], -v[14:15]
	v_add_f64 v[24:25], v[12:13], v[16:17]
	v_add_f64 v[22:23], v[16:17], -v[18:19]
	v_add_f64 v[7:8], v[7:8], -v[18:19]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_ldexp_f64 v[18:19], v[24:25], -2
	v_add_f64 v[12:13], v[24:25], -v[12:13]
	v_add_f64 v[14:15], v[14:15], -v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[18:19]|
	v_add_f64 v[12:13], v[16:17], -v[12:13]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[7:8], v[7:8], v[14:15]
	v_fract_f64_e32 v[14:15], v[18:19]
	v_cndmask_b32_e32 v15, 0, v15, vcc_lo
	v_mul_f64 v[26:27], v[20:21], v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v14, 0, v14, vcc_lo
	v_ldexp_f64 v[14:15], v[14:15], 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[22:23], v[26:27], v[10:11]
	v_fma_f64 v[5:6], v[20:21], v[5:6], -v[26:27]
	v_add_f64 v[16:17], v[22:23], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[18:19], v[12:13], v[16:17]
	v_add_f64 v[24:25], v[18:19], v[14:15]
	v_add_f64 v[12:13], v[18:19], -v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_gt_f64_e32 vcc_lo, 0, v[24:25]
	v_add_f64 v[24:25], v[22:23], -v[26:27]
	v_add_f64 v[12:13], v[16:17], -v[12:13]
	v_cndmask_b32_e64 v29, 0, 0x40100000, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[33:34], v[22:23], -v[24:25]
	v_add_f64 v[10:11], v[10:11], -v[24:25]
	v_add_f64 v[14:15], v[14:15], v[28:29]
	v_add_f64 v[29:30], v[16:17], -v[22:23]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[24:25], v[26:27], -v[33:34]
	v_add_f64 v[31:32], v[18:19], v[14:15]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[35:36], v[16:17], -v[29:30]
	v_add_f64 v[7:8], v[7:8], -v[29:30]
	v_add_f64 v[10:11], v[10:11], v[24:25]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_i32_f64_e32 v0, v[31:32]
	v_add_f64 v[22:23], v[22:23], -v[35:36]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_i32_e32 v[29:30], v0
	v_add_f64 v[7:8], v[7:8], v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[14:15], v[14:15], -v[29:30]
	v_add_f64 v[7:8], v[10:11], v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[10:11], v[18:19], v[14:15]
	v_add_f64 v[5:6], v[5:6], v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[7:8], v[10:11], -v[14:15]
	v_cmp_le_f64_e32 vcc_lo, 0.5, v[10:11]
	v_add_f64 v[5:6], v[12:13], v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f64 v[7:8], v[18:19], -v[7:8]
	v_cndmask_b32_e64 v29, 0, 0x3ff00000, vcc_lo
	v_add_co_ci_u32_e64 v0, s2, 0, v0, vcc_lo
	v_add_f64 v[5:6], v[5:6], v[7:8]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[7:8], v[10:11], -v[28:29]
	v_add_f64 v[10:11], v[7:8], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f64 v[12:13], v[10:11], s[6:7]
	v_add_f64 v[7:8], v[10:11], -v[7:8]
	v_fma_f64 v[14:15], v[10:11], s[6:7], -v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[5:6], v[5:6], -v[7:8]
	v_fma_f64 v[7:8], v[10:11], s[16:17], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], v[5:6], s[6:7], v[7:8]
	v_add_f64 v[5:6], v[12:13], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[10:11], v[5:6], -v[12:13]
	v_add_f64 v[7:8], v[7:8], -v[10:11]
.LBB0_3:                                ; %Flow66
	s_and_not1_saveexec_b32 s2, s3
	s_cbranch_execz .LBB0_5
; %bb.4:
	s_mov_b32 s6, 0x6dc9c883
	s_mov_b32 s7, 0x3fe45f30
	s_mov_b32 s17, 0xbc91a626
	v_mul_f64 v[5:6], |v[3:4]|, s[6:7]
	s_mov_b32 s6, 0x54442d18
	s_mov_b32 s7, 0xbff921fb
	s_mov_b32 s16, 0x33145c00
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[10:11], v[5:6]
	v_fma_f64 v[5:6], v[10:11], s[6:7], |v[3:4]|
	v_mul_f64 v[7:8], v[10:11], s[16:17]
	s_mov_b32 s6, 0x252049c0
	s_mov_b32 s7, 0xb97b839a
	v_cvt_i32_f64_e32 v0, v[10:11]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[14:15], v[10:11], s[16:17], v[5:6]
	v_add_f64 v[12:13], v[5:6], v[7:8]
	s_mov_b32 s17, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[5:6], v[5:6], -v[12:13]
	v_add_f64 v[12:13], v[12:13], -v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[5:6], v[5:6], v[7:8]
	v_fma_f64 v[7:8], v[10:11], s[16:17], v[7:8]
	v_add_f64 v[5:6], v[12:13], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[5:6], v[5:6], -v[7:8]
	v_fma_f64 v[7:8], v[10:11], s[6:7], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[5:6], v[14:15], v[7:8]
	v_add_f64 v[12:13], v[5:6], -v[14:15]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[7:8], v[7:8], -v[12:13]
.LBB0_5:                                ; %_ZL3cosd.exit
	s_or_b32 exec_lo, exec_lo, s2
	v_ashrrev_i32_e32 v10, 31, v9
	s_load_b128 s[0:3], s[0:1], 0x40
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[9:10], 3, v[9:10]
	v_add_co_u32 v9, vcc_lo, s8, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, s9, v10, vcc_lo
	global_load_b64 v[9:10], v[9:10], off
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[11:12], s[0:1], -s[2:3]
	s_waitcnt vmcnt(0)
	v_fma_f64 v[9:10], v[9:10], 2.0, -s[0:1]
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[9:10], v[9:10], -s[2:3]
	v_mul_f64 v[9:10], v[9:10], s[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[13:14], null, v[11:12], v[11:12], v[9:10]
	v_rcp_f64_e32 v[15:16], v[13:14]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[17:18], -v[13:14], v[15:16], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
	v_fma_f64 v[17:18], -v[13:14], v[15:16], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], v[15:16], v[17:18], v[15:16]
	v_div_scale_f64 v[17:18], vcc_lo, v[9:10], v[11:12], v[9:10]
	v_mul_f64 v[19:20], v[17:18], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], -v[13:14], v[19:20], v[17:18]
	v_div_fmas_f64 v[13:14], v[13:14], v[15:16], v[19:20]
                                        ; implicit-def: $vgpr15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[9:10], v[13:14], v[11:12], v[9:10]
                                        ; implicit-def: $vgpr11_vgpr12
                                        ; implicit-def: $vgpr13_vgpr14
	v_cmpx_ngt_f64_e64 0x41d00000, |v[9:10]|
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB0_7
; %bb.6:
	v_ldexp_f64 v[11:12], |v[9:10]|, 0xffffff80
	v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[9:10]|
	v_trig_preop_f64 v[13:14], |v[9:10]|, 0
	v_and_b32_e32 v15, 0x7fffffff, v10
	v_trig_preop_f64 v[25:26], |v[9:10]|, 2
	v_mov_b32_e32 v33, 0
	s_mov_b32 s2, 0x54442d18
	s_mov_b32 s3, 0x3ff921fb
	s_mov_b32 s6, 0x33145c07
	s_mov_b32 s7, 0x3c91a626
	v_dual_cndmask_b32 v12, v15, v12 :: v_dual_cndmask_b32 v11, v9, v11
	v_trig_preop_f64 v[15:16], |v[9:10]|, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f64 v[17:18], v[13:14], v[11:12]
	v_mul_f64 v[31:32], v[25:26], v[11:12]
	v_mul_f64 v[19:20], v[15:16], v[11:12]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[13:14], v[13:14], v[11:12], -v[17:18]
	v_fma_f64 v[15:16], v[15:16], v[11:12], -v[19:20]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[11:12], v[25:26], v[11:12], -v[31:32]
	v_add_f64 v[21:22], v[19:20], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[23:24], v[21:22], -v[19:20]
	v_add_f64 v[29:30], v[17:18], v[21:22]
	v_add_f64 v[27:28], v[21:22], -v[23:24]
	v_add_f64 v[13:14], v[13:14], -v[23:24]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_ldexp_f64 v[23:24], v[29:30], -2
	v_add_f64 v[17:18], v[29:30], -v[17:18]
	v_add_f64 v[19:20], v[19:20], -v[27:28]
	v_add_f64 v[27:28], v[31:32], v[15:16]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[23:24]|
	v_add_f64 v[17:18], v[21:22], -v[17:18]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[13:14], v[13:14], v[19:20]
	v_fract_f64_e32 v[19:20], v[23:24]
	v_add_f64 v[21:22], v[27:28], v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v20, 0, v20 :: v_dual_cndmask_b32 v19, 0, v19
	v_ldexp_f64 v[19:20], v[19:20], 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[23:24], v[17:18], v[21:22]
	v_add_f64 v[29:30], v[23:24], v[19:20]
	v_add_f64 v[17:18], v[23:24], -v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_gt_f64_e32 vcc_lo, 0, v[29:30]
	v_add_f64 v[29:30], v[27:28], -v[31:32]
	v_cndmask_b32_e64 v34, 0, 0x40100000, vcc_lo
	v_add_f64 v[38:39], v[27:28], -v[29:30]
	v_add_f64 v[15:16], v[15:16], -v[29:30]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[19:20], v[19:20], v[33:34]
	v_add_f64 v[34:35], v[21:22], -v[27:28]
	v_add_f64 v[29:30], v[31:32], -v[38:39]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[36:37], v[23:24], v[19:20]
	v_add_f64 v[40:41], v[21:22], -v[34:35]
	v_add_f64 v[13:14], v[13:14], -v[34:35]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[15:16], v[15:16], v[29:30]
	v_cvt_i32_f64_e32 v36, v[36:37]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[27:28], v[27:28], -v[40:41]
	v_cvt_f64_i32_e32 v[34:35], v36
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[13:14], v[13:14], v[27:28]
	v_add_f64 v[19:20], v[19:20], -v[34:35]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[13:14], v[15:16], v[13:14]
	v_add_f64 v[15:16], v[21:22], -v[17:18]
	v_add_f64 v[25:26], v[23:24], v[19:20]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[11:12], v[11:12], v[13:14]
	v_add_f64 v[13:14], v[25:26], -v[19:20]
	v_cmp_le_f64_e32 vcc_lo, 0.5, v[25:26]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[11:12], v[15:16], v[11:12]
	v_add_f64 v[13:14], v[23:24], -v[13:14]
	v_cndmask_b32_e64 v34, 0, 0x3ff00000, vcc_lo
	v_add_co_ci_u32_e64 v15, s0, 0, v36, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[11:12], v[11:12], v[13:14]
	v_add_f64 v[13:14], v[25:26], -v[33:34]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[16:17], v[13:14], v[11:12]
	v_mul_f64 v[18:19], v[16:17], s[2:3]
	v_add_f64 v[13:14], v[16:17], -v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[20:21], v[16:17], s[2:3], -v[18:19]
	v_add_f64 v[11:12], v[11:12], -v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], v[16:17], s[6:7], v[20:21]
	v_fma_f64 v[13:14], v[11:12], s[2:3], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[11:12], v[18:19], v[13:14]
	v_add_f64 v[16:17], v[11:12], -v[18:19]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[13:14], v[13:14], -v[16:17]
.LBB0_7:                                ; %Flow
	s_and_not1_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_9
; %bb.8:
	s_mov_b32 s2, 0x6dc9c883
	s_mov_b32 s3, 0x3fe45f30
	s_mov_b32 s7, 0xbc91a626
	v_mul_f64 v[11:12], |v[9:10]|, s[2:3]
	s_mov_b32 s2, 0x54442d18
	s_mov_b32 s3, 0xbff921fb
	s_mov_b32 s6, 0x33145c00
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[15:16], v[11:12]
	v_fma_f64 v[11:12], v[15:16], s[2:3], |v[9:10]|
	v_mul_f64 v[13:14], v[15:16], s[6:7]
	s_mov_b32 s2, 0x252049c0
	s_mov_b32 s3, 0xb97b839a
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[19:20], v[15:16], s[6:7], v[11:12]
	v_add_f64 v[17:18], v[11:12], v[13:14]
	s_mov_b32 s7, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[11:12], v[11:12], -v[17:18]
	v_add_f64 v[17:18], v[17:18], -v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[11:12], v[11:12], v[13:14]
	v_fma_f64 v[13:14], v[15:16], s[6:7], v[13:14]
	v_add_f64 v[11:12], v[17:18], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[11:12], v[11:12], -v[13:14]
	v_fma_f64 v[13:14], v[15:16], s[2:3], v[11:12]
	v_cvt_i32_f64_e32 v15, v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[11:12], v[19:20], v[13:14]
	v_add_f64 v[17:18], v[11:12], -v[19:20]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[13:14], v[13:14], -v[17:18]
.LBB0_9:                                ; %_ZL3sind.exit
	s_or_b32 exec_lo, exec_lo, s0
	v_mul_f64 v[16:17], v[5:6], v[5:6]
	s_mov_b32 s0, 0xb42fdfa7
	s_mov_b32 s2, 0xf9a43bb8
	s_mov_b32 s1, 0xbe5ae600
	s_mov_b32 s3, 0x3de5e0b2
	v_mul_f64 v[18:19], v[11:12], v[11:12]
	s_mov_b32 s14, 0x796cde01
	s_mov_b32 s15, 0x3ec71de3
	s_mov_b32 s6, 0x9037ab78
	s_mov_b32 s8, 0x46cc5e42
	s_mov_b32 s7, 0x3e21eeb6
	s_mov_b32 s9, 0xbda907db
	v_mul_f64 v[34:35], v[7:8], 0.5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f64 v[42:43], v[13:14], 0.5
	v_fma_f64 v[20:21], v[16:17], s[2:3], s[0:1]
	v_mul_f64 v[26:27], v[16:17], 0.5
	v_fma_f64 v[22:23], v[16:17], s[8:9], s[6:7]
	v_mul_f64 v[36:37], v[5:6], -v[16:17]
	v_fma_f64 v[24:25], v[18:19], s[2:3], s[0:1]
	s_mov_b32 s2, 0x19e83e5c
	s_mov_b32 s3, 0xbf2a01a0
	s_mov_b32 s0, 0xa17f65f6
	s_mov_b32 s1, 0xbe927e4f
	v_mul_f64 v[28:29], v[18:19], 0.5
	v_fma_f64 v[30:31], v[18:19], s[8:9], s[6:7]
	s_mov_b32 s8, 0x11110bb3
	s_mov_b32 s9, 0x3f811111
	s_mov_b32 s6, 0x19f4ec90
	s_mov_b32 s7, 0x3efa01a0
	v_mul_f64 v[44:45], v[11:12], -v[18:19]
	v_fma_f64 v[20:21], v[16:17], v[20:21], s[14:15]
	v_add_f64 v[32:33], -v[26:27], 1.0
	v_fma_f64 v[22:23], v[16:17], v[22:23], s[0:1]
	v_fma_f64 v[24:25], v[18:19], v[24:25], s[14:15]
	v_add_f64 v[38:39], -v[28:29], 1.0
	v_fma_f64 v[30:31], v[18:19], v[30:31], s[0:1]
	s_mov_b32 s0, 0x16c16967
	s_mov_b32 s1, 0xbf56c16c
	v_fma_f64 v[20:21], v[16:17], v[20:21], s[2:3]
	v_add_f64 v[40:41], -v[32:33], 1.0
	v_fma_f64 v[22:23], v[16:17], v[22:23], s[6:7]
	v_fma_f64 v[24:25], v[18:19], v[24:25], s[2:3]
	s_mov_b32 s2, 0x55555555
	s_mov_b32 s3, 0x3fa55555
	v_add_f64 v[46:47], -v[38:39], 1.0
	v_fma_f64 v[30:31], v[18:19], v[30:31], s[6:7]
	v_fma_f64 v[20:21], v[16:17], v[20:21], s[8:9]
	v_add_f64 v[26:27], v[40:41], -v[26:27]
	v_fma_f64 v[22:23], v[16:17], v[22:23], s[0:1]
	v_fma_f64 v[24:25], v[18:19], v[24:25], s[8:9]
	v_add_f64 v[28:29], v[46:47], -v[28:29]
	v_fma_f64 v[30:31], v[18:19], v[30:31], s[0:1]
	s_mov_b32 s1, 0xbfc55555
	s_mov_b32 s0, s2
	v_fma_f64 v[20:21], v[36:37], v[20:21], v[34:35]
	v_fma_f64 v[26:27], v[5:6], -v[7:8], v[26:27]
	v_mul_f64 v[34:35], v[16:17], v[16:17]
	v_fma_f64 v[22:23], v[16:17], v[22:23], s[2:3]
	v_fma_f64 v[24:25], v[44:45], v[24:25], v[42:43]
	v_fma_f64 v[28:29], v[11:12], -v[13:14], v[28:29]
	v_fma_f64 v[7:8], v[16:17], v[20:21], -v[7:8]
	v_mul_f64 v[16:17], v[18:19], v[18:19]
	v_fma_f64 v[20:21], v[18:19], v[30:31], s[2:3]
	v_fma_f64 v[13:14], v[18:19], v[24:25], -v[13:14]
	v_fma_f64 v[18:19], v[34:35], v[22:23], v[26:27]
	v_fma_f64 v[7:8], v[36:37], s[0:1], v[7:8]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[16:17], v[16:17], v[20:21], v[28:29]
	v_fma_f64 v[13:14], v[44:45], s[0:1], v[13:14]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f64 v[18:19], v[32:33], v[18:19]
	v_cmp_class_f64_e64 s0, v[3:4], 0x1f8
	v_add_f64 v[5:6], v[5:6], -v[7:8]
	v_and_b32_e32 v20, 1, v0
	v_add_f64 v[7:8], v[38:39], v[16:17]
	v_add_f64 v[11:12], v[11:12], -v[13:14]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e32 vcc_lo, 0, v20
	v_and_b32_e32 v4, 1, v15
	v_xor_b32_e32 v3, 0x80000000, v6
	v_dual_cndmask_b32 v5, v5, v18 :: v_dual_lshlrev_b32 v0, 30, v0
	v_dual_cndmask_b32 v3, v3, v19 :: v_dual_and_b32 v0, 0x80000000, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e32 vcc_lo, 0, v4
	v_xor_b32_e32 v0, v3, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v3, 0, v5, s0
	v_dual_cndmask_b32 v5, v8, v12 :: v_dual_cndmask_b32 v6, v7, v11
	v_cndmask_b32_e64 v4, 0x7ff80000, v0, s0
	v_cmp_class_f64_e64 s0, v[9:10], 0x1f8
	v_lshlrev_b32_e32 v0, 30, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[3:4], v[3:4], s[12:13]
	v_xor_b32_e32 v0, v0, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v0, 0x80000000, v0
	v_xor_b32_e32 v0, v5, v0
	v_cndmask_b32_e64 v5, 0, v6, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v6, 0x7ff80000, v0, s0
	v_lshlrev_b64 v[0:1], 3, v[1:2]
	v_fma_f64 v[3:4], v[3:4], v[5:6], s[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	global_store_b64 v[0:1], v[3:4], off
.LBB0_10:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZN7kernels11initialiseUEPdS0_S0_dddddddii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 344
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 48
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_ZN7kernels11initialiseUEPdS0_S0_dddddddii, .Lfunc_end0-_ZN7kernels11initialiseUEPdS0_S0_dddddddii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3396
; NumSgprs: 22
; NumVgprs: 48
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 48
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_ZN7kernels11initialiseVEPdS0_S0_dddddddii ; -- Begin function _ZN7kernels11initialiseVEPdS0_S0_dddddddii
	.globl	_ZN7kernels11initialiseVEPdS0_S0_dddddddii
	.p2align	8
	.type	_ZN7kernels11initialiseVEPdS0_S0_dddddddii,@function
_ZN7kernels11initialiseVEPdS0_S0_dddddddii: ; @_ZN7kernels11initialiseVEPdS0_S0_dddddddii
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x64
	s_load_b64 s[2:3], s[0:1], 0x50
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	s_add_i32 s4, s3, -1
	s_mul_i32 s4, s4, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_u32_e32 vcc_lo, s4, v1
	s_and_saveexec_b32 s4, vcc_lo
	s_cbranch_execz .LBB1_10
; %bb.1:
	s_ashr_i32 s4, s2, 31
	v_ashrrev_i32_e32 v3, 31, v1
	s_add_i32 s5, s2, s4
	s_load_b128 s[20:23], s[0:1], 0x40
	s_xor_b32 s5, s5, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v1, v3
	v_cvt_f32_u32_e32 v0, s5
	s_sub_i32 s6, 0, s5
	v_xor_b32_e32 v4, v4, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_rcp_iflag_f32_e32 v0, v0
	v_xor_b32_e32 v3, s4, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[6:7], s[20:21], -s[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_mul_lo_u32 v2, s6, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v2, v0, v2
	v_add_nc_u32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v0, v4, v0
	v_mul_lo_u32 v2, v0, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v2, v4, v2
	v_add_nc_u32_e32 v4, 1, v0
	v_subrev_nc_u32_e32 v5, s5, v2
	v_cmp_le_u32_e32 vcc_lo, s5, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	v_cndmask_b32_e32 v2, v2, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, 1, v0
	v_cmp_le_u32_e32 vcc_lo, s5, v2
	s_load_b512 s[4:19], s[0:1], 0x0
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	v_xor_b32_e32 v0, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v8, v0, v3
                                        ; implicit-def: $vgpr0
	v_ashrrev_i32_e32 v9, 31, v8
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[4:5], s[14:15], 0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 3, v[8:9]
	v_add_co_u32 v2, vcc_lo, s8, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	global_load_b64 v[2:3], v[2:3], off
	s_waitcnt vmcnt(0)
	v_fma_f64 v[2:3], v[2:3], 2.0, -s[20:21]
	v_add_f64 v[2:3], v[2:3], -s[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[2:3], v[4:5], v[2:3]
	v_div_scale_f64 v[4:5], null, v[6:7], v[6:7], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[9:10], v[4:5]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[11:12], -v[4:5], v[9:10], 1.0
	v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[11:12], -v[4:5], v[9:10], 1.0
	v_fma_f64 v[9:10], v[9:10], v[11:12], v[9:10]
	v_div_scale_f64 v[11:12], vcc_lo, v[2:3], v[6:7], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[13:14], v[11:12], v[9:10]
	v_fma_f64 v[4:5], -v[4:5], v[13:14], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[4:5], v[4:5], v[9:10], v[13:14]
	v_div_fixup_f64 v[2:3], v[4:5], v[6:7], v[2:3]
                                        ; implicit-def: $vgpr4_vgpr5
                                        ; implicit-def: $vgpr6_vgpr7
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ngt_f64_e64 0x41d00000, |v[2:3]|
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB1_3
; %bb.2:
	v_ldexp_f64 v[4:5], |v[2:3]|, 0xffffff80
	v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[2:3]|
	v_trig_preop_f64 v[6:7], |v[2:3]|, 0
	v_and_b32_e32 v0, 0x7fffffff, v3
	v_trig_preop_f64 v[9:10], |v[2:3]|, 1
	v_trig_preop_f64 v[19:20], |v[2:3]|, 2
	s_mov_b32 s8, 0x54442d18
	s_mov_b32 s9, 0x3ff921fb
	s_mov_b32 s20, 0x33145c07
	s_mov_b32 s21, 0x3c91a626
	v_mov_b32_e32 v27, 0
	v_dual_cndmask_b32 v5, v0, v5 :: v_dual_cndmask_b32 v4, v2, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f64 v[11:12], v[6:7], v[4:5]
	v_mul_f64 v[13:14], v[9:10], v[4:5]
	v_mul_f64 v[25:26], v[19:20], v[4:5]
	v_fma_f64 v[6:7], v[6:7], v[4:5], -v[11:12]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[9:10], v[9:10], v[4:5], -v[13:14]
	v_fma_f64 v[4:5], v[19:20], v[4:5], -v[25:26]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[15:16], v[13:14], v[6:7]
	v_add_f64 v[17:18], v[15:16], -v[13:14]
	v_add_f64 v[23:24], v[11:12], v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[21:22], v[15:16], -v[17:18]
	v_add_f64 v[6:7], v[6:7], -v[17:18]
	v_ldexp_f64 v[17:18], v[23:24], -2
	v_add_f64 v[11:12], v[23:24], -v[11:12]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[13:14], v[13:14], -v[21:22]
	v_add_f64 v[21:22], v[25:26], v[9:10]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[17:18]|
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[11:12], v[15:16], -v[11:12]
	v_add_f64 v[6:7], v[6:7], v[13:14]
	v_fract_f64_e32 v[13:14], v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[15:16], v[21:22], v[6:7]
	v_dual_cndmask_b32 v14, 0, v14 :: v_dual_cndmask_b32 v13, 0, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ldexp_f64 v[13:14], v[13:14], 2
	v_add_f64 v[17:18], v[11:12], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[23:24], v[17:18], v[13:14]
	v_add_f64 v[11:12], v[17:18], -v[11:12]
	v_cmp_gt_f64_e32 vcc_lo, 0, v[23:24]
	v_add_f64 v[23:24], v[21:22], -v[25:26]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[11:12], v[15:16], -v[11:12]
	v_cndmask_b32_e64 v28, 0, 0x40100000, vcc_lo
	v_add_f64 v[32:33], v[21:22], -v[23:24]
	v_add_f64 v[9:10], v[9:10], -v[23:24]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[13:14], v[13:14], v[27:28]
	v_add_f64 v[28:29], v[15:16], -v[21:22]
	v_add_f64 v[23:24], v[25:26], -v[32:33]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[30:31], v[17:18], v[13:14]
	v_add_f64 v[34:35], v[15:16], -v[28:29]
	v_add_f64 v[6:7], v[6:7], -v[28:29]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[9:10], v[9:10], v[23:24]
	v_cvt_i32_f64_e32 v0, v[30:31]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[21:22], v[21:22], -v[34:35]
	v_cvt_f64_i32_e32 v[28:29], v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], v[6:7], v[21:22]
	v_add_f64 v[13:14], v[13:14], -v[28:29]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[6:7], v[9:10], v[6:7]
	v_add_f64 v[9:10], v[17:18], v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[4:5], v[4:5], v[6:7]
	v_add_f64 v[6:7], v[9:10], -v[13:14]
	v_cmp_le_f64_e32 vcc_lo, 0.5, v[9:10]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[4:5], v[11:12], v[4:5]
	v_add_f64 v[6:7], v[17:18], -v[6:7]
	v_cndmask_b32_e64 v28, 0, 0x3ff00000, vcc_lo
	v_add_co_ci_u32_e64 v0, s0, 0, v0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[4:5], v[4:5], v[6:7]
	v_add_f64 v[6:7], v[9:10], -v[27:28]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[9:10], v[6:7], v[4:5]
	v_mul_f64 v[11:12], v[9:10], s[8:9]
	v_add_f64 v[6:7], v[9:10], -v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[13:14], v[9:10], s[8:9], -v[11:12]
	v_add_f64 v[4:5], v[4:5], -v[6:7]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[9:10], s[20:21], v[13:14]
	v_fma_f64 v[6:7], v[4:5], s[8:9], v[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[4:5], v[11:12], v[6:7]
	v_add_f64 v[9:10], v[4:5], -v[11:12]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[6:7], v[6:7], -v[9:10]
.LBB1_3:                                ; %Flow68
	s_and_not1_saveexec_b32 s0, s1
	s_cbranch_execz .LBB1_5
; %bb.4:
	s_mov_b32 s8, 0x6dc9c883
	s_mov_b32 s9, 0x3fe45f30
	s_mov_b32 s21, 0xbc91a626
	v_mul_f64 v[4:5], |v[2:3]|, s[8:9]
	s_mov_b32 s8, 0x54442d18
	s_mov_b32 s9, 0xbff921fb
	s_mov_b32 s20, 0x33145c00
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[9:10], v[4:5]
	v_fma_f64 v[4:5], v[9:10], s[8:9], |v[2:3]|
	v_mul_f64 v[6:7], v[9:10], s[20:21]
	s_mov_b32 s8, 0x252049c0
	s_mov_b32 s9, 0xb97b839a
	v_cvt_i32_f64_e32 v0, v[9:10]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[13:14], v[9:10], s[20:21], v[4:5]
	v_add_f64 v[11:12], v[4:5], v[6:7]
	s_mov_b32 s21, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[4:5], v[4:5], -v[11:12]
	v_add_f64 v[11:12], v[11:12], -v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[4:5], v[4:5], v[6:7]
	v_fma_f64 v[6:7], v[9:10], s[20:21], v[6:7]
	v_add_f64 v[4:5], v[11:12], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[4:5], v[4:5], -v[6:7]
	v_fma_f64 v[6:7], v[9:10], s[8:9], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[4:5], v[13:14], v[6:7]
	v_add_f64 v[11:12], v[4:5], -v[13:14]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[6:7], v[6:7], -v[11:12]
.LBB1_5:                                ; %_ZL3cosd.exit
	s_or_b32 exec_lo, exec_lo, s0
	v_mul_lo_u32 v8, v8, s2
	v_add_f64 v[10:11], s[16:17], -s[18:19]
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v8, v1, v8
	v_ashrrev_i32_e32 v9, 31, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 3, v[8:9]
	v_add_co_u32 v8, vcc_lo, s6, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
	global_load_b64 v[8:9], v[8:9], off
	s_waitcnt vmcnt(0)
	v_fma_f64 v[8:9], v[8:9], 2.0, -s[16:17]
	v_add_f64 v[8:9], v[8:9], -s[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[8:9], v[8:9], s[14:15]
	v_div_scale_f64 v[12:13], null, v[10:11], v[10:11], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[14:15], v[12:13]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0
	v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0
	v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
	v_div_scale_f64 v[16:17], vcc_lo, v[8:9], v[10:11], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[18:19], v[16:17], v[14:15]
	v_fma_f64 v[12:13], -v[12:13], v[18:19], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[12:13], v[12:13], v[14:15], v[18:19]
                                        ; implicit-def: $vgpr14
	v_div_fixup_f64 v[8:9], v[12:13], v[10:11], v[8:9]
                                        ; implicit-def: $vgpr10_vgpr11
                                        ; implicit-def: $vgpr12_vgpr13
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ngt_f64_e64 0x41d00000, |v[8:9]|
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB1_7
; %bb.6:
	v_ldexp_f64 v[10:11], |v[8:9]|, 0xffffff80
	v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[8:9]|
	v_trig_preop_f64 v[12:13], |v[8:9]|, 0
	v_and_b32_e32 v14, 0x7fffffff, v9
	v_trig_preop_f64 v[24:25], |v[8:9]|, 2
	v_mov_b32_e32 v32, 0
	s_mov_b32 s6, 0x54442d18
	s_mov_b32 s7, 0x3ff921fb
	s_mov_b32 s8, 0x33145c07
	s_mov_b32 s9, 0x3c91a626
	v_dual_cndmask_b32 v11, v14, v11 :: v_dual_cndmask_b32 v10, v8, v10
	v_trig_preop_f64 v[14:15], |v[8:9]|, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f64 v[16:17], v[12:13], v[10:11]
	v_mul_f64 v[30:31], v[24:25], v[10:11]
	v_mul_f64 v[18:19], v[14:15], v[10:11]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[12:13], v[12:13], v[10:11], -v[16:17]
	v_fma_f64 v[14:15], v[14:15], v[10:11], -v[18:19]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[10:11], v[24:25], v[10:11], -v[30:31]
	v_add_f64 v[20:21], v[18:19], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[22:23], v[20:21], -v[18:19]
	v_add_f64 v[28:29], v[16:17], v[20:21]
	v_add_f64 v[26:27], v[20:21], -v[22:23]
	v_add_f64 v[12:13], v[12:13], -v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_ldexp_f64 v[22:23], v[28:29], -2
	v_add_f64 v[16:17], v[28:29], -v[16:17]
	v_add_f64 v[18:19], v[18:19], -v[26:27]
	v_add_f64 v[26:27], v[30:31], v[14:15]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[22:23]|
	v_add_f64 v[16:17], v[20:21], -v[16:17]
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[12:13], v[12:13], v[18:19]
	v_fract_f64_e32 v[18:19], v[22:23]
	v_add_f64 v[20:21], v[26:27], v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v19, 0, v19 :: v_dual_cndmask_b32 v18, 0, v18
	v_ldexp_f64 v[18:19], v[18:19], 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[22:23], v[16:17], v[20:21]
	v_add_f64 v[28:29], v[22:23], v[18:19]
	v_add_f64 v[16:17], v[22:23], -v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_gt_f64_e32 vcc_lo, 0, v[28:29]
	v_add_f64 v[28:29], v[26:27], -v[30:31]
	v_cndmask_b32_e64 v33, 0, 0x40100000, vcc_lo
	v_add_f64 v[37:38], v[26:27], -v[28:29]
	v_add_f64 v[14:15], v[14:15], -v[28:29]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_f64 v[18:19], v[18:19], v[32:33]
	v_add_f64 v[33:34], v[20:21], -v[26:27]
	v_add_f64 v[28:29], v[30:31], -v[37:38]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[35:36], v[22:23], v[18:19]
	v_add_f64 v[39:40], v[20:21], -v[33:34]
	v_add_f64 v[12:13], v[12:13], -v[33:34]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f64 v[14:15], v[14:15], v[28:29]
	v_cvt_i32_f64_e32 v35, v[35:36]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[26:27], v[26:27], -v[39:40]
	v_cvt_f64_i32_e32 v[33:34], v35
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[12:13], v[12:13], v[26:27]
	v_add_f64 v[18:19], v[18:19], -v[33:34]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[12:13], v[14:15], v[12:13]
	v_add_f64 v[14:15], v[20:21], -v[16:17]
	v_add_f64 v[24:25], v[22:23], v[18:19]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[10:11], v[10:11], v[12:13]
	v_add_f64 v[12:13], v[24:25], -v[18:19]
	v_cmp_le_f64_e32 vcc_lo, 0.5, v[24:25]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[10:11], v[14:15], v[10:11]
	v_add_f64 v[12:13], v[22:23], -v[12:13]
	v_cndmask_b32_e64 v33, 0, 0x3ff00000, vcc_lo
	v_add_co_ci_u32_e64 v14, s0, 0, v35, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[10:11], v[10:11], v[12:13]
	v_add_f64 v[12:13], v[24:25], -v[32:33]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[15:16], v[12:13], v[10:11]
	v_mul_f64 v[17:18], v[15:16], s[6:7]
	v_add_f64 v[12:13], v[15:16], -v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[19:20], v[15:16], s[6:7], -v[17:18]
	v_add_f64 v[10:11], v[10:11], -v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[15:16], s[8:9], v[19:20]
	v_fma_f64 v[12:13], v[10:11], s[6:7], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[10:11], v[17:18], v[12:13]
	v_add_f64 v[15:16], v[10:11], -v[17:18]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[12:13], v[12:13], -v[15:16]
.LBB1_7:                                ; %Flow
	s_and_not1_saveexec_b32 s0, s1
	s_cbranch_execz .LBB1_9
; %bb.8:
	s_mov_b32 s6, 0x6dc9c883
	s_mov_b32 s7, 0x3fe45f30
	s_mov_b32 s9, 0xbc91a626
	v_mul_f64 v[10:11], |v[8:9]|, s[6:7]
	s_mov_b32 s6, 0x54442d18
	s_mov_b32 s7, 0xbff921fb
	s_mov_b32 s8, 0x33145c00
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[14:15], v[10:11]
	v_fma_f64 v[10:11], v[14:15], s[6:7], |v[8:9]|
	v_mul_f64 v[12:13], v[14:15], s[8:9]
	s_mov_b32 s6, 0x252049c0
	s_mov_b32 s7, 0xb97b839a
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[18:19], v[14:15], s[8:9], v[10:11]
	v_add_f64 v[16:17], v[10:11], v[12:13]
	s_mov_b32 s9, 0x3c91a626
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[10:11], v[10:11], -v[16:17]
	v_add_f64 v[16:17], v[16:17], -v[18:19]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[10:11], v[10:11], v[12:13]
	v_fma_f64 v[12:13], v[14:15], s[8:9], v[12:13]
	v_add_f64 v[10:11], v[16:17], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[10:11], v[10:11], -v[12:13]
	v_fma_f64 v[12:13], v[14:15], s[6:7], v[10:11]
	v_cvt_i32_f64_e32 v14, v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[10:11], v[18:19], v[12:13]
	v_add_f64 v[16:17], v[10:11], -v[18:19]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[12:13], v[12:13], -v[16:17]
.LBB1_9:                                ; %_ZL3sind.exit
	s_or_b32 exec_lo, exec_lo, s0
	v_mul_f64 v[15:16], v[4:5], v[4:5]
	v_mul_f64 v[17:18], v[10:11], v[10:11]
	s_mov_b32 s0, 0xb42fdfa7
	s_mov_b32 s6, 0xf9a43bb8
	s_mov_b32 s1, 0xbe5ae600
	s_mov_b32 s7, 0x3de5e0b2
	s_mov_b32 s16, 0x796cde01
	s_mov_b32 s17, 0x3ec71de3
	s_mov_b32 s8, 0x9037ab78
	s_mov_b32 s14, 0x46cc5e42
	s_mov_b32 s9, 0x3e21eeb6
	s_mov_b32 s15, 0xbda907db
	v_mul_f64 v[33:34], v[6:7], 0.5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f64 v[41:42], v[12:13], 0.5
	v_fma_f64 v[19:20], v[15:16], s[6:7], s[0:1]
	s_delay_alu instid0(VALU_DEP_4)
	v_fma_f64 v[23:24], v[17:18], s[6:7], s[0:1]
	v_mul_f64 v[25:26], v[15:16], 0.5
	v_fma_f64 v[21:22], v[15:16], s[14:15], s[8:9]
	v_mul_f64 v[27:28], v[17:18], 0.5
	v_fma_f64 v[29:30], v[17:18], s[14:15], s[8:9]
	s_mov_b32 s6, 0x19e83e5c
	s_mov_b32 s7, 0xbf2a01a0
	s_mov_b32 s0, 0xa17f65f6
	s_mov_b32 s1, 0xbe927e4f
	s_mov_b32 s14, 0x11110bb3
	s_mov_b32 s15, 0x3f811111
	v_mul_f64 v[35:36], v[4:5], -v[15:16]
	s_mov_b32 s8, 0x19f4ec90
	s_mov_b32 s9, 0x3efa01a0
	v_mul_f64 v[43:44], v[10:11], -v[17:18]
	v_fma_f64 v[19:20], v[15:16], v[19:20], s[16:17]
	v_fma_f64 v[23:24], v[17:18], v[23:24], s[16:17]
	v_add_f64 v[31:32], -v[25:26], 1.0
	v_fma_f64 v[21:22], v[15:16], v[21:22], s[0:1]
	v_add_f64 v[37:38], -v[27:28], 1.0
	v_fma_f64 v[29:30], v[17:18], v[29:30], s[0:1]
	s_mov_b32 s0, 0x16c16967
	s_mov_b32 s1, 0xbf56c16c
	v_fma_f64 v[19:20], v[15:16], v[19:20], s[6:7]
	v_fma_f64 v[23:24], v[17:18], v[23:24], s[6:7]
	v_add_f64 v[39:40], -v[31:32], 1.0
	v_fma_f64 v[21:22], v[15:16], v[21:22], s[8:9]
	v_add_f64 v[45:46], -v[37:38], 1.0
	v_fma_f64 v[29:30], v[17:18], v[29:30], s[8:9]
	s_mov_b32 s6, 0x55555555
	s_mov_b32 s7, 0x3fa55555
	v_fma_f64 v[19:20], v[15:16], v[19:20], s[14:15]
	v_fma_f64 v[23:24], v[17:18], v[23:24], s[14:15]
	v_add_f64 v[25:26], v[39:40], -v[25:26]
	v_fma_f64 v[21:22], v[15:16], v[21:22], s[0:1]
	v_add_f64 v[27:28], v[45:46], -v[27:28]
	v_fma_f64 v[29:30], v[17:18], v[29:30], s[0:1]
	s_mov_b32 s1, 0xbfc55555
	s_mov_b32 s0, s6
	v_fma_f64 v[19:20], v[35:36], v[19:20], v[33:34]
	v_fma_f64 v[23:24], v[43:44], v[23:24], v[41:42]
	v_fma_f64 v[25:26], v[4:5], -v[6:7], v[25:26]
	v_mul_f64 v[33:34], v[15:16], v[15:16]
	v_fma_f64 v[21:22], v[15:16], v[21:22], s[6:7]
	v_fma_f64 v[27:28], v[10:11], -v[12:13], v[27:28]
	v_fma_f64 v[6:7], v[15:16], v[19:20], -v[6:7]
	v_mul_f64 v[15:16], v[17:18], v[17:18]
	v_fma_f64 v[19:20], v[17:18], v[29:30], s[6:7]
	v_fma_f64 v[12:13], v[17:18], v[23:24], -v[12:13]
	v_fma_f64 v[17:18], v[33:34], v[21:22], v[25:26]
	v_fma_f64 v[6:7], v[35:36], s[0:1], v[6:7]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[15:16], v[15:16], v[19:20], v[27:28]
	v_fma_f64 v[12:13], v[43:44], s[0:1], v[12:13]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_f64 v[17:18], v[31:32], v[17:18]
	v_cmp_class_f64_e64 s0, v[2:3], 0x1f8
	v_add_f64 v[4:5], v[4:5], -v[6:7]
	v_and_b32_e32 v19, 1, v0
	v_add_f64 v[6:7], v[37:38], v[15:16]
	v_add_f64 v[10:11], v[10:11], -v[12:13]
	v_and_b32_e32 v3, 1, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_eq_u32_e32 vcc_lo, 0, v19
	v_xor_b32_e32 v2, 0x80000000, v5
	v_cndmask_b32_e32 v4, v4, v17, vcc_lo
	v_cndmask_b32_e32 v2, v2, v18, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v3
	v_dual_cndmask_b32 v5, v6, v10 :: v_dual_lshlrev_b32 v0, 30, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v0, 0x80000000, v0
	v_xor_b32_e32 v0, v2, v0
	v_cndmask_b32_e64 v2, 0, v4, s0
	v_cndmask_b32_e32 v4, v7, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v3, 0x7ff80000, v0, s0
	v_cmp_class_f64_e64 s0, v[8:9], 0x1f8
	v_lshlrev_b32_e32 v0, 30, v14
	v_mul_f64 v[2:3], v[2:3], s[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v0, v0, v9
	v_and_b32_e32 v0, 0x80000000, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v0, v4, v0
	v_cndmask_b32_e64 v4, 0, v5, s0
	v_cndmask_b32_e64 v5, 0x7ff80000, v0, s0
	s_add_i32 s0, s2, -1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[2:3], v[2:3], v[4:5], s[10:11]
	v_mad_u64_u32 v[4:5], null, s0, s3, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[0:1], 3, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	global_store_b64 v[0:1], v[2:3], off
.LBB1_10:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _ZN7kernels11initialiseVEPdS0_S0_dddddddii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 344
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 47
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_ZN7kernels11initialiseVEPdS0_S0_dddddddii, .Lfunc_end1-_ZN7kernels11initialiseVEPdS0_S0_dddddddii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3428
; NumSgprs: 26
; NumVgprs: 47
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 47
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           8
        .value_kind:     by_value
      - .offset:         56
        .size:           8
        .value_kind:     by_value
      - .offset:         64
        .size:           8
        .value_kind:     by_value
      - .offset:         72
        .size:           8
        .value_kind:     by_value
      - .offset:         80
        .size:           4
        .value_kind:     by_value
      - .offset:         84
        .size:           4
        .value_kind:     by_value
      - .offset:         88
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         92
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         96
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         100
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         102
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         104
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         106
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         108
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         110
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         144
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         152
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 344
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZN7kernels11initialiseUEPdS0_S0_dddddddii
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _ZN7kernels11initialiseUEPdS0_S0_dddddddii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     48
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           8
        .value_kind:     by_value
      - .offset:         56
        .size:           8
        .value_kind:     by_value
      - .offset:         64
        .size:           8
        .value_kind:     by_value
      - .offset:         72
        .size:           8
        .value_kind:     by_value
      - .offset:         80
        .size:           4
        .value_kind:     by_value
      - .offset:         84
        .size:           4
        .value_kind:     by_value
      - .offset:         88
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         92
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         96
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         100
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         102
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         104
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         106
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         108
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         110
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         144
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         152
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 344
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _ZN7kernels11initialiseVEPdS0_S0_dddddddii
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         _ZN7kernels11initialiseVEPdS0_S0_dddddddii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     47
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
