/* File: matmult-cuda-float.cu
 *
 * Purpose: 
 * 
 * Input:
 * 
 * Output:
 * 
 * Compile: nvcc -o matmult-cuda-float.o matmult-cuda-float.cu
 * 
 * Run: ./matmult-cuda-float.o
 * 
 * Algorithm:
 * 
 * Note:
 * 
 * */

#include <stdio.h>
#include <cuda_runtime.h>

__global__ void VecAdd(float* A, float* B, float* C, int N)
{
	int index = blockIdx.x * blockDim.x + threadIdx.x; //indice del vector 
	int ix; //ix indica el renglon 
    int iy; //iy toma valores solo entre 0 a N-1
	float result; //Acumula la suma del renglon por la columna 
	int k; // Iterador 
	
	if(index < N * N)
	{
		ix = index / N;
		iy = index % N;
		result = 0.0;

		for(k = 0; k < N; k++)
			result += A[k + N * ix] * B[k * N + iy ];

		C[iy + N * ix] = result;
	}
}

// Host code
int main()
{
    //Variables 
	int N;              // Tamaño de la matriz cuadrada.
    int i;              // Indice del renglon.
    int j;              // Indice de la columna.
	size_t size;        // Tamaño total en memoria.
	float* h_A;         // Matriz A en el equipo.
    float* h_B;         // Matriz B en el equipo.
    float* h_C;         // Matriz C (resultado) en el equipo.
    float* d_A;         // Matriz A en la memoria de la GPU.
    float* d_B;         // Matriz B en la memoria de la GPU.
    float* d_C;         // Matriz C (resultado) en la memoria de la GPU.
    int Tam;            // Numero de datos que se manejan
    int NumHilos;       // Hilos por bloque 
    int numBlock;       // Numero de bloques necesario para procesar los datos 

    //Asignacion de variables
    N = 2500;
    size = N * sizeof(float) * N;

    //En la memoria del equipo 
	h_A = (float*)malloc(size);
	h_B = (float*)malloc(size);
	h_C = (float*)malloc(size);
	
	//En la memoria de la GPU
	cudaMalloc(&d_A, size);
	cudaMalloc(&d_B, size);
    cudaMalloc(&d_C, size);

	//
    Tam = N * N;
    NumHilos = 1024;
	numBlock = Tam / NumHilos; 

	if(Tam % NumHilos > 0) //Si sobran datos, aumenta los bloques en 1
	    numBlock++;
	
	// LLena los arreglos A y B
	for(i = 0;i < N;i++) //Renglon 
		for(j = 0;j < N;j++) // Columna 
		{
			h_A[j + i * N] = rand() % (11 * (i + 1)) * 1.12;
			h_B[j + i * N] = rand() % (11 * (i + 1)) * 1.12;
		}

	//Copia los arreglos de memoria del CPU a memoria de la GPU 
	cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
	cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);

	// Invoke kernel
	VecAdd<<<numBlock, NumHilos >>>(d_A, d_B, d_C, N);

    //Copea el resultado de la multiplicacion de memoria de la GPU a memoria de la CPU
	cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
/*	
	//Imprime la matriz A
	printf("Matriz A\n");
	for(i = 0;i < N;i++)
	{
		for(j = 0;j < N;j++)
			printf("%.2f ", h_A[j + i * N]);
		printf("\n");
	}
	
    //Imprime la matriz B
	printf("Matriz B\n");
	for(i = 0;i < N;i++)
	{
		for(j = 0;j < N;j++)
			printf("%.2f ", h_B[j + i * N]);
		printf("\n");
	}
	
    //Imprime la matriz C
	printf("Matriz C\n");
	for(i = 0;i < N;i++)
	{
		for(j = 0;j < N;j++)
			printf("%.2f ", h_C[j + i * N]);
		printf("\n");
	}*/

	//Libera la memoria utilizada.
	// Free device memory
	cudaFree(d_A);
	cudaFree(d_B);
	cudaFree(d_C);
	// Free host memory
	free(h_A);
	free(h_B);
	free(h_C);
}
	.file	"tmpxft_0023000d_00000000-6_matmult-cuda-float.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i
	.type	_Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i, @function
_Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z6VecAddPfS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i, .-_Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i
	.globl	_Z6VecAddPfS_S_i
	.type	_Z6VecAddPfS_S_i, @function
_Z6VecAddPfS_S_i:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i
	.cfi_endproc
.LFE2053:
	.size	_Z6VecAddPfS_S_i, .-_Z6VecAddPfS_S_i
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$25000000, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$88, %rsp
	.cfi_def_cfa_offset 144
	movq	%fs:40, %rax
	movq	%rax, 72(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$25000000, %edi
	movq	%rax, %r12
	call	malloc@PLT
	movl	$25000000, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	leaq	24(%rsp), %rdi
	movl	$25000000, %esi
	movq	%rax, (%rsp)
	call	cudaMalloc@PLT
	leaq	32(%rsp), %rdi
	movl	$25000000, %esi
	call	cudaMalloc@PLT
	movl	$25000000, %esi
	leaq	40(%rsp), %rdi
	call	cudaMalloc@PLT
	xorl	%esi, %esi
.L9:
	imulq	$10000, %rsi, %r14
	leal	1(%rsi), %ebx
	xorl	%r13d, %r13d
	imull	$11, %ebx, %ebx
	leaq	(%r12,%r14), %r15
	addq	%rbp, %r14
.L10:
	movq	%rsi, 8(%rsp)
	call	rand@PLT
	cltd
	idivl	%ebx
	cvtsi2sdl	%edx, %xmm0
	mulsd	.LC0(%rip), %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, (%r15,%r13)
	call	rand@PLT
	movq	8(%rsp), %rsi
	cltd
	idivl	%ebx
	cvtsi2sdl	%edx, %xmm0
	mulsd	.LC0(%rip), %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, (%r14,%r13)
	addq	$4, %r13
	cmpq	$10000, %r13
	jne	.L10
	incq	%rsi
	cmpq	$2500, %rsi
	jne	.L9
	movq	24(%rsp), %rdi
	movl	$1, %ecx
	movl	$25000000, %edx
	movq	%r12, %rsi
	call	cudaMemcpy@PLT
	movq	32(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$25000000, %edx
	call	cudaMemcpy@PLT
	movl	$4194305, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$536871675, %edi
	salq	$10, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	salq	$3, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	movq	40(%rsp), %rdx
	movq	32(%rsp), %rsi
	movl	$2500, %ecx
	movq	24(%rsp), %rdi
	call	_Z30__device_stub__Z6VecAddPfS_S_iPfS_S_i
.L12:
	movq	40(%rsp), %rsi
	movq	(%rsp), %rdi
	movl	$2, %ecx
	movl	$25000000, %edx
	call	cudaMemcpy@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	%r12, %rdi
	call	free@PLT
	movq	%rbp, %rdi
	call	free@PLT
	movq	(%rsp), %rdi
	call	free@PLT
	movq	72(%rsp), %rax
	subq	%fs:40, %rax
	je	.L13
	call	__stack_chk_fail@PLT
.L13:
	addq	$88, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"_Z6VecAddPfS_S_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC1(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z6VecAddPfS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC0:
	.long	515396076
	.long	1072819077
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/* File: matmult-cuda-float.cu
 *
 * Purpose: 
 * 
 * Input:
 * 
 * Output:
 * 
 * Compile: nvcc -o matmult-cuda-float.o matmult-cuda-float.cu
 * 
 * Run: ./matmult-cuda-float.o
 * 
 * Algorithm:
 * 
 * Note:
 * 
 * */

#include <stdio.h>
#include <hip/hip_runtime.h>

__global__ void VecAdd(float* A, float* B, float* C, int N)
{
	int index = blockIdx.x * blockDim.x + threadIdx.x; //indice del vector 
	int ix; //ix indica el renglon 
    int iy; //iy toma valores solo entre 0 a N-1
	float result; //Acumula la suma del renglon por la columna 
	int k; // Iterador 
	
	if(index < N * N)
	{
		ix = index / N;
		iy = index % N;
		result = 0.0;

		for(k = 0; k < N; k++)
			result += A[k + N * ix] * B[k * N + iy ];

		C[iy + N * ix] = result;
	}
}

// Host code
int main()
{
    //Variables 
	int N;              // Tamaño de la matriz cuadrada.
    int i;              // Indice del renglon.
    int j;              // Indice de la columna.
	size_t size;        // Tamaño total en memoria.
	float* h_A;         // Matriz A en el equipo.
    float* h_B;         // Matriz B en el equipo.
    float* h_C;         // Matriz C (resultado) en el equipo.
    float* d_A;         // Matriz A en la memoria de la GPU.
    float* d_B;         // Matriz B en la memoria de la GPU.
    float* d_C;         // Matriz C (resultado) en la memoria de la GPU.
    int Tam;            // Numero de datos que se manejan
    int NumHilos;       // Hilos por bloque 
    int numBlock;       // Numero de bloques necesario para procesar los datos 

    //Asignacion de variables
    N = 2500;
    size = N * sizeof(float) * N;

    //En la memoria del equipo 
	h_A = (float*)malloc(size);
	h_B = (float*)malloc(size);
	h_C = (float*)malloc(size);
	
	//En la memoria de la GPU
	hipMalloc(&d_A, size);
	hipMalloc(&d_B, size);
    hipMalloc(&d_C, size);

	//
    Tam = N * N;
    NumHilos = 1024;
	numBlock = Tam / NumHilos; 

	if(Tam % NumHilos > 0) //Si sobran datos, aumenta los bloques en 1
	    numBlock++;
	
	// LLena los arreglos A y B
	for(i = 0;i < N;i++) //Renglon 
		for(j = 0;j < N;j++) // Columna 
		{
			h_A[j + i * N] = rand() % (11 * (i + 1)) * 1.12;
			h_B[j + i * N] = rand() % (11 * (i + 1)) * 1.12;
		}

	//Copia los arreglos de memoria del CPU a memoria de la GPU 
	hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
	hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);

	// Invoke kernel
	VecAdd<<<numBlock, NumHilos >>>(d_A, d_B, d_C, N);

    //Copea el resultado de la multiplicacion de memoria de la GPU a memoria de la CPU
	hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
/*	
	//Imprime la matriz A
	printf("Matriz A\n");
	for(i = 0;i < N;i++)
	{
		for(j = 0;j < N;j++)
			printf("%.2f ", h_A[j + i * N]);
		printf("\n");
	}
	
    //Imprime la matriz B
	printf("Matriz B\n");
	for(i = 0;i < N;i++)
	{
		for(j = 0;j < N;j++)
			printf("%.2f ", h_B[j + i * N]);
		printf("\n");
	}
	
    //Imprime la matriz C
	printf("Matriz C\n");
	for(i = 0;i < N;i++)
	{
		for(j = 0;j < N;j++)
			printf("%.2f ", h_C[j + i * N]);
		printf("\n");
	}*/

	//Libera la memoria utilizada.
	// Free device memory
	hipFree(d_A);
	hipFree(d_B);
	hipFree(d_C);
	// Free host memory
	free(h_A);
	free(h_B);
	free(h_C);
}
	.text
	.file	"matmult-cuda-float.hip"
	.globl	_Z21__device_stub__VecAddPfS_S_i # -- Begin function _Z21__device_stub__VecAddPfS_S_i
	.type	_Z21__device_stub__VecAddPfS_S_i,@function
_Z21__device_stub__VecAddPfS_S_i:       # @_Z21__device_stub__VecAddPfS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6VecAddPfS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z21__device_stub__VecAddPfS_S_i, .Lfunc_end0-_Z21__device_stub__VecAddPfS_S_i
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI1_0:
	.quad	0x3ff1eb851eb851ec              # double 1.1200000000000001
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$56, %rsp
	.cfi_def_cfa_offset 112
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$25000000, %edi                 # imm = 0x17D7840
	callq	malloc
	movq	%rax, %rbp
	movl	$25000000, %edi                 # imm = 0x17D7840
	callq	malloc
	movq	%rax, %r14
	movl	$25000000, %edi                 # imm = 0x17D7840
	callq	malloc
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	leaq	24(%rsp), %rdi
	movl	$25000000, %esi                 # imm = 0x17D7840
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movl	$25000000, %esi                 # imm = 0x17D7840
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movl	$25000000, %esi                 # imm = 0x17D7840
	callq	hipMalloc
	xorl	%r12d, %r12d
	movl	$10000, %r13d                   # imm = 0x2710
	movq	%rbp, 48(%rsp)                  # 8-byte Spill
	movq	%r14, 40(%rsp)                  # 8-byte Spill
.LBB1_1:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_2 Depth 2
	leal	(%r12,%r12,4), %eax
	leal	(%r12,%rax,2), %ebx
	addl	$11, %ebx
	xorl	%r15d, %r15d
.LBB1_2:                                #   Parent Loop BB1_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
	cltd
	idivl	%ebx
	xorps	%xmm0, %xmm0
	cvtsi2sd	%edx, %xmm0
	mulsd	.LCPI1_0(%rip), %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, (%rbp,%r15,4)
	callq	rand
	movsd	.LCPI1_0(%rip), %xmm1           # xmm1 = mem[0],zero
	cltd
	idivl	%ebx
	xorps	%xmm0, %xmm0
	cvtsi2sd	%edx, %xmm0
	mulsd	%xmm1, %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, (%r14,%r15,4)
	incq	%r15
	cmpq	$2500, %r15                     # imm = 0x9C4
	jne	.LBB1_2
# %bb.3:                                #   in Loop: Header=BB1_1 Depth=1
	incq	%r12
	addq	%r13, %r14
	addq	%r13, %rbp
	cmpq	$2500, %r12                     # imm = 0x9C4
	jne	.LBB1_1
# %bb.4:
	movq	24(%rsp), %rdi
	movl	$25000000, %edx                 # imm = 0x17D7840
	movq	48(%rsp), %rbx                  # 8-byte Reload
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rdi
	movl	$25000000, %edx                 # imm = 0x17D7840
	movq	40(%rsp), %r14                  # 8-byte Reload
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$4294968320, %rdx               # imm = 0x100000400
	leaq	5080(%rdx), %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_6
# %bb.5:
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	movl	$2500, %ecx                     # imm = 0x9C4
	callq	_Z21__device_stub__VecAddPfS_S_i
.LBB1_6:
	movq	8(%rsp), %rsi
	movl	$25000000, %edx                 # imm = 0x17D7840
	movq	32(%rsp), %r15                  # 8-byte Reload
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	xorl	%eax, %eax
	addq	$56, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6VecAddPfS_S_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z6VecAddPfS_S_i,@object        # @_Z6VecAddPfS_S_i
	.section	.rodata,"a",@progbits
	.globl	_Z6VecAddPfS_S_i
	.p2align	3, 0x0
_Z6VecAddPfS_S_i:
	.quad	_Z21__device_stub__VecAddPfS_S_i
	.size	_Z6VecAddPfS_S_i, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z6VecAddPfS_S_i"
	.size	.L__unnamed_1, 17

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z21__device_stub__VecAddPfS_S_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z6VecAddPfS_S_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z6VecAddPfS_S_i        ; -- Begin function _Z6VecAddPfS_S_i
	.globl	_Z6VecAddPfS_S_i
	.p2align	8
	.type	_Z6VecAddPfS_S_i,@function
_Z6VecAddPfS_S_i:                       ; @_Z6VecAddPfS_S_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x2c
	s_load_b32 s2, s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
	s_mul_i32 s3, s2, s2
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s3, v1
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB0_6
; %bb.1:
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	v_ashrrev_i32_e32 v2, 31, v1
	s_cmp_lt_i32 s2, 1
	s_cbranch_scc1 .LBB0_4
; %bb.2:                                ; %.lr.ph.preheader
	s_ashr_i32 s3, s2, 31
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v4, v1, v2
	s_add_i32 s8, s2, s3
	s_xor_b32 s3, s8, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v4, v4, v2
	v_cvt_f32_u32_e32 v0, s3
	s_sub_i32 s8, 0, s3
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_mul_lo_u32 v3, s8, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v0, v3
	v_add_nc_u32_e32 v0, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v0, v4, v0
	v_mul_lo_u32 v0, v0, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v4, v0
	v_subrev_nc_u32_e32 v3, s3, v0
	v_cmp_le_u32_e32 vcc_lo, s3, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v3, vcc_lo
	v_subrev_nc_u32_e32 v3, s3, v0
	v_cmp_le_u32_e32 vcc_lo, s3, v0
	s_mov_b32 s3, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v3, vcc_lo
	v_xor_b32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v3, v0, v2
	v_mov_b32_e32 v0, 0
	v_sub_nc_u32_e32 v5, v1, v3
.LBB0_3:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, s3, v5
	v_ashrrev_i32_e32 v4, 31, v3
	s_add_i32 s3, s3, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_cmp_lg_u32 s2, s3
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[8:9], 2, v[3:4]
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v8, vcc_lo, s6, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s7, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v6, vcc_lo, s4, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	global_load_b32 v4, v[8:9], off
	global_load_b32 v6, v[6:7], off
	s_waitcnt vmcnt(0)
	v_dual_fmac_f32 v0, v6, v4 :: v_dual_add_nc_u32 v3, s2, v3
	s_cbranch_scc1 .LBB0_3
	s_branch .LBB0_5
.LBB0_4:
	v_mov_b32_e32 v0, 0
.LBB0_5:                                ; %._crit_edge
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v1, vcc_lo, s0, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_store_b32 v[1:2], v0, off
.LBB0_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6VecAddPfS_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z6VecAddPfS_S_i, .Lfunc_end0-_Z6VecAddPfS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 440
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6VecAddPfS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z6VecAddPfS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
