//Darrien Park

#include "cuda_runtime.h"
#include "device_launch_parameters.h"
#include <stdio.h>
#include <string.h>
#include <time.h>
#include <stdlib.h>
#define BLOCK_SIZE 16

const size_t w = 200;

//kernel functions to be called from the host and executed in the gpu
//produces one output matrix element per thread
__global__ void MatrixAddKernel(float* a, float *b, float *sum, int width){

	int row = blockIdx.y*blockDim.y + threadIdx.y;
	int col = blockIdx.x*blockDim.x + threadIdx.x;

	if (row < width && col < width){					//only threads within range
			sum[row*width + col] = a[row*width + col] + b[row*width + col];
	}
}

//produces one output matrix row per thread
__global__ void MatrixAddRow(float* a, float *b, float *sum, int width){

	int row = blockIdx.x*blockDim.x + threadIdx.x;

	if (row < width){				//only threads within range
		int j;
		for (j = 0; j < width; j++)
			sum[row*width + j] = a[row*width + j] + b[row*width + j];
	}
}

//produces one output matrix row per thread
__global__ void MatrixAddCol(float* a, float *b, float *sum, int width){

	int col = blockIdx.x*blockDim.x + threadIdx.x;

	if (col < width){				//only threads within range
		for (int i = 0; i < width; i++)
			sum[col + width*i] = a[col + width* i] + b[col + width * i];
	}

}

//define a new type for matrix so that matrices can be stored on the heap; execution will not crash on large matrix sizes
typedef float squareMatrix[w];

//function to check if the resultant matrix from the CPU is the same as the GPU
void correct_output(squareMatrix *CPUout, squareMatrix *GPUout, int width){
	for (int i = 0; i < width; i++)
		for (int j = 0; j < width; j++){
			if (CPUout[i][j] != GPUout[i][j])
				printf("TEST FAILED\n");
		}
	printf("TEST PASSED\n");
}

int main(){
	//define and initialize variables, allocate memory in heap for matrices
	int size = w*w*sizeof(float);
	squareMatrix *a, *b, *GPUsum, *CPUsum;
	a		= (squareMatrix *)malloc(size);
	b		= (squareMatrix *)malloc(size);
	GPUsum	= (squareMatrix *)malloc(size);
	CPUsum	= (squareMatrix *)malloc(size);

	//populate the matrix with randum numbers between 0 and 10 to read output easily
	srand(time(NULL));
	for(int i =0; i<w; i++)
		for(int j=0;j<w;j++){
			a[i][j] = rand() % (10 + 1 - 0) + 0;
			b[i][j] = rand() % (10 + 1 - 0) + 0;
		}

	//find number of blocks required which is width = width of matrix/block size
	int NumBlocks = w/BLOCK_SIZE;
	//if remainder, extra block is needed
	if(w % BLOCK_SIZE) NumBlocks++;
	//set grid dimensions
	dim3 dimGrid(NumBlocks,NumBlocks);	//for 16x16 parameters are (NumBlocks, Numblocks), for 16 block/thread (Numblocks)
	//set block dimensions 16x16
	dim3 dimBlock(BLOCK_SIZE,BLOCK_SIZE);	//for 16x16 (BLOCK_SIZE, BLOCK_SIZE)


	float *d_a, *d_b, *d_sum;
	//allocate host memory onto device
	cudaMalloc((void**)&d_a, size);
	cudaMalloc((void**)&d_b, size);
	cudaMalloc((void**)&d_sum, size);

	cudaMemcpyAsync(d_a, a, size, cudaMemcpyHostToDevice);
	cudaMemcpyAsync(d_b, b, size, cudaMemcpyHostToDevice);
	cudaMemcpyAsync(d_sum, GPUsum, size, cudaMemcpyHostToDevice);

	cudaEvent_t start,stop;
	cudaEventCreate(&start);
	cudaEventCreate(&stop);
	cudaDeviceSynchronize();
	float gpu_time = 0.0f;

	//record gpu calculation time
	cudaEventRecord(start,0);
	MatrixAddKernel<<<dimGrid,dimBlock>>>(d_a, d_b, d_sum, w);	//change kernel name to compare performance
	cudaEventRecord(stop,0);

	cudaMemcpy(GPUsum, d_sum, size, cudaMemcpyDeviceToHost);

	//CPU calculation runs asynchronously with GPU
	cudaEvent_t CPUstart, CPUstop;
	cudaEventCreate(&CPUstart);
	cudaEventCreate(&CPUstop);
	cudaEventRecord(CPUstart);
	for(int i = 0; i < w; i++)
		for(int j =0; j<w; j++){
			CPUsum[i][j] = a[i][j]+b[i][j];
	}
	cudaEventRecord(CPUstop);
	cudaEventSynchronize(CPUstop);
	float cpu_time = 0.0f;
	cudaEventElapsedTime(&cpu_time, CPUstart, CPUstop);
	printf("Time spent executing bv the CPU: %.2f\n",cpu_time);

	unsigned long int counter = 0;
	while(cudaEventQuery(stop) == cudaErrorNotReady){
		counter ++;
	}

	cudaEventElapsedTime(&gpu_time,start,stop);

	printf("Time spent executing bv the GPU: %.2f\n",gpu_time);

	correct_output(CPUsum, GPUsum, w);

	//free memory space pointed to by host
	cudaFreeHost(a);
	cudaFreeHost(b);
	cudaFreeHost(GPUsum);
	//free memory space pointed to by device
	cudaFree(d_a);
	cudaFree(d_b);
	cudaFree(d_sum);
	cudaDeviceReset();

	return 0;
}

	.file	"tmpxft_0023136f_00000000-6_mp2.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"TEST FAILED\n"
.LC1:
	.string	"TEST PASSED\n"
	.text
	.globl	_Z14correct_outputPA200_fS0_i
	.type	_Z14correct_outputPA200_fS0_i, @function
_Z14correct_outputPA200_fS0_i:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movslq	%edx, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	xorl	%r14d, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%r15, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movq	%rsi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rdi, %rbx
	pushq	%rcx
	.cfi_def_cfa_offset 64
.L3:
	cmpl	%r13d, %r14d
	jge	.L12
	xorl	%r12d, %r12d
.L6:
	movss	(%rbx,%r12,4), %xmm0
	ucomiss	0(%rbp,%r12,4), %xmm0
	jp	.L8
	je	.L4
.L8:
	leaq	.LC0(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L4:
	incq	%r12
	cmpq	%r15, %r12
	jne	.L6
	incl	%r14d
	addq	$800, %rbx
	addq	$800, %rbp
	jmp	.L3
.L12:
	popq	%rdx
	.cfi_def_cfa_offset 56
	leaq	.LC1(%rip), %rsi
	popq	%rbx
	.cfi_def_cfa_offset 48
	movl	$2, %edi
	popq	%rbp
	.cfi_def_cfa_offset 40
	xorl	%eax, %eax
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	__printf_chk@PLT
	.cfi_endproc
.LFE2027:
	.size	_Z14correct_outputPA200_fS0_i, .-_Z14correct_outputPA200_fS0_i
	.globl	_Z40__device_stub__Z15MatrixAddKernelPfS_S_iPfS_S_i
	.type	_Z40__device_stub__Z15MatrixAddKernelPfS_S_iPfS_S_i, @function
_Z40__device_stub__Z15MatrixAddKernelPfS_S_iPfS_S_i:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z15MatrixAddKernelPfS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L13:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z40__device_stub__Z15MatrixAddKernelPfS_S_iPfS_S_i, .-_Z40__device_stub__Z15MatrixAddKernelPfS_S_iPfS_S_i
	.globl	_Z15MatrixAddKernelPfS_S_i
	.type	_Z15MatrixAddKernelPfS_S_i, @function
_Z15MatrixAddKernelPfS_S_i:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z15MatrixAddKernelPfS_S_iPfS_S_i
	.cfi_endproc
.LFE2054:
	.size	_Z15MatrixAddKernelPfS_S_i, .-_Z15MatrixAddKernelPfS_S_i
	.section	.rodata.str1.1
.LC3:
	.string	"Time spent executing bv the CPU: %.2f\n"
.LC4:
	.string	"Time spent executing bv the GPU: %.2f\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$160000, %edi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movl	$11, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$136, %rsp
	.cfi_def_cfa_offset 192
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$160000, %edi
	movq	%rax, %r12
	call	malloc@PLT
	movl	$160000, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	movl	$160000, %edi
	movq	%rax, 8(%rsp)
	call	malloc@PLT
	xorl	%edi, %edi
	movq	%rax, %r13
	call	time@PLT
	movl	%eax, %edi
	call	srand@PLT
	xorl	%esi, %esi
.L19:
	leaq	(%rsi,%r12), %r15
	leaq	(%rsi,%rbp), %rdi
	xorl	%ebx, %ebx
.L20:
	movq	%rsi, 24(%rsp)
	movq	%rdi, 16(%rsp)
	call	rand@PLT
	cltd
	idivl	%r14d
	cvtsi2ssl	%edx, %xmm0
	movss	%xmm0, (%r15,%rbx)
	call	rand@PLT
	movq	16(%rsp), %rdi
	movq	24(%rsp), %rsi
	cltd
	idivl	%r14d
	cvtsi2ssl	%edx, %xmm0
	movss	%xmm0, (%rdi,%rbx)
	addq	$4, %rbx
	cmpq	$800, %rbx
	jne	.L20
	addq	$800, %rsi
	cmpq	$160000, %rsi
	jne	.L19
	movabsq	$55834574861, %rax
	leaq	40(%rsp), %rdi
	movl	$160000, %esi
	movl	$1, 104(%rsp)
	movq	%rax, 96(%rsp)
	movabsq	$68719476752, %rax
	movq	%rax, 108(%rsp)
	movl	$1, 116(%rsp)
	call	cudaMalloc@PLT
	leaq	48(%rsp), %rdi
	movl	$160000, %esi
	call	cudaMalloc@PLT
	leaq	56(%rsp), %rdi
	movl	$160000, %esi
	call	cudaMalloc@PLT
	movq	40(%rsp), %rdi
	xorl	%r8d, %r8d
	movq	%r12, %rsi
	movl	$1, %ecx
	movl	$160000, %edx
	call	cudaMemcpyAsync@PLT
	movq	48(%rsp), %rdi
	xorl	%r8d, %r8d
	movq	%rbp, %rsi
	movl	$1, %ecx
	movl	$160000, %edx
	call	cudaMemcpyAsync@PLT
	movq	8(%rsp), %rsi
	movq	56(%rsp), %rdi
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movl	$160000, %edx
	call	cudaMemcpyAsync@PLT
	leaq	64(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	72(%rsp), %rdi
	call	cudaEventCreate@PLT
	call	cudaDeviceSynchronize@PLT
	movq	64(%rsp), %rdi
	xorl	%esi, %esi
	movl	$0x00000000, 32(%rsp)
	call	cudaEventRecord@PLT
	movl	116(%rsp), %ecx
	movl	104(%rsp), %esi
	xorl	%r9d, %r9d
	movq	108(%rsp), %rdx
	movq	96(%rsp), %rdi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L22
	movq	56(%rsp), %rdx
	movq	48(%rsp), %rsi
	movl	$200, %ecx
	movq	40(%rsp), %rdi
	call	_Z40__device_stub__Z15MatrixAddKernelPfS_S_iPfS_S_i
.L22:
	movq	72(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	56(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	$160000, %edx
	movl	$2, %ecx
	call	cudaMemcpy@PLT
	leaq	80(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	88(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	80(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	xorl	%edx, %edx
.L23:
	leaq	(%r12,%rdx), %rdi
	leaq	0(%rbp,%rdx), %rsi
	xorl	%eax, %eax
	leaq	0(%r13,%rdx), %rcx
.L24:
	movss	(%rdi,%rax), %xmm0
	addss	(%rsi,%rax), %xmm0
	movss	%xmm0, (%rcx,%rax)
	addq	$4, %rax
	cmpq	$800, %rax
	jne	.L24
	addq	$800, %rdx
	cmpq	$160000, %rdx
	jne	.L23
	movq	88(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	88(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	80(%rsp), %rsi
	movq	88(%rsp), %rdx
	leaq	36(%rsp), %rdi
	movl	$0x00000000, 36(%rsp)
	call	cudaEventElapsedTime@PLT
	leaq	.LC3(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	36(%rsp), %xmm0
	call	__printf_chk@PLT
.L26:
	movq	72(%rsp), %rdi
	call	cudaEventQuery@PLT
	cmpl	$600, %eax
	je	.L26
	movq	72(%rsp), %rdx
	movq	64(%rsp), %rsi
	leaq	32(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	32(%rsp), %xmm0
	call	__printf_chk@PLT
	movq	8(%rsp), %rsi
	movl	$200, %edx
	movq	%r13, %rdi
	call	_Z14correct_outputPA200_fS0_i
	movq	%r12, %rdi
	call	cudaFreeHost@PLT
	movq	%rbp, %rdi
	call	cudaFreeHost@PLT
	movq	8(%rsp), %rdi
	call	cudaFreeHost@PLT
	movq	40(%rsp), %rdi
	call	cudaFree@PLT
	movq	48(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	call	cudaDeviceReset@PLT
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L27
	call	__stack_chk_fail@PLT
.L27:
	addq	$136, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	main, .-main
	.text
	.globl	_Z37__device_stub__Z12MatrixAddRowPfS_S_iPfS_S_i
	.type	_Z37__device_stub__Z12MatrixAddRowPfS_S_iPfS_S_i, @function
_Z37__device_stub__Z12MatrixAddRowPfS_S_iPfS_S_i:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L33
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z12MatrixAddRowPfS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L33:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L35
	call	__stack_chk_fail@PLT
.L35:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z37__device_stub__Z12MatrixAddRowPfS_S_iPfS_S_i, .-_Z37__device_stub__Z12MatrixAddRowPfS_S_iPfS_S_i
	.globl	_Z12MatrixAddRowPfS_S_i
	.type	_Z12MatrixAddRowPfS_S_i, @function
_Z12MatrixAddRowPfS_S_i:
.LFB2056:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z12MatrixAddRowPfS_S_iPfS_S_i
	.cfi_endproc
.LFE2056:
	.size	_Z12MatrixAddRowPfS_S_i, .-_Z12MatrixAddRowPfS_S_i
	.globl	_Z37__device_stub__Z12MatrixAddColPfS_S_iPfS_S_i
	.type	_Z37__device_stub__Z12MatrixAddColPfS_S_iPfS_S_i, @function
_Z37__device_stub__Z12MatrixAddColPfS_S_iPfS_S_i:
.LFB2057:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L38
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z12MatrixAddColPfS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L38:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L40
	call	__stack_chk_fail@PLT
.L40:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2057:
	.size	_Z37__device_stub__Z12MatrixAddColPfS_S_iPfS_S_i, .-_Z37__device_stub__Z12MatrixAddColPfS_S_iPfS_S_i
	.globl	_Z12MatrixAddColPfS_S_i
	.type	_Z12MatrixAddColPfS_S_i, @function
_Z12MatrixAddColPfS_S_i:
.LFB2058:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z12MatrixAddColPfS_S_iPfS_S_i
	.cfi_endproc
.LFE2058:
	.size	_Z12MatrixAddColPfS_S_i, .-_Z12MatrixAddColPfS_S_i
	.section	.rodata.str1.1
.LC5:
	.string	"_Z12MatrixAddColPfS_S_i"
.LC6:
	.string	"_Z12MatrixAddRowPfS_S_i"
.LC7:
	.string	"_Z15MatrixAddKernelPfS_S_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2060:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z12MatrixAddColPfS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z12MatrixAddRowPfS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC7(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z15MatrixAddKernelPfS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2060:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

//Darrien Park

#include "hip/hip_runtime.h"

#include <stdio.h>
#include <string.h>
#include <time.h>
#include <stdlib.h>
#define BLOCK_SIZE 16

const size_t w = 200;

//kernel functions to be called from the host and executed in the gpu
//produces one output matrix element per thread
__global__ void MatrixAddKernel(float* a, float *b, float *sum, int width){

	int row = blockIdx.y*blockDim.y + threadIdx.y;
	int col = blockIdx.x*blockDim.x + threadIdx.x;

	if (row < width && col < width){					//only threads within range
			sum[row*width + col] = a[row*width + col] + b[row*width + col];
	}
}

//produces one output matrix row per thread
__global__ void MatrixAddRow(float* a, float *b, float *sum, int width){

	int row = blockIdx.x*blockDim.x + threadIdx.x;

	if (row < width){				//only threads within range
		int j;
		for (j = 0; j < width; j++)
			sum[row*width + j] = a[row*width + j] + b[row*width + j];
	}
}

//produces one output matrix row per thread
__global__ void MatrixAddCol(float* a, float *b, float *sum, int width){

	int col = blockIdx.x*blockDim.x + threadIdx.x;

	if (col < width){				//only threads within range
		for (int i = 0; i < width; i++)
			sum[col + width*i] = a[col + width* i] + b[col + width * i];
	}

}

//define a new type for matrix so that matrices can be stored on the heap; execution will not crash on large matrix sizes
typedef float squareMatrix[w];

//function to check if the resultant matrix from the CPU is the same as the GPU
void correct_output(squareMatrix *CPUout, squareMatrix *GPUout, int width){
	for (int i = 0; i < width; i++)
		for (int j = 0; j < width; j++){
			if (CPUout[i][j] != GPUout[i][j])
				printf("TEST FAILED\n");
		}
	printf("TEST PASSED\n");
}

int main(){
	//define and initialize variables, allocate memory in heap for matrices
	int size = w*w*sizeof(float);
	squareMatrix *a, *b, *GPUsum, *CPUsum;
	a		= (squareMatrix *)malloc(size);
	b		= (squareMatrix *)malloc(size);
	GPUsum	= (squareMatrix *)malloc(size);
	CPUsum	= (squareMatrix *)malloc(size);

	//populate the matrix with randum numbers between 0 and 10 to read output easily
	srand(time(NULL));
	for(int i =0; i<w; i++)
		for(int j=0;j<w;j++){
			a[i][j] = rand() % (10 + 1 - 0) + 0;
			b[i][j] = rand() % (10 + 1 - 0) + 0;
		}

	//find number of blocks required which is width = width of matrix/block size
	int NumBlocks = w/BLOCK_SIZE;
	//if remainder, extra block is needed
	if(w % BLOCK_SIZE) NumBlocks++;
	//set grid dimensions
	dim3 dimGrid(NumBlocks,NumBlocks);	//for 16x16 parameters are (NumBlocks, Numblocks), for 16 block/thread (Numblocks)
	//set block dimensions 16x16
	dim3 dimBlock(BLOCK_SIZE,BLOCK_SIZE);	//for 16x16 (BLOCK_SIZE, BLOCK_SIZE)


	float *d_a, *d_b, *d_sum;
	//allocate host memory onto device
	hipMalloc((void**)&d_a, size);
	hipMalloc((void**)&d_b, size);
	hipMalloc((void**)&d_sum, size);

	hipMemcpyAsync(d_a, a, size, hipMemcpyHostToDevice);
	hipMemcpyAsync(d_b, b, size, hipMemcpyHostToDevice);
	hipMemcpyAsync(d_sum, GPUsum, size, hipMemcpyHostToDevice);

	hipEvent_t start,stop;
	hipEventCreate(&start);
	hipEventCreate(&stop);
	hipDeviceSynchronize();
	float gpu_time = 0.0f;

	//record gpu calculation time
	hipEventRecord(start,0);
	MatrixAddKernel<<<dimGrid,dimBlock>>>(d_a, d_b, d_sum, w);	//change kernel name to compare performance
	hipEventRecord(stop,0);

	hipMemcpy(GPUsum, d_sum, size, hipMemcpyDeviceToHost);

	//CPU calculation runs asynchronously with GPU
	hipEvent_t CPUstart, CPUstop;
	hipEventCreate(&CPUstart);
	hipEventCreate(&CPUstop);
	hipEventRecord(CPUstart);
	for(int i = 0; i < w; i++)
		for(int j =0; j<w; j++){
			CPUsum[i][j] = a[i][j]+b[i][j];
	}
	hipEventRecord(CPUstop);
	hipEventSynchronize(CPUstop);
	float cpu_time = 0.0f;
	hipEventElapsedTime(&cpu_time, CPUstart, CPUstop);
	printf("Time spent executing bv the CPU: %.2f\n",cpu_time);

	unsigned long int counter = 0;
	while(hipEventQuery(stop) == hipErrorNotReady){
		counter ++;
	}

	hipEventElapsedTime(&gpu_time,start,stop);

	printf("Time spent executing bv the GPU: %.2f\n",gpu_time);

	correct_output(CPUsum, GPUsum, w);

	//free memory space pointed to by host
	hipHostFree(a);
	hipHostFree(b);
	hipHostFree(GPUsum);
	//free memory space pointed to by device
	hipFree(d_a);
	hipFree(d_b);
	hipFree(d_sum);
	hipDeviceReset();

	return 0;
}

	.text
	.file	"mp2.hip"
	.globl	_Z30__device_stub__MatrixAddKernelPfS_S_i # -- Begin function _Z30__device_stub__MatrixAddKernelPfS_S_i
	.type	_Z30__device_stub__MatrixAddKernelPfS_S_i,@function
_Z30__device_stub__MatrixAddKernelPfS_S_i: # @_Z30__device_stub__MatrixAddKernelPfS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z15MatrixAddKernelPfS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z30__device_stub__MatrixAddKernelPfS_S_i, .Lfunc_end0-_Z30__device_stub__MatrixAddKernelPfS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z27__device_stub__MatrixAddRowPfS_S_i # -- Begin function _Z27__device_stub__MatrixAddRowPfS_S_i
	.type	_Z27__device_stub__MatrixAddRowPfS_S_i,@function
_Z27__device_stub__MatrixAddRowPfS_S_i: # @_Z27__device_stub__MatrixAddRowPfS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12MatrixAddRowPfS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z27__device_stub__MatrixAddRowPfS_S_i, .Lfunc_end1-_Z27__device_stub__MatrixAddRowPfS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z27__device_stub__MatrixAddColPfS_S_i # -- Begin function _Z27__device_stub__MatrixAddColPfS_S_i
	.type	_Z27__device_stub__MatrixAddColPfS_S_i,@function
_Z27__device_stub__MatrixAddColPfS_S_i: # @_Z27__device_stub__MatrixAddColPfS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z12MatrixAddColPfS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z27__device_stub__MatrixAddColPfS_S_i, .Lfunc_end2-_Z27__device_stub__MatrixAddColPfS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z14correct_outputPA200_fS0_i   # -- Begin function _Z14correct_outputPA200_fS0_i
	.type	_Z14correct_outputPA200_fS0_i,@function
_Z14correct_outputPA200_fS0_i:          # @_Z14correct_outputPA200_fS0_i
	.cfi_startproc
# %bb.0:
	testl	%edx, %edx
	jle	.LBB3_8
# %bb.1:                                # %.preheader.lr.ph
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	pushq	%rax
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsi, %rbx
	movq	%rdi, %r14
	movl	%edx, %r15d
	xorl	%r12d, %r12d
	movl	$800, %r13d                     # imm = 0x320
.LBB3_2:                                # %.lr.ph
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB3_3 Depth 2
	xorl	%ebp, %ebp
.LBB3_3:                                #   Parent Loop BB3_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movss	(%r14,%rbp,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	ucomiss	(%rbx,%rbp,4), %xmm0
	jne	.LBB3_4
	jnp	.LBB3_5
.LBB3_4:                                #   in Loop: Header=BB3_3 Depth=2
	movl	$.Lstr.1, %edi
	callq	puts@PLT
.LBB3_5:                                #   in Loop: Header=BB3_3 Depth=2
	incq	%rbp
	cmpq	%rbp, %r15
	jne	.LBB3_3
# %bb.6:                                # %._crit_edge
                                        #   in Loop: Header=BB3_2 Depth=1
	incq	%r12
	addq	%r13, %rbx
	addq	%r13, %r14
	cmpq	%r15, %r12
	jne	.LBB3_2
# %bb.7:
	addq	$8, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	.cfi_restore %rbx
	.cfi_restore %r12
	.cfi_restore %r13
	.cfi_restore %r14
	.cfi_restore %r15
	.cfi_restore %rbp
.LBB3_8:                                # %._crit_edge16
	movl	$.Lstr, %edi
	jmp	puts@PLT                        # TAILCALL
.Lfunc_end3:
	.size	_Z14correct_outputPA200_fS0_i, .Lfunc_end3-_Z14correct_outputPA200_fS0_i
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$160000, %edi                   # imm = 0x27100
	callq	malloc
	movq	%rax, %rbx
	movl	$160000, %edi                   # imm = 0x27100
	callq	malloc
	movq	%rax, %rbp
	movl	$160000, %edi                   # imm = 0x27100
	callq	malloc
	movq	%rax, 64(%rsp)                  # 8-byte Spill
	movl	$160000, %edi                   # imm = 0x27100
	callq	malloc
	movq	%rax, 56(%rsp)                  # 8-byte Spill
	xorl	%r12d, %r12d
	xorl	%edi, %edi
	callq	time
	movl	%eax, %edi
	callq	srand
	movl	$800, %r13d                     # imm = 0x320
	movq	%rbp, 72(%rsp)                  # 8-byte Spill
	movq	%rbx, %r15
.LBB4_1:                                # %.preheader63
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB4_2 Depth 2
	xorl	%r14d, %r14d
.LBB4_2:                                #   Parent Loop BB4_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	callq	rand
	cltq
	imulq	$780903145, %rax, %rcx          # imm = 0x2E8BA2E9
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$33, %rcx
	addl	%edx, %ecx
	leal	(%rcx,%rcx,4), %edx
	leal	(%rcx,%rdx,2), %ecx
	subl	%ecx, %eax
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	movss	%xmm0, (%rbx,%r14,4)
	callq	rand
	cltq
	imulq	$780903145, %rax, %rcx          # imm = 0x2E8BA2E9
	movq	%rcx, %rdx
	shrq	$63, %rdx
	sarq	$33, %rcx
	addl	%edx, %ecx
	leal	(%rcx,%rcx,4), %edx
	leal	(%rcx,%rdx,2), %ecx
	subl	%ecx, %eax
	xorps	%xmm0, %xmm0
	cvtsi2ss	%eax, %xmm0
	movss	%xmm0, (%rbp,%r14,4)
	incq	%r14
	cmpq	$200, %r14
	jne	.LBB4_2
# %bb.3:                                #   in Loop: Header=BB4_1 Depth=1
	incq	%r12
	addq	%r13, %rbx
	addq	%r13, %rbp
	cmpq	$200, %r12
	jne	.LBB4_1
# %bb.4:
	leaq	48(%rsp), %rbp
	movl	$160000, %esi                   # imm = 0x27100
	movq	%rbp, %rdi
	callq	hipMalloc
	leaq	40(%rsp), %r12
	movl	$160000, %esi                   # imm = 0x27100
	movq	%r12, %rdi
	callq	hipMalloc
	leaq	24(%rsp), %r13
	movl	$160000, %esi                   # imm = 0x27100
	movq	%r13, %rdi
	callq	hipMalloc
	movq	(%rbp), %rdi
	movl	$160000, %edx                   # imm = 0x27100
	movq	%r15, %r14
	movq	%r15, %rsi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	hipMemcpyAsync
	movq	(%r12), %rdi
	movl	$160000, %edx                   # imm = 0x27100
	movq	72(%rsp), %r15                  # 8-byte Reload
	movq	%r15, %rsi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	hipMemcpyAsync
	movq	(%r13), %rdi
	movl	$160000, %edx                   # imm = 0x27100
	movq	64(%rsp), %r13                  # 8-byte Reload
	movq	%r13, %rsi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	callq	hipMemcpyAsync
	leaq	88(%rsp), %r12
	movq	%r12, %rdi
	callq	hipEventCreate
	leaq	16(%rsp), %rdi
	callq	hipEventCreate
	callq	hipDeviceSynchronize
	movl	$0, 36(%rsp)
	movq	(%r12), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movabsq	$55834574861, %rdi              # imm = 0xD0000000D
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_6
# %bb.5:
	movq	48(%rsp), %rdi
	movq	40(%rsp), %rsi
	movq	24(%rsp), %rdx
	movl	$200, %ecx
	callq	_Z30__device_stub__MatrixAddKernelPfS_S_i
.LBB4_6:
	movq	16(%rsp), %rdi
	xorl	%ebx, %ebx
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	24(%rsp), %rsi
	movl	$160000, %edx                   # imm = 0x27100
	movq	%r13, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	leaq	80(%rsp), %r12
	movq	%r12, %rdi
	callq	hipEventCreate
	leaq	8(%rsp), %rdi
	callq	hipEventCreate
	movq	(%r12), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movl	$800, %eax                      # imm = 0x320
	movq	56(%rsp), %rbp                  # 8-byte Reload
	movq	%rbp, %rcx
	movq	%r15, %rdx
	movq	%r14, %rsi
.LBB4_7:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB4_8 Depth 2
	xorl	%edi, %edi
.LBB4_8:                                #   Parent Loop BB4_7 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movss	(%rsi,%rdi,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	addss	(%rdx,%rdi,4), %xmm0
	movss	%xmm0, (%rcx,%rdi,4)
	incq	%rdi
	cmpq	$200, %rdi
	jne	.LBB4_8
# %bb.9:                                #   in Loop: Header=BB4_7 Depth=1
	incq	%rbx
	addq	%rax, %rsi
	addq	%rax, %rdx
	addq	%rax, %rcx
	cmpq	$200, %rbx
	jne	.LBB4_7
# %bb.10:
	movq	8(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	8(%rsp), %rdi
	callq	hipEventSynchronize
	leaq	100(%rsp), %r12
	movl	$0, (%r12)
	movq	80(%rsp), %rsi
	movq	8(%rsp), %rdx
	movq	%r12, %rdi
	callq	hipEventElapsedTime
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r12), %xmm0
	movl	$.L.str.2, %edi
	movb	$1, %al
	callq	printf
.LBB4_11:                               # =>This Inner Loop Header: Depth=1
	movq	16(%rsp), %rdi
	callq	hipEventQuery
	cmpl	$600, %eax                      # imm = 0x258
	je	.LBB4_11
# %bb.12:
	movq	88(%rsp), %rsi
	movq	16(%rsp), %rdx
	leaq	36(%rsp), %r12
	movq	%r12, %rdi
	callq	hipEventElapsedTime
	xorps	%xmm0, %xmm0
	cvtss2sd	(%r12), %xmm0
	movl	$.L.str.3, %edi
	movb	$1, %al
	callq	printf
	movq	%rbp, %rdi
	movq	%r13, %rsi
	movl	$200, %edx
	callq	_Z14correct_outputPA200_fS0_i
	movq	%r14, %rdi
	callq	hipHostFree
	movq	%r15, %rdi
	callq	hipHostFree
	movq	%r13, %rdi
	callq	hipHostFree
	movq	48(%rsp), %rdi
	callq	hipFree
	movq	40(%rsp), %rdi
	callq	hipFree
	movq	24(%rsp), %rdi
	callq	hipFree
	callq	hipDeviceReset
	xorl	%eax, %eax
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	main, .Lfunc_end4-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z15MatrixAddKernelPfS_S_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12MatrixAddRowPfS_S_i, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z12MatrixAddColPfS_S_i, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z15MatrixAddKernelPfS_S_i,@object # @_Z15MatrixAddKernelPfS_S_i
	.section	.rodata,"a",@progbits
	.globl	_Z15MatrixAddKernelPfS_S_i
	.p2align	3, 0x0
_Z15MatrixAddKernelPfS_S_i:
	.quad	_Z30__device_stub__MatrixAddKernelPfS_S_i
	.size	_Z15MatrixAddKernelPfS_S_i, 8

	.type	_Z12MatrixAddRowPfS_S_i,@object # @_Z12MatrixAddRowPfS_S_i
	.globl	_Z12MatrixAddRowPfS_S_i
	.p2align	3, 0x0
_Z12MatrixAddRowPfS_S_i:
	.quad	_Z27__device_stub__MatrixAddRowPfS_S_i
	.size	_Z12MatrixAddRowPfS_S_i, 8

	.type	_Z12MatrixAddColPfS_S_i,@object # @_Z12MatrixAddColPfS_S_i
	.globl	_Z12MatrixAddColPfS_S_i
	.p2align	3, 0x0
_Z12MatrixAddColPfS_S_i:
	.quad	_Z27__device_stub__MatrixAddColPfS_S_i
	.size	_Z12MatrixAddColPfS_S_i, 8

	.type	.L.str.2,@object                # @.str.2
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.2:
	.asciz	"Time spent executing bv the CPU: %.2f\n"
	.size	.L.str.2, 39

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Time spent executing bv the GPU: %.2f\n"
	.size	.L.str.3, 39

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z15MatrixAddKernelPfS_S_i"
	.size	.L__unnamed_1, 27

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z12MatrixAddRowPfS_S_i"
	.size	.L__unnamed_2, 24

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z12MatrixAddColPfS_S_i"
	.size	.L__unnamed_3, 24

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"TEST PASSED"
	.size	.Lstr, 12

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"TEST FAILED"
	.size	.Lstr.1, 12

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z30__device_stub__MatrixAddKernelPfS_S_i
	.addrsig_sym _Z27__device_stub__MatrixAddRowPfS_S_i
	.addrsig_sym _Z27__device_stub__MatrixAddColPfS_S_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z15MatrixAddKernelPfS_S_i
	.addrsig_sym _Z12MatrixAddRowPfS_S_i
	.addrsig_sym _Z12MatrixAddColPfS_S_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z15MatrixAddKernelPfS_S_i ; -- Begin function _Z15MatrixAddKernelPfS_S_i
	.globl	_Z15MatrixAddKernelPfS_S_i
	.p2align	8
	.type	_Z15MatrixAddKernelPfS_S_i,@function
_Z15MatrixAddKernelPfS_S_i:             ; @_Z15MatrixAddKernelPfS_S_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x2c
	s_load_b32 s2, s[0:1], 0x18
	v_bfe_u32 v2, v0, 10, 10
	v_and_b32_e32 v3, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s4, s3, 16
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, s15, s4, v[2:3]
	v_mad_u64_u32 v[1:2], null, s14, s3, v[3:4]
	s_mov_b32 s3, exec_lo
	v_max_i32_e32 v2, v0, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s2, v2
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x0
	v_mad_u64_u32 v[2:3], null, v0, s2, v[1:2]
	s_load_b64 s[0:1], s[0:1], 0x10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[4:5], off
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, v2, v3
	global_store_b32 v[0:1], v2, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z15MatrixAddKernelPfS_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z15MatrixAddKernelPfS_S_i, .Lfunc_end0-_Z15MatrixAddKernelPfS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 224
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z12MatrixAddRowPfS_S_i ; -- Begin function _Z12MatrixAddRowPfS_S_i
	.globl	_Z12MatrixAddRowPfS_S_i
	.p2align	8
	.type	_Z12MatrixAddRowPfS_S_i,@function
_Z12MatrixAddRowPfS_S_i:                ; @_Z12MatrixAddRowPfS_S_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x2c
	s_load_b32 s2, s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
	s_mov_b32 s3, exec_lo
	v_max_i32_e32 v0, 0, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s2, v0
	s_cbranch_execz .LBB1_3
; %bb.1:                                ; %.lr.ph
	s_load_b128 s[4:7], s[0:1], 0x0
	v_mul_lo_u32 v0, v1, s2
	s_load_b64 s[0:1], s[0:1], 0x10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[4:5], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s4, v4
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v5, vcc_lo
	v_add_co_u32 v2, vcc_lo, s6, v4
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v5, vcc_lo
	v_add_co_u32 v4, vcc_lo, s0, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
.LBB1_2:                                ; =>This Inner Loop Header: Depth=1
	global_load_b32 v6, v[0:1], off
	global_load_b32 v7, v[2:3], off
	v_add_co_u32 v0, vcc_lo, v0, 4
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
	v_add_co_u32 v2, vcc_lo, v2, 4
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	s_add_i32 s2, s2, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s2, 0
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v6, v6, v7
	global_store_b32 v[4:5], v6, off
	v_add_co_u32 v4, vcc_lo, v4, 4
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v5, vcc_lo
	s_cbranch_scc1 .LBB1_2
.LBB1_3:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12MatrixAddRowPfS_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z12MatrixAddRowPfS_S_i, .Lfunc_end1-_Z12MatrixAddRowPfS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 248
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z12MatrixAddColPfS_S_i ; -- Begin function _Z12MatrixAddColPfS_S_i
	.globl	_Z12MatrixAddColPfS_S_i
	.p2align	8
	.type	_Z12MatrixAddColPfS_S_i,@function
_Z12MatrixAddColPfS_S_i:                ; @_Z12MatrixAddColPfS_S_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x2c
	s_load_b32 s2, s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_and_b32 s3, s3, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s3, v[0:1]
	s_mov_b32 s3, exec_lo
	v_max_i32_e32 v0, 0, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s2, v0
	s_cbranch_execz .LBB2_3
; %bb.1:                                ; %.lr.ph.preheader
	s_clause 0x1
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[0:1], s[0:1], 0x10
	s_mov_b32 s3, s2
.LBB2_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v2, 31, v1
	s_add_i32 s3, s3, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s3, 0
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_add_nc_u32_e32 v1, s2, v1
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	v_add_co_u32 v6, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
	global_load_b32 v0, v[4:5], off
	global_load_b32 v4, v[6:7], off
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v0, v0, v4
	global_store_b32 v[2:3], v0, off
	s_cbranch_scc1 .LBB2_2
.LBB2_3:                                ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z12MatrixAddColPfS_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z12MatrixAddColPfS_S_i, .Lfunc_end2-_Z12MatrixAddColPfS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 212
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z15MatrixAddKernelPfS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z15MatrixAddKernelPfS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12MatrixAddRowPfS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z12MatrixAddRowPfS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z12MatrixAddColPfS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z12MatrixAddColPfS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
