#include <stdio.h>
#include <cuda.h>

#define Width 1920
#define Height 2520
#define iterations 100


__global__ void convolution_kernel(unsigned char* in_device_buffer,unsigned char* out_device_buffer);
void swap_images(unsigned char **in_image,unsigned char **out_image);


int main (){
	
	unsigned char *in_image ;
	unsigned char *in_device_buffer;
	unsigned char *out_image ;
	unsigned char *out_device_buffer ;
	int grid, i;
	grid = Width* Height;
	in_image =(unsigned char*)malloc(grid);
	out_image =(unsigned char*)malloc(grid);
	
	
	FILE *fp;
	fp = fopen("images/grey_X1.raw","rb");
	if (fp == NULL){
		printf("Empty file ... Exiting");
		exit(1);
	}else {
		fread(in_image,grid,1,fp);
		fclose(fp);
	}
	 
	
	cudaEvent_t start, stop;
	cudaEventCreate(&start);
	cudaEventCreate(&stop);
	
	dim3 threadNum(32,32);
	dim3 blockNum(Width/((threadNum.x)-2),Height/((threadNum.y)-2));
	
	
	
	
	
	
	cudaMalloc(&in_device_buffer,grid);
	cudaMalloc(&out_device_buffer,grid);
	cudaMemcpy(in_device_buffer,in_image,grid,cudaMemcpyHostToDevice);
	
	cudaEventRecord(start, 0);
	for (i = 0 ; i < iterations; i++){
		convolution_kernel <<<blockNum,threadNum>>> (in_device_buffer, out_device_buffer);
		swap_images(&in_device_buffer,&out_device_buffer);	
	}
	cudaEventRecord(stop, 0);


	cudaMemcpy(out_image, out_device_buffer, grid, cudaMemcpyDeviceToHost);
	cudaFree(out_device_buffer);
	cudaFree(in_device_buffer);
	
	
	cudaEventSynchronize(stop);
	
	fp = fopen("out.raw","w+");
	fwrite(out_image,grid,1,fp);
	fclose(fp);
	
return 0;

}


void swap_images(unsigned char **in_image,unsigned char **out_image)
{
	unsigned char* temp = *in_image;
	*in_image = *out_image;
	*out_image = temp;
}

__global__ void convolution_kernel(unsigned char* A, unsigned char* B)
{
	int i = blockIdx.x * blockDim.x + threadIdx.x;
	int j = blockIdx.y * blockDim.y + threadIdx.y;
	
	int x = i-2*blockIdx.x-1;
	int y = j-2*blockIdx.y-1;
	
	__shared__ unsigned char As[32][32];
	
	//Copy from global memory to shared memory	
		
		if (x<0) {
			x=0;
		} else if (x==Width) {
			x=Width-1;
		}
		if (y<0) {
			y=0;
		} else if (y == Height) {
			y = Height-1;
		}
		As[threadIdx.x][threadIdx.y] = A[Width*y + x];
		
		__syncthreads();
	
	// Computations
	
		if (threadIdx.x!=0 && threadIdx.x!=31 && threadIdx.y!=0 && threadIdx.y!=31) {
			B[Width*y + x] =     (As[threadIdx.x-1][threadIdx.y-1]  +
										As[threadIdx.x  ][threadIdx.y-1] * 2 +
										As[threadIdx.x+1][threadIdx.y-1]  +
										As[threadIdx.x-1][threadIdx.y  ] *2 +
										As[threadIdx.x  ][threadIdx.y  ] *4 +
										As[threadIdx.x+1][threadIdx.y  ] * 2 +
										As[threadIdx.x-1][threadIdx.y+1] * 1 +
										As[threadIdx.x  ][threadIdx.y+1] * 2 +
										As[threadIdx.x+1][threadIdx.y+1] * 1)/16;
		}
}

	.file	"tmpxft_002aa7ff_00000000-6_cuda_convergence.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z11swap_imagesPPhS0_
	.type	_Z11swap_imagesPPhS0_, @function
_Z11swap_imagesPPhS0_:
.LFB2028:
	.cfi_startproc
	endbr64
	movq	(%rdi), %rax
	movq	(%rsi), %rdx
	movq	%rdx, (%rdi)
	movq	%rax, (%rsi)
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z11swap_imagesPPhS0_, .-_Z11swap_imagesPPhS0_
	.globl	_Z40__device_stub__Z18convolution_kernelPhS_PhS_
	.type	_Z40__device_stub__Z18convolution_kernelPhS_PhS_, @function
_Z40__device_stub__Z18convolution_kernelPhS_PhS_:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L3
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z18convolution_kernelPhS_(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L3:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L5
	call	__stack_chk_fail@PLT
.L5:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z40__device_stub__Z18convolution_kernelPhS_PhS_, .-_Z40__device_stub__Z18convolution_kernelPhS_PhS_
	.globl	_Z18convolution_kernelPhS_
	.type	_Z18convolution_kernelPhS_, @function
_Z18convolution_kernelPhS_:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z40__device_stub__Z18convolution_kernelPhS_PhS_
	.cfi_endproc
.LFE2054:
	.size	_Z18convolution_kernelPhS_, .-_Z18convolution_kernelPhS_
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"rb"
.LC1:
	.string	"images/grey_X1.raw"
.LC2:
	.string	"Empty file ... Exiting"
.LC3:
	.string	"w+"
.LC4:
	.string	"out.raw"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$4838400, %edi
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$64, %rsp
	.cfi_def_cfa_offset 96
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$4838400, %edi
	movq	%rax, %r12
	call	malloc@PLT
	leaq	.LC0(%rip), %rsi
	leaq	.LC1(%rip), %rdi
	movq	%rax, %rbp
	call	fopen@PLT
	testq	%rax, %rax
	jne	.L10
	movl	$2, %edi
	leaq	.LC2(%rip), %rsi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$1, %edi
	call	exit@PLT
.L10:
	movq	%rax, %r8
	movl	$1, %ecx
	movl	$4838400, %edx
	movq	%rax, %rbx
	movl	$4838400, %esi
	movq	%r12, %rdi
	call	__fread_chk@PLT
	movq	%rbx, %rdi
	movl	$100, %ebx
	call	fclose@PLT
	leaq	16(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	24(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	%rsp, %rdi
	movabsq	$360777252928, %rax
	movl	$4838400, %esi
	movl	$1, 40(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	cudaMalloc@PLT
	leaq	8(%rsp), %rdi
	movl	$4838400, %esi
	call	cudaMalloc@PLT
	movq	(%rsp), %rdi
	movq	%r12, %rsi
	movl	$1, %ecx
	movabsq	$137438953504, %r12
	movl	$4838400, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
.L12:
	movl	40(%rsp), %ecx
	movq	44(%rsp), %rdi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	52(%rsp), %esi
	movq	%r12, %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L11
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdi
	call	_Z40__device_stub__Z18convolution_kernelPhS_PhS_
.L11:
	movq	(%rsp), %rax
	movq	8(%rsp), %rdx
	movq	%rax, 8(%rsp)
	movq	%rdx, (%rsp)
	decl	%ebx
	jne	.L12
	movq	24(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	8(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbp, %rdi
	movl	$4838400, %edx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	leaq	.LC3(%rip), %rsi
	leaq	.LC4(%rip), %rdi
	call	fopen@PLT
	movq	%rbp, %rdi
	movl	$1, %edx
	movl	$4838400, %esi
	movq	%rax, %rbx
	movq	%rax, %rcx
	call	fwrite@PLT
	movq	%rbx, %rdi
	call	fclose@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L13
	call	__stack_chk_fail@PLT
.L13:
	addq	$64, %rsp
	.cfi_def_cfa_offset 32
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC5:
	.string	"_Z18convolution_kernelPhS_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z18convolution_kernelPhS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2056:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <hip/hip_runtime.h>

#define Width 1920
#define Height 2520
#define iterations 100


__global__ void convolution_kernel(unsigned char* in_device_buffer,unsigned char* out_device_buffer);
void swap_images(unsigned char **in_image,unsigned char **out_image);


int main (){
	
	unsigned char *in_image ;
	unsigned char *in_device_buffer;
	unsigned char *out_image ;
	unsigned char *out_device_buffer ;
	int grid, i;
	grid = Width* Height;
	in_image =(unsigned char*)malloc(grid);
	out_image =(unsigned char*)malloc(grid);
	
	
	FILE *fp;
	fp = fopen("images/grey_X1.raw","rb");
	if (fp == NULL){
		printf("Empty file ... Exiting");
		exit(1);
	}else {
		fread(in_image,grid,1,fp);
		fclose(fp);
	}
	 
	
	hipEvent_t start, stop;
	hipEventCreate(&start);
	hipEventCreate(&stop);
	
	dim3 threadNum(32,32);
	dim3 blockNum(Width/((threadNum.x)-2),Height/((threadNum.y)-2));
	
	
	
	
	
	
	hipMalloc(&in_device_buffer,grid);
	hipMalloc(&out_device_buffer,grid);
	hipMemcpy(in_device_buffer,in_image,grid,hipMemcpyHostToDevice);
	
	hipEventRecord(start, 0);
	for (i = 0 ; i < iterations; i++){
		convolution_kernel <<<blockNum,threadNum>>> (in_device_buffer, out_device_buffer);
		swap_images(&in_device_buffer,&out_device_buffer);	
	}
	hipEventRecord(stop, 0);


	hipMemcpy(out_image, out_device_buffer, grid, hipMemcpyDeviceToHost);
	hipFree(out_device_buffer);
	hipFree(in_device_buffer);
	
	
	hipEventSynchronize(stop);
	
	fp = fopen("out.raw","w+");
	fwrite(out_image,grid,1,fp);
	fclose(fp);
	
return 0;

}


void swap_images(unsigned char **in_image,unsigned char **out_image)
{
	unsigned char* temp = *in_image;
	*in_image = *out_image;
	*out_image = temp;
}

__global__ void convolution_kernel(unsigned char* A, unsigned char* B)
{
	int i = blockIdx.x * blockDim.x + threadIdx.x;
	int j = blockIdx.y * blockDim.y + threadIdx.y;
	
	int x = i-2*blockIdx.x-1;
	int y = j-2*blockIdx.y-1;
	
	__shared__ unsigned char As[32][32];
	
	//Copy from global memory to shared memory	
		
		if (x<0) {
			x=0;
		} else if (x==Width) {
			x=Width-1;
		}
		if (y<0) {
			y=0;
		} else if (y == Height) {
			y = Height-1;
		}
		As[threadIdx.x][threadIdx.y] = A[Width*y + x];
		
		__syncthreads();
	
	// Computations
	
		if (threadIdx.x!=0 && threadIdx.x!=31 && threadIdx.y!=0 && threadIdx.y!=31) {
			B[Width*y + x] =     (As[threadIdx.x-1][threadIdx.y-1]  +
										As[threadIdx.x  ][threadIdx.y-1] * 2 +
										As[threadIdx.x+1][threadIdx.y-1]  +
										As[threadIdx.x-1][threadIdx.y  ] *2 +
										As[threadIdx.x  ][threadIdx.y  ] *4 +
										As[threadIdx.x+1][threadIdx.y  ] * 2 +
										As[threadIdx.x-1][threadIdx.y+1] * 1 +
										As[threadIdx.x  ][threadIdx.y+1] * 2 +
										As[threadIdx.x+1][threadIdx.y+1] * 1)/16;
		}
}

	.text
	.file	"cuda_convergence.hip"
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$32, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$4838400, %edi                  # imm = 0x49D400
	callq	malloc
	movq	%rax, %r14
	movl	$4838400, %edi                  # imm = 0x49D400
	callq	malloc
	movq	%rax, %rbx
	movl	$.L.str, %edi
	movl	$.L.str.1, %esi
	callq	fopen
	testq	%rax, %rax
	je	.LBB0_6
# %bb.1:
	movq	%rax, %r15
	movl	$4838400, %esi                  # imm = 0x49D400
	movl	$1, %edx
	movq	%r14, %rdi
	movq	%rax, %rcx
	callq	fread
	movq	%r15, %rdi
	callq	fclose
	leaq	24(%rsp), %r15
	movq	%r15, %rdi
	callq	hipEventCreate
	leaq	16(%rsp), %rdi
	callq	hipEventCreate
	leaq	8(%rsp), %r12
	movl	$4838400, %esi                  # imm = 0x49D400
	movq	%r12, %rdi
	callq	hipMalloc
	movq	%rsp, %rdi
	movl	$4838400, %esi                  # imm = 0x49D400
	callq	hipMalloc
	movq	(%r12), %rdi
	movl	$4838400, %edx                  # imm = 0x49D400
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r15), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movl	$100, %ebp
	movabsq	$360777252928, %r14             # imm = 0x5400000040
	movabsq	$137438953504, %r15             # imm = 0x2000000020
.LBB0_2:                                # =>This Inner Loop Header: Depth=1
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_4
# %bb.3:                                #   in Loop: Header=BB0_2 Depth=1
	movq	8(%rsp), %rdi
	movq	(%rsp), %rsi
	callq	_Z33__device_stub__convolution_kernelPhS_
.LBB0_4:                                #   in Loop: Header=BB0_2 Depth=1
	movq	8(%rsp), %rax
	movq	(%rsp), %rcx
	movq	%rcx, 8(%rsp)
	movq	%rax, (%rsp)
	decl	%ebp
	jne	.LBB0_2
# %bb.5:
	movq	16(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	(%rsp), %rsi
	movl	$4838400, %edx                  # imm = 0x49D400
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipEventSynchronize
	movl	$.L.str.3, %edi
	movl	$.L.str.4, %esi
	callq	fopen
	movq	%rax, %r14
	movl	$4838400, %esi                  # imm = 0x49D400
	movl	$1, %edx
	movq	%rbx, %rdi
	movq	%rax, %rcx
	callq	fwrite
	movq	%r14, %rdi
	callq	fclose
	xorl	%eax, %eax
	addq	$32, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB0_6:
	.cfi_def_cfa_offset 80
	movl	$.L.str.2, %edi
	xorl	%eax, %eax
	callq	printf
	movl	$1, %edi
	callq	exit
.Lfunc_end0:
	.size	main, .Lfunc_end0-main
	.cfi_endproc
                                        # -- End function
	.globl	_Z33__device_stub__convolution_kernelPhS_ # -- Begin function _Z33__device_stub__convolution_kernelPhS_
	.type	_Z33__device_stub__convolution_kernelPhS_,@function
_Z33__device_stub__convolution_kernelPhS_: # @_Z33__device_stub__convolution_kernelPhS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	16(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	8(%rsp), %r12
	movq	%rsp, %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18convolution_kernelPhS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z33__device_stub__convolution_kernelPhS_, .Lfunc_end1-_Z33__device_stub__convolution_kernelPhS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z11swap_imagesPPhS0_           # -- Begin function _Z11swap_imagesPPhS0_
	.type	_Z11swap_imagesPPhS0_,@function
_Z11swap_imagesPPhS0_:                  # @_Z11swap_imagesPPhS0_
	.cfi_startproc
# %bb.0:
	movq	(%rdi), %rax
	movq	(%rsi), %rcx
	movq	%rcx, (%rdi)
	movq	%rax, (%rsi)
	retq
.Lfunc_end2:
	.size	_Z11swap_imagesPPhS0_, .Lfunc_end2-_Z11swap_imagesPPhS0_
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18convolution_kernelPhS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"images/grey_X1.raw"
	.size	.L.str, 19

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"rb"
	.size	.L.str.1, 3

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Empty file ... Exiting"
	.size	.L.str.2, 23

	.type	_Z18convolution_kernelPhS_,@object # @_Z18convolution_kernelPhS_
	.section	.rodata,"a",@progbits
	.globl	_Z18convolution_kernelPhS_
	.p2align	3, 0x0
_Z18convolution_kernelPhS_:
	.quad	_Z33__device_stub__convolution_kernelPhS_
	.size	_Z18convolution_kernelPhS_, 8

	.type	.L.str.3,@object                # @.str.3
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.3:
	.asciz	"out.raw"
	.size	.L.str.3, 8

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"w+"
	.size	.L.str.4, 3

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z18convolution_kernelPhS_"
	.size	.L__unnamed_1, 27

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z33__device_stub__convolution_kernelPhS_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z18convolution_kernelPhS_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z18convolution_kernelPhS_ ; -- Begin function _Z18convolution_kernelPhS_
	.globl	_Z18convolution_kernelPhS_
	.p2align	8
	.type	_Z18convolution_kernelPhS_,@function
_Z18convolution_kernelPhS_:             ; @_Z18convolution_kernelPhS_
; %bb.0:
	s_load_b32 s2, s[0:1], 0x1c
	v_bfe_u32 v2, v0, 10, 10
	s_lshl_b32 s3, s15, 1
	v_and_b32_e32 v3, 0x3ff, v0
	s_lshl_b32 s4, s14, 1
	s_not_b32 s3, s3
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s5, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_mul_i32 s15, s15, s5
	s_mul_i32 s14, s14, s2
	v_add3_u32 v0, s15, s3, v2
	s_not_b32 s3, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add3_u32 v1, s14, s3, v3
	s_load_b128 s[0:3], s[0:1], 0x0
	v_mul_lo_u32 v4, 0x780, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cmp_ne_u32_e32 vcc_lo, 0x780, v1
	v_cndmask_b32_e32 v5, 0x77f, v1, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0x9d8, v0
	v_cndmask_b32_e32 v4, 0x49cc80, v4, vcc_lo
	v_cmp_lt_i32_e32 vcc_lo, -1, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v1, 0, v5, vcc_lo
	v_cmp_lt_i32_e32 vcc_lo, -1, v0
	v_cndmask_b32_e32 v0, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v0, v1
	v_ashrrev_i32_e32 v1, 31, v0
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s0, v0
	s_mov_b32 s0, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
	s_mov_b32 s1, exec_lo
	global_load_u8 v5, v[4:5], off
	v_lshl_add_u32 v4, v3, 5, v2
	s_waitcnt vmcnt(0)
	ds_store_b8 v4, v5
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_cmpx_lt_i32_e32 30, v3
	s_xor_b32 s1, exec_lo, s1
; %bb.1:                                ; %LeafBlock38
	v_cmp_ne_u32_e32 vcc_lo, 31, v3
	s_and_b32 s0, vcc_lo, exec_lo
; %bb.2:                                ; %Flow48
	s_and_not1_saveexec_b32 s1, s1
; %bb.3:                                ; %LeafBlock
	v_cmp_ne_u32_e32 vcc_lo, 0, v3
	s_and_not1_b32 s0, s0, exec_lo
	s_and_b32 s4, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s0, s0, s4
; %bb.4:                                ; %Flow49
	s_or_b32 exec_lo, exec_lo, s1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_11
; %bb.5:                                ; %NodeBlock44
	s_mov_b32 s0, 0
	s_mov_b32 s1, exec_lo
	v_cmpx_lt_i32_e32 30, v2
	s_xor_b32 s1, exec_lo, s1
; %bb.6:                                ; %LeafBlock42
	v_cmp_ne_u32_e32 vcc_lo, 31, v2
	s_and_b32 s0, vcc_lo, exec_lo
; %bb.7:                                ; %Flow
	s_and_not1_saveexec_b32 s1, s1
; %bb.8:                                ; %LeafBlock40
	v_cmp_ne_u32_e32 vcc_lo, 0, v2
	s_and_not1_b32 s0, s0, exec_lo
	s_and_b32 s4, vcc_lo, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s0, s0, s4
; %bb.9:                                ; %Flow46
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_11
; %bb.10:
	v_lshlrev_b32_e32 v3, 5, v3
	v_subrev_nc_u32_e32 v5, 32, v4
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add3_u32 v2, v3, v2, 0xffffffdf
	v_add_nc_u32_e32 v3, -1, v4
	ds_load_u8 v6, v4
	ds_load_u8 v2, v2
	ds_load_u8 v3, v3
	ds_load_u8 v7, v5
	ds_load_u8 v8, v4 offset:31
	ds_load_u8 v9, v4 offset:32
	ds_load_u8 v10, v4 offset:1
	ds_load_u8 v5, v5 offset:1
	ds_load_u8 v4, v4 offset:33
	s_waitcnt lgkmcnt(8)
	v_lshlrev_b16 v6, 2, v6
	s_waitcnt lgkmcnt(5)
	v_add_nc_u16 v3, v7, v3
	s_waitcnt lgkmcnt(4)
	v_add_nc_u16 v2, v8, v2
	s_waitcnt lgkmcnt(3)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u16 v3, v3, v9
	v_add_nc_u16 v2, v2, v6
	s_waitcnt lgkmcnt(2)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u16 v3, v3, v10
	s_waitcnt lgkmcnt(1)
	v_add_nc_u16 v2, v2, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b16 v3, 1, v3
	s_waitcnt lgkmcnt(0)
	v_add_nc_u16 v2, v2, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u16 v2, v2, v3
	v_lshrrev_b16 v2, 4, v2
	global_store_b8 v[0:1], v2, off
.LBB0_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18convolution_kernelPhS_
		.amdhsa_group_segment_fixed_size 1024
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z18convolution_kernelPhS_, .Lfunc_end0-_Z18convolution_kernelPhS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 624
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 1024 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 1024
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18convolution_kernelPhS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z18convolution_kernelPhS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     11
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
