#import <cuda_runtime.h>
#include <cuda_runtime_api.h>
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
#include <math.h>

void error(char const *str)
{
	fprintf(stderr, "%s\n", str);
	exit(1);
}

void cuda_check(cudaError_t err, char const *str)
{
	if (err != cudaSuccess) {
		fprintf(stderr, "%s: CUDA error %d (%s)\n",
			str, err, cudaGetErrorString(err));
	}
}

__host__ __device__
float4 operator+(const float4 &a, const float4 &b)
{
	return make_float4(a.x + b.x, a.y + b.y, a.z + b.z, a.w + b.w);
}


__global__
void init_vec(int nels, float* __restrict__ d_vec1)
{
	int i = threadIdx.x + blockIdx.x * blockDim.x;
	d_vec1[i] = i;
}


__global__
void multi_vec2(int nels,int n_row1,int n_col1,int n_row2,int n_col2,float* __restrict__ res_vec,float* __restrict__ d_vec1,float* __restrict__ d_vec2)
{
	int i = threadIdx.x + blockIdx.x * blockDim.x;
	int r_res,c_res;
	r_res=n_row1;
	c_res=n_row2*n_col2;
	if(i<(r_res*c_res)){
	//int c= blockIdx.x*n_row1 + (threadIdx.x)%n_col1;


	int c= ((int)(i/c_res))*n_row1 + ((int)(i%n_col1))%n_col1;

	int j= ((int)(((int)(i%c_res))/n_row2) + (((int)(i%c_res))%n_row2)*n_col2);

	printf("%f %f\n",d_vec1[c],d_vec2[j] );
	res_vec[i]=d_vec1[c]*d_vec2[j];
	}
}


__global__
void multi_vec(int nels,int n_row1,int n_col1,int n_row2,int n_col2,float* __restrict__ res_vec,
								float* __restrict__ d_vec1,float* __restrict__ d_vec2)
{
	int i = threadIdx.x + blockIdx.x * blockDim.x;
	int r_res,c_res;
	r_res=n_row1;
	c_res=n_row2*n_col2;
	if(i<(r_res*c_res)){
		int c= ((int)(i/c_res))*n_row1 + ((int)(i%n_col1))%n_col1;
		int j= ((int)(((int)(i%c_res))/n_row2) + (((int)(i%c_res))%n_row2)*n_col2);
		res_vec[i]=d_vec1[c]*d_vec2[j];
	}
}

__global__
void scalareMatrice(float* __restrict__ res_vec,float scalar,float* __restrict__ d_vec)
{
	int i = threadIdx.x + blockIdx.x * blockDim.x;
	res_vec[i]=d_vec[i]*scalar;
}


__global__
void reduction_row(int nels,int l_elem,float* res_vec, float*  d_vec1)
{
	int idx = threadIdx.x + blockIdx.x * blockDim.x;
	const float4 noels = make_float4(0.0, 0.0, 0.0, 0.0);
	const int nquarts = nels*4;
	const int elem=nels/l_elem;
	int i=idx*l_elem;
	int i0 = i;
	int i1 = i +   4;
	int i2 = i + 2*4;
	int i3 = i + 3*4;
		 __syncthreads();
	float4 r0;
	if(l_elem >= 4){
		r0.x=d_vec1[i];
		r0.y=d_vec1[i+1];
		r0.z=d_vec1[i+2];
		r0.w=d_vec1[i+3];
	}
	else r0= noels;
	float4 r1;
	if(l_elem >= 8){
		r1.x=d_vec1[i1];
		r1.y=d_vec1[i1+1];
		r1.z=d_vec1[i1+2];
		r1.w=d_vec1[i1+3];
	}
	else r1= noels;

	float4 r2;
	if(l_elem >= 12){
		r2.x=d_vec1[i2];
		r2.y=d_vec1[i2+1];
		r2.z=d_vec1[i2+2];
		r2.w=d_vec1[i2+3];
	}
	else r2= noels;
	float4 r3;
	if(l_elem >= 16){
		r3.x=d_vec1[i3];
		r3.y=d_vec1[i3+1];
		r3.z=d_vec1[i3+2];
		r3.w=d_vec1[i3+3];
	}
	else r3= noels;

	float4 v = (r0 + r1) + (r2 + r3);

	if (idx < nels)
		res_vec[idx] = (v.x + v.y) + (v.z + v.w);

}

__global__
void transpose(int nrow,int ncols, float* __restrict__ res_vec, float* __restrict__ d_vec1)
{
	int i = threadIdx.x + blockIdx.x * blockDim.x;
	int c =i%ncols;
	int r=i/ncols;
	int l_in = r*ncols + c;
	int l_out = c * nrow + r;
	res_vec[l_out] = d_vec1[l_in];
}


__global__
void vecsum(int nels, float* __restrict__ res_vec, float* __restrict__ d_vec1, float* __restrict__ d_vec2)
{
	int i = threadIdx.x + blockIdx.x * blockDim.x;
	res_vec[i] = d_vec1[i]+d_vec2[i];
}

__global__
void vecdif(int nels, float* __restrict__ res_vec, float* __restrict__ d_vec1, float* __restrict__ d_vec2)
{
	int i = threadIdx.x + blockIdx.x * blockDim.x;
	res_vec[i] = d_vec1[i]-d_vec2[i];
}
void stampa(float* matrice,int m){
  int i,j;
	printf("\n");
  for(i=0;i<m;i++){
      printf("%f  ",matrice[i]);
			printf("\n");
	}

}

int main(int argc, char *argv[]){
  float* matriceA;
  float* matriceB;
  float* matriceX;
	float* pk;
	float* trasposta;
	float* prodotto;
	float* somma;
	float* res;
	float* den;
	float* res0;
	float* res1;
	float* res2;
	float* red_den;
  float* matrice;
	float* scalar;
	float* num;
	float* deno;
  float ak;
  int nels;
  if (argc != 2) {
    error("syntax: vecsum nels v");
  }

  int N = atoi(argv[1]);
  if (N < 0) {
    error("N < 0");
  }
	int M=1;

  nels=N*N;
  size_t memsize = nels*sizeof(float);
  cudaError_t err;
  err = cudaMalloc((void**)&matriceA, memsize);
  cuda_check(err, "alloc matriceA");
  err = cudaMalloc((void**)&matriceB, N*M*sizeof(float));
  cuda_check(err, "alloc matriceB");
  err = cudaMalloc((void**)&matriceX, N*sizeof(float));
  cuda_check(err, "alloc matriceX");
  err = cudaMallocHost(&matrice, N*N*sizeof(float));
	cuda_check(err, "alloc matrice");
	err = cudaMallocHost(&num, M*sizeof(float));
	cuda_check(err, "alloc matrice");
	err = cudaMallocHost(&deno, M*sizeof(float));
	cuda_check(err, "alloc matrice");
	err = cudaMalloc((void**)&somma,nels*M*sizeof(float));
	cuda_check(err, "alloc somma");
	err = cudaMalloc((void**)&res,M*N*N*sizeof(float));
	cuda_check(err, "alloc res");
	err = cudaMalloc((void**)&res0,N*M*N*sizeof(float));
	cuda_check(err, "alloc res0");
	err = cudaMalloc((void**)&prodotto,M*N*N*sizeof(float));
	cuda_check(err, "alloc prodotto");
	err = cudaMalloc((void**)&res1,M*N*sizeof(float));
	cuda_check(err, "alloc res1");
	err = cudaMalloc((void**)&res2,M*N*N*sizeof(float));
	cuda_check(err, "alloc res2");
	err = cudaMalloc((void**)&pk,M*N*sizeof(float));
	cuda_check(err, "alloc pk");
	err = cudaMalloc((void**)&trasposta,M*N*sizeof(float));
	cuda_check(err, "alloc trasposta	");
	err = cudaMalloc((void**)&den,M*N*sizeof(float));
	cuda_check(err, "alloc den");
	err = cudaMalloc((void**)&red_den,M*N*sizeof(float));
	cuda_check(err, "alloc den");
	err = cudaMalloc((void**)&scalar,M*N*sizeof(float));
	cuda_check(err, "alloc scalar");

	cudaEvent_t pre_init, post_init, pre_sum, post_sum,pre_prodotto,post_prodotto,
							pre_transpose,post_transpose,pre_scalar_matrice,post_scalar_matrice,pre_vecsum,post_vecsum,
							pre_vecdif,post_vecdif;


	err = cudaEventCreate(&pre_init, 0);
	cuda_check(err, "create pre_init");
	err = cudaEventCreate(&pre_prodotto, 0);
	cuda_check(err, "create pre_sum");
	err = cudaEventCreate(&pre_transpose, 0);
	cuda_check(err, "create pre_traspose");
	err = cudaEventCreate(&pre_scalar_matrice, 0);
	cuda_check(err, "create pre_scalar_matrice");
	err = cudaEventCreate(&pre_vecdif, 0);
	cuda_check(err, "create pre_vecdif");
	err = cudaEventCreate(&pre_vecsum, 0);
	cuda_check(err, "create pre_vecsum");

	err = cudaEventCreate(&post_init, 0);
	cuda_check(err, "create post_init");
	err = cudaEventCreate(&post_prodotto, 0);
	cuda_check(err, "create post_sum");
	err = cudaEventCreate(&post_transpose, 0);
	cuda_check(err, "create post_traspose");
	err = cudaEventCreate(&post_scalar_matrice, 0);
	cuda_check(err, "create post_scalar_matrice");
	err = cudaEventCreate(&post_vecdif, 0);
	cuda_check(err, "create post_vecdif");
	err = cudaEventCreate(&post_vecsum, 0);
	cuda_check(err, "create post_vecsum");
  const int blockSize = 512;
	int numBlocks = (nels + blockSize - 1)/blockSize;


	cudaEventRecord(pre_init);
	init_vec<<<blockSize,numBlocks>>>(nels, matriceA);
	cudaEventRecord(post_init);

	numBlocks = (M*N + blockSize - 1)/blockSize;
  init_vec<<<blockSize, numBlocks>>>(M*N, matriceB);

	init_vec<<<blockSize, numBlocks>>>(M*N, matriceX);
	int i;

	//calcolo i parametri della riduzione
	int THREAD_LOAD=0;
	float n = N;
	while (n > 1) {
		n/=4;
		if(n==1){
			THREAD_LOAD=4;
		}
	}
	n = N;
	while (n > 1) {

		n/=8;
		if(n==1){
			THREAD_LOAD=8;
		}
	}
	n=N;
	while (n > 1) {
		n/=12;
		if(n==1){
			THREAD_LOAD=12;
		}
	}
	while (n > 1) {
		n/=16;
		if(n==1){
			THREAD_LOAD=16;
		}
	}
	if(THREAD_LOAD==0){
		printf("Errore N deve essere una potenza di 4,8,12,16");
		exit(0);
	}
	int j;
	int c=N;
	float* temp;
	float runtime_red_ms;
	int lr=0;
	int log=N*N;
	while(log>N){
		++lr;
		log=log/THREAD_LOAD;
	}

	cudaEvent_t pre_red[lr], post_red[lr];
	//inizializzo gli eventi per la riduzione
	for(i=0;i<lr;i++){
		err = cudaEventCreate(&(pre_red[i]), 0);
		cuda_check(err, "create pre_red");

		err = cudaEventCreate(&(post_red[i]), 0);
		cuda_check(err, "create post_red");
	}
	for(i=0;i<1;i++){
		numBlocks = (nels + blockSize - 1)/blockSize;
		cudaEventRecord(pre_prodotto);
		multi_vec<<<blockSize, numBlocks>>>(nels*M,N,N,N,M,somma,matriceA,matriceX);
		cudaEventRecord(post_prodotto);

		c=N*N;

		int nels_red=0;
		int cont=0;
		while(c>N){
			c/=THREAD_LOAD;
			nels_red+=c;

			numBlocks = (c + blockSize - 1)/blockSize;
			cudaEventRecord(pre_red[cont]);
			reduction_row<<<blockSize, numBlocks>>>(c,THREAD_LOAD,res0,somma);
			cudaEventRecord(post_red[cont]);
			err = cudaMemcpy(somma, res0, c*sizeof(float), cudaMemcpyDeviceToDevice);
			cuda_check(err, "cpy");
			cont++;
		}

		printf("%d %d\n",lr,nels_red );
		numBlocks = (N*M + blockSize - 1)/blockSize;
		cudaEventRecord(pre_vecdif);
		vecdif<<<blockSize, numBlocks>>>(N*M,pk,matriceB,res0);
		cudaEventRecord(post_vecdif);

		numBlocks = (N*N + blockSize - 1)/blockSize;
		cudaEventRecord(pre_transpose);
		transpose<<<blockSize, numBlocks>>>(N,M,trasposta,pk);
		cudaEventRecord(post_transpose);
		numBlocks = (M*N + blockSize - 1)/blockSize;
		multi_vec<<<blockSize, numBlocks>>>(N*M,M,N,N,M,prodotto,trasposta,pk);
		c=N;
		while (c>1) {
			c/=THREAD_LOAD;
			numBlocks = (c + blockSize - 1)/blockSize;
			reduction_row<<<blockSize, numBlocks>>>(c,THREAD_LOAD,res1,prodotto);
			err = cudaMemcpy(prodotto, res1, c*sizeof(float), cudaMemcpyDeviceToDevice);
			cuda_check(err, "cpy");
		}

		numBlocks = (M*N*N*M + blockSize - 1)/blockSize;
		multi_vec<<<blockSize, numBlocks>>>(M*N*N*M,M,N,N,N,res,trasposta,matriceA);

		c=N*N;
		while (c>N) {
			c/=THREAD_LOAD;
			numBlocks = (c + blockSize - 1)/blockSize;
			reduction_row<<<blockSize, numBlocks>>>(c,THREAD_LOAD,res2,res);
			err = cudaMemcpy(res, res2, c*sizeof(float), cudaMemcpyDeviceToDevice);
			cuda_check(err, "cpy");
		}


		numBlocks = (N*N + blockSize - 1)/blockSize;
		multi_vec<<<blockSize, numBlocks>>>(N*N,M,N,N,M,den,res2,pk);
		c=N;
		while (c>1) {
			c/=THREAD_LOAD;
			numBlocks = (c + blockSize - 1)/blockSize;
			reduction_row<<<blockSize, numBlocks>>>(c,THREAD_LOAD,red_den,den);
			err = cudaMemcpy(den, red_den, c*sizeof(float), cudaMemcpyDeviceToDevice);
			cuda_check(err, "cpy");
		}
		err = cudaMemcpy(num, res1, 1*sizeof(float), cudaMemcpyDeviceToHost);
		err = cudaMemcpy(deno, red_den, 1*sizeof(float), cudaMemcpyDeviceToHost);
		ak=num[0]/deno[0];
		printf("%f\n",ak );
		numBlocks = (N + blockSize - 1)/blockSize;
		cudaEventRecord(pre_scalar_matrice);
		scalareMatrice<<<blockSize, numBlocks>>>(scalar,ak,pk);
		cudaEventRecord(post_scalar_matrice);

		numBlocks = (N*N + blockSize - 1)/blockSize;
		cudaEventRecord(pre_vecsum);
		vecsum<<<blockSize, numBlocks>>>(N*M*N,matriceX,matriceX,scalar);
		cudaEventRecord(post_vecsum);

		err = cudaMemcpy(matrice, matriceX, M*N*sizeof(float), cudaMemcpyDeviceToHost);
		cuda_check(err, "create mem");
	  stampa(matrice,M*N);



		float runtime_init_ms, runtime_prodotto_ms, runtime_red_ms,runtime_transpose_ms,runtime_scalar_matrice_ms,
					runtime_vecdif_ms,runtime_vecsum_ms,runtime_red_count_ms;
		err = cudaEventElapsedTime(&runtime_init_ms, pre_init, post_init);
		cuda_check(err, "elapsed time init");
		err = cudaEventElapsedTime(&runtime_prodotto_ms, pre_prodotto, post_prodotto);
		cuda_check(err, "elapsed time prodotto");
		runtime_red_count_ms=0;
		for(j=0;j<lr;j++){

			err = cudaEventElapsedTime(&runtime_red_ms, pre_red[j], post_red[j]);
			cuda_check(err, "elapsed time reduction");
			runtime_red_count_ms+=runtime_red_ms;

		}
		err = cudaEventElapsedTime(&runtime_transpose_ms, pre_transpose, post_transpose);
		cuda_check(err, "elapsed time traspose");
		err = cudaEventElapsedTime(&runtime_scalar_matrice_ms, pre_scalar_matrice, post_scalar_matrice);
		cuda_check(err, "elapsed time scalar_matrice");
		err = cudaEventElapsedTime(&runtime_vecdif_ms, pre_vecdif, post_vecdif);
		cuda_check(err, "elapsed time vecdif");
		err = cudaEventElapsedTime(&runtime_vecsum_ms, pre_vecsum, post_vecsum);
		cuda_check(err, "elapsed time vecsum");


		printf("init: runtime %.4gms, %.4g GE/s, %.4g GB/s\n",
			runtime_init_ms, nels/runtime_init_ms/1.0e6, memsize/runtime_init_ms/1.0e6);
		printf("prodotto: runtime %.4gms, %.4g GE/s, %.4g GB/s\n",
			runtime_prodotto_ms, nels/runtime_prodotto_ms/1.0e6, memsize/runtime_prodotto_ms/1.0e6);
		printf("reduction: runtime %.4gms, %.4g GE/s, %.4g GB/s\n",
			runtime_red_count_ms, nels_red/runtime_red_count_ms/1.0e6, (nels_red*sizeof(float))/runtime_red_count_ms/1.0e6);
		printf("transpose: runtime %.4gms, %.4g GE/s, %.4g GB/s\n",
			runtime_transpose_ms, N/runtime_transpose_ms/1.0e6, (N*sizeof(float))/runtime_transpose_ms/1.0e6);
		printf("scalareMatrice: runtime %.4gms, %.4g GE/s, %.4g GB/s\n",
			runtime_scalar_matrice_ms, N/runtime_scalar_matrice_ms/1.0e6, (N*sizeof(float))/runtime_scalar_matrice_ms/1.0e6);
		printf("vecdif: runtime %.4gms, %.4g GE/s, %.4g GB/s\n",
			runtime_vecdif_ms, N/runtime_vecdif_ms/1.0e6, (N*sizeof(float))/runtime_vecdif_ms/1.0e6);
		printf("vecsum: runtime %.4gms, %.4g GE/s, %.4g GB/s\n",
				runtime_vecsum_ms, N/runtime_vecsum_ms/1.0e6, (N*sizeof(float))/runtime_vecsum_ms/1.0e6);

	}
  cudaFree(matriceA);
	cudaFreeHost(matrice);
	cudaFree(somma);
	cudaFree(res);
	cudaFree(pk);
	cudaFree(trasposta);
	cudaFree(prodotto);
	cudaFree(den);
	cudaFree(res0);
	cudaFree(res1);
	cudaFree(res2);
	cudaFree(red_den);
	cudaFree(scalar);
	cudaFree(matriceB);
	cudaFree(matriceX);
	cudaFreeHost(num);
	cudaFreeHost(deno);

}

	.file	"tmpxft_002edeaa_00000000-6_versione2.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2034:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2034:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"%s\n"
	.text
	.globl	_Z5errorPKc
	.type	_Z5errorPKc, @function
_Z5errorPKc:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	leaq	.LC0(%rip), %rdx
	movl	$2, %esi
	pushq	%rax
	.cfi_def_cfa_offset 16
	movq	%rdi, %rcx
	movq	stderr(%rip), %rdi
	xorl	%eax, %eax
	call	__fprintf_chk@PLT
	movl	$1, %edi
	call	exit@PLT
	.cfi_endproc
.LFE2027:
	.size	_Z5errorPKc, .-_Z5errorPKc
	.section	.rodata.str1.1
.LC1:
	.string	"%s: CUDA error %d (%s)\n"
	.text
	.globl	_Z10cuda_check9cudaErrorPKc
	.type	_Z10cuda_check9cudaErrorPKc, @function
_Z10cuda_check9cudaErrorPKc:
.LFB2028:
	.cfi_startproc
	endbr64
	testl	%edi, %edi
	je	.L4
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movq	%rsi, %rbx
	subq	$16, %rsp
	.cfi_def_cfa_offset 32
	movl	%edi, 12(%rsp)
	call	cudaGetErrorString@PLT
	movl	12(%rsp), %r8d
	movq	%rbx, %rcx
	movq	stderr(%rip), %rdi
	addq	$16, %rsp
	.cfi_def_cfa_offset 16
	movq	%rax, %r9
	movl	$2, %esi
	xorl	%eax, %eax
	leaq	.LC1(%rip), %rdx
	popq	%rbx
	.cfi_restore 3
	.cfi_def_cfa_offset 8
	jmp	__fprintf_chk@PLT
.L4:
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z10cuda_check9cudaErrorPKc, .-_Z10cuda_check9cudaErrorPKc
	.globl	_ZplRK6float4S1_
	.type	_ZplRK6float4S1_, @function
_ZplRK6float4S1_:
.LFB2029:
	.cfi_startproc
	endbr64
	movss	4(%rdi), %xmm3
	addss	4(%rsi), %xmm3
	movss	12(%rdi), %xmm2
	movss	(%rdi), %xmm1
	addss	12(%rsi), %xmm2
	addss	(%rsi), %xmm1
	movss	8(%rdi), %xmm0
	addss	8(%rsi), %xmm0
	movd	%xmm3, %edx
	salq	$32, %rdx
	movd	%xmm1, %eax
	movd	%xmm2, %ecx
	orq	%rax, %rdx
	salq	$32, %rcx
	movd	%xmm0, %eax
	orq	%rcx, %rax
	movq	%rdx, %xmm0
	movq	%rax, %xmm1
	ret
	.cfi_endproc
.LFE2029:
	.size	_ZplRK6float4S1_, .-_ZplRK6float4S1_
	.section	.rodata.str1.1
.LC2:
	.string	"\n"
.LC3:
	.string	"%f  "
	.text
	.globl	_Z6stampaPfi
	.type	_Z6stampaPfi, @function
_Z6stampaPfi:
.LFB2030:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	xorl	%eax, %eax
	leaq	.LC3(%rip), %r14
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	leaq	.LC2(%rip), %r13
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	movq	%rdi, %r12
	movl	$2, %edi
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movl	%esi, %ebp
	movq	%r13, %rsi
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	xorl	%ebx, %ebx
	call	__printf_chk@PLT
.L12:
	cmpl	%ebx, %ebp
	jle	.L15
	movq	%r14, %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	(%r12,%rbx,4), %xmm0
	call	__printf_chk@PLT
	movq	%r13, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	incq	%rbx
	jmp	.L12
.L15:
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2030:
	.size	_Z6stampaPfi, .-_Z6stampaPfi
	.globl	_Z28__device_stub__Z8init_veciPfiPf
	.type	_Z28__device_stub__Z8init_veciPfiPf, @function
_Z28__device_stub__Z8init_veciPfiPf:
.LFB2056:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movl	%edi, 12(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	leaq	40(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rax
	movq	%rsi, 16(%rsp)
	leaq	52(%rsp), %rsi
	movq	%rax, 88(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movl	$1, 48(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L16
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z8init_veciPf(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L16:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L18
	call	__stack_chk_fail@PLT
.L18:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2056:
	.size	_Z28__device_stub__Z8init_veciPfiPf, .-_Z28__device_stub__Z8init_veciPfiPf
	.globl	_Z8init_veciPf
	.type	_Z8init_veciPf, @function
_Z8init_veciPf:
.LFB2057:
	.cfi_startproc
	endbr64
	jmp	_Z28__device_stub__Z8init_veciPfiPf
	.cfi_endproc
.LFE2057:
	.size	_Z8init_veciPf, .-_Z8init_veciPf
	.globl	_Z39__device_stub__Z10multi_vec2iiiiiPfS_S_iiiiiPfS_S_
	.type	_Z39__device_stub__Z10multi_vec2iiiiiPfS_S_iiiiiPfS_S_, @function
_Z39__device_stub__Z10multi_vec2iiiiiPfS_S_iiiiiPfS_S_:
.LFB2058:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movl	%edi, 28(%rsp)
	leaq	72(%rsp), %rdi
	movl	%esi, 24(%rsp)
	leaq	84(%rsp), %rsi
	movl	%edx, 20(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movq	%r9, 32(%rsp)
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 160(%rsp)
	movq	208(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 40(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 168(%rsp)
	movq	216(%rsp), %rax
	movl	$1, 92(%rsp)
	movq	%rax, 48(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L21
	pushq	64(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z10multi_vec2iiiiiPfS_S_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 224
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L21:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L23
	call	__stack_chk_fail@PLT
.L23:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2058:
	.size	_Z39__device_stub__Z10multi_vec2iiiiiPfS_S_iiiiiPfS_S_, .-_Z39__device_stub__Z10multi_vec2iiiiiPfS_S_iiiiiPfS_S_
	.globl	_Z10multi_vec2iiiiiPfS_S_
	.type	_Z10multi_vec2iiiiiPfS_S_, @function
_Z10multi_vec2iiiiiPfS_S_:
.LFB2059:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z10multi_vec2iiiiiPfS_S_iiiiiPfS_S_
	.cfi_endproc
.LFE2059:
	.size	_Z10multi_vec2iiiiiPfS_S_, .-_Z10multi_vec2iiiiiPfS_S_
	.globl	_Z37__device_stub__Z9multi_veciiiiiPfS_S_iiiiiPfS_S_
	.type	_Z37__device_stub__Z9multi_veciiiiiPfS_S_iiiiiPfS_S_, @function
_Z37__device_stub__Z9multi_veciiiiiPfS_S_iiiiiPfS_S_:
.LFB2060:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movl	%edi, 28(%rsp)
	leaq	72(%rsp), %rdi
	movl	%esi, 24(%rsp)
	leaq	84(%rsp), %rsi
	movl	%edx, 20(%rsp)
	leaq	56(%rsp), %rdx
	movl	%ecx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movq	%r9, 32(%rsp)
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 160(%rsp)
	movq	208(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 40(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 168(%rsp)
	movq	216(%rsp), %rax
	movl	$1, 92(%rsp)
	movq	%rax, 48(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L26
	pushq	64(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z9multi_veciiiiiPfS_S_(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 224
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L26:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L28
	call	__stack_chk_fail@PLT
.L28:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2060:
	.size	_Z37__device_stub__Z9multi_veciiiiiPfS_S_iiiiiPfS_S_, .-_Z37__device_stub__Z9multi_veciiiiiPfS_S_iiiiiPfS_S_
	.globl	_Z9multi_veciiiiiPfS_S_
	.type	_Z9multi_veciiiiiPfS_S_, @function
_Z9multi_veciiiiiPfS_S_:
.LFB2061:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z9multi_veciiiiiPfS_S_iiiiiPfS_S_
	.cfi_endproc
.LFE2061:
	.size	_Z9multi_veciiiiiPfS_S_, .-_Z9multi_veciiiiiPfS_S_
	.globl	_Z37__device_stub__Z14scalareMatricePffS_PffS_
	.type	_Z37__device_stub__Z14scalareMatricePffS_PffS_, @function
_Z37__device_stub__Z14scalareMatricePffS_PffS_:
.LFB2062:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movss	%xmm0, 12(%rsp)
	leaq	40(%rsp), %rcx
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	16(%rsp), %rax
	movq	%rdi, 16(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rax, 96(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	24(%rsp), %rax
	movq	%rsi, 24(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movl	$1, 56(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L31
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z14scalareMatricePffS_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L31:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L33
	call	__stack_chk_fail@PLT
.L33:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2062:
	.size	_Z37__device_stub__Z14scalareMatricePffS_PffS_, .-_Z37__device_stub__Z14scalareMatricePffS_PffS_
	.globl	_Z14scalareMatricePffS_
	.type	_Z14scalareMatricePffS_, @function
_Z14scalareMatricePffS_:
.LFB2063:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z14scalareMatricePffS_PffS_
	.cfi_endproc
.LFE2063:
	.size	_Z14scalareMatricePffS_, .-_Z14scalareMatricePffS_
	.globl	_Z37__device_stub__Z13reduction_rowiiPfS_iiPfS_
	.type	_Z37__device_stub__Z13reduction_rowiiPfS_iiPfS_, @function
_Z37__device_stub__Z13reduction_rowiiPfS_iiPfS_:
.LFB2064:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movl	%edi, 28(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 24(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 16(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, 8(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L36
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z13reduction_rowiiPfS_(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L36:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L38
	call	__stack_chk_fail@PLT
.L38:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2064:
	.size	_Z37__device_stub__Z13reduction_rowiiPfS_iiPfS_, .-_Z37__device_stub__Z13reduction_rowiiPfS_iiPfS_
	.globl	_Z13reduction_rowiiPfS_
	.type	_Z13reduction_rowiiPfS_, @function
_Z13reduction_rowiiPfS_:
.LFB2065:
	.cfi_startproc
	endbr64
	jmp	_Z37__device_stub__Z13reduction_rowiiPfS_iiPfS_
	.cfi_endproc
.LFE2065:
	.size	_Z13reduction_rowiiPfS_, .-_Z13reduction_rowiiPfS_
	.globl	_Z32__device_stub__Z9transposeiiPfS_iiPfS_
	.type	_Z32__device_stub__Z9transposeiiPfS_iiPfS_, @function
_Z32__device_stub__Z9transposeiiPfS_iiPfS_:
.LFB2066:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movl	%edi, 12(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 8(%rsp)
	leaq	68(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rax
	movq	%rdx, 24(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rcx, 32(%rsp)
	leaq	48(%rsp), %rcx
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movl	$1, 64(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L41
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z9transposeiiPfS_(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L41:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L43
	call	__stack_chk_fail@PLT
.L43:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2066:
	.size	_Z32__device_stub__Z9transposeiiPfS_iiPfS_, .-_Z32__device_stub__Z9transposeiiPfS_iiPfS_
	.globl	_Z9transposeiiPfS_
	.type	_Z9transposeiiPfS_, @function
_Z9transposeiiPfS_:
.LFB2067:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z9transposeiiPfS_iiPfS_
	.cfi_endproc
.LFE2067:
	.size	_Z9transposeiiPfS_, .-_Z9transposeiiPfS_
	.globl	_Z30__device_stub__Z6vecsumiPfS_S_iPfS_S_
	.type	_Z30__device_stub__Z6vecsumiPfS_S_iPfS_S_, @function
_Z30__device_stub__Z6vecsumiPfS_S_iPfS_S_:
.LFB2068:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movl	%edi, 12(%rsp)
	leaq	56(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rax
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rdx, 24(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	48(%rsp), %rcx
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movl	$1, 64(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L46
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z6vecsumiPfS_S_(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L46:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L48
	call	__stack_chk_fail@PLT
.L48:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2068:
	.size	_Z30__device_stub__Z6vecsumiPfS_S_iPfS_S_, .-_Z30__device_stub__Z6vecsumiPfS_S_iPfS_S_
	.globl	_Z6vecsumiPfS_S_
	.type	_Z6vecsumiPfS_S_, @function
_Z6vecsumiPfS_S_:
.LFB2069:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z6vecsumiPfS_S_iPfS_S_
	.cfi_endproc
.LFE2069:
	.size	_Z6vecsumiPfS_S_, .-_Z6vecsumiPfS_S_
	.globl	_Z30__device_stub__Z6vecdifiPfS_S_iPfS_S_
	.type	_Z30__device_stub__Z6vecdifiPfS_S_iPfS_S_, @function
_Z30__device_stub__Z6vecdifiPfS_S_iPfS_S_:
.LFB2070:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movl	%edi, 12(%rsp)
	leaq	56(%rsp), %rdi
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rax
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rdx, 24(%rsp)
	leaq	40(%rsp), %rdx
	movq	%rcx, 32(%rsp)
	leaq	48(%rsp), %rcx
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movl	$1, 64(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L51
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z6vecdifiPfS_S_(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L51:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L53
	call	__stack_chk_fail@PLT
.L53:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2070:
	.size	_Z30__device_stub__Z6vecdifiPfS_S_iPfS_S_, .-_Z30__device_stub__Z6vecdifiPfS_S_iPfS_S_
	.globl	_Z6vecdifiPfS_S_
	.type	_Z6vecdifiPfS_S_, @function
_Z6vecdifiPfS_S_:
.LFB2071:
	.cfi_startproc
	endbr64
	jmp	_Z30__device_stub__Z6vecdifiPfS_S_iPfS_S_
	.cfi_endproc
.LFE2071:
	.size	_Z6vecdifiPfS_S_, .-_Z6vecdifiPfS_S_
	.section	.rodata.str1.1
.LC5:
	.string	"syntax: vecsum nels v"
.LC6:
	.string	"N < 0"
.LC7:
	.string	"alloc matriceA"
.LC8:
	.string	"alloc matriceB"
.LC9:
	.string	"alloc matriceX"
.LC10:
	.string	"alloc matrice"
.LC11:
	.string	"alloc somma"
.LC12:
	.string	"alloc res"
.LC13:
	.string	"alloc res0"
.LC14:
	.string	"alloc prodotto"
.LC15:
	.string	"alloc res1"
.LC16:
	.string	"alloc res2"
.LC17:
	.string	"alloc pk"
.LC18:
	.string	"alloc trasposta\t"
.LC19:
	.string	"alloc den"
.LC20:
	.string	"alloc scalar"
.LC21:
	.string	"create pre_init"
.LC22:
	.string	"create pre_sum"
.LC23:
	.string	"create pre_traspose"
.LC24:
	.string	"create pre_scalar_matrice"
.LC25:
	.string	"create pre_vecdif"
.LC26:
	.string	"create pre_vecsum"
.LC27:
	.string	"create post_init"
.LC28:
	.string	"create post_sum"
.LC29:
	.string	"create post_traspose"
.LC30:
	.string	"create post_scalar_matrice"
.LC31:
	.string	"create post_vecdif"
.LC32:
	.string	"create post_vecsum"
.LC37:
	.string	"Errore N deve essere una potenza di 4,8,12,16"
.LC38:
	.string	"create pre_red"
.LC39:
	.string	"create post_red"
.LC40:
	.string	"cpy"
.LC41:
	.string	"%d %d\n"
.LC42:
	.string	"%f\n"
.LC43:
	.string	"create mem"
.LC44:
	.string	"elapsed time init"
.LC45:
	.string	"elapsed time prodotto"
.LC46:
	.string	"elapsed time reduction"
.LC47:
	.string	"elapsed time traspose"
.LC48:
	.string	"elapsed time scalar_matrice"
.LC49:
	.string	"elapsed time vecdif"
.LC50:
	.string	"elapsed time vecsum"
.LC52:
	.string	"init: runtime %.4gms, %.4g GE/s, %.4g GB/s\n"
.LC53:
	.string	"prodotto: runtime %.4gms, %.4g GE/s, %.4g GB/s\n"
.LC54:
	.string	"reduction: runtime %.4gms, %.4g GE/s, %.4g GB/s\n"
.LC55:
	.string	"transpose: runtime %.4gms, %.4g GE/s, %.4g GB/s\n"
.LC56:
	.string	"scalareMatrice: runtime %.4gms, %.4g GE/s, %.4g GB/s\n"
.LC57:
	.string	"vecdif: runtime %.4gms, %.4g GE/s, %.4g GB/s\n"
.LC58:
	.string	"vecsum: runtime %.4gms, %.4g GE/s, %.4g GB/s\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2031:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register 6
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$376, %rsp
	.cfi_offset 15, -24
	.cfi_offset 14, -32
	.cfi_offset 13, -40
	.cfi_offset 12, -48
	.cfi_offset 3, -56
	movq	%fs:40, %rax
	movq	%rax, -56(%rbp)
	xorl	%eax, %eax
	cmpl	$2, %edi
	je	.L57
	movq	-56(%rbp), %rax
	subq	%fs:40, %rax
	leaq	.LC5(%rip), %rdi
	je	.L129
	jmp	.L125
.L57:
	movq	8(%rsi), %rdi
	call	atoi@PLT
	movl	%eax, %ebx
	testl	%eax, %eax
	jns	.L59
	movq	-56(%rbp), %rax
	subq	%fs:40, %rax
	leaq	.LC6(%rip), %rdi
	jne	.L125
.L129:
	call	_Z5errorPKc
.L59:
	imull	%eax, %eax
	leaq	-312(%rbp), %rdi
	leaq	.LC10(%rip), %r12
	movl	%eax, -340(%rbp)
	cltq
	salq	$2, %rax
	movq	%rax, %rsi
	movq	%rax, -360(%rbp)
	call	cudaMalloc@PLT
	leaq	.LC7(%rip), %rsi
	movl	%eax, %edi
	call	_Z10cuda_check9cudaErrorPKc
	movslq	%ebx, %rax
	leaq	-304(%rbp), %rdi
	salq	$2, %rax
	movq	%rax, %rsi
	movq	%rax, -352(%rbp)
	call	cudaMalloc@PLT
	leaq	.LC8(%rip), %rsi
	movl	%eax, %edi
	call	_Z10cuda_check9cudaErrorPKc
	movq	-352(%rbp), %rsi
	leaq	-296(%rbp), %rdi
	call	cudaMalloc@PLT
	leaq	.LC9(%rip), %rsi
	movl	%eax, %edi
	call	_Z10cuda_check9cudaErrorPKc
	movq	-360(%rbp), %rsi
	xorl	%edx, %edx
	leaq	-208(%rbp), %rdi
	call	cudaHostAlloc@PLT
	movq	%r12, %rsi
	movl	%eax, %edi
	call	_Z10cuda_check9cudaErrorPKc
	xorl	%edx, %edx
	movl	$4, %esi
	leaq	-192(%rbp), %rdi
	call	cudaHostAlloc@PLT
	movq	%r12, %rsi
	movl	%eax, %edi
	call	_Z10cuda_check9cudaErrorPKc
	xorl	%edx, %edx
	movl	$4, %esi
	leaq	-184(%rbp), %rdi
	call	cudaHostAlloc@PLT
	movq	%r12, %rsi
	leaq	.LC19(%rip), %r12
	movl	%eax, %edi
	call	_Z10cuda_check9cudaErrorPKc
	movq	-360(%rbp), %rsi
	leaq	-264(%rbp), %rdi
	call	cudaMalloc@PLT
	leaq	.LC11(%rip), %rsi
	movl	%eax, %edi
	call	_Z10cuda_check9cudaErrorPKc
	movq	-360(%rbp), %rsi
	leaq	-256(%rbp), %rdi
	call	cudaMalloc@PLT
	leaq	.LC12(%rip), %rsi
	movl	%eax, %edi
	call	_Z10cuda_check9cudaErrorPKc
	movq	-360(%rbp), %rsi
	leaq	-240(%rbp), %rdi
	call	cudaMalloc@PLT
	leaq	.LC13(%rip), %rsi
	movl	%eax, %edi
	call	_Z10cuda_check9cudaErrorPKc
	movq	-360(%rbp), %rsi
	leaq	-272(%rbp), %rdi
	call	cudaMalloc@PLT
	leaq	.LC14(%rip), %rsi
	movl	%eax, %edi
	call	_Z10cuda_check9cudaErrorPKc
	movq	-352(%rbp), %rsi
	leaq	-232(%rbp), %rdi
	call	cudaMalloc@PLT
	leaq	.LC15(%rip), %rsi
	movl	%eax, %edi
	call	_Z10cuda_check9cudaErrorPKc
	movq	-360(%rbp), %rsi
	leaq	-224(%rbp), %rdi
	call	cudaMalloc@PLT
	leaq	.LC16(%rip), %rsi
	movl	%eax, %edi
	call	_Z10cuda_check9cudaErrorPKc
	movq	-352(%rbp), %rsi
	leaq	-288(%rbp), %rdi
	call	cudaMalloc@PLT
	leaq	.LC17(%rip), %rsi
	movl	%eax, %edi
	call	_Z10cuda_check9cudaErrorPKc
	movq	-352(%rbp), %rsi
	leaq	-280(%rbp), %rdi
	call	cudaMalloc@PLT
	leaq	.LC18(%rip), %rsi
	movl	%eax, %edi
	call	_Z10cuda_check9cudaErrorPKc
	movq	-352(%rbp), %rsi
	leaq	-248(%rbp), %rdi
	call	cudaMalloc@PLT
	movq	%r12, %rsi
	movl	%eax, %edi
	call	_Z10cuda_check9cudaErrorPKc
	movq	-352(%rbp), %rsi
	leaq	-216(%rbp), %rdi
	call	cudaMalloc@PLT
	movq	%r12, %rsi
	movl	%eax, %edi
	call	_Z10cuda_check9cudaErrorPKc
	movq	-352(%rbp), %rsi
	leaq	-200(%rbp), %rdi
	call	cudaMalloc@PLT
	leaq	.LC20(%rip), %rsi
	movl	%eax, %edi
	call	_Z10cuda_check9cudaErrorPKc
	xorl	%esi, %esi
	leaq	-176(%rbp), %rdi
	call	cudaEventCreateWithFlags@PLT
	leaq	.LC21(%rip), %rsi
	movl	%eax, %edi
	call	_Z10cuda_check9cudaErrorPKc
	xorl	%esi, %esi
	leaq	-160(%rbp), %rdi
	call	cudaEventCreateWithFlags@PLT
	leaq	.LC22(%rip), %rsi
	movl	%eax, %edi
	call	_Z10cuda_check9cudaErrorPKc
	xorl	%esi, %esi
	leaq	-144(%rbp), %rdi
	call	cudaEventCreateWithFlags@PLT
	leaq	.LC23(%rip), %rsi
	movl	%eax, %edi
	call	_Z10cuda_check9cudaErrorPKc
	xorl	%esi, %esi
	leaq	-128(%rbp), %rdi
	call	cudaEventCreateWithFlags@PLT
	leaq	.LC24(%rip), %rsi
	movl	%eax, %edi
	call	_Z10cuda_check9cudaErrorPKc
	xorl	%esi, %esi
	leaq	-96(%rbp), %rdi
	call	cudaEventCreateWithFlags@PLT
	leaq	.LC25(%rip), %rsi
	movl	%eax, %edi
	call	_Z10cuda_check9cudaErrorPKc
	xorl	%esi, %esi
	leaq	-112(%rbp), %rdi
	call	cudaEventCreateWithFlags@PLT
	leaq	.LC26(%rip), %rsi
	movl	%eax, %edi
	call	_Z10cuda_check9cudaErrorPKc
	xorl	%esi, %esi
	leaq	-168(%rbp), %rdi
	call	cudaEventCreateWithFlags@PLT
	leaq	.LC27(%rip), %rsi
	movl	%eax, %edi
	call	_Z10cuda_check9cudaErrorPKc
	xorl	%esi, %esi
	leaq	-152(%rbp), %rdi
	call	cudaEventCreateWithFlags@PLT
	leaq	.LC28(%rip), %rsi
	movl	%eax, %edi
	call	_Z10cuda_check9cudaErrorPKc
	xorl	%esi, %esi
	leaq	-136(%rbp), %rdi
	call	cudaEventCreateWithFlags@PLT
	leaq	.LC29(%rip), %rsi
	movl	%eax, %edi
	call	_Z10cuda_check9cudaErrorPKc
	xorl	%esi, %esi
	leaq	-120(%rbp), %rdi
	call	cudaEventCreateWithFlags@PLT
	leaq	.LC30(%rip), %rsi
	movl	%eax, %edi
	call	_Z10cuda_check9cudaErrorPKc
	xorl	%esi, %esi
	leaq	-88(%rbp), %rdi
	call	cudaEventCreateWithFlags@PLT
	leaq	.LC31(%rip), %rsi
	movl	%eax, %edi
	call	_Z10cuda_check9cudaErrorPKc
	xorl	%esi, %esi
	leaq	-104(%rbp), %rdi
	call	cudaEventCreateWithFlags@PLT
	leaq	.LC32(%rip), %rsi
	movl	%eax, %edi
	call	_Z10cuda_check9cudaErrorPKc
	movq	-176(%rbp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	$8388609, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	-340(%rbp), %eax
	salq	$9, %rdi
	movl	$1, %esi
	movl	$1, -72(%rbp)
	movq	%rdi, -80(%rbp)
	addl	$511, %eax
	sarl	$9, %eax
	movl	%eax, -68(%rbp)
	movl	%eax, %r14d
	movabsq	$4294967297, %rax
	movq	%rax, -64(%rbp)
	movl	-60(%rbp), %ecx
	movq	-68(%rbp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L61
	movq	-312(%rbp), %rsi
	movl	-340(%rbp), %edi
	call	_Z28__device_stub__Z8init_veciPfiPf
.L61:
	movq	-168(%rbp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	$8388609, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	leal	511(%rbx), %eax
	salq	$9, %rdi
	movl	$1, %esi
	movl	$1, -72(%rbp)
	sarl	$9, %eax
	movq	%rdi, -80(%rbp)
	movl	%eax, -68(%rbp)
	movl	%eax, -364(%rbp)
	movabsq	$4294967297, %rax
	movq	%rax, -64(%rbp)
	movl	-60(%rbp), %ecx
	movq	-68(%rbp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L62
	movq	-304(%rbp), %rsi
	movl	%ebx, %edi
	call	_Z28__device_stub__Z8init_veciPfiPf
.L62:
	movl	$8388609, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %esi
	movl	-364(%rbp), %eax
	salq	$9, %rdi
	movl	$1, -72(%rbp)
	movq	%rdi, -80(%rbp)
	movl	%eax, -68(%rbp)
	movabsq	$4294967297, %rax
	movq	%rax, -64(%rbp)
	movl	-60(%rbp), %ecx
	movq	-68(%rbp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L63
	movq	-296(%rbp), %rsi
	movl	%ebx, %edi
	call	_Z28__device_stub__Z8init_veciPfiPf
.L63:
	cvtsi2ssl	%ebx, %xmm6
	movss	.LC34(%rip), %xmm0
	movss	.LC33(%rip), %xmm2
	movss	%xmm6, -344(%rbp)
	movaps	%xmm6, %xmm1
.L64:
	comiss	%xmm0, %xmm1
	jbe	.L130
	mulss	%xmm2, %xmm1
	ucomiss	%xmm0, %xmm1
	jp	.L64
	jne	.L64
	movl	$4, %r12d
	jmp	.L65
.L130:
	xorl	%r12d, %r12d
.L65:
	movss	-344(%rbp), %xmm1
	movss	.LC35(%rip), %xmm2
.L68:
	comiss	%xmm0, %xmm1
	jbe	.L69
	mulss	%xmm2, %xmm1
	ucomiss	%xmm0, %xmm1
	jp	.L68
	jne	.L68
	movl	$8, %r12d
.L69:
	movss	-344(%rbp), %xmm1
	movss	.LC36(%rip), %xmm2
.L74:
	comiss	%xmm0, %xmm1
	jbe	.L131
	divss	%xmm2, %xmm1
	ucomiss	%xmm0, %xmm1
	jp	.L74
	movl	$12, %eax
	cmove	%eax, %r12d
	jmp	.L74
.L131:
	testl	%r12d, %r12d
	jne	.L116
	movl	$2, %edi
	leaq	.LC37(%rip), %rsi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	xorl	%edi, %edi
	call	exit@PLT
.L116:
	xorl	%r13d, %r13d
	movl	-340(%rbp), %eax
	movl	%r13d, -368(%rbp)
.L76:
	cmpl	%ebx, %eax
	jle	.L132
	cltd
	incl	-368(%rbp)
	idivl	%r12d
	jmp	.L76
.L132:
	movslq	-368(%rbp), %rax
	movq	%rsp, %rcx
	leaq	15(,%rax,8), %rax
	movq	%rax, %rsi
	movq	%rax, %rdx
	andq	$-4096, %rsi
	andq	$-16, %rdx
	subq	%rsi, %rcx
.L78:
	cmpq	%rcx, %rsp
	je	.L79
	subq	$4096, %rsp
	orq	$0, 4088(%rsp)
	jmp	.L78
.L79:
	andl	$4095, %edx
	subq	%rdx, %rsp
	testq	%rdx, %rdx
	je	.L80
	orq	$0, -8(%rsp,%rdx)
.L80:
	movq	%rsp, -384(%rbp)
	movq	%rax, %rdx
	movq	%rsp, %rcx
	andq	$-4096, %rax
	andq	$-16, %rdx
	subq	%rax, %rcx
.L81:
	cmpq	%rcx, %rsp
	je	.L82
	subq	$4096, %rsp
	orq	$0, 4088(%rsp)
	jmp	.L81
.L82:
	movq	%rdx, %rax
	andl	$4095, %eax
	subq	%rax, %rsp
	testq	%rax, %rax
	je	.L83
	orq	$0, -8(%rsp,%rax)
.L83:
	movq	-384(%rbp), %rax
	movq	-384(%rbp), %rcx
	movq	%rsp, -392(%rbp)
	movq	%rsp, %r13
	movq	%rax, -408(%rbp)
	movq	%rsp, %rax
	movq	%rcx, %rdx
	movq	%rax, -400(%rbp)
	movslq	-368(%rbp), %rax
	leaq	(%rcx,%rax,8), %r15
.L84:
	cmpq	%r15, %rdx
	je	.L133
	movq	%rdx, %rdi
	xorl	%esi, %esi
	movq	%rdx, -376(%rbp)
	call	cudaEventCreateWithFlags@PLT
	leaq	.LC38(%rip), %rsi
	movl	%eax, %edi
	call	_Z10cuda_check9cudaErrorPKc
	movq	%r13, %rdi
	xorl	%esi, %esi
	addq	$8, %r13
	call	cudaEventCreateWithFlags@PLT
	leaq	.LC39(%rip), %rsi
	movl	%eax, %edi
	call	_Z10cuda_check9cudaErrorPKc
	movq	-376(%rbp), %rdx
	addq	$8, %rdx
	jmp	.L84
.L133:
	movq	-160(%rbp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	%r14d, -68(%rbp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rax
	movl	$8388609, %edi
	movl	$1, %esi
	movl	$1, -72(%rbp)
	movq	%rax, -64(%rbp)
	movl	-60(%rbp), %ecx
	salq	$9, %rdi
	movq	-68(%rbp), %rdx
	movq	%rdi, -80(%rbp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L110
	pushq	-296(%rbp)
	movl	-340(%rbp), %edi
	movl	%ebx, %ecx
	movl	%ebx, %edx
	pushq	-312(%rbp)
	movl	$1, %r8d
	movl	%ebx, %esi
	movq	-264(%rbp), %r9
	call	_Z37__device_stub__Z9multi_veciiiiiPfS_S_iiiiiPfS_S_
	popq	%r10
	popq	%r11
.L110:
	movq	-152(%rbp), %rdi
	xorl	%esi, %esi
	movabsq	$4294967297, %r15
	call	cudaEventRecord@PLT
	xorl	%r9d, %r9d
	movl	-340(%rbp), %r13d
	movl	%r9d, -376(%rbp)
.L87:
	cmpl	%ebx, %r13d
	jle	.L134
	movl	%r13d, %eax
	xorl	%esi, %esi
	cltd
	idivl	%r12d
	addl	%eax, -376(%rbp)
	movl	%eax, -412(%rbp)
	movl	%eax, %r13d
	movq	-408(%rbp), %rax
	movq	(%rax), %rdi
	call	cudaEventRecord@PLT
	movl	$512, %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	leal	511(%r13), %eax
	movq	%r15, -64(%rbp)
	movl	$8388609, %edi
	movl	$1, %esi
	cltd
	salq	$9, %rdi
	movl	$1, -72(%rbp)
	idivl	%ecx
	movl	-60(%rbp), %ecx
	movq	%rdi, -80(%rbp)
	movl	%eax, -68(%rbp)
	movq	-68(%rbp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L88
	movq	-264(%rbp), %rcx
	movq	-240(%rbp), %rdx
	movl	%r12d, %esi
	movl	%r13d, %edi
	call	_Z37__device_stub__Z13reduction_rowiiPfS_iiPfS_
.L88:
	movq	-400(%rbp), %rax
	xorl	%esi, %esi
	movq	(%rax), %rdi
	call	cudaEventRecord@PLT
	movslq	-412(%rbp), %rdx
	movl	$3, %ecx
	movq	-240(%rbp), %rsi
	movq	-264(%rbp), %rdi
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	leaq	.LC40(%rip), %rsi
	movl	%eax, %edi
	call	_Z10cuda_check9cudaErrorPKc
	addq	$8, -400(%rbp)
	addq	$8, -408(%rbp)
	jmp	.L87
.L134:
	movl	-376(%rbp), %ecx
	movl	-368(%rbp), %edx
	leaq	.LC41(%rip), %rsi
	xorl	%eax, %eax
	movl	$2, %edi
	call	__printf_chk@PLT
	movq	-96(%rbp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	$8388609, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	-364(%rbp), %eax
	salq	$9, %rdi
	movl	$1, %esi
	movl	$1, -72(%rbp)
	movq	%rdi, -80(%rbp)
	movl	%eax, -68(%rbp)
	movabsq	$4294967297, %rax
	movq	%rax, -64(%rbp)
	movl	-60(%rbp), %ecx
	movq	-68(%rbp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L90
	movq	-240(%rbp), %rcx
	movq	-304(%rbp), %rdx
	movl	%ebx, %edi
	movq	-288(%rbp), %rsi
	call	_Z30__device_stub__Z6vecdifiPfS_S_iPfS_S_
.L90:
	movq	-88(%rbp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	-144(%rbp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	%r14d, -68(%rbp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rax
	movl	$8388609, %edi
	movl	$1, %esi
	movl	$1, -72(%rbp)
	movq	%rax, -64(%rbp)
	movl	-60(%rbp), %ecx
	salq	$9, %rdi
	movq	-68(%rbp), %rdx
	movq	%rdi, -80(%rbp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L91
	movq	-288(%rbp), %rcx
	movq	-280(%rbp), %rdx
	movl	$1, %esi
	movl	%ebx, %edi
	call	_Z32__device_stub__Z9transposeiiPfS_iiPfS_
.L91:
	movq	-136(%rbp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	$8388609, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	-364(%rbp), %eax
	salq	$9, %rdi
	movl	$1, %esi
	movl	$1, -72(%rbp)
	movq	%rdi, -80(%rbp)
	movl	%eax, -68(%rbp)
	movabsq	$4294967297, %rax
	movq	%rax, -64(%rbp)
	movl	-60(%rbp), %ecx
	movq	-68(%rbp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L92
	pushq	-288(%rbp)
	movl	$1, %r8d
	movl	%ebx, %edi
	movl	%ebx, %ecx
	pushq	-280(%rbp)
	movl	%ebx, %edx
	movl	$1, %esi
	movq	-272(%rbp), %r9
	call	_Z37__device_stub__Z9multi_veciiiiiPfS_S_iiiiiPfS_S_
	popq	%rdi
	popq	%r8
.L92:
	movabsq	$4294967297, %r15
	movl	%ebx, %r13d
.L93:
	cmpl	$1, %r13d
	jle	.L135
	movl	%r13d, %eax
	movq	%r15, -64(%rbp)
	movl	$8388609, %edi
	movl	-60(%rbp), %ecx
	cltd
	salq	$9, %rdi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	idivl	%r12d
	movq	%rdi, -80(%rbp)
	movl	$1, -72(%rbp)
	movl	$1, %esi
	movl	%eax, -400(%rbp)
	movl	%eax, %r13d
	leal	511(%rax), %eax
	sarl	$9, %eax
	movl	%eax, -68(%rbp)
	movq	-68(%rbp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L94
	movq	-272(%rbp), %rcx
	movq	-232(%rbp), %rdx
	movl	%r12d, %esi
	movl	%r13d, %edi
	call	_Z37__device_stub__Z13reduction_rowiiPfS_iiPfS_
.L94:
	movslq	-400(%rbp), %rdx
	movq	-232(%rbp), %rsi
	movl	$3, %ecx
	movq	-272(%rbp), %rdi
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	leaq	.LC40(%rip), %rsi
	movl	%eax, %edi
	call	_Z10cuda_check9cudaErrorPKc
	jmp	.L93
.L135:
	movl	%r14d, -68(%rbp)
	movl	$8388609, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$9, %rdi
	movl	$1, %esi
	movabsq	$4294967297, %rax
	movl	$1, -72(%rbp)
	movq	%rax, -64(%rbp)
	movl	-60(%rbp), %ecx
	movq	-68(%rbp), %rdx
	movq	%rdi, -80(%rbp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L96
	pushq	-312(%rbp)
	movl	-340(%rbp), %edi
	movl	%ebx, %ecx
	movl	%ebx, %edx
	pushq	-280(%rbp)
	movl	$1, %esi
	movl	%ebx, %r8d
	movq	-256(%rbp), %r9
	call	_Z37__device_stub__Z9multi_veciiiiiPfS_S_iiiiiPfS_S_
	popq	%rcx
	popq	%rsi
.L96:
	movl	-340(%rbp), %r13d
	movabsq	$4294967297, %r15
.L97:
	cmpl	%ebx, %r13d
	jle	.L136
	movl	%r13d, %eax
	movq	%r15, -64(%rbp)
	movl	$8388609, %edi
	movl	-60(%rbp), %ecx
	cltd
	salq	$9, %rdi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	idivl	%r12d
	movq	%rdi, -80(%rbp)
	movl	$1, -72(%rbp)
	movl	$1, %esi
	movl	%eax, -400(%rbp)
	movl	%eax, %r13d
	leal	511(%rax), %eax
	sarl	$9, %eax
	movl	%eax, -68(%rbp)
	movq	-68(%rbp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L98
	movq	-256(%rbp), %rcx
	movq	-224(%rbp), %rdx
	movl	%r12d, %esi
	movl	%r13d, %edi
	call	_Z37__device_stub__Z13reduction_rowiiPfS_iiPfS_
.L98:
	movslq	-400(%rbp), %rdx
	movq	-224(%rbp), %rsi
	movl	$3, %ecx
	movq	-256(%rbp), %rdi
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	leaq	.LC40(%rip), %rsi
	movl	%eax, %edi
	call	_Z10cuda_check9cudaErrorPKc
	jmp	.L97
.L136:
	movl	%r14d, -68(%rbp)
	movl	$8388609, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$9, %rdi
	movl	$1, %esi
	movabsq	$4294967297, %rax
	movl	$1, -72(%rbp)
	movq	%rax, -64(%rbp)
	movl	-60(%rbp), %ecx
	movq	-68(%rbp), %rdx
	movq	%rdi, -80(%rbp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L100
	pushq	-288(%rbp)
	movl	-340(%rbp), %edi
	movl	%ebx, %edx
	movl	%ebx, %ecx
	pushq	-224(%rbp)
	movl	$1, %r8d
	movl	$1, %esi
	movq	-248(%rbp), %r9
	call	_Z37__device_stub__Z9multi_veciiiiiPfS_S_iiiiiPfS_S_
	popq	%rax
	popq	%rdx
.L100:
	movabsq	$4294967297, %r15
	movl	%ebx, %r13d
.L101:
	cmpl	$1, %r13d
	jle	.L137
	movl	%r13d, %eax
	movq	%r15, -64(%rbp)
	movl	$8388609, %edi
	movl	-60(%rbp), %ecx
	cltd
	salq	$9, %rdi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	idivl	%r12d
	movq	%rdi, -80(%rbp)
	movl	$1, -72(%rbp)
	movl	$1, %esi
	movl	%eax, -400(%rbp)
	movl	%eax, %r13d
	leal	511(%rax), %eax
	sarl	$9, %eax
	movl	%eax, -68(%rbp)
	movq	-68(%rbp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L102
	movq	-248(%rbp), %rcx
	movq	-216(%rbp), %rdx
	movl	%r12d, %esi
	movl	%r13d, %edi
	call	_Z37__device_stub__Z13reduction_rowiiPfS_iiPfS_
.L102:
	movslq	-400(%rbp), %rdx
	movq	-216(%rbp), %rsi
	movl	$3, %ecx
	movq	-248(%rbp), %rdi
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	leaq	.LC40(%rip), %rsi
	movl	%eax, %edi
	call	_Z10cuda_check9cudaErrorPKc
	jmp	.L101
.L137:
	movq	-232(%rbp), %rsi
	movl	$2, %ecx
	movl	$4, %edx
	movq	-192(%rbp), %rdi
	call	cudaMemcpy@PLT
	movl	$2, %ecx
	movl	$4, %edx
	movq	-216(%rbp), %rsi
	movq	-184(%rbp), %rdi
	call	cudaMemcpy@PLT
	movq	-192(%rbp), %rax
	movl	$2, %edi
	leaq	.LC42(%rip), %rsi
	movss	(%rax), %xmm0
	movq	-184(%rbp), %rax
	divss	(%rax), %xmm0
	movb	$1, %al
	movd	%xmm0, %r12d
	cvtss2sd	%xmm0, %xmm0
	call	__printf_chk@PLT
	movq	-128(%rbp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	$8388609, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	-364(%rbp), %eax
	salq	$9, %rdi
	movl	$1, %esi
	movl	$1, -72(%rbp)
	movq	%rdi, -80(%rbp)
	movl	%eax, -68(%rbp)
	movabsq	$4294967297, %rax
	movq	%rax, -64(%rbp)
	movl	-60(%rbp), %ecx
	movq	-68(%rbp), %rdx
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L104
	movq	-288(%rbp), %rsi
	movq	-200(%rbp), %rdi
	movd	%r12d, %xmm0
	call	_Z37__device_stub__Z14scalareMatricePffS_PffS_
.L104:
	movq	-120(%rbp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	-112(%rbp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movl	%r14d, -68(%rbp)
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movabsq	$4294967297, %rax
	movl	$8388609, %edi
	movl	$1, %esi
	movl	$1, -72(%rbp)
	movq	%rax, -64(%rbp)
	movl	-60(%rbp), %ecx
	salq	$9, %rdi
	movq	-68(%rbp), %rdx
	movq	%rdi, -80(%rbp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L105
	movq	-296(%rbp), %rsi
	movq	-200(%rbp), %rcx
	movl	-340(%rbp), %edi
	movq	%rsi, %rdx
	call	_Z30__device_stub__Z6vecsumiPfS_S_iPfS_S_
.L105:
	movq	-104(%rbp), %rdi
	xorl	%esi, %esi
	xorl	%r12d, %r12d
	call	cudaEventRecord@PLT
	movq	-352(%rbp), %rdx
	movl	$2, %ecx
	movq	-296(%rbp), %rsi
	movq	-208(%rbp), %rdi
	call	cudaMemcpy@PLT
	leaq	.LC43(%rip), %rsi
	movl	%eax, %edi
	call	_Z10cuda_check9cudaErrorPKc
	movq	-208(%rbp), %rdi
	movl	%ebx, %esi
	leaq	.LC46(%rip), %rbx
	call	_Z6stampaPfi
	movq	-168(%rbp), %rdx
	movq	-176(%rbp), %rsi
	leaq	-332(%rbp), %rdi
	call	cudaEventElapsedTime@PLT
	leaq	.LC44(%rip), %rsi
	movl	%eax, %edi
	call	_Z10cuda_check9cudaErrorPKc
	movq	-152(%rbp), %rdx
	movq	-160(%rbp), %rsi
	leaq	-328(%rbp), %rdi
	call	cudaEventElapsedTime@PLT
	leaq	.LC45(%rip), %rsi
	movl	%eax, %edi
	call	_Z10cuda_check9cudaErrorPKc
	xorps	%xmm3, %xmm3
.L106:
	cmpl	%r12d, -368(%rbp)
	movss	%xmm3, -364(%rbp)
	jle	.L138
	movq	-392(%rbp), %rax
	leaq	-324(%rbp), %rdi
	movq	(%rax,%r12,8), %rdx
	movq	-384(%rbp), %rax
	movq	(%rax,%r12,8), %rsi
	incq	%r12
	call	cudaEventElapsedTime@PLT
	movq	%rbx, %rsi
	movl	%eax, %edi
	call	_Z10cuda_check9cudaErrorPKc
	movss	-364(%rbp), %xmm3
	addss	-324(%rbp), %xmm3
	jmp	.L106
.L138:
	movq	-136(%rbp), %rdx
	movq	-144(%rbp), %rsi
	leaq	-320(%rbp), %rdi
	call	cudaEventElapsedTime@PLT
	leaq	.LC47(%rip), %rsi
	movl	%eax, %edi
	call	_Z10cuda_check9cudaErrorPKc
	movq	-120(%rbp), %rdx
	movq	-128(%rbp), %rsi
	leaq	-316(%rbp), %rdi
	call	cudaEventElapsedTime@PLT
	leaq	.LC48(%rip), %rsi
	movl	%eax, %edi
	call	_Z10cuda_check9cudaErrorPKc
	movq	-88(%rbp), %rdx
	movq	-96(%rbp), %rsi
	leaq	-80(%rbp), %rdi
	call	cudaEventElapsedTime@PLT
	leaq	.LC49(%rip), %rsi
	movl	%eax, %edi
	call	_Z10cuda_check9cudaErrorPKc
	movq	-104(%rbp), %rdx
	movq	-112(%rbp), %rsi
	leaq	-68(%rbp), %rdi
	call	cudaEventElapsedTime@PLT
	leaq	.LC50(%rip), %rsi
	movl	%eax, %edi
	call	_Z10cuda_check9cudaErrorPKc
	cvtsi2ssl	-340(%rbp), %xmm4
	movl	$2, %edi
	movb	$3, %al
	cvtsi2ssq	-360(%rbp), %xmm5
	movss	-332(%rbp), %xmm0
	leaq	.LC52(%rip), %rsi
	movaps	%xmm4, %xmm1
	movss	%xmm4, -340(%rbp)
	divss	%xmm0, %xmm1
	movaps	%xmm5, %xmm2
	movss	%xmm5, -360(%rbp)
	divss	%xmm0, %xmm2
	cvtss2sd	%xmm0, %xmm0
	cvtss2sd	%xmm1, %xmm1
	divsd	.LC51(%rip), %xmm1
	cvtss2sd	%xmm2, %xmm2
	divsd	.LC51(%rip), %xmm2
	call	__printf_chk@PLT
	movb	$3, %al
	movss	-328(%rbp), %xmm0
	movss	-360(%rbp), %xmm5
	leaq	.LC53(%rip), %rsi
	movl	$2, %edi
	movss	-340(%rbp), %xmm4
	divss	%xmm0, %xmm5
	divss	%xmm0, %xmm4
	cvtss2sd	%xmm0, %xmm0
	cvtss2sd	%xmm5, %xmm2
	divsd	.LC51(%rip), %xmm2
	cvtss2sd	%xmm4, %xmm1
	divsd	.LC51(%rip), %xmm1
	call	__printf_chk@PLT
	movslq	-376(%rbp), %rax
	movss	-364(%rbp), %xmm3
	salq	$2, %rax
	js	.L108
	cvtsi2ssq	%rax, %xmm2
	jmp	.L109
.L108:
	shrq	%rax
	cvtsi2ssq	%rax, %xmm2
	addss	%xmm2, %xmm2
.L109:
	divss	%xmm3, %xmm2
	movl	$2, %edi
	leaq	.LC54(%rip), %rsi
	movb	$3, %al
	cvtsi2ssl	-376(%rbp), %xmm1
	cvtss2sd	%xmm3, %xmm0
	divss	%xmm3, %xmm1
	cvtss2sd	%xmm2, %xmm2
	divsd	.LC51(%rip), %xmm2
	cvtss2sd	%xmm1, %xmm1
	divsd	.LC51(%rip), %xmm1
	call	__printf_chk@PLT
	movb	$3, %al
	cvtsi2ssq	-352(%rbp), %xmm6
	movss	-320(%rbp), %xmm0
	leaq	.LC55(%rip), %rsi
	movl	$2, %edi
	movss	-344(%rbp), %xmm1
	divss	%xmm0, %xmm1
	movaps	%xmm6, %xmm2
	movd	%xmm6, %ebx
	divss	%xmm0, %xmm2
	cvtss2sd	%xmm0, %xmm0
	cvtss2sd	%xmm1, %xmm1
	divsd	.LC51(%rip), %xmm1
	cvtss2sd	%xmm2, %xmm2
	divsd	.LC51(%rip), %xmm2
	call	__printf_chk@PLT
	movd	%ebx, %xmm2
	movss	-316(%rbp), %xmm0
	movss	-344(%rbp), %xmm1
	leaq	.LC56(%rip), %rsi
	movb	$3, %al
	movl	$2, %edi
	divss	%xmm0, %xmm2
	divss	%xmm0, %xmm1
	cvtss2sd	%xmm0, %xmm0
	cvtss2sd	%xmm2, %xmm2
	divsd	.LC51(%rip), %xmm2
	cvtss2sd	%xmm1, %xmm1
	divsd	.LC51(%rip), %xmm1
	call	__printf_chk@PLT
	movd	%ebx, %xmm2
	movss	-80(%rbp), %xmm0
	movss	-344(%rbp), %xmm1
	leaq	.LC57(%rip), %rsi
	movb	$3, %al
	movl	$2, %edi
	divss	%xmm0, %xmm2
	divss	%xmm0, %xmm1
	cvtss2sd	%xmm0, %xmm0
	cvtss2sd	%xmm2, %xmm2
	divsd	.LC51(%rip), %xmm2
	cvtss2sd	%xmm1, %xmm1
	divsd	.LC51(%rip), %xmm1
	call	__printf_chk@PLT
	movd	%ebx, %xmm2
	movss	-68(%rbp), %xmm0
	movss	-344(%rbp), %xmm1
	leaq	.LC58(%rip), %rsi
	movb	$3, %al
	movl	$2, %edi
	divss	%xmm0, %xmm2
	divss	%xmm0, %xmm1
	cvtss2sd	%xmm0, %xmm0
	cvtss2sd	%xmm2, %xmm2
	divsd	.LC51(%rip), %xmm2
	cvtss2sd	%xmm1, %xmm1
	divsd	.LC51(%rip), %xmm1
	call	__printf_chk@PLT
	movq	-312(%rbp), %rdi
	call	cudaFree@PLT
	movq	-208(%rbp), %rdi
	call	cudaFreeHost@PLT
	movq	-264(%rbp), %rdi
	call	cudaFree@PLT
	movq	-256(%rbp), %rdi
	call	cudaFree@PLT
	movq	-288(%rbp), %rdi
	call	cudaFree@PLT
	movq	-280(%rbp), %rdi
	call	cudaFree@PLT
	movq	-272(%rbp), %rdi
	call	cudaFree@PLT
	movq	-248(%rbp), %rdi
	call	cudaFree@PLT
	movq	-240(%rbp), %rdi
	call	cudaFree@PLT
	movq	-232(%rbp), %rdi
	call	cudaFree@PLT
	movq	-224(%rbp), %rdi
	call	cudaFree@PLT
	movq	-216(%rbp), %rdi
	call	cudaFree@PLT
	movq	-200(%rbp), %rdi
	call	cudaFree@PLT
	movq	-304(%rbp), %rdi
	call	cudaFree@PLT
	movq	-296(%rbp), %rdi
	call	cudaFree@PLT
	movq	-192(%rbp), %rdi
	call	cudaFreeHost@PLT
	movq	-184(%rbp), %rdi
	call	cudaFreeHost@PLT
	movq	-56(%rbp), %rax
	subq	%fs:40, %rax
	je	.L112
.L125:
	call	__stack_chk_fail@PLT
.L112:
	leaq	-40(%rbp), %rsp
	xorl	%eax, %eax
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE2031:
	.size	main, .-main
	.section	.rodata.str1.1
.LC59:
	.string	"_Z6vecdifiPfS_S_"
.LC60:
	.string	"_Z6vecsumiPfS_S_"
.LC61:
	.string	"_Z9transposeiiPfS_"
.LC62:
	.string	"_Z13reduction_rowiiPfS_"
.LC63:
	.string	"_Z14scalareMatricePffS_"
.LC64:
	.string	"_Z9multi_veciiiiiPfS_S_"
.LC65:
	.string	"_Z10multi_vec2iiiiiPfS_S_"
.LC66:
	.string	"_Z8init_veciPf"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2073:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC59(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z6vecdifiPfS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC60(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z6vecsumiPfS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC61(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z9transposeiiPfS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC62(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z13reduction_rowiiPfS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC63(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z14scalareMatricePffS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC64(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z9multi_veciiiiiPfS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC65(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z10multi_vec2iiiiiPfS_S_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC66(%rip), %rdx
	movq	%rbx, %rdi
	leaq	_Z8init_veciPf(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2073:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC33:
	.long	1048576000
	.align 4
.LC34:
	.long	1065353216
	.align 4
.LC35:
	.long	1040187392
	.align 4
.LC36:
	.long	1094713344
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC51:
	.long	0
	.long	1093567616
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#import <hip/hip_runtime.h>
#include <hip/hip_runtime_api.h>
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
#include <math.h>

void error(char const *str)
{
	fprintf(stderr, "%s\n", str);
	exit(1);
}

void cuda_check(hipError_t err, char const *str)
{
	if (err != hipSuccess) {
		fprintf(stderr, "%s: CUDA error %d (%s)\n",
			str, err, hipGetErrorString(err));
	}
}

__host__ __device__
float4 operator+(const float4 &a, const float4 &b)
{
	return make_float4(a.x + b.x, a.y + b.y, a.z + b.z, a.w + b.w);
}


__global__
void init_vec(int nels, float* __restrict__ d_vec1)
{
	int i = threadIdx.x + blockIdx.x * blockDim.x;
	d_vec1[i] = i;
}


__global__
void multi_vec2(int nels,int n_row1,int n_col1,int n_row2,int n_col2,float* __restrict__ res_vec,float* __restrict__ d_vec1,float* __restrict__ d_vec2)
{
	int i = threadIdx.x + blockIdx.x * blockDim.x;
	int r_res,c_res;
	r_res=n_row1;
	c_res=n_row2*n_col2;
	if(i<(r_res*c_res)){
	//int c= blockIdx.x*n_row1 + (threadIdx.x)%n_col1;


	int c= ((int)(i/c_res))*n_row1 + ((int)(i%n_col1))%n_col1;

	int j= ((int)(((int)(i%c_res))/n_row2) + (((int)(i%c_res))%n_row2)*n_col2);

	printf("%f %f\n",d_vec1[c],d_vec2[j] );
	res_vec[i]=d_vec1[c]*d_vec2[j];
	}
}


__global__
void multi_vec(int nels,int n_row1,int n_col1,int n_row2,int n_col2,float* __restrict__ res_vec,
								float* __restrict__ d_vec1,float* __restrict__ d_vec2)
{
	int i = threadIdx.x + blockIdx.x * blockDim.x;
	int r_res,c_res;
	r_res=n_row1;
	c_res=n_row2*n_col2;
	if(i<(r_res*c_res)){
		int c= ((int)(i/c_res))*n_row1 + ((int)(i%n_col1))%n_col1;
		int j= ((int)(((int)(i%c_res))/n_row2) + (((int)(i%c_res))%n_row2)*n_col2);
		res_vec[i]=d_vec1[c]*d_vec2[j];
	}
}

__global__
void scalareMatrice(float* __restrict__ res_vec,float scalar,float* __restrict__ d_vec)
{
	int i = threadIdx.x + blockIdx.x * blockDim.x;
	res_vec[i]=d_vec[i]*scalar;
}


__global__
void reduction_row(int nels,int l_elem,float* res_vec, float*  d_vec1)
{
	int idx = threadIdx.x + blockIdx.x * blockDim.x;
	const float4 noels = make_float4(0.0, 0.0, 0.0, 0.0);
	const int nquarts = nels*4;
	const int elem=nels/l_elem;
	int i=idx*l_elem;
	int i0 = i;
	int i1 = i +   4;
	int i2 = i + 2*4;
	int i3 = i + 3*4;
		 __syncthreads();
	float4 r0;
	if(l_elem >= 4){
		r0.x=d_vec1[i];
		r0.y=d_vec1[i+1];
		r0.z=d_vec1[i+2];
		r0.w=d_vec1[i+3];
	}
	else r0= noels;
	float4 r1;
	if(l_elem >= 8){
		r1.x=d_vec1[i1];
		r1.y=d_vec1[i1+1];
		r1.z=d_vec1[i1+2];
		r1.w=d_vec1[i1+3];
	}
	else r1= noels;

	float4 r2;
	if(l_elem >= 12){
		r2.x=d_vec1[i2];
		r2.y=d_vec1[i2+1];
		r2.z=d_vec1[i2+2];
		r2.w=d_vec1[i2+3];
	}
	else r2= noels;
	float4 r3;
	if(l_elem >= 16){
		r3.x=d_vec1[i3];
		r3.y=d_vec1[i3+1];
		r3.z=d_vec1[i3+2];
		r3.w=d_vec1[i3+3];
	}
	else r3= noels;

	float4 v = (r0 + r1) + (r2 + r3);

	if (idx < nels)
		res_vec[idx] = (v.x + v.y) + (v.z + v.w);

}

__global__
void transpose(int nrow,int ncols, float* __restrict__ res_vec, float* __restrict__ d_vec1)
{
	int i = threadIdx.x + blockIdx.x * blockDim.x;
	int c =i%ncols;
	int r=i/ncols;
	int l_in = r*ncols + c;
	int l_out = c * nrow + r;
	res_vec[l_out] = d_vec1[l_in];
}


__global__
void vecsum(int nels, float* __restrict__ res_vec, float* __restrict__ d_vec1, float* __restrict__ d_vec2)
{
	int i = threadIdx.x + blockIdx.x * blockDim.x;
	res_vec[i] = d_vec1[i]+d_vec2[i];
}

__global__
void vecdif(int nels, float* __restrict__ res_vec, float* __restrict__ d_vec1, float* __restrict__ d_vec2)
{
	int i = threadIdx.x + blockIdx.x * blockDim.x;
	res_vec[i] = d_vec1[i]-d_vec2[i];
}
void stampa(float* matrice,int m){
  int i,j;
	printf("\n");
  for(i=0;i<m;i++){
      printf("%f  ",matrice[i]);
			printf("\n");
	}

}

int main(int argc, char *argv[]){
  float* matriceA;
  float* matriceB;
  float* matriceX;
	float* pk;
	float* trasposta;
	float* prodotto;
	float* somma;
	float* res;
	float* den;
	float* res0;
	float* res1;
	float* res2;
	float* red_den;
  float* matrice;
	float* scalar;
	float* num;
	float* deno;
  float ak;
  int nels;
  if (argc != 2) {
    error("syntax: vecsum nels v");
  }

  int N = atoi(argv[1]);
  if (N < 0) {
    error("N < 0");
  }
	int M=1;

  nels=N*N;
  size_t memsize = nels*sizeof(float);
  hipError_t err;
  err = hipMalloc((void**)&matriceA, memsize);
  cuda_check(err, "alloc matriceA");
  err = hipMalloc((void**)&matriceB, N*M*sizeof(float));
  cuda_check(err, "alloc matriceB");
  err = hipMalloc((void**)&matriceX, N*sizeof(float));
  cuda_check(err, "alloc matriceX");
  err = hipHostMalloc(&matrice, N*N*sizeof(float), hipHostMallocDefault);
	cuda_check(err, "alloc matrice");
	err = hipHostMalloc(&num, M*sizeof(float), hipHostMallocDefault);
	cuda_check(err, "alloc matrice");
	err = hipHostMalloc(&deno, M*sizeof(float), hipHostMallocDefault);
	cuda_check(err, "alloc matrice");
	err = hipMalloc((void**)&somma,nels*M*sizeof(float));
	cuda_check(err, "alloc somma");
	err = hipMalloc((void**)&res,M*N*N*sizeof(float));
	cuda_check(err, "alloc res");
	err = hipMalloc((void**)&res0,N*M*N*sizeof(float));
	cuda_check(err, "alloc res0");
	err = hipMalloc((void**)&prodotto,M*N*N*sizeof(float));
	cuda_check(err, "alloc prodotto");
	err = hipMalloc((void**)&res1,M*N*sizeof(float));
	cuda_check(err, "alloc res1");
	err = hipMalloc((void**)&res2,M*N*N*sizeof(float));
	cuda_check(err, "alloc res2");
	err = hipMalloc((void**)&pk,M*N*sizeof(float));
	cuda_check(err, "alloc pk");
	err = hipMalloc((void**)&trasposta,M*N*sizeof(float));
	cuda_check(err, "alloc trasposta	");
	err = hipMalloc((void**)&den,M*N*sizeof(float));
	cuda_check(err, "alloc den");
	err = hipMalloc((void**)&red_den,M*N*sizeof(float));
	cuda_check(err, "alloc den");
	err = hipMalloc((void**)&scalar,M*N*sizeof(float));
	cuda_check(err, "alloc scalar");

	hipEvent_t pre_init, post_init, pre_sum, post_sum,pre_prodotto,post_prodotto,
							pre_transpose,post_transpose,pre_scalar_matrice,post_scalar_matrice,pre_vecsum,post_vecsum,
							pre_vecdif,post_vecdif;


	err = hipEventCreateWithFlags(&pre_init, 0);
	cuda_check(err, "create pre_init");
	err = hipEventCreateWithFlags(&pre_prodotto, 0);
	cuda_check(err, "create pre_sum");
	err = hipEventCreateWithFlags(&pre_transpose, 0);
	cuda_check(err, "create pre_traspose");
	err = hipEventCreateWithFlags(&pre_scalar_matrice, 0);
	cuda_check(err, "create pre_scalar_matrice");
	err = hipEventCreateWithFlags(&pre_vecdif, 0);
	cuda_check(err, "create pre_vecdif");
	err = hipEventCreateWithFlags(&pre_vecsum, 0);
	cuda_check(err, "create pre_vecsum");

	err = hipEventCreateWithFlags(&post_init, 0);
	cuda_check(err, "create post_init");
	err = hipEventCreateWithFlags(&post_prodotto, 0);
	cuda_check(err, "create post_sum");
	err = hipEventCreateWithFlags(&post_transpose, 0);
	cuda_check(err, "create post_traspose");
	err = hipEventCreateWithFlags(&post_scalar_matrice, 0);
	cuda_check(err, "create post_scalar_matrice");
	err = hipEventCreateWithFlags(&post_vecdif, 0);
	cuda_check(err, "create post_vecdif");
	err = hipEventCreateWithFlags(&post_vecsum, 0);
	cuda_check(err, "create post_vecsum");
  const int blockSize = 512;
	int numBlocks = (nels + blockSize - 1)/blockSize;


	hipEventRecord(pre_init);
	init_vec<<<blockSize,numBlocks>>>(nels, matriceA);
	hipEventRecord(post_init);

	numBlocks = (M*N + blockSize - 1)/blockSize;
  init_vec<<<blockSize, numBlocks>>>(M*N, matriceB);

	init_vec<<<blockSize, numBlocks>>>(M*N, matriceX);
	int i;

	//calcolo i parametri della riduzione
	int THREAD_LOAD=0;
	float n = N;
	while (n > 1) {
		n/=4;
		if(n==1){
			THREAD_LOAD=4;
		}
	}
	n = N;
	while (n > 1) {

		n/=8;
		if(n==1){
			THREAD_LOAD=8;
		}
	}
	n=N;
	while (n > 1) {
		n/=12;
		if(n==1){
			THREAD_LOAD=12;
		}
	}
	while (n > 1) {
		n/=16;
		if(n==1){
			THREAD_LOAD=16;
		}
	}
	if(THREAD_LOAD==0){
		printf("Errore N deve essere una potenza di 4,8,12,16");
		exit(0);
	}
	int j;
	int c=N;
	float* temp;
	float runtime_red_ms;
	int lr=0;
	int log=N*N;
	while(log>N){
		++lr;
		log=log/THREAD_LOAD;
	}

	hipEvent_t pre_red[lr], post_red[lr];
	//inizializzo gli eventi per la riduzione
	for(i=0;i<lr;i++){
		err = hipEventCreateWithFlags(&(pre_red[i]), 0);
		cuda_check(err, "create pre_red");

		err = hipEventCreateWithFlags(&(post_red[i]), 0);
		cuda_check(err, "create post_red");
	}
	for(i=0;i<1;i++){
		numBlocks = (nels + blockSize - 1)/blockSize;
		hipEventRecord(pre_prodotto);
		multi_vec<<<blockSize, numBlocks>>>(nels*M,N,N,N,M,somma,matriceA,matriceX);
		hipEventRecord(post_prodotto);

		c=N*N;

		int nels_red=0;
		int cont=0;
		while(c>N){
			c/=THREAD_LOAD;
			nels_red+=c;

			numBlocks = (c + blockSize - 1)/blockSize;
			hipEventRecord(pre_red[cont]);
			reduction_row<<<blockSize, numBlocks>>>(c,THREAD_LOAD,res0,somma);
			hipEventRecord(post_red[cont]);
			err = hipMemcpy(somma, res0, c*sizeof(float), hipMemcpyDeviceToDevice);
			cuda_check(err, "cpy");
			cont++;
		}

		printf("%d %d\n",lr,nels_red );
		numBlocks = (N*M + blockSize - 1)/blockSize;
		hipEventRecord(pre_vecdif);
		vecdif<<<blockSize, numBlocks>>>(N*M,pk,matriceB,res0);
		hipEventRecord(post_vecdif);

		numBlocks = (N*N + blockSize - 1)/blockSize;
		hipEventRecord(pre_transpose);
		transpose<<<blockSize, numBlocks>>>(N,M,trasposta,pk);
		hipEventRecord(post_transpose);
		numBlocks = (M*N + blockSize - 1)/blockSize;
		multi_vec<<<blockSize, numBlocks>>>(N*M,M,N,N,M,prodotto,trasposta,pk);
		c=N;
		while (c>1) {
			c/=THREAD_LOAD;
			numBlocks = (c + blockSize - 1)/blockSize;
			reduction_row<<<blockSize, numBlocks>>>(c,THREAD_LOAD,res1,prodotto);
			err = hipMemcpy(prodotto, res1, c*sizeof(float), hipMemcpyDeviceToDevice);
			cuda_check(err, "cpy");
		}

		numBlocks = (M*N*N*M + blockSize - 1)/blockSize;
		multi_vec<<<blockSize, numBlocks>>>(M*N*N*M,M,N,N,N,res,trasposta,matriceA);

		c=N*N;
		while (c>N) {
			c/=THREAD_LOAD;
			numBlocks = (c + blockSize - 1)/blockSize;
			reduction_row<<<blockSize, numBlocks>>>(c,THREAD_LOAD,res2,res);
			err = hipMemcpy(res, res2, c*sizeof(float), hipMemcpyDeviceToDevice);
			cuda_check(err, "cpy");
		}


		numBlocks = (N*N + blockSize - 1)/blockSize;
		multi_vec<<<blockSize, numBlocks>>>(N*N,M,N,N,M,den,res2,pk);
		c=N;
		while (c>1) {
			c/=THREAD_LOAD;
			numBlocks = (c + blockSize - 1)/blockSize;
			reduction_row<<<blockSize, numBlocks>>>(c,THREAD_LOAD,red_den,den);
			err = hipMemcpy(den, red_den, c*sizeof(float), hipMemcpyDeviceToDevice);
			cuda_check(err, "cpy");
		}
		err = hipMemcpy(num, res1, 1*sizeof(float), hipMemcpyDeviceToHost);
		err = hipMemcpy(deno, red_den, 1*sizeof(float), hipMemcpyDeviceToHost);
		ak=num[0]/deno[0];
		printf("%f\n",ak );
		numBlocks = (N + blockSize - 1)/blockSize;
		hipEventRecord(pre_scalar_matrice);
		scalareMatrice<<<blockSize, numBlocks>>>(scalar,ak,pk);
		hipEventRecord(post_scalar_matrice);

		numBlocks = (N*N + blockSize - 1)/blockSize;
		hipEventRecord(pre_vecsum);
		vecsum<<<blockSize, numBlocks>>>(N*M*N,matriceX,matriceX,scalar);
		hipEventRecord(post_vecsum);

		err = hipMemcpy(matrice, matriceX, M*N*sizeof(float), hipMemcpyDeviceToHost);
		cuda_check(err, "create mem");
	  stampa(matrice,M*N);



		float runtime_init_ms, runtime_prodotto_ms, runtime_red_ms,runtime_transpose_ms,runtime_scalar_matrice_ms,
					runtime_vecdif_ms,runtime_vecsum_ms,runtime_red_count_ms;
		err = hipEventElapsedTime(&runtime_init_ms, pre_init, post_init);
		cuda_check(err, "elapsed time init");
		err = hipEventElapsedTime(&runtime_prodotto_ms, pre_prodotto, post_prodotto);
		cuda_check(err, "elapsed time prodotto");
		runtime_red_count_ms=0;
		for(j=0;j<lr;j++){

			err = hipEventElapsedTime(&runtime_red_ms, pre_red[j], post_red[j]);
			cuda_check(err, "elapsed time reduction");
			runtime_red_count_ms+=runtime_red_ms;

		}
		err = hipEventElapsedTime(&runtime_transpose_ms, pre_transpose, post_transpose);
		cuda_check(err, "elapsed time traspose");
		err = hipEventElapsedTime(&runtime_scalar_matrice_ms, pre_scalar_matrice, post_scalar_matrice);
		cuda_check(err, "elapsed time scalar_matrice");
		err = hipEventElapsedTime(&runtime_vecdif_ms, pre_vecdif, post_vecdif);
		cuda_check(err, "elapsed time vecdif");
		err = hipEventElapsedTime(&runtime_vecsum_ms, pre_vecsum, post_vecsum);
		cuda_check(err, "elapsed time vecsum");


		printf("init: runtime %.4gms, %.4g GE/s, %.4g GB/s\n",
			runtime_init_ms, nels/runtime_init_ms/1.0e6, memsize/runtime_init_ms/1.0e6);
		printf("prodotto: runtime %.4gms, %.4g GE/s, %.4g GB/s\n",
			runtime_prodotto_ms, nels/runtime_prodotto_ms/1.0e6, memsize/runtime_prodotto_ms/1.0e6);
		printf("reduction: runtime %.4gms, %.4g GE/s, %.4g GB/s\n",
			runtime_red_count_ms, nels_red/runtime_red_count_ms/1.0e6, (nels_red*sizeof(float))/runtime_red_count_ms/1.0e6);
		printf("transpose: runtime %.4gms, %.4g GE/s, %.4g GB/s\n",
			runtime_transpose_ms, N/runtime_transpose_ms/1.0e6, (N*sizeof(float))/runtime_transpose_ms/1.0e6);
		printf("scalareMatrice: runtime %.4gms, %.4g GE/s, %.4g GB/s\n",
			runtime_scalar_matrice_ms, N/runtime_scalar_matrice_ms/1.0e6, (N*sizeof(float))/runtime_scalar_matrice_ms/1.0e6);
		printf("vecdif: runtime %.4gms, %.4g GE/s, %.4g GB/s\n",
			runtime_vecdif_ms, N/runtime_vecdif_ms/1.0e6, (N*sizeof(float))/runtime_vecdif_ms/1.0e6);
		printf("vecsum: runtime %.4gms, %.4g GE/s, %.4g GB/s\n",
				runtime_vecsum_ms, N/runtime_vecsum_ms/1.0e6, (N*sizeof(float))/runtime_vecsum_ms/1.0e6);

	}
  hipFree(matriceA);
	hipHostFree(matrice);
	hipFree(somma);
	hipFree(res);
	hipFree(pk);
	hipFree(trasposta);
	hipFree(prodotto);
	hipFree(den);
	hipFree(res0);
	hipFree(res1);
	hipFree(res2);
	hipFree(red_den);
	hipFree(scalar);
	hipFree(matriceB);
	hipFree(matriceX);
	hipHostFree(num);
	hipHostFree(deno);

}

	.text
	.file	"versione2.hip"
	.globl	_Z5errorPKc                     # -- Begin function _Z5errorPKc
	.type	_Z5errorPKc,@function
_Z5errorPKc:                            # @_Z5errorPKc
	.cfi_startproc
# %bb.0:
	pushq	%rax
	.cfi_def_cfa_offset 16
	movq	%rdi, %rdx
	movq	stderr(%rip), %rdi
	movl	$.L.str, %esi
	xorl	%eax, %eax
	callq	fprintf
	movl	$1, %edi
	callq	exit
.Lfunc_end0:
	.size	_Z5errorPKc, .Lfunc_end0-_Z5errorPKc
	.cfi_endproc
                                        # -- End function
	.globl	_Z10cuda_check10hipError_tPKc   # -- Begin function _Z10cuda_check10hipError_tPKc
	.type	_Z10cuda_check10hipError_tPKc,@function
_Z10cuda_check10hipError_tPKc:          # @_Z10cuda_check10hipError_tPKc
	.cfi_startproc
# %bb.0:
	testl	%edi, %edi
	jne	.LBB1_2
# %bb.1:
	retq
.LBB1_2:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movq	%rsi, %r14
	movl	%edi, %ebx
	movq	stderr(%rip), %r15
	callq	hipGetErrorString
	movl	$.L.str.1, %esi
	movq	%r15, %rdi
	movq	%r14, %rdx
	movl	%ebx, %ecx
	movq	%rax, %r8
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	fprintf                         # TAILCALL
.Lfunc_end1:
	.size	_Z10cuda_check10hipError_tPKc, .Lfunc_end1-_Z10cuda_check10hipError_tPKc
	.cfi_endproc
                                        # -- End function
	.globl	_ZplRK15HIP_vector_typeIfLj4EES2_ # -- Begin function _ZplRK15HIP_vector_typeIfLj4EES2_
	.type	_ZplRK15HIP_vector_typeIfLj4EES2_,@function
_ZplRK15HIP_vector_typeIfLj4EES2_:      # @_ZplRK15HIP_vector_typeIfLj4EES2_
	.cfi_startproc
# %bb.0:
	movss	(%rdi), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	movss	4(%rdi), %xmm2                  # xmm2 = mem[0],zero,zero,zero
	addss	(%rsi), %xmm0
	addss	4(%rsi), %xmm2
	movss	8(%rdi), %xmm1                  # xmm1 = mem[0],zero,zero,zero
	addss	8(%rsi), %xmm1
	movss	12(%rdi), %xmm3                 # xmm3 = mem[0],zero,zero,zero
	addss	12(%rsi), %xmm3
	unpcklps	%xmm2, %xmm0                    # xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
	unpcklps	%xmm3, %xmm1                    # xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1]
	retq
.Lfunc_end2:
	.size	_ZplRK15HIP_vector_typeIfLj4EES2_, .Lfunc_end2-_ZplRK15HIP_vector_typeIfLj4EES2_
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__init_veciPf  # -- Begin function _Z23__device_stub__init_veciPf
	.type	_Z23__device_stub__init_veciPf,@function
_Z23__device_stub__init_veciPf:         # @_Z23__device_stub__init_veciPf
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	leaq	24(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8init_veciPf, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z23__device_stub__init_veciPf, .Lfunc_end3-_Z23__device_stub__init_veciPf
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__multi_vec2iiiiiPfS_S_ # -- Begin function _Z25__device_stub__multi_vec2iiiiiPfS_S_
	.type	_Z25__device_stub__multi_vec2iiiiiPfS_S_,@function
_Z25__device_stub__multi_vec2iiiiiPfS_S_: # @_Z25__device_stub__multi_vec2iiiiiPfS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	192(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	200(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10multi_vec2iiiiiPfS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z25__device_stub__multi_vec2iiiiiPfS_S_, .Lfunc_end4-_Z25__device_stub__multi_vec2iiiiiPfS_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__multi_veciiiiiPfS_S_ # -- Begin function _Z24__device_stub__multi_veciiiiiPfS_S_
	.type	_Z24__device_stub__multi_veciiiiiPfS_S_,@function
_Z24__device_stub__multi_veciiiiiPfS_S_: # @_Z24__device_stub__multi_veciiiiiPfS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$144, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	20(%rsp), %rax
	movl	%edi, (%rax)
	leaq	16(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	8(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	4(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	40(%rsp), %r8
	movq	%r9, (%r8)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	192(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	200(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9multi_veciiiiiPfS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$160, %rsp
	.cfi_adjust_cfa_offset -160
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	_Z24__device_stub__multi_veciiiiiPfS_S_, .Lfunc_end5-_Z24__device_stub__multi_veciiiiiPfS_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z29__device_stub__scalareMatricePffS_ # -- Begin function _Z29__device_stub__scalareMatricePffS_
	.type	_Z29__device_stub__scalareMatricePffS_,@function
_Z29__device_stub__scalareMatricePffS_: # @_Z29__device_stub__scalareMatricePffS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	12(%rsp), %rcx
	movss	%xmm0, (%rcx)
	leaq	32(%rsp), %rdx
	movq	%rsi, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rdx, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z14scalareMatricePffS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end6:
	.size	_Z29__device_stub__scalareMatricePffS_, .Lfunc_end6-_Z29__device_stub__scalareMatricePffS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z28__device_stub__reduction_rowiiPfS_ # -- Begin function _Z28__device_stub__reduction_rowiiPfS_
	.type	_Z28__device_stub__reduction_rowiiPfS_,@function
_Z28__device_stub__reduction_rowiiPfS_: # @_Z28__device_stub__reduction_rowiiPfS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	8(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z13reduction_rowiiPfS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end7:
	.size	_Z28__device_stub__reduction_rowiiPfS_, .Lfunc_end7-_Z28__device_stub__reduction_rowiiPfS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z24__device_stub__transposeiiPfS_ # -- Begin function _Z24__device_stub__transposeiiPfS_
	.type	_Z24__device_stub__transposeiiPfS_,@function
_Z24__device_stub__transposeiiPfS_:     # @_Z24__device_stub__transposeiiPfS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	12(%rsp), %rax
	movl	%edi, (%rax)
	leaq	8(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9transposeiiPfS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end8:
	.size	_Z24__device_stub__transposeiiPfS_, .Lfunc_end8-_Z24__device_stub__transposeiiPfS_
	.cfi_endproc
                                        # -- End function
	.globl	_Z21__device_stub__vecsumiPfS_S_ # -- Begin function _Z21__device_stub__vecsumiPfS_S_
	.type	_Z21__device_stub__vecsumiPfS_S_,@function
_Z21__device_stub__vecsumiPfS_S_:       # @_Z21__device_stub__vecsumiPfS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	24(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6vecsumiPfS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end9:
	.size	_Z21__device_stub__vecsumiPfS_S_, .Lfunc_end9-_Z21__device_stub__vecsumiPfS_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z21__device_stub__vecdifiPfS_S_ # -- Begin function _Z21__device_stub__vecdifiPfS_S_
	.type	_Z21__device_stub__vecdifiPfS_S_,@function
_Z21__device_stub__vecdifiPfS_S_:       # @_Z21__device_stub__vecdifiPfS_S_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	24(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6vecdifiPfS_S_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end10:
	.size	_Z21__device_stub__vecdifiPfS_S_, .Lfunc_end10-_Z21__device_stub__vecdifiPfS_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z6stampaPfi                    # -- Begin function _Z6stampaPfi
	.type	_Z6stampaPfi,@function
_Z6stampaPfi:                           # @_Z6stampaPfi
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%esi, %ebp
	movq	%rdi, %rbx
	movl	$10, %edi
	callq	putchar@PLT
	testl	%ebp, %ebp
	jle	.LBB11_3
# %bb.1:                                # %.lr.ph.preheader
	movl	%ebp, %r14d
	xorl	%r15d, %r15d
.LBB11_2:                               # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rbx,%r15,4), %xmm0
	movl	$.L.str.3, %edi
	movb	$1, %al
	callq	printf
	movl	$10, %edi
	callq	putchar@PLT
	incq	%r15
	cmpq	%r15, %r14
	jne	.LBB11_2
.LBB11_3:                               # %._crit_edge
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end11:
	.size	_Z6stampaPfi, .Lfunc_end11-_Z6stampaPfi
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI12_0:
	.long	0x3e800000                      # float 0.25
.LCPI12_1:
	.long	0x3f800000                      # float 1
.LCPI12_2:
	.long	0x3e000000                      # float 0.125
.LCPI12_3:
	.long	0x41400000                      # float 12
.LCPI12_4:
	.long	0x3d800000                      # float 0.0625
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0
.LCPI12_5:
	.quad	0x412e848000000000              # double 1.0E+6
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset %rbp, -16
	movq	%rsp, %rbp
	.cfi_def_cfa_register %rbp
	pushq	%r15
	pushq	%r14
	pushq	%r13
	pushq	%r12
	pushq	%rbx
	subq	$360, %rsp                      # imm = 0x168
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	cmpl	$2, %edi
	jne	.LBB12_1
# %bb.3:
	movq	8(%rsi), %rdi
	callq	atoi
	testl	%eax, %eax
	js	.LBB12_4
# %bb.5:
	movl	%eax, %r14d
	movabsq	$4294967808, %r15               # imm = 0x100000200
	movl	%eax, %r13d
	imull	%r13d, %r13d
	leaq	(,%r13,4), %rbx
	leaq	-200(%rbp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	movl	$.L.str.6, %esi
	movl	%eax, %edi
	callq	_Z10cuda_check10hipError_tPKc
	movl	%r14d, %r12d
	shlq	$2, %r12
	leaq	-256(%rbp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movl	$.L.str.7, %esi
	movl	%eax, %edi
	callq	_Z10cuda_check10hipError_tPKc
	leaq	-112(%rbp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movl	$.L.str.8, %esi
	movl	%eax, %edi
	callq	_Z10cuda_check10hipError_tPKc
	leaq	-248(%rbp), %rdi
	movq	%rbx, %rsi
	xorl	%edx, %edx
	callq	hipHostMalloc
	movl	$.L.str.9, %esi
	movl	%eax, %edi
	callq	_Z10cuda_check10hipError_tPKc
	leaq	-232(%rbp), %rdi
	movl	$4, %esi
	xorl	%edx, %edx
	callq	hipHostMalloc
	movl	$.L.str.9, %esi
	movl	%eax, %edi
	callq	_Z10cuda_check10hipError_tPKc
	leaq	-224(%rbp), %rdi
	movl	$4, %esi
	xorl	%edx, %edx
	callq	hipHostMalloc
	movl	$.L.str.9, %esi
	movl	%eax, %edi
	callq	_Z10cuda_check10hipError_tPKc
	leaq	-176(%rbp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	movl	$.L.str.10, %esi
	movl	%eax, %edi
	callq	_Z10cuda_check10hipError_tPKc
	leaq	-168(%rbp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	movl	$.L.str.11, %esi
	movl	%eax, %edi
	callq	_Z10cuda_check10hipError_tPKc
	leaq	-152(%rbp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	movl	$.L.str.12, %esi
	movl	%eax, %edi
	callq	_Z10cuda_check10hipError_tPKc
	leaq	-184(%rbp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	movl	$.L.str.13, %esi
	movl	%eax, %edi
	callq	_Z10cuda_check10hipError_tPKc
	leaq	-144(%rbp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movl	$.L.str.14, %esi
	movl	%eax, %edi
	callq	_Z10cuda_check10hipError_tPKc
	leaq	-136(%rbp), %rdi
	movq	%rbx, -392(%rbp)                # 8-byte Spill
	movq	%rbx, %rsi
	callq	hipMalloc
	movl	$.L.str.15, %esi
	movl	%eax, %edi
	callq	_Z10cuda_check10hipError_tPKc
	leaq	-72(%rbp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movl	$.L.str.16, %esi
	movl	%eax, %edi
	callq	_Z10cuda_check10hipError_tPKc
	leaq	-192(%rbp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movl	$.L.str.17, %esi
	movl	%eax, %edi
	callq	_Z10cuda_check10hipError_tPKc
	leaq	-160(%rbp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movl	$.L.str.18, %esi
	movl	%eax, %edi
	callq	_Z10cuda_check10hipError_tPKc
	leaq	-128(%rbp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movl	$.L.str.18, %esi
	movl	%eax, %edi
	callq	_Z10cuda_check10hipError_tPKc
	leaq	-240(%rbp), %rdi
	movq	%r12, -208(%rbp)                # 8-byte Spill
	movq	%r12, %rsi
	callq	hipMalloc
	movl	$.L.str.19, %esi
	movl	%eax, %edi
	callq	_Z10cuda_check10hipError_tPKc
	leaq	-400(%rbp), %r12
	movq	%r12, %rdi
	xorl	%esi, %esi
	callq	hipEventCreateWithFlags
	movl	$.L.str.20, %esi
	movl	%eax, %edi
	callq	_Z10cuda_check10hipError_tPKc
	leaq	-376(%rbp), %rdi
	xorl	%esi, %esi
	callq	hipEventCreateWithFlags
	movl	$.L.str.21, %esi
	movl	%eax, %edi
	callq	_Z10cuda_check10hipError_tPKc
	leaq	-360(%rbp), %rdi
	xorl	%esi, %esi
	callq	hipEventCreateWithFlags
	movl	$.L.str.22, %esi
	movl	%eax, %edi
	callq	_Z10cuda_check10hipError_tPKc
	leaq	-344(%rbp), %rdi
	xorl	%esi, %esi
	callq	hipEventCreateWithFlags
	movl	$.L.str.23, %esi
	movl	%eax, %edi
	callq	_Z10cuda_check10hipError_tPKc
	leaq	-312(%rbp), %rdi
	xorl	%esi, %esi
	callq	hipEventCreateWithFlags
	movl	$.L.str.24, %esi
	movl	%eax, %edi
	callq	_Z10cuda_check10hipError_tPKc
	leaq	-328(%rbp), %rdi
	xorl	%esi, %esi
	callq	hipEventCreateWithFlags
	movl	$.L.str.25, %esi
	movl	%eax, %edi
	callq	_Z10cuda_check10hipError_tPKc
	leaq	-384(%rbp), %rdi
	xorl	%esi, %esi
	callq	hipEventCreateWithFlags
	movl	$.L.str.26, %esi
	movl	%eax, %edi
	callq	_Z10cuda_check10hipError_tPKc
	leaq	-368(%rbp), %rdi
	xorl	%esi, %esi
	callq	hipEventCreateWithFlags
	movl	$.L.str.27, %esi
	movl	%eax, %edi
	callq	_Z10cuda_check10hipError_tPKc
	leaq	-352(%rbp), %rdi
	xorl	%esi, %esi
	callq	hipEventCreateWithFlags
	movl	$.L.str.28, %esi
	movl	%eax, %edi
	callq	_Z10cuda_check10hipError_tPKc
	leaq	-336(%rbp), %rdi
	xorl	%esi, %esi
	callq	hipEventCreateWithFlags
	movl	$.L.str.29, %esi
	movl	%eax, %edi
	callq	_Z10cuda_check10hipError_tPKc
	leaq	-304(%rbp), %rdi
	xorl	%esi, %esi
	callq	hipEventCreateWithFlags
	movl	$.L.str.30, %esi
	movl	%eax, %edi
	callq	_Z10cuda_check10hipError_tPKc
	leaq	-320(%rbp), %rdi
	xorl	%esi, %esi
	callq	hipEventCreateWithFlags
	movl	$.L.str.31, %esi
	movl	%eax, %edi
	callq	_Z10cuda_check10hipError_tPKc
	movq	%r14, %rbx
	leal	511(%r13), %r14d
	shrl	$9, %r14d
	movq	(%r12), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	leaq	(%r14,%r15), %rdx
	addq	$-512, %rdx                     # imm = 0xFE00
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%rdx, -80(%rbp)                 # 8-byte Spill
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB12_7
# %bb.6:
	movq	-200(%rbp), %rsi
	movl	%r13d, %edi
	callq	_Z23__device_stub__init_veciPf
.LBB12_7:
	movq	%r13, %r12
	movq	-384(%rbp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	leal	511(%rbx), %eax
	shrl	$9, %eax
	leaq	(%r15,%rax), %r13
	addq	$-512, %r13                     # imm = 0xFE00
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	movq	%rbx, %r14
	jne	.LBB12_9
# %bb.8:
	movq	-256(%rbp), %rsi
	movl	%r14d, %edi
	callq	_Z23__device_stub__init_veciPf
.LBB12_9:
	xorl	%ebx, %ebx
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r13, -216(%rbp)                # 8-byte Spill
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB12_11
# %bb.10:
	movq	-112(%rbp), %rsi
	movl	%r14d, %edi
	callq	_Z23__device_stub__init_veciPf
.LBB12_11:
	cvtsi2ss	%r14d, %xmm3
	movaps	%xmm3, %xmm1
	cmpl	$2, %r14d
	movq	%r12, %r13
	jb	.LBB12_16
# %bb.12:                               # %.lr.ph.preheader
	xorl	%eax, %eax
	movss	.LCPI12_0(%rip), %xmm1          # xmm1 = mem[0],zero,zero,zero
	movss	.LCPI12_1(%rip), %xmm0          # xmm0 = mem[0],zero,zero,zero
	movaps	%xmm3, %xmm2
.LBB12_13:                              # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	%eax, %ecx
	mulss	%xmm1, %xmm2
	ucomiss	%xmm0, %xmm2
	movl	$4, %eax
	cmovnel	%ecx, %eax
	cmovpl	%ecx, %eax
	ja	.LBB12_13
# %bb.14:                               # %.preheader441
	cmpl	$2, %r14d
	jb	.LBB12_15
# %bb.29:
	movss	.LCPI12_2(%rip), %xmm1          # xmm1 = mem[0],zero,zero,zero
	movaps	%xmm3, %xmm2
.LBB12_30:                              # %.lr.ph446
                                        # =>This Inner Loop Header: Depth=1
	movl	%eax, %ecx
	mulss	%xmm1, %xmm2
	ucomiss	%xmm0, %xmm2
	movl	$8, %eax
	cmovnel	%ecx, %eax
	cmovpl	%ecx, %eax
	ja	.LBB12_30
# %bb.26:                               # %.preheader440
	cmpl	$2, %r14d
	jb	.LBB12_15
# %bb.27:
	movss	.LCPI12_3(%rip), %xmm2          # xmm2 = mem[0],zero,zero,zero
	movaps	%xmm3, %xmm1
.LBB12_28:                              # %.lr.ph450
                                        # =>This Inner Loop Header: Depth=1
	divss	%xmm2, %xmm1
	ucomiss	%xmm0, %xmm1
	movl	$12, %ebx
	cmovnel	%eax, %ebx
	cmovpl	%eax, %ebx
	movl	%ebx, %eax
	ja	.LBB12_28
	jmp	.LBB12_16
.LBB12_15:
	movaps	%xmm3, %xmm1
	movl	%eax, %ebx
.LBB12_16:                              # %.preheader439
	ucomiss	.LCPI12_1(%rip), %xmm1
	jbe	.LBB12_19
# %bb.17:
	movss	.LCPI12_4(%rip), %xmm0          # xmm0 = mem[0],zero,zero,zero
	movss	.LCPI12_1(%rip), %xmm2          # xmm2 = mem[0],zero,zero,zero
.LBB12_18:                              # %.lr.ph455
                                        # =>This Inner Loop Header: Depth=1
	mulss	%xmm0, %xmm1
	ucomiss	%xmm2, %xmm1
	movl	$16, %eax
	cmovnel	%ebx, %eax
	cmovnpl	%eax, %ebx
	ja	.LBB12_18
.LBB12_19:                              # %._crit_edge
	testl	%ebx, %ebx
	je	.LBB12_73
# %bb.20:                               # %.preheader
	cmpl	%r14d, %r13d
	movq	%r13, -120(%rbp)                # 8-byte Spill
	movq	%r14, -48(%rbp)                 # 8-byte Spill
	movss	%xmm3, -56(%rbp)                # 4-byte Spill
	jle	.LBB12_31
# %bb.21:                               # %.lr.ph459.preheader
	xorl	%r12d, %r12d
	movl	%r13d, %eax
.LBB12_22:                              # %.lr.ph459
                                        # =>This Inner Loop Header: Depth=1
	cltd
	idivl	%ebx
	incq	%r12
	cmpl	%r14d, %eax
	jg	.LBB12_22
# %bb.23:                               # %.lr.ph464.preheader
	movq	%rsp, -296(%rbp)                # 8-byte Spill
	movq	%rsp, %r14
	leaq	15(,%r12,8), %rax
	andq	$-16, %rax
	subq	%rax, %r14
	movq	%r14, %rsp
	movq	%rsp, %r15
	subq	%rax, %r15
	movq	%r15, %rsp
	movq	%r12, %r13
	movq	%r14, -96(%rbp)                 # 8-byte Spill
	movq	%r15, -88(%rbp)                 # 8-byte Spill
.LBB12_24:                              # %.lr.ph464
                                        # =>This Inner Loop Header: Depth=1
	movq	%r14, %rdi
	xorl	%esi, %esi
	callq	hipEventCreateWithFlags
	movl	$.L.str.33, %esi
	movl	%eax, %edi
	callq	_Z10cuda_check10hipError_tPKc
	movq	%r15, %rdi
	xorl	%esi, %esi
	callq	hipEventCreateWithFlags
	movl	$.L.str.34, %esi
	movl	%eax, %edi
	callq	_Z10cuda_check10hipError_tPKc
	addq	$8, %r15
	addq	$8, %r14
	decq	%r13
	jne	.LBB12_24
# %bb.25:                               # %._crit_edge465.loopexit
	movl	%r12d, %eax
	movl	%r12d, -52(%rbp)                # 4-byte Spill
	movq	-120(%rbp), %r13                # 8-byte Reload
	movq	-48(%rbp), %r14                 # 8-byte Reload
	jmp	.LBB12_32
.LBB12_31:                              # %._crit_edge460.thread
	movq	%rsp, -296(%rbp)                # 8-byte Spill
	xorl	%r12d, %r12d
	leaq	-64(%rbp), %rax
	movq	%rax, -88(%rbp)                 # 8-byte Spill
	movq	%rax, -96(%rbp)                 # 8-byte Spill
	movl	$0, -52(%rbp)                   # 4-byte Folded Spill
.LBB12_32:                              # %._crit_edge465
	movq	-376(%rbp), %rdi
	xorl	%eax, %eax
	movq	%rax, -104(%rbp)                # 8-byte Spill
	xorl	%esi, %esi
	callq	hipEventRecord
	movabsq	$4294967808, %rdi               # imm = 0x100000200
	movl	$1, %esi
	movq	-80(%rbp), %rdx                 # 8-byte Reload
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB12_34
# %bb.33:
	movq	-176(%rbp), %r9
	movl	%r13d, %edi
	movl	%r14d, %esi
	movl	%r14d, %edx
	movl	%r14d, %ecx
	movl	$1, %r8d
	pushq	-112(%rbp)
	pushq	-200(%rbp)
	callq	_Z24__device_stub__multi_veciiiiiPfS_S_
	addq	$16, %rsp
.LBB12_34:
	movq	-368(%rbp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	cmpl	%r14d, %r13d
	jle	.LBB12_39
# %bb.35:                               # %.lr.ph470.preheader
	xorl	%r13d, %r13d
	movq	-120(%rbp), %r15                # 8-byte Reload
                                        # kill: def $r15d killed $r15d killed $r15 def $r15
	xorl	%eax, %eax
	movq	%rax, -104(%rbp)                # 8-byte Spill
.LBB12_36:                              # %.lr.ph470
                                        # =>This Inner Loop Header: Depth=1
	movl	%r15d, %eax
	cltd
	idivl	%ebx
	movl	%eax, %r15d
	leal	511(%r15), %eax
	leal	1022(%r15), %r14d
	testl	%eax, %eax
	cmovnsl	%eax, %r14d
	sarl	$9, %r14d
	movq	-96(%rbp), %rax                 # 8-byte Reload
	movq	(%rax,%r13), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movabsq	$4294967808, %rdi               # imm = 0x100000200
	leaq	(%rdi,%r14), %rdx
	addq	$-512, %rdx                     # imm = 0xFE00
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB12_38
# %bb.37:                               #   in Loop: Header=BB12_36 Depth=1
	movq	-152(%rbp), %rdx
	movq	-176(%rbp), %rcx
	movl	%r15d, %edi
	movl	%ebx, %esi
	callq	_Z28__device_stub__reduction_rowiiPfS_
.LBB12_38:                              #   in Loop: Header=BB12_36 Depth=1
	movq	-104(%rbp), %rax                # 8-byte Reload
	addl	%r15d, %eax
	movq	%rax, -104(%rbp)                # 8-byte Spill
	movq	-88(%rbp), %rax                 # 8-byte Reload
	movq	(%rax,%r13), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	-176(%rbp), %rdi
	movq	-152(%rbp), %rsi
	movslq	%r15d, %rdx
	shlq	$2, %rdx
	movl	$3, %ecx
	callq	hipMemcpy
	movl	$.L.str.35, %esi
	movl	%eax, %edi
	callq	_Z10cuda_check10hipError_tPKc
	addq	$8, %r13
	movq	-48(%rbp), %r14                 # 8-byte Reload
	cmpl	%r14d, %r15d
	jg	.LBB12_36
.LBB12_39:                              # %._crit_edge471
	movl	$.L.str.36, %edi
	movl	-52(%rbp), %esi                 # 4-byte Reload
	movq	-104(%rbp), %rdx                # 8-byte Reload
                                        # kill: def $edx killed $edx killed $rdx
	xorl	%eax, %eax
	callq	printf
	movq	-312(%rbp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movabsq	$4294967808, %r15               # imm = 0x100000200
	movq	%r15, %rdi
	movl	$1, %esi
	movq	-216(%rbp), %rdx                # 8-byte Reload
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB12_41
# %bb.40:
	movq	-72(%rbp), %rsi
	movq	-256(%rbp), %rdx
	movq	-152(%rbp), %rcx
	movl	%r14d, %edi
	callq	_Z21__device_stub__vecdifiPfS_S_
.LBB12_41:
	movq	-304(%rbp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	-360(%rbp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	%r15, %rdi
	movl	$1, %esi
	movq	-80(%rbp), %rdx                 # 8-byte Reload
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	movq	-208(%rbp), %r14                # 8-byte Reload
	movq	-120(%rbp), %r13                # 8-byte Reload
	jne	.LBB12_43
# %bb.42:
	movq	-192(%rbp), %rdx
	movq	-72(%rbp), %rcx
	movq	-48(%rbp), %rdi                 # 8-byte Reload
                                        # kill: def $edi killed $edi killed $rdi
	movl	$1, %esi
	callq	_Z24__device_stub__transposeiiPfS_
.LBB12_43:
	movq	-352(%rbp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	%r15, %rdi
	movl	$1, %esi
	movq	-216(%rbp), %rdx                # 8-byte Reload
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB12_45
# %bb.44:
	movq	-184(%rbp), %r9
	movq	-48(%rbp), %rcx                 # 8-byte Reload
	movl	%ecx, %edi
	movl	$1, %esi
	movl	%ecx, %edx
                                        # kill: def $ecx killed $ecx killed $rcx
	movl	$1, %r8d
	pushq	-72(%rbp)
	pushq	-192(%rbp)
	callq	_Z24__device_stub__multi_veciiiiiPfS_S_
	addq	$16, %rsp
.LBB12_45:
	cmpl	$2, -48(%rbp)                   # 4-byte Folded Reload
	jb	.LBB12_50
# %bb.46:                               # %.lr.ph475.preheader
	movq	-48(%rbp), %r15                 # 8-byte Reload
                                        # kill: def $r15d killed $r15d killed $r15 def $r15
.LBB12_47:                              # %.lr.ph475
                                        # =>This Inner Loop Header: Depth=1
	movl	%r15d, %eax
	xorl	%edx, %edx
	divl	%ebx
	movl	%eax, %r15d
	leal	511(%r15), %eax
	shrl	$9, %eax
	movabsq	$4294967808, %rdi               # imm = 0x100000200
	leaq	(%rdi,%rax), %rdx
	addq	$-512, %rdx                     # imm = 0xFE00
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB12_49
# %bb.48:                               #   in Loop: Header=BB12_47 Depth=1
	movq	-144(%rbp), %rdx
	movq	-184(%rbp), %rcx
	movl	%r15d, %edi
	movl	%ebx, %esi
	callq	_Z28__device_stub__reduction_rowiiPfS_
.LBB12_49:                              #   in Loop: Header=BB12_47 Depth=1
	movq	-184(%rbp), %rdi
	movq	-144(%rbp), %rsi
	movl	%r15d, %edx
	shlq	$2, %rdx
	movl	$3, %ecx
	callq	hipMemcpy
	movl	$.L.str.35, %esi
	movl	%eax, %edi
	callq	_Z10cuda_check10hipError_tPKc
	cmpl	$1, %r15d
	ja	.LBB12_47
.LBB12_50:                              # %._crit_edge476
	movabsq	$4294967808, %rdi               # imm = 0x100000200
	movl	$1, %esi
	movq	-80(%rbp), %rdx                 # 8-byte Reload
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB12_52
# %bb.51:
	movq	-168(%rbp), %r9
	movl	%r13d, %edi
	movl	$1, %esi
	movq	-48(%rbp), %rcx                 # 8-byte Reload
	movl	%ecx, %edx
	movl	%ecx, %r8d
	pushq	-200(%rbp)
	pushq	-192(%rbp)
	callq	_Z24__device_stub__multi_veciiiiiPfS_S_
	addq	$16, %rsp
.LBB12_52:
	cmpl	-48(%rbp), %r13d                # 4-byte Folded Reload
	jle	.LBB12_57
# %bb.53:                               # %.lr.ph479.preheader
	movl	%r13d, %r15d
.LBB12_54:                              # %.lr.ph479
                                        # =>This Inner Loop Header: Depth=1
	movl	%r15d, %eax
	cltd
	idivl	%ebx
	movl	%eax, %r15d
	leal	511(%r15), %eax
	leal	1022(%r15), %ecx
	testl	%eax, %eax
	cmovnsl	%eax, %ecx
	sarl	$9, %ecx
	movabsq	$4294967808, %rdi               # imm = 0x100000200
	leaq	(%rdi,%rcx), %rdx
	addq	$-512, %rdx                     # imm = 0xFE00
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB12_56
# %bb.55:                               #   in Loop: Header=BB12_54 Depth=1
	movq	-136(%rbp), %rdx
	movq	-168(%rbp), %rcx
	movl	%r15d, %edi
	movl	%ebx, %esi
	callq	_Z28__device_stub__reduction_rowiiPfS_
.LBB12_56:                              #   in Loop: Header=BB12_54 Depth=1
	movq	-168(%rbp), %rdi
	movq	-136(%rbp), %rsi
	movslq	%r15d, %rdx
	shlq	$2, %rdx
	movl	$3, %ecx
	callq	hipMemcpy
	movl	$.L.str.35, %esi
	movl	%eax, %edi
	callq	_Z10cuda_check10hipError_tPKc
	cmpl	-48(%rbp), %r15d                # 4-byte Folded Reload
	jg	.LBB12_54
.LBB12_57:                              # %._crit_edge480
	movabsq	$4294967808, %rdi               # imm = 0x100000200
	movl	$1, %esi
	movq	-80(%rbp), %rdx                 # 8-byte Reload
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB12_59
# %bb.58:
	movq	-160(%rbp), %r9
	movl	%r13d, %edi
	movl	$1, %esi
	movq	-48(%rbp), %rcx                 # 8-byte Reload
	movl	%ecx, %edx
                                        # kill: def $ecx killed $ecx killed $rcx
	movl	$1, %r8d
	pushq	-72(%rbp)
	pushq	-136(%rbp)
	callq	_Z24__device_stub__multi_veciiiiiPfS_S_
	addq	$16, %rsp
.LBB12_59:
	cmpl	$2, -48(%rbp)                   # 4-byte Folded Reload
	jb	.LBB12_64
# %bb.60:                               # %.lr.ph483.preheader
	movq	-48(%rbp), %r15                 # 8-byte Reload
                                        # kill: def $r15d killed $r15d killed $r15 def $r15
.LBB12_61:                              # %.lr.ph483
                                        # =>This Inner Loop Header: Depth=1
	movl	%r15d, %eax
	xorl	%edx, %edx
	divl	%ebx
	movl	%eax, %r15d
	leal	511(%r15), %eax
	shrl	$9, %eax
	movabsq	$4294967808, %rdi               # imm = 0x100000200
	leaq	(%rdi,%rax), %rdx
	addq	$-512, %rdx                     # imm = 0xFE00
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB12_63
# %bb.62:                               #   in Loop: Header=BB12_61 Depth=1
	movq	-128(%rbp), %rdx
	movq	-160(%rbp), %rcx
	movl	%r15d, %edi
	movl	%ebx, %esi
	callq	_Z28__device_stub__reduction_rowiiPfS_
.LBB12_63:                              #   in Loop: Header=BB12_61 Depth=1
	movq	-160(%rbp), %rdi
	movq	-128(%rbp), %rsi
	movl	%r15d, %edx
	shlq	$2, %rdx
	movl	$3, %ecx
	callq	hipMemcpy
	movl	$.L.str.35, %esi
	movl	%eax, %edi
	callq	_Z10cuda_check10hipError_tPKc
	cmpl	$1, %r15d
	ja	.LBB12_61
.LBB12_64:                              # %._crit_edge484
	movq	-232(%rbp), %rdi
	movq	-144(%rbp), %rsi
	movl	$4, %edx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	-224(%rbp), %rdi
	movq	-128(%rbp), %rsi
	movl	$4, %edx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	-232(%rbp), %rax
	movss	(%rax), %xmm0                   # xmm0 = mem[0],zero,zero,zero
	movq	-224(%rbp), %rax
	divss	(%rax), %xmm0
	movss	%xmm0, -52(%rbp)                # 4-byte Spill
	cvtss2sd	%xmm0, %xmm0
	movl	$.L.str.37, %edi
	movb	$1, %al
	callq	printf
	movq	-344(%rbp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movabsq	$4294967808, %rbx               # imm = 0x100000200
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	-216(%rbp), %rdx                # 8-byte Reload
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB12_66
# %bb.65:
	movq	-240(%rbp), %rdi
	movq	-72(%rbp), %rsi
	movss	-52(%rbp), %xmm0                # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	callq	_Z29__device_stub__scalareMatricePffS_
.LBB12_66:
	movq	-336(%rbp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	-328(%rbp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	-80(%rbp), %rdx                 # 8-byte Reload
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB12_68
# %bb.67:
	movq	-112(%rbp), %rdx
	movq	-240(%rbp), %rcx
	movl	%r13d, %edi
	movq	%rdx, %rsi
	callq	_Z21__device_stub__vecsumiPfS_S_
.LBB12_68:
	movq	-320(%rbp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	-248(%rbp), %rdi
	movq	-112(%rbp), %rsi
	movq	%r14, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$.L.str.38, %esi
	movl	%eax, %edi
	callq	_Z10cuda_check10hipError_tPKc
	movq	-248(%rbp), %rdi
	movq	-48(%rbp), %rbx                 # 8-byte Reload
	movl	%ebx, %esi
	callq	_Z6stampaPfi
	movq	-400(%rbp), %rsi
	movq	-384(%rbp), %rdx
	leaq	-284(%rbp), %rdi
	callq	hipEventElapsedTime
	movl	$.L.str.39, %esi
	movl	%eax, %edi
	callq	_Z10cuda_check10hipError_tPKc
	movq	-376(%rbp), %rsi
	movq	-368(%rbp), %rdx
	leaq	-280(%rbp), %rdi
	callq	hipEventElapsedTime
	movl	$.L.str.40, %esi
	movl	%eax, %edi
	callq	_Z10cuda_check10hipError_tPKc
	xorps	%xmm0, %xmm0
	cmpl	%ebx, %r13d
	movq	-96(%rbp), %r14                 # 8-byte Reload
	movq	-88(%rbp), %r13                 # 8-byte Reload
	jle	.LBB12_71
# %bb.69:                               # %.lr.ph488.preheader
	xorl	%r15d, %r15d
	leaq	-276(%rbp), %rbx
.LBB12_70:                              # %.lr.ph488
                                        # =>This Inner Loop Header: Depth=1
	movss	%xmm0, -48(%rbp)                # 4-byte Spill
	movq	(%r14,%r15,8), %rsi
	movq	(%r13,%r15,8), %rdx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	movl	$.L.str.41, %esi
	movl	%eax, %edi
	callq	_Z10cuda_check10hipError_tPKc
	movss	-48(%rbp), %xmm0                # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	addss	-276(%rbp), %xmm0
	incq	%r15
	cmpq	%r15, %r12
	jne	.LBB12_70
.LBB12_71:                              # %.critedge
	movss	%xmm0, -48(%rbp)                # 4-byte Spill
	movq	-360(%rbp), %rsi
	movq	-352(%rbp), %rdx
	leaq	-272(%rbp), %rdi
	callq	hipEventElapsedTime
	movl	$.L.str.42, %esi
	movl	%eax, %edi
	callq	_Z10cuda_check10hipError_tPKc
	movq	-344(%rbp), %rsi
	movq	-336(%rbp), %rdx
	leaq	-268(%rbp), %rdi
	callq	hipEventElapsedTime
	movl	$.L.str.43, %esi
	movl	%eax, %edi
	callq	_Z10cuda_check10hipError_tPKc
	movq	-312(%rbp), %rsi
	movq	-304(%rbp), %rdx
	leaq	-264(%rbp), %rdi
	callq	hipEventElapsedTime
	movl	$.L.str.44, %esi
	movl	%eax, %edi
	callq	_Z10cuda_check10hipError_tPKc
	movq	-328(%rbp), %rsi
	movq	-320(%rbp), %rdx
	leaq	-260(%rbp), %rdi
	callq	hipEventElapsedTime
	movl	$.L.str.45, %esi
	movl	%eax, %edi
	callq	_Z10cuda_check10hipError_tPKc
	movss	-284(%rbp), %xmm2               # xmm2 = mem[0],zero,zero,zero
	xorps	%xmm0, %xmm0
	cvtss2sd	%xmm2, %xmm0
	cvtsi2ssl	-120(%rbp), %xmm1       # 4-byte Folded Reload
	movss	%xmm1, -96(%rbp)                # 4-byte Spill
	divss	%xmm2, %xmm1
	cvtss2sd	%xmm1, %xmm1
	movsd	.LCPI12_5(%rip), %xmm4          # xmm4 = mem[0],zero
	divsd	%xmm4, %xmm1
	cvtsi2ssq	-392(%rbp), %xmm3       # 8-byte Folded Reload
	movss	%xmm3, -88(%rbp)                # 4-byte Spill
	divss	%xmm2, %xmm3
	xorps	%xmm2, %xmm2
	cvtss2sd	%xmm3, %xmm2
	divsd	%xmm4, %xmm2
	movl	$.L.str.46, %edi
	movb	$3, %al
	callq	printf
	movss	-280(%rbp), %xmm2               # xmm2 = mem[0],zero,zero,zero
	xorps	%xmm0, %xmm0
	cvtss2sd	%xmm2, %xmm0
	movss	-96(%rbp), %xmm1                # 4-byte Reload
                                        # xmm1 = mem[0],zero,zero,zero
	divss	%xmm2, %xmm1
	cvtss2sd	%xmm1, %xmm1
	movsd	.LCPI12_5(%rip), %xmm3          # xmm3 = mem[0],zero
	divsd	%xmm3, %xmm1
	movss	-88(%rbp), %xmm4                # 4-byte Reload
                                        # xmm4 = mem[0],zero,zero,zero
	divss	%xmm2, %xmm4
	xorps	%xmm2, %xmm2
	cvtss2sd	%xmm4, %xmm2
	divsd	%xmm3, %xmm2
	movl	$.L.str.47, %edi
	movb	$3, %al
	callq	printf
	movss	-48(%rbp), %xmm3                # 4-byte Reload
                                        # xmm3 = mem[0],zero,zero,zero
	movq	-104(%rbp), %rax                # 8-byte Reload
	xorps	%xmm1, %xmm1
	cvtsi2ss	%eax, %xmm1
	xorps	%xmm0, %xmm0
	cvtss2sd	%xmm3, %xmm0
	divss	%xmm3, %xmm1
	cvtss2sd	%xmm1, %xmm1
	movsd	.LCPI12_5(%rip), %xmm2          # xmm2 = mem[0],zero
	movapd	%xmm2, %xmm4
	divsd	%xmm2, %xmm1
	cltq
	shlq	$2, %rax
	testq	%rax, %rax
	js	.LBB12_72
# %bb.74:                               # %.critedge
	xorps	%xmm2, %xmm2
	cvtsi2ss	%rax, %xmm2
	jmp	.LBB12_75
.LBB12_72:
	shrq	%rax
	xorps	%xmm2, %xmm2
	cvtsi2ss	%rax, %xmm2
	addss	%xmm2, %xmm2
.LBB12_75:                              # %.critedge
	movq	-208(%rbp), %rbx                # 8-byte Reload
	divss	%xmm3, %xmm2
	cvtss2sd	%xmm2, %xmm2
	divsd	%xmm4, %xmm2
	movl	$.L.str.48, %edi
	movb	$3, %al
	callq	printf
	movss	-272(%rbp), %xmm2               # xmm2 = mem[0],zero,zero,zero
	xorps	%xmm0, %xmm0
	cvtss2sd	%xmm2, %xmm0
	movss	-56(%rbp), %xmm1                # 4-byte Reload
                                        # xmm1 = mem[0],zero,zero,zero
	divss	%xmm2, %xmm1
	cvtss2sd	%xmm1, %xmm1
	movsd	.LCPI12_5(%rip), %xmm4          # xmm4 = mem[0],zero
	divsd	%xmm4, %xmm1
	xorps	%xmm3, %xmm3
	cvtsi2ss	%rbx, %xmm3
	movss	%xmm3, -48(%rbp)                # 4-byte Spill
	divss	%xmm2, %xmm3
	xorps	%xmm2, %xmm2
	cvtss2sd	%xmm3, %xmm2
	divsd	%xmm4, %xmm2
	movl	$.L.str.49, %edi
	movb	$3, %al
	callq	printf
	movss	-268(%rbp), %xmm2               # xmm2 = mem[0],zero,zero,zero
	xorps	%xmm0, %xmm0
	cvtss2sd	%xmm2, %xmm0
	movss	-56(%rbp), %xmm1                # 4-byte Reload
                                        # xmm1 = mem[0],zero,zero,zero
	divss	%xmm2, %xmm1
	cvtss2sd	%xmm1, %xmm1
	movsd	.LCPI12_5(%rip), %xmm4          # xmm4 = mem[0],zero
	divsd	%xmm4, %xmm1
	movss	-48(%rbp), %xmm3                # 4-byte Reload
                                        # xmm3 = mem[0],zero,zero,zero
	divss	%xmm2, %xmm3
	xorps	%xmm2, %xmm2
	cvtss2sd	%xmm3, %xmm2
	divsd	%xmm4, %xmm2
	movl	$.L.str.50, %edi
	movb	$3, %al
	callq	printf
	movss	-264(%rbp), %xmm2               # xmm2 = mem[0],zero,zero,zero
	xorps	%xmm0, %xmm0
	cvtss2sd	%xmm2, %xmm0
	movss	-56(%rbp), %xmm1                # 4-byte Reload
                                        # xmm1 = mem[0],zero,zero,zero
	divss	%xmm2, %xmm1
	cvtss2sd	%xmm1, %xmm1
	movsd	.LCPI12_5(%rip), %xmm4          # xmm4 = mem[0],zero
	divsd	%xmm4, %xmm1
	movss	-48(%rbp), %xmm3                # 4-byte Reload
                                        # xmm3 = mem[0],zero,zero,zero
	divss	%xmm2, %xmm3
	xorps	%xmm2, %xmm2
	cvtss2sd	%xmm3, %xmm2
	divsd	%xmm4, %xmm2
	movl	$.L.str.51, %edi
	movb	$3, %al
	callq	printf
	movss	-260(%rbp), %xmm2               # xmm2 = mem[0],zero,zero,zero
	xorps	%xmm0, %xmm0
	cvtss2sd	%xmm2, %xmm0
	movss	-56(%rbp), %xmm1                # 4-byte Reload
                                        # xmm1 = mem[0],zero,zero,zero
	divss	%xmm2, %xmm1
	cvtss2sd	%xmm1, %xmm1
	movsd	.LCPI12_5(%rip), %xmm4          # xmm4 = mem[0],zero
	divsd	%xmm4, %xmm1
	movss	-48(%rbp), %xmm3                # 4-byte Reload
                                        # xmm3 = mem[0],zero,zero,zero
	divss	%xmm2, %xmm3
	xorps	%xmm2, %xmm2
	cvtss2sd	%xmm3, %xmm2
	divsd	%xmm4, %xmm2
	movl	$.L.str.52, %edi
	movb	$3, %al
	callq	printf
	movq	-200(%rbp), %rdi
	callq	hipFree
	movq	-248(%rbp), %rdi
	callq	hipHostFree
	movq	-176(%rbp), %rdi
	callq	hipFree
	movq	-168(%rbp), %rdi
	callq	hipFree
	movq	-72(%rbp), %rdi
	callq	hipFree
	movq	-192(%rbp), %rdi
	callq	hipFree
	movq	-184(%rbp), %rdi
	callq	hipFree
	movq	-160(%rbp), %rdi
	callq	hipFree
	movq	-152(%rbp), %rdi
	callq	hipFree
	movq	-144(%rbp), %rdi
	callq	hipFree
	movq	-136(%rbp), %rdi
	callq	hipFree
	movq	-128(%rbp), %rdi
	callq	hipFree
	movq	-240(%rbp), %rdi
	callq	hipFree
	movq	-256(%rbp), %rdi
	callq	hipFree
	movq	-112(%rbp), %rdi
	callq	hipFree
	movq	-232(%rbp), %rdi
	callq	hipHostFree
	movq	-224(%rbp), %rdi
	callq	hipHostFree
	movq	-296(%rbp), %rsp                # 8-byte Reload
	xorl	%eax, %eax
	leaq	-40(%rbp), %rsp
	popq	%rbx
	popq	%r12
	popq	%r13
	popq	%r14
	popq	%r15
	popq	%rbp
	.cfi_def_cfa %rsp, 8
	retq
.LBB12_1:
	.cfi_def_cfa %rbp, 16
	movq	stderr(%rip), %rdi
	movl	$.L.str, %esi
	movl	$.L.str.4, %edx
	jmp	.LBB12_2
.LBB12_4:
	movq	stderr(%rip), %rdi
	movl	$.L.str, %esi
	movl	$.L.str.5, %edx
.LBB12_2:
	xorl	%eax, %eax
	callq	fprintf
	movl	$1, %edi
	callq	exit
.LBB12_73:
	movl	$.L.str.32, %edi
	xorl	%eax, %eax
	callq	printf
	xorl	%edi, %edi
	callq	exit
.Lfunc_end12:
	.size	main, .Lfunc_end12-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB13_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB13_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8init_veciPf, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10multi_vec2iiiiiPfS_S_, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9multi_veciiiiiPfS_S_, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z14scalareMatricePffS_, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z13reduction_rowiiPfS_, %esi
	movl	$.L__unnamed_5, %edx
	movl	$.L__unnamed_5, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9transposeiiPfS_, %esi
	movl	$.L__unnamed_6, %edx
	movl	$.L__unnamed_6, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6vecsumiPfS_S_, %esi
	movl	$.L__unnamed_7, %edx
	movl	$.L__unnamed_7, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6vecdifiPfS_S_, %esi
	movl	$.L__unnamed_8, %edx
	movl	$.L__unnamed_8, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end13:
	.size	__hip_module_ctor, .Lfunc_end13-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB14_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB14_2:
	retq
.Lfunc_end14:
	.size	__hip_module_dtor, .Lfunc_end14-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"%s\n"
	.size	.L.str, 4

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"%s: CUDA error %d (%s)\n"
	.size	.L.str.1, 24

	.type	_Z8init_veciPf,@object          # @_Z8init_veciPf
	.section	.rodata,"a",@progbits
	.globl	_Z8init_veciPf
	.p2align	3, 0x0
_Z8init_veciPf:
	.quad	_Z23__device_stub__init_veciPf
	.size	_Z8init_veciPf, 8

	.type	_Z10multi_vec2iiiiiPfS_S_,@object # @_Z10multi_vec2iiiiiPfS_S_
	.globl	_Z10multi_vec2iiiiiPfS_S_
	.p2align	3, 0x0
_Z10multi_vec2iiiiiPfS_S_:
	.quad	_Z25__device_stub__multi_vec2iiiiiPfS_S_
	.size	_Z10multi_vec2iiiiiPfS_S_, 8

	.type	_Z9multi_veciiiiiPfS_S_,@object # @_Z9multi_veciiiiiPfS_S_
	.globl	_Z9multi_veciiiiiPfS_S_
	.p2align	3, 0x0
_Z9multi_veciiiiiPfS_S_:
	.quad	_Z24__device_stub__multi_veciiiiiPfS_S_
	.size	_Z9multi_veciiiiiPfS_S_, 8

	.type	_Z14scalareMatricePffS_,@object # @_Z14scalareMatricePffS_
	.globl	_Z14scalareMatricePffS_
	.p2align	3, 0x0
_Z14scalareMatricePffS_:
	.quad	_Z29__device_stub__scalareMatricePffS_
	.size	_Z14scalareMatricePffS_, 8

	.type	_Z13reduction_rowiiPfS_,@object # @_Z13reduction_rowiiPfS_
	.globl	_Z13reduction_rowiiPfS_
	.p2align	3, 0x0
_Z13reduction_rowiiPfS_:
	.quad	_Z28__device_stub__reduction_rowiiPfS_
	.size	_Z13reduction_rowiiPfS_, 8

	.type	_Z9transposeiiPfS_,@object      # @_Z9transposeiiPfS_
	.globl	_Z9transposeiiPfS_
	.p2align	3, 0x0
_Z9transposeiiPfS_:
	.quad	_Z24__device_stub__transposeiiPfS_
	.size	_Z9transposeiiPfS_, 8

	.type	_Z6vecsumiPfS_S_,@object        # @_Z6vecsumiPfS_S_
	.globl	_Z6vecsumiPfS_S_
	.p2align	3, 0x0
_Z6vecsumiPfS_S_:
	.quad	_Z21__device_stub__vecsumiPfS_S_
	.size	_Z6vecsumiPfS_S_, 8

	.type	_Z6vecdifiPfS_S_,@object        # @_Z6vecdifiPfS_S_
	.globl	_Z6vecdifiPfS_S_
	.p2align	3, 0x0
_Z6vecdifiPfS_S_:
	.quad	_Z21__device_stub__vecdifiPfS_S_
	.size	_Z6vecdifiPfS_S_, 8

	.type	.L.str.3,@object                # @.str.3
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.3:
	.asciz	"%f  "
	.size	.L.str.3, 5

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"syntax: vecsum nels v"
	.size	.L.str.4, 22

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"N < 0"
	.size	.L.str.5, 6

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"alloc matriceA"
	.size	.L.str.6, 15

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"alloc matriceB"
	.size	.L.str.7, 15

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"alloc matriceX"
	.size	.L.str.8, 15

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"alloc matrice"
	.size	.L.str.9, 14

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"alloc somma"
	.size	.L.str.10, 12

	.type	.L.str.11,@object               # @.str.11
.L.str.11:
	.asciz	"alloc res"
	.size	.L.str.11, 10

	.type	.L.str.12,@object               # @.str.12
.L.str.12:
	.asciz	"alloc res0"
	.size	.L.str.12, 11

	.type	.L.str.13,@object               # @.str.13
.L.str.13:
	.asciz	"alloc prodotto"
	.size	.L.str.13, 15

	.type	.L.str.14,@object               # @.str.14
.L.str.14:
	.asciz	"alloc res1"
	.size	.L.str.14, 11

	.type	.L.str.15,@object               # @.str.15
.L.str.15:
	.asciz	"alloc res2"
	.size	.L.str.15, 11

	.type	.L.str.16,@object               # @.str.16
.L.str.16:
	.asciz	"alloc pk"
	.size	.L.str.16, 9

	.type	.L.str.17,@object               # @.str.17
.L.str.17:
	.asciz	"alloc trasposta\t"
	.size	.L.str.17, 17

	.type	.L.str.18,@object               # @.str.18
.L.str.18:
	.asciz	"alloc den"
	.size	.L.str.18, 10

	.type	.L.str.19,@object               # @.str.19
.L.str.19:
	.asciz	"alloc scalar"
	.size	.L.str.19, 13

	.type	.L.str.20,@object               # @.str.20
.L.str.20:
	.asciz	"create pre_init"
	.size	.L.str.20, 16

	.type	.L.str.21,@object               # @.str.21
.L.str.21:
	.asciz	"create pre_sum"
	.size	.L.str.21, 15

	.type	.L.str.22,@object               # @.str.22
.L.str.22:
	.asciz	"create pre_traspose"
	.size	.L.str.22, 20

	.type	.L.str.23,@object               # @.str.23
.L.str.23:
	.asciz	"create pre_scalar_matrice"
	.size	.L.str.23, 26

	.type	.L.str.24,@object               # @.str.24
.L.str.24:
	.asciz	"create pre_vecdif"
	.size	.L.str.24, 18

	.type	.L.str.25,@object               # @.str.25
.L.str.25:
	.asciz	"create pre_vecsum"
	.size	.L.str.25, 18

	.type	.L.str.26,@object               # @.str.26
.L.str.26:
	.asciz	"create post_init"
	.size	.L.str.26, 17

	.type	.L.str.27,@object               # @.str.27
.L.str.27:
	.asciz	"create post_sum"
	.size	.L.str.27, 16

	.type	.L.str.28,@object               # @.str.28
.L.str.28:
	.asciz	"create post_traspose"
	.size	.L.str.28, 21

	.type	.L.str.29,@object               # @.str.29
.L.str.29:
	.asciz	"create post_scalar_matrice"
	.size	.L.str.29, 27

	.type	.L.str.30,@object               # @.str.30
.L.str.30:
	.asciz	"create post_vecdif"
	.size	.L.str.30, 19

	.type	.L.str.31,@object               # @.str.31
.L.str.31:
	.asciz	"create post_vecsum"
	.size	.L.str.31, 19

	.type	.L.str.32,@object               # @.str.32
.L.str.32:
	.asciz	"Errore N deve essere una potenza di 4,8,12,16"
	.size	.L.str.32, 46

	.type	.L.str.33,@object               # @.str.33
.L.str.33:
	.asciz	"create pre_red"
	.size	.L.str.33, 15

	.type	.L.str.34,@object               # @.str.34
.L.str.34:
	.asciz	"create post_red"
	.size	.L.str.34, 16

	.type	.L.str.35,@object               # @.str.35
.L.str.35:
	.asciz	"cpy"
	.size	.L.str.35, 4

	.type	.L.str.36,@object               # @.str.36
.L.str.36:
	.asciz	"%d %d\n"
	.size	.L.str.36, 7

	.type	.L.str.37,@object               # @.str.37
.L.str.37:
	.asciz	"%f\n"
	.size	.L.str.37, 4

	.type	.L.str.38,@object               # @.str.38
.L.str.38:
	.asciz	"create mem"
	.size	.L.str.38, 11

	.type	.L.str.39,@object               # @.str.39
.L.str.39:
	.asciz	"elapsed time init"
	.size	.L.str.39, 18

	.type	.L.str.40,@object               # @.str.40
.L.str.40:
	.asciz	"elapsed time prodotto"
	.size	.L.str.40, 22

	.type	.L.str.41,@object               # @.str.41
.L.str.41:
	.asciz	"elapsed time reduction"
	.size	.L.str.41, 23

	.type	.L.str.42,@object               # @.str.42
.L.str.42:
	.asciz	"elapsed time traspose"
	.size	.L.str.42, 22

	.type	.L.str.43,@object               # @.str.43
.L.str.43:
	.asciz	"elapsed time scalar_matrice"
	.size	.L.str.43, 28

	.type	.L.str.44,@object               # @.str.44
.L.str.44:
	.asciz	"elapsed time vecdif"
	.size	.L.str.44, 20

	.type	.L.str.45,@object               # @.str.45
.L.str.45:
	.asciz	"elapsed time vecsum"
	.size	.L.str.45, 20

	.type	.L.str.46,@object               # @.str.46
.L.str.46:
	.asciz	"init: runtime %.4gms, %.4g GE/s, %.4g GB/s\n"
	.size	.L.str.46, 44

	.type	.L.str.47,@object               # @.str.47
.L.str.47:
	.asciz	"prodotto: runtime %.4gms, %.4g GE/s, %.4g GB/s\n"
	.size	.L.str.47, 48

	.type	.L.str.48,@object               # @.str.48
.L.str.48:
	.asciz	"reduction: runtime %.4gms, %.4g GE/s, %.4g GB/s\n"
	.size	.L.str.48, 49

	.type	.L.str.49,@object               # @.str.49
.L.str.49:
	.asciz	"transpose: runtime %.4gms, %.4g GE/s, %.4g GB/s\n"
	.size	.L.str.49, 49

	.type	.L.str.50,@object               # @.str.50
.L.str.50:
	.asciz	"scalareMatrice: runtime %.4gms, %.4g GE/s, %.4g GB/s\n"
	.size	.L.str.50, 54

	.type	.L.str.51,@object               # @.str.51
.L.str.51:
	.asciz	"vecdif: runtime %.4gms, %.4g GE/s, %.4g GB/s\n"
	.size	.L.str.51, 46

	.type	.L.str.52,@object               # @.str.52
.L.str.52:
	.asciz	"vecsum: runtime %.4gms, %.4g GE/s, %.4g GB/s\n"
	.size	.L.str.52, 46

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z8init_veciPf"
	.size	.L__unnamed_1, 15

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z10multi_vec2iiiiiPfS_S_"
	.size	.L__unnamed_2, 26

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z9multi_veciiiiiPfS_S_"
	.size	.L__unnamed_3, 24

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z14scalareMatricePffS_"
	.size	.L__unnamed_4, 24

	.type	.L__unnamed_5,@object           # @4
.L__unnamed_5:
	.asciz	"_Z13reduction_rowiiPfS_"
	.size	.L__unnamed_5, 24

	.type	.L__unnamed_6,@object           # @5
.L__unnamed_6:
	.asciz	"_Z9transposeiiPfS_"
	.size	.L__unnamed_6, 19

	.type	.L__unnamed_7,@object           # @6
.L__unnamed_7:
	.asciz	"_Z6vecsumiPfS_S_"
	.size	.L__unnamed_7, 17

	.type	.L__unnamed_8,@object           # @7
.L__unnamed_8:
	.asciz	"_Z6vecdifiPfS_S_"
	.size	.L__unnamed_8, 17

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z23__device_stub__init_veciPf
	.addrsig_sym _Z25__device_stub__multi_vec2iiiiiPfS_S_
	.addrsig_sym _Z24__device_stub__multi_veciiiiiPfS_S_
	.addrsig_sym _Z29__device_stub__scalareMatricePffS_
	.addrsig_sym _Z28__device_stub__reduction_rowiiPfS_
	.addrsig_sym _Z24__device_stub__transposeiiPfS_
	.addrsig_sym _Z21__device_stub__vecsumiPfS_S_
	.addrsig_sym _Z21__device_stub__vecdifiPfS_S_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z8init_veciPf
	.addrsig_sym _Z10multi_vec2iiiiiPfS_S_
	.addrsig_sym _Z9multi_veciiiiiPfS_S_
	.addrsig_sym _Z14scalareMatricePffS_
	.addrsig_sym _Z13reduction_rowiiPfS_
	.addrsig_sym _Z9transposeiiPfS_
	.addrsig_sym _Z6vecsumiPfS_S_
	.addrsig_sym _Z6vecdifiPfS_S_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z8init_veciPf          ; -- Begin function _Z8init_veciPf
	.globl	_Z8init_veciPf
	.p2align	8
	.type	_Z8init_veciPf,@function
_Z8init_veciPf:                         ; @_Z8init_veciPf
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x1c
	s_load_b64 s[0:1], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	v_ashrrev_i32_e32 v2, 31, v1
	v_cvt_f32_i32_e32 v4, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	v_add_co_u32 v0, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
	global_store_b32 v[0:1], v4, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8init_veciPf
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 5
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z8init_veciPf, .Lfunc_end0-_Z8init_veciPf
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 100
; NumSgprs: 18
; NumVgprs: 5
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 5
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z10multi_vec2iiiiiPfS_S_ ; -- Begin function _Z10multi_vec2iiiiiPfS_S_
	.globl	_Z10multi_vec2iiiiiPfS_S_
	.p2align	8
	.type	_Z10multi_vec2iiiiiPfS_S_,@function
_Z10multi_vec2iiiiiPfS_S_:              ; @_Z10multi_vec2iiiiiPfS_S_
; %bb.0:
	s_clause 0x1
	s_load_b32 s8, s[0:1], 0x3c
	s_load_b128 s[4:7], s[0:1], 0x4
	s_add_u32 s2, s0, 48
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s8, s8, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[28:29], null, s15, s8, v[0:1]
	s_mul_i32 s8, s7, s6
	s_mul_i32 s9, s8, s4
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s9, v28
	s_and_saveexec_b32 s9, vcc_lo
	s_cbranch_execz .LBB1_198
; %bb.1:
	s_ashr_i32 s9, s8, 31
	v_ashrrev_i32_e32 v29, 31, v28
	s_add_i32 s10, s8, s9
	s_ashr_i32 s13, s5, 31
	s_xor_b32 s10, s10, s9
	s_add_i32 s5, s5, s13
	v_cvt_f32_u32_e32 v0, s10
	s_sub_i32 s11, 0, s10
	v_add_nc_u32_e32 v2, v28, v29
	v_xor_b32_e32 v5, s9, v29
	s_xor_b32 s5, s5, s13
	v_rcp_iflag_f32_e32 v0, v0
	v_mbcnt_lo_u32_b32 v30, -1, 0
	v_xor_b32_e32 v2, v2, v29
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_mul_lo_u32 v1, s11, v0
	s_ashr_i32 s11, s6, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s12, s6, s11
	s_xor_b32 s12, s12, s11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v1, v0, v1
	v_add_nc_u32_e32 v0, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v0, v2, v0
	v_mul_lo_u32 v1, v0, s10
	v_add_nc_u32_e32 v3, 1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v1, v2, v1
	v_subrev_nc_u32_e32 v4, s10, v1
	v_cmp_le_u32_e32 vcc_lo, s10, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v0, v0, v3 :: v_dual_cndmask_b32 v1, v1, v4
	v_cvt_f32_u32_e32 v4, s12
	v_add_nc_u32_e32 v3, 1, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s10, v1
	v_rcp_iflag_f32_e32 v1, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v0, v0, v3, vcc_lo
	v_cvt_f32_u32_e32 v3, s5
	v_xor_b32_e32 v0, v0, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v3, v3
	v_sub_nc_u32_e32 v4, v0, v5
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v1
	v_mul_lo_u32 v1, v4, s8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v0, v0
	s_sub_i32 s8, 0, s12
	v_mul_f32_e32 v3, 0x4f7ffffe, v3
	v_mul_lo_u32 v5, s8, v0
	s_sub_i32 s8, 0, s5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v6, v28, v1
	v_cvt_u32_f32_e32 v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_ashrrev_i32_e32 v3, 31, v6
	v_mul_hi_u32 v5, v0, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v7, s8, v1
	v_add_nc_u32_e32 v8, v6, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v0, v0, v5
	v_xor_b32_e32 v5, v8, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v7, v1, v7
	v_xor_b32_e32 v3, s11, v3
	s_load_b128 s[8:11], s[0:1], 0x20
	v_mul_hi_u32 v0, v5, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v1, v7
	v_mul_lo_u32 v7, v0, s12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v1, v2, v1
	v_sub_nc_u32_e32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v1, v1, s5
	v_add_nc_u32_e32 v7, 1, v0
	v_subrev_nc_u32_e32 v8, s12, v5
	v_cmp_le_u32_e32 vcc_lo, s12, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v1, v2, v1
	v_cndmask_b32_e32 v0, v0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v2, v5, v8, vcc_lo
	v_subrev_nc_u32_e32 v7, s5, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v5, 1, v0
	v_cmp_le_u32_e32 vcc_lo, s12, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v0, v0, v5, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s5, v1
	v_xor_b32_e32 v0, v0, v3
	v_cndmask_b32_e32 v1, v1, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v0, v0, v3
	v_subrev_nc_u32_e32 v2, s5, v1
	v_cmp_le_u32_e32 vcc_lo, s5, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v1, v1, v2, vcc_lo
	v_mul_lo_u32 v2, v0, s6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v1, v1, v29
	v_sub_nc_u32_e32 v6, v6, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v1, v1, v29
	v_mad_u64_u32 v[2:3], null, v4, s4, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[4:5], null, v6, s7, v[0:1]
	v_mov_b32_e32 v6, 0
	v_mov_b32_e32 v7, 0
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[2:3], 2, v[4:5]
	v_mov_b32_e32 v4, v30
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s8, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	v_add_co_u32 v2, vcc_lo, s10, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s11, v3, vcc_lo
	global_load_b32 v33, v[0:1], off
	global_load_b32 v34, v[2:3], off
	s_load_b64 s[4:5], s[2:3], 0x50
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s2, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s2, s2, v4
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_7
; %bb.2:
	v_mov_b32_e32 v0, 0
	s_mov_b32 s6, exec_lo
	s_waitcnt lgkmcnt(0)
	global_load_b64 v[8:9], v0, s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[1:2], v0, s[4:5] offset:40
	global_load_b64 v[5:6], v0, s[4:5]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v8
	v_and_b32_e32 v2, v2, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v3, v1, 24
	v_mul_lo_u32 v2, v2, 24
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v2, v3, v2
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v5, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, v6, v2, vcc_lo
	global_load_b64 v[6:7], v[1:2], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[6:7], v[8:9]
	s_cbranch_execz .LBB1_6
; %bb.3:                                ; %.preheader3.i.i.i.preheader
	s_mov_b32 s7, 0
.LBB1_4:                                ; %.preheader3.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[1:2], v0, s[4:5] offset:40
	global_load_b64 v[10:11], v0, s[4:5]
	v_dual_mov_b32 v9, v7 :: v_dual_mov_b32 v8, v6
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v1, v1, v8
	v_and_b32_e32 v7, v2, v9
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v1, 24, v[10:11]
	v_mov_b32_e32 v1, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, v7, 24, v[1:2]
	v_mov_b32_e32 v6, v2
	global_load_b64 v[6:7], v[5:6], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[6:7], v0, v[6:9], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[8:9]
	s_or_b32 s7, vcc_lo, s7
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s7
	s_cbranch_execnz .LBB1_4
; %bb.5:                                ; %Flow406
	s_or_b32 exec_lo, exec_lo, s7
.LBB1_6:                                ; %Flow408
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s6
.LBB1_7:                                ; %.loopexit4.i.i.i
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
	v_mov_b32_e32 v5, 0
	v_readfirstlane_b32 s8, v6
	v_readfirstlane_b32 s9, v7
	s_mov_b32 s12, exec_lo
	s_waitcnt lgkmcnt(0)
	s_clause 0x1
	global_load_b64 v[8:9], v5, s[4:5] offset:40
	global_load_b128 v[0:3], v5, s[4:5]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s6, v8
	v_readfirstlane_b32 s7, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[6:7], s[8:9], s[6:7]
	s_mul_i32 s3, s7, 24
	s_mul_hi_u32 s10, s6, 24
	s_mul_i32 s11, s6, 24
	s_and_saveexec_b32 s13, s2
	s_cbranch_execz .LBB1_9
; %bb.8:
	v_dual_mov_b32 v6, s12 :: v_dual_mov_b32 v7, v5
	s_add_i32 s12, s10, s3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v10, vcc_lo, v0, s11
	v_add_co_ci_u32_e32 v11, vcc_lo, s12, v1, vcc_lo
	v_dual_mov_b32 v8, 2 :: v_dual_mov_b32 v9, 1
	global_store_b128 v[10:11], v[6:9], off offset:8
.LBB1_9:
	s_or_b32 exec_lo, exec_lo, s13
	s_lshl_b64 s[6:7], s[6:7], 12
	v_lshlrev_b64 v[6:7], 6, v[4:5]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v2, s6
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	s_load_b64 s[6:7], s[0:1], 0x18
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v2, v6
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_add_co_ci_u32_e32 v9, vcc_lo, v3, v7, vcc_lo
	v_dual_mov_b32 v4, 33 :: v_dual_mov_b32 v7, v5
	v_mov_b32_e32 v6, v5
	v_dual_mov_b32 v10, s12 :: v_dual_mov_b32 v13, s15
	v_dual_mov_b32 v11, s13 :: v_dual_mov_b32 v12, s14
	s_clause 0x3
	global_store_b128 v[8:9], v[4:7], off
	global_store_b128 v[8:9], v[10:13], off offset:16
	global_store_b128 v[8:9], v[10:13], off offset:32
	global_store_b128 v[8:9], v[10:13], off offset:48
	s_and_saveexec_b32 s0, s2
	s_cbranch_execz .LBB1_16
; %bb.10:
	v_mov_b32_e32 v10, 0
	s_mov_b32 s1, exec_lo
	s_clause 0x1
	global_load_b64 v[13:14], v10, s[4:5] offset:32 glc
	global_load_b64 v[2:3], v10, s[4:5] offset:40
	v_dual_mov_b32 v11, s8 :: v_dual_mov_b32 v12, s9
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v3, s9, v3
	v_and_b32_e32 v2, s8, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v4, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v4, v3
	v_add_co_u32 v6, vcc_lo, v0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, v1, v3, vcc_lo
	global_store_b64 v[6:7], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v10, v[11:14], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[13:14]
	s_cbranch_execz .LBB1_12
.LBB1_11:                               ; %.preheader1.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v3, s9
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v10, v[2:5], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s12, vcc_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB1_11
.LBB1_12:                               ; %Flow404
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v5, 0
	s_mov_b32 s12, exec_lo
	s_mov_b32 s1, exec_lo
	v_mbcnt_lo_u32_b32 v4, s12, 0
	global_load_b64 v[2:3], v5, s[4:5] offset:16
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB1_14
; %bb.13:
	s_bcnt1_i32_b32 s12, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v4, s12
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[4:5], off offset:8
.LBB1_14:
	s_or_b32 exec_lo, exec_lo, s1
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB1_16
; %bb.15:
	global_load_b32 v2, v[2:3], off offset:24
	v_mov_b32_e32 v3, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s1, v2
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[2:3], off
	s_and_b32 m0, s1, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_16:                               ; %Flow405
	s_or_b32 exec_lo, exec_lo, s0
	s_add_i32 s10, s10, s3
	v_add_co_u32 v0, vcc_lo, v0, s11
	v_add_co_ci_u32_e32 v1, vcc_lo, s10, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_17:                               ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s0, s2
	s_cbranch_execz .LBB1_19
; %bb.18:                               ;   in Loop: Header=BB1_17 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_19:                               ;   in Loop: Header=BB1_17 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v2
	s_cmp_eq_u32 s0, 0
	s_cbranch_scc1 .LBB1_21
; %bb.20:                               ;   in Loop: Header=BB1_17 Depth=1
	s_mov_b32 s0, 0
	s_sleep 1
	s_branch .LBB1_22
.LBB1_21:                               ;   in Loop: Header=BB1_17 Depth=1
	s_mov_b32 s0, -1
.LBB1_22:                               ; %Flow399
                                        ;   in Loop: Header=BB1_17 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB1_17
; %bb.23:
	global_load_b64 v[0:1], v[8:9], off
	s_and_saveexec_b32 s0, s2
	s_cbranch_execz .LBB1_27
; %bb.24:
	v_mov_b32_e32 v8, 0
	s_clause 0x2
	global_load_b64 v[4:5], v8, s[4:5] offset:40
	global_load_b64 v[9:10], v8, s[4:5] offset:24 glc
	global_load_b64 v[6:7], v8, s[4:5]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v11, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v11, s8
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v12 :: v_dual_cndmask_b32 v2, v2, v11
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v2, v4
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v4, 24
	v_mul_lo_u32 v4, v4, 24
	v_add_nc_u32_e32 v5, v11, v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v9
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v10
	global_store_b64 v[6:7], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v8, v[2:5], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_27
; %bb.25:                               ; %.preheader.i.i.i.preheader
	s_mov_b32 s1, 0
.LBB1_26:                               ; %.preheader.i.i.i
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v8, v[2:5], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[4:5]
	v_dual_mov_b32 v4, v9 :: v_dual_mov_b32 v5, v10
	s_or_b32 s1, vcc_lo, s1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s1
	s_cbranch_execnz .LBB1_26
.LBB1_27:                               ; %__ockl_printf_begin.exit
	s_or_b32 exec_lo, exec_lo, s0
	s_getpc_b64 s[2:3]
	s_add_u32 s2, s2, .str@rel32@lo+4
	s_addc_u32 s3, s3, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u64 s[2:3], 0
	s_cbranch_scc0 .LBB1_113
; %bb.28:
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v32, 0 :: v_dual_and_b32 v35, 2, v0
	v_dual_mov_b32 v3, v1 :: v_dual_and_b32 v2, -3, v0
	v_dual_mov_b32 v6, 2 :: v_dual_mov_b32 v7, 1
	s_mov_b64 s[8:9], 7
.LBB1_29:                               ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_32 Depth 2
                                        ;     Child Loop BB1_39 Depth 2
                                        ;     Child Loop BB1_47 Depth 2
                                        ;     Child Loop BB1_55 Depth 2
                                        ;     Child Loop BB1_63 Depth 2
                                        ;     Child Loop BB1_71 Depth 2
                                        ;     Child Loop BB1_79 Depth 2
                                        ;     Child Loop BB1_87 Depth 2
                                        ;     Child Loop BB1_95 Depth 2
                                        ;     Child Loop BB1_101 Depth 2
                                        ;     Child Loop BB1_110 Depth 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s0, s[8:9], 56
                                        ; implicit-def: $vgpr10_vgpr11
                                        ; implicit-def: $sgpr17
	s_and_b32 s0, s0, exec_lo
	s_cselect_b32 s10, s8, 56
	s_cselect_b32 s11, s9, 0
	s_cmp_gt_u32 s10, 7
	s_mov_b32 s0, -1
	s_cbranch_scc1 .LBB1_34
; %bb.30:                               ;   in Loop: Header=BB1_29 Depth=1
	v_mov_b32_e32 v10, 0
	v_mov_b32_e32 v11, 0
	s_cmp_eq_u32 s10, 0
	s_cbranch_scc1 .LBB1_33
; %bb.31:                               ; %.preheader31.i.preheader
                                        ;   in Loop: Header=BB1_29 Depth=1
	s_lshl_b64 s[0:1], s[10:11], 3
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[14:15], s[2:3]
.LBB1_32:                               ; %.preheader31.i
                                        ;   Parent Loop BB1_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_u8 v4, v32, s[14:15]
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v31, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s12, v[31:32]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_add_u32 s14, s14, 1
	s_addc_u32 s15, s15, 0
	s_cmp_lg_u32 s0, s12
	v_or_b32_e32 v10, v4, v10
	v_or_b32_e32 v11, v5, v11
	s_cbranch_scc1 .LBB1_32
.LBB1_33:                               ; %Flow375
                                        ;   in Loop: Header=BB1_29 Depth=1
	s_mov_b32 s0, 0
	s_mov_b32 s17, 0
.LBB1_34:                               ; %Flow377
                                        ;   in Loop: Header=BB1_29 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_mov_b64 s[0:1], s[2:3]
	s_cbranch_vccnz .LBB1_36
; %bb.35:                               ;   in Loop: Header=BB1_29 Depth=1
	global_load_b64 v[10:11], v32, s[2:3]
	s_add_i32 s17, s10, -8
	s_add_u32 s0, s2, 8
	s_addc_u32 s1, s3, 0
.LBB1_36:                               ; %.loopexit32.i
                                        ;   in Loop: Header=BB1_29 Depth=1
	s_cmp_gt_u32 s17, 7
	s_cbranch_scc1 .LBB1_41
; %bb.37:                               ;   in Loop: Header=BB1_29 Depth=1
	v_mov_b32_e32 v12, 0
	v_mov_b32_e32 v13, 0
	s_cmp_eq_u32 s17, 0
	s_cbranch_scc1 .LBB1_40
; %bb.38:                               ; %.preheader29.i.preheader
                                        ;   in Loop: Header=BB1_29 Depth=1
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[14:15], 0
.LBB1_39:                               ; %.preheader29.i
                                        ;   Parent Loop BB1_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s18, s0, s14
	s_addc_u32 s19, s1, s15
	s_add_u32 s14, s14, 1
	global_load_u8 v4, v32, s[18:19]
	s_addc_u32 s15, s15, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v31, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s12, v[31:32]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s17, s14
	v_or_b32_e32 v12, v4, v12
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v13, v5, v13
	s_cbranch_scc1 .LBB1_39
.LBB1_40:                               ; %Flow370
                                        ;   in Loop: Header=BB1_29 Depth=1
	s_mov_b32 s12, 0
	s_mov_b32 s16, 0
	s_branch .LBB1_42
.LBB1_41:                               ;   in Loop: Header=BB1_29 Depth=1
	s_mov_b32 s12, -1
                                        ; implicit-def: $vgpr12_vgpr13
                                        ; implicit-def: $sgpr16
.LBB1_42:                               ; %Flow372
                                        ;   in Loop: Header=BB1_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB1_44
; %bb.43:                               ;   in Loop: Header=BB1_29 Depth=1
	global_load_b64 v[12:13], v32, s[0:1]
	s_add_i32 s16, s17, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB1_44:                               ; %.loopexit30.i
                                        ;   in Loop: Header=BB1_29 Depth=1
	s_cmp_gt_u32 s16, 7
	s_cbranch_scc1 .LBB1_49
; %bb.45:                               ;   in Loop: Header=BB1_29 Depth=1
	v_mov_b32_e32 v14, 0
	v_mov_b32_e32 v15, 0
	s_cmp_eq_u32 s16, 0
	s_cbranch_scc1 .LBB1_48
; %bb.46:                               ; %.preheader27.i.preheader
                                        ;   in Loop: Header=BB1_29 Depth=1
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[14:15], 0
.LBB1_47:                               ; %.preheader27.i
                                        ;   Parent Loop BB1_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s18, s0, s14
	s_addc_u32 s19, s1, s15
	s_add_u32 s14, s14, 1
	global_load_u8 v4, v32, s[18:19]
	s_addc_u32 s15, s15, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v31, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s12, v[31:32]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s16, s14
	v_or_b32_e32 v14, v4, v14
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v15, v5, v15
	s_cbranch_scc1 .LBB1_47
.LBB1_48:                               ; %Flow365
                                        ;   in Loop: Header=BB1_29 Depth=1
	s_mov_b32 s12, 0
	s_mov_b32 s17, 0
	s_branch .LBB1_50
.LBB1_49:                               ;   in Loop: Header=BB1_29 Depth=1
	s_mov_b32 s12, -1
                                        ; implicit-def: $sgpr17
.LBB1_50:                               ; %Flow367
                                        ;   in Loop: Header=BB1_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB1_52
; %bb.51:                               ;   in Loop: Header=BB1_29 Depth=1
	global_load_b64 v[14:15], v32, s[0:1]
	s_add_i32 s17, s16, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB1_52:                               ; %.loopexit28.i
                                        ;   in Loop: Header=BB1_29 Depth=1
	s_cmp_gt_u32 s17, 7
	s_cbranch_scc1 .LBB1_57
; %bb.53:                               ;   in Loop: Header=BB1_29 Depth=1
	v_mov_b32_e32 v16, 0
	v_mov_b32_e32 v17, 0
	s_cmp_eq_u32 s17, 0
	s_cbranch_scc1 .LBB1_56
; %bb.54:                               ; %.preheader25.i.preheader
                                        ;   in Loop: Header=BB1_29 Depth=1
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[14:15], 0
.LBB1_55:                               ; %.preheader25.i
                                        ;   Parent Loop BB1_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s18, s0, s14
	s_addc_u32 s19, s1, s15
	s_add_u32 s14, s14, 1
	global_load_u8 v4, v32, s[18:19]
	s_addc_u32 s15, s15, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v31, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s12, v[31:32]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s17, s14
	v_or_b32_e32 v16, v4, v16
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v17, v5, v17
	s_cbranch_scc1 .LBB1_55
.LBB1_56:                               ; %Flow360
                                        ;   in Loop: Header=BB1_29 Depth=1
	s_mov_b32 s12, 0
	s_mov_b32 s16, 0
	s_branch .LBB1_58
.LBB1_57:                               ;   in Loop: Header=BB1_29 Depth=1
	s_mov_b32 s12, -1
                                        ; implicit-def: $vgpr16_vgpr17
                                        ; implicit-def: $sgpr16
.LBB1_58:                               ; %Flow362
                                        ;   in Loop: Header=BB1_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB1_60
; %bb.59:                               ;   in Loop: Header=BB1_29 Depth=1
	global_load_b64 v[16:17], v32, s[0:1]
	s_add_i32 s16, s17, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB1_60:                               ; %.loopexit26.i
                                        ;   in Loop: Header=BB1_29 Depth=1
	s_cmp_gt_u32 s16, 7
	s_cbranch_scc1 .LBB1_65
; %bb.61:                               ;   in Loop: Header=BB1_29 Depth=1
	v_mov_b32_e32 v18, 0
	v_mov_b32_e32 v19, 0
	s_cmp_eq_u32 s16, 0
	s_cbranch_scc1 .LBB1_64
; %bb.62:                               ; %.preheader23.i.preheader
                                        ;   in Loop: Header=BB1_29 Depth=1
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[14:15], 0
.LBB1_63:                               ; %.preheader23.i
                                        ;   Parent Loop BB1_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s18, s0, s14
	s_addc_u32 s19, s1, s15
	s_add_u32 s14, s14, 1
	global_load_u8 v4, v32, s[18:19]
	s_addc_u32 s15, s15, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v31, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s12, v[31:32]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s16, s14
	v_or_b32_e32 v18, v4, v18
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v19, v5, v19
	s_cbranch_scc1 .LBB1_63
.LBB1_64:                               ; %Flow355
                                        ;   in Loop: Header=BB1_29 Depth=1
	s_mov_b32 s12, 0
	s_mov_b32 s17, 0
	s_branch .LBB1_66
.LBB1_65:                               ;   in Loop: Header=BB1_29 Depth=1
	s_mov_b32 s12, -1
                                        ; implicit-def: $sgpr17
.LBB1_66:                               ; %Flow357
                                        ;   in Loop: Header=BB1_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB1_68
; %bb.67:                               ;   in Loop: Header=BB1_29 Depth=1
	global_load_b64 v[18:19], v32, s[0:1]
	s_add_i32 s17, s16, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB1_68:                               ; %.loopexit24.i
                                        ;   in Loop: Header=BB1_29 Depth=1
	s_cmp_gt_u32 s17, 7
	s_cbranch_scc1 .LBB1_73
; %bb.69:                               ;   in Loop: Header=BB1_29 Depth=1
	v_mov_b32_e32 v20, 0
	v_mov_b32_e32 v21, 0
	s_cmp_eq_u32 s17, 0
	s_cbranch_scc1 .LBB1_72
; %bb.70:                               ; %.preheader21.i.preheader
                                        ;   in Loop: Header=BB1_29 Depth=1
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[14:15], 0
.LBB1_71:                               ; %.preheader21.i
                                        ;   Parent Loop BB1_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s18, s0, s14
	s_addc_u32 s19, s1, s15
	s_add_u32 s14, s14, 1
	global_load_u8 v4, v32, s[18:19]
	s_addc_u32 s15, s15, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v31, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s12, v[31:32]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_cmp_lg_u32 s17, s14
	v_or_b32_e32 v20, v4, v20
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v21, v5, v21
	s_cbranch_scc1 .LBB1_71
.LBB1_72:                               ; %Flow350
                                        ;   in Loop: Header=BB1_29 Depth=1
	s_mov_b32 s12, 0
	s_mov_b32 s16, 0
	s_branch .LBB1_74
.LBB1_73:                               ;   in Loop: Header=BB1_29 Depth=1
	s_mov_b32 s12, -1
                                        ; implicit-def: $vgpr20_vgpr21
                                        ; implicit-def: $sgpr16
.LBB1_74:                               ; %Flow352
                                        ;   in Loop: Header=BB1_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB1_76
; %bb.75:                               ;   in Loop: Header=BB1_29 Depth=1
	global_load_b64 v[20:21], v32, s[0:1]
	s_add_i32 s16, s17, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB1_76:                               ; %.loopexit22.i
                                        ;   in Loop: Header=BB1_29 Depth=1
	s_cmp_gt_u32 s16, 7
	s_cbranch_scc1 .LBB1_81
; %bb.77:                               ;   in Loop: Header=BB1_29 Depth=1
	v_mov_b32_e32 v22, 0
	v_mov_b32_e32 v23, 0
	s_cmp_eq_u32 s16, 0
	s_cbranch_scc1 .LBB1_80
; %bb.78:                               ; %.preheader.i.preheader
                                        ;   in Loop: Header=BB1_29 Depth=1
	s_mov_b64 s[12:13], 0
	s_mov_b64 s[14:15], s[0:1]
.LBB1_79:                               ; %.preheader.i
                                        ;   Parent Loop BB1_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_u8 v4, v32, s[14:15]
	s_add_i32 s16, s16, -1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v31, 0xffff, v4
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], s12, v[31:32]
	s_add_u32 s12, s12, 8
	s_addc_u32 s13, s13, 0
	s_add_u32 s14, s14, 1
	s_addc_u32 s15, s15, 0
	s_cmp_lg_u32 s16, 0
	v_or_b32_e32 v22, v4, v22
	v_or_b32_e32 v23, v5, v23
	s_cbranch_scc1 .LBB1_79
.LBB1_80:                               ; %Flow345
                                        ;   in Loop: Header=BB1_29 Depth=1
	s_mov_b32 s12, 0
	s_branch .LBB1_82
.LBB1_81:                               ;   in Loop: Header=BB1_29 Depth=1
	s_mov_b32 s12, -1
.LBB1_82:                               ; %Flow347
                                        ;   in Loop: Header=BB1_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s12
	s_cbranch_vccnz .LBB1_84
; %bb.83:                               ;   in Loop: Header=BB1_29 Depth=1
	global_load_b64 v[22:23], v32, s[0:1]
.LBB1_84:                               ; %.loopexit.i
                                        ;   in Loop: Header=BB1_29 Depth=1
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v31, v30 :: v_dual_mov_b32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v31
	v_mov_b32_e32 v5, 0
	v_cmp_eq_u32_e64 s0, s0, v31
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_90
; %bb.85:                               ;   in Loop: Header=BB1_29 Depth=1
	global_load_b64 v[26:27], v32, s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[4:5], v32, s[4:5] offset:40
	global_load_b64 v[8:9], v32, s[4:5]
	s_mov_b32 s12, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v5, v5, v27
	v_and_b32_e32 v4, v4, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v5, v5, 24
	v_mul_hi_u32 v24, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v24, v5
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v8, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v9, v5, vcc_lo
	global_load_b64 v[24:25], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v32, v[24:27], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[4:5], v[26:27]
	s_cbranch_execz .LBB1_89
; %bb.86:                               ; %.preheader3.i.i19.i.preheader
                                        ;   in Loop: Header=BB1_29 Depth=1
	s_mov_b32 s13, 0
.LBB1_87:                               ; %.preheader3.i.i19.i
                                        ;   Parent Loop BB1_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[8:9], v32, s[4:5] offset:40
	global_load_b64 v[24:25], v32, s[4:5]
	v_dual_mov_b32 v27, v5 :: v_dual_mov_b32 v26, v4
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v8, v8, v26
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[4:5], null, v8, 24, v[24:25]
	v_and_b32_e32 v24, v9, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v24, 24, v[5:6]
	v_mov_b32_e32 v5, v8
	global_load_b64 v[24:25], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v32, v[24:27], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[26:27]
	s_or_b32 s13, vcc_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB1_87
; %bb.88:                               ; %Flow340
                                        ;   in Loop: Header=BB1_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
.LBB1_89:                               ; %Flow342
                                        ;   in Loop: Header=BB1_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s12
.LBB1_90:                               ; %.loopexit4.i.i14.i
                                        ;   in Loop: Header=BB1_29 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[8:9], v32, s[4:5] offset:40
	global_load_b128 v[24:27], v32, s[4:5]
	v_readfirstlane_b32 s12, v4
	v_readfirstlane_b32 s13, v5
	s_mov_b32 s18, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s14, v8
	v_readfirstlane_b32 s15, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[14:15], s[12:13], s[14:15]
	s_mul_i32 s1, s15, 24
	s_mul_hi_u32 s16, s14, 24
	s_mul_i32 s17, s14, 24
	s_and_saveexec_b32 s19, s0
	s_cbranch_execz .LBB1_92
; %bb.91:                               ;   in Loop: Header=BB1_29 Depth=1
	v_dual_mov_b32 v4, s18 :: v_dual_mov_b32 v5, v32
	s_add_i32 s18, s16, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v8, vcc_lo, v24, s17
	v_add_co_ci_u32_e32 v9, vcc_lo, s18, v25, vcc_lo
	global_store_b128 v[8:9], v[4:7], off offset:8
.LBB1_92:                               ;   in Loop: Header=BB1_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s19
	v_cmp_gt_u64_e64 vcc_lo, s[8:9], 56
	v_or_b32_e32 v4, 0, v3
	v_or_b32_e32 v5, v2, v35
	s_lshl_b64 s[14:15], s[14:15], 12
	s_lshl_b32 s18, s10, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s18, s18, 28
	v_dual_cndmask_b32 v9, v4, v3 :: v_dual_cndmask_b32 v4, v5, v2
	v_lshlrev_b64 v[2:3], 6, v[31:32]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v26, s14
	v_add_co_ci_u32_e32 v27, vcc_lo, s15, v27, vcc_lo
	s_and_b32 s18, s18, 0x1e0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v26, vcc_lo, v5, v2
	v_and_or_b32 v8, 0xffffff1f, v4, s18
	v_add_co_ci_u32_e32 v27, vcc_lo, v27, v3, vcc_lo
	s_clause 0x3
	global_store_b128 v[26:27], v[8:11], off
	global_store_b128 v[26:27], v[12:15], off offset:16
	global_store_b128 v[26:27], v[16:19], off offset:32
	global_store_b128 v[26:27], v[20:23], off offset:48
	s_and_saveexec_b32 s14, s0
	s_cbranch_execz .LBB1_100
; %bb.93:                               ;   in Loop: Header=BB1_29 Depth=1
	s_clause 0x1
	global_load_b64 v[12:13], v32, s[4:5] offset:32 glc
	global_load_b64 v[2:3], v32, s[4:5] offset:40
	v_dual_mov_b32 v10, s12 :: v_dual_mov_b32 v11, s13
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s18, v2
	v_readfirstlane_b32 s19, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[18:19], s[18:19], s[12:13]
	s_mul_i32 s15, s19, 24
	s_mul_hi_u32 s19, s18, 24
	s_mul_i32 s18, s18, 24
	s_add_i32 s19, s19, s15
	v_add_co_u32 v8, vcc_lo, v24, s18
	v_add_co_ci_u32_e32 v9, vcc_lo, s19, v25, vcc_lo
	s_mov_b32 s15, exec_lo
	global_store_b64 v[8:9], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v32, v[10:13], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[4:5], v[12:13]
	s_cbranch_execz .LBB1_96
; %bb.94:                               ; %.preheader1.i.i17.i.preheader
                                        ;   in Loop: Header=BB1_29 Depth=1
	s_mov_b32 s18, 0
.LBB1_95:                               ; %.preheader1.i.i17.i
                                        ;   Parent Loop BB1_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v2, s12 :: v_dual_mov_b32 v3, s13
	s_sleep 1
	global_store_b64 v[8:9], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v32, v[2:5], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[4:5]
	v_dual_mov_b32 v5, v3 :: v_dual_mov_b32 v4, v2
	s_or_b32 s18, vcc_lo, s18
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s18
	s_cbranch_execnz .LBB1_95
.LBB1_96:                               ; %Flow338
                                        ;   in Loop: Header=BB1_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s15
	global_load_b64 v[2:3], v32, s[4:5] offset:16
	s_mov_b32 s18, exec_lo
	s_mov_b32 s15, exec_lo
	v_mbcnt_lo_u32_b32 v4, s18, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v4
	s_cbranch_execz .LBB1_98
; %bb.97:                               ;   in Loop: Header=BB1_29 Depth=1
	s_bcnt1_i32_b32 s18, s18
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v31, s18
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[2:3], v[31:32], off offset:8
.LBB1_98:                               ;   in Loop: Header=BB1_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s15
	s_waitcnt vmcnt(0)
	global_load_b64 v[4:5], v[2:3], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	s_cbranch_vccnz .LBB1_100
; %bb.99:                               ;   in Loop: Header=BB1_29 Depth=1
	global_load_b32 v31, v[2:3], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s15, v31
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[4:5], v[31:32], off
	s_and_b32 m0, s15, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_100:                              ; %Flow339
                                        ;   in Loop: Header=BB1_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	s_add_i32 s16, s16, s1
	v_add_co_u32 v2, vcc_lo, v24, s17
	v_add_co_ci_u32_e32 v3, vcc_lo, s16, v25, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v2, 20
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
.LBB1_101:                              ;   Parent Loop BB1_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v4, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_103
; %bb.102:                              ;   in Loop: Header=BB1_101 Depth=2
	global_load_b32 v4, v[2:3], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v4, 1, v4
.LBB1_103:                              ;   in Loop: Header=BB1_101 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v4
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_105
; %bb.104:                              ;   in Loop: Header=BB1_101 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_106
.LBB1_105:                              ;   in Loop: Header=BB1_101 Depth=2
	s_mov_b32 s1, -1
.LBB1_106:                              ; %Flow333
                                        ;   in Loop: Header=BB1_101 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_101
; %bb.107:                              ;   in Loop: Header=BB1_29 Depth=1
	global_load_b128 v[2:5], v[26:27], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_111
; %bb.108:                              ;   in Loop: Header=BB1_29 Depth=1
	s_clause 0x2
	global_load_b64 v[4:5], v32, s[4:5] offset:40
	global_load_b64 v[12:13], v32, s[4:5] offset:24 glc
	global_load_b64 v[10:11], v32, s[4:5]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v14, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v14, s12
	v_add_co_ci_u32_e32 v9, vcc_lo, s13, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[8:9]
	v_dual_cndmask_b32 v9, v9, v15 :: v_dual_cndmask_b32 v8, v8, v14
	v_and_b32_e32 v5, v9, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v4, v8, v4
	v_mul_hi_u32 v14, v4, 24
	v_mul_lo_u32 v4, v4, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v4, vcc_lo, v10, v4
	v_mov_b32_e32 v10, v12
	v_mul_lo_u32 v5, v5, 24
	v_add_nc_u32_e32 v5, v14, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, v11, v5, vcc_lo
	v_mov_b32_e32 v11, v13
	global_store_b64 v[4:5], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v32, v[8:11], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[10:11], v[12:13]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_111
; %bb.109:                              ; %.preheader.i.i16.i.preheader
                                        ;   in Loop: Header=BB1_29 Depth=1
	s_mov_b32 s0, 0
.LBB1_110:                              ; %.preheader.i.i16.i
                                        ;   Parent Loop BB1_29 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[4:5], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[12:13], v32, v[8:11], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[12:13], v[10:11]
	v_dual_mov_b32 v10, v12 :: v_dual_mov_b32 v11, v13
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_110
.LBB1_111:                              ; %__ockl_hostcall_preview.exit20.i
                                        ;   in Loop: Header=BB1_29 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_sub_u32 s8, s8, s10
	s_subb_u32 s9, s9, s11
	s_add_u32 s2, s2, s10
	s_addc_u32 s3, s3, s11
	s_cmp_lg_u64 s[8:9], 0
	s_cbranch_scc1 .LBB1_29
; %bb.112:                              ; %Flow378
	s_mov_b32 s0, 0
	s_branch .LBB1_114
.LBB1_113:
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr2_vgpr3
.LBB1_114:                              ; %Flow393
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB1_143
; %bb.115:
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v2, v30
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v2
	v_cmp_eq_u32_e64 s0, s0, v2
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_121
; %bb.116:
	v_mov_b32_e32 v3, 0
	s_mov_b32 s2, exec_lo
	global_load_b64 v[6:7], v3, s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[4:5] offset:40
	global_load_b64 v[8:9], v3, s[4:5]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v6
	v_and_b32_e32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v10, v4, 24
	v_mul_lo_u32 v5, v5, 24
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v10, v5
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v8, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v9, v5, vcc_lo
	global_load_b64 v[4:5], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v3, v[4:7], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[8:9], v[6:7]
	s_cbranch_execz .LBB1_120
; %bb.117:                              ; %.preheader3.i.i.i36.preheader
	s_mov_b32 s3, 0
.LBB1_118:                              ; %.preheader3.i.i.i36
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[4:5], v3, s[4:5] offset:40
	global_load_b64 v[10:11], v3, s[4:5]
	v_dual_mov_b32 v6, v8 :: v_dual_mov_b32 v7, v9
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v4, v6
	v_and_b32_e32 v5, v5, v7
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v4, 24, v[10:11]
	v_mov_b32_e32 v4, v9
	s_delay_alu instid0(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, v5, 24, v[4:5]
	global_load_b64 v[4:5], v[8:9], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[8:9], v3, v[4:7], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[8:9], v[6:7]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_118
; %bb.119:                              ; %Flow390
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_120:                              ; %Flow392
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_121:                              ; %.loopexit4.i.i.i31
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v3, 0
	v_readfirstlane_b32 s2, v8
	v_readfirstlane_b32 s3, v9
	s_mov_b32 s12, exec_lo
	s_clause 0x1
	global_load_b64 v[10:11], v3, s[4:5] offset:40
	global_load_b128 v[4:7], v3, s[4:5]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s8, v10
	v_readfirstlane_b32 s9, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[2:3], s[8:9]
	s_mul_i32 s1, s9, 24
	s_mul_hi_u32 s10, s8, 24
	s_mul_i32 s11, s8, 24
	s_and_saveexec_b32 s13, s0
	s_cbranch_execz .LBB1_123
; %bb.122:
	v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v9, v3
	s_add_i32 s12, s10, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v12, vcc_lo, v4, s11
	v_add_co_ci_u32_e32 v13, vcc_lo, s12, v5, vcc_lo
	v_dual_mov_b32 v10, 2 :: v_dual_mov_b32 v11, 1
	global_store_b128 v[12:13], v[8:11], off offset:8
.LBB1_123:
	s_or_b32 exec_lo, exec_lo, s13
	s_lshl_b64 s[8:9], s[8:9], 12
	v_lshlrev_b64 v[8:9], 6, v[2:3]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v6, s8
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v2, v8
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_and_or_b32 v0, 0xffffff1f, v0, 32
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v9, vcc_lo
	v_mov_b32_e32 v2, v3
	v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v11, s15
	v_dual_mov_b32 v9, s13 :: v_dual_mov_b32 v10, s14
	s_clause 0x3
	global_store_b128 v[6:7], v[0:3], off
	global_store_b128 v[6:7], v[8:11], off offset:16
	global_store_b128 v[6:7], v[8:11], off offset:32
	global_store_b128 v[6:7], v[8:11], off offset:48
	s_and_saveexec_b32 s8, s0
	s_cbranch_execz .LBB1_131
; %bb.124:
	v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s2
	v_mov_b32_e32 v12, s3
	s_clause 0x1
	global_load_b64 v[13:14], v10, s[4:5] offset:32 glc
	global_load_b64 v[0:1], v10, s[4:5] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s12, v0
	v_readfirstlane_b32 s13, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[12:13], s[12:13], s[2:3]
	s_mul_i32 s9, s13, 24
	s_mul_hi_u32 s13, s12, 24
	s_mul_i32 s12, s12, 24
	s_add_i32 s13, s13, s9
	v_add_co_u32 v8, vcc_lo, v4, s12
	v_add_co_ci_u32_e32 v9, vcc_lo, s13, v5, vcc_lo
	s_mov_b32 s9, exec_lo
	global_store_b64 v[8:9], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v10, v[11:14], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[13:14]
	s_cbranch_execz .LBB1_127
; %bb.125:                              ; %.preheader1.i.i.i34.preheader
	s_mov_b32 s12, 0
.LBB1_126:                              ; %.preheader1.i.i.i34
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
	s_sleep 1
	global_store_b64 v[8:9], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v10, v[0:3], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s12, vcc_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB1_126
.LBB1_127:                              ; %Flow388
	s_or_b32 exec_lo, exec_lo, s9
	v_mov_b32_e32 v3, 0
	s_mov_b32 s12, exec_lo
	s_mov_b32 s9, exec_lo
	v_mbcnt_lo_u32_b32 v2, s12, 0
	global_load_b64 v[0:1], v3, s[4:5] offset:16
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB1_129
; %bb.128:
	s_bcnt1_i32_b32 s12, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s12
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB1_129:
	s_or_b32 exec_lo, exec_lo, s9
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB1_131
; %bb.130:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s9, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[0:1], off
	s_and_b32 m0, s9, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_131:                              ; %Flow389
	s_or_b32 exec_lo, exec_lo, s8
	s_add_i32 s10, s10, s1
	v_add_co_u32 v0, vcc_lo, v4, s11
	v_add_co_ci_u32_e32 v1, vcc_lo, s10, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_132:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_134
; %bb.133:                              ;   in Loop: Header=BB1_132 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_134:                              ;   in Loop: Header=BB1_132 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_136
; %bb.135:                              ;   in Loop: Header=BB1_132 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_137
.LBB1_136:                              ;   in Loop: Header=BB1_132 Depth=1
	s_mov_b32 s1, -1
.LBB1_137:                              ; %Flow383
                                        ;   in Loop: Header=BB1_132 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_132
; %bb.138:
	global_load_b128 v[2:5], v[6:7], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_142
; %bb.139:
	v_mov_b32_e32 v8, 0
	s_clause 0x2
	global_load_b64 v[0:1], v8, s[4:5] offset:40
	global_load_b64 v[9:10], v8, s[4:5] offset:24 glc
	global_load_b64 v[6:7], v8, s[4:5]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v11, vcc_lo, v0, 1
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v11, s2
	v_add_co_ci_u32_e32 v5, vcc_lo, s3, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[4:5]
	v_dual_cndmask_b32 v5, v5, v12 :: v_dual_cndmask_b32 v4, v4, v11
	v_and_b32_e32 v1, v5, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v4, v0
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v0, 24
	v_mul_lo_u32 v0, v0, 24
	v_add_nc_u32_e32 v1, v11, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v6, v0
	v_mov_b32_e32 v6, v9
	v_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo
	v_mov_b32_e32 v7, v10
	global_store_b64 v[0:1], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[6:7], v8, v[4:7], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[6:7], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_142
; %bb.140:                              ; %.preheader.i.i.i33.preheader
	s_mov_b32 s0, 0
.LBB1_141:                              ; %.preheader.i.i.i33
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[0:1], v[6:7], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v8, v[4:7], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[6:7]
	v_dual_mov_b32 v6, v9 :: v_dual_mov_b32 v7, v10
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_141
.LBB1_142:                              ; %__ockl_hostcall_preview.exit.i
	s_or_b32 exec_lo, exec_lo, s1
.LBB1_143:                              ; %__ockl_printf_append_string_n.exit
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v0, v30
	v_mov_b32_e32 v4, 0
	v_mov_b32_e32 v5, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v0
	v_cmp_eq_u32_e64 s0, s0, v0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_149
; %bb.144:
	v_mov_b32_e32 v1, 0
	s_mov_b32 s2, exec_lo
	global_load_b64 v[6:7], v1, s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[4:5], v1, s[4:5] offset:40
	global_load_b64 v[8:9], v1, s[4:5]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v6
	v_and_b32_e32 v5, v5, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v10, v4, 24
	v_mul_lo_u32 v5, v5, 24
	v_mul_lo_u32 v4, v4, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v10, v5
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v8, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, v9, v5, vcc_lo
	global_load_b64 v[4:5], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v1, v[4:7], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[4:5], v[6:7]
	s_cbranch_execz .LBB1_148
; %bb.145:                              ; %.preheader3.i.i.i43.preheader
	s_mov_b32 s3, 0
.LBB1_146:                              ; %.preheader3.i.i.i43
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[8:9], v1, s[4:5] offset:40
	global_load_b64 v[10:11], v1, s[4:5]
	v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v6, v4
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v8, v8, v6
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[4:5], null, v8, 24, v[10:11]
	v_and_b32_e32 v10, v9, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, v10, 24, v[5:6]
	v_mov_b32_e32 v5, v8
	global_load_b64 v[4:5], v[4:5], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[4:5], v1, v[4:7], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[6:7]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_146
; %bb.147:                              ; %Flow326
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_148:                              ; %Flow328
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_149:                              ; %.loopexit4.i.i.i37
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v1, 0
	v_readfirstlane_b32 s2, v4
	v_readfirstlane_b32 s3, v5
	s_mov_b32 s12, exec_lo
	s_clause 0x1
	global_load_b64 v[10:11], v1, s[4:5] offset:40
	global_load_b128 v[6:9], v1, s[4:5]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s8, v10
	v_readfirstlane_b32 s9, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[2:3], s[8:9]
	s_mul_i32 s1, s9, 24
	s_mul_hi_u32 s10, s8, 24
	s_mul_i32 s11, s8, 24
	s_and_saveexec_b32 s13, s0
	s_cbranch_execz .LBB1_151
; %bb.150:
	v_dual_mov_b32 v10, s12 :: v_dual_mov_b32 v11, v1
	s_add_i32 s12, s10, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v4, vcc_lo, v6, s11
	v_add_co_ci_u32_e32 v5, vcc_lo, s12, v7, vcc_lo
	v_dual_mov_b32 v12, 2 :: v_dual_mov_b32 v13, 1
	global_store_b128 v[4:5], v[10:13], off offset:8
.LBB1_151:
	s_or_b32 exec_lo, exec_lo, s13
	v_cvt_f64_f32_e32 v[4:5], v33
	s_lshl_b64 s[8:9], s[8:9], 12
	v_lshlrev_b64 v[0:1], 6, v[0:1]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v8, vcc_lo, v8, s8
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v9, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, v8, v0
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_and_or_b32 v2, 0xffffff1f, v2, 32
	v_add_co_ci_u32_e32 v9, vcc_lo, v9, v1, vcc_lo
	v_dual_mov_b32 v10, s12 :: v_dual_mov_b32 v11, s13
	v_dual_mov_b32 v12, s14 :: v_dual_mov_b32 v13, s15
	s_clause 0x3
	global_store_b128 v[8:9], v[2:5], off
	global_store_b128 v[8:9], v[10:13], off offset:16
	global_store_b128 v[8:9], v[10:13], off offset:32
	global_store_b128 v[8:9], v[10:13], off offset:48
	s_and_saveexec_b32 s8, s0
	s_cbranch_execz .LBB1_159
; %bb.152:
	v_dual_mov_b32 v10, 0 :: v_dual_mov_b32 v11, s2
	v_mov_b32_e32 v12, s3
	s_clause 0x1
	global_load_b64 v[13:14], v10, s[4:5] offset:32 glc
	global_load_b64 v[0:1], v10, s[4:5] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s12, v0
	v_readfirstlane_b32 s13, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[12:13], s[12:13], s[2:3]
	s_mul_i32 s9, s13, 24
	s_mul_hi_u32 s13, s12, 24
	s_mul_i32 s12, s12, 24
	s_add_i32 s13, s13, s9
	v_add_co_u32 v4, vcc_lo, v6, s12
	v_add_co_ci_u32_e32 v5, vcc_lo, s13, v7, vcc_lo
	s_mov_b32 s9, exec_lo
	global_store_b64 v[4:5], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v10, v[11:14], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[13:14]
	s_cbranch_execz .LBB1_155
; %bb.153:                              ; %.preheader1.i.i.i41.preheader
	s_mov_b32 s12, 0
.LBB1_154:                              ; %.preheader1.i.i.i41
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v10, v[0:3], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s12, vcc_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB1_154
.LBB1_155:                              ; %Flow324
	s_or_b32 exec_lo, exec_lo, s9
	v_mov_b32_e32 v3, 0
	s_mov_b32 s12, exec_lo
	s_mov_b32 s9, exec_lo
	v_mbcnt_lo_u32_b32 v2, s12, 0
	global_load_b64 v[0:1], v3, s[4:5] offset:16
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB1_157
; %bb.156:
	s_bcnt1_i32_b32 s12, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s12
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB1_157:
	s_or_b32 exec_lo, exec_lo, s9
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB1_159
; %bb.158:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s9, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[0:1], off
	s_and_b32 m0, s9, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_159:                              ; %Flow325
	s_or_b32 exec_lo, exec_lo, s8
	s_add_i32 s10, s10, s1
	v_add_co_u32 v0, vcc_lo, v6, s11
	v_add_co_ci_u32_e32 v1, vcc_lo, s10, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_160:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_162
; %bb.161:                              ;   in Loop: Header=BB1_160 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_162:                              ;   in Loop: Header=BB1_160 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_164
; %bb.163:                              ;   in Loop: Header=BB1_160 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_165
.LBB1_164:                              ;   in Loop: Header=BB1_160 Depth=1
	s_mov_b32 s1, -1
.LBB1_165:                              ; %Flow319
                                        ;   in Loop: Header=BB1_160 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_160
; %bb.166:
	global_load_b64 v[0:1], v[8:9], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_170
; %bb.167:
	v_mov_b32_e32 v8, 0
	s_clause 0x2
	global_load_b64 v[4:5], v8, s[4:5] offset:40
	global_load_b64 v[9:10], v8, s[4:5] offset:24 glc
	global_load_b64 v[6:7], v8, s[4:5]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v11, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v12, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, v11, s2
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	v_dual_cndmask_b32 v3, v3, v12 :: v_dual_cndmask_b32 v2, v2, v11
	v_and_b32_e32 v5, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v4, v2, v4
	v_mul_lo_u32 v5, v5, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v11, v4, 24
	v_mul_lo_u32 v4, v4, 24
	v_add_nc_u32_e32 v5, v11, v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v6, vcc_lo, v6, v4
	v_mov_b32_e32 v4, v9
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v5, vcc_lo
	v_mov_b32_e32 v5, v10
	global_store_b64 v[6:7], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[4:5], v8, v[2:5], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[4:5], v[9:10]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_170
; %bb.168:                              ; %.preheader.i.i.i40.preheader
	s_mov_b32 s0, 0
.LBB1_169:                              ; %.preheader.i.i.i40
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[6:7], v[4:5], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v8, v[2:5], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[9:10], v[4:5]
	v_dual_mov_b32 v4, v9 :: v_dual_mov_b32 v5, v10
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_169
.LBB1_170:                              ; %__ockl_printf_append_args.exit
	s_or_b32 exec_lo, exec_lo, s1
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v30
	v_mov_b32_e32 v2, 0
	v_mov_b32_e32 v3, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v30
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_176
; %bb.171:
	v_mov_b32_e32 v4, 0
	s_mov_b32 s2, exec_lo
	global_load_b64 v[7:8], v4, s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[2:3], v4, s[4:5] offset:40
	global_load_b64 v[5:6], v4, s[4:5]
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v3, v3, v8
	v_and_b32_e32 v2, v2, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v3, 24
	v_mul_hi_u32 v9, v2, 24
	v_mul_lo_u32 v2, v2, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v9, v3
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v5, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, v6, v3, vcc_lo
	global_load_b64 v[5:6], v[2:3], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[2:3], v4, v[5:8], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[2:3], v[7:8]
	s_cbranch_execz .LBB1_175
; %bb.172:                              ; %.preheader3.i.i.i50.preheader
	s_mov_b32 s3, 0
.LBB1_173:                              ; %.preheader3.i.i.i50
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[5:6], v4, s[4:5] offset:40
	global_load_b64 v[9:10], v4, s[4:5]
	v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v7, v2
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v5, v5, v7
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[2:3], null, v5, 24, v[9:10]
	v_and_b32_e32 v9, v6, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, v9, 24, v[3:4]
	v_mov_b32_e32 v3, v5
	global_load_b64 v[5:6], v[2:3], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[2:3], v4, v[5:8], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[2:3], v[7:8]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB1_173
; %bb.174:                              ; %Flow312
	s_or_b32 exec_lo, exec_lo, s3
.LBB1_175:                              ; %Flow314
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
.LBB1_176:                              ; %.loopexit4.i.i.i44
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v31, 0
	v_readfirstlane_b32 s2, v2
	v_readfirstlane_b32 s3, v3
	s_mov_b32 s12, exec_lo
	s_clause 0x1
	global_load_b64 v[8:9], v31, s[4:5] offset:40
	global_load_b128 v[4:7], v31, s[4:5]
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s8, v8
	v_readfirstlane_b32 s9, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[8:9], s[2:3], s[8:9]
	s_mul_i32 s1, s9, 24
	s_mul_hi_u32 s10, s8, 24
	s_mul_i32 s11, s8, 24
	s_and_saveexec_b32 s13, s0
	s_cbranch_execz .LBB1_178
; %bb.177:
	v_dual_mov_b32 v8, s12 :: v_dual_mov_b32 v9, v31
	s_add_i32 s12, s10, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v2, vcc_lo, v4, s11
	v_add_co_ci_u32_e32 v3, vcc_lo, s12, v5, vcc_lo
	v_dual_mov_b32 v10, 2 :: v_dual_mov_b32 v11, 1
	global_store_b128 v[2:3], v[8:11], off offset:8
.LBB1_178:
	s_or_b32 exec_lo, exec_lo, s13
	v_cvt_f64_f32_e32 v[2:3], v34
	s_lshl_b64 s[8:9], s[8:9], 12
	v_lshlrev_b64 v[8:9], 6, v[30:31]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v6, vcc_lo, v6, s8
	v_add_co_ci_u32_e32 v7, vcc_lo, s9, v7, vcc_lo
	s_mov_b32 s12, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v6, v8
	s_mov_b32 s13, s12
	s_mov_b32 s14, s12
	s_mov_b32 s15, s12
	v_and_or_b32 v0, 0xffffff1d, v0, 34
	v_add_co_ci_u32_e32 v11, vcc_lo, v7, v9, vcc_lo
	v_dual_mov_b32 v6, s12 :: v_dual_mov_b32 v7, s13
	v_dual_mov_b32 v8, s14 :: v_dual_mov_b32 v9, s15
	s_clause 0x3
	global_store_b128 v[10:11], v[0:3], off
	global_store_b128 v[10:11], v[6:9], off offset:16
	global_store_b128 v[10:11], v[6:9], off offset:32
	global_store_b128 v[10:11], v[6:9], off offset:48
	s_and_saveexec_b32 s8, s0
	s_cbranch_execz .LBB1_186
; %bb.179:
	v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, s2
	v_mov_b32_e32 v10, s3
	s_clause 0x1
	global_load_b64 v[11:12], v8, s[4:5] offset:32 glc
	global_load_b64 v[0:1], v8, s[4:5] offset:40
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s12, v0
	v_readfirstlane_b32 s13, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[12:13], s[12:13], s[2:3]
	s_mul_i32 s9, s13, 24
	s_mul_hi_u32 s13, s12, 24
	s_mul_i32 s12, s12, 24
	s_add_i32 s13, s13, s9
	v_add_co_u32 v6, vcc_lo, v4, s12
	v_add_co_ci_u32_e32 v7, vcc_lo, s13, v5, vcc_lo
	s_mov_b32 s9, exec_lo
	global_store_b64 v[6:7], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v8, v[9:12], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[2:3], v[11:12]
	s_cbranch_execz .LBB1_182
; %bb.180:                              ; %.preheader1.i.i.i48.preheader
	s_mov_b32 s12, 0
.LBB1_181:                              ; %.preheader1.i.i.i48
                                        ; =>This Inner Loop Header: Depth=1
	v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
	s_sleep 1
	global_store_b64 v[6:7], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[0:1], v8, v[0:3], s[4:5] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[2:3]
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v2, v0
	s_or_b32 s12, vcc_lo, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s12
	s_cbranch_execnz .LBB1_181
.LBB1_182:                              ; %Flow310
	s_or_b32 exec_lo, exec_lo, s9
	v_mov_b32_e32 v3, 0
	s_mov_b32 s12, exec_lo
	s_mov_b32 s9, exec_lo
	v_mbcnt_lo_u32_b32 v2, s12, 0
	global_load_b64 v[0:1], v3, s[4:5] offset:16
	v_cmpx_eq_u32_e32 0, v2
	s_cbranch_execz .LBB1_184
; %bb.183:
	s_bcnt1_i32_b32 s12, s12
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s12
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[2:3], off offset:8
.LBB1_184:
	s_or_b32 exec_lo, exec_lo, s9
	s_waitcnt vmcnt(0)
	global_load_b64 v[2:3], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
	s_cbranch_vccnz .LBB1_186
; %bb.185:
	global_load_b32 v0, v[0:1], off offset:24
	v_mov_b32_e32 v1, 0
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s9, v0
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[2:3], v[0:1], off
	s_and_b32 m0, s9, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB1_186:                              ; %Flow311
	s_or_b32 exec_lo, exec_lo, s8
	s_add_i32 s10, s10, s1
	v_add_co_u32 v0, vcc_lo, v4, s11
	v_add_co_ci_u32_e32 v1, vcc_lo, s10, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB1_187:                              ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v2, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_189
; %bb.188:                              ;   in Loop: Header=BB1_187 Depth=1
	global_load_b32 v2, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v2, 1, v2
.LBB1_189:                              ;   in Loop: Header=BB1_187 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v2
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB1_191
; %bb.190:                              ;   in Loop: Header=BB1_187 Depth=1
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB1_192
.LBB1_191:                              ;   in Loop: Header=BB1_187 Depth=1
	s_mov_b32 s1, -1
.LBB1_192:                              ; %Flow305
                                        ;   in Loop: Header=BB1_187 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB1_187
; %bb.193:
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB1_197
; %bb.194:
	v_mov_b32_e32 v6, 0
	s_clause 0x2
	global_load_b64 v[2:3], v6, s[4:5] offset:40
	global_load_b64 v[7:8], v6, s[4:5] offset:24 glc
	global_load_b64 v[4:5], v6, s[4:5]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v9, vcc_lo, v2, 1
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v9, s2
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[0:1]
	v_dual_cndmask_b32 v1, v1, v10 :: v_dual_cndmask_b32 v0, v0, v9
	v_and_b32_e32 v3, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v2, v0, v2
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v9, v2, 24
	v_mul_lo_u32 v2, v2, 24
	v_add_nc_u32_e32 v3, v9, v3
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, v4, v2
	v_mov_b32_e32 v2, v7
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
	v_mov_b32_e32 v3, v8
	global_store_b64 v[4:5], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[2:3], v6, v[0:3], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[2:3], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB1_197
; %bb.195:                              ; %.preheader.i.i.i47.preheader
	s_mov_b32 s0, 0
.LBB1_196:                              ; %.preheader.i.i.i47
                                        ; =>This Inner Loop Header: Depth=1
	s_sleep 1
	global_store_b64 v[4:5], v[2:3], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v6, v[0:3], s[4:5] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[2:3]
	v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB1_196
.LBB1_197:                              ; %__ockl_printf_append_args.exit51
	s_or_b32 exec_lo, exec_lo, s1
	v_lshlrev_b64 v[0:1], 2, v[28:29]
	v_mul_f32_e32 v2, v33, v34
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB1_198:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10multi_vec2iiiiiPfS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 36
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z10multi_vec2iiiiiPfS_S_, .Lfunc_end1-_Z10multi_vec2iiiiiPfS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 8760
; NumSgprs: 22
; NumVgprs: 36
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 36
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z9multi_veciiiiiPfS_S_ ; -- Begin function _Z9multi_veciiiiiPfS_S_
	.globl	_Z9multi_veciiiiiPfS_S_
	.p2align	8
	.type	_Z9multi_veciiiiiPfS_S_,@function
_Z9multi_veciiiiiPfS_S_:                ; @_Z9multi_veciiiiiPfS_S_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x3c
	s_load_b128 s[4:7], s[0:1], 0x4
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mul_i32 s2, s7, s6
	s_mul_i32 s3, s2, s4
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s3, v1
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB2_2
; %bb.1:
	s_ashr_i32 s3, s2, 31
	v_ashrrev_i32_e32 v2, 31, v1
	s_add_i32 s8, s2, s3
	s_ashr_i32 s11, s5, 31
	s_xor_b32 s8, s8, s3
	s_add_i32 s5, s5, s11
	v_cvt_f32_u32_e32 v0, s8
	s_sub_i32 s9, 0, s8
	v_add_nc_u32_e32 v4, v1, v2
	v_xor_b32_e32 v7, s3, v2
	s_xor_b32 s3, s5, s11
	v_rcp_iflag_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v4, v4, v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v3, s9, v0
	s_ashr_i32 s9, s6, 31
	s_add_i32 s10, s6, s9
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_xor_b32 s10, s10, s9
	v_mul_hi_u32 v3, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v0, v3
	v_mul_hi_u32 v0, v4, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v0, s8
	v_add_nc_u32_e32 v5, 1, v0
	v_sub_nc_u32_e32 v3, v4, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v6, s8, v3
	v_cmp_le_u32_e32 vcc_lo, s8, v3
	v_dual_cndmask_b32 v0, v0, v5 :: v_dual_cndmask_b32 v3, v3, v6
	v_cvt_f32_u32_e32 v6, s10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v5, 1, v0
	v_cmp_le_u32_e32 vcc_lo, s8, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_iflag_f32_e32 v3, v6
	v_cndmask_b32_e32 v0, v0, v5, vcc_lo
	v_cvt_f32_u32_e32 v5, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v0, v0, v7
	v_rcp_iflag_f32_e32 v5, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v6, v0, v7
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v3
	v_mul_lo_u32 v3, v6, s2
	v_cvt_u32_f32_e32 v0, v0
	s_sub_i32 s2, 0, s10
	v_mul_f32_e32 v5, 0x4f7ffffe, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v7, s2, v0
	s_sub_i32 s2, 0, s3
	v_sub_nc_u32_e32 v8, v1, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v3, v5
	v_ashrrev_i32_e32 v5, 31, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v7, v0, v7
	v_mul_lo_u32 v9, s2, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v10, v8, v5
	v_add_nc_u32_e32 v0, v0, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v7, v10, v5
	v_mul_hi_u32 v9, v3, v9
	v_xor_b32_e32 v5, s9, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v0, v7, v0
	v_add_nc_u32_e32 v3, v3, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v9, v0, s10
	v_mul_hi_u32 v3, v4, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v7, v7, v9
	v_mul_lo_u32 v3, v3, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_subrev_nc_u32_e32 v10, s10, v7
	v_cmp_le_u32_e32 vcc_lo, s10, v7
	v_add_nc_u32_e32 v9, 1, v0
	v_sub_nc_u32_e32 v3, v4, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v4, v7, v10, vcc_lo
	v_cndmask_b32_e32 v0, v0, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_subrev_nc_u32_e32 v9, s3, v3
	v_cmp_le_u32_e32 vcc_lo, s10, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v7, 1, v0
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x18
	s_load_b64 s[0:1], s[0:1], 0x28
	v_cndmask_b32_e32 v0, v0, v7, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s3, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v0, v0, v5
	v_cndmask_b32_e32 v3, v3, v9, vcc_lo
	v_sub_nc_u32_e32 v0, v0, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v4, s3, v3
	v_cmp_le_u32_e32 vcc_lo, s3, v3
	v_cndmask_b32_e32 v3, v3, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v0, s6
	v_xor_b32_e32 v3, v3, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v8, v8, v4
	v_sub_nc_u32_e32 v3, v3, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[4:5], null, v6, s4, v[3:4]
	v_mad_u64_u32 v[6:7], null, v8, s7, v[0:1]
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v5, 31, v4
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[3:4], 2, v[4:5]
	v_lshlrev_b64 v[5:6], 2, v[6:7]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, s10, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s11, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, s0, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
	global_load_b32 v3, v[3:4], off
	global_load_b32 v4, v[5:6], off
	v_add_co_u32 v0, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v2, v3, v4
	global_store_b32 v[0:1], v2, off
.LBB2_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9multi_veciiiiiPfS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 11
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z9multi_veciiiiiPfS_S_, .Lfunc_end2-_Z9multi_veciiiiiPfS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 748
; NumSgprs: 18
; NumVgprs: 11
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 11
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z14scalareMatricePffS_ ; -- Begin function _Z14scalareMatricePffS_
	.globl	_Z14scalareMatricePffS_
	.p2align	8
	.type	_Z14scalareMatricePffS_,@function
_Z14scalareMatricePffS_:                ; @_Z14scalareMatricePffS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x24
	s_load_b64 s[2:3], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_add_co_u32 v2, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s3, v1, vcc_lo
	global_load_b32 v2, v[2:3], off
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x8
	s_load_b64 s[0:1], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v2, s2, v2
	global_store_b32 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z14scalareMatricePffS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z14scalareMatricePffS_, .Lfunc_end3-_Z14scalareMatricePffS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 148
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z13reduction_rowiiPfS_ ; -- Begin function _Z13reduction_rowiiPfS_
	.globl	_Z13reduction_rowiiPfS_
	.p2align	8
	.type	_Z13reduction_rowiiPfS_,@function
_Z13reduction_rowiiPfS_:                ; @_Z13reduction_rowiiPfS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x24
	s_load_b64 s[4:5], s[0:1], 0x0
	v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v7, 0
	v_mov_b32_e32 v6, 0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	v_mov_b32_e32 v5, 0
	s_and_b32 s2, s2, 0xffff
	s_cmp_lt_i32 s5, 4
	v_mad_u64_u32 v[16:17], null, s15, s2, v[0:1]
	s_load_b128 s[0:3], s[0:1], 0x8
	v_mov_b32_e32 v0, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v17, v16, s5
	v_ashrrev_i32_e32 v18, 31, v17
	s_cbranch_scc1 .LBB4_2
; %bb.1:
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[1:2], 2, v[17:18]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v1, vcc_lo, s2, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v2, vcc_lo, s3, v2, vcc_lo
	global_load_b128 v[4:7], v[1:2], off
.LBB4_2:
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v2, 0
	v_mov_b32_e32 v3, 0
	s_cmp_lt_i32 s5, 8
	s_cbranch_scc1 .LBB4_4
; %bb.3:
	v_lshlrev_b64 v[0:1], 2, v[17:18]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s2, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_load_b128 v[0:3], v[0:1], off offset:16
.LBB4_4:
	v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v13, 0
	v_dual_mov_b32 v12, 0 :: v_dual_mov_b32 v15, 0
	v_mov_b32_e32 v14, 0
	s_cmp_lt_i32 s5, 12
	s_cbranch_scc1 .LBB4_6
; %bb.5:
	v_lshlrev_b64 v[9:10], 2, v[17:18]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v9, vcc_lo, s2, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s3, v10, vcc_lo
	global_load_b128 v[12:15], v[9:10], off offset:32
.LBB4_6:
	v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v10, 0
	v_mov_b32_e32 v11, 0
	s_cmp_lt_i32 s5, 16
	s_cbranch_scc1 .LBB4_8
; %bb.7:
	v_lshlrev_b64 v[8:9], 2, v[17:18]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v8, vcc_lo, s2, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s3, v9, vcc_lo
	global_load_b128 v[8:11], v[8:9], off offset:48
.LBB4_8:
	s_waitcnt lgkmcnt(0)
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s4, v16
	s_cbranch_execz .LBB4_10
; %bb.9:
	s_waitcnt vmcnt(0)
	v_dual_add_f32 v0, v4, v0 :: v_dual_add_f32 v1, v5, v1
	v_dual_add_f32 v4, v12, v8 :: v_dual_add_f32 v5, v13, v9
	v_dual_add_f32 v2, v6, v2 :: v_dual_add_f32 v3, v7, v3
	v_dual_add_f32 v6, v14, v10 :: v_dual_add_f32 v7, v15, v11
	v_ashrrev_i32_e32 v17, 31, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v4, v0, v4 :: v_dual_add_f32 v5, v1, v5
	v_dual_add_f32 v2, v2, v6 :: v_dual_add_f32 v3, v3, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[0:1], 2, v[16:17]
	v_add_f32_e32 v4, v4, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v2, v2, v3
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	v_add_f32_e32 v2, v4, v2
	global_store_b32 v[0:1], v2, off
.LBB4_10:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z13reduction_rowiiPfS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 19
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end4:
	.size	_Z13reduction_rowiiPfS_, .Lfunc_end4-_Z13reduction_rowiiPfS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 464
; NumSgprs: 18
; NumVgprs: 19
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 19
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z9transposeiiPfS_      ; -- Begin function _Z9transposeiiPfS_
	.globl	_Z9transposeiiPfS_
	.p2align	8
	.type	_Z9transposeiiPfS_,@function
_Z9transposeiiPfS_:                     ; @_Z9transposeiiPfS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x24
	s_load_b64 s[2:3], s[0:1], 0x10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[3:4], 2, v[1:2]
	v_add_nc_u32_e32 v5, v1, v2
	v_add_co_u32 v3, vcc_lo, s2, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v4, vcc_lo, s3, v4, vcc_lo
	s_load_b128 s[0:3], s[0:1], 0x0
	v_xor_b32_e32 v5, v5, v2
	global_load_b32 v3, v[3:4], off
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s4, s1, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_add_i32 s5, s1, s4
	v_xor_b32_e32 v2, s4, v2
	s_xor_b32 s5, s5, s4
	v_cvt_f32_u32_e32 v0, s5
	s_sub_i32 s6, 0, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	v_cvt_u32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v4, s6, v0
	v_mul_hi_u32 v4, v0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v0, v4
	v_mul_hi_u32 v0, v5, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v4, v0, s5
	v_sub_nc_u32_e32 v4, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v6, s5, v4
	v_cmp_le_u32_e32 vcc_lo, s5, v4
	v_dual_cndmask_b32 v4, v4, v6 :: v_dual_add_nc_u32 v5, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v0, v0, v5, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s5, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v5, 1, v0
	v_cndmask_b32_e32 v0, v0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v0, v0, v2
	v_sub_nc_u32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, v0, s1
	v_sub_nc_u32_e32 v4, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, v4, s0, v[0:1]
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_add_co_u32 v0, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v3, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9transposeiiPfS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 7
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end5:
	.size	_Z9transposeiiPfS_, .Lfunc_end5-_Z9transposeiiPfS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 348
; NumSgprs: 18
; NumVgprs: 7
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 7
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z6vecsumiPfS_S_        ; -- Begin function _Z6vecsumiPfS_S_
	.globl	_Z6vecsumiPfS_S_
	.p2align	8
	.type	_Z6vecsumiPfS_S_,@function
_Z6vecsumiPfS_S_:                       ; @_Z6vecsumiPfS_S_
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b128 s[4:7], s[0:1], 0x8
	s_load_b64 s[0:1], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_add_co_u32 v2, vcc_lo, s6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s4, v0
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[4:5], off
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, v2, v3
	global_store_b32 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6vecsumiPfS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end6:
	.size	_Z6vecsumiPfS_S_, .Lfunc_end6-_Z6vecsumiPfS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 152
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z6vecdifiPfS_S_        ; -- Begin function _Z6vecdifiPfS_S_
	.globl	_Z6vecdifiPfS_S_
	.p2align	8
	.type	_Z6vecdifiPfS_S_,@function
_Z6vecdifiPfS_S_:                       ; @_Z6vecdifiPfS_S_
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x2c
	s_load_b128 s[4:7], s[0:1], 0x8
	s_load_b64 s[0:1], s[0:1], 0x18
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_add_co_u32 v2, vcc_lo, s6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s4, v0
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[4:5], off
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_sub_f32_e32 v2, v2, v3
	global_store_b32 v[0:1], v2, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6vecdifiPfS_S_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end7:
	.size	_Z6vecdifiPfS_S_, .Lfunc_end7-_Z6vecdifiPfS_S_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 152
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	.str,@object                    ; @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.str:
	.asciz	"%f %f\n"
	.size	.str, 7

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .actual_access:  write_only
        .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8init_veciPf
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z8init_veciPf.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     5
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .offset:         4
        .size:           4
        .value_kind:     by_value
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .actual_access:  write_only
        .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .actual_access:  read_only
        .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
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...

	.end_amdgpu_metadata
