extern "C"
__global__ void rowfilter(
    float* dest, const float* src, const float *w, int N, int C, int H, int W,
    int Win, int Mlow, int Mhigh, int stride) {
    /* dest - output array. should be same shape as input
       src - input array
       w - input kernel. Should be a 1d array
       N, C, H, W - input tensor sizes
       Mlow - idx of most negative filter tap
       Mhigh - idx of most positive filter tap
       rev - used for calculating gradients - need to do correlation, and
        some funny things with the filter.
    */
    for (int i = stride * (blockIdx.x * blockDim.x + threadIdx.x);
         i < N*C*H*W; i += stride * (blockDim.x * gridDim.x)) {
        const int n = i / C / H / W;
        const int c = (i / H / W) % C;
        const int y = (i / W) % H;
        const int x = i % W;
        float value = 0;
        // Use convolution formula: y[n] = sum h[k]*x[n-k]
#pragma unroll
        for (int k = Mlow; k <= Mhigh; k++) {
            int x_in = x - k;

            // handle padding - the above complicated equation
            // simply makes sure that the correct index input is used
            // for symmetric padding. I.e. it should result in x_in going from:
            // -3 -2 -1 | 0  1  2  3  4  5  6 | 7  8  9
            //  to:
            //  2  1  0 | 0  1  2  3  4  5  6 | 6  5  4
            // It also allows padding by more than the input length.
            // The group variable will be:
            // 1  1  1  | 0  0  0  0  0  0  0 | 1  1  1  1  1  1 | 0  0  0 ...
            const int group = x_in >= 0 ? ((x_in / Win) % 2)
                                        : 1-(((-x_in-1)/Win) % 2);

            // This does modulo operation but allowing for negative numbers
            // i.e. we want  -2 % 5 = 3. In python this works but in C we it
            // gives -2.
            // On top of reflecting the signal, we also need to reflect the
            // filter around the boundary (unlike with the forward pass).
            const int res = (x_in % Win + Win) % Win;
            x_in = (group == 1) ? (Win-1) - res : res;

            const int offset = n*C*H*Win + c*H*Win + y*Win + x_in;
            value +=  w[k-Mlow] * src[offset];
        }
        dest[i/stride] = value;
    }
}

extern "C"
__global__ void rowfilter_bwd(
    float* dest, const float* src, const float *w, int N, int C, int H, int W,
    int Win, int Mlow, int Mhigh, int stride) {
    /* dest - output array. should be same shape as input
       src - input array
       w - input kernel. Should be a 1d array
       N, C, H, W - input tensor sizes
       Mlow - idx of most negative filter tap
       Mhigh - idx of most positive filter tap
       rev - used for calculating gradients - need to do correlation, and
        some funny things with the filter.
    */
    for (int i = stride * (blockIdx.x * blockDim.x + threadIdx.x);
         i < N*C*H*W; i += stride * (blockDim.x * gridDim.x)) {
        const int n = i / C / H / W;
        const int c = (i / H / W) % C;
        const int y = (i / W) % H;
        const int x = i % W;
        float value = 0;
        // Use correlation formula: y[n] = sum h[k]*x[n+k]
#pragma unroll
        for (int k = Mlow; k <= Mhigh; k++) {
            int x_in = x + k;
            int k_in = (x_in < 0 || x_in >= Win) ? -k : k;

            // handle padding - the above complicated equation
            // simply makes sure that the correct index input is used
            // for symmetric padding. I.e. it should result in x_in going from:
            // -3 -2 -1 | 0  1  2  3  4  5  6 | 7  8  9
            //  to:
            //  2  1  0 | 0  1  2  3  4  5  6 | 6  5  4
            // It also allows padding by more than the input length.
            // The group variable will be:
            // 1  1  1  | 0  0  0  0  0  0  0 | 1  1  1  1  1  1 | 0  0  0 ...
            const int group = x_in >= 0 ? ((x_in / Win) % 2)
                                        : 1-(((-x_in-1)/Win) % 2);

            // This does modulo operation but allowing for negative numbers
            // i.e. we want  -2 % 5 = 3. In python this works but in C we it
            // gives -2.
            // On top of reflecting the signal, we also need to reflect the
            // filter around the boundary (unlike with the forward pass).
            const int res = (x_in % Win + Win) % Win;
            x_in = (group == 1) ? (Win-1) - res : res;

            const int offset = n*C*H*Win + c*H*Win + y*Win + x_in;
            value += w[k_in - Mlow] * src[offset];
        }
        dest[i/stride] = value;
    }
}

extern "C"
__global__ void colfilter(
    float* dest, const float* src, const float *w, int N, int C, int H, int W,
    int Hin, int Mlow, int Mhigh, int stride) {
    /* dest - output array. should be same shape as input
       src - input array
       w - input kernel. Should be a 1d array
       N, C, H, W - input tensor sizes
       Mlow - idx of most negative filter tap
       Mhigh - idx of most positive filter tap
       rev - used for calculating gradients - need to do correlation, and
        some funny things with the filter.
    */
    for (int i = stride * (blockIdx.x * blockDim.x + threadIdx.x);
         i < N*C*H*W; i += stride * (blockDim.x * gridDim.x)) {
        const int n = i / C / H / W;
        const int c = (i / H / W) % C;
        const int y = (i / W) % H;
        const int x = i % W;
        float value = 0;
        // Use convolution formula: y[n] = sum h[k]*x[n-k]
#pragma unroll
        for (int k = Mlow; k <= Mhigh; k++) {
            int y_in = y - k;

            // handle padding - the above complicated equation
            // simply makes sure that the correct index input is used
            // for symmetric padding. I.e. it should result in x_in going from:
            // -3 -2 -1 | 0  1  2  3  4  5  6 | 7  8  9
            //  to:
            //  2  1  0 | 0  1  2  3  4  5  6 | 6  5  4
            // It also allows padding by more than the input length.
            // The group variable will be:
            // 1  1  1  | 0  0  0  0  0  0  0 | 1  1  1  1  1  1 | 0  0  0 ...
            const int group = y_in >= 0 ? ((y_in / Hin) % 2)
                                        : 1-(((-y_in-1)/Hin) % 2);

            // This does modulo operation but allowing for negative numbers
            // i.e. we want  -2 % 5 = 3. In python this works but in C we it
            // gives -2.
            // On top of reflecting the signal, we also need to reflect the
            // filter around the boundary (unlike with the forward pass).
            const int res = (y_in % Hin + Hin) % Hin;
            y_in = (group == 1) ? (Hin-1) - res : res;

            const int offset = n*C*Hin*W + c*Hin*W + y_in*W + x;
            value +=  w[k-Mlow] * src[offset];
        }
        dest[i/stride] = value;
    }
}

extern "C"
__global__ void colfilter_bwd(
    float* dest, const float* src, const float *w, int N, int C, int H, int W,
    int Hin, int Mlow, int Mhigh, int stride) {
    /* dest - output array. should be same shape as input
       src - input array
       w - input kernel. Should be a 1d array
       N, C, H, W - input tensor sizes
       Mlow - idx of most negative filter tap
       Mhigh - idx of most positive filter tap
       rev - used for calculating gradients - need to do correlation, and
        some funny things with the filter.
    */
    for (int i = stride * (blockIdx.x * blockDim.x + threadIdx.x);
         i < N*C*H*W; i += stride * (blockDim.x * gridDim.x)) {
        const int n = i / C / H / W;
        const int c = (i / H / W) % C;
        const int y = (i / W) % H;
        const int x = i % W;
        float value = 0;

        // Use correlation formula: y[n] = sum h[k]*x[n+k]
#pragma unroll
        for (int k = Mlow; k <= Mhigh; k++) {
            int y_in = y + k;
            int k_in = (y_in < 0 || y_in >= Hin) ? -k : k;

            // handle padding - the above complicated equation
            // simply makes sure that the correct index input is used
            // for symmetric padding. I.e. it should result in x_in going from:
            // -3 -2 -1 | 0  1  2  3  4  5  6 | 7  8  9
            //  to:
            //  2  1  0 | 0  1  2  3  4  5  6 | 6  5  4
            // It also allows padding by more than the input length.
            // The group variable will be:
            // 1  1  1  | 0  0  0  0  0  0  0 | 1  1  1  1  1  1 | 0  0  0 ...
            const int group = y_in >= 0 ? ((y_in / Hin) % 2)
                                        : 1-(((-y_in-1)/Hin) % 2);

            // This does modulo operation but allowing for negative numbers
            // i.e. we want  -2 % 5 = 3. In python this works but in C we it
            // gives -2.
            // On top of reflecting the signal, we also need to reflect the
            // filter around the boundary (unlike with the forward pass).
            const int res = (y_in % Hin + Hin) % Hin;
            y_in = (group == 1) ? (Hin-1) - res : res;

            const int offset = n*C*Hin*W + c*Hin*W + y_in*W + x;
            value += w[k_in - Mlow] * src[offset];
        }
        dest[i/stride] = value;
    }
}


	.file	"tmpxft_0023cace_00000000-6_filters.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z42__device_stub__Z9rowfilterPfPKfS1_iiiiiiiiPfPKfS1_iiiiiiii
	.type	_Z42__device_stub__Z9rowfilterPfPKfS1_iiiiiiiiPfPKfS1_iiiiiiii, @function
_Z42__device_stub__Z9rowfilterPfPKfS1_iiiiiiiiPfPKfS1_iiiiiiii:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	232(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	248(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	56(%rsp)
	.cfi_def_cfa_offset 232
	leaq	rowfilter(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 240
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L2:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z42__device_stub__Z9rowfilterPfPKfS1_iiiiiiiiPfPKfS1_iiiiiiii, .-_Z42__device_stub__Z9rowfilterPfPKfS1_iiiiiiiiPfPKfS1_iiiiiiii
	.globl	rowfilter
	.type	rowfilter, @function
rowfilter:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z9rowfilterPfPKfS1_iiiiiiiiPfPKfS1_iiiiiiii
	.cfi_endproc
.LFE2033:
	.size	rowfilter, .-rowfilter
	.globl	_Z47__device_stub__Z13rowfilter_bwdPfPKfS1_iiiiiiiiPfPKfS1_iiiiiiii
	.type	_Z47__device_stub__Z13rowfilter_bwdPfPKfS1_iiiiiiiiPfPKfS1_iiiiiiii, @function
_Z47__device_stub__Z13rowfilter_bwdPfPKfS1_iiiiiiiiPfPKfS1_iiiiiiii:
.LFB2034:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	232(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	248(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	56(%rsp)
	.cfi_def_cfa_offset 232
	leaq	rowfilter_bwd(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 240
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L8:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2034:
	.size	_Z47__device_stub__Z13rowfilter_bwdPfPKfS1_iiiiiiiiPfPKfS1_iiiiiiii, .-_Z47__device_stub__Z13rowfilter_bwdPfPKfS1_iiiiiiiiPfPKfS1_iiiiiiii
	.globl	rowfilter_bwd
	.type	rowfilter_bwd, @function
rowfilter_bwd:
.LFB2035:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z13rowfilter_bwdPfPKfS1_iiiiiiiiPfPKfS1_iiiiiiii
	.cfi_endproc
.LFE2035:
	.size	rowfilter_bwd, .-rowfilter_bwd
	.globl	_Z42__device_stub__Z9colfilterPfPKfS1_iiiiiiiiPfPKfS1_iiiiiiii
	.type	_Z42__device_stub__Z9colfilterPfPKfS1_iiiiiiiiPfPKfS1_iiiiiiii, @function
_Z42__device_stub__Z9colfilterPfPKfS1_iiiiiiiiPfPKfS1_iiiiiiii:
.LFB2036:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	232(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	248(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	56(%rsp)
	.cfi_def_cfa_offset 232
	leaq	colfilter(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 240
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L13:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2036:
	.size	_Z42__device_stub__Z9colfilterPfPKfS1_iiiiiiiiPfPKfS1_iiiiiiii, .-_Z42__device_stub__Z9colfilterPfPKfS1_iiiiiiiiPfPKfS1_iiiiiiii
	.globl	colfilter
	.type	colfilter, @function
colfilter:
.LFB2037:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z9colfilterPfPKfS1_iiiiiiiiPfPKfS1_iiiiiiii
	.cfi_endproc
.LFE2037:
	.size	colfilter, .-colfilter
	.globl	_Z47__device_stub__Z13colfilter_bwdPfPKfS1_iiiiiiiiPfPKfS1_iiiiiiii
	.type	_Z47__device_stub__Z13colfilter_bwdPfPKfS1_iiiiiiiiPfPKfS1_iiiiiiii, @function
_Z47__device_stub__Z13colfilter_bwdPfPKfS1_iiiiiiiiPfPKfS1_iiiiiiii:
.LFB2038:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movl	%ecx, 20(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 16(%rsp)
	movl	%r9d, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	232(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	248(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	pushq	56(%rsp)
	.cfi_def_cfa_offset 232
	leaq	colfilter_bwd(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 240
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L18:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2038:
	.size	_Z47__device_stub__Z13colfilter_bwdPfPKfS1_iiiiiiiiPfPKfS1_iiiiiiii, .-_Z47__device_stub__Z13colfilter_bwdPfPKfS1_iiiiiiiiPfPKfS1_iiiiiiii
	.globl	colfilter_bwd
	.type	colfilter_bwd, @function
colfilter_bwd:
.LFB2039:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z13colfilter_bwdPfPKfS1_iiiiiiiiPfPKfS1_iiiiiiii
	.cfi_endproc
.LFE2039:
	.size	colfilter_bwd, .-colfilter_bwd
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"colfilter_bwd"
.LC1:
	.string	"colfilter"
.LC2:
	.string	"rowfilter_bwd"
.LC3:
	.string	"rowfilter"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2041:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	colfilter_bwd(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	colfilter(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	rowfilter_bwd(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	rowfilter(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2041:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
extern "C"
__global__ void rowfilter(
    float* dest, const float* src, const float *w, int N, int C, int H, int W,
    int Win, int Mlow, int Mhigh, int stride) {
    /* dest - output array. should be same shape as input
       src - input array
       w - input kernel. Should be a 1d array
       N, C, H, W - input tensor sizes
       Mlow - idx of most negative filter tap
       Mhigh - idx of most positive filter tap
       rev - used for calculating gradients - need to do correlation, and
        some funny things with the filter.
    */
    for (int i = stride * (blockIdx.x * blockDim.x + threadIdx.x);
         i < N*C*H*W; i += stride * (blockDim.x * gridDim.x)) {
        const int n = i / C / H / W;
        const int c = (i / H / W) % C;
        const int y = (i / W) % H;
        const int x = i % W;
        float value = 0;
        // Use convolution formula: y[n] = sum h[k]*x[n-k]
#pragma unroll
        for (int k = Mlow; k <= Mhigh; k++) {
            int x_in = x - k;

            // handle padding - the above complicated equation
            // simply makes sure that the correct index input is used
            // for symmetric padding. I.e. it should result in x_in going from:
            // -3 -2 -1 | 0  1  2  3  4  5  6 | 7  8  9
            //  to:
            //  2  1  0 | 0  1  2  3  4  5  6 | 6  5  4
            // It also allows padding by more than the input length.
            // The group variable will be:
            // 1  1  1  | 0  0  0  0  0  0  0 | 1  1  1  1  1  1 | 0  0  0 ...
            const int group = x_in >= 0 ? ((x_in / Win) % 2)
                                        : 1-(((-x_in-1)/Win) % 2);

            // This does modulo operation but allowing for negative numbers
            // i.e. we want  -2 % 5 = 3. In python this works but in C we it
            // gives -2.
            // On top of reflecting the signal, we also need to reflect the
            // filter around the boundary (unlike with the forward pass).
            const int res = (x_in % Win + Win) % Win;
            x_in = (group == 1) ? (Win-1) - res : res;

            const int offset = n*C*H*Win + c*H*Win + y*Win + x_in;
            value +=  w[k-Mlow] * src[offset];
        }
        dest[i/stride] = value;
    }
}

extern "C"
__global__ void rowfilter_bwd(
    float* dest, const float* src, const float *w, int N, int C, int H, int W,
    int Win, int Mlow, int Mhigh, int stride) {
    /* dest - output array. should be same shape as input
       src - input array
       w - input kernel. Should be a 1d array
       N, C, H, W - input tensor sizes
       Mlow - idx of most negative filter tap
       Mhigh - idx of most positive filter tap
       rev - used for calculating gradients - need to do correlation, and
        some funny things with the filter.
    */
    for (int i = stride * (blockIdx.x * blockDim.x + threadIdx.x);
         i < N*C*H*W; i += stride * (blockDim.x * gridDim.x)) {
        const int n = i / C / H / W;
        const int c = (i / H / W) % C;
        const int y = (i / W) % H;
        const int x = i % W;
        float value = 0;
        // Use correlation formula: y[n] = sum h[k]*x[n+k]
#pragma unroll
        for (int k = Mlow; k <= Mhigh; k++) {
            int x_in = x + k;
            int k_in = (x_in < 0 || x_in >= Win) ? -k : k;

            // handle padding - the above complicated equation
            // simply makes sure that the correct index input is used
            // for symmetric padding. I.e. it should result in x_in going from:
            // -3 -2 -1 | 0  1  2  3  4  5  6 | 7  8  9
            //  to:
            //  2  1  0 | 0  1  2  3  4  5  6 | 6  5  4
            // It also allows padding by more than the input length.
            // The group variable will be:
            // 1  1  1  | 0  0  0  0  0  0  0 | 1  1  1  1  1  1 | 0  0  0 ...
            const int group = x_in >= 0 ? ((x_in / Win) % 2)
                                        : 1-(((-x_in-1)/Win) % 2);

            // This does modulo operation but allowing for negative numbers
            // i.e. we want  -2 % 5 = 3. In python this works but in C we it
            // gives -2.
            // On top of reflecting the signal, we also need to reflect the
            // filter around the boundary (unlike with the forward pass).
            const int res = (x_in % Win + Win) % Win;
            x_in = (group == 1) ? (Win-1) - res : res;

            const int offset = n*C*H*Win + c*H*Win + y*Win + x_in;
            value += w[k_in - Mlow] * src[offset];
        }
        dest[i/stride] = value;
    }
}

extern "C"
__global__ void colfilter(
    float* dest, const float* src, const float *w, int N, int C, int H, int W,
    int Hin, int Mlow, int Mhigh, int stride) {
    /* dest - output array. should be same shape as input
       src - input array
       w - input kernel. Should be a 1d array
       N, C, H, W - input tensor sizes
       Mlow - idx of most negative filter tap
       Mhigh - idx of most positive filter tap
       rev - used for calculating gradients - need to do correlation, and
        some funny things with the filter.
    */
    for (int i = stride * (blockIdx.x * blockDim.x + threadIdx.x);
         i < N*C*H*W; i += stride * (blockDim.x * gridDim.x)) {
        const int n = i / C / H / W;
        const int c = (i / H / W) % C;
        const int y = (i / W) % H;
        const int x = i % W;
        float value = 0;
        // Use convolution formula: y[n] = sum h[k]*x[n-k]
#pragma unroll
        for (int k = Mlow; k <= Mhigh; k++) {
            int y_in = y - k;

            // handle padding - the above complicated equation
            // simply makes sure that the correct index input is used
            // for symmetric padding. I.e. it should result in x_in going from:
            // -3 -2 -1 | 0  1  2  3  4  5  6 | 7  8  9
            //  to:
            //  2  1  0 | 0  1  2  3  4  5  6 | 6  5  4
            // It also allows padding by more than the input length.
            // The group variable will be:
            // 1  1  1  | 0  0  0  0  0  0  0 | 1  1  1  1  1  1 | 0  0  0 ...
            const int group = y_in >= 0 ? ((y_in / Hin) % 2)
                                        : 1-(((-y_in-1)/Hin) % 2);

            // This does modulo operation but allowing for negative numbers
            // i.e. we want  -2 % 5 = 3. In python this works but in C we it
            // gives -2.
            // On top of reflecting the signal, we also need to reflect the
            // filter around the boundary (unlike with the forward pass).
            const int res = (y_in % Hin + Hin) % Hin;
            y_in = (group == 1) ? (Hin-1) - res : res;

            const int offset = n*C*Hin*W + c*Hin*W + y_in*W + x;
            value +=  w[k-Mlow] * src[offset];
        }
        dest[i/stride] = value;
    }
}

extern "C"
__global__ void colfilter_bwd(
    float* dest, const float* src, const float *w, int N, int C, int H, int W,
    int Hin, int Mlow, int Mhigh, int stride) {
    /* dest - output array. should be same shape as input
       src - input array
       w - input kernel. Should be a 1d array
       N, C, H, W - input tensor sizes
       Mlow - idx of most negative filter tap
       Mhigh - idx of most positive filter tap
       rev - used for calculating gradients - need to do correlation, and
        some funny things with the filter.
    */
    for (int i = stride * (blockIdx.x * blockDim.x + threadIdx.x);
         i < N*C*H*W; i += stride * (blockDim.x * gridDim.x)) {
        const int n = i / C / H / W;
        const int c = (i / H / W) % C;
        const int y = (i / W) % H;
        const int x = i % W;
        float value = 0;

        // Use correlation formula: y[n] = sum h[k]*x[n+k]
#pragma unroll
        for (int k = Mlow; k <= Mhigh; k++) {
            int y_in = y + k;
            int k_in = (y_in < 0 || y_in >= Hin) ? -k : k;

            // handle padding - the above complicated equation
            // simply makes sure that the correct index input is used
            // for symmetric padding. I.e. it should result in x_in going from:
            // -3 -2 -1 | 0  1  2  3  4  5  6 | 7  8  9
            //  to:
            //  2  1  0 | 0  1  2  3  4  5  6 | 6  5  4
            // It also allows padding by more than the input length.
            // The group variable will be:
            // 1  1  1  | 0  0  0  0  0  0  0 | 1  1  1  1  1  1 | 0  0  0 ...
            const int group = y_in >= 0 ? ((y_in / Hin) % 2)
                                        : 1-(((-y_in-1)/Hin) % 2);

            // This does modulo operation but allowing for negative numbers
            // i.e. we want  -2 % 5 = 3. In python this works but in C we it
            // gives -2.
            // On top of reflecting the signal, we also need to reflect the
            // filter around the boundary (unlike with the forward pass).
            const int res = (y_in % Hin + Hin) % Hin;
            y_in = (group == 1) ? (Hin-1) - res : res;

            const int offset = n*C*Hin*W + c*Hin*W + y_in*W + x;
            value += w[k_in - Mlow] * src[offset];
        }
        dest[i/stride] = value;
    }
}


	.text
	.file	"filters.hip"
	.globl	__device_stub__rowfilter        # -- Begin function __device_stub__rowfilter
	.type	__device_stub__rowfilter,@function
__device_stub__rowfilter:               # @__device_stub__rowfilter
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$rowfilter, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	__device_stub__rowfilter, .Lfunc_end0-__device_stub__rowfilter
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__rowfilter_bwd    # -- Begin function __device_stub__rowfilter_bwd
	.type	__device_stub__rowfilter_bwd,@function
__device_stub__rowfilter_bwd:           # @__device_stub__rowfilter_bwd
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$rowfilter_bwd, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	__device_stub__rowfilter_bwd, .Lfunc_end1-__device_stub__rowfilter_bwd
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__colfilter        # -- Begin function __device_stub__colfilter
	.type	__device_stub__colfilter,@function
__device_stub__colfilter:               # @__device_stub__colfilter
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$colfilter, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	__device_stub__colfilter, .Lfunc_end2-__device_stub__colfilter
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__colfilter_bwd    # -- Begin function __device_stub__colfilter_bwd
	.type	__device_stub__colfilter_bwd,@function
__device_stub__colfilter_bwd:           # @__device_stub__colfilter_bwd
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	20(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	16(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	12(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$colfilter_bwd, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	__device_stub__colfilter_bwd, .Lfunc_end3-__device_stub__colfilter_bwd
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$rowfilter, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$rowfilter_bwd, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$colfilter, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$colfilter_bwd, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	rowfilter,@object               # @rowfilter
	.section	.rodata,"a",@progbits
	.globl	rowfilter
	.p2align	3, 0x0
rowfilter:
	.quad	__device_stub__rowfilter
	.size	rowfilter, 8

	.type	rowfilter_bwd,@object           # @rowfilter_bwd
	.globl	rowfilter_bwd
	.p2align	3, 0x0
rowfilter_bwd:
	.quad	__device_stub__rowfilter_bwd
	.size	rowfilter_bwd, 8

	.type	colfilter,@object               # @colfilter
	.globl	colfilter
	.p2align	3, 0x0
colfilter:
	.quad	__device_stub__colfilter
	.size	colfilter, 8

	.type	colfilter_bwd,@object           # @colfilter_bwd
	.globl	colfilter_bwd
	.p2align	3, 0x0
colfilter_bwd:
	.quad	__device_stub__colfilter_bwd
	.size	colfilter_bwd, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"rowfilter"
	.size	.L__unnamed_1, 10

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"rowfilter_bwd"
	.size	.L__unnamed_2, 14

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"colfilter"
	.size	.L__unnamed_3, 10

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"colfilter_bwd"
	.size	.L__unnamed_4, 14

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __device_stub__rowfilter
	.addrsig_sym __device_stub__rowfilter_bwd
	.addrsig_sym __device_stub__colfilter
	.addrsig_sym __device_stub__colfilter_bwd
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym rowfilter
	.addrsig_sym rowfilter_bwd
	.addrsig_sym colfilter
	.addrsig_sym colfilter_bwd
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	rowfilter               ; -- Begin function rowfilter
	.globl	rowfilter
	.p2align	8
	.type	rowfilter,@function
rowfilter:                              ; @rowfilter
; %bb.0:
	s_clause 0x1
	s_load_b32 s12, s[0:1], 0x44
	s_load_b256 s[4:11], s[0:1], 0x18
	s_add_u32 s2, s0, 56
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s27, s12, 0xffff
	s_mul_i32 s4, s5, s4
	v_mad_u64_u32 v[1:2], null, s15, s27, v[0:1]
	s_mul_i32 s4, s4, s6
	s_mov_b32 s12, exec_lo
	s_mul_i32 s4, s4, s7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v0, v1, s11
	v_cmpx_gt_i32_e64 s4, v0
	s_cbranch_execz .LBB0_10
; %bb.1:                                ; %.lr.ph70
	s_cmp_le_i32 s9, s10
	s_load_b32 s28, s[2:3], 0x0
	s_cselect_b32 s16, -1, 0
	s_ashr_i32 s17, s7, 31
	s_ashr_i32 s18, s6, 31
	s_add_i32 s12, s7, s17
	s_ashr_i32 s19, s5, 31
	s_xor_b32 s20, s12, s17
	s_add_i32 s12, s6, s18
	v_cvt_f32_u32_e32 v1, s20
	s_xor_b32 s21, s12, s18
	s_add_i32 s13, s5, s19
	v_cvt_f32_u32_e32 v2, s21
	s_ashr_i32 s23, s8, 31
	v_rcp_iflag_f32_e32 v1, v1
	s_ashr_i32 s24, s11, 31
	s_xor_b32 s22, s13, s19
	v_rcp_iflag_f32_e32 v2, v2
	s_add_i32 s12, s8, s23
	s_add_i32 s13, s11, s24
	v_cvt_f32_u32_e32 v3, s22
	s_xor_b32 s25, s12, s23
	s_xor_b32 s26, s13, s24
	v_cvt_f32_u32_e32 v4, s25
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_f32_u32_e32 v5, s26
	s_sub_i32 s2, 0, s20
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	v_rcp_iflag_f32_e32 v3, v3
	v_cvt_u32_f32_e32 v1, v1
	v_rcp_iflag_f32_e32 v4, v4
	v_rcp_iflag_f32_e32 v5, v5
	v_cvt_u32_f32_e32 v2, v2
	s_sub_i32 s3, 0, s26
	v_mul_lo_u32 v6, s2, v1
	s_sub_i32 s2, 0, s21
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s11, s28, s11
	v_mul_lo_u32 v7, s2, v2
	v_mul_f32_e32 v3, 0x4f7ffffe, v3
	s_sub_i32 s2, 0, s22
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v4, 0x4f7ffffe, v4
	s_mul_i32 s11, s11, s27
	v_mul_hi_u32 v6, v1, v6
	v_cvt_u32_f32_e32 v3, v3
	s_mov_b32 s27, 0
	v_mul_hi_u32 v7, v2, v7
	v_mul_f32_e32 v5, 0x4f7ffffe, v5
	v_cvt_u32_f32_e32 v4, v4
	v_mul_lo_u32 v8, s2, v3
	s_sub_i32 s2, 0, s25
	v_dual_mov_b32 v6, 0 :: v_dual_add_nc_u32 v1, v1, v6
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_lo_u32 v9, s2, v4
	v_add_nc_u32_e32 v2, v2, v7
	v_cvt_u32_f32_e32 v5, v5
	s_add_i32 s28, s9, -1
	v_mul_hi_u32 v8, v3, v8
	s_sub_i32 s9, 0, s9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v10, s3, v5
	s_clause 0x1
	s_load_b128 s[12:15], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	v_mul_hi_u32 v9, v4, v9
	v_add_nc_u32_e32 v3, v3, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v10, v5, v10
	v_add_nc_u32_e32 v4, v4, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v5, v10
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
	v_ashrrev_i32_e32 v7, 31, v0
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v9, 0 :: v_dual_add_nc_u32 v8, v0, v7
	v_xor_b32_e32 v8, v8, v7
	s_cbranch_vccnz .LBB0_9
; %bb.3:                                ; %.lr.ph
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v9, v8, v2
	v_mul_hi_u32 v10, v8, v3
	v_xor_b32_e32 v20, s17, v7
	s_mov_b32 s29, s28
	v_mul_lo_u32 v11, v9, s21
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v12, v10, s22
	v_add_nc_u32_e32 v13, 1, v9
	v_sub_nc_u32_e32 v11, v8, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v12, v8, v12
	v_subrev_nc_u32_e32 v15, s21, v11
	v_cmp_le_u32_e32 vcc_lo, s21, v11
	v_add_nc_u32_e32 v14, 1, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_cmp_le_u32_e64 s0, s22, v12
	v_cndmask_b32_e32 v9, v9, v13, vcc_lo
	v_subrev_nc_u32_e32 v13, s22, v12
	v_cndmask_b32_e32 v11, v11, v15, vcc_lo
	v_cndmask_b32_e64 v10, v10, v14, s0
	v_xor_b32_e32 v15, s18, v7
	v_add_nc_u32_e32 v14, 1, v9
	v_cndmask_b32_e64 v12, v12, v13, s0
	v_cmp_le_u32_e32 vcc_lo, s21, v11
	v_add_nc_u32_e32 v13, 1, v10
	v_xor_b32_e32 v11, s19, v7
	v_cndmask_b32_e32 v9, v9, v14, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s22, v12
	v_mul_hi_u32 v12, v8, v1
	v_cndmask_b32_e32 v10, v10, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v9, v9, v15
	v_mul_lo_u32 v13, v12, s20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v10, v10, v11
	v_sub_nc_u32_e32 v9, v9, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v10, v10, v11
	v_ashrrev_i32_e32 v11, 31, v9
	v_sub_nc_u32_e32 v13, v8, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v14, 31, v10
	v_add_nc_u32_e32 v9, v9, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_subrev_nc_u32_e32 v18, s20, v13
	v_cmp_le_u32_e32 vcc_lo, s20, v13
	v_add_nc_u32_e32 v16, 1, v12
	v_xor_b32_e32 v9, v9, v11
	v_xor_b32_e32 v11, s17, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v13, v13, v18 :: v_dual_cndmask_b32 v12, v12, v16
	v_mul_hi_u32 v15, v9, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s20, v13
	v_add_nc_u32_e32 v19, 1, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v16, v15, s20
	v_cndmask_b32_e32 v12, v12, v19, vcc_lo
	v_add_nc_u32_e32 v13, 1, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v12, v12, v20
	v_sub_nc_u32_e32 v9, v9, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_le_u32_e32 vcc_lo, s20, v9
	v_dual_cndmask_b32 v13, v15, v13 :: v_dual_add_nc_u32 v10, v10, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v10, v10, v14
	v_mul_hi_u32 v17, v10, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v18, v17, s21
	v_sub_nc_u32_e32 v10, v10, v18
	v_subrev_nc_u32_e32 v18, s20, v9
	v_add_nc_u32_e32 v16, 1, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e64 s0, s21, v10
	v_cndmask_b32_e32 v9, v9, v18, vcc_lo
	v_subrev_nc_u32_e32 v15, s21, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v16, v17, v16, s0
	v_add_nc_u32_e32 v17, 1, v13
	v_cmp_le_u32_e32 vcc_lo, s20, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v10, v10, v15, s0
	v_add_nc_u32_e32 v15, 1, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v9, v13, v17, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s21, v10
	v_xor_b32_e32 v13, s18, v14
	v_sub_nc_u32_e32 v14, v12, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v9, v9, v11
	v_cndmask_b32_e32 v10, v16, v15, vcc_lo
	v_ashrrev_i32_e32 v12, 31, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v9, v9, v11
	v_xor_b32_e32 v10, v10, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v15, v14, v12
	v_ashrrev_i32_e32 v11, 31, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v10, v10, v13
	v_xor_b32_e32 v15, v15, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v9, v9, v11
	v_ashrrev_i32_e32 v13, 31, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v17, v15, v2
	v_xor_b32_e32 v9, v9, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v16, v9, v3
	v_mul_lo_u32 v17, v17, s21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v16, v16, s22
	v_sub_nc_u32_e32 v15, v15, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_subrev_nc_u32_e32 v17, s21, v15
	v_cmp_le_u32_e64 s0, s21, v15
	v_sub_nc_u32_e32 v9, v9, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v15, v15, v17, s0
	v_subrev_nc_u32_e32 v16, s22, v9
	v_cmp_le_u32_e32 vcc_lo, s22, v9
	v_add_nc_u32_e32 v10, v10, v13
	s_waitcnt lgkmcnt(0)
	s_mov_b64 s[0:1], s[2:3]
	v_cndmask_b32_e32 v9, v9, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v10, v10, v13
	v_xor_b32_e32 v13, s17, v13
	v_subrev_nc_u32_e32 v17, s22, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v18, v10, v1
	v_mul_lo_u32 v19, v18, s20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v10, v10, v19
	v_add_nc_u32_e32 v19, 1, v18
	v_subrev_nc_u32_e32 v20, s20, v10
	v_cmp_le_u32_e32 vcc_lo, s20, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v16, v18, v19, vcc_lo
	v_cndmask_b32_e32 v10, v10, v20, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s22, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v9, v9, v17 :: v_dual_add_nc_u32 v18, 1, v16
	v_cmp_le_u32_e32 vcc_lo, s20, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v9, v9, v11
	v_cndmask_b32_e32 v10, v16, v18, vcc_lo
	v_subrev_nc_u32_e32 v16, s21, v15
	v_cmp_le_u32_e32 vcc_lo, s21, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v9, v9, v11
	v_xor_b32_e32 v10, v10, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v15, v15, v16, vcc_lo
	v_sub_nc_u32_e32 v13, v10, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v15, v15, v12
	v_mad_u64_u32 v[10:11], null, v13, s5, v[9:10]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v9, v15, v12
	v_mad_u64_u32 v[11:12], null, v10, s6, v[9:10]
	v_add_nc_u32_e32 v12, s9, v0
	v_mul_lo_u32 v9, v14, s7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v10, v11, s8
	v_sub_nc_u32_e32 v11, v12, v9
	v_sub_nc_u32_e32 v12, v9, v0
	v_mov_b32_e32 v9, 0
.LBB0_4:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_mov_b32 s30, exec_lo
                                        ; implicit-def: $vgpr13
	s_delay_alu instid0(VALU_DEP_3)
	v_cmpx_gt_i32_e32 0, v11
	s_xor_b32 s30, exec_lo, s30
	s_cbranch_execz .LBB0_6
; %bb.5:                                ;   in Loop: Header=BB0_4 Depth=2
	v_add_nc_u32_e32 v13, s29, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v14, 31, v13
	v_add_nc_u32_e32 v13, v13, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v13, v13, v14
	v_xor_b32_e32 v14, s23, v14
	v_mul_hi_u32 v15, v13, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v16, v15, s25
	v_sub_nc_u32_e32 v13, v13, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v17, s25, v13
	v_cmp_le_u32_e32 vcc_lo, s25, v13
	v_dual_cndmask_b32 v13, v13, v17 :: v_dual_add_nc_u32 v16, 1, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v15, v15, v16, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s25, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v16, 1, v15
	v_cndmask_b32_e32 v13, v15, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v13, v13, v14
	v_sub_nc_u32_e32 v13, v13, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v14, 31, v13
	v_add_nc_u32_e32 v14, v13, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v14, -2, v14
	v_sub_nc_u32_e32 v13, v14, v13
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v13, 1, v13
.LBB0_6:                                ; %Flow
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_or_saveexec_b32 s30, s30
	v_ashrrev_i32_e32 v14, 31, v11
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v15, v11, v14
	s_xor_b32 exec_lo, exec_lo, s30
	s_cbranch_execz .LBB0_8
; %bb.7:                                ;   in Loop: Header=BB0_4 Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v13, v15, v14
	v_mul_hi_u32 v16, v13, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v17, v16, s25
	v_sub_nc_u32_e32 v13, v13, v17
	v_add_nc_u32_e32 v17, 1, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v18, s25, v13
	v_cmp_le_u32_e32 vcc_lo, s25, v13
	v_dual_cndmask_b32 v16, v16, v17 :: v_dual_cndmask_b32 v13, v13, v18
	v_xor_b32_e32 v18, s23, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v17, 1, v16
	v_cmp_le_u32_e32 vcc_lo, s25, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v13, v16, v17, vcc_lo
	v_xor_b32_e32 v13, v13, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v13, v13, v18
	v_lshrrev_b32_e32 v16, 31, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v16, v13, v16
	v_and_b32_e32 v16, -2, v16
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_nc_u32_e32 v13, v13, v16
.LBB0_8:                                ;   in Loop: Header=BB0_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s30
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v15, v15, v14
	s_add_i32 s29, s29, 1
	v_add_nc_u32_e32 v11, -1, v11
	v_mul_hi_u32 v16, v15, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v16, v16, s25
	v_sub_nc_u32_e32 v15, v15, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v16, s25, v15
	v_cmp_le_u32_e32 vcc_lo, s25, v15
	v_cndmask_b32_e32 v15, v15, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v16, s25, v15
	v_cmp_le_u32_e32 vcc_lo, s25, v15
	v_cndmask_b32_e32 v15, v15, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v15, v15, v14
	v_sub_nc_u32_e32 v14, v15, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v14, s8, v14
	v_ashrrev_i32_e32 v15, 31, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v14, v14, v15
	v_xor_b32_e32 v14, v14, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v16, v14, v4
	v_mul_lo_u32 v16, v16, s25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v14, v14, v16
	v_subrev_nc_u32_e32 v16, s25, v14
	v_cmp_le_u32_e32 vcc_lo, s25, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v14, v14, v16, vcc_lo
	v_subrev_nc_u32_e32 v16, s25, v14
	v_cmp_le_u32_e32 vcc_lo, s25, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v14, v14, v16, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 1, v13
	v_xor_b32_e32 v14, v14, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v14, v14, v15
	v_xad_u32 v15, v14, -1, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v13, v14, v15, vcc_lo
	v_add_nc_u32_e32 v13, v13, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v14, 31, v13
	v_lshlrev_b64 v[13:14], 2, v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v13, vcc_lo, s14, v13
	v_add_co_ci_u32_e32 v14, vcc_lo, s15, v14, vcc_lo
	global_load_b32 v15, v6, s[0:1]
	global_load_b32 v13, v[13:14], off
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_cmp_ge_i32 s29, s10
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v9, v15, v13
	s_cbranch_scc0 .LBB0_4
.LBB0_9:                                ; %._crit_edge
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v10, v8, v5
	v_xor_b32_e32 v7, s24, v7
	v_add_nc_u32_e32 v0, s11, v0
	v_mul_lo_u32 v11, v10, s26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v8, v8, v11
	v_subrev_nc_u32_e32 v12, s26, v8
	v_cmp_le_u32_e32 vcc_lo, s26, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v8, v8, v12 :: v_dual_add_nc_u32 v11, 1, v10
	v_cndmask_b32_e32 v10, v10, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s26, v8
	v_add_nc_u32_e32 v11, 1, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v8, v10, v11, vcc_lo
	v_cmp_le_i32_e32 vcc_lo, s4, v0
	v_xor_b32_e32 v8, v8, v7
	s_or_b32 s27, vcc_lo, s27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v7, v8, v7
	v_ashrrev_i32_e32 v8, 31, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v7, s0, s12, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v8, s0, s13, v8, s0
	global_store_b32 v[7:8], v9, off
	s_and_not1_b32 exec_lo, exec_lo, s27
	s_cbranch_execnz .LBB0_2
.LBB0_10:                               ; %Flow111
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel rowfilter
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 21
		.amdhsa_next_free_sgpr 31
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	rowfilter, .Lfunc_end0-rowfilter
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2036
; NumSgprs: 33
; NumVgprs: 21
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 33
; NumVGPRsForWavesPerEU: 21
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	rowfilter_bwd           ; -- Begin function rowfilter_bwd
	.globl	rowfilter_bwd
	.p2align	8
	.type	rowfilter_bwd,@function
rowfilter_bwd:                          ; @rowfilter_bwd
; %bb.0:
	s_clause 0x1
	s_load_b32 s12, s[0:1], 0x44
	s_load_b256 s[4:11], s[0:1], 0x18
	s_add_u32 s2, s0, 56
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s27, s12, 0xffff
	s_mul_i32 s4, s5, s4
	v_mad_u64_u32 v[1:2], null, s15, s27, v[0:1]
	s_mul_i32 s4, s4, s6
	s_mov_b32 s12, exec_lo
	s_mul_i32 s4, s4, s7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v0, v1, s11
	v_cmpx_gt_i32_e64 s4, v0
	s_cbranch_execz .LBB1_10
; %bb.1:                                ; %.lr.ph76
	s_cmp_le_i32 s9, s10
	s_load_b32 s28, s[2:3], 0x0
	s_cselect_b32 s16, -1, 0
	s_ashr_i32 s17, s7, 31
	s_ashr_i32 s18, s6, 31
	s_add_i32 s12, s7, s17
	s_ashr_i32 s19, s5, 31
	s_xor_b32 s20, s12, s17
	s_add_i32 s12, s6, s18
	v_cvt_f32_u32_e32 v1, s20
	s_xor_b32 s21, s12, s18
	s_add_i32 s13, s5, s19
	v_cvt_f32_u32_e32 v2, s21
	s_ashr_i32 s23, s8, 31
	v_rcp_iflag_f32_e32 v1, v1
	s_ashr_i32 s24, s11, 31
	s_xor_b32 s22, s13, s19
	v_rcp_iflag_f32_e32 v2, v2
	s_add_i32 s12, s8, s23
	s_add_i32 s13, s11, s24
	v_cvt_f32_u32_e32 v3, s22
	s_xor_b32 s25, s12, s23
	s_xor_b32 s26, s13, s24
	v_cvt_f32_u32_e32 v4, s25
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	v_cvt_f32_u32_e32 v5, s26
	s_sub_i32 s2, 0, s20
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	v_rcp_iflag_f32_e32 v3, v3
	v_cvt_u32_f32_e32 v1, v1
	v_rcp_iflag_f32_e32 v4, v4
	v_rcp_iflag_f32_e32 v5, v5
	v_cvt_u32_f32_e32 v2, v2
	s_sub_i32 s3, 0, s26
	v_mul_lo_u32 v6, s2, v1
	s_sub_i32 s2, 0, s21
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v7, s2, v2
	s_delay_alu instid0(TRANS32_DEP_3)
	v_mul_f32_e32 v3, 0x4f7ffffe, v3
	s_sub_i32 s2, 0, s22
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v4, 0x4f7ffffe, v4
	v_mul_hi_u32 v6, v1, v6
	v_cvt_u32_f32_e32 v3, v3
	v_mul_hi_u32 v7, v2, v7
	v_mul_f32_e32 v5, 0x4f7ffffe, v5
	v_cvt_u32_f32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v8, s2, v3
	s_sub_i32 s2, 0, s25
	v_add_nc_u32_e32 v1, v1, v6
	v_mul_lo_u32 v9, s2, v4
	v_add_nc_u32_e32 v2, v2, v7
	v_cvt_u32_f32_e32 v5, v5
	v_mul_hi_u32 v8, v3, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_lo_u32 v10, s3, v5
	s_clause 0x1
	s_load_b128 s[12:15], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	v_mul_hi_u32 v9, v4, v9
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s1, s28, s11
	s_mov_b32 s11, 0
	v_add_nc_u32_e32 v3, v3, v8
	s_mul_i32 s1, s1, s27
	s_add_i32 s27, s9, -1
	v_mul_hi_u32 v10, v5, v10
	s_sub_i32 s28, 0, s9
	v_add_nc_u32_e32 v4, v4, v9
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v5, v10
.LBB1_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_4 Depth 2
	v_ashrrev_i32_e32 v6, 31, v0
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v8, 0 :: v_dual_add_nc_u32 v7, v0, v6
	v_xor_b32_e32 v7, v7, v6
	s_cbranch_vccnz .LBB1_9
; %bb.3:                                ; %.lr.ph
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v8, v7, v2
	v_mul_hi_u32 v9, v7, v3
	v_xor_b32_e32 v19, s17, v6
	s_mov_b32 s29, s28
	s_mov_b32 s30, s27
	v_mul_lo_u32 v10, v8, s21
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v11, v9, s22
	v_add_nc_u32_e32 v12, 1, v8
	v_sub_nc_u32_e32 v10, v7, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v11, v7, v11
	v_subrev_nc_u32_e32 v14, s21, v10
	v_cmp_le_u32_e32 vcc_lo, s21, v10
	v_add_nc_u32_e32 v13, 1, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_cmp_le_u32_e64 s0, s22, v11
	v_cndmask_b32_e32 v8, v8, v12, vcc_lo
	v_subrev_nc_u32_e32 v12, s22, v11
	v_cndmask_b32_e32 v10, v10, v14, vcc_lo
	v_cndmask_b32_e64 v9, v9, v13, s0
	v_xor_b32_e32 v14, s18, v6
	v_add_nc_u32_e32 v13, 1, v8
	v_cndmask_b32_e64 v11, v11, v12, s0
	v_cmp_le_u32_e32 vcc_lo, s21, v10
	v_add_nc_u32_e32 v12, 1, v9
	v_xor_b32_e32 v10, s19, v6
	v_cndmask_b32_e32 v8, v8, v13, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s22, v11
	v_mul_hi_u32 v11, v7, v1
	v_cndmask_b32_e32 v9, v9, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v8, v8, v14
	v_mul_lo_u32 v12, v11, s20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v9, v9, v10
	v_sub_nc_u32_e32 v8, v8, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v9, v9, v10
	v_ashrrev_i32_e32 v10, 31, v8
	v_sub_nc_u32_e32 v12, v7, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v13, 31, v9
	v_add_nc_u32_e32 v8, v8, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_subrev_nc_u32_e32 v17, s20, v12
	v_cmp_le_u32_e32 vcc_lo, s20, v12
	v_add_nc_u32_e32 v15, 1, v11
	v_xor_b32_e32 v8, v8, v10
	v_xor_b32_e32 v10, s17, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v12, v12, v17 :: v_dual_cndmask_b32 v11, v11, v15
	v_mul_hi_u32 v14, v8, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s20, v12
	v_add_nc_u32_e32 v18, 1, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v15, v14, s20
	v_cndmask_b32_e32 v11, v11, v18, vcc_lo
	v_add_nc_u32_e32 v12, 1, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v11, v11, v19
	v_sub_nc_u32_e32 v8, v8, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_le_u32_e32 vcc_lo, s20, v8
	v_dual_cndmask_b32 v12, v14, v12 :: v_dual_add_nc_u32 v9, v9, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v9, v9, v13
	v_mul_hi_u32 v16, v9, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v17, v16, s21
	v_sub_nc_u32_e32 v9, v9, v17
	v_subrev_nc_u32_e32 v17, s20, v8
	v_add_nc_u32_e32 v15, 1, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e64 s0, s21, v9
	v_cndmask_b32_e32 v8, v8, v17, vcc_lo
	v_subrev_nc_u32_e32 v14, s21, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v15, v16, v15, s0
	v_add_nc_u32_e32 v16, 1, v12
	v_cmp_le_u32_e32 vcc_lo, s20, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v9, v9, v14, s0
	v_add_nc_u32_e32 v14, 1, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v8, v12, v16, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s21, v9
	v_xor_b32_e32 v12, s18, v13
	v_sub_nc_u32_e32 v13, v11, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v8, v8, v10
	v_cndmask_b32_e32 v9, v15, v14, vcc_lo
	v_ashrrev_i32_e32 v11, 31, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v8, v8, v10
	v_xor_b32_e32 v9, v9, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v14, v13, v11
	v_ashrrev_i32_e32 v10, 31, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v9, v9, v12
	v_xor_b32_e32 v14, v14, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v8, v8, v10
	v_ashrrev_i32_e32 v12, 31, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v16, v14, v2
	v_xor_b32_e32 v8, v8, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v15, v8, v3
	v_mul_lo_u32 v16, v16, s21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v15, v15, s22
	v_sub_nc_u32_e32 v14, v14, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_subrev_nc_u32_e32 v16, s21, v14
	v_cmp_le_u32_e64 s0, s21, v14
	v_sub_nc_u32_e32 v8, v8, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v14, v14, v16, s0
	v_subrev_nc_u32_e32 v15, s22, v8
	v_cmp_le_u32_e32 vcc_lo, s22, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v8, v8, v15 :: v_dual_add_nc_u32 v9, v9, v12
	v_xor_b32_e32 v9, v9, v12
	v_xor_b32_e32 v12, s17, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_subrev_nc_u32_e32 v16, s22, v8
	v_mul_hi_u32 v17, v9, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v18, v17, s20
	v_sub_nc_u32_e32 v9, v9, v18
	v_add_nc_u32_e32 v18, 1, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_subrev_nc_u32_e32 v19, s20, v9
	v_cmp_le_u32_e32 vcc_lo, s20, v9
	v_cndmask_b32_e32 v15, v17, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v9, v9, v19, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s22, v8
	v_dual_cndmask_b32 v8, v8, v16 :: v_dual_add_nc_u32 v17, 1, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s20, v9
	v_xor_b32_e32 v8, v8, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v9, v15, v17, vcc_lo
	v_subrev_nc_u32_e32 v15, s21, v14
	v_cmp_le_u32_e32 vcc_lo, s21, v14
	v_sub_nc_u32_e32 v8, v8, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v9, v9, v12
	v_cndmask_b32_e32 v14, v14, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v12, v9, v12
	v_xor_b32_e32 v14, v14, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[9:10], null, v12, s5, v[8:9]
	v_sub_nc_u32_e32 v8, v14, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[10:11], null, v9, s6, v[8:9]
	v_mul_lo_u32 v8, v13, s7
	v_mul_lo_u32 v9, v10, s8
	s_delay_alu instid0(VALU_DEP_2)
	v_sub_nc_u32_e32 v10, v0, v8
	v_xad_u32 v11, v0, -1, v8
	v_mov_b32_e32 v8, 0
.LBB1_4:                                ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v15, s30, v10
	s_mov_b32 s31, exec_lo
                                        ; implicit-def: $vgpr13
	v_add_nc_u32_e32 v12, 1, v15
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_i32_e32 vcc_lo, -1, v12
	v_cmpx_gt_i32_e32 0, v12
	s_xor_b32 s31, exec_lo, s31
	s_cbranch_execz .LBB1_6
; %bb.5:                                ;   in Loop: Header=BB1_4 Depth=2
	v_add_nc_u32_e32 v13, s29, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v14, 31, v13
	v_add_nc_u32_e32 v13, v13, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v13, v13, v14
	v_xor_b32_e32 v14, s23, v14
	v_mul_hi_u32 v16, v13, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v17, v16, s25
	v_sub_nc_u32_e32 v13, v13, v17
	v_add_nc_u32_e32 v17, 1, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_subrev_nc_u32_e32 v18, s25, v13
	v_cmp_le_u32_e64 s0, s25, v13
	v_cndmask_b32_e64 v16, v16, v17, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v13, v13, v18, s0
	v_add_nc_u32_e32 v17, 1, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u32_e64 s0, s25, v13
	v_cndmask_b32_e64 v13, v16, v17, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v13, v13, v14
	v_sub_nc_u32_e32 v13, v13, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v14, 31, v13
	v_add_nc_u32_e32 v14, v13, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v14, -2, v14
	v_sub_nc_u32_e32 v13, v14, v13
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v13, 1, v13
.LBB1_6:                                ; %Flow
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_or_saveexec_b32 s31, s31
	v_ashrrev_i32_e32 v14, 31, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v15, v15, v14, 1
	s_xor_b32 exec_lo, exec_lo, s31
	s_cbranch_execz .LBB1_8
; %bb.7:                                ;   in Loop: Header=BB1_4 Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v13, v15, v14
	v_mul_hi_u32 v16, v13, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v17, v16, s25
	v_sub_nc_u32_e32 v13, v13, v17
	v_add_nc_u32_e32 v17, 1, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_subrev_nc_u32_e32 v18, s25, v13
	v_cmp_le_u32_e64 s0, s25, v13
	v_cndmask_b32_e64 v16, v16, v17, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v13, v13, v18, s0
	v_xor_b32_e32 v18, s23, v14
	v_add_nc_u32_e32 v17, 1, v16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u32_e64 s0, s25, v13
	v_cndmask_b32_e64 v13, v16, v17, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v13, v13, v18
	v_sub_nc_u32_e32 v13, v13, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v16, 31, v13
	v_add_nc_u32_e32 v16, v13, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v16, -2, v16
	v_sub_nc_u32_e32 v13, v13, v16
.LBB1_8:                                ;   in Loop: Header=BB1_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s31
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v15, v15, v14
	s_add_i32 s30, s30, 1
	v_mul_hi_u32 v16, v15, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v16, v16, s25
	v_sub_nc_u32_e32 v15, v15, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_subrev_nc_u32_e32 v16, s25, v15
	v_cmp_le_u32_e64 s0, s25, v15
	v_cndmask_b32_e64 v15, v15, v16, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_subrev_nc_u32_e32 v16, s25, v15
	v_cmp_le_u32_e64 s0, s25, v15
	v_cndmask_b32_e64 v15, v15, v16, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v15, v15, v14
	v_sub_nc_u32_e32 v14, v15, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v14, s8, v14
	v_ashrrev_i32_e32 v15, 31, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v14, v14, v15
	v_xor_b32_e32 v14, v14, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v16, v14, v4
	v_mul_lo_u32 v16, v16, s25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v14, v14, v16
	v_subrev_nc_u32_e32 v16, s25, v14
	v_cmp_le_u32_e64 s0, s25, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v14, v14, v16, s0
	v_subrev_nc_u32_e32 v16, s25, v14
	v_cmp_le_u32_e64 s0, s25, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v14, v14, v16, s0
	v_cmp_gt_i32_e64 s0, s8, v12
	v_xor_b32_e32 v14, v14, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_and_b32 vcc_lo, vcc_lo, s0
	v_sub_nc_u32_e32 v14, v14, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_xad_u32 v15, v14, -1, s8
	v_mov_b32_e32 v12, s30
	v_cndmask_b32_e32 v12, s29, v12, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 1, v13
	s_add_i32 s29, s29, -1
	s_cmp_ge_i32 s30, s10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_subrev_nc_u32_e32 v12, s9, v12
	v_cndmask_b32_e32 v13, v14, v15, vcc_lo
	v_add_nc_u32_e32 v14, v13, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v13, 31, v12
	v_ashrrev_i32_e32 v15, 31, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	v_lshlrev_b64 v[14:15], 2, v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v12, vcc_lo, s2, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, s3, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v14, vcc_lo, s14, v14
	v_add_co_ci_u32_e32 v15, vcc_lo, s15, v15, vcc_lo
	global_load_b32 v12, v[12:13], off
	global_load_b32 v13, v[14:15], off
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v8, v12, v13
	s_cbranch_scc0 .LBB1_4
.LBB1_9:                                ; %._crit_edge
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v9, v7, v5
	v_xor_b32_e32 v6, s24, v6
	v_add_nc_u32_e32 v0, s1, v0
	v_mul_lo_u32 v10, v9, s26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v7, v7, v10
	v_subrev_nc_u32_e32 v11, s26, v7
	v_cmp_le_u32_e32 vcc_lo, s26, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v7, v7, v11 :: v_dual_add_nc_u32 v10, 1, v9
	v_cndmask_b32_e32 v9, v9, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s26, v7
	v_add_nc_u32_e32 v10, 1, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v7, v9, v10, vcc_lo
	v_cmp_le_i32_e32 vcc_lo, s4, v0
	v_xor_b32_e32 v7, v7, v6
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v6, v7, v6
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_add_co_u32 v6, s0, s12, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v7, s0, s13, v7, s0
	global_store_b32 v[6:7], v8, off
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB1_2
.LBB1_10:                               ; %Flow117
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel rowfilter_bwd
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 20
		.amdhsa_next_free_sgpr 32
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	rowfilter_bwd, .Lfunc_end1-rowfilter_bwd
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2176
; NumSgprs: 34
; NumVgprs: 20
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 34
; NumVGPRsForWavesPerEU: 20
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	colfilter               ; -- Begin function colfilter
	.globl	colfilter
	.p2align	8
	.type	colfilter,@function
colfilter:                              ; @colfilter
; %bb.0:
	s_clause 0x1
	s_load_b32 s12, s[0:1], 0x44
	s_load_b256 s[4:11], s[0:1], 0x18
	s_add_u32 s2, s0, 56
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s26, s12, 0xffff
	s_mul_i32 s4, s5, s4
	v_mad_u64_u32 v[1:2], null, s15, s26, v[0:1]
	s_mul_i32 s4, s4, s6
	s_mov_b32 s12, exec_lo
	s_mul_i32 s4, s4, s7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v1, v1, s11
	v_cmpx_gt_i32_e64 s4, v1
	s_cbranch_execz .LBB2_10
; %bb.1:                                ; %.lr.ph70
	s_cmp_le_i32 s9, s10
	s_load_b32 s27, s[2:3], 0x0
	s_cselect_b32 s16, -1, 0
	s_ashr_i32 s17, s7, 31
	s_ashr_i32 s18, s6, 31
	s_add_i32 s12, s7, s17
	s_add_i32 s6, s6, s18
	s_xor_b32 s20, s12, s17
	s_ashr_i32 s19, s5, 31
	v_cvt_f32_u32_e32 v0, s20
	s_xor_b32 s6, s6, s18
	s_add_i32 s12, s5, s19
	v_cvt_f32_u32_e32 v2, s6
	s_xor_b32 s21, s12, s19
	v_rcp_iflag_f32_e32 v0, v0
	v_cvt_f32_u32_e32 v3, s21
	s_ashr_i32 s22, s8, 31
	s_ashr_i32 s23, s11, 31
	v_rcp_iflag_f32_e32 v2, v2
	s_add_i32 s12, s8, s22
	s_add_i32 s13, s11, s23
	v_rcp_iflag_f32_e32 v3, v3
	s_xor_b32 s24, s12, s22
	s_xor_b32 s25, s13, s23
	v_cvt_f32_u32_e32 v4, s24
	v_cvt_f32_u32_e32 v5, s25
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	s_sub_i32 s2, 0, s20
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	v_rcp_iflag_f32_e32 v4, v4
	v_rcp_iflag_f32_e32 v5, v5
	v_mul_f32_e32 v3, 0x4f7ffffe, v3
	v_cvt_u32_f32_e32 v0, v0
	v_cvt_u32_f32_e32 v7, v2
	s_sub_i32 s3, 0, s25
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s11, s27, s11
	s_add_i32 s27, s9, -1
	v_mul_lo_u32 v6, s2, v0
	s_sub_i32 s2, 0, s6
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, 0x4f7ffffe, v4
	v_mul_f32_e32 v4, 0x4f7ffffe, v5
	v_cvt_u32_f32_e32 v5, v3
	v_mul_lo_u32 v3, s2, v7
	s_sub_i32 s2, 0, s21
	s_mul_i32 s11, s11, s26
	v_cvt_u32_f32_e32 v9, v4
	v_mul_hi_u32 v6, v0, v6
	s_mov_b32 s26, 0
	s_sub_i32 s9, 0, s9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v3, v7, v3
	v_mul_lo_u32 v10, s3, v9
	v_add_nc_u32_e32 v3, v7, v3
	v_mov_b32_e32 v7, 0
	v_cvt_u32_f32_e32 v8, v2
	v_mul_lo_u32 v2, s2, v5
	s_sub_i32 s2, 0, s24
	v_mul_hi_u32 v10, v9, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v4, s2, v8
	s_clause 0x1
	s_load_b128 s[12:15], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	v_mul_hi_u32 v11, v5, v2
	v_add_nc_u32_e32 v2, v0, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v6, v9, v10
	v_mul_hi_u32 v12, v8, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v5, v11
	v_add_nc_u32_e32 v5, v8, v12
.LBB2_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB2_4 Depth 2
	v_ashrrev_i32_e32 v8, 31, v1
	v_mov_b32_e32 v10, 0
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v1, v8
	v_xor_b32_e32 v9, v0, v8
	s_cbranch_vccnz .LBB2_9
; %bb.3:                                ; %.lr.ph
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v0, v9, v3
	v_mul_hi_u32 v10, v9, v4
	v_xor_b32_e32 v20, s17, v8
	s_mov_b32 s28, s27
	v_mul_lo_u32 v11, v0, s6
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v12, v10, s21
	v_add_nc_u32_e32 v13, 1, v0
	v_sub_nc_u32_e32 v11, v9, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v12, v9, v12
	v_subrev_nc_u32_e32 v15, s6, v11
	v_cmp_le_u32_e32 vcc_lo, s6, v11
	v_add_nc_u32_e32 v14, 1, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_le_u32_e64 s0, s21, v12
	v_cndmask_b32_e32 v11, v11, v15, vcc_lo
	v_xor_b32_e32 v15, s18, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v10, v10, v14, s0
	v_cndmask_b32_e32 v0, v0, v13, vcc_lo
	v_subrev_nc_u32_e32 v13, s21, v12
	v_cmp_le_u32_e32 vcc_lo, s6, v11
	v_xor_b32_e32 v11, s19, v8
	v_cndmask_b32_e64 v12, v12, v13, s0
	v_add_nc_u32_e32 v13, 1, v10
	v_add_nc_u32_e32 v14, 1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v0, v0, v14, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s21, v12
	v_mul_hi_u32 v12, v9, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v0, v0, v15
	v_cndmask_b32_e32 v10, v10, v13, vcc_lo
	v_mul_lo_u32 v13, v12, s20
	v_add_nc_u32_e32 v16, 1, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v0, v0, v15
	v_sub_nc_u32_e32 v13, v9, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_le_u32_e32 vcc_lo, s20, v13
	v_subrev_nc_u32_e32 v18, s20, v13
	v_dual_cndmask_b32 v12, v12, v16 :: v_dual_cndmask_b32 v13, v13, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v19, 1, v12
	v_xor_b32_e32 v10, v10, v11
	v_cmp_le_u32_e32 vcc_lo, s20, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v10, v10, v11
	v_ashrrev_i32_e32 v11, 31, v0
	v_ashrrev_i32_e32 v14, 31, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v0, v0, v11
	v_add_nc_u32_e32 v10, v10, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v0, v0, v11
	v_xor_b32_e32 v11, s17, v11
	v_xor_b32_e32 v10, v10, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v15, v0, v2
	v_mul_hi_u32 v17, v10, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v16, v15, s20
	v_add_nc_u32_e32 v13, 1, v15
	v_cndmask_b32_e32 v12, v12, v19, vcc_lo
	v_mul_lo_u32 v18, v17, s6
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v0, v0, v16
	v_add_nc_u32_e32 v16, 1, v17
	v_sub_nc_u32_e32 v10, v10, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_subrev_nc_u32_e32 v18, s20, v0
	v_cmp_le_u32_e32 vcc_lo, s20, v0
	v_cmp_le_u32_e64 s0, s6, v10
	v_cndmask_b32_e32 v13, v15, v13, vcc_lo
	v_subrev_nc_u32_e32 v15, s6, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v16, v17, v16, s0
	v_dual_cndmask_b32 v0, v0, v18 :: v_dual_add_nc_u32 v17, 1, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v10, v10, v15, s0
	v_xor_b32_e32 v12, v12, v20
	v_add_nc_u32_e32 v15, 1, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_cmp_le_u32_e32 vcc_lo, s20, v0
	v_cndmask_b32_e32 v0, v13, v17, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s6, v10
	v_xor_b32_e32 v13, s18, v14
	v_cndmask_b32_e32 v10, v16, v15, vcc_lo
	v_xor_b32_e32 v10, v10, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v10, v10, v13
	v_ashrrev_i32_e32 v14, 31, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v10, v10, v14
	v_xor_b32_e32 v10, v10, v14
	v_xor_b32_e32 v14, s17, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v18, v10, v2
	v_mul_lo_u32 v19, v18, s20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v10, v10, v19
	v_add_nc_u32_e32 v19, 1, v18
	v_xor_b32_e32 v0, v0, v11
	v_sub_nc_u32_e32 v0, v0, v11
	v_sub_nc_u32_e32 v11, v12, v20
	v_subrev_nc_u32_e32 v20, s20, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v12, 31, v0
	v_ashrrev_i32_e32 v13, 31, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v0, v0, v12
	v_add_nc_u32_e32 v15, v11, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v0, v0, v12
	v_xor_b32_e32 v15, v15, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v16, v0, v4
	v_mul_hi_u32 v17, v15, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v16, v16, s21
	v_mul_lo_u32 v17, v17, s6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v0, v0, v16
	v_sub_nc_u32_e32 v15, v15, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_subrev_nc_u32_e32 v16, s21, v0
	v_cmp_le_u32_e32 vcc_lo, s21, v0
	v_subrev_nc_u32_e32 v17, s6, v15
	v_cmp_le_u32_e64 s0, s6, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v0, v0, v16, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s20, v10
	v_cndmask_b32_e64 v15, v15, v17, s0
	s_waitcnt lgkmcnt(0)
	s_mov_b64 s[0:1], s[2:3]
	v_subrev_nc_u32_e32 v17, s21, v0
	v_cndmask_b32_e32 v16, v18, v19, vcc_lo
	v_cndmask_b32_e32 v10, v10, v20, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s21, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v18, 1, v16
	v_cndmask_b32_e32 v0, v0, v17, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s20, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v0, v0, v12
	v_cndmask_b32_e32 v10, v16, v18, vcc_lo
	v_subrev_nc_u32_e32 v16, s6, v15
	v_cmp_le_u32_e32 vcc_lo, s6, v15
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v0, v0, v12
	v_xor_b32_e32 v10, v10, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v15, v15, v16, vcc_lo
	v_sub_nc_u32_e32 v12, v10, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v14, v15, v13
	v_mul_lo_u32 v15, v11, s7
	v_mad_u64_u32 v[10:11], null, v12, s5, v[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v12, s9, v14
	v_sub_nc_u32_e32 v0, v1, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v12, v12, v13
	v_mul_lo_u32 v11, v10, s8
	v_sub_nc_u32_e32 v13, v13, v14
	v_mov_b32_e32 v10, 0
.LBB2_4:                                ;   Parent Loop BB2_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_mov_b32 s29, exec_lo
                                        ; implicit-def: $vgpr14
	v_cmpx_gt_i32_e32 0, v12
	s_xor_b32 s29, exec_lo, s29
	s_cbranch_execz .LBB2_6
; %bb.5:                                ;   in Loop: Header=BB2_4 Depth=2
	v_add_nc_u32_e32 v14, s28, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v15, 31, v14
	v_add_nc_u32_e32 v14, v14, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v14, v14, v15
	v_xor_b32_e32 v15, s22, v15
	v_mul_hi_u32 v16, v14, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v17, v16, s24
	v_sub_nc_u32_e32 v14, v14, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v18, s24, v14
	v_cmp_le_u32_e32 vcc_lo, s24, v14
	v_dual_cndmask_b32 v14, v14, v18 :: v_dual_add_nc_u32 v17, 1, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v16, v16, v17, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s24, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v17, 1, v16
	v_cndmask_b32_e32 v14, v16, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v14, v14, v15
	v_sub_nc_u32_e32 v14, v14, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v15, 31, v14
	v_add_nc_u32_e32 v15, v14, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v15, -2, v15
	v_sub_nc_u32_e32 v14, v15, v14
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v14, 1, v14
.LBB2_6:                                ; %Flow
                                        ;   in Loop: Header=BB2_4 Depth=2
	s_or_saveexec_b32 s29, s29
	v_ashrrev_i32_e32 v15, 31, v12
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v16, v12, v15
	s_xor_b32 exec_lo, exec_lo, s29
	s_cbranch_execz .LBB2_8
; %bb.7:                                ;   in Loop: Header=BB2_4 Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v14, v16, v15
	v_mul_hi_u32 v17, v14, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v18, v17, s24
	v_sub_nc_u32_e32 v14, v14, v18
	v_add_nc_u32_e32 v18, 1, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v19, s24, v14
	v_cmp_le_u32_e32 vcc_lo, s24, v14
	v_dual_cndmask_b32 v17, v17, v18 :: v_dual_cndmask_b32 v14, v14, v19
	v_xor_b32_e32 v19, s22, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v18, 1, v17
	v_cmp_le_u32_e32 vcc_lo, s24, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v14, v17, v18, vcc_lo
	v_xor_b32_e32 v14, v14, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v14, v14, v19
	v_lshrrev_b32_e32 v17, 31, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v17, v14, v17
	v_and_b32_e32 v17, -2, v17
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_nc_u32_e32 v14, v14, v17
.LBB2_8:                                ;   in Loop: Header=BB2_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s29
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v16, v16, v15
	s_add_i32 s28, s28, 1
	v_add_nc_u32_e32 v12, -1, v12
	v_mul_hi_u32 v17, v16, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v17, v17, s24
	v_sub_nc_u32_e32 v16, v16, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v17, s24, v16
	v_cmp_le_u32_e32 vcc_lo, s24, v16
	v_cndmask_b32_e32 v16, v16, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_subrev_nc_u32_e32 v17, s24, v16
	v_cmp_le_u32_e32 vcc_lo, s24, v16
	v_cndmask_b32_e32 v16, v16, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v16, v16, v15
	v_sub_nc_u32_e32 v15, v16, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v15, s8, v15
	v_ashrrev_i32_e32 v16, 31, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v15, v15, v16
	v_xor_b32_e32 v15, v15, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v17, v15, v5
	v_mul_lo_u32 v17, v17, s24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v15, v15, v17
	v_subrev_nc_u32_e32 v17, s24, v15
	v_cmp_le_u32_e32 vcc_lo, s24, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v15, v15, v17, vcc_lo
	v_subrev_nc_u32_e32 v17, s24, v15
	v_cmp_le_u32_e32 vcc_lo, s24, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v15, v15, v17, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 1, v14
	v_xor_b32_e32 v15, v15, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v15, v15, v16
	v_xad_u32 v16, v15, -1, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v14, v15, v16, vcc_lo
	v_add_nc_u32_e32 v16, v14, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[14:15], null, v16, s7, v[0:1]
	v_ashrrev_i32_e32 v15, 31, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[14:15], 2, v[14:15]
	v_add_co_u32 v14, vcc_lo, s14, v14
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v15, vcc_lo, s15, v15, vcc_lo
	global_load_b32 v16, v7, s[0:1]
	global_load_b32 v14, v[14:15], off
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_cmp_ge_i32 s28, s10
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v10, v16, v14
	s_cbranch_scc0 .LBB2_4
.LBB2_9:                                ; %._crit_edge
                                        ;   in Loop: Header=BB2_2 Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v0, v9, v6
	v_xor_b32_e32 v8, s23, v8
	v_add_nc_u32_e32 v1, s11, v1
	v_mul_lo_u32 v11, v0, s25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v9, v9, v11
	v_add_nc_u32_e32 v11, 1, v0
	v_subrev_nc_u32_e32 v12, s25, v9
	v_cmp_le_u32_e32 vcc_lo, s25, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v0, v0, v11 :: v_dual_cndmask_b32 v9, v9, v12
	v_add_nc_u32_e32 v11, 1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s25, v9
	v_cndmask_b32_e32 v0, v0, v11, vcc_lo
	v_cmp_le_i32_e32 vcc_lo, s4, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v0, v0, v8
	s_or_b32 s26, vcc_lo, s26
	v_sub_nc_u32_e32 v8, v0, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v9, 31, v8
	v_lshlrev_b64 v[8:9], 2, v[8:9]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v8, s0, s12, v8
	v_add_co_ci_u32_e64 v9, s0, s13, v9, s0
	global_store_b32 v[8:9], v10, off
	s_and_not1_b32 exec_lo, exec_lo, s26
	s_cbranch_execnz .LBB2_2
.LBB2_10:                               ; %Flow111
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel colfilter
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 21
		.amdhsa_next_free_sgpr 30
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	colfilter, .Lfunc_end2-colfilter
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2024
; NumSgprs: 32
; NumVgprs: 21
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 32
; NumVGPRsForWavesPerEU: 21
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	colfilter_bwd           ; -- Begin function colfilter_bwd
	.globl	colfilter_bwd
	.p2align	8
	.type	colfilter_bwd,@function
colfilter_bwd:                          ; @colfilter_bwd
; %bb.0:
	s_clause 0x1
	s_load_b32 s12, s[0:1], 0x44
	s_load_b256 s[4:11], s[0:1], 0x18
	s_add_u32 s2, s0, 56
	s_addc_u32 s3, s1, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s26, s12, 0xffff
	s_mul_i32 s4, s5, s4
	v_mad_u64_u32 v[1:2], null, s15, s26, v[0:1]
	s_mul_i32 s4, s4, s6
	s_mov_b32 s12, exec_lo
	s_mul_i32 s4, s4, s7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v1, v1, s11
	v_cmpx_gt_i32_e64 s4, v1
	s_cbranch_execz .LBB3_10
; %bb.1:                                ; %.lr.ph76
	s_cmp_le_i32 s9, s10
	s_load_b32 s27, s[2:3], 0x0
	s_cselect_b32 s16, -1, 0
	s_ashr_i32 s18, s6, 31
	s_ashr_i32 s17, s7, 31
	s_add_i32 s6, s6, s18
	s_add_i32 s12, s7, s17
	s_ashr_i32 s19, s5, 31
	s_xor_b32 s6, s6, s18
	s_xor_b32 s20, s12, s17
	s_add_i32 s12, s5, s19
	s_ashr_i32 s22, s8, 31
	v_cvt_f32_u32_e32 v2, s6
	s_xor_b32 s21, s12, s19
	s_add_i32 s12, s8, s22
	v_cvt_f32_u32_e32 v0, s20
	s_xor_b32 s24, s12, s22
	s_ashr_i32 s23, s11, 31
	v_rcp_iflag_f32_e32 v2, v2
	v_cvt_f32_u32_e32 v4, s24
	s_add_i32 s13, s11, s23
	v_cvt_f32_u32_e32 v3, s21
	s_xor_b32 s25, s13, s23
	v_rcp_iflag_f32_e32 v0, v0
	v_cvt_f32_u32_e32 v5, s25
	v_rcp_iflag_f32_e32 v4, v4
	v_rcp_iflag_f32_e32 v3, v3
	s_sub_i32 s2, 0, s20
	v_mul_f32_e32 v2, 0x4f7ffffe, v2
	v_rcp_iflag_f32_e32 v5, v5
	s_sub_i32 s3, 0, s25
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s11, s27, s11
	s_add_i32 s27, s9, -1
	v_mul_f32_e32 v0, 0x4f7ffffe, v0
	v_cvt_u32_f32_e32 v7, v2
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v2, 0x4f7ffffe, v4 :: v_dual_mul_f32 v3, 0x4f7ffffe, v3
	s_mul_i32 s11, s11, s26
	v_cvt_u32_f32_e32 v0, v0
	s_mov_b32 s26, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_cvt_u32_f32_e32 v8, v2
	v_mul_f32_e32 v4, 0x4f7ffffe, v5
	v_cvt_u32_f32_e32 v5, v3
	v_mul_lo_u32 v6, s2, v0
	s_sub_i32 s2, 0, s6
	s_sub_i32 s28, 0, s9
	v_cvt_u32_f32_e32 v9, v4
	v_mul_lo_u32 v3, s2, v7
	s_sub_i32 s2, 0, s21
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mul_lo_u32 v2, s2, v5
	s_sub_i32 s2, 0, s24
	v_mul_lo_u32 v10, s3, v9
	v_mul_lo_u32 v4, s2, v8
	s_clause 0x1
	s_load_b128 s[12:15], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	v_mul_hi_u32 v6, v0, v6
	v_mul_hi_u32 v3, v7, v3
	v_mul_hi_u32 v11, v5, v2
	v_mul_hi_u32 v10, v9, v10
	v_mul_hi_u32 v12, v8, v4
	v_add_nc_u32_e32 v2, v0, v6
	v_add_nc_u32_e32 v3, v7, v3
	v_add_nc_u32_e32 v4, v5, v11
	v_add_nc_u32_e32 v6, v9, v10
	v_add_nc_u32_e32 v5, v8, v12
.LBB3_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB3_4 Depth 2
	v_ashrrev_i32_e32 v7, 31, v1
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v9, 0 :: v_dual_add_nc_u32 v0, v1, v7
	v_xor_b32_e32 v8, v0, v7
	s_cbranch_vccnz .LBB3_9
; %bb.3:                                ; %.lr.ph
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v0, v8, v3
	v_mul_hi_u32 v9, v8, v4
	v_xor_b32_e32 v20, s17, v7
	s_mov_b32 s29, s28
	s_mov_b32 s30, s27
	v_mul_lo_u32 v10, v0, s6
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v11, v9, s21
	v_add_nc_u32_e32 v12, 1, v0
	v_sub_nc_u32_e32 v10, v8, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v11, v8, v11
	v_subrev_nc_u32_e32 v14, s6, v10
	v_cmp_le_u32_e32 vcc_lo, s6, v10
	v_add_nc_u32_e32 v13, 1, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_cmp_le_u32_e64 s0, s21, v11
	v_cndmask_b32_e32 v0, v0, v12, vcc_lo
	v_subrev_nc_u32_e32 v12, s21, v11
	v_cndmask_b32_e32 v10, v10, v14, vcc_lo
	v_cndmask_b32_e64 v9, v9, v13, s0
	v_xor_b32_e32 v14, s18, v7
	v_add_nc_u32_e32 v13, 1, v0
	v_cndmask_b32_e64 v11, v11, v12, s0
	v_cmp_le_u32_e32 vcc_lo, s6, v10
	v_add_nc_u32_e32 v12, 1, v9
	v_xor_b32_e32 v10, s19, v7
	v_cndmask_b32_e32 v0, v0, v13, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s21, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v9, v9, v12, vcc_lo
	v_xor_b32_e32 v0, v0, v14
	v_mul_hi_u32 v12, v8, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v9, v9, v10
	v_sub_nc_u32_e32 v0, v0, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v9, v9, v10
	v_ashrrev_i32_e32 v10, 31, v0
	v_mul_lo_u32 v13, v12, s20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v11, 31, v9
	v_add_nc_u32_e32 v0, v0, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v13, v8, v13
	v_xor_b32_e32 v0, v0, v10
	v_xor_b32_e32 v10, s17, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_subrev_nc_u32_e32 v18, s20, v13
	v_mul_hi_u32 v14, v0, v2
	v_cmp_le_u32_e32 vcc_lo, s20, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v13, v13, v18, vcc_lo
	v_mul_lo_u32 v16, v14, s20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v0, v0, v16
	v_add_nc_u32_e32 v16, 1, v14
	v_subrev_nc_u32_e32 v18, s20, v0
	v_add_nc_u32_e32 v17, 1, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v12, v12, v17 :: v_dual_add_nc_u32 v9, v9, v11
	v_xor_b32_e32 v9, v9, v11
	v_cmp_le_u32_e32 vcc_lo, s20, v0
	v_xor_b32_e32 v11, s18, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v15, v9, v3
	v_cndmask_b32_e32 v14, v14, v16, vcc_lo
	v_cndmask_b32_e32 v0, v0, v18, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s20, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v19, v15, s6
	v_add_nc_u32_e32 v17, 1, v15
	v_sub_nc_u32_e32 v9, v9, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_subrev_nc_u32_e32 v16, s6, v9
	v_cmp_le_u32_e64 s0, s6, v9
	v_cndmask_b32_e64 v15, v15, v17, s0
	v_add_nc_u32_e32 v17, 1, v14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v9, v9, v16, s0
	v_add_nc_u32_e32 v16, 1, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v0, v14, v17, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s6, v9
	v_add_nc_u32_e32 v14, 1, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v0, v0, v10
	v_cndmask_b32_e32 v9, v15, v16, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s20, v13
	v_sub_nc_u32_e32 v0, v0, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v9, v9, v11
	v_cndmask_b32_e32 v12, v12, v14, vcc_lo
	v_sub_nc_u32_e32 v9, v9, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v10, v12, v20
	v_ashrrev_i32_e32 v11, 31, v0
	v_sub_nc_u32_e32 v12, v10, v20
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v10, 31, v9
	v_add_nc_u32_e32 v0, v0, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v13, 31, v12
	v_add_nc_u32_e32 v9, v9, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v0, v0, v11
	v_add_nc_u32_e32 v14, v12, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v9, v9, v10
	v_mul_hi_u32 v15, v0, v4
	v_xor_b32_e32 v10, s17, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v14, v14, v13
	v_mul_hi_u32 v16, v9, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v15, v15, s21
	v_mul_hi_u32 v17, v14, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v18, v16, s20
	v_sub_nc_u32_e32 v0, v0, v15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v17, v17, s6
	v_sub_nc_u32_e32 v9, v9, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_subrev_nc_u32_e32 v15, s21, v0
	v_cmp_le_u32_e32 vcc_lo, s21, v0
	v_sub_nc_u32_e32 v14, v14, v17
	v_add_nc_u32_e32 v17, 1, v16
	v_subrev_nc_u32_e32 v18, s20, v9
	v_cndmask_b32_e32 v0, v0, v15, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s20, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v15, v16, v17, vcc_lo
	v_subrev_nc_u32_e32 v17, s21, v0
	v_cndmask_b32_e32 v9, v9, v18, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s21, v0
	v_subrev_nc_u32_e32 v16, s6, v14
	v_add_nc_u32_e32 v18, 1, v15
	v_cndmask_b32_e32 v0, v0, v17, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s20, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v0, v0, v11
	v_cndmask_b32_e32 v9, v15, v18, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s6, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v0, v0, v11
	v_xor_b32_e32 v9, v9, v10
	v_cndmask_b32_e32 v14, v14, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v11, v9, v10
	v_subrev_nc_u32_e32 v15, s6, v14
	v_cmp_le_u32_e32 vcc_lo, s6, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[9:10], null, v11, s5, v[0:1]
	v_cndmask_b32_e32 v14, v14, v15, vcc_lo
	v_mul_lo_u32 v0, v12, s7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v12, v14, v13
	v_mul_lo_u32 v11, v9, s8
	v_mov_b32_e32 v9, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v0, v1, v0
	v_sub_nc_u32_e32 v10, v12, v13
	v_xad_u32 v12, v12, -1, v13
.LBB3_4:                                ;   Parent Loop BB3_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v16, s30, v10
	s_mov_b32 s1, exec_lo
                                        ; implicit-def: $vgpr14
	v_add_nc_u32_e32 v13, 1, v16
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_lt_i32_e32 vcc_lo, -1, v13
	v_cmpx_gt_i32_e32 0, v13
	s_xor_b32 s1, exec_lo, s1
	s_cbranch_execz .LBB3_6
; %bb.5:                                ;   in Loop: Header=BB3_4 Depth=2
	v_add_nc_u32_e32 v14, s29, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v15, 31, v14
	v_add_nc_u32_e32 v14, v14, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v14, v14, v15
	v_xor_b32_e32 v15, s22, v15
	v_mul_hi_u32 v17, v14, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v18, v17, s24
	v_sub_nc_u32_e32 v14, v14, v18
	v_add_nc_u32_e32 v18, 1, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_subrev_nc_u32_e32 v19, s24, v14
	v_cmp_le_u32_e64 s0, s24, v14
	v_cndmask_b32_e64 v17, v17, v18, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v14, v14, v19, s0
	v_add_nc_u32_e32 v18, 1, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u32_e64 s0, s24, v14
	v_cndmask_b32_e64 v14, v17, v18, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v14, v14, v15
	v_sub_nc_u32_e32 v14, v14, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v15, 31, v14
	v_add_nc_u32_e32 v15, v14, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v15, -2, v15
	v_sub_nc_u32_e32 v14, v15, v14
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v14, 1, v14
.LBB3_6:                                ; %Flow
                                        ;   in Loop: Header=BB3_4 Depth=2
	s_or_saveexec_b32 s1, s1
	v_ashrrev_i32_e32 v15, 31, v13
	s_delay_alu instid0(VALU_DEP_1)
	v_add3_u32 v16, v16, v15, 1
	s_xor_b32 exec_lo, exec_lo, s1
	s_cbranch_execz .LBB3_8
; %bb.7:                                ;   in Loop: Header=BB3_4 Depth=2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v14, v16, v15
	v_mul_hi_u32 v17, v14, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v18, v17, s24
	v_sub_nc_u32_e32 v14, v14, v18
	v_add_nc_u32_e32 v18, 1, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_subrev_nc_u32_e32 v19, s24, v14
	v_cmp_le_u32_e64 s0, s24, v14
	v_cndmask_b32_e64 v17, v17, v18, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v14, v14, v19, s0
	v_xor_b32_e32 v19, s22, v15
	v_add_nc_u32_e32 v18, 1, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_le_u32_e64 s0, s24, v14
	v_cndmask_b32_e64 v14, v17, v18, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v14, v14, v19
	v_sub_nc_u32_e32 v14, v14, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v17, 31, v14
	v_add_nc_u32_e32 v17, v14, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v17, -2, v17
	v_sub_nc_u32_e32 v14, v14, v17
.LBB3_8:                                ;   in Loop: Header=BB3_4 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v16, v16, v15
	v_cmp_eq_u32_e64 s1, 1, v14
	s_add_i32 s30, s30, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v17, v16, v5
	v_mul_lo_u32 v17, v17, s24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v16, v16, v17
	v_subrev_nc_u32_e32 v17, s24, v16
	v_cmp_le_u32_e64 s0, s24, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v16, v16, v17, s0
	v_subrev_nc_u32_e32 v17, s24, v16
	v_cmp_le_u32_e64 s0, s24, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v16, v16, v17, s0
	v_xor_b32_e32 v16, v16, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v15, v16, v15
	v_add_nc_u32_e32 v15, s8, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v16, 31, v15
	v_add_nc_u32_e32 v15, v15, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v15, v15, v16
	v_mul_hi_u32 v17, v15, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v17, v17, s24
	v_sub_nc_u32_e32 v15, v15, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_subrev_nc_u32_e32 v17, s24, v15
	v_cmp_le_u32_e64 s0, s24, v15
	v_cndmask_b32_e64 v15, v15, v17, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_subrev_nc_u32_e32 v17, s24, v15
	v_cmp_le_u32_e64 s0, s24, v15
	v_cndmask_b32_e64 v15, v15, v17, s0
	v_cmp_gt_i32_e64 s0, s8, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v15, v15, v16
	s_and_b32 vcc_lo, vcc_lo, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v15, v15, v16
	v_xad_u32 v16, v15, -1, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v14, v15, v16, s1
	v_dual_mov_b32 v13, s30 :: v_dual_add_nc_u32 v14, v14, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v13, s29, v13, vcc_lo
	s_add_i32 s29, s29, -1
	s_cmp_ge_i32 s30, s10
	v_mad_u64_u32 v[15:16], null, v14, s7, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_subrev_nc_u32_e32 v13, s9, v13
	v_ashrrev_i32_e32 v14, 31, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v16, 31, v15
	v_lshlrev_b64 v[13:14], 2, v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[15:16], 2, v[15:16]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v13, vcc_lo, s2, v13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v14, vcc_lo, s3, v14, vcc_lo
	v_add_co_u32 v15, vcc_lo, s14, v15
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v16, vcc_lo, s15, v16, vcc_lo
	global_load_b32 v13, v[13:14], off
	global_load_b32 v14, v[15:16], off
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v9, v13, v14
	s_cbranch_scc0 .LBB3_4
.LBB3_9:                                ; %._crit_edge
                                        ;   in Loop: Header=BB3_2 Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v0, v8, v6
	v_xor_b32_e32 v7, s23, v7
	v_add_nc_u32_e32 v1, s11, v1
	v_mul_lo_u32 v10, v0, s25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v8, v8, v10
	v_add_nc_u32_e32 v10, 1, v0
	v_subrev_nc_u32_e32 v11, s25, v8
	v_cmp_le_u32_e32 vcc_lo, s25, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v0, v0, v10, vcc_lo
	v_cndmask_b32_e32 v8, v8, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v10, 1, v0
	v_cmp_le_u32_e32 vcc_lo, s25, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v0, v0, v10, vcc_lo
	v_cmp_le_i32_e32 vcc_lo, s4, v1
	v_xor_b32_e32 v0, v0, v7
	s_or_b32 s26, vcc_lo, s26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v7, v0, v7
	v_ashrrev_i32_e32 v8, 31, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v7, s0, s12, v7
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v8, s0, s13, v8, s0
	global_store_b32 v[7:8], v9, off
	s_and_not1_b32 exec_lo, exec_lo, s26
	s_cbranch_execnz .LBB3_2
.LBB3_10:                               ; %Flow117
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel colfilter_bwd
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 21
		.amdhsa_next_free_sgpr 31
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	colfilter_bwd, .Lfunc_end3-colfilter_bwd
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2152
; NumSgprs: 33
; NumVgprs: 21
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 33
; NumVGPRsForWavesPerEU: 21
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           rowfilter
    .private_segment_fixed_size: 0
    .sgpr_count:     33
    .sgpr_spill_count: 0
    .symbol:         rowfilter.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     21
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           rowfilter_bwd
    .private_segment_fixed_size: 0
    .sgpr_count:     34
    .sgpr_spill_count: 0
    .symbol:         rowfilter_bwd.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     20
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           colfilter
    .private_segment_fixed_size: 0
    .sgpr_count:     32
    .sgpr_spill_count: 0
    .symbol:         colfilter.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     21
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           colfilter_bwd
    .private_segment_fixed_size: 0
    .sgpr_count:     33
    .sgpr_spill_count: 0
    .symbol:         colfilter_bwd.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     21
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
