#include <stdlib.h>
#include <stdio.h>
#include <time.h>
#include <limits.h>

#define TRUE 0
#define FALSE 1


typedef struct {
	
	int src;
	int dst;
	int cost;
} Edge;


__global__ void bellman_ford_kernel(int *dis_arr, Edge *edges, int *change) {
	int my_id;
	my_id = blockIdx.x*blockDim.x + threadIdx.x;

	Edge my_edge = edges[my_id];
	int curr_dis, cand_dis;


	int i;
	// test code
	for (i =0; i < 5; i++) {
		printf("%d->%d: %d\n", edges[i].src, edges[i].dst, edges[i].cost);
	}

	curr_dis = dis_arr[my_edge.dst];
	cand_dis = dis_arr[my_edge.src] + my_edge.cost;

	if (cand_dis < curr_dis) {
		*change = TRUE;
		dis_arr[my_edge.dst] = cand_dis;
	}
}

int main() {
	
	int *dis_arr;
	Edge *edges;

	int n = 5; // num vertices
	int m = 5; // num edges

	dis_arr = (int*)malloc(sizeof(int)*n);
	edges = (Edge*)malloc(sizeof(Edge)*m);

	int i;

	// init edges
	Edge e1 = {0,1, 5};
	Edge e2 = {0,3, 1};
	Edge e3 = {1,2, 3};
	Edge e4 = {3,4, 4};
	Edge e5 = {2,4, 8};
	edges[0] = e1;
	edges[1] = e2;
	edges[2] = e3;
	edges[3] = e4;
	edges[4] = e5;

	// init dis_arr
	// set each val to INT_MAX
	for (i=0; i < n; i++)
		dis_arr[i] = INT_MAX;

	// set source dis
	dis_arr[0] = 0;

	int *gpu_dis_arr;
	Edge *gpu_edges;

	cudaMalloc((void**)&gpu_dis_arr, sizeof(int)*n);
	cudaMalloc((void**)&gpu_edges, sizeof(Edge)*m);

	cudaMemcpy(gpu_dis_arr, dis_arr, sizeof(int)*n, cudaMemcpyHostToDevice);
	cudaMemcpy(gpu_edges, edges, sizeof(Edge)*m, cudaMemcpyHostToDevice);

	int *change;
	int *gpu_change;

	change = (int*)malloc(sizeof(int));
	cudaMalloc((void**)&gpu_change, sizeof(int));

	*change = TRUE;

	while(change == TRUE) {
		//*change = FALSE;
		cudaMemcpy(gpu_change, change, sizeof(int)*1, cudaMemcpyHostToDevice);
		bellman_ford_kernel<<< 1 , 5 >>>(gpu_dis_arr, gpu_edges, gpu_change);
		cudaMemcpy(change, gpu_change, sizeof(int)*1, cudaMemcpyDeviceToHost);
	}

	cudaMemcpy(dis_arr, gpu_dis_arr, sizeof(int)*n, cudaMemcpyDeviceToHost);

	// print dis-arr
	printf("Distance array\n");
	for (i=0; i < n; i++)
		printf("%d ", dis_arr[i]);

}




	.file	"tmpxft_00208d32_00000000-6_sssp.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Distance array\n"
.LC1:
	.string	"%d "
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r12
	.cfi_def_cfa_offset 16
	.cfi_offset 12, -16
	movl	$20, %edi
	leaq	.LC1(%rip), %r12
	pushq	%rbp
	.cfi_def_cfa_offset 24
	.cfi_offset 6, -24
	pushq	%rbx
	.cfi_def_cfa_offset 32
	.cfi_offset 3, -32
	subq	$32, %rsp
	.cfi_def_cfa_offset 64
	movq	%fs:40, %rax
	movq	%rax, 24(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$60, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	movl	$2147483647, 16(%rbp)
	movq	%rsp, %rdi
	movl	$20, %esi
	movq	%rax, %rbx
	movl	$1, %eax
	salq	$32, %rax
	movq	$5, 8(%rbx)
	movq	%rax, (%rbx)
	addq	$3, %rax
	movq	%rax, 16(%rbx)
	movabsq	$8589934593, %rax
	movq	%rax, 24(%rbx)
	movabsq	$12884901891, %rax
	movq	%rax, 32(%rbx)
	movabsq	$17179869188, %rax
	movq	%rax, 40(%rbx)
	subq	$2, %rax
	movq	%rax, 48(%rbx)
	movl	$2147483647, %eax
	salq	$32, %rax
	movl	$8, 56(%rbx)
	movq	%rax, 0(%rbp)
	addq	$2147483647, %rax
	movq	%rax, 8(%rbp)
	call	cudaMalloc@PLT
	leaq	8(%rsp), %rdi
	movl	$60, %esi
	call	cudaMalloc@PLT
	movq	(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$20, %edx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$60, %edx
	xorl	%ebx, %ebx
	call	cudaMemcpy@PLT
	leaq	16(%rsp), %rdi
	movl	$4, %esi
	call	cudaMalloc@PLT
	movq	(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbp, %rdi
	movl	$20, %edx
	call	cudaMemcpy@PLT
	leaq	.LC0(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
.L3:
	movl	0(%rbp,%rbx,4), %edx
	movq	%r12, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%rbx
	call	__printf_chk@PLT
	cmpq	$5, %rbx
	jne	.L3
	movq	24(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$32, %rsp
	.cfi_def_cfa_offset 32
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 24
	popq	%rbp
	.cfi_def_cfa_offset 16
	popq	%r12
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.text
	.globl	_Z47__device_stub__Z19bellman_ford_kernelPiP4EdgeS_PiP4EdgeS_
	.type	_Z47__device_stub__Z19bellman_ford_kernelPiP4EdgeS_PiP4EdgeS_, @function
_Z47__device_stub__Z19bellman_ford_kernelPiP4EdgeS_PiP4EdgeS_:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z19bellman_ford_kernelPiP4EdgeS_(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L8:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z47__device_stub__Z19bellman_ford_kernelPiP4EdgeS_PiP4EdgeS_, .-_Z47__device_stub__Z19bellman_ford_kernelPiP4EdgeS_PiP4EdgeS_
	.globl	_Z19bellman_ford_kernelPiP4EdgeS_
	.type	_Z19bellman_ford_kernelPiP4EdgeS_, @function
_Z19bellman_ford_kernelPiP4EdgeS_:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z47__device_stub__Z19bellman_ford_kernelPiP4EdgeS_PiP4EdgeS_
	.cfi_endproc
.LFE2053:
	.size	_Z19bellman_ford_kernelPiP4EdgeS_, .-_Z19bellman_ford_kernelPiP4EdgeS_
	.section	.rodata.str1.1
.LC2:
	.string	"_Z19bellman_ford_kernelPiP4EdgeS_"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z19bellman_ford_kernelPiP4EdgeS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdlib.h>
#include <stdio.h>
#include <time.h>
#include <limits.h>

#define TRUE 0
#define FALSE 1


typedef struct {
	
	int src;
	int dst;
	int cost;
} Edge;


__global__ void bellman_ford_kernel(int *dis_arr, Edge *edges, int *change) {
	int my_id;
	my_id = blockIdx.x*blockDim.x + threadIdx.x;

	Edge my_edge = edges[my_id];
	int curr_dis, cand_dis;


	int i;
	// test code
	for (i =0; i < 5; i++) {
		printf("%d->%d: %d\n", edges[i].src, edges[i].dst, edges[i].cost);
	}

	curr_dis = dis_arr[my_edge.dst];
	cand_dis = dis_arr[my_edge.src] + my_edge.cost;

	if (cand_dis < curr_dis) {
		*change = TRUE;
		dis_arr[my_edge.dst] = cand_dis;
	}
}

int main() {
	
	int *dis_arr;
	Edge *edges;

	int n = 5; // num vertices
	int m = 5; // num edges

	dis_arr = (int*)malloc(sizeof(int)*n);
	edges = (Edge*)malloc(sizeof(Edge)*m);

	int i;

	// init edges
	Edge e1 = {0,1, 5};
	Edge e2 = {0,3, 1};
	Edge e3 = {1,2, 3};
	Edge e4 = {3,4, 4};
	Edge e5 = {2,4, 8};
	edges[0] = e1;
	edges[1] = e2;
	edges[2] = e3;
	edges[3] = e4;
	edges[4] = e5;

	// init dis_arr
	// set each val to INT_MAX
	for (i=0; i < n; i++)
		dis_arr[i] = INT_MAX;

	// set source dis
	dis_arr[0] = 0;

	int *gpu_dis_arr;
	Edge *gpu_edges;

	hipMalloc((void**)&gpu_dis_arr, sizeof(int)*n);
	hipMalloc((void**)&gpu_edges, sizeof(Edge)*m);

	hipMemcpy(gpu_dis_arr, dis_arr, sizeof(int)*n, hipMemcpyHostToDevice);
	hipMemcpy(gpu_edges, edges, sizeof(Edge)*m, hipMemcpyHostToDevice);

	int *change;
	int *gpu_change;

	change = (int*)malloc(sizeof(int));
	hipMalloc((void**)&gpu_change, sizeof(int));

	*change = TRUE;

	while(change == TRUE) {
		//*change = FALSE;
		hipMemcpy(gpu_change, change, sizeof(int)*1, hipMemcpyHostToDevice);
		bellman_ford_kernel<<< 1 , 5 >>>(gpu_dis_arr, gpu_edges, gpu_change);
		hipMemcpy(change, gpu_change, sizeof(int)*1, hipMemcpyDeviceToHost);
	}

	hipMemcpy(dis_arr, gpu_dis_arr, sizeof(int)*n, hipMemcpyDeviceToHost);

	// print dis-arr
	printf("Distance array\n");
	for (i=0; i < n; i++)
		printf("%d ", dis_arr[i]);

}




	.text
	.file	"sssp.hip"
	.globl	_Z34__device_stub__bellman_ford_kernelPiP4EdgeS_ # -- Begin function _Z34__device_stub__bellman_ford_kernelPiP4EdgeS_
	.type	_Z34__device_stub__bellman_ford_kernelPiP4EdgeS_,@function
_Z34__device_stub__bellman_ford_kernelPiP4EdgeS_: # @_Z34__device_stub__bellman_ford_kernelPiP4EdgeS_
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19bellman_ford_kernelPiP4EdgeS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z34__device_stub__bellman_ford_kernelPiP4EdgeS_, .Lfunc_end0-_Z34__device_stub__bellman_ford_kernelPiP4EdgeS_
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function main
.LCPI1_0:
	.long	0                               # 0x0
	.long	1                               # 0x1
	.long	5                               # 0x5
	.long	0                               # 0x0
.LCPI1_1:
	.long	3                               # 0x3
	.long	1                               # 0x1
	.long	1                               # 0x1
	.long	2                               # 0x2
.LCPI1_2:
	.long	3                               # 0x3
	.long	3                               # 0x3
	.long	4                               # 0x4
	.long	4                               # 0x4
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	subq	$24, %rsp
	.cfi_def_cfa_offset 64
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	$20, %edi
	callq	malloc
	movq	%rax, %rbx
	movl	$60, %edi
	callq	malloc
	movq	%rax, %r14
	movaps	.LCPI1_0(%rip), %xmm0           # xmm0 = [0,1,5,0]
	movups	%xmm0, (%rax)
	movaps	.LCPI1_1(%rip), %xmm0           # xmm0 = [3,1,1,2]
	movups	%xmm0, 16(%rax)
	movaps	.LCPI1_2(%rip), %xmm0           # xmm0 = [3,3,4,4]
	movups	%xmm0, 32(%rax)
	movabsq	$17179869186, %rax              # imm = 0x400000002
	movq	%rax, 48(%r14)
	movl	$8, 56(%r14)
	xorl	%eax, %eax
.LBB1_1:                                # =>This Inner Loop Header: Depth=1
	movl	$2147483647, (%rbx,%rax,4)      # imm = 0x7FFFFFFF
	incq	%rax
	cmpq	$5, %rax
	jne	.LBB1_1
# %bb.2:
	movl	$0, (%rbx)
	leaq	16(%rsp), %r15
	movl	$20, %esi
	movq	%r15, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %r12
	movl	$60, %esi
	movq	%r12, %rdi
	callq	hipMalloc
	movq	(%r15), %rdi
	movl	$20, %edx
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%r12), %rdi
	movl	$60, %edx
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%rsp, %rdi
	movl	$4, %esi
	callq	hipMalloc
	movq	(%r15), %rsi
	movl	$20, %edx
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$.Lstr, %edi
	callq	puts@PLT
	xorl	%r14d, %r14d
.LBB1_3:                                # =>This Inner Loop Header: Depth=1
	movl	(%rbx,%r14,4), %esi
	movl	$.L.str.1, %edi
	xorl	%eax, %eax
	callq	printf
	incq	%r14
	cmpq	$5, %r14
	jne	.LBB1_3
# %bb.4:
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19bellman_ford_kernelPiP4EdgeS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z19bellman_ford_kernelPiP4EdgeS_,@object # @_Z19bellman_ford_kernelPiP4EdgeS_
	.section	.rodata,"a",@progbits
	.globl	_Z19bellman_ford_kernelPiP4EdgeS_
	.p2align	3, 0x0
_Z19bellman_ford_kernelPiP4EdgeS_:
	.quad	_Z34__device_stub__bellman_ford_kernelPiP4EdgeS_
	.size	_Z19bellman_ford_kernelPiP4EdgeS_, 8

	.type	.L.str.1,@object                # @.str.1
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.1:
	.asciz	"%d "
	.size	.L.str.1, 4

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z19bellman_ford_kernelPiP4EdgeS_"
	.size	.L__unnamed_1, 34

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"Distance array"
	.size	.Lstr, 15

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z34__device_stub__bellman_ford_kernelPiP4EdgeS_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z19bellman_ford_kernelPiP4EdgeS_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z19bellman_ford_kernelPiP4EdgeS_ ; -- Begin function _Z19bellman_ford_kernelPiP4EdgeS_
	.globl	_Z19bellman_ford_kernelPiP4EdgeS_
	.p2align	8
	.type	_Z19bellman_ford_kernelPiP4EdgeS_,@function
_Z19bellman_ford_kernelPiP4EdgeS_:      ; @_Z19bellman_ford_kernelPiP4EdgeS_
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x24
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[12:13], s[0:1], 0x68
	v_mbcnt_lo_u32_b32 v35, -1, 0
	v_mov_b32_e32 v6, 1
	s_mov_b32 s8, 0
	s_mov_b32 s22, 0
	v_mov_b32_e32 v5, 2
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_load_b64 s[2:3], s[0:1], 0x10
	v_mov_b32_e32 v0, 33
	v_mad_i64_i32 v[2:3], null, v1, 12, s[6:7]
	global_load_b96 v[32:34], v[2:3], off
	v_mov_b32_e32 v2, 0
.LBB0_1:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
                                        ;     Child Loop BB0_12 Depth 2
                                        ;     Child Loop BB0_18 Depth 2
                                        ;     Child Loop BB0_27 Depth 2
                                        ;     Child Loop BB0_30 Depth 2
                                        ;       Child Loop BB0_33 Depth 3
                                        ;       Child Loop BB0_41 Depth 3
                                        ;       Child Loop BB0_49 Depth 3
                                        ;       Child Loop BB0_57 Depth 3
                                        ;       Child Loop BB0_65 Depth 3
                                        ;       Child Loop BB0_73 Depth 3
                                        ;       Child Loop BB0_81 Depth 3
                                        ;       Child Loop BB0_89 Depth 3
                                        ;       Child Loop BB0_97 Depth 3
                                        ;       Child Loop BB0_103 Depth 3
                                        ;       Child Loop BB0_112 Depth 3
                                        ;     Child Loop BB0_120 Depth 2
                                        ;     Child Loop BB0_128 Depth 2
                                        ;     Child Loop BB0_134 Depth 2
                                        ;     Child Loop BB0_143 Depth 2
                                        ;     Child Loop BB0_148 Depth 2
                                        ;     Child Loop BB0_156 Depth 2
                                        ;     Child Loop BB0_162 Depth 2
                                        ;     Child Loop BB0_171 Depth 2
                                        ;     Child Loop BB0_175 Depth 2
                                        ;     Child Loop BB0_183 Depth 2
                                        ;     Child Loop BB0_189 Depth 2
                                        ;     Child Loop BB0_198 Depth 2
                                        ;     Child Loop BB0_202 Depth 2
                                        ;     Child Loop BB0_210 Depth 2
                                        ;     Child Loop BB0_216 Depth 2
                                        ;     Child Loop BB0_225 Depth 2
	s_mul_i32 s0, s22, 12
	s_mul_hi_u32 s1, s22, 12
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	v_mov_b32_e32 v1, v35
	global_load_b96 v[7:9], v2, s[0:1]
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_7
; %bb.2:                                ;   in Loop: Header=BB0_1 Depth=1
	global_load_b64 v[12:13], v2, s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[12:13] offset:40
	global_load_b64 v[10:11], v2, s[12:13]
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v13
	v_and_b32_e32 v3, v3, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v14, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v14, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v10, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v11, v4, vcc_lo
	global_load_b64 v[10:11], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[10:13], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[12:13]
	s_cbranch_execz .LBB0_6
; %bb.3:                                ; %.preheader3.i.i.i.preheader
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_mov_b32 s10, 0
.LBB0_4:                                ; %.preheader3.i.i.i
                                        ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[10:11], v2, s[12:13] offset:40
	global_load_b64 v[14:15], v2, s[12:13]
	v_dual_mov_b32 v13, v4 :: v_dual_mov_b32 v12, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v10, v10, v12
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v10, 24, v[14:15]
	v_and_b32_e32 v14, v11, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[10:11], null, v14, 24, v[4:5]
	v_mov_b32_e32 v4, v10
	global_load_b64 v[10:11], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[10:13], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[12:13]
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_4
; %bb.5:                                ; %Flow491
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_6:                                ; %Flow493
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
.LBB0_7:                                ; %.loopexit4.i.i.i
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[14:15], v2, s[12:13] offset:40
	global_load_b128 v[10:13], v2, s[12:13]
	v_readfirstlane_b32 s14, v3
	v_readfirstlane_b32 s15, v4
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v14
	v_readfirstlane_b32 s11, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[14:15], s[10:11]
	s_mul_i32 s1, s11, 24
	s_mul_hi_u32 s16, s10, 24
	s_mul_i32 s17, s10, 24
	s_and_saveexec_b32 s18, s0
	s_cbranch_execz .LBB0_9
; %bb.8:                                ;   in Loop: Header=BB0_1 Depth=1
	v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, v2
	s_add_i32 s9, s16, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v14, vcc_lo, v10, s17
	v_add_co_ci_u32_e32 v15, vcc_lo, s9, v11, vcc_lo
	global_store_b128 v[14:15], v[3:6], off offset:8
.LBB0_9:                                ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s18
	s_lshl_b64 s[10:11], s[10:11], 12
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v12, s10
	v_add_co_ci_u32_e32 v12, vcc_lo, s11, v13, vcc_lo
	s_mov_b32 s11, s8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v16, vcc_lo, v1, v3
	s_mov_b32 s9, s8
	s_mov_b32 s10, s8
	v_add_co_ci_u32_e32 v17, vcc_lo, v12, v4, vcc_lo
	v_mov_b32_e32 v1, v2
	v_mov_b32_e32 v3, v2
	v_dual_mov_b32 v15, s11 :: v_dual_mov_b32 v12, s8
	v_dual_mov_b32 v14, s10 :: v_dual_mov_b32 v13, s9
	s_clause 0x3
	global_store_b128 v[16:17], v[0:3], off
	global_store_b128 v[16:17], v[12:15], off offset:16
	global_store_b128 v[16:17], v[12:15], off offset:32
	global_store_b128 v[16:17], v[12:15], off offset:48
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB0_17
; %bb.10:                               ;   in Loop: Header=BB0_1 Depth=1
	s_clause 0x1
	global_load_b64 v[20:21], v2, s[12:13] offset:32 glc
	global_load_b64 v[3:4], v2, s[12:13] offset:40
	v_dual_mov_b32 v18, s14 :: v_dual_mov_b32 v19, s15
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v3
	v_readfirstlane_b32 s11, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[14:15]
	s_mul_i32 s11, s11, 24
	s_mul_hi_u32 s18, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s18, s18, s11
	v_add_co_u32 v3, vcc_lo, v10, s10
	v_add_co_ci_u32_e32 v4, vcc_lo, s18, v11, vcc_lo
	s_mov_b32 s10, exec_lo
	global_store_b64 v[3:4], v[20:21], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[14:15], v2, v[18:21], s[12:13] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[14:15], v[20:21]
	s_cbranch_execz .LBB0_13
; %bb.11:                               ; %.preheader1.i.i.i.preheader
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_mov_b32 s11, 0
.LBB0_12:                               ; %.preheader1.i.i.i
                                        ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v12, s14 :: v_dual_mov_b32 v13, s15
	s_sleep 1
	global_store_b64 v[3:4], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[12:13], v2, v[12:15], s[12:13] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[12:13], v[14:15]
	v_dual_mov_b32 v15, v13 :: v_dual_mov_b32 v14, v12
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_12
.LBB0_13:                               ; %Flow489
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	global_load_b64 v[3:4], v2, s[12:13] offset:16
	s_mov_b32 s11, exec_lo
	s_mov_b32 s10, exec_lo
	v_mbcnt_lo_u32_b32 v1, s11, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB0_15
; %bb.14:                               ;   in Loop: Header=BB0_1 Depth=1
	s_bcnt1_i32_b32 s11, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s11
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[1:2], off offset:8
.LBB0_15:                               ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_waitcnt vmcnt(0)
	global_load_b64 v[12:13], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[12:13]
	s_cbranch_vccnz .LBB0_17
; %bb.16:                               ;   in Loop: Header=BB0_1 Depth=1
	global_load_b32 v1, v[3:4], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[12:13], v[1:2], off
	s_and_b32 m0, s10, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_17:                               ; %Flow490
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	s_add_i32 s16, s16, s1
	v_add_co_u32 v1, vcc_lo, v10, s17
	v_add_co_ci_u32_e32 v4, vcc_lo, s16, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB0_18:                               ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_20
; %bb.19:                               ;   in Loop: Header=BB0_18 Depth=2
	global_load_b32 v1, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB0_20:                               ;   in Loop: Header=BB0_18 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_22
; %bb.21:                               ;   in Loop: Header=BB0_18 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_23
.LBB0_22:                               ;   in Loop: Header=BB0_18 Depth=2
	s_mov_b32 s1, -1
.LBB0_23:                               ; %Flow484
                                        ;   in Loop: Header=BB0_18 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_18
; %bb.24:                               ;   in Loop: Header=BB0_1 Depth=1
	global_load_b64 v[10:11], v[16:17], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_28
; %bb.25:                               ;   in Loop: Header=BB0_1 Depth=1
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[12:13] offset:40
	global_load_b64 v[16:17], v2, s[12:13] offset:24 glc
	global_load_b64 v[14:15], v2, s[12:13]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v18, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v12, vcc_lo, v1, s14
	v_add_co_ci_u32_e32 v13, vcc_lo, s15, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[12:13]
	v_dual_cndmask_b32 v13, v13, v18 :: v_dual_cndmask_b32 v12, v12, v1
	v_and_b32_e32 v1, v13, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v3, v12, v3
	v_mul_hi_u32 v4, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v3, vcc_lo, v14, v3
	v_mov_b32_e32 v14, v16
	v_mul_lo_u32 v1, v1, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v4, vcc_lo, v15, v1, vcc_lo
	v_mov_b32_e32 v15, v17
	global_store_b64 v[3:4], v[16:17], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[14:15], v2, v[12:15], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[14:15], v[16:17]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_28
; %bb.26:                               ; %.preheader.i.i.i.preheader
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_mov_b32 s0, 0
.LBB0_27:                               ; %.preheader.i.i.i
                                        ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[3:4], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[16:17], v2, v[12:15], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[16:17], v[14:15]
	v_dual_mov_b32 v14, v16 :: v_dual_mov_b32 v15, v17
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_27
.LBB0_28:                               ; %__ockl_printf_begin.exit
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, .str@rel32@lo+4
	s_addc_u32 s11, s11, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u64 s[10:11], 0
	s_cbranch_scc0 .LBB0_115
; %bb.29:                               ;   in Loop: Header=BB0_1 Depth=1
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v13, v11 :: v_dual_and_b32 v36, 2, v10
	v_and_b32_e32 v12, -3, v10
	s_mov_b64 s[14:15], 12
.LBB0_30:                               ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_33 Depth 3
                                        ;       Child Loop BB0_41 Depth 3
                                        ;       Child Loop BB0_49 Depth 3
                                        ;       Child Loop BB0_57 Depth 3
                                        ;       Child Loop BB0_65 Depth 3
                                        ;       Child Loop BB0_73 Depth 3
                                        ;       Child Loop BB0_81 Depth 3
                                        ;       Child Loop BB0_89 Depth 3
                                        ;       Child Loop BB0_97 Depth 3
                                        ;       Child Loop BB0_103 Depth 3
                                        ;       Child Loop BB0_112 Depth 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s0, s[14:15], 56
	s_and_b32 s0, s0, exec_lo
	s_cselect_b32 s16, s14, 56
	s_cselect_b32 s17, s15, 0
	s_cmp_gt_u32 s16, 7
	s_cbranch_scc1 .LBB0_35
; %bb.31:                               ;   in Loop: Header=BB0_30 Depth=2
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v14, 0
	v_mov_b32_e32 v15, 0
	s_cmp_eq_u32 s16, 0
	s_cbranch_scc1 .LBB0_34
; %bb.32:                               ; %.preheader31.i.preheader
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_lshl_b64 s[0:1], s[16:17], 3
	s_mov_b64 s[18:19], 0
	s_mov_b64 s[20:21], s[10:11]
.LBB0_33:                               ; %.preheader31.i
                                        ;   Parent Loop BB0_1 Depth=1
                                        ;     Parent Loop BB0_30 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	global_load_u8 v1, v2, s[20:21]
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s18, v[1:2]
	s_add_u32 s18, s18, 8
	s_addc_u32 s19, s19, 0
	s_add_u32 s20, s20, 1
	s_addc_u32 s21, s21, 0
	s_cmp_lg_u32 s0, s18
	v_or_b32_e32 v14, v3, v14
	v_or_b32_e32 v15, v4, v15
	s_cbranch_scc1 .LBB0_33
.LBB0_34:                               ; %Flow460
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_mov_b32 s0, 0
	s_mov_b32 s9, 0
	s_branch .LBB0_36
.LBB0_35:                               ;   in Loop: Header=BB0_30 Depth=2
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr14_vgpr15
                                        ; implicit-def: $sgpr9
.LBB0_36:                               ; %Flow462
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_mov_b64 s[0:1], s[10:11]
	s_cbranch_vccnz .LBB0_38
; %bb.37:                               ;   in Loop: Header=BB0_30 Depth=2
	global_load_b64 v[14:15], v2, s[10:11]
	s_add_i32 s9, s16, -8
	s_add_u32 s0, s10, 8
	s_addc_u32 s1, s11, 0
.LBB0_38:                               ; %.loopexit32.i
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_cmp_gt_u32 s9, 7
	s_cbranch_scc1 .LBB0_43
; %bb.39:                               ;   in Loop: Header=BB0_30 Depth=2
	v_mov_b32_e32 v16, 0
	v_mov_b32_e32 v17, 0
	s_cmp_eq_u32 s9, 0
	s_cbranch_scc1 .LBB0_42
; %bb.40:                               ; %.preheader29.i.preheader
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_mov_b64 s[18:19], 0
	s_mov_b64 s[20:21], 0
.LBB0_41:                               ; %.preheader29.i
                                        ;   Parent Loop BB0_1 Depth=1
                                        ;     Parent Loop BB0_30 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s24, s0, s20
	s_addc_u32 s25, s1, s21
	s_add_u32 s20, s20, 1
	global_load_u8 v1, v2, s[24:25]
	s_addc_u32 s21, s21, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s18, v[1:2]
	s_add_u32 s18, s18, 8
	s_addc_u32 s19, s19, 0
	s_cmp_lg_u32 s9, s20
	v_or_b32_e32 v16, v3, v16
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v17, v4, v17
	s_cbranch_scc1 .LBB0_41
.LBB0_42:                               ; %Flow455
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_mov_b32 s18, 0
	s_mov_b32 s23, 0
	s_branch .LBB0_44
.LBB0_43:                               ;   in Loop: Header=BB0_30 Depth=2
	s_mov_b32 s18, -1
                                        ; implicit-def: $vgpr16_vgpr17
                                        ; implicit-def: $sgpr23
.LBB0_44:                               ; %Flow457
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccnz .LBB0_46
; %bb.45:                               ;   in Loop: Header=BB0_30 Depth=2
	global_load_b64 v[16:17], v2, s[0:1]
	s_add_i32 s23, s9, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_46:                               ; %.loopexit30.i
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_cmp_gt_u32 s23, 7
	s_cbranch_scc1 .LBB0_51
; %bb.47:                               ;   in Loop: Header=BB0_30 Depth=2
	v_mov_b32_e32 v18, 0
	v_mov_b32_e32 v19, 0
	s_cmp_eq_u32 s23, 0
	s_cbranch_scc1 .LBB0_50
; %bb.48:                               ; %.preheader27.i.preheader
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_mov_b64 s[18:19], 0
	s_mov_b64 s[20:21], 0
.LBB0_49:                               ; %.preheader27.i
                                        ;   Parent Loop BB0_1 Depth=1
                                        ;     Parent Loop BB0_30 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s24, s0, s20
	s_addc_u32 s25, s1, s21
	s_add_u32 s20, s20, 1
	global_load_u8 v1, v2, s[24:25]
	s_addc_u32 s21, s21, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s18, v[1:2]
	s_add_u32 s18, s18, 8
	s_addc_u32 s19, s19, 0
	s_cmp_lg_u32 s23, s20
	v_or_b32_e32 v18, v3, v18
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v19, v4, v19
	s_cbranch_scc1 .LBB0_49
.LBB0_50:                               ; %Flow450
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_mov_b32 s18, 0
	s_mov_b32 s9, 0
	s_branch .LBB0_52
.LBB0_51:                               ;   in Loop: Header=BB0_30 Depth=2
	s_mov_b32 s18, -1
                                        ; implicit-def: $sgpr9
.LBB0_52:                               ; %Flow452
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccnz .LBB0_54
; %bb.53:                               ;   in Loop: Header=BB0_30 Depth=2
	global_load_b64 v[18:19], v2, s[0:1]
	s_add_i32 s9, s23, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_54:                               ; %.loopexit28.i
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_cmp_gt_u32 s9, 7
	s_cbranch_scc1 .LBB0_59
; %bb.55:                               ;   in Loop: Header=BB0_30 Depth=2
	v_mov_b32_e32 v20, 0
	v_mov_b32_e32 v21, 0
	s_cmp_eq_u32 s9, 0
	s_cbranch_scc1 .LBB0_58
; %bb.56:                               ; %.preheader25.i.preheader
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_mov_b64 s[18:19], 0
	s_mov_b64 s[20:21], 0
.LBB0_57:                               ; %.preheader25.i
                                        ;   Parent Loop BB0_1 Depth=1
                                        ;     Parent Loop BB0_30 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s24, s0, s20
	s_addc_u32 s25, s1, s21
	s_add_u32 s20, s20, 1
	global_load_u8 v1, v2, s[24:25]
	s_addc_u32 s21, s21, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s18, v[1:2]
	s_add_u32 s18, s18, 8
	s_addc_u32 s19, s19, 0
	s_cmp_lg_u32 s9, s20
	v_or_b32_e32 v20, v3, v20
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v21, v4, v21
	s_cbranch_scc1 .LBB0_57
.LBB0_58:                               ; %Flow445
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_mov_b32 s18, 0
	s_mov_b32 s23, 0
	s_branch .LBB0_60
.LBB0_59:                               ;   in Loop: Header=BB0_30 Depth=2
	s_mov_b32 s18, -1
                                        ; implicit-def: $vgpr20_vgpr21
                                        ; implicit-def: $sgpr23
.LBB0_60:                               ; %Flow447
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccnz .LBB0_62
; %bb.61:                               ;   in Loop: Header=BB0_30 Depth=2
	global_load_b64 v[20:21], v2, s[0:1]
	s_add_i32 s23, s9, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_62:                               ; %.loopexit26.i
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_cmp_gt_u32 s23, 7
	s_cbranch_scc1 .LBB0_67
; %bb.63:                               ;   in Loop: Header=BB0_30 Depth=2
	v_mov_b32_e32 v22, 0
	v_mov_b32_e32 v23, 0
	s_cmp_eq_u32 s23, 0
	s_cbranch_scc1 .LBB0_66
; %bb.64:                               ; %.preheader23.i.preheader
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_mov_b64 s[18:19], 0
	s_mov_b64 s[20:21], 0
.LBB0_65:                               ; %.preheader23.i
                                        ;   Parent Loop BB0_1 Depth=1
                                        ;     Parent Loop BB0_30 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s24, s0, s20
	s_addc_u32 s25, s1, s21
	s_add_u32 s20, s20, 1
	global_load_u8 v1, v2, s[24:25]
	s_addc_u32 s21, s21, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s18, v[1:2]
	s_add_u32 s18, s18, 8
	s_addc_u32 s19, s19, 0
	s_cmp_lg_u32 s23, s20
	v_or_b32_e32 v22, v3, v22
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v23, v4, v23
	s_cbranch_scc1 .LBB0_65
.LBB0_66:                               ; %Flow440
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_mov_b32 s18, 0
	s_mov_b32 s9, 0
	s_branch .LBB0_68
.LBB0_67:                               ;   in Loop: Header=BB0_30 Depth=2
	s_mov_b32 s18, -1
                                        ; implicit-def: $sgpr9
.LBB0_68:                               ; %Flow442
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccnz .LBB0_70
; %bb.69:                               ;   in Loop: Header=BB0_30 Depth=2
	global_load_b64 v[22:23], v2, s[0:1]
	s_add_i32 s9, s23, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_70:                               ; %.loopexit24.i
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_cmp_gt_u32 s9, 7
	s_cbranch_scc1 .LBB0_75
; %bb.71:                               ;   in Loop: Header=BB0_30 Depth=2
	v_mov_b32_e32 v24, 0
	v_mov_b32_e32 v25, 0
	s_cmp_eq_u32 s9, 0
	s_cbranch_scc1 .LBB0_74
; %bb.72:                               ; %.preheader21.i.preheader
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_mov_b64 s[18:19], 0
	s_mov_b64 s[20:21], 0
.LBB0_73:                               ; %.preheader21.i
                                        ;   Parent Loop BB0_1 Depth=1
                                        ;     Parent Loop BB0_30 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s24, s0, s20
	s_addc_u32 s25, s1, s21
	s_add_u32 s20, s20, 1
	global_load_u8 v1, v2, s[24:25]
	s_addc_u32 s21, s21, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s18, v[1:2]
	s_add_u32 s18, s18, 8
	s_addc_u32 s19, s19, 0
	s_cmp_lg_u32 s9, s20
	v_or_b32_e32 v24, v3, v24
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v25, v4, v25
	s_cbranch_scc1 .LBB0_73
.LBB0_74:                               ; %Flow435
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_mov_b32 s18, 0
	s_mov_b32 s23, 0
	s_branch .LBB0_76
.LBB0_75:                               ;   in Loop: Header=BB0_30 Depth=2
	s_mov_b32 s18, -1
                                        ; implicit-def: $vgpr24_vgpr25
                                        ; implicit-def: $sgpr23
.LBB0_76:                               ; %Flow437
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccnz .LBB0_78
; %bb.77:                               ;   in Loop: Header=BB0_30 Depth=2
	global_load_b64 v[24:25], v2, s[0:1]
	s_add_i32 s23, s9, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_78:                               ; %.loopexit22.i
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_cmp_gt_u32 s23, 7
	s_cbranch_scc1 .LBB0_83
; %bb.79:                               ;   in Loop: Header=BB0_30 Depth=2
	v_mov_b32_e32 v26, 0
	v_mov_b32_e32 v27, 0
	s_cmp_eq_u32 s23, 0
	s_cbranch_scc1 .LBB0_82
; %bb.80:                               ; %.preheader.i.preheader
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_mov_b64 s[18:19], 0
	s_mov_b64 s[20:21], s[0:1]
.LBB0_81:                               ; %.preheader.i
                                        ;   Parent Loop BB0_1 Depth=1
                                        ;     Parent Loop BB0_30 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	global_load_u8 v1, v2, s[20:21]
	s_add_i32 s23, s23, -1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v1, 0xffff, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], s18, v[1:2]
	s_add_u32 s18, s18, 8
	s_addc_u32 s19, s19, 0
	s_add_u32 s20, s20, 1
	s_addc_u32 s21, s21, 0
	s_cmp_lg_u32 s23, 0
	v_or_b32_e32 v26, v3, v26
	v_or_b32_e32 v27, v4, v27
	s_cbranch_scc1 .LBB0_81
.LBB0_82:                               ; %Flow430
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_mov_b32 s9, 0
	s_branch .LBB0_84
.LBB0_83:                               ;   in Loop: Header=BB0_30 Depth=2
	s_mov_b32 s9, -1
.LBB0_84:                               ; %Flow432
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s9
	s_cbranch_vccnz .LBB0_86
; %bb.85:                               ;   in Loop: Header=BB0_30 Depth=2
	global_load_b64 v[26:27], v2, s[0:1]
.LBB0_86:                               ; %.loopexit.i
                                        ;   in Loop: Header=BB0_30 Depth=2
	v_mov_b32_e32 v1, v35
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	v_cmp_eq_u32_e64 s0, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_92
; %bb.87:                               ;   in Loop: Header=BB0_30 Depth=2
	global_load_b64 v[30:31], v2, s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[12:13] offset:40
	global_load_b64 v[28:29], v2, s[12:13]
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v31
	v_and_b32_e32 v3, v3, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v37, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v37, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v28, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v29, v4, vcc_lo
	global_load_b64 v[28:29], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[28:31], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[30:31]
	s_cbranch_execz .LBB0_91
; %bb.88:                               ; %.preheader3.i.i19.i.preheader
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_mov_b32 s18, 0
.LBB0_89:                               ; %.preheader3.i.i19.i
                                        ;   Parent Loop BB0_1 Depth=1
                                        ;     Parent Loop BB0_30 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[28:29], v2, s[12:13] offset:40
	global_load_b64 v[37:38], v2, s[12:13]
	v_dual_mov_b32 v31, v4 :: v_dual_mov_b32 v30, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v28, v28, v30
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v28, 24, v[37:38]
	v_and_b32_e32 v37, v29, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[28:29], null, v37, 24, v[4:5]
	v_mov_b32_e32 v4, v28
	global_load_b64 v[28:29], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[28:31], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[30:31]
	s_or_b32 s18, vcc_lo, s18
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s18
	s_cbranch_execnz .LBB0_89
; %bb.90:                               ; %Flow425
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_or_b32 exec_lo, exec_lo, s18
.LBB0_91:                               ; %Flow427
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
.LBB0_92:                               ; %.loopexit4.i.i14.i
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[37:38], v2, s[12:13] offset:40
	global_load_b128 v[28:31], v2, s[12:13]
	v_readfirstlane_b32 s18, v3
	v_readfirstlane_b32 s19, v4
	s_mov_b32 s24, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s20, v37
	v_readfirstlane_b32 s21, v38
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[20:21], s[18:19], s[20:21]
	s_mul_i32 s1, s21, 24
	s_mul_hi_u32 s9, s20, 24
	s_mul_i32 s23, s20, 24
	s_and_saveexec_b32 s25, s0
	s_cbranch_execz .LBB0_94
; %bb.93:                               ;   in Loop: Header=BB0_30 Depth=2
	v_dual_mov_b32 v3, s24 :: v_dual_mov_b32 v4, v2
	s_add_i32 s24, s9, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v37, vcc_lo, v28, s23
	v_add_co_ci_u32_e32 v38, vcc_lo, s24, v29, vcc_lo
	global_store_b128 v[37:38], v[3:6], off offset:8
.LBB0_94:                               ;   in Loop: Header=BB0_30 Depth=2
	s_or_b32 exec_lo, exec_lo, s25
	v_cmp_gt_u64_e64 vcc_lo, s[14:15], 56
	v_or_b32_e32 v3, 0, v13
	v_or_b32_e32 v4, v12, v36
	s_lshl_b64 s[20:21], s[20:21], 12
	s_lshl_b32 s24, s16, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s24, s24, 28
	v_dual_cndmask_b32 v13, v3, v13 :: v_dual_cndmask_b32 v12, v4, v12
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v30, s20
	v_add_co_ci_u32_e32 v30, vcc_lo, s21, v31, vcc_lo
	s_and_b32 s24, s24, 0x1e0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v1, v3
	v_and_or_b32 v12, 0xffffff1f, v12, s24
	v_add_co_ci_u32_e32 v4, vcc_lo, v30, v4, vcc_lo
	s_clause 0x3
	global_store_b128 v[3:4], v[12:15], off
	global_store_b128 v[3:4], v[16:19], off offset:16
	global_store_b128 v[3:4], v[20:23], off offset:32
	global_store_b128 v[3:4], v[24:27], off offset:48
	s_and_saveexec_b32 s20, s0
	s_cbranch_execz .LBB0_102
; %bb.95:                               ;   in Loop: Header=BB0_30 Depth=2
	s_clause 0x1
	global_load_b64 v[20:21], v2, s[12:13] offset:32 glc
	global_load_b64 v[12:13], v2, s[12:13] offset:40
	v_dual_mov_b32 v18, s18 :: v_dual_mov_b32 v19, s19
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s24, v12
	v_readfirstlane_b32 s25, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[24:25], s[24:25], s[18:19]
	s_mul_i32 s21, s25, 24
	s_mul_hi_u32 s25, s24, 24
	s_mul_i32 s24, s24, 24
	s_add_i32 s25, s25, s21
	v_add_co_u32 v16, vcc_lo, v28, s24
	v_add_co_ci_u32_e32 v17, vcc_lo, s25, v29, vcc_lo
	s_mov_b32 s21, exec_lo
	global_store_b64 v[16:17], v[20:21], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[14:15], v2, v[18:21], s[12:13] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[14:15], v[20:21]
	s_cbranch_execz .LBB0_98
; %bb.96:                               ; %.preheader1.i.i17.i.preheader
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_mov_b32 s24, 0
.LBB0_97:                               ; %.preheader1.i.i17.i
                                        ;   Parent Loop BB0_1 Depth=1
                                        ;     Parent Loop BB0_30 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_dual_mov_b32 v12, s18 :: v_dual_mov_b32 v13, s19
	s_sleep 1
	global_store_b64 v[16:17], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[12:13], v2, v[12:15], s[12:13] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[12:13], v[14:15]
	v_dual_mov_b32 v15, v13 :: v_dual_mov_b32 v14, v12
	s_or_b32 s24, vcc_lo, s24
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s24
	s_cbranch_execnz .LBB0_97
.LBB0_98:                               ; %Flow423
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_or_b32 exec_lo, exec_lo, s21
	global_load_b64 v[12:13], v2, s[12:13] offset:16
	s_mov_b32 s24, exec_lo
	s_mov_b32 s21, exec_lo
	v_mbcnt_lo_u32_b32 v1, s24, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB0_100
; %bb.99:                               ;   in Loop: Header=BB0_30 Depth=2
	s_bcnt1_i32_b32 s24, s24
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s24
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[12:13], v[1:2], off offset:8
.LBB0_100:                              ;   in Loop: Header=BB0_30 Depth=2
	s_or_b32 exec_lo, exec_lo, s21
	s_waitcnt vmcnt(0)
	global_load_b64 v[14:15], v[12:13], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[14:15]
	s_cbranch_vccnz .LBB0_102
; %bb.101:                              ;   in Loop: Header=BB0_30 Depth=2
	global_load_b32 v1, v[12:13], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s21, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[14:15], v[1:2], off
	s_and_b32 m0, s21, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_102:                              ; %Flow424
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_or_b32 exec_lo, exec_lo, s20
	s_add_i32 s9, s9, s1
	v_add_co_u32 v1, vcc_lo, v28, s23
	v_add_co_ci_u32_e32 v13, vcc_lo, s9, v29, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v12, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v13, vcc_lo
.LBB0_103:                              ;   Parent Loop BB0_1 Depth=1
                                        ;     Parent Loop BB0_30 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_105
; %bb.104:                              ;   in Loop: Header=BB0_103 Depth=3
	global_load_b32 v1, v[12:13], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB0_105:                              ;   in Loop: Header=BB0_103 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_107
; %bb.106:                              ;   in Loop: Header=BB0_103 Depth=3
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_108
.LBB0_107:                              ;   in Loop: Header=BB0_103 Depth=3
	s_mov_b32 s1, -1
.LBB0_108:                              ; %Flow418
                                        ;   in Loop: Header=BB0_103 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_103
; %bb.109:                              ;   in Loop: Header=BB0_30 Depth=2
	global_load_b128 v[12:15], v[3:4], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_113
; %bb.110:                              ;   in Loop: Header=BB0_30 Depth=2
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[12:13] offset:40
	global_load_b64 v[18:19], v2, s[12:13] offset:24 glc
	global_load_b64 v[16:17], v2, s[12:13]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v20, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v14, vcc_lo, v1, s18
	v_add_co_ci_u32_e32 v15, vcc_lo, s19, v20, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[14:15]
	v_dual_cndmask_b32 v15, v15, v20 :: v_dual_cndmask_b32 v14, v14, v1
	v_and_b32_e32 v1, v15, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v3, v14, v3
	v_mul_hi_u32 v4, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v3, vcc_lo, v16, v3
	v_mov_b32_e32 v16, v18
	v_mul_lo_u32 v1, v1, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v4, vcc_lo, v17, v1, vcc_lo
	v_mov_b32_e32 v17, v19
	global_store_b64 v[3:4], v[18:19], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[16:17], v2, v[14:17], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[16:17], v[18:19]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_113
; %bb.111:                              ; %.preheader.i.i16.i.preheader
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_mov_b32 s0, 0
.LBB0_112:                              ; %.preheader.i.i16.i
                                        ;   Parent Loop BB0_1 Depth=1
                                        ;     Parent Loop BB0_30 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	global_store_b64 v[3:4], v[16:17], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[18:19], v2, v[14:17], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[18:19], v[16:17]
	v_dual_mov_b32 v16, v18 :: v_dual_mov_b32 v17, v19
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_112
.LBB0_113:                              ; %__ockl_hostcall_preview.exit20.i
                                        ;   in Loop: Header=BB0_30 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_sub_u32 s14, s14, s16
	s_subb_u32 s15, s15, s17
	s_add_u32 s10, s10, s16
	s_addc_u32 s11, s11, s17
	s_cmp_lg_u64 s[14:15], 0
	s_cbranch_scc1 .LBB0_30
; %bb.114:                              ; %Flow463
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_mov_b32 s0, 0
	s_branch .LBB0_116
.LBB0_115:                              ;   in Loop: Header=BB0_1 Depth=1
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr12_vgpr13
.LBB0_116:                              ; %Flow478
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB0_145
; %bb.117:                              ;   in Loop: Header=BB0_1 Depth=1
	v_mov_b32_e32 v1, v35
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	v_cmp_eq_u32_e64 s0, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_123
; %bb.118:                              ;   in Loop: Header=BB0_1 Depth=1
	global_load_b64 v[14:15], v2, s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[12:13] offset:40
	global_load_b64 v[12:13], v2, s[12:13]
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v15
	v_and_b32_e32 v3, v3, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v16, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v16, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v12, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v13, v4, vcc_lo
	global_load_b64 v[12:13], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[12:15], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[14:15]
	s_cbranch_execz .LBB0_122
; %bb.119:                              ; %.preheader3.i.i.i26.preheader
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_mov_b32 s10, 0
.LBB0_120:                              ; %.preheader3.i.i.i26
                                        ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[12:13], v2, s[12:13] offset:40
	global_load_b64 v[16:17], v2, s[12:13]
	v_dual_mov_b32 v15, v4 :: v_dual_mov_b32 v14, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v12, v12, v14
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v12, 24, v[16:17]
	v_and_b32_e32 v16, v13, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[12:13], null, v16, 24, v[4:5]
	v_mov_b32_e32 v4, v12
	global_load_b64 v[12:13], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[12:15], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[14:15]
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_120
; %bb.121:                              ; %Flow475
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_122:                              ; %Flow477
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
.LBB0_123:                              ; %.loopexit4.i.i.i21
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[12:13], v2, s[12:13] offset:40
	global_load_b128 v[14:17], v2, s[12:13]
	v_readfirstlane_b32 s14, v3
	v_readfirstlane_b32 s15, v4
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v12
	v_readfirstlane_b32 s11, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[14:15], s[10:11]
	s_mul_i32 s1, s11, 24
	s_mul_hi_u32 s16, s10, 24
	s_mul_i32 s17, s10, 24
	s_and_saveexec_b32 s18, s0
	s_cbranch_execz .LBB0_125
; %bb.124:                              ;   in Loop: Header=BB0_1 Depth=1
	v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, v2
	s_add_i32 s9, s16, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v12, vcc_lo, v14, s17
	v_add_co_ci_u32_e32 v13, vcc_lo, s9, v15, vcc_lo
	global_store_b128 v[12:13], v[3:6], off offset:8
.LBB0_125:                              ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s18
	s_lshl_b64 s[10:11], s[10:11], 12
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v16, s10
	v_add_co_ci_u32_e32 v12, vcc_lo, s11, v17, vcc_lo
	s_mov_b32 s11, s8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, v3
	s_mov_b32 s9, s8
	s_mov_b32 s10, s8
	v_and_or_b32 v10, 0xffffff1f, v10, 32
	v_add_co_ci_u32_e32 v4, vcc_lo, v12, v4, vcc_lo
	v_dual_mov_b32 v12, v2 :: v_dual_mov_b32 v19, s11
	v_dual_mov_b32 v13, v2 :: v_dual_mov_b32 v18, s10
	v_dual_mov_b32 v17, s9 :: v_dual_mov_b32 v16, s8
	s_clause 0x3
	global_store_b128 v[3:4], v[10:13], off
	global_store_b128 v[3:4], v[16:19], off offset:16
	global_store_b128 v[3:4], v[16:19], off offset:32
	global_store_b128 v[3:4], v[16:19], off offset:48
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB0_133
; %bb.126:                              ;   in Loop: Header=BB0_1 Depth=1
	s_clause 0x1
	global_load_b64 v[20:21], v2, s[12:13] offset:32 glc
	global_load_b64 v[10:11], v2, s[12:13] offset:40
	v_dual_mov_b32 v18, s14 :: v_dual_mov_b32 v19, s15
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v10
	v_readfirstlane_b32 s11, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[14:15]
	s_mul_i32 s11, s11, 24
	s_mul_hi_u32 s18, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s18, s18, s11
	v_add_co_u32 v16, vcc_lo, v14, s10
	v_add_co_ci_u32_e32 v17, vcc_lo, s18, v15, vcc_lo
	s_mov_b32 s10, exec_lo
	global_store_b64 v[16:17], v[20:21], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[12:13], v2, v[18:21], s[12:13] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[12:13], v[20:21]
	s_cbranch_execz .LBB0_129
; %bb.127:                              ; %.preheader1.i.i.i24.preheader
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_mov_b32 s11, 0
.LBB0_128:                              ; %.preheader1.i.i.i24
                                        ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v10, s14 :: v_dual_mov_b32 v11, s15
	s_sleep 1
	global_store_b64 v[16:17], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v2, v[10:13], s[12:13] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[12:13]
	v_dual_mov_b32 v13, v11 :: v_dual_mov_b32 v12, v10
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_128
.LBB0_129:                              ; %Flow473
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	global_load_b64 v[10:11], v2, s[12:13] offset:16
	s_mov_b32 s11, exec_lo
	s_mov_b32 s10, exec_lo
	v_mbcnt_lo_u32_b32 v1, s11, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB0_131
; %bb.130:                              ;   in Loop: Header=BB0_1 Depth=1
	s_bcnt1_i32_b32 s11, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s11
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[10:11], v[1:2], off offset:8
.LBB0_131:                              ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_waitcnt vmcnt(0)
	global_load_b64 v[12:13], v[10:11], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[12:13]
	s_cbranch_vccnz .LBB0_133
; %bb.132:                              ;   in Loop: Header=BB0_1 Depth=1
	global_load_b32 v1, v[10:11], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[12:13], v[1:2], off
	s_and_b32 m0, s10, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_133:                              ; %Flow474
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	s_add_i32 s16, s16, s1
	v_add_co_u32 v1, vcc_lo, v14, s17
	v_add_co_ci_u32_e32 v11, vcc_lo, s16, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v11, vcc_lo
.LBB0_134:                              ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_136
; %bb.135:                              ;   in Loop: Header=BB0_134 Depth=2
	global_load_b32 v1, v[10:11], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB0_136:                              ;   in Loop: Header=BB0_134 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_138
; %bb.137:                              ;   in Loop: Header=BB0_134 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_139
.LBB0_138:                              ;   in Loop: Header=BB0_134 Depth=2
	s_mov_b32 s1, -1
.LBB0_139:                              ; %Flow468
                                        ;   in Loop: Header=BB0_134 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_134
; %bb.140:                              ;   in Loop: Header=BB0_1 Depth=1
	global_load_b128 v[12:15], v[3:4], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_144
; %bb.141:                              ;   in Loop: Header=BB0_1 Depth=1
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[12:13] offset:40
	global_load_b64 v[10:11], v2, s[12:13] offset:24 glc
	global_load_b64 v[16:17], v2, s[12:13]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v18, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v14, vcc_lo, v1, s14
	v_add_co_ci_u32_e32 v15, vcc_lo, s15, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[14:15]
	v_dual_cndmask_b32 v15, v15, v18 :: v_dual_cndmask_b32 v14, v14, v1
	v_and_b32_e32 v1, v15, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v3, v14, v3
	v_mul_hi_u32 v4, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v3, vcc_lo, v16, v3
	v_mov_b32_e32 v16, v10
	v_mul_lo_u32 v1, v1, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v4, vcc_lo, v17, v1, vcc_lo
	v_mov_b32_e32 v17, v11
	global_store_b64 v[3:4], v[10:11], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[16:17], v2, v[14:17], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[16:17], v[10:11]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_144
; %bb.142:                              ; %.preheader.i.i.i23.preheader
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_mov_b32 s0, 0
.LBB0_143:                              ; %.preheader.i.i.i23
                                        ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[3:4], v[16:17], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v2, v[14:17], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[16:17]
	v_dual_mov_b32 v17, v11 :: v_dual_mov_b32 v16, v10
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_143
.LBB0_144:                              ; %__ockl_hostcall_preview.exit.i
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_145:                              ; %__ockl_printf_append_string_n.exit
                                        ;   in Loop: Header=BB0_1 Depth=1
	v_mov_b32_e32 v1, v35
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	v_cmp_eq_u32_e64 s0, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_151
; %bb.146:                              ;   in Loop: Header=BB0_1 Depth=1
	global_load_b64 v[16:17], v2, s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[12:13] offset:40
	global_load_b64 v[10:11], v2, s[12:13]
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v17
	v_and_b32_e32 v3, v3, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v14, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v14, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v10, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v11, v4, vcc_lo
	global_load_b64 v[14:15], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[14:17], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[16:17]
	s_cbranch_execz .LBB0_150
; %bb.147:                              ; %.preheader3.i.i.i33.preheader
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_mov_b32 s10, 0
.LBB0_148:                              ; %.preheader3.i.i.i33
                                        ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[10:11], v2, s[12:13] offset:40
	global_load_b64 v[14:15], v2, s[12:13]
	v_dual_mov_b32 v17, v4 :: v_dual_mov_b32 v16, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v10, v10, v16
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v10, 24, v[14:15]
	v_and_b32_e32 v14, v11, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[10:11], null, v14, 24, v[4:5]
	v_mov_b32_e32 v4, v10
	global_load_b64 v[14:15], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[14:17], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[16:17]
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_148
; %bb.149:                              ; %Flow411
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_150:                              ; %Flow413
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
.LBB0_151:                              ; %.loopexit4.i.i.i27
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[10:11], v2, s[12:13] offset:40
	global_load_b128 v[16:19], v2, s[12:13]
	v_readfirstlane_b32 s14, v3
	v_readfirstlane_b32 s15, v4
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v10
	v_readfirstlane_b32 s11, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[14:15], s[10:11]
	s_mul_i32 s1, s11, 24
	s_mul_hi_u32 s16, s10, 24
	s_mul_i32 s17, s10, 24
	s_and_saveexec_b32 s18, s0
	s_cbranch_execz .LBB0_153
; %bb.152:                              ;   in Loop: Header=BB0_1 Depth=1
	v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, v2
	s_add_i32 s9, s16, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v10, vcc_lo, v16, s17
	v_add_co_ci_u32_e32 v11, vcc_lo, s9, v17, vcc_lo
	global_store_b128 v[10:11], v[3:6], off offset:8
.LBB0_153:                              ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s18
	s_lshl_b64 s[10:11], s[10:11], 12
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v18, s10
	v_add_co_ci_u32_e32 v10, vcc_lo, s11, v19, vcc_lo
	s_mov_b32 s11, s8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, v3
	s_mov_b32 s9, s8
	s_mov_b32 s10, s8
	v_and_or_b32 v12, 0xffffff1f, v12, 32
	v_add_co_ci_u32_e32 v4, vcc_lo, v10, v4, vcc_lo
	v_dual_mov_b32 v14, v7 :: v_dual_mov_b32 v15, v2
	v_dual_mov_b32 v21, s11 :: v_dual_mov_b32 v20, s10
	v_dual_mov_b32 v19, s9 :: v_dual_mov_b32 v18, s8
	s_clause 0x3
	global_store_b128 v[3:4], v[12:15], off
	global_store_b128 v[3:4], v[18:21], off offset:16
	global_store_b128 v[3:4], v[18:21], off offset:32
	global_store_b128 v[3:4], v[18:21], off offset:48
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB0_161
; %bb.154:                              ;   in Loop: Header=BB0_1 Depth=1
	s_clause 0x1
	global_load_b64 v[20:21], v2, s[12:13] offset:32 glc
	global_load_b64 v[10:11], v2, s[12:13] offset:40
	v_dual_mov_b32 v18, s14 :: v_dual_mov_b32 v19, s15
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v10
	v_readfirstlane_b32 s11, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[14:15]
	s_mul_i32 s11, s11, 24
	s_mul_hi_u32 s18, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s18, s18, s11
	v_add_co_u32 v14, vcc_lo, v16, s10
	v_add_co_ci_u32_e32 v15, vcc_lo, s18, v17, vcc_lo
	s_mov_b32 s10, exec_lo
	global_store_b64 v[14:15], v[20:21], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[12:13], v2, v[18:21], s[12:13] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[12:13], v[20:21]
	s_cbranch_execz .LBB0_157
; %bb.155:                              ; %.preheader1.i.i.i31.preheader
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_mov_b32 s11, 0
.LBB0_156:                              ; %.preheader1.i.i.i31
                                        ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v10, s14 :: v_dual_mov_b32 v11, s15
	s_sleep 1
	global_store_b64 v[14:15], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v2, v[10:13], s[12:13] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[12:13]
	v_dual_mov_b32 v13, v11 :: v_dual_mov_b32 v12, v10
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_156
.LBB0_157:                              ; %Flow409
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	global_load_b64 v[10:11], v2, s[12:13] offset:16
	s_mov_b32 s11, exec_lo
	s_mov_b32 s10, exec_lo
	v_mbcnt_lo_u32_b32 v1, s11, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB0_159
; %bb.158:                              ;   in Loop: Header=BB0_1 Depth=1
	s_bcnt1_i32_b32 s11, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s11
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[10:11], v[1:2], off offset:8
.LBB0_159:                              ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_waitcnt vmcnt(0)
	global_load_b64 v[12:13], v[10:11], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[12:13]
	s_cbranch_vccnz .LBB0_161
; %bb.160:                              ;   in Loop: Header=BB0_1 Depth=1
	global_load_b32 v1, v[10:11], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[12:13], v[1:2], off
	s_and_b32 m0, s10, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_161:                              ; %Flow410
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	s_add_i32 s16, s16, s1
	v_add_co_u32 v1, vcc_lo, v16, s17
	v_add_co_ci_u32_e32 v7, vcc_lo, s16, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v7, vcc_lo
.LBB0_162:                              ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_164
; %bb.163:                              ;   in Loop: Header=BB0_162 Depth=2
	global_load_b32 v1, v[10:11], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB0_164:                              ;   in Loop: Header=BB0_162 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_166
; %bb.165:                              ;   in Loop: Header=BB0_162 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_167
.LBB0_166:                              ;   in Loop: Header=BB0_162 Depth=2
	s_mov_b32 s1, -1
.LBB0_167:                              ; %Flow404
                                        ;   in Loop: Header=BB0_162 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_162
; %bb.168:                              ;   in Loop: Header=BB0_1 Depth=1
	global_load_b64 v[10:11], v[3:4], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_172
; %bb.169:                              ;   in Loop: Header=BB0_1 Depth=1
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[12:13] offset:40
	global_load_b64 v[16:17], v2, s[12:13] offset:24 glc
	global_load_b64 v[14:15], v2, s[12:13]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v7, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v12, vcc_lo, v1, s14
	v_add_co_ci_u32_e32 v13, vcc_lo, s15, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[12:13]
	v_dual_cndmask_b32 v13, v13, v7 :: v_dual_cndmask_b32 v12, v12, v1
	v_and_b32_e32 v1, v13, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v3, v12, v3
	v_mul_hi_u32 v4, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v3, vcc_lo, v14, v3
	v_mov_b32_e32 v14, v16
	v_mul_lo_u32 v1, v1, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v4, vcc_lo, v15, v1, vcc_lo
	v_mov_b32_e32 v15, v17
	global_store_b64 v[3:4], v[16:17], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[14:15], v2, v[12:15], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[14:15], v[16:17]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_172
; %bb.170:                              ; %.preheader.i.i.i30.preheader
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_mov_b32 s0, 0
.LBB0_171:                              ; %.preheader.i.i.i30
                                        ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[3:4], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[16:17], v2, v[12:15], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[16:17], v[14:15]
	v_dual_mov_b32 v14, v16 :: v_dual_mov_b32 v15, v17
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_171
.LBB0_172:                              ; %__ockl_printf_append_args.exit
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v1, v35
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	v_cmp_eq_u32_e64 s0, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_178
; %bb.173:                              ;   in Loop: Header=BB0_1 Depth=1
	global_load_b64 v[14:15], v2, s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[12:13] offset:40
	global_load_b64 v[12:13], v2, s[12:13]
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v15
	v_and_b32_e32 v3, v3, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v7, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v7, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v12, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v13, v4, vcc_lo
	global_load_b64 v[12:13], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[12:15], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[14:15]
	s_cbranch_execz .LBB0_177
; %bb.174:                              ; %.preheader3.i.i.i40.preheader
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_mov_b32 s10, 0
.LBB0_175:                              ; %.preheader3.i.i.i40
                                        ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[12:13], v2, s[12:13] offset:40
	global_load_b64 v[16:17], v2, s[12:13]
	v_dual_mov_b32 v15, v4 :: v_dual_mov_b32 v14, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v12, v14
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v7, 24, v[16:17]
	v_and_b32_e32 v7, v13, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[12:13], null, v7, 24, v[4:5]
	v_mov_b32_e32 v4, v12
	global_load_b64 v[12:13], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[12:15], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[14:15]
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_175
; %bb.176:                              ; %Flow397
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_177:                              ; %Flow399
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
.LBB0_178:                              ; %.loopexit4.i.i.i34
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[12:13], v2, s[12:13] offset:40
	global_load_b128 v[14:17], v2, s[12:13]
	v_readfirstlane_b32 s14, v3
	v_readfirstlane_b32 s15, v4
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v12
	v_readfirstlane_b32 s11, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[14:15], s[10:11]
	s_mul_i32 s1, s11, 24
	s_mul_hi_u32 s16, s10, 24
	s_mul_i32 s17, s10, 24
	s_and_saveexec_b32 s18, s0
	s_cbranch_execz .LBB0_180
; %bb.179:                              ;   in Loop: Header=BB0_1 Depth=1
	v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, v2
	s_add_i32 s9, s16, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v12, vcc_lo, v14, s17
	v_add_co_ci_u32_e32 v13, vcc_lo, s9, v15, vcc_lo
	global_store_b128 v[12:13], v[3:6], off offset:8
.LBB0_180:                              ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s18
	s_lshl_b64 s[10:11], s[10:11], 12
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v16, s10
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v17, vcc_lo
	s_mov_b32 s11, s8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, v3
	s_mov_b32 s9, s8
	s_mov_b32 s10, s8
	v_and_or_b32 v10, 0xffffff1f, v10, 32
	v_add_co_ci_u32_e32 v4, vcc_lo, v7, v4, vcc_lo
	v_dual_mov_b32 v12, v8 :: v_dual_mov_b32 v13, v2
	v_dual_mov_b32 v19, s11 :: v_dual_mov_b32 v18, s10
	v_dual_mov_b32 v17, s9 :: v_dual_mov_b32 v16, s8
	s_clause 0x3
	global_store_b128 v[3:4], v[10:13], off
	global_store_b128 v[3:4], v[16:19], off offset:16
	global_store_b128 v[3:4], v[16:19], off offset:32
	global_store_b128 v[3:4], v[16:19], off offset:48
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB0_188
; %bb.181:                              ;   in Loop: Header=BB0_1 Depth=1
	s_clause 0x1
	global_load_b64 v[18:19], v2, s[12:13] offset:32 glc
	global_load_b64 v[7:8], v2, s[12:13] offset:40
	v_dual_mov_b32 v16, s14 :: v_dual_mov_b32 v17, s15
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v7
	v_readfirstlane_b32 s11, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[14:15]
	s_mul_i32 s11, s11, 24
	s_mul_hi_u32 s18, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s18, s18, s11
	v_add_co_u32 v7, vcc_lo, v14, s10
	v_add_co_ci_u32_e32 v8, vcc_lo, s18, v15, vcc_lo
	s_mov_b32 s10, exec_lo
	global_store_b64 v[7:8], v[18:19], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[12:13], v2, v[16:19], s[12:13] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[12:13], v[18:19]
	s_cbranch_execz .LBB0_184
; %bb.182:                              ; %.preheader1.i.i.i38.preheader
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_mov_b32 s11, 0
.LBB0_183:                              ; %.preheader1.i.i.i38
                                        ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v10, s14 :: v_dual_mov_b32 v11, s15
	s_sleep 1
	global_store_b64 v[7:8], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[10:11], v2, v[10:13], s[12:13] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[10:11], v[12:13]
	v_dual_mov_b32 v13, v11 :: v_dual_mov_b32 v12, v10
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_183
.LBB0_184:                              ; %Flow395
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	global_load_b64 v[7:8], v2, s[12:13] offset:16
	s_mov_b32 s11, exec_lo
	s_mov_b32 s10, exec_lo
	v_mbcnt_lo_u32_b32 v1, s11, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB0_186
; %bb.185:                              ;   in Loop: Header=BB0_1 Depth=1
	s_bcnt1_i32_b32 s11, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s11
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[7:8], v[1:2], off offset:8
.LBB0_186:                              ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_waitcnt vmcnt(0)
	global_load_b64 v[10:11], v[7:8], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11]
	s_cbranch_vccnz .LBB0_188
; %bb.187:                              ;   in Loop: Header=BB0_1 Depth=1
	global_load_b32 v1, v[7:8], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[10:11], v[1:2], off
	s_and_b32 m0, s10, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_188:                              ; %Flow396
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	s_add_i32 s16, s16, s1
	v_add_co_u32 v1, vcc_lo, v14, s17
	v_add_co_ci_u32_e32 v8, vcc_lo, s16, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
.LBB0_189:                              ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_191
; %bb.190:                              ;   in Loop: Header=BB0_189 Depth=2
	global_load_b32 v1, v[7:8], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB0_191:                              ;   in Loop: Header=BB0_189 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_193
; %bb.192:                              ;   in Loop: Header=BB0_189 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_194
.LBB0_193:                              ;   in Loop: Header=BB0_189 Depth=2
	s_mov_b32 s1, -1
.LBB0_194:                              ; %Flow390
                                        ;   in Loop: Header=BB0_189 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_189
; %bb.195:                              ;   in Loop: Header=BB0_1 Depth=1
	global_load_b64 v[7:8], v[3:4], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_199
; %bb.196:                              ;   in Loop: Header=BB0_1 Depth=1
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[12:13] offset:40
	global_load_b64 v[14:15], v2, s[12:13] offset:24 glc
	global_load_b64 v[12:13], v2, s[12:13]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v16, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v1, s14
	v_add_co_ci_u32_e32 v11, vcc_lo, s15, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11]
	v_dual_cndmask_b32 v11, v11, v16 :: v_dual_cndmask_b32 v10, v10, v1
	v_and_b32_e32 v1, v11, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v3, v10, v3
	v_mul_hi_u32 v4, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_u32 v3, vcc_lo, v12, v3
	v_mov_b32_e32 v12, v14
	v_mul_lo_u32 v1, v1, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v4, vcc_lo, v13, v1, vcc_lo
	v_mov_b32_e32 v13, v15
	global_store_b64 v[3:4], v[14:15], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[12:13], v2, v[10:13], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[12:13], v[14:15]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_199
; %bb.197:                              ; %.preheader.i.i.i37.preheader
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_mov_b32 s0, 0
.LBB0_198:                              ; %.preheader.i.i.i37
                                        ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[3:4], v[12:13], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[14:15], v2, v[10:13], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[14:15], v[12:13]
	v_dual_mov_b32 v12, v14 :: v_dual_mov_b32 v13, v15
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_198
.LBB0_199:                              ; %__ockl_printf_append_args.exit41
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v1, v35
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	v_cmp_eq_u32_e64 s0, s0, v1
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_205
; %bb.200:                              ;   in Loop: Header=BB0_1 Depth=1
	global_load_b64 v[12:13], v2, s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[3:4], v2, s[12:13] offset:40
	global_load_b64 v[10:11], v2, s[12:13]
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v4, v4, v13
	v_and_b32_e32 v3, v3, v12
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v4, 24
	v_mul_hi_u32 v14, v3, 24
	v_mul_lo_u32 v3, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v14, v4
	s_waitcnt vmcnt(0)
	v_add_co_u32 v3, vcc_lo, v10, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v4, vcc_lo, v11, v4, vcc_lo
	global_load_b64 v[10:11], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[10:13], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[3:4], v[12:13]
	s_cbranch_execz .LBB0_204
; %bb.201:                              ; %.preheader3.i.i.i48.preheader
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_mov_b32 s10, 0
.LBB0_202:                              ; %.preheader3.i.i.i48
                                        ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[10:11], v2, s[12:13] offset:40
	global_load_b64 v[14:15], v2, s[12:13]
	v_dual_mov_b32 v13, v4 :: v_dual_mov_b32 v12, v3
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v10, v10, v12
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[3:4], null, v10, 24, v[14:15]
	v_and_b32_e32 v14, v11, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[10:11], null, v14, 24, v[4:5]
	v_mov_b32_e32 v4, v10
	global_load_b64 v[10:11], v[3:4], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[3:4], v2, v[10:13], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[3:4], v[12:13]
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_202
; %bb.203:                              ; %Flow383
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_204:                              ; %Flow385
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
.LBB0_205:                              ; %.loopexit4.i.i.i42
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[15:16], v2, s[12:13] offset:40
	global_load_b128 v[11:14], v2, s[12:13]
	v_readfirstlane_b32 s14, v3
	v_readfirstlane_b32 s15, v4
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v15
	v_readfirstlane_b32 s11, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[14:15], s[10:11]
	s_mul_i32 s1, s11, 24
	s_mul_hi_u32 s16, s10, 24
	s_mul_i32 s17, s10, 24
	s_and_saveexec_b32 s18, s0
	s_cbranch_execz .LBB0_207
; %bb.206:                              ;   in Loop: Header=BB0_1 Depth=1
	v_dual_mov_b32 v3, s9 :: v_dual_mov_b32 v4, v2
	s_add_i32 s9, s16, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v15, vcc_lo, v11, s17
	v_add_co_ci_u32_e32 v16, vcc_lo, s9, v12, vcc_lo
	global_store_b128 v[15:16], v[3:6], off offset:8
.LBB0_207:                              ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s18
	s_lshl_b64 s[10:11], s[10:11], 12
	v_lshlrev_b64 v[3:4], 6, v[1:2]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v1, vcc_lo, v13, s10
	v_add_co_ci_u32_e32 v10, vcc_lo, s11, v14, vcc_lo
	s_mov_b32 s11, s8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, v3
	s_mov_b32 s9, s8
	s_mov_b32 s10, s8
	v_and_or_b32 v7, 0xffffff1d, v7, 34
	v_add_co_ci_u32_e32 v4, vcc_lo, v10, v4, vcc_lo
	v_mov_b32_e32 v10, v2
	v_dual_mov_b32 v16, s11 :: v_dual_mov_b32 v13, s8
	v_dual_mov_b32 v15, s10 :: v_dual_mov_b32 v14, s9
	s_clause 0x3
	global_store_b128 v[3:4], v[7:10], off
	global_store_b128 v[3:4], v[13:16], off offset:16
	global_store_b128 v[3:4], v[13:16], off offset:32
	global_store_b128 v[3:4], v[13:16], off offset:48
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB0_215
; %bb.208:                              ;   in Loop: Header=BB0_1 Depth=1
	s_clause 0x1
	global_load_b64 v[15:16], v2, s[12:13] offset:32 glc
	global_load_b64 v[3:4], v2, s[12:13] offset:40
	v_dual_mov_b32 v13, s14 :: v_dual_mov_b32 v14, s15
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v3
	v_readfirstlane_b32 s11, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[14:15]
	s_mul_i32 s11, s11, 24
	s_mul_hi_u32 s18, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s18, s18, s11
	v_add_co_u32 v3, vcc_lo, v11, s10
	v_add_co_ci_u32_e32 v4, vcc_lo, s18, v12, vcc_lo
	s_mov_b32 s10, exec_lo
	global_store_b64 v[3:4], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v2, v[13:16], s[12:13] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[9:10], v[15:16]
	s_cbranch_execz .LBB0_211
; %bb.209:                              ; %.preheader1.i.i.i46.preheader
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_mov_b32 s11, 0
.LBB0_210:                              ; %.preheader1.i.i.i46
                                        ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v7, s14 :: v_dual_mov_b32 v8, s15
	s_sleep 1
	global_store_b64 v[3:4], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v2, v[7:10], s[12:13] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[9:10]
	v_dual_mov_b32 v10, v8 :: v_dual_mov_b32 v9, v7
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_210
.LBB0_211:                              ; %Flow381
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	global_load_b64 v[3:4], v2, s[12:13] offset:16
	s_mov_b32 s11, exec_lo
	s_mov_b32 s10, exec_lo
	v_mbcnt_lo_u32_b32 v1, s11, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB0_213
; %bb.212:                              ;   in Loop: Header=BB0_1 Depth=1
	s_bcnt1_i32_b32 s11, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v1, s11
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[3:4], v[1:2], off offset:8
.LBB0_213:                              ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s10
	s_waitcnt vmcnt(0)
	global_load_b64 v[7:8], v[3:4], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[7:8]
	s_cbranch_vccnz .LBB0_215
; %bb.214:                              ;   in Loop: Header=BB0_1 Depth=1
	global_load_b32 v1, v[3:4], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v1
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[7:8], v[1:2], off
	s_and_b32 m0, s10, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_215:                              ; %Flow382
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s9
	s_add_i32 s16, s16, s1
	v_add_co_u32 v1, vcc_lo, v11, s17
	v_add_co_ci_u32_e32 v4, vcc_lo, s16, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v1, 20
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
.LBB0_216:                              ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v1, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_218
; %bb.217:                              ;   in Loop: Header=BB0_216 Depth=2
	global_load_b32 v1, v[3:4], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v1, 1, v1
.LBB0_218:                              ;   in Loop: Header=BB0_216 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v1
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_220
; %bb.219:                              ;   in Loop: Header=BB0_216 Depth=2
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_221
.LBB0_220:                              ;   in Loop: Header=BB0_216 Depth=2
	s_mov_b32 s1, -1
.LBB0_221:                              ; %Flow376
                                        ;   in Loop: Header=BB0_216 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_216
; %bb.222:                              ;   in Loop: Header=BB0_1 Depth=1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_226
; %bb.223:                              ;   in Loop: Header=BB0_1 Depth=1
	s_clause 0x2
	global_load_b64 v[3:4], v2, s[12:13] offset:40
	global_load_b64 v[11:12], v2, s[12:13] offset:24 glc
	global_load_b64 v[9:10], v2, s[12:13]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v1, vcc_lo, v3, 1
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v1, s14
	v_add_co_ci_u32_e32 v8, vcc_lo, s15, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[7:8]
	v_cndmask_b32_e32 v7, v7, v1, vcc_lo
	v_dual_cndmask_b32 v8, v8, v13 :: v_dual_and_b32 v3, v7, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v1, v8, v4
	v_mul_hi_u32 v4, v3, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_lo_u32 v3, v3, 24
	v_add_nc_u32_e32 v1, v4, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v9, v3
	v_mov_b32_e32 v9, v11
	v_add_co_ci_u32_e32 v4, vcc_lo, v10, v1, vcc_lo
	v_mov_b32_e32 v10, v12
	global_store_b64 v[3:4], v[11:12], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[9:10], v2, v[7:10], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[9:10], v[11:12]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_226
; %bb.224:                              ; %.preheader.i.i.i45.preheader
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_mov_b32 s0, 0
.LBB0_225:                              ; %.preheader.i.i.i45
                                        ;   Parent Loop BB0_1 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_sleep 1
	global_store_b64 v[3:4], v[9:10], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v2, v[7:10], s[12:13] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[9:10]
	v_dual_mov_b32 v9, v11 :: v_dual_mov_b32 v10, v12
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_225
.LBB0_226:                              ; %__ockl_printf_append_args.exit49
                                        ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	s_add_i32 s22, s22, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s22, 5
	s_cbranch_scc1 .LBB0_1
; %bb.227:
	v_ashrrev_i32_e32 v1, 31, v33
	v_mov_b32_e32 v0, v33
	v_ashrrev_i32_e32 v33, 31, v32
	s_mov_b32 s0, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_lshlrev_b64 v[2:3], 2, v[32:33]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	s_clause 0x1
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[0:1], off
	s_waitcnt vmcnt(1)
	v_add_nc_u32_e32 v2, v2, v34
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v2, v3
	s_cbranch_execz .LBB0_229
; %bb.228:
	v_mov_b32_e32 v3, 0
	s_waitcnt lgkmcnt(0)
	global_store_b32 v3, v3, s[2:3]
	global_store_b32 v[0:1], v2, off
.LBB0_229:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19bellman_ford_kernelPiP4EdgeS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 39
		.amdhsa_next_free_sgpr 26
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z19bellman_ford_kernelPiP4EdgeS_, .Lfunc_end0-_Z19bellman_ford_kernelPiP4EdgeS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 9460
; NumSgprs: 28
; NumVgprs: 39
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 28
; NumVGPRsForWavesPerEU: 39
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	.str,@object                    ; @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.str:
	.asciz	"%d->%d: %d\n"
	.size	.str, 12

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         104
        .size:           8
        .value_kind:     hidden_hostcall_buffer
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z19bellman_ford_kernelPiP4EdgeS_
    .private_segment_fixed_size: 0
    .sgpr_count:     28
    .sgpr_spill_count: 0
    .symbol:         _Z19bellman_ford_kernelPiP4EdgeS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     39
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
