#include <cuda.h>
#include <iostream>
#include <math.h>
#include <ctime>
#include <cmath>
#include <stdlib.h>
#include <fstream>
#include <sstream>


double* three_dim_index(double* matrix, int i, int j, int k, double m, int b, int num_assets);


double* two_dim_index(double* vector, int i, int j, double m, int b);


__device__ double* two_dim_indexME(double* vector, int i, int j, double m, int b){


double* p;

//specify index layout here
p=&vector[b*(i)+(j)];

return p;


}

__device__ double* three_dim_indexME(double* matrix, int i, int j, int k, double m, int b, int num_assets){

double* p;

p=&matrix[i*b*num_assets+j*num_assets+k];
return p;

}

//this function returns the payoff of a geometric average call option.
__device__ double GeometricPayOffCallM(double* X, int i, int j, double m, int b, int num_assets, double Strike){
double h;
h=1;
for(int l=0; l<num_assets; l++){

                h*= exp(*three_dim_indexME(X, i, j, l, m, b, num_assets));
        }
        h=pow(h,1.0/(num_assets));

        if(h-Strike>0){
                h=h-Strike;
        }
        else{
                h=0;
        }
return h;
}

//this function returns the payoff of a geometric average put option.
__device__ double GeometricPayOffPutM(double* X, int i, int j, double m, int b, int num_assets, double Strike){
double h;
h=1;
for(int l=0; l<num_assets; l++){

                h*=exp(*three_dim_indexME(X, i, j, l, m, b, num_assets));
        }
        h=pow(h,1.0/(num_assets));

        if(Strike-h>0){
                h=Strike-h;
        }
        else{
                h=0;
        }
return h;
}

//this function returns the continuation value given by the inner control.
__device__ double inner_control_meshME(int i, int j, int b, double r, double delta_t, double m, double* W_device, double* X_device, double* V_device, int num_assets ){

int m_int= (int)m;
double ControlMeshContinVal=0;

double sum=0, ContinVal=0, stock_expectation=0, true_stock_expectation=0, numerator=0, denominator=0, beta=0;

for(int k=0; k<b; k++){


        sum+= (*three_dim_indexME(W_device, (m_int-i), k, j, m, b, b)) * (*two_dim_indexME(V_device, (i-1), k, m, b));
}

ContinVal=(1/((double)b))*sum;

sum=0;

for(int l=0; l<b; l++){


        sum+=(*three_dim_indexME(W_device, (m_int-i), l, j, m, b, b)) * exp((*three_dim_indexME(X_device, (m_int-i), l,0 , m, b, num_assets))); 

}
stock_expectation=(1/((double)b))*sum; 

true_stock_expectation=exp(*three_dim_indexME(X_device, (m_int-i-1), j, 0, m, b, num_assets)) * exp(r*delta_t);//old


for(int p=0; p<b; p++){


numerator += ( (*three_dim_indexME(W_device, (m_int-i), p, j, m, b, b)) * exp( *three_dim_indexME(X_device, (m_int-i), p, 0, m, b, num_assets) ) - stock_expectation ) * ( (*three_dim_indexME(W_device, (m_int-i), p, j, m, b, b)) * (*two_dim_indexME(V_device, (i-1), p, m, b)) - ContinVal );


denominator += pow( ( (*three_dim_indexME(W_device, (m_int-i), p, j, m, b, b))  * exp( *three_dim_indexME(X_device, (m_int-i), p, 0, m, b, num_assets) ) - stock_expectation ) , 2 );

}

beta=numerator/denominator;

ControlMeshContinVal= ContinVal-beta*(stock_expectation-true_stock_expectation);

return ControlMeshContinVal;
}



//this kernel updates the V matrix of high bias mesh prices
__global__ void MeshEstimatorKernel(double strike, double r, double delta_t, int b, double m, double* X_device, double* W_device, double* V_device, double* asset_amount_device, int num_assets, int ker){


double H; //payoff variable 
double C; //continuation value variable
int idx =blockDim.x*blockIdx.x + threadIdx.x;

if(idx<b){


	if(ker==0){
			

		H=GeometricPayOffCallM( X_device, m-1-ker, idx, m, b, num_assets, strike)*exp(-r*delta_t*(m-ker));

		*two_dim_indexME(V_device, ker, idx, m, b)=H;
	}
	
	else{


		C=inner_control_meshME(ker, idx, b, r, delta_t, m, W_device, X_device, V_device, num_assets);



		H=GeometricPayOffCallM( X_device, m-1-ker, idx, m, b, num_assets, strike)*exp(-r*delta_t*(m-ker));	
		if(H>=C){

			*two_dim_indexME(V_device, ker, idx, m, b)=H;
			
		}

		else{
			*two_dim_indexME(V_device, ker, idx, m, b)=C;
		}	
	}
	

}

}


//This function allocates memory on the device and reutrns the high bias estimate to the main function.
double MeshEstimator(double strike, double r, double delta_t, int b, double m, double* X, double* W, double* V, double asset_amount[], int num_assets){

double V_0;
int m_int=(int)m;


double* asset_amount_host;
asset_amount_host =asset_amount;


int X_N=(m_int) * b * (num_assets);
int asset_amount_N=num_assets;
int W_N=(m_int) * b*b;
int V_N=(m_int) * b;

double* X_device;
double* V_device;
double* asset_amount_device;
double* W_device;


cudaMalloc((void**) &X_device, X_N*sizeof(double) );
cudaMemcpy(X_device, X, X_N*sizeof(double), cudaMemcpyHostToDevice);

cudaMalloc((void**) &asset_amount_device, asset_amount_N*sizeof(double) );
cudaMemcpy(asset_amount_device, asset_amount_host, asset_amount_N*sizeof(double), cudaMemcpyHostToDevice);

cudaMalloc((void**) &V_device, V_N*sizeof(double) );
cudaMemcpy(V_device, V, V_N*sizeof(double), cudaMemcpyHostToDevice);

cudaMalloc((void**) &W_device, W_N*sizeof(double) );
cudaMemcpy(W_device, W, W_N*sizeof(double), cudaMemcpyHostToDevice);


dim3 gridDim((int)ceil(b/512.0));
dim3 blockDim(512.0);


cudaError_t error = cudaGetLastError();

  if( error != cudaSuccess )
  {
    std::cout << cudaGetErrorString(error) << std::endl;
    printf("found at line %d\n", __LINE__);
    exit(1);
  }


for(int ker=0; ker<m; ker++){
MeshEstimatorKernel<<<gridDim, blockDim>>>(strike, r, delta_t, b, m,  X_device,  W_device, V_device, asset_amount_device, num_assets, ker);

cudaDeviceSynchronize();


error = cudaGetLastError();

  if( error != cudaSuccess )
  {
    std::cout << cudaGetErrorString(error) << std::endl;
    printf("found at line %d\n", __LINE__);
    exit(1);
  }


cudaMemcpy(V, V_device, sizeof(double)*V_N, cudaMemcpyDeviceToHost);

if(ker<m-1){
cudaMemcpy(V_device, V, V_N*sizeof(double), cudaMemcpyHostToDevice);
}

}

cudaFree(X_device);
cudaFree(asset_amount_device);
cudaFree(V_device);
cudaFree(W_device);

double sum=0;

for(int k=0; k<b; k++){

sum+=*two_dim_index(V, (m_int-1), k, m, b);
}
//this is the high bias option value at time 0
V_0=(1/((double)b))*sum;


return V_0;

}

	.file	"tmpxft_002f7d89_00000000-6_cuda_mesh_estimator.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3831:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3831:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z15two_dim_indexMEPdiidi
	.type	_Z15two_dim_indexMEPdiidi, @function
_Z15two_dim_indexMEPdiidi:
.LFB3823:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3823:
	.size	_Z15two_dim_indexMEPdiidi, .-_Z15two_dim_indexMEPdiidi
	.globl	_Z17three_dim_indexMEPdiiidii
	.type	_Z17three_dim_indexMEPdiiidii, @function
_Z17three_dim_indexMEPdiiidii:
.LFB3824:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3824:
	.size	_Z17three_dim_indexMEPdiiidii, .-_Z17three_dim_indexMEPdiiidii
	.globl	_Z20GeometricPayOffCallMPdiidiid
	.type	_Z20GeometricPayOffCallMPdiidiid, @function
_Z20GeometricPayOffCallMPdiidiid:
.LFB3825:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3825:
	.size	_Z20GeometricPayOffCallMPdiidiid, .-_Z20GeometricPayOffCallMPdiidiid
	.globl	_Z19GeometricPayOffPutMPdiidiid
	.type	_Z19GeometricPayOffPutMPdiidiid, @function
_Z19GeometricPayOffPutMPdiidiid:
.LFB4504:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE4504:
	.size	_Z19GeometricPayOffPutMPdiidiid, .-_Z19GeometricPayOffPutMPdiidiid
	.globl	_Z20inner_control_meshMEiiidddPdS_S_i
	.type	_Z20inner_control_meshMEiiidddPdS_S_i, @function
_Z20inner_control_meshMEiiidddPdS_S_i:
.LFB3827:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE3827:
	.size	_Z20inner_control_meshMEiiidddPdS_S_i, .-_Z20inner_control_meshMEiiidddPdS_S_i
	.globl	_Z52__device_stub__Z19MeshEstimatorKerneldddidPdS_S_S_iidddidPdS_S_S_ii
	.type	_Z52__device_stub__Z19MeshEstimatorKerneldddidPdS_S_S_iidddidPdS_S_S_ii, @function
_Z52__device_stub__Z19MeshEstimatorKerneldddidPdS_S_S_iidddidPdS_S_S_ii:
.LFB3853:
	.cfi_startproc
	endbr64
	subq	$248, %rsp
	.cfi_def_cfa_offset 256
	movl	%edi, 52(%rsp)
	leaq	96(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	108(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	80(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	88(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movl	%r9d, 48(%rsp)
	movsd	%xmm0, 72(%rsp)
	movsd	%xmm1, 64(%rsp)
	movsd	%xmm2, 56(%rsp)
	movsd	%xmm3, 40(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 232(%rsp)
	xorl	%eax, %eax
	leaq	72(%rsp), %rax
	movl	$1, 104(%rsp)
	movq	%rax, 144(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	52(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 224(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 96(%rsp)
	movq	%rax, 108(%rsp)
	movl	$1, 116(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	pushq	88(%rsp)
	.cfi_def_cfa_offset 264
	leaq	_Z19MeshEstimatorKerneldddidPdS_S_S_ii(%rip), %rdi
	pushq	88(%rsp)
	.cfi_def_cfa_offset 272
	movq	124(%rsp), %rcx
	movl	132(%rsp), %r8d
	movq	112(%rsp), %rsi
	movl	120(%rsp), %edx
	leaq	160(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 264
	popq	%rdx
	.cfi_def_cfa_offset 256
.L12:
	movq	232(%rsp), %rax
	subq	%fs:40, %rax
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$248, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3853:
	.size	_Z52__device_stub__Z19MeshEstimatorKerneldddidPdS_S_S_iidddidPdS_S_S_ii, .-_Z52__device_stub__Z19MeshEstimatorKerneldddidPdS_S_S_iidddidPdS_S_S_ii
	.globl	_Z19MeshEstimatorKerneldddidPdS_S_S_ii
	.type	_Z19MeshEstimatorKerneldddidPdS_S_S_ii, @function
_Z19MeshEstimatorKerneldddidPdS_S_S_ii:
.LFB3854:
	.cfi_startproc
	endbr64
	jmp	_Z52__device_stub__Z19MeshEstimatorKerneldddidPdS_S_S_iidddidPdS_S_S_ii
	.cfi_endproc
.LFE3854:
	.size	_Z19MeshEstimatorKerneldddidPdS_S_S_ii, .-_Z19MeshEstimatorKerneldddidPdS_S_S_ii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC2:
	.string	"found at line %d\n"
	.text
	.globl	_Z13MeshEstimatordddidPdS_S_S_i
	.type	_Z13MeshEstimatordddidPdS_S_S_i, @function
_Z13MeshEstimatordddidPdS_S_S_i:
.LFB3828:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rsi, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	cvttsd2sil	%xmm3, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%r9d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%edi, %ebx
	movl	%r13d, %r14d
	imull	%edi, %r14d
	subq	$136, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdx, 16(%rsp)
	movl	%r14d, %edx
	movq	%r8, 24(%rsp)
	movl	%r14d, %ebp
	imull	%r9d, %edx
	movq	%rcx, 8(%rsp)
	movsd	%xmm1, 40(%rsp)
	imull	%edi, %ebp
	leaq	64(%rsp), %rdi
	movsd	%xmm2, 48(%rsp)
	movslq	%edx, %rdx
	movsd	%xmm3, (%rsp)
	salq	$3, %rdx
	movsd	%xmm0, 32(%rsp)
	movslq	%ebp, %rbp
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	movq	%rdx, %rsi
	movq	%rdx, 56(%rsp)
	salq	$3, %rbp
	call	cudaMalloc@PLT
	movq	56(%rsp), %rdx
	movq	%r15, %rsi
	movq	64(%rsp), %rdi
	movslq	%r12d, %r15
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	salq	$3, %r15
	leaq	80(%rsp), %rdi
	movq	%r15, %rsi
	call	cudaMalloc@PLT
	movq	24(%rsp), %rsi
	movq	80(%rsp), %rdi
	movq	%r15, %rdx
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movslq	%r14d, %rax
	leaq	72(%rsp), %rdi
	leaq	0(,%rax,8), %r14
	movq	%r14, %rsi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rsi
	movq	72(%rsp), %rdi
	movq	%r14, %rdx
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movq	%rbp, %rsi
	leaq	88(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	16(%rsp), %rsi
	movq	88(%rsp), %rdi
	movq	%rbp, %rdx
	movl	$1, %ecx
	xorl	%ebp, %ebp
	call	cudaMemcpy@PLT
	cvtsi2sdl	%ebx, %xmm4
	movsd	.LC1(%rip), %xmm0
	mulsd	%xmm4, %xmm0
	movsd	%xmm4, 24(%rsp)
	call	ceil@PLT
	movl	$1, 116(%rsp)
	cvttsd2sil	%xmm0, %eax
	movl	%eax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 100(%rsp)
	addq	$511, %rax
	movq	%rax, 108(%rsp)
	call	cudaGetLastError@PLT
	testl	%eax, %eax
	je	.L19
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	leaq	_ZSt4cout(%rip), %rdi
	movq	%rax, %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movl	$213, %edx
	jmp	.L33
.L21:
	movq	72(%rsp), %rsi
	movq	8(%rsp), %rdi
	movl	$2, %ecx
	movq	%r14, %rdx
	call	cudaMemcpy@PLT
	movsd	(%rsp), %xmm0
	subsd	.LC3(%rip), %xmm0
	comisd	16(%rsp), %xmm0
	jbe	.L22
	movq	8(%rsp), %rsi
	movq	72(%rsp), %rdi
	movl	$1, %ecx
	movq	%r14, %rdx
	call	cudaMemcpy@PLT
.L22:
	incl	%ebp
.L19:
	cvtsi2sdl	%ebp, %xmm6
	movsd	(%rsp), %xmm7
	comisd	%xmm6, %xmm7
	movsd	%xmm6, 16(%rsp)
	jbe	.L34
	movl	116(%rsp), %ecx
	movq	108(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	96(%rsp), %rdi
	movl	104(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L20
	pushq	%rax
	.cfi_def_cfa_offset 200
	movl	%r12d, %r9d
	movl	%ebx, %edi
	pushq	%rbp
	.cfi_def_cfa_offset 208
	movq	96(%rsp), %r8
	movq	88(%rsp), %rcx
	movq	104(%rsp), %rdx
	movq	80(%rsp), %rsi
	movsd	16(%rsp), %xmm3
	movsd	64(%rsp), %xmm2
	movsd	56(%rsp), %xmm1
	movsd	48(%rsp), %xmm0
	call	_Z52__device_stub__Z19MeshEstimatorKerneldddidPdS_S_S_iidddidPdS_S_S_ii
	popq	%rdx
	.cfi_def_cfa_offset 200
	popq	%rcx
	.cfi_def_cfa_offset 192
.L20:
	call	cudaDeviceSynchronize@PLT
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	testl	%eax, %eax
	je	.L21
	call	cudaGetErrorString@PLT
	leaq	_ZSt4cout(%rip), %rdi
	movq	%rax, %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movl	$229, %edx
.L33:
	movl	$2, %edi
	leaq	.LC2(%rip), %rsi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	$1, %edi
	call	exit@PLT
.L34:
	movq	64(%rsp), %rdi
	xorl	%ebp, %ebp
	decl	%r13d
	call	cudaFree@PLT
	movq	80(%rsp), %rdi
	call	cudaFree@PLT
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movq	88(%rsp), %rdi
	call	cudaFree@PLT
	xorps	%xmm1, %xmm1
.L25:
	cmpl	%ebx, %ebp
	jge	.L35
	movsd	(%rsp), %xmm0
	movq	8(%rsp), %rdi
	movl	%ebp, %edx
	movl	%ebx, %ecx
	movl	%r13d, %esi
	movsd	%xmm1, 16(%rsp)
	incl	%ebp
	call	_Z13two_dim_indexPdiidi@PLT
	movsd	16(%rsp), %xmm1
	addsd	(%rax), %xmm1
	jmp	.L25
.L35:
	movsd	.LC3(%rip), %xmm0
	divsd	24(%rsp), %xmm0
	mulsd	%xmm1, %xmm0
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L27
	call	__stack_chk_fail@PLT
.L27:
	addq	$136, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3828:
	.size	_Z13MeshEstimatordddidPdS_S_S_i, .-_Z13MeshEstimatordddidPdS_S_S_i
	.section	.rodata.str1.1
.LC4:
	.string	"_Z19MeshEstimatorKerneldddidPdS_S_S_ii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3856:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z19MeshEstimatorKerneldddidPdS_S_S_ii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3856:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC1:
	.long	0
	.long	1063256064
	.align 8
.LC3:
	.long	0
	.long	1072693248
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <hip/hip_runtime.h>
#include <iostream>
#include <math.h>
#include <ctime>
#include <cmath>
#include <stdlib.h>
#include <fstream>
#include <sstream>


double* three_dim_index(double* matrix, int i, int j, int k, double m, int b, int num_assets);


double* two_dim_index(double* vector, int i, int j, double m, int b);


__device__ double* two_dim_indexME(double* vector, int i, int j, double m, int b){


double* p;

//specify index layout here
p=&vector[b*(i)+(j)];

return p;


}

__device__ double* three_dim_indexME(double* matrix, int i, int j, int k, double m, int b, int num_assets){

double* p;

p=&matrix[i*b*num_assets+j*num_assets+k];
return p;

}

//this function returns the payoff of a geometric average call option.
__device__ double GeometricPayOffCallM(double* X, int i, int j, double m, int b, int num_assets, double Strike){
double h;
h=1;
for(int l=0; l<num_assets; l++){

                h*= exp(*three_dim_indexME(X, i, j, l, m, b, num_assets));
        }
        h=pow(h,1.0/(num_assets));

        if(h-Strike>0){
                h=h-Strike;
        }
        else{
                h=0;
        }
return h;
}

//this function returns the payoff of a geometric average put option.
__device__ double GeometricPayOffPutM(double* X, int i, int j, double m, int b, int num_assets, double Strike){
double h;
h=1;
for(int l=0; l<num_assets; l++){

                h*=exp(*three_dim_indexME(X, i, j, l, m, b, num_assets));
        }
        h=pow(h,1.0/(num_assets));

        if(Strike-h>0){
                h=Strike-h;
        }
        else{
                h=0;
        }
return h;
}

//this function returns the continuation value given by the inner control.
__device__ double inner_control_meshME(int i, int j, int b, double r, double delta_t, double m, double* W_device, double* X_device, double* V_device, int num_assets ){

int m_int= (int)m;
double ControlMeshContinVal=0;

double sum=0, ContinVal=0, stock_expectation=0, true_stock_expectation=0, numerator=0, denominator=0, beta=0;

for(int k=0; k<b; k++){


        sum+= (*three_dim_indexME(W_device, (m_int-i), k, j, m, b, b)) * (*two_dim_indexME(V_device, (i-1), k, m, b));
}

ContinVal=(1/((double)b))*sum;

sum=0;

for(int l=0; l<b; l++){


        sum+=(*three_dim_indexME(W_device, (m_int-i), l, j, m, b, b)) * exp((*three_dim_indexME(X_device, (m_int-i), l,0 , m, b, num_assets))); 

}
stock_expectation=(1/((double)b))*sum; 

true_stock_expectation=exp(*three_dim_indexME(X_device, (m_int-i-1), j, 0, m, b, num_assets)) * exp(r*delta_t);//old


for(int p=0; p<b; p++){


numerator += ( (*three_dim_indexME(W_device, (m_int-i), p, j, m, b, b)) * exp( *three_dim_indexME(X_device, (m_int-i), p, 0, m, b, num_assets) ) - stock_expectation ) * ( (*three_dim_indexME(W_device, (m_int-i), p, j, m, b, b)) * (*two_dim_indexME(V_device, (i-1), p, m, b)) - ContinVal );


denominator += pow( ( (*three_dim_indexME(W_device, (m_int-i), p, j, m, b, b))  * exp( *three_dim_indexME(X_device, (m_int-i), p, 0, m, b, num_assets) ) - stock_expectation ) , 2 );

}

beta=numerator/denominator;

ControlMeshContinVal= ContinVal-beta*(stock_expectation-true_stock_expectation);

return ControlMeshContinVal;
}



//this kernel updates the V matrix of high bias mesh prices
__global__ void MeshEstimatorKernel(double strike, double r, double delta_t, int b, double m, double* X_device, double* W_device, double* V_device, double* asset_amount_device, int num_assets, int ker){


double H; //payoff variable 
double C; //continuation value variable
int idx =blockDim.x*blockIdx.x + threadIdx.x;

if(idx<b){


	if(ker==0){
			

		H=GeometricPayOffCallM( X_device, m-1-ker, idx, m, b, num_assets, strike)*exp(-r*delta_t*(m-ker));

		*two_dim_indexME(V_device, ker, idx, m, b)=H;
	}
	
	else{


		C=inner_control_meshME(ker, idx, b, r, delta_t, m, W_device, X_device, V_device, num_assets);



		H=GeometricPayOffCallM( X_device, m-1-ker, idx, m, b, num_assets, strike)*exp(-r*delta_t*(m-ker));	
		if(H>=C){

			*two_dim_indexME(V_device, ker, idx, m, b)=H;
			
		}

		else{
			*two_dim_indexME(V_device, ker, idx, m, b)=C;
		}	
	}
	

}

}


//This function allocates memory on the device and reutrns the high bias estimate to the main function.
double MeshEstimator(double strike, double r, double delta_t, int b, double m, double* X, double* W, double* V, double asset_amount[], int num_assets){

double V_0;
int m_int=(int)m;


double* asset_amount_host;
asset_amount_host =asset_amount;


int X_N=(m_int) * b * (num_assets);
int asset_amount_N=num_assets;
int W_N=(m_int) * b*b;
int V_N=(m_int) * b;

double* X_device;
double* V_device;
double* asset_amount_device;
double* W_device;


hipMalloc((void**) &X_device, X_N*sizeof(double) );
hipMemcpy(X_device, X, X_N*sizeof(double), hipMemcpyHostToDevice);

hipMalloc((void**) &asset_amount_device, asset_amount_N*sizeof(double) );
hipMemcpy(asset_amount_device, asset_amount_host, asset_amount_N*sizeof(double), hipMemcpyHostToDevice);

hipMalloc((void**) &V_device, V_N*sizeof(double) );
hipMemcpy(V_device, V, V_N*sizeof(double), hipMemcpyHostToDevice);

hipMalloc((void**) &W_device, W_N*sizeof(double) );
hipMemcpy(W_device, W, W_N*sizeof(double), hipMemcpyHostToDevice);


dim3 gridDim((int)ceil(b/512.0));
dim3 blockDim(512.0);


hipError_t error = hipGetLastError();

  if( error != hipSuccess )
  {
    std::cout << hipGetErrorString(error) << std::endl;
    printf("found at line %d\n", __LINE__);
    exit(1);
  }


for(int ker=0; ker<m; ker++){
MeshEstimatorKernel<<<gridDim, blockDim>>>(strike, r, delta_t, b, m,  X_device,  W_device, V_device, asset_amount_device, num_assets, ker);

hipDeviceSynchronize();


error = hipGetLastError();

  if( error != hipSuccess )
  {
    std::cout << hipGetErrorString(error) << std::endl;
    printf("found at line %d\n", __LINE__);
    exit(1);
  }


hipMemcpy(V, V_device, sizeof(double)*V_N, hipMemcpyDeviceToHost);

if(ker<m-1){
hipMemcpy(V_device, V, V_N*sizeof(double), hipMemcpyHostToDevice);
}

}

hipFree(X_device);
hipFree(asset_amount_device);
hipFree(V_device);
hipFree(W_device);

double sum=0;

for(int k=0; k<b; k++){

sum+=*two_dim_index(V, (m_int-1), k, m, b);
}
//this is the high bias option value at time 0
V_0=(1/((double)b))*sum;


return V_0;

}

	.text
	.file	"cuda_mesh_estimator.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z34__device_stub__MeshEstimatorKerneldddidPdS_S_S_ii # -- Begin function _Z34__device_stub__MeshEstimatorKerneldddidPdS_S_S_ii
	.type	_Z34__device_stub__MeshEstimatorKerneldddidPdS_S_S_ii,@function
_Z34__device_stub__MeshEstimatorKerneldddidPdS_S_S_ii: # @_Z34__device_stub__MeshEstimatorKerneldddidPdS_S_S_ii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$224, %rsp
	.cfi_def_cfa_offset 272
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	88(%rsp), %rax
	movsd	%xmm0, (%rax)
	leaq	80(%rsp), %r10
	movsd	%xmm1, (%r10)
	leaq	72(%rsp), %r11
	movsd	%xmm2, (%r11)
	leaq	12(%rsp), %r14
	movl	%edi, (%r14)
	leaq	64(%rsp), %rdi
	movsd	%xmm3, (%rdi)
	leaq	56(%rsp), %r15
	movq	%rsi, (%r15)
	leaq	48(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	40(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	32(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	128(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%r10, 8(%rbx)
	movq	%r11, 16(%rbx)
	movq	%r14, 24(%rbx)
	movq	%rdi, 32(%rbx)
	movq	%r15, 40(%rbx)
	movq	%rsi, 48(%rbx)
	movq	%rdx, 56(%rbx)
	movq	%rcx, 64(%rbx)
	movq	%r8, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	112(%rsp), %r14
	leaq	96(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z19MeshEstimatorKerneldddidPdS_S_S_ii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$240, %rsp
	.cfi_adjust_cfa_offset -240
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z34__device_stub__MeshEstimatorKerneldddidPdS_S_S_ii, .Lfunc_end0-_Z34__device_stub__MeshEstimatorKerneldddidPdS_S_S_ii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function _Z13MeshEstimatordddidPdS_S_S_i
.LCPI1_0:
	.quad	0x3f60000000000000              # double 0.001953125
.LCPI1_1:
	.quad	0xbff0000000000000              # double -1
.LCPI1_2:
	.quad	0x3ff0000000000000              # double 1
	.text
	.globl	_Z13MeshEstimatordddidPdS_S_S_i
	.type	_Z13MeshEstimatordddidPdS_S_S_i,@function
_Z13MeshEstimatordddidPdS_S_S_i:        # @_Z13MeshEstimatordddidPdS_S_S_i
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$120, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, %r12d
	movq	%r8, 48(%rsp)                   # 8-byte Spill
	movq	%rcx, %rbx
	movq	%rdx, 16(%rsp)                  # 8-byte Spill
	movq	%rsi, 40(%rsp)                  # 8-byte Spill
	movl	%edi, %ebp
	movsd	%xmm2, 112(%rsp)                # 8-byte Spill
	movsd	%xmm1, 104(%rsp)                # 8-byte Spill
	movsd	%xmm0, 96(%rsp)                 # 8-byte Spill
	movsd	%xmm3, 24(%rsp)                 # 8-byte Spill
	cvttsd2si	%xmm3, %r14d
	movl	%r14d, 68(%rsp)                 # 4-byte Spill
	imull	%edi, %r14d
	movl	%r14d, %eax
	imull	%r9d, %eax
	movl	%r14d, %r13d
	imull	%edi, %r13d
	movslq	%eax, %r15
	shlq	$3, %r15
	leaq	56(%rsp), %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	leaq	56(%rsp), %rax
	movq	(%rax), %rdi
	movq	40(%rsp), %rsi                  # 8-byte Reload
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	%r12d, 40(%rsp)                 # 4-byte Spill
	movslq	%r12d, %r15
	shlq	$3, %r15
	leaq	80(%rsp), %r12
	movq	%r12, %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	movq	(%r12), %rdi
	movq	48(%rsp), %rsi                  # 8-byte Reload
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movslq	%r14d, %r12
	shlq	$3, %r12
	leaq	32(%rsp), %r15
	movq	%r15, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movq	(%r15), %rdi
	movq	%rbx, %rsi
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movslq	%r13d, %r15
	shlq	$3, %r15
	leaq	72(%rsp), %r13
	movq	%r13, %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	movq	(%r13), %rdi
	movq	16(%rsp), %rsi                  # 8-byte Reload
	movq	%r15, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	cvtsi2sd	%ebp, %xmm1
	movsd	.LCPI1_0(%rip), %xmm0           # xmm0 = mem[0],zero
	movsd	%xmm1, 88(%rsp)                 # 8-byte Spill
	mulsd	%xmm1, %xmm0
	callq	ceil@PLT
	movsd	%xmm0, 16(%rsp)                 # 8-byte Spill
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB1_7
# %bb.1:                                # %.preheader
	xorpd	%xmm0, %xmm0
	movsd	24(%rsp), %xmm1                 # 8-byte Reload
                                        # xmm1 = mem[0],zero
	ucomisd	%xmm0, %xmm1
	jbe	.LBB1_9
# %bb.2:                                # %.lr.ph
	movapd	%xmm1, %xmm0
	movabsq	$4294967296, %r13               # imm = 0x100000000
	cvttsd2si	16(%rsp), %r15d         # 8-byte Folded Reload
	btsq	$32, %r15
	movsd	.LCPI1_1(%rip), %xmm1           # xmm1 = mem[0],zero
	addsd	%xmm0, %xmm1
	movsd	%xmm1, 48(%rsp)                 # 8-byte Spill
	xorpd	%xmm1, %xmm1
	movl	$1, %r14d
	addq	$512, %r13                      # imm = 0x200
.LBB1_3:                                # =>This Inner Loop Header: Depth=1
	movsd	%xmm1, 16(%rsp)                 # 8-byte Spill
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_5
# %bb.4:                                #   in Loop: Header=BB1_3 Depth=1
	leal	-1(%r14), %eax
	movq	56(%rsp), %rsi
	movq	72(%rsp), %rdx
	movq	32(%rsp), %rcx
	movq	80(%rsp), %r8
	movl	%eax, (%rsp)
	movsd	96(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	movsd	104(%rsp), %xmm1                # 8-byte Reload
                                        # xmm1 = mem[0],zero
	movsd	112(%rsp), %xmm2                # 8-byte Reload
                                        # xmm2 = mem[0],zero
	movl	%ebp, %edi
	movsd	24(%rsp), %xmm3                 # 8-byte Reload
                                        # xmm3 = mem[0],zero
	movl	40(%rsp), %r9d                  # 4-byte Reload
	callq	_Z34__device_stub__MeshEstimatorKerneldddidPdS_S_S_ii
.LBB1_5:                                #   in Loop: Header=BB1_3 Depth=1
	callq	hipDeviceSynchronize
	callq	hipGetLastError
	testl	%eax, %eax
	jne	.LBB1_6
# %bb.13:                               #   in Loop: Header=BB1_3 Depth=1
	movq	32(%rsp), %rsi
	movq	%rbx, %rdi
	movq	%r12, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movsd	48(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	ucomisd	16(%rsp), %xmm0                 # 8-byte Folded Reload
	jbe	.LBB1_15
# %bb.14:                               #   in Loop: Header=BB1_3 Depth=1
	movq	32(%rsp), %rdi
	movq	%rbx, %rsi
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
.LBB1_15:                               #   in Loop: Header=BB1_3 Depth=1
	xorps	%xmm1, %xmm1
	cvtsi2sd	%r14d, %xmm1
	incl	%r14d
	movsd	24(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	ucomisd	%xmm1, %xmm0
	ja	.LBB1_3
.LBB1_9:                                # %._crit_edge
	movq	56(%rsp), %rdi
	callq	hipFree
	movq	80(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	72(%rsp), %rdi
	callq	hipFree
	testl	%ebp, %ebp
	movl	68(%rsp), %r14d                 # 4-byte Reload
	xorpd	%xmm1, %xmm1
	jle	.LBB1_12
# %bb.10:                               # %.lr.ph76
	decl	%r14d
	xorl	%r15d, %r15d
.LBB1_11:                               # =>This Inner Loop Header: Depth=1
	movsd	%xmm1, 16(%rsp)                 # 8-byte Spill
	movq	%rbx, %rdi
	movl	%r14d, %esi
	movl	%r15d, %edx
	movsd	24(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	movl	%ebp, %ecx
	callq	_Z13two_dim_indexPdiidi
	movsd	16(%rsp), %xmm1                 # 8-byte Reload
                                        # xmm1 = mem[0],zero
	addsd	(%rax), %xmm1
	incl	%r15d
	cmpl	%r15d, %ebp
	jne	.LBB1_11
.LBB1_12:                               # %._crit_edge77
	movsd	.LCPI1_2(%rip), %xmm0           # xmm0 = mem[0],zero
	divsd	88(%rsp), %xmm0                 # 8-byte Folded Reload
	mulsd	%xmm1, %xmm0
	addq	$120, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB1_6:
	.cfi_def_cfa_offset 176
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$_ZSt4cout, %edi
	movq	%rax, %rsi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	callq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
	movl	$.L.str, %edi
	movl	$229, %esi
.LBB1_8:
	xorl	%eax, %eax
	callq	printf
	movl	$1, %edi
	callq	exit
.LBB1_7:
	movl	%eax, %edi
	callq	hipGetErrorString
	movl	$_ZSt4cout, %edi
	movq	%rax, %rsi
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movq	%rax, %rdi
	callq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_
	movl	$.L.str, %edi
	movl	$213, %esi
	jmp	.LBB1_8
.Lfunc_end1:
	.size	_Z13MeshEstimatordddidPdS_S_S_i, .Lfunc_end1-_Z13MeshEstimatordddidPdS_S_S_i
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z19MeshEstimatorKerneldddidPdS_S_S_ii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z19MeshEstimatorKerneldddidPdS_S_S_ii,@object # @_Z19MeshEstimatorKerneldddidPdS_S_S_ii
	.section	.rodata,"a",@progbits
	.globl	_Z19MeshEstimatorKerneldddidPdS_S_S_ii
	.p2align	3, 0x0
_Z19MeshEstimatorKerneldddidPdS_S_S_ii:
	.quad	_Z34__device_stub__MeshEstimatorKerneldddidPdS_S_S_ii
	.size	_Z19MeshEstimatorKerneldddidPdS_S_S_ii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"found at line %d\n"
	.size	.L.str, 18

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z19MeshEstimatorKerneldddidPdS_S_S_ii"
	.size	.L__unnamed_1, 39

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z34__device_stub__MeshEstimatorKerneldddidPdS_S_S_ii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z19MeshEstimatorKerneldddidPdS_S_S_ii
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.p2align	2                               ; -- Begin function _Z20GeometricPayOffCallMPdiidiid
	.type	_Z20GeometricPayOffCallMPdiidiid,@function
_Z20GeometricPayOffCallMPdiidiid:       ; @_Z20GeometricPayOffCallMPdiidiid
; %bb.0:
	s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0x3ff00000
	s_mov_b32 s28, 0
	s_mov_b32 s1, exec_lo
	v_cmpx_lt_i32_e32 0, v5
	s_cbranch_execz .LBB0_4
; %bb.1:                                ; %.lr.ph
	v_mad_u64_u32 v[10:11], null, v4, v2, v[3:4]
	v_mov_b32_e32 v8, 0
	v_mov_b32_e32 v9, 0x3ff00000
	s_mov_b32 s2, 0x652b82fe
	s_mov_b32 s4, 0xfefa39ef
	s_mov_b32 s6, 0x3b39803f
	s_mov_b32 s8, 0xfca7ab0c
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_lo_u32 v2, v10, v5
	s_mov_b32 s10, 0x6a5dcb37
	s_mov_b32 s12, 0x623fde64
	s_mov_b32 s14, 0x7c89e6b0
	s_mov_b32 s16, 0x14761f6e
	s_mov_b32 s18, 0x1852b7b0
	s_mov_b32 s20, 0x11122322
	s_mov_b32 s22, 0x555502a1
	v_ashrrev_i32_e32 v3, 31, v2
	s_mov_b32 s24, 0x55555511
	s_mov_b32 s26, 11
	s_mov_b32 s3, 0x3ff71547
	s_mov_b32 s5, 0xbfe62e42
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_mov_b32 s7, 0xbc7abc9e
	s_mov_b32 s9, 0x3e928af3
	s_mov_b32 s11, 0x3e5ade15
	s_mov_b32 s13, 0x3ec71dee
	s_mov_b32 s15, 0x3efa0199
	v_add_co_u32 v0, vcc_lo, v0, v2
	v_mov_b32_e32 v2, v5
	v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
	s_mov_b32 s17, 0x3f2a01a0
	s_mov_b32 s19, 0x3f56c16c
	s_mov_b32 s21, 0x3f811111
	s_mov_b32 s23, 0x3fa55555
	s_mov_b32 s25, 0x3fc55555
	s_mov_b32 s27, 0x3fe00000
.LBB0_2:                                ; =>This Inner Loop Header: Depth=1
	flat_load_b64 v[3:4], v[0:1]
	v_add_nc_u32_e32 v2, -1, v2
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_mul_f64 v[10:11], v[3:4], s[2:3]
	v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[3:4]
	v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[3:4]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[10:11], v[10:11]
	v_fma_f64 v[12:13], v[10:11], s[4:5], v[3:4]
	v_cvt_i32_f64_e32 v16, v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[10:11], s[6:7], v[12:13]
	v_fma_f64 v[14:15], v[12:13], s[10:11], s[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[12:13], v[14:15], s[12:13]
	v_fma_f64 v[14:15], v[12:13], v[14:15], s[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[12:13], v[14:15], s[16:17]
	v_fma_f64 v[14:15], v[12:13], v[14:15], s[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[12:13], v[14:15], s[20:21]
	v_fma_f64 v[14:15], v[12:13], v[14:15], s[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[12:13], v[14:15], s[24:25]
	v_fma_f64 v[14:15], v[12:13], v[14:15], s[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[12:13], v[14:15], 1.0
	v_fma_f64 v[10:11], v[12:13], v[14:15], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[10:11], v[10:11], v16
	v_cndmask_b32_e32 v11, 0x7ff00000, v11, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v3, 0, v10, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v2
	v_cndmask_b32_e64 v4, 0, v11, s0
	v_add_co_u32 v0, s0, v0, 8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e64 v1, s0, 0, v1, s0
	v_mul_f64 v[8:9], v[8:9], v[3:4]
	s_or_b32 s28, vcc_lo, s28
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s28
	s_cbranch_execnz .LBB0_2
; %bb.3:                                ; %Flow
	s_or_b32 exec_lo, exec_lo, s28
.LBB0_4:                                ; %Flow3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	v_cvt_f64_i32_e32 v[0:1], v5
	s_mov_b32 s1, 0x3fe55555
	s_mov_b32 s0, 0x55555555
	s_mov_b32 s2, 0x968915a9
	s_mov_b32 s4, 0x4222de17
	s_mov_b32 s3, 0x3fba6564
	s_mov_b32 s5, 0x3fbdee67
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[2:3], null, v[0:1], v[0:1], 1.0
	v_div_scale_f64 v[12:13], vcc_lo, 1.0, v[0:1], 1.0
	v_rcp_f64_e32 v[4:5], v[2:3]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[10:11], -v[2:3], v[4:5], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], v[4:5], v[10:11], v[4:5]
	v_fma_f64 v[10:11], -v[2:3], v[4:5], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], v[4:5], v[10:11], v[4:5]
	v_mul_f64 v[10:11], v[12:13], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[2:3], -v[2:3], v[10:11], v[12:13]
	v_div_fmas_f64 v[2:3], v[2:3], v[4:5], v[10:11]
	v_cmp_neq_f64_e32 vcc_lo, 1.0, v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[0:1], v[2:3], v[0:1], 1.0
	v_cndmask_b32_e32 v3, 0x3ff00000, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v2, 0, v0, vcc_lo
	v_cmp_neq_f64_e32 vcc_lo, 0, v[2:3]
	v_cndmask_b32_e32 v1, 0x3ff00000, v9, vcc_lo
	v_cndmask_b32_e32 v0, 0, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_frexp_mant_f64_e64 v[4:5], |v[0:1]|
	v_cmp_gt_f64_e32 vcc_lo, s[0:1], v[4:5]
	v_cndmask_b32_e64 v8, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[4:5], v[4:5], v8
	v_add_f64 v[8:9], v[4:5], 1.0
	v_add_f64 v[14:15], v[4:5], -1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[10:11], v[8:9]
	v_add_f64 v[16:17], v[8:9], -1.0
	v_add_f64 v[4:5], v[4:5], -v[16:17]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[12:13], v[10:11], v[10:11]
	v_fma_f64 v[12:13], -v[8:9], v[10:11], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[12:13], v[10:11], v[10:11]
	v_mul_f64 v[12:13], v[14:15], v[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[18:19], v[8:9], v[12:13]
	v_fma_f64 v[8:9], v[12:13], v[8:9], -v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], v[12:13], v[4:5], v[8:9]
	v_add_f64 v[8:9], v[18:19], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[16:17], v[14:15], -v[8:9]
	v_add_f64 v[18:19], v[8:9], -v[18:19]
	v_add_f64 v[14:15], v[14:15], -v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[4:5], v[18:19], -v[4:5]
	v_add_f64 v[8:9], v[14:15], -v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[4:5], v[4:5], v[8:9]
	v_add_f64 v[4:5], v[16:17], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[4:5], v[10:11], v[4:5]
	v_add_f64 v[8:9], v[12:13], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[10:11], v[8:9], -v[12:13]
	v_mul_f64 v[12:13], v[8:9], v[8:9]
	v_add_f64 v[4:5], v[4:5], -v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[10:11], v[8:9], v[8:9], -v[12:13]
	v_add_f64 v[14:15], v[4:5], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[8:9], v[14:15], v[10:11]
	v_add_f64 v[14:15], v[12:13], v[10:11]
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[16:17], v[14:15], s[4:5], s[2:3]
	s_mov_b32 s2, 0x3abe935a
	s_mov_b32 s3, 0x3fbe25e4
	v_add_f64 v[12:13], v[14:15], -v[12:13]
	v_mul_f64 v[22:23], v[8:9], v[14:15]
	s_mov_b32 s4, 0x652b82fe
	s_mov_b32 s5, 0x3ff71547
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[16:17], v[14:15], v[16:17], s[2:3]
	s_mov_b32 s2, 0x47e6c9c2
	s_mov_b32 s3, 0x3fc110ef
	v_add_f64 v[10:11], v[10:11], -v[12:13]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[16:17], v[14:15], v[16:17], s[2:3]
	s_mov_b32 s2, 0xcfa74449
	s_mov_b32 s3, 0x3fc3b13b
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[16:17], v[14:15], v[16:17], s[2:3]
	s_mov_b32 s2, 0x71bf3c30
	s_mov_b32 s3, 0x3fc745d1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[16:17], v[14:15], v[16:17], s[2:3]
	s_mov_b32 s2, 0x1c7792ce
	s_mov_b32 s3, 0x3fcc71c7
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[16:17], v[14:15], v[16:17], s[2:3]
	s_mov_b32 s2, 0x924920da
	s_mov_b32 s3, 0x3fd24924
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[16:17], v[14:15], v[16:17], s[2:3]
	s_mov_b32 s2, 0x9999999c
	s_mov_b32 s3, 0x3fd99999
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[16:17], v[14:15], v[16:17], s[2:3]
	s_mov_b32 s3, 0x3c7abc9e
	s_mov_b32 s2, 0x3b39803f
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[18:19], v[14:15], v[16:17]
	v_fma_f64 v[12:13], v[14:15], v[16:17], -v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[10:11], v[16:17], v[12:13]
	v_add_f64 v[16:17], v[18:19], v[12:13]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[20:21], v[16:17], s[0:1]
	v_add_f64 v[18:19], v[16:17], -v[18:19]
	s_mov_b32 s1, 0xbfe55555
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_add_f64 v[24:25], v[20:21], s[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_add_f64 v[12:13], v[12:13], -v[18:19]
	v_fma_f64 v[18:19], v[14:15], v[8:9], -v[22:23]
	s_mov_b32 s0, 0xd5df274d
	s_mov_b32 s1, 0x3c8543b0
	v_add_f64 v[16:17], v[16:17], -v[24:25]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[12:13], v[12:13], s[0:1]
	v_fma_f64 v[14:15], v[14:15], v[4:5], v[18:19]
	s_mov_b32 s1, 0x3fe62e42
	s_mov_b32 s0, 0xfefa39ef
	v_ldexp_f64 v[4:5], v[4:5], 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[12:13], v[12:13], v[16:17]
	v_fma_f64 v[10:11], v[10:11], v[8:9], v[14:15]
	v_ldexp_f64 v[8:9], v[8:9], 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[14:15], v[20:21], v[12:13]
	v_add_f64 v[16:17], v[22:23], v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[18:19], v[20:21], -v[14:15]
	v_mul_f64 v[20:21], v[16:17], v[14:15]
	v_add_f64 v[22:23], v[16:17], -v[22:23]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[12:13], v[12:13], v[18:19]
	v_fma_f64 v[18:19], v[16:17], v[14:15], -v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[10:11], v[10:11], -v[22:23]
	v_fma_f64 v[12:13], v[16:17], v[12:13], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[10:11], v[10:11], v[14:15], v[12:13]
	v_frexp_exp_i32_f64_e32 v14, v[0:1]
	v_add_f64 v[12:13], v[20:21], v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_subrev_co_ci_u32_e32 v14, vcc_lo, 0, v14, vcc_lo
	v_cvt_f64_i32_e32 v[14:15], v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[16:17], v[8:9], v[12:13]
	v_add_f64 v[18:19], v[12:13], -v[20:21]
	v_mul_f64 v[20:21], v[14:15], s[0:1]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[8:9], v[16:17], -v[8:9]
	v_add_f64 v[10:11], v[10:11], -v[18:19]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[18:19], v[14:15], s[0:1], -v[20:21]
	s_mov_b32 s1, 0xbfe62e42
	v_add_f64 v[8:9], v[12:13], -v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[4:5], v[4:5], v[10:11]
	v_fma_f64 v[10:11], v[14:15], s[2:3], v[18:19]
	s_mov_b32 s3, 0xbc7abc9e
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[4:5], v[4:5], v[8:9]
	v_add_f64 v[8:9], v[20:21], v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[12:13], v[16:17], v[4:5]
	v_add_f64 v[20:21], v[8:9], -v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[14:15], v[8:9], v[12:13]
	v_add_f64 v[16:17], v[12:13], -v[16:17]
	v_add_f64 v[10:11], v[10:11], -v[20:21]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[18:19], v[14:15], -v[8:9]
	v_add_f64 v[4:5], v[4:5], -v[16:17]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[22:23], v[14:15], -v[18:19]
	v_add_f64 v[12:13], v[12:13], -v[18:19]
	v_add_f64 v[16:17], v[10:11], v[4:5]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[8:9], v[8:9], -v[22:23]
	v_add_f64 v[8:9], v[12:13], v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[12:13], v[16:17], -v[10:11]
	v_add_f64 v[8:9], v[16:17], v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[16:17], v[16:17], -v[12:13]
	v_add_f64 v[4:5], v[4:5], -v[12:13]
	v_add_f64 v[18:19], v[14:15], v[8:9]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[10:11], v[10:11], -v[16:17]
	v_add_f64 v[12:13], v[18:19], -v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[4:5], v[4:5], v[10:11]
	v_add_f64 v[8:9], v[8:9], -v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[4:5], v[4:5], v[8:9]
	v_add_f64 v[8:9], v[18:19], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[10:11], v[8:9], -v[18:19]
	v_mul_f64 v[12:13], v[2:3], v[8:9]
	v_add_f64 v[4:5], v[4:5], -v[10:11]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[8:9], v[2:3], v[8:9], -v[12:13]
	v_cmp_class_f64_e64 vcc_lo, v[12:13], 0x204
	v_fma_f64 v[4:5], v[2:3], v[4:5], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[8:9], v[12:13], v[4:5]
	v_dual_cndmask_b32 v11, v9, v13 :: v_dual_cndmask_b32 v10, v8, v12
	v_add_f64 v[8:9], v[8:9], -v[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f64 v[14:15], v[10:11], s[4:5]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[10:11]|
	v_add_f64 v[4:5], v[4:5], -v[8:9]
	v_mul_f64 v[8:9], v[2:3], 0.5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rndne_f64_e32 v[14:15], v[14:15]
	v_dual_cndmask_b32 v5, 0, v5 :: v_dual_cndmask_b32 v4, 0, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_fma_f64 v[16:17], v[14:15], s[0:1], v[10:11]
	s_mov_b32 s0, 0xfca7ab0c
	s_mov_b32 s1, 0x3e928af3
	v_cvt_i32_f64_e32 v20, v[14:15]
	v_fma_f64 v[16:17], v[14:15], s[2:3], v[16:17]
	s_mov_b32 s2, 0x6a5dcb37
	s_mov_b32 s3, 0x3e5ade15
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[18:19], v[16:17], s[2:3], s[0:1]
	s_mov_b32 s0, 0x623fde64
	s_mov_b32 s1, 0x3ec71dee
	v_cmp_neq_f64_e64 s2, v[2:3], |v[2:3]|
	v_cmp_lt_f64_e64 s3, |v[0:1]|, 1.0
	s_delay_alu instid0(VALU_DEP_3)
	v_fma_f64 v[18:19], v[16:17], v[18:19], s[0:1]
	s_mov_b32 s0, 0x7c89e6b0
	s_mov_b32 s1, 0x3efa0199
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[18:19], v[16:17], v[18:19], s[0:1]
	s_mov_b32 s0, 0x14761f6e
	s_mov_b32 s1, 0x3f2a01a0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[18:19], v[16:17], v[18:19], s[0:1]
	s_mov_b32 s0, 0x1852b7b0
	s_mov_b32 s1, 0x3f56c16c
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[18:19], v[16:17], v[18:19], s[0:1]
	s_mov_b32 s0, 0x11122322
	s_mov_b32 s1, 0x3f811111
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[18:19], v[16:17], v[18:19], s[0:1]
	s_mov_b32 s0, 0x555502a1
	s_mov_b32 s1, 0x3fa55555
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[18:19], v[16:17], v[18:19], s[0:1]
	s_mov_b32 s0, 0x55555511
	s_mov_b32 s1, 0x3fc55555
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[18:19], v[16:17], v[18:19], s[0:1]
	s_mov_b32 s0, 11
	s_mov_b32 s1, 0x3fe00000
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[18:19], v[16:17], v[18:19], s[0:1]
	v_cmp_nlt_f64_e64 s0, 0x40900000, v[10:11]
	v_cmp_ngt_f64_e64 s1, 0xc090cc00, v[10:11]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[18:19], v[16:17], v[18:19], 1.0
	s_and_b32 vcc_lo, s1, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], v[16:17], v[18:19], 1.0
	v_ldexp_f64 v[12:13], v[14:15], v20
	v_trunc_f64_e32 v[14:15], v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v13, 0x7ff00000, v13, s0
	v_cndmask_b32_e32 v10, 0, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v11, 0, v13, s1
	v_trunc_f64_e32 v[12:13], v[8:9]
	v_cmp_eq_f64_e64 s1, v[14:15], v[2:3]
	v_fma_f64 v[4:5], v[10:11], v[4:5], v[10:11]
	v_cmp_class_f64_e64 s0, v[10:11], 0x204
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_neq_f64_e32 vcc_lo, v[12:13], v[8:9]
	v_cndmask_b32_e64 v5, v5, v11, s0
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v4, v4, v10, s0
	v_and_b32_e32 v10, 0x7fffffff, v3
	s_xor_b32 s0, s2, s3
	v_cmp_gt_f64_e64 s2, 0, v[2:3]
	v_cmp_eq_f64_e64 s3, 0, v[0:1]
	v_cndmask_b32_e64 v8, 0, v4, s1
	v_cndmask_b32_e64 v10, v10, 0, s0
	v_and_b32_e32 v11, 0x7fffffff, v1
	s_and_b32 vcc_lo, s1, vcc_lo
	v_cndmask_b32_e32 v9, 0x3ff00000, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_bfi_b32 v5, 0x7fffffff, v5, v9
	v_cndmask_b32_e64 v9, v2, 0, s0
	v_cmp_eq_f64_e64 s0, |v[0:1]|, 1.0
	s_xor_b32 s2, s2, s3
	v_cndmask_b32_e64 v12, 0x7ff80000, v5, s1
	v_cmp_gt_f64_e64 s1, 0, v[0:1]
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e64 v10, v10, v11, s0
	v_cndmask_b32_e64 v9, v9, v0, s0
	v_cmp_class_f64_e64 s0, v[2:3], 0x204
	v_cndmask_b32_e32 v3, 0, v1, vcc_lo
	v_cndmask_b32_e64 v5, v5, v12, s1
	v_cndmask_b32_e64 v4, v4, v8, s1
	v_cmp_class_f64_e64 s1, v[0:1], 0x204
	v_cndmask_b32_e64 v2, 0x7ff00000, 0, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_bfi_b32 v2, 0x7fffffff, v2, v3
	v_cndmask_b32_e64 v3, v4, v9, s0
	v_cndmask_b32_e64 v4, v5, v10, s0
	s_or_b32 vcc_lo, s3, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v2, v4, v2, vcc_lo
	v_cndmask_b32_e64 v3, v3, 0, vcc_lo
	v_cmp_o_f64_e32 vcc_lo, v[0:1], v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v0, 0, v3, vcc_lo
	v_cndmask_b32_e32 v1, 0x7ff80000, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[0:1], v[0:1], -v[6:7]
	v_max_f64 v[0:1], v[0:1], 0
	s_setpc_b64 s[30:31]
.Lfunc_end0:
	.size	_Z20GeometricPayOffCallMPdiidiid, .Lfunc_end0-_Z20GeometricPayOffCallMPdiidiid
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Function info:
; codeLenInByte = 2928
; NumSgprs: 34
; NumVgprs: 26
; ScratchSize: 0
; MemoryBound: 0
	.text
	.protected	_Z19MeshEstimatorKerneldddidPdS_S_S_ii ; -- Begin function _Z19MeshEstimatorKerneldddidPdS_S_S_ii
	.globl	_Z19MeshEstimatorKerneldddidPdS_S_S_ii
	.p2align	8
	.type	_Z19MeshEstimatorKerneldddidPdS_S_S_ii,@function
_Z19MeshEstimatorKerneldddidPdS_S_S_ii: ; @_Z19MeshEstimatorKerneldddidPdS_S_S_ii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x5c
	s_load_b32 s33, s[0:1], 0x18
	s_mov_b32 s32, 0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_mul_i32 s3, s15, s2
	s_mov_b32 s2, exec_lo
	v_add_nc_u32_e32 v26, s3, v0
	v_cmpx_gt_i32_e64 s33, v26
	s_cbranch_execz .LBB1_22
; %bb.1:
	s_clause 0x3
	s_load_b64 s[48:49], s[0:1], 0x48
	s_load_b128 s[44:47], s[0:1], 0x0
	s_load_b64 s[34:35], s[0:1], 0x10
	s_load_b256 s[36:43], s[0:1], 0x20
	s_waitcnt lgkmcnt(0)
	s_cmp_lg_u32 s49, 0
	s_cbranch_scc0 .LBB1_5
; %bb.2:
	v_cvt_i32_f64_e32 v1, s[36:37]
	s_cmp_gt_i32 s33, 0
	s_mul_i32 s50, s33, s33
	s_cselect_b32 s2, -1, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v1
	s_sub_i32 s51, s0, s49
	s_cmp_lt_i32 s33, 1
	s_mul_i32 s50, s50, s51
	s_cbranch_scc1 .LBB1_6
; %bb.3:                                ; %.lr.ph.i
	s_add_i32 s0, s49, -1
	v_mov_b32_e32 v3, 0
	s_mul_i32 s0, s0, s33
	v_mov_b32_e32 v4, 0
	s_ashr_i32 s1, s0, 31
	v_add3_u32 v1, s3, s50, v0
	s_lshl_b64 s[0:1], s[0:1], 3
	s_mov_b32 s4, s33
	s_add_u32 s0, s42, s0
	s_addc_u32 s1, s43, s1
.LBB1_4:                                ; =>This Inner Loop Header: Depth=1
	v_ashrrev_i32_e32 v2, 31, v1
	s_load_b64 s[6:7], s[0:1], 0x0
	s_add_i32 s4, s4, -1
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
	v_lshlrev_b64 v[5:6], 3, v[1:2]
	v_add_nc_u32_e32 v1, s33, v1
	s_cmp_eq_u32 s4, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v5, vcc_lo, s40, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s41, v6, vcc_lo
	global_load_b64 v[5:6], v[5:6], off
	s_waitcnt vmcnt(0) lgkmcnt(0)
	v_fma_f64 v[3:4], v[5:6], s[6:7], v[3:4]
	s_cbranch_scc0 .LBB1_4
	s_branch .LBB1_7
.LBB1_5:
	s_mov_b32 s0, -1
	s_branch .LBB1_20
.LBB1_6:
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v4, 0
.LBB1_7:                                ; %._crit_edge.i
	v_mov_b32_e32 v5, 0
	v_cndmask_b32_e64 v7, 0, 1, s2
	v_mov_b32_e32 v6, 0
	s_mul_i32 s0, s48, s33
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_mul_i32 s2, s0, s51
	s_cbranch_vccnz .LBB1_10
; %bb.8:                                ; %.lr.ph119.i
	v_add3_u32 v1, s3, s50, v0
	s_mov_b32 s4, 0x652b82fe
	s_mov_b32 s6, 0xfefa39ef
	s_mov_b32 s8, 0x3b39803f
	s_mov_b32 s10, 0xfca7ab0c
	s_mov_b32 s12, 0x6a5dcb37
	s_mov_b32 s14, 0x623fde64
	s_mov_b32 s16, 0x7c89e6b0
	s_mov_b32 s18, 0x14761f6e
	s_mov_b32 s20, 0x1852b7b0
	s_mov_b32 s22, 0x11122322
	s_mov_b32 s24, 0x555502a1
	s_mov_b32 s26, 0x55555511
	s_mov_b32 s28, 11
	s_mov_b32 s5, 0x3ff71547
	s_mov_b32 s7, 0xbfe62e42
	s_mov_b32 s9, 0xbc7abc9e
	s_mov_b32 s11, 0x3e928af3
	s_mov_b32 s13, 0x3e5ade15
	s_mov_b32 s15, 0x3ec71dee
	s_mov_b32 s17, 0x3efa0199
	s_mov_b32 s19, 0x3f2a01a0
	s_mov_b32 s21, 0x3f56c16c
	s_mov_b32 s23, 0x3f811111
	s_mov_b32 s25, 0x3fa55555
	s_mov_b32 s27, 0x3fc55555
	s_mov_b32 s29, 0x3fe00000
	s_mul_i32 s30, s0, s51
	s_mov_b32 s1, s33
.LBB1_9:                                ; =>This Inner Loop Header: Depth=1
	s_ashr_i32 s31, s30, 31
	v_ashrrev_i32_e32 v2, 31, v1
	s_lshl_b64 s[52:53], s[30:31], 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s52, s38, s52
	s_addc_u32 s53, s39, s53
	v_lshlrev_b64 v[14:15], 3, v[1:2]
	s_load_b64 s[52:53], s[52:53], 0x0
	s_add_i32 s1, s1, -1
	s_add_i32 s30, s30, s48
	v_add_nc_u32_e32 v1, s33, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v14, vcc_lo, s40, v14
	v_add_co_ci_u32_e32 v15, vcc_lo, s41, v15, vcc_lo
	global_load_b64 v[14:15], v[14:15], off
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[8:9], s[52:53], s[4:5]
	v_cmp_nlt_f64_e64 vcc_lo, 0x40900000, s[52:53]
	v_cmp_ngt_f64_e64 s0, 0xc090cc00, s[52:53]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[8:9], v[8:9]
	v_fma_f64 v[10:11], v[8:9], s[6:7], s[52:53]
	v_cvt_i32_f64_e32 v2, v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[10:11], v[8:9], s[8:9], v[10:11]
	v_fma_f64 v[12:13], v[10:11], s[12:13], s[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[10:11], v[12:13], s[14:15]
	v_fma_f64 v[12:13], v[10:11], v[12:13], s[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[10:11], v[12:13], s[18:19]
	v_fma_f64 v[12:13], v[10:11], v[12:13], s[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[10:11], v[12:13], s[22:23]
	v_fma_f64 v[12:13], v[10:11], v[12:13], s[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[10:11], v[12:13], s[26:27]
	v_fma_f64 v[12:13], v[10:11], v[12:13], s[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[12:13], v[10:11], v[12:13], 1.0
	v_fma_f64 v[8:9], v[10:11], v[12:13], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[8:9], v[8:9], v2
	v_cndmask_b32_e32 v2, 0x7ff00000, v9, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	s_cmp_eq_u32 s1, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v8, 0, v8, vcc_lo
	v_cndmask_b32_e64 v9, 0, v2, s0
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[5:6], v[14:15], v[8:9], v[5:6]
	s_cbranch_scc0 .LBB1_9
.LBB1_10:                               ; %._crit_edge120.i
	v_cvt_f64_i32_e32 v[8:9], s33
	s_add_i32 s51, s51, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s51, s33, v[26:27]
	v_mul_lo_u32 v1, v1, s48
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v2, 31, v1
	v_lshlrev_b64 v[1:2], 3, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s38, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s39, v2, vcc_lo
	global_load_b64 v[1:2], v[1:2], off
	v_div_scale_f64 v[10:11], null, v[8:9], v[8:9], 1.0
	v_div_scale_f64 v[16:17], vcc_lo, 1.0, v[8:9], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[12:13], v[10:11]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
	v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[14:15], -v[10:11], v[12:13], 1.0
	v_fma_f64 v[12:13], v[12:13], v[14:15], v[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[14:15], v[16:17], v[12:13]
	v_fma_f64 v[10:11], -v[10:11], v[14:15], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[10:11], v[10:11], v[12:13], v[14:15]
	v_cmp_ne_u32_e32 vcc_lo, 1, v7
	v_div_fixup_f64 v[8:9], v[10:11], v[8:9], 1.0
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f64 v[3:4], v[8:9], v[3:4]
	v_mul_f64 v[5:6], v[8:9], v[5:6]
	s_cbranch_vccnz .LBB1_14
; %bb.11:                               ; %.lr.ph126.i
	v_mov_b32_e32 v7, 0
	v_mov_b32_e32 v8, 0
	v_add3_u32 v9, s3, s50, v0
	s_add_i32 s76, s49, -1
	s_mov_b32 s4, 0x652b82fe
	s_mov_b32 s6, 0xfefa39ef
	v_dual_mov_b32 v12, v8 :: v_dual_mov_b32 v11, v7
	s_mov_b32 s8, 0x3b39803f
	s_mov_b32 s10, 0xfca7ab0c
	s_mov_b32 s12, 0x6a5dcb37
	s_mov_b32 s14, 0x623fde64
	s_mov_b32 s16, 0x7c89e6b0
	s_mov_b32 s18, 0x14761f6e
	s_mov_b32 s20, 0x1852b7b0
	s_mov_b32 s22, 0x11122322
	s_mov_b32 s24, 0x555502a1
	s_mov_b32 s26, 0x55555511
	s_mov_b32 s28, 11
	s_mov_b32 s30, 0x55555555
	s_mov_b32 s50, 0x968915a9
	s_mov_b32 s52, 0x4222de17
	s_mov_b32 s54, 0x3abe935a
	s_mov_b32 s56, 0x47e6c9c2
	s_mov_b32 s58, 0xcfa74449
	s_mov_b32 s60, 0x71bf3c30
	s_mov_b32 s62, 0x1c7792ce
	s_mov_b32 s64, 0x924920da
	s_mov_b32 s66, 0x9999999c
	s_mov_b32 s68, 0xd5df274d
	s_mul_i32 s76, s76, s33
	s_mov_b32 s77, 0
	s_mov_b32 s5, 0x3ff71547
	s_mov_b32 s7, 0xbfe62e42
	s_mov_b32 s9, 0xbc7abc9e
	s_mov_b32 s11, 0x3e928af3
	s_mov_b32 s13, 0x3e5ade15
	s_mov_b32 s15, 0x3ec71dee
	s_mov_b32 s17, 0x3efa0199
	s_mov_b32 s19, 0x3f2a01a0
	s_mov_b32 s21, 0x3f56c16c
	s_mov_b32 s23, 0x3f811111
	s_mov_b32 s25, 0x3fa55555
	s_mov_b32 s27, 0x3fc55555
	s_mov_b32 s29, 0x3fe00000
	s_mov_b32 s31, 0x3fe55555
	s_mov_b32 s51, 0x3fba6564
	s_mov_b32 s53, 0x3fbdee67
	s_mov_b32 s55, 0x3fbe25e4
	s_mov_b32 s57, 0x3fc110ef
	s_mov_b32 s59, 0x3fc3b13b
	s_mov_b32 s61, 0x3fc745d1
	s_mov_b32 s63, 0x3fcc71c7
	s_mov_b32 s65, 0x3fd24924
	s_mov_b32 s67, 0x3fd99999
	s_mov_b32 s69, 0x3c8543b0
	s_mov_b32 s71, 0x3fe62e42
	s_mov_b32 s73, 0x3c7abc9e
	s_mov_b32 s75, 0xbfe55555
.LBB1_12:                               ; =>This Inner Loop Header: Depth=1
	s_ashr_i32 s3, s2, 31
	v_ashrrev_i32_e32 v10, 31, v9
	s_lshl_b64 s[0:1], s[2:3], 3
	s_mov_b32 s74, s30
	s_add_u32 s0, s38, s0
	s_addc_u32 s1, s39, s1
	v_lshlrev_b64 v[19:20], 3, v[9:10]
	s_load_b64 s[0:1], s[0:1], 0x0
	s_mov_b32 s70, s6
	s_mov_b32 s72, s8
	s_add_i32 s78, s76, s77
	v_add_nc_u32_e32 v9, s33, v9
	v_add_co_u32 v19, vcc_lo, s40, v19
	v_add_co_ci_u32_e32 v20, vcc_lo, s41, v20, vcc_lo
	s_ashr_i32 s79, s78, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	s_lshl_b64 s[78:79], s[78:79], 3
	global_load_b64 v[19:20], v[19:20], off
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[13:14], s[0:1], s[4:5]
	v_cmp_nlt_f64_e64 vcc_lo, 0x40900000, s[0:1]
	v_rndne_f64_e32 v[13:14], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[15:16], v[13:14], s[6:7], s[0:1]
	v_cvt_i32_f64_e32 v0, v[13:14]
	v_cmp_ngt_f64_e64 s0, 0xc090cc00, s[0:1]
	v_fma_f64 v[15:16], v[13:14], s[8:9], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[15:16], s[12:13], s[10:11]
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[16:17]
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[20:21]
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[24:25]
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[26:27]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[15:16], v[17:18], s[28:29]
	v_fma_f64 v[17:18], v[15:16], v[17:18], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], v[15:16], v[17:18], 1.0
	v_ldexp_f64 v[13:14], v[13:14], v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v0, 0x7ff00000, v14, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	s_add_u32 s78, s42, s78
	v_cndmask_b32_e32 v13, 0, v13, vcc_lo
	s_addc_u32 s79, s43, s79
	v_cndmask_b32_e64 v14, 0, v0, s0
	s_load_b64 s[78:79], s[78:79], 0x0
	s_add_i32 s77, s77, 1
	s_add_i32 s2, s2, s48
	s_waitcnt vmcnt(0)
	v_fma_f64 v[13:14], v[19:20], v[13:14], -v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_frexp_mant_f64_e64 v[15:16], |v[13:14]|
	v_cmp_gt_f64_e32 vcc_lo, s[30:31], v[15:16]
	v_cndmask_b32_e64 v0, 0, 1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ldexp_f64 v[15:16], v[15:16], v0
	v_frexp_exp_i32_f64_e32 v0, v[13:14]
	v_add_f64 v[17:18], v[15:16], 1.0
	v_add_f64 v[27:28], v[15:16], -1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e32 v0, vcc_lo, 0, v0, vcc_lo
	v_rcp_f64_e32 v[21:22], v[17:18]
	v_add_f64 v[29:30], v[17:18], -1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_f64 v[15:16], v[15:16], -v[29:30]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[23:24], -v[17:18], v[21:22], 1.0
	v_fma_f64 v[21:22], v[23:24], v[21:22], v[21:22]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[23:24], -v[17:18], v[21:22], 1.0
	v_fma_f64 v[21:22], v[23:24], v[21:22], v[21:22]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[23:24], v[27:28], v[21:22]
	v_mul_f64 v[31:32], v[17:18], v[23:24]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[17:18], v[23:24], v[17:18], -v[31:32]
	v_fma_f64 v[15:16], v[23:24], v[15:16], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[17:18], v[31:32], v[15:16]
	v_add_f64 v[29:30], v[27:28], -v[17:18]
	v_add_f64 v[31:32], v[17:18], -v[31:32]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[27:28], v[27:28], -v[29:30]
	v_add_f64 v[15:16], v[31:32], -v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[17:18], v[27:28], -v[17:18]
	v_add_f64 v[15:16], v[15:16], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[15:16], v[29:30], v[15:16]
	v_mul_f64 v[15:16], v[21:22], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[17:18], v[23:24], v[15:16]
	v_add_f64 v[21:22], v[17:18], -v[23:24]
	v_mul_f64 v[23:24], v[17:18], v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[15:16], v[15:16], -v[21:22]
	v_fma_f64 v[21:22], v[17:18], v[17:18], -v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[27:28], v[15:16], v[15:16]
	v_fma_f64 v[21:22], v[17:18], v[27:28], v[21:22]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[27:28], v[23:24], v[21:22]
	v_fma_f64 v[29:30], v[27:28], s[52:53], s[50:51]
	v_add_f64 v[23:24], v[27:28], -v[23:24]
	v_mul_f64 v[33:34], v[17:18], v[27:28]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[29:30], v[27:28], v[29:30], s[54:55]
	v_add_f64 v[21:22], v[21:22], -v[23:24]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[37:38], v[27:28], v[17:18], -v[33:34]
	v_fma_f64 v[29:30], v[27:28], v[29:30], s[56:57]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[29:30], v[27:28], v[29:30], s[58:59]
	v_fma_f64 v[29:30], v[27:28], v[29:30], s[60:61]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[29:30], v[27:28], v[29:30], s[62:63]
	v_fma_f64 v[29:30], v[27:28], v[29:30], s[64:65]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[29:30], v[27:28], v[29:30], s[66:67]
	v_mul_f64 v[31:32], v[27:28], v[29:30]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f64 v[23:24], v[27:28], v[29:30], -v[31:32]
	v_fma_f64 v[27:28], v[27:28], v[15:16], v[37:38]
	v_ldexp_f64 v[15:16], v[15:16], 1
	v_fma_f64 v[23:24], v[21:22], v[29:30], v[23:24]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[21:22], v[21:22], v[17:18], v[27:28]
	v_ldexp_f64 v[17:18], v[17:18], 1
	v_add_f64 v[29:30], v[31:32], v[23:24]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[27:28], v[33:34], v[21:22]
	v_add_f64 v[35:36], v[29:30], s[30:31]
	v_add_f64 v[31:32], v[29:30], -v[31:32]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[33:34], v[27:28], -v[33:34]
	v_add_f64 v[39:40], v[35:36], s[74:75]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[23:24], v[23:24], -v[31:32]
	v_add_f64 v[21:22], v[21:22], -v[33:34]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[29:30], v[29:30], -v[39:40]
	v_add_f64 v[23:24], v[23:24], s[68:69]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[23:24], v[23:24], v[29:30]
	v_add_f64 v[29:30], v[35:36], v[23:24]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[31:32], v[35:36], -v[29:30]
	v_mul_f64 v[35:36], v[27:28], v[29:30]
	v_add_f64 v[23:24], v[23:24], v[31:32]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[31:32], v[27:28], v[29:30], -v[35:36]
	v_fma_f64 v[23:24], v[27:28], v[23:24], v[31:32]
	v_cvt_f64_i32_e32 v[27:28], v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[21:22], v[21:22], v[29:30], v[23:24]
	v_mul_f64 v[33:34], v[27:28], s[70:71]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[23:24], v[35:36], v[21:22]
	v_add_f64 v[29:30], v[17:18], v[23:24]
	v_add_f64 v[31:32], v[23:24], -v[35:36]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[17:18], v[29:30], -v[17:18]
	v_add_f64 v[21:22], v[21:22], -v[31:32]
	v_fma_f64 v[31:32], v[27:28], s[70:71], -v[33:34]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[17:18], v[23:24], -v[17:18]
	v_add_f64 v[15:16], v[15:16], v[21:22]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[21:22], v[27:28], s[72:73], v[31:32]
	v_add_f64 v[15:16], v[15:16], v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[17:18], v[33:34], v[21:22]
	v_add_f64 v[23:24], v[29:30], v[15:16]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[33:34], v[17:18], -v[33:34]
	v_add_f64 v[27:28], v[17:18], v[23:24]
	v_add_f64 v[29:30], v[23:24], -v[29:30]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[21:22], v[21:22], -v[33:34]
	v_add_f64 v[31:32], v[27:28], -v[17:18]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[15:16], v[15:16], -v[29:30]
	v_add_f64 v[35:36], v[27:28], -v[31:32]
	v_add_f64 v[23:24], v[23:24], -v[31:32]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[29:30], v[21:22], v[15:16]
	v_add_f64 v[17:18], v[17:18], -v[35:36]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[17:18], v[23:24], v[17:18]
	v_add_f64 v[23:24], v[29:30], -v[21:22]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[17:18], v[29:30], v[17:18]
	v_add_f64 v[29:30], v[29:30], -v[23:24]
	v_add_f64 v[15:16], v[15:16], -v[23:24]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[31:32], v[27:28], v[17:18]
	v_add_f64 v[21:22], v[21:22], -v[29:30]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[23:24], v[31:32], -v[27:28]
	v_add_f64 v[15:16], v[15:16], v[21:22]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[17:18], v[17:18], -v[23:24]
	v_add_f64 v[15:16], v[15:16], v[17:18]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[17:18], v[31:32], v[15:16]
	v_add_f64 v[21:22], v[17:18], -v[31:32]
	v_add_f64 v[23:24], v[17:18], v[17:18]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[15:16], v[15:16], -v[21:22]
	v_fma_f64 v[17:18], v[17:18], 2.0, -v[23:24]
	v_cmp_class_f64_e64 vcc_lo, v[23:24], 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[15:16], v[15:16], 2.0, v[17:18]
	v_add_f64 v[17:18], v[23:24], v[15:16]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v22, v18, v24 :: v_dual_cndmask_b32 v21, v17, v23
	v_add_f64 v[17:18], v[17:18], -v[23:24]
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[21:22]|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[15:16], v[15:16], -v[17:18]
	v_cndmask_b32_e32 v16, 0, v16, vcc_lo
	v_mul_f64 v[27:28], v[21:22], s[4:5]
	v_cmp_nlt_f64_e64 s0, 0x40900000, v[21:22]
	v_cmp_ngt_f64_e64 s1, 0xc090cc00, v[21:22]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[27:28], v[27:28]
	v_fma_f64 v[29:30], v[27:28], s[6:7], v[21:22]
	v_cvt_i32_f64_e32 v0, v[27:28]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[29:30], v[27:28], s[8:9], v[29:30]
	v_fma_f64 v[31:32], v[29:30], s[12:13], s[10:11]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[31:32], v[29:30], v[31:32], s[14:15]
	v_fma_f64 v[31:32], v[29:30], v[31:32], s[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[31:32], v[29:30], v[31:32], s[18:19]
	v_fma_f64 v[31:32], v[29:30], v[31:32], s[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[31:32], v[29:30], v[31:32], s[22:23]
	v_fma_f64 v[31:32], v[29:30], v[31:32], s[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[31:32], v[29:30], v[31:32], s[26:27]
	v_fma_f64 v[31:32], v[29:30], v[31:32], s[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[31:32], v[29:30], v[31:32], 1.0
	v_fma_f64 v[27:28], v[29:30], v[31:32], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[23:24], v[27:28], v0
	v_cndmask_b32_e64 v0, 0x7ff00000, v24, s0
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e64 v18, 0, v0, s1
	v_cndmask_b32_e32 v15, 0, v15, vcc_lo
	s_and_b32 vcc_lo, s1, s0
	v_cmp_neq_f64_e64 s0, 0x7ff00000, |v[13:14]|
	v_cndmask_b32_e32 v17, 0, v23, vcc_lo
	v_cmp_neq_f64_e64 s1, 0, v[13:14]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f64 v[15:16], v[17:18], v[15:16], v[17:18]
	v_cmp_class_f64_e64 vcc_lo, v[17:18], 0x204
	v_cndmask_b32_e32 v0, v16, v18, vcc_lo
	s_waitcnt lgkmcnt(0)
	v_fma_f64 v[18:19], v[19:20], s[78:79], -v[3:4]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, 0x7fffffff, v0
	v_cndmask_b32_e32 v10, v15, v17, vcc_lo
	s_and_b32 vcc_lo, s1, s0
	s_cmp_eq_u32 s33, s77
	v_cndmask_b32_e64 v0, 0x7ff00000, v0, s0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v15, 0, v10, vcc_lo
	v_cndmask_b32_e64 v16, 0, v0, s1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[7:8], v[7:8], v[15:16]
	v_fma_f64 v[11:12], v[18:19], v[13:14], v[11:12]
	s_cbranch_scc0 .LBB1_12
; %bb.13:                               ; %._crit_edge127.loopexit.i
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[9:10], null, v[7:8], v[7:8], v[11:12]
	v_rcp_f64_e32 v[13:14], v[9:10]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[15:16], -v[9:10], v[13:14], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
	v_fma_f64 v[15:16], -v[9:10], v[13:14], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[13:14], v[13:14], v[15:16], v[13:14]
	v_div_scale_f64 v[15:16], vcc_lo, v[11:12], v[7:8], v[11:12]
	v_mul_f64 v[17:18], v[15:16], v[13:14]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], -v[9:10], v[17:18], v[15:16]
	v_div_fmas_f64 v[9:10], v[9:10], v[13:14], v[17:18]
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fixup_f64 v[7:8], v[9:10], v[7:8], v[11:12]
	s_branch .LBB1_15
.LBB1_14:
	v_mov_b32_e32 v7, 0
	v_mov_b32_e32 v8, 0x7ff80000
.LBB1_15:                               ; %_Z20inner_control_meshMEiiidddPdS_S_i.exit
	v_mul_f64 v[9:10], s[46:47], s[34:35]
	s_mov_b32 s40, 0x652b82fe
	s_mov_b32 s41, 0x3ff71547
	s_mov_b32 s50, 0xfefa39ef
	s_waitcnt vmcnt(0)
	v_mul_f64 v[13:14], v[1:2], s[40:41]
	s_mov_b32 s51, 0xbfe62e42
	s_mov_b32 s52, 0x3b39803f
	s_mov_b32 s53, 0xbc7abc9e
	s_mov_b32 s54, 0xfca7ab0c
	s_mov_b32 s56, 0x6a5dcb37
	s_mov_b32 s55, 0x3e928af3
	s_mov_b32 s57, 0x3e5ade15
	s_mov_b32 s58, 0x623fde64
	s_mov_b32 s59, 0x3ec71dee
	s_mov_b32 s60, 0x7c89e6b0
	s_mov_b32 s61, 0x3efa0199
	s_mov_b32 s62, 0x14761f6e
	s_mov_b32 s63, 0x3f2a01a0
	s_mov_b32 s64, 0x1852b7b0
	s_mov_b32 s65, 0x3f56c16c
	s_mov_b32 s66, 0x11122322
	s_mov_b32 s67, 0x3f811111
	s_mov_b32 s68, 0x555502a1
	s_mov_b32 s69, 0x3fa55555
	s_mov_b32 s70, 0x55555511
	s_mov_b32 s71, 0x3fc55555
	s_mov_b32 s72, 11
	s_mov_b32 s73, 0x3fe00000
	v_cvt_f64_i32_e32 v[29:30], s49
	v_cmp_nlt_f64_e64 s1, 0x40900000, v[1:2]
	v_cmp_ngt_f64_e64 s2, 0xc090cc00, v[1:2]
	v_mul_f64 v[11:12], v[9:10], s[40:41]
	v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[9:10]
	v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[9:10]
	v_rndne_f64_e32 v[13:14], v[13:14]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rndne_f64_e32 v[11:12], v[11:12]
	v_fma_f64 v[17:18], v[13:14], s[50:51], v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f64 v[15:16], v[11:12], s[50:51], v[9:10]
	v_cvt_i32_f64_e32 v0, v[11:12]
	v_fma_f64 v[17:18], v[13:14], s[52:53], v[17:18]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[15:16], v[11:12], s[52:53], v[15:16]
	v_fma_f64 v[21:22], v[17:18], s[56:57], s[54:55]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[19:20], v[15:16], s[56:57], s[54:55]
	v_fma_f64 v[21:22], v[17:18], v[21:22], s[58:59]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[19:20], v[15:16], v[19:20], s[58:59]
	v_fma_f64 v[21:22], v[17:18], v[21:22], s[60:61]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[19:20], v[15:16], v[19:20], s[60:61]
	v_fma_f64 v[21:22], v[17:18], v[21:22], s[62:63]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[19:20], v[15:16], v[19:20], s[62:63]
	v_fma_f64 v[21:22], v[17:18], v[21:22], s[64:65]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[19:20], v[15:16], v[19:20], s[64:65]
	v_fma_f64 v[21:22], v[17:18], v[21:22], s[66:67]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[19:20], v[15:16], v[19:20], s[66:67]
	v_fma_f64 v[21:22], v[17:18], v[21:22], s[68:69]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[19:20], v[15:16], v[19:20], s[68:69]
	v_fma_f64 v[21:22], v[17:18], v[21:22], s[70:71]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[19:20], v[15:16], v[19:20], s[70:71]
	v_fma_f64 v[21:22], v[17:18], v[21:22], s[72:73]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[19:20], v[15:16], v[19:20], s[72:73]
	v_fma_f64 v[21:22], v[17:18], v[21:22], 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[19:20], v[15:16], v[19:20], 1.0
	v_fma_f64 v[11:12], v[15:16], v[19:20], 1.0
	v_cvt_i32_f64_e32 v15, v[13:14]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[13:14], v[17:18], v[21:22], 1.0
	v_ldexp_f64 v[11:12], v[11:12], v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_ldexp_f64 v[13:14], v[13:14], v15
	v_add_f64 v[15:16], s[36:37], -1.0
	v_cndmask_b32_e32 v12, 0x7ff00000, v12, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v9, 0x7ff00000, v14, s1
	v_add_f64 v[0:1], v[15:16], -v[29:30]
	v_cndmask_b32_e32 v11, 0, v11, vcc_lo
	s_and_b32 vcc_lo, s2, s1
	v_cndmask_b32_e64 v12, 0, v12, s0
	v_cndmask_b32_e64 v10, 0, v9, s2
	v_cndmask_b32_e32 v9, 0, v13, vcc_lo
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, _Z20GeometricPayOffCallMPdiidiid@rel32@lo+4
	s_addc_u32 s1, s1, _Z20GeometricPayOffCallMPdiidiid@rel32@hi+12
	v_cvt_i32_f64_e32 v2, v[0:1]
	v_mov_b32_e32 v0, s38
	v_fma_f64 v[5:6], -v[11:12], v[9:10], v[5:6]
	v_mov_b32_e32 v1, s39
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[27:28], -v[5:6], v[7:8], v[3:4]
	v_dual_mov_b32 v6, s44 :: v_dual_mov_b32 v3, v26
	v_dual_mov_b32 v4, s33 :: v_dual_mov_b32 v5, s48
	v_mov_b32_e32 v7, s45
	s_swappc_b64 s[30:31], s[0:1]
	v_mul_f64 v[2:3], -s[46:47], s[34:35]
	v_add_f64 v[4:5], s[36:37], -v[29:30]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[2:3], v[2:3], v[4:5]
	v_mul_f64 v[4:5], v[2:3], s[40:41]
	v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[2:3]
	v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[2:3]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[4:5], v[4:5]
	v_fma_f64 v[6:7], v[4:5], s[50:51], v[2:3]
	v_cvt_i32_f64_e32 v10, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], v[4:5], s[52:53], v[6:7]
	v_fma_f64 v[8:9], v[6:7], s[56:57], s[54:55]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], v[6:7], v[8:9], s[58:59]
	v_fma_f64 v[8:9], v[6:7], v[8:9], s[60:61]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], v[6:7], v[8:9], s[62:63]
	v_fma_f64 v[8:9], v[6:7], v[8:9], s[64:65]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], v[6:7], v[8:9], s[66:67]
	v_fma_f64 v[8:9], v[6:7], v[8:9], s[68:69]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], v[6:7], v[8:9], s[70:71]
	v_fma_f64 v[8:9], v[6:7], v[8:9], s[72:73]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], v[6:7], v[8:9], 1.0
	v_fma_f64 v[4:5], v[6:7], v[8:9], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[4:5], v[4:5], v10
	v_cndmask_b32_e32 v5, 0x7ff00000, v5, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v2, 0, v4, vcc_lo
	v_cndmask_b32_e64 v3, 0, v5, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f64 v[2:3], v[2:3], v[0:1]
	v_mad_u64_u32 v[0:1], null, s49, s33, v[26:27]
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_add_co_u32 v0, s0, s42, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e64 v1, s0, s43, v1, s0
	s_mov_b32 s0, exec_lo
	v_cmpx_ge_f64_e32 v[2:3], v[27:28]
	s_xor_b32 s0, exec_lo, s0
	s_cbranch_execz .LBB1_17
; %bb.16:
	global_store_b64 v[0:1], v[2:3], off
                                        ; implicit-def: $vgpr0_vgpr1
                                        ; implicit-def: $vgpr27_vgpr28
.LBB1_17:                               ; %Flow
	s_and_not1_saveexec_b32 s0, s0
	s_cbranch_execz .LBB1_19
; %bb.18:
	global_store_b64 v[0:1], v[27:28], off
.LBB1_19:                               ; %Flow127
	s_or_b32 exec_lo, exec_lo, s0
	s_mov_b32 s0, 0
.LBB1_20:                               ; %Flow133
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB1_22
; %bb.21:
	v_add_f64 v[0:1], s[36:37], -1.0
	v_dual_mov_b32 v3, v26 :: v_dual_mov_b32 v4, s33
	v_dual_mov_b32 v5, s48 :: v_dual_mov_b32 v6, s44
	v_mov_b32_e32 v7, s45
	s_getpc_b64 s[0:1]
	s_add_u32 s0, s0, _Z20GeometricPayOffCallMPdiidiid@rel32@lo+4
	s_addc_u32 s1, s1, _Z20GeometricPayOffCallMPdiidiid@rel32@hi+12
	s_delay_alu instid0(VALU_DEP_4)
	v_cvt_i32_f64_e32 v2, v[0:1]
	v_dual_mov_b32 v0, s38 :: v_dual_mov_b32 v1, s39
	s_swappc_b64 s[30:31], s[0:1]
	v_mul_f64 v[2:3], -s[46:47], s[34:35]
	s_mov_b32 s0, 0x652b82fe
	s_mov_b32 s1, 0x3ff71547
	s_mov_b32 s2, 0x6a5dcb37
	s_mov_b32 s3, 0x3e5ade15
	v_ashrrev_i32_e32 v27, 31, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[2:3], v[2:3], s[36:37]
	v_mul_f64 v[4:5], v[2:3], s[0:1]
	s_mov_b32 s0, 0xfefa39ef
	s_mov_b32 s1, 0xbfe62e42
	v_cmp_nlt_f64_e32 vcc_lo, 0x40900000, v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[4:5], v[4:5]
	v_fma_f64 v[6:7], v[4:5], s[0:1], v[2:3]
	s_mov_b32 s0, 0x3b39803f
	s_mov_b32 s1, 0xbc7abc9e
	v_cvt_i32_f64_e32 v10, v[4:5]
	s_delay_alu instid0(VALU_DEP_2)
	v_fma_f64 v[6:7], v[4:5], s[0:1], v[6:7]
	s_mov_b32 s0, 0xfca7ab0c
	s_mov_b32 s1, 0x3e928af3
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[8:9], v[6:7], s[2:3], s[0:1]
	s_mov_b32 s0, 0x623fde64
	s_mov_b32 s1, 0x3ec71dee
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
	s_mov_b32 s0, 0x7c89e6b0
	s_mov_b32 s1, 0x3efa0199
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
	s_mov_b32 s0, 0x14761f6e
	s_mov_b32 s1, 0x3f2a01a0
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
	s_mov_b32 s0, 0x1852b7b0
	s_mov_b32 s1, 0x3f56c16c
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
	s_mov_b32 s0, 0x11122322
	s_mov_b32 s1, 0x3f811111
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
	s_mov_b32 s0, 0x555502a1
	s_mov_b32 s1, 0x3fa55555
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
	s_mov_b32 s0, 0x55555511
	s_mov_b32 s1, 0x3fc55555
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
	s_mov_b32 s0, 11
	s_mov_b32 s1, 0x3fe00000
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_fma_f64 v[8:9], v[6:7], v[8:9], s[0:1]
	v_cmp_ngt_f64_e64 s0, 0xc090cc00, v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], v[6:7], v[8:9], 1.0
	v_fma_f64 v[4:5], v[6:7], v[8:9], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f64 v[4:5], v[4:5], v10
	v_cndmask_b32_e32 v5, 0x7ff00000, v5, vcc_lo
	s_and_b32 vcc_lo, s0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v2, 0, v4, vcc_lo
	v_cndmask_b32_e64 v3, 0, v5, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f64 v[0:1], v[2:3], v[0:1]
	v_lshlrev_b64 v[2:3], 3, v[26:27]
	v_add_co_u32 v2, vcc_lo, s42, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s43, v3, vcc_lo
	global_store_b64 v[2:3], v[0:1], off
.LBB1_22:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z19MeshEstimatorKerneldddidPdS_S_S_ii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 336
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 41
		.amdhsa_next_free_sgpr 80
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z19MeshEstimatorKerneldddidPdS_S_S_ii, .Lfunc_end1-_Z19MeshEstimatorKerneldddidPdS_S_S_ii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 5124
; NumSgprs: 82
; NumVgprs: 41
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 10
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 82
; NumVGPRsForWavesPerEU: 41
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           8
        .value_kind:     by_value
      - .offset:         8
        .size:           8
        .value_kind:     by_value
      - .offset:         16
        .size:           8
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .offset:         72
        .size:           4
        .value_kind:     by_value
      - .offset:         76
        .size:           4
        .value_kind:     by_value
      - .offset:         80
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         84
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         88
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         92
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         94
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         96
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         98
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         100
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         102
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         144
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 336
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z19MeshEstimatorKerneldddidPdS_S_S_ii
    .private_segment_fixed_size: 0
    .sgpr_count:     82
    .sgpr_spill_count: 0
    .symbol:         _Z19MeshEstimatorKerneldddidPdS_S_S_ii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     41
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
