#include <stdio.h>
#include <stdlib.h>

void print_array(int n, char str, float *a) {
	printf("%c:  ", str);
	for(int i=0; i<n; i++) printf("\t%f", a[i]);
	printf("\n");
}

void vecadd(int n, float *a, float *b, float *c) {
	for(int i=0; i<n; i++) {
		c[i] = a[i] + b[i];
	}
}

__global__ void vecadd_gpu(int n, float *a, float *b, float *c, int offset) {
	int tid = blockDim.x*blockIdx.x + threadIdx.x + offset;

	if( tid<n ) {
		c[tid] = a[tid] + b[tid];
	}
}


int main() {
	int i;
	int n=300000000;
	float *a, *b, *c;

	// allocation in host memory
	a = (float *)malloc(n*sizeof(float));
	b = (float *)malloc(n*sizeof(float));
	c = (float *)malloc(n*sizeof(float));

	// initialize
	for(i=0; i<n; i++) {
		//a[i] = i+5.5;
		//b[i] = -1.2*i;
		a[i] = rand()/(RAND_MAX+1.);
		b[i] = rand()/(RAND_MAX+1.);
	}
	//print_array(n, 'a', a);
	//print_array(n, 'b', b);

	// call the function
	vecadd(n, a, b, c);
	//printf("results from CPU\n");
	//print_array(n, 'c', c);

	// allocation in device memory
	float *a_dev, *b_dev, *c_dev;
	cudaMalloc((void**)&a_dev, n*sizeof(float));
	cudaMalloc((void**)&b_dev, n*sizeof(float));
	cudaMalloc((void**)&c_dev, n*sizeof(float));
	
	// copy arrays 'a' and 'b' to the device
	cudaMemcpy(a_dev, a, n*sizeof(float), cudaMemcpyHostToDevice);
	cudaMemcpy(b_dev, b, n*sizeof(float), cudaMemcpyHostToDevice);
	
	// call the kernel
	int tpb =256;	// thread per block
    int max_bpg = 65535;
	int ng = n/(max_bpg*tpb); 	// number of grid
	for(i=0; i<ng; i++) {
		vecadd_gpu<<<max_bpg,tpb>>>(n, a_dev, b_dev, c_dev, i*max_bpg*tpb);
	}
	if( n%(max_bpg*tpb)!=0 ) {
		int nn = n-ng*max_bpg*tpb;
		int bpg = nn%tpb==0 ? nn/tpb : nn/tpb+1;
		vecadd_gpu<<<bpg,tpb>>>(n, a_dev, b_dev, c_dev, ng*max_bpg*tpb);
	}
			
	// copy array 'c' back from the device to the host
	float *c2;
	c2 = (float *)malloc(n*sizeof(float));
	cudaMemcpy(c2, c_dev, n*sizeof(float), cudaMemcpyDeviceToHost);
	//printf("results from GPU\n");
	//print_array(n, 'c', c2);

	printf("n=%d\n", n);
	printf("Check results..");
	float diff;
	for(i=0; i<n; i++) {
		diff = fabs(c2[i]-c[i]);
		if(diff > 1e-7) break;
	}
	if(diff > 1e-7) printf("Mismatch!\n");
	else printf("OK!\n");

	free(a);
	free(b);
	free(c);
	free(c2);
	cudaFree(a_dev);
	cudaFree(b_dev);
	cudaFree(c_dev);
	return 0;
}

	.file	"tmpxft_002158ea_00000000-6_120-vecadd-block.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2032:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2032:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"%c:  "
.LC1:
	.string	"\t%f"
.LC2:
	.string	"\n"
	.text
	.globl	_Z11print_arrayicPf
	.type	_Z11print_arrayicPf, @function
_Z11print_arrayicPf:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	xorl	%eax, %eax
	leaq	.LC1(%rip), %r13
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movq	%rdx, %r12
	movsbl	%sil, %edx
	leaq	.LC0(%rip), %rsi
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movl	%edi, %ebp
	movl	$2, %edi
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	xorl	%ebx, %ebx
	pushq	%rcx
	.cfi_def_cfa_offset 48
	call	__printf_chk@PLT
.L3:
	cmpl	%ebx, %ebp
	jle	.L7
	movq	%r13, %rsi
	movl	$2, %edi
	movb	$1, %al
	cvtss2sd	(%r12,%rbx,4), %xmm0
	call	__printf_chk@PLT
	incq	%rbx
	jmp	.L3
.L7:
	popq	%rdx
	.cfi_def_cfa_offset 40
	leaq	.LC2(%rip), %rsi
	popq	%rbx
	.cfi_def_cfa_offset 32
	movl	$2, %edi
	popq	%rbp
	.cfi_def_cfa_offset 24
	xorl	%eax, %eax
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	__printf_chk@PLT
	.cfi_endproc
.LFE2027:
	.size	_Z11print_arrayicPf, .-_Z11print_arrayicPf
	.globl	_Z6vecaddiPfS_S_
	.type	_Z6vecaddiPfS_S_, @function
_Z6vecaddiPfS_S_:
.LFB2028:
	.cfi_startproc
	endbr64
	xorl	%eax, %eax
.L9:
	cmpl	%eax, %edi
	jle	.L11
	movss	(%rsi,%rax,4), %xmm0
	addss	(%rdx,%rax,4), %xmm0
	movss	%xmm0, (%rcx,%rax,4)
	incq	%rax
	jmp	.L9
.L11:
	ret
	.cfi_endproc
.LFE2028:
	.size	_Z6vecaddiPfS_S_, .-_Z6vecaddiPfS_S_
	.globl	_Z36__device_stub__Z10vecadd_gpuiPfS_S_iiPfS_S_i
	.type	_Z36__device_stub__Z10vecadd_gpuiPfS_S_iiPfS_S_i, @function
_Z36__device_stub__Z10vecadd_gpuiPfS_S_iiPfS_S_i:
.LFB2054:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movl	%edi, 28(%rsp)
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rsp)
	leaq	40(%rsp), %rcx
	movl	%r8d, 24(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	28(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 112(%rsp)
	movq	%rsp, %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	pushq	40(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z10vecadd_gpuiPfS_S_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 176
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L12:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L14
	call	__stack_chk_fail@PLT
.L14:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2054:
	.size	_Z36__device_stub__Z10vecadd_gpuiPfS_S_iiPfS_S_i, .-_Z36__device_stub__Z10vecadd_gpuiPfS_S_iiPfS_S_i
	.globl	_Z10vecadd_gpuiPfS_S_i
	.type	_Z10vecadd_gpuiPfS_S_i, @function
_Z10vecadd_gpuiPfS_S_i:
.LFB2055:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z10vecadd_gpuiPfS_S_iiPfS_S_i
	.cfi_endproc
.LFE2055:
	.size	_Z10vecadd_gpuiPfS_S_i, .-_Z10vecadd_gpuiPfS_S_i
	.section	.rodata.str1.1
.LC4:
	.string	"n=%d\n"
.LC5:
	.string	"Check results.."
.LC8:
	.string	"Mismatch!\n"
.LC9:
	.string	"OK!\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	movl	$1200000000, %edi
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	xorl	%r12d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	subq	$64, %rsp
	.cfi_def_cfa_offset 112
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	call	malloc@PLT
	movl	$1200000000, %edi
	movq	%rax, %rbp
	call	malloc@PLT
	movl	$1200000000, %edi
	movq	%rax, %rbx
	call	malloc@PLT
	movq	%rax, %r13
.L18:
	call	rand@PLT
	cvtsi2sdl	%eax, %xmm0
	mulsd	.LC3(%rip), %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, 0(%rbp,%r12)
	call	rand@PLT
	cvtsi2sdl	%eax, %xmm0
	mulsd	.LC3(%rip), %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, (%rbx,%r12)
	addq	$4, %r12
	cmpq	$1200000000, %r12
	jne	.L18
	movq	%r13, %rcx
	movq	%rbx, %rdx
	movq	%rbp, %rsi
	movl	$300000000, %edi
	call	_Z6vecaddiPfS_S_
	leaq	8(%rsp), %rdi
	xorl	%r12d, %r12d
	movl	$1200000000, %esi
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$1200000000, %esi
	movabsq	$4294967552, %r14
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movl	$1200000000, %esi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$1200000000, %edx
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$1200000000, %edx
	call	cudaMemcpy@PLT
.L20:
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r14, %rdx
	movl	$1, %ecx
	movabsq	$4295032831, %rdi
	movl	$1, %esi
	movq	%r14, 44(%rsp)
	movl	$1, 52(%rsp)
	movq	%rdi, 32(%rsp)
	movl	$1, 40(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	movq	24(%rsp), %rcx
	movq	16(%rsp), %rdx
	movl	%r12d, %r8d
	movl	$300000000, %edi
	movq	8(%rsp), %rsi
	call	_Z36__device_stub__Z10vecadd_gpuiPfS_S_iiPfS_S_i
.L19:
	addl	$16776960, %r12d
	cmpl	$285208320, %r12d
	jne	.L20
	movl	$16777217, %edx
	movl	$1073756269, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$8, %rdx
	salq	$2, %rdi
	movl	$1, %ecx
	movl	$1, %esi
	movq	%rdx, 44(%rsp)
	movl	$1, 52(%rsp)
	movq	%rdi, 32(%rsp)
	movl	$1, 40(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L21
	movq	24(%rsp), %rcx
	movq	16(%rsp), %rdx
	movl	$300000000, %edi
	movl	$285208320, %r8d
	movq	8(%rsp), %rsi
	call	_Z36__device_stub__Z10vecadd_gpuiPfS_S_iiPfS_S_i
.L21:
	movl	$1200000000, %edi
	call	malloc@PLT
	movq	24(%rsp), %rsi
	movl	$2, %ecx
	movl	$1200000000, %edx
	movq	%rax, %rdi
	movq	%rax, %r12
	call	cudaMemcpy@PLT
	movl	$300000000, %edx
	leaq	.LC4(%rip), %rsi
	xorl	%eax, %eax
	movl	$2, %edi
	call	__printf_chk@PLT
	leaq	.LC5(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movsd	.LC7(%rip), %xmm2
	xorl	%eax, %eax
	movss	.LC6(%rip), %xmm1
.L23:
	movss	(%r12,%rax), %xmm0
	subss	0(%r13,%rax), %xmm0
	andps	%xmm1, %xmm0
	cvtss2sd	%xmm0, %xmm0
	comisd	%xmm2, %xmm0
	ja	.L22
	addq	$4, %rax
	cmpq	$1200000000, %rax
	jne	.L23
	leaq	.LC9(%rip), %rsi
	jmp	.L32
.L22:
	leaq	.LC8(%rip), %rsi
.L32:
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	%rbp, %rdi
	call	free@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	%r13, %rdi
	call	free@PLT
	movq	%r12, %rdi
	call	free@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L26
	call	__stack_chk_fail@PLT
.L26:
	addq	$64, %rsp
	.cfi_def_cfa_offset 48
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	main, .-main
	.section	.rodata.str1.1
.LC10:
	.string	"_Z10vecadd_gpuiPfS_S_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2057:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z10vecadd_gpuiPfS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2057:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC3:
	.long	0
	.long	1040187392
	.section	.rodata.cst16,"aM",@progbits,16
	.align 16
.LC6:
	.long	2147483647
	.long	0
	.long	0
	.long	0
	.section	.rodata.cst8
	.align 8
.LC7:
	.long	-1698910392
	.long	1048238066
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <stdio.h>
#include <stdlib.h>

void print_array(int n, char str, float *a) {
	printf("%c:  ", str);
	for(int i=0; i<n; i++) printf("\t%f", a[i]);
	printf("\n");
}

void vecadd(int n, float *a, float *b, float *c) {
	for(int i=0; i<n; i++) {
		c[i] = a[i] + b[i];
	}
}

__global__ void vecadd_gpu(int n, float *a, float *b, float *c, int offset) {
	int tid = blockDim.x*blockIdx.x + threadIdx.x + offset;

	if( tid<n ) {
		c[tid] = a[tid] + b[tid];
	}
}


int main() {
	int i;
	int n=300000000;
	float *a, *b, *c;

	// allocation in host memory
	a = (float *)malloc(n*sizeof(float));
	b = (float *)malloc(n*sizeof(float));
	c = (float *)malloc(n*sizeof(float));

	// initialize
	for(i=0; i<n; i++) {
		//a[i] = i+5.5;
		//b[i] = -1.2*i;
		a[i] = rand()/(RAND_MAX+1.);
		b[i] = rand()/(RAND_MAX+1.);
	}
	//print_array(n, 'a', a);
	//print_array(n, 'b', b);

	// call the function
	vecadd(n, a, b, c);
	//printf("results from CPU\n");
	//print_array(n, 'c', c);

	// allocation in device memory
	float *a_dev, *b_dev, *c_dev;
	hipMalloc((void**)&a_dev, n*sizeof(float));
	hipMalloc((void**)&b_dev, n*sizeof(float));
	hipMalloc((void**)&c_dev, n*sizeof(float));
	
	// copy arrays 'a' and 'b' to the device
	hipMemcpy(a_dev, a, n*sizeof(float), hipMemcpyHostToDevice);
	hipMemcpy(b_dev, b, n*sizeof(float), hipMemcpyHostToDevice);
	
	// call the kernel
	int tpb =256;	// thread per block
    int max_bpg = 65535;
	int ng = n/(max_bpg*tpb); 	// number of grid
	for(i=0; i<ng; i++) {
		vecadd_gpu<<<max_bpg,tpb>>>(n, a_dev, b_dev, c_dev, i*max_bpg*tpb);
	}
	if( n%(max_bpg*tpb)!=0 ) {
		int nn = n-ng*max_bpg*tpb;
		int bpg = nn%tpb==0 ? nn/tpb : nn/tpb+1;
		vecadd_gpu<<<bpg,tpb>>>(n, a_dev, b_dev, c_dev, ng*max_bpg*tpb);
	}
			
	// copy array 'c' back from the device to the host
	float *c2;
	c2 = (float *)malloc(n*sizeof(float));
	hipMemcpy(c2, c_dev, n*sizeof(float), hipMemcpyDeviceToHost);
	//printf("results from GPU\n");
	//print_array(n, 'c', c2);

	printf("n=%d\n", n);
	printf("Check results..");
	float diff;
	for(i=0; i<n; i++) {
		diff = fabs(c2[i]-c[i]);
		if(diff > 1e-7) break;
	}
	if(diff > 1e-7) printf("Mismatch!\n");
	else printf("OK!\n");

	free(a);
	free(b);
	free(c);
	free(c2);
	hipFree(a_dev);
	hipFree(b_dev);
	hipFree(c_dev);
	return 0;
}

	.text
	.file	"120-vecadd-block.hip"
	.globl	_Z11print_arrayicPf             # -- Begin function _Z11print_arrayicPf
	.type	_Z11print_arrayicPf,@function
_Z11print_arrayicPf:                    # @_Z11print_arrayicPf
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rdx, %rbx
	movl	%edi, %ebp
	movl	$.L.str, %edi
	xorl	%eax, %eax
	callq	printf
	testl	%ebp, %ebp
	jle	.LBB0_3
# %bb.1:                                # %.lr.ph.preheader
	movl	%ebp, %r14d
	xorl	%r15d, %r15d
.LBB0_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rbx,%r15,4), %xmm0
	movl	$.L.str.1, %edi
	movb	$1, %al
	callq	printf
	incq	%r15
	cmpq	%r15, %r14
	jne	.LBB0_2
.LBB0_3:                                # %._crit_edge
	movl	$10, %edi
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	putchar@PLT                     # TAILCALL
.Lfunc_end0:
	.size	_Z11print_arrayicPf, .Lfunc_end0-_Z11print_arrayicPf
	.cfi_endproc
                                        # -- End function
	.globl	_Z6vecaddiPfS_S_                # -- Begin function _Z6vecaddiPfS_S_
	.type	_Z6vecaddiPfS_S_,@function
_Z6vecaddiPfS_S_:                       # @_Z6vecaddiPfS_S_
	.cfi_startproc
# %bb.0:
	testl	%edi, %edi
	jle	.LBB1_3
# %bb.1:                                # %.lr.ph.preheader
	movl	%edi, %eax
	xorl	%edi, %edi
.LBB1_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movss	(%rsi,%rdi,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	addss	(%rdx,%rdi,4), %xmm0
	movss	%xmm0, (%rcx,%rdi,4)
	incq	%rdi
	cmpq	%rdi, %rax
	jne	.LBB1_2
.LBB1_3:                                # %._crit_edge
	retq
.Lfunc_end1:
	.size	_Z6vecaddiPfS_S_, .Lfunc_end1-_Z6vecaddiPfS_S_
	.cfi_endproc
                                        # -- End function
	.globl	_Z25__device_stub__vecadd_gpuiPfS_S_i # -- Begin function _Z25__device_stub__vecadd_gpuiPfS_S_i
	.type	_Z25__device_stub__vecadd_gpuiPfS_S_i,@function
_Z25__device_stub__vecadd_gpuiPfS_S_i:  # @_Z25__device_stub__vecadd_gpuiPfS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	leaq	40(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	32(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	24(%rsp), %rdx
	movq	%rcx, (%rdx)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10vecadd_gpuiPfS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z25__device_stub__vecadd_gpuiPfS_S_i, .Lfunc_end2-_Z25__device_stub__vecadd_gpuiPfS_S_i
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI3_0:
	.quad	0x3e00000000000000              # double 4.6566128730773926E-10
.LCPI3_2:
	.quad	0x3e7ad7f29abcaf48              # double 9.9999999999999995E-8
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0
.LCPI3_1:
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.long	0x7fffffff                      # float NaN
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$1200000000, %edi               # imm = 0x47868C00
	callq	malloc
	movq	%rax, %rbx
	movl	$1200000000, %edi               # imm = 0x47868C00
	callq	malloc
	movq	%rax, %r14
	movl	$1200000000, %edi               # imm = 0x47868C00
	callq	malloc
	movq	%rax, %r15
	xorl	%r12d, %r12d
.LBB3_1:                                # =>This Inner Loop Header: Depth=1
	callq	rand
	xorps	%xmm0, %xmm0
	cvtsi2sd	%eax, %xmm0
	movsd	.LCPI3_0(%rip), %xmm1           # xmm1 = mem[0],zero
	mulsd	%xmm1, %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, (%rbx,%r12,4)
	callq	rand
	xorps	%xmm0, %xmm0
	cvtsi2sd	%eax, %xmm0
	mulsd	.LCPI3_0(%rip), %xmm0
	cvtsd2ss	%xmm0, %xmm0
	movss	%xmm0, (%r14,%r12,4)
	incq	%r12
	cmpq	$300000000, %r12                # imm = 0x11E1A300
	jne	.LBB3_1
# %bb.2:                                # %.lr.ph.i.preheader
	xorl	%eax, %eax
.LBB3_3:                                # %.lr.ph.i
                                        # =>This Inner Loop Header: Depth=1
	movss	(%rbx,%rax,4), %xmm0            # xmm0 = mem[0],zero,zero,zero
	addss	(%r14,%rax,4), %xmm0
	movss	%xmm0, (%r15,%rax,4)
	incq	%rax
	cmpq	$300000000, %rax                # imm = 0x11E1A300
	jne	.LBB3_3
# %bb.4:                                # %_Z6vecaddiPfS_S_.exit
	movabsq	$4294967552, %r12               # imm = 0x100000100
	leaq	16(%rsp), %r13
	movl	$1200000000, %esi               # imm = 0x47868C00
	movq	%r13, %rdi
	callq	hipMalloc
	leaq	8(%rsp), %rbp
	movl	$1200000000, %esi               # imm = 0x47868C00
	movq	%rbp, %rdi
	callq	hipMalloc
	movq	%rsp, %rdi
	movl	$1200000000, %esi               # imm = 0x47868C00
	callq	hipMalloc
	movq	(%r13), %rdi
	movl	$1200000000, %edx               # imm = 0x47868C00
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movq	(%rbp), %rdi
	movl	$1200000000, %edx               # imm = 0x47868C00
	movq	%r14, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	xorl	%r13d, %r13d
	leaq	65279(%r12), %rbp
.LBB3_5:                                # =>This Inner Loop Header: Depth=1
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_7
# %bb.6:                                #   in Loop: Header=BB3_5 Depth=1
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	movq	(%rsp), %rcx
	movl	$300000000, %edi                # imm = 0x11E1A300
	movl	%r13d, %r8d
	callq	_Z25__device_stub__vecadd_gpuiPfS_S_i
.LBB3_7:                                #   in Loop: Header=BB3_5 Depth=1
	addl	$16776960, %r13d                # imm = 0xFFFF00
	cmpl	$285208320, %r13d               # imm = 0x10FFEF00
	jne	.LBB3_5
# %bb.8:
	leaq	57524(%r12), %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_10
# %bb.9:
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	movq	(%rsp), %rcx
	movl	$300000000, %edi                # imm = 0x11E1A300
	movl	$285208320, %r8d                # imm = 0x10FFEF00
	callq	_Z25__device_stub__vecadd_gpuiPfS_S_i
.LBB3_10:
	movl	$1200000000, %edi               # imm = 0x47868C00
	callq	malloc
	movq	%rax, %r12
	movq	(%rsp), %rsi
	movl	$1200000000, %edx               # imm = 0x47868C00
	movq	%rax, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	xorl	%r13d, %r13d
	movl	$.L.str.3, %edi
	movl	$300000000, %esi                # imm = 0x11E1A300
	xorl	%eax, %eax
	callq	printf
	movl	$.L.str.4, %edi
	xorl	%eax, %eax
	callq	printf
	movaps	.LCPI3_1(%rip), %xmm0           # xmm0 = [NaN,NaN,NaN,NaN]
	movsd	.LCPI3_2(%rip), %xmm1           # xmm1 = mem[0],zero
.LBB3_11:                               # =>This Inner Loop Header: Depth=1
	movss	(%r12,%r13,4), %xmm2            # xmm2 = mem[0],zero,zero,zero
	subss	(%r15,%r13,4), %xmm2
	andps	%xmm0, %xmm2
	cvtss2sd	%xmm2, %xmm2
	ucomisd	%xmm1, %xmm2
	ja	.LBB3_14
# %bb.12:                               #   in Loop: Header=BB3_11 Depth=1
	incq	%r13
	cmpq	$300000000, %r13                # imm = 0x11E1A300
	jne	.LBB3_11
# %bb.13:
	movl	$.Lstr, %edi
	jmp	.LBB3_15
.LBB3_14:
	movl	$.Lstr.1, %edi
.LBB3_15:
	callq	puts@PLT
	movq	%rbx, %rdi
	callq	free
	movq	%r14, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	movq	%r12, %rdi
	callq	free
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	main, .Lfunc_end3-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10vecadd_gpuiPfS_S_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"%c:  "
	.size	.L.str, 6

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"\t%f"
	.size	.L.str.1, 4

	.type	_Z10vecadd_gpuiPfS_S_i,@object  # @_Z10vecadd_gpuiPfS_S_i
	.section	.rodata,"a",@progbits
	.globl	_Z10vecadd_gpuiPfS_S_i
	.p2align	3, 0x0
_Z10vecadd_gpuiPfS_S_i:
	.quad	_Z25__device_stub__vecadd_gpuiPfS_S_i
	.size	_Z10vecadd_gpuiPfS_S_i, 8

	.type	.L.str.3,@object                # @.str.3
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str.3:
	.asciz	"n=%d\n"
	.size	.L.str.3, 6

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"Check results.."
	.size	.L.str.4, 16

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z10vecadd_gpuiPfS_S_i"
	.size	.L__unnamed_1, 23

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.type	.Lstr,@object                   # @str
	.section	.rodata.str1.1,"aMS",@progbits,1
.Lstr:
	.asciz	"OK!"
	.size	.Lstr, 4

	.type	.Lstr.1,@object                 # @str.1
.Lstr.1:
	.asciz	"Mismatch!"
	.size	.Lstr.1, 10

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub__vecadd_gpuiPfS_S_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z10vecadd_gpuiPfS_S_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z10vecadd_gpuiPfS_S_i  ; -- Begin function _Z10vecadd_gpuiPfS_S_i
	.globl	_Z10vecadd_gpuiPfS_S_i
	.p2align	8
	.type	_Z10vecadd_gpuiPfS_S_i,@function
_Z10vecadd_gpuiPfS_S_i:                 ; @_Z10vecadd_gpuiPfS_S_i
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x34
	s_load_b32 s3, s[0:1], 0x20
	s_load_b32 s4, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_mul_i32 s15, s15, s2
	s_mov_b32 s2, exec_lo
	v_add3_u32 v0, s15, s3, v0
	v_cmpx_gt_i32_e64 s4, v0
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b128 s[4:7], s[0:1], 0x8
	v_ashrrev_i32_e32 v1, 31, v0
	s_load_b64 s[0:1], s[0:1], 0x18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v2, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v0
	global_load_b32 v2, v[2:3], off
	global_load_b32 v3, v[4:5], off
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v2, v2, v3
	global_store_b32 v[0:1], v2, off
.LBB0_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10vecadd_gpuiPfS_S_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 296
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 6
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z10vecadd_gpuiPfS_S_i, .Lfunc_end0-_Z10vecadd_gpuiPfS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 192
; NumSgprs: 18
; NumVgprs: 6
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 6
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         44
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         52
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         54
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         56
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         58
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         60
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         62
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         104
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 296
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10vecadd_gpuiPfS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z10vecadd_gpuiPfS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     6
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
