#include <iostream>
#include <iomanip>
#include <cstdio>
using namespace std;

const int d = 8;
const int w = 4;

template <class T>
__global__  void runMaxtrix(T *d_m, T *d_mout, int d){
	__shared__ T b_mr[w][w];
	__shared__ T b_mc[w][w];
	int bdx = blockIdx.x;
	int bdy = blockIdx.y;
	int tdx = threadIdx.x;
	int tdy = threadIdx.y;
	int row = bdx * blockDim.x + tdx;
	int col = bdy * blockDim.y + tdy;
	int pos = row*d+col;
	//printf("(%d, %d) (%d, %d): (%d, %d) %d\n", bdx, bdy, tdx, tdy, row, col, d_m[pos]);
	T mval = 0;
	for (int bk = 0; bk < d/w; bk++){
		b_mr[tdx][tdy] = d_m[(bdx*w + tdx)*d + bk * w + tdy]; // (bdx*w+tdx, bk*w+tdy)
		b_mc[tdx][tdy] = d_m[(bdy*w + tdx)*d + bk * w + tdy];	// (bdy*w+tdx, bk*w+tdy)
//		printf("(%d, %d)\n", b_mr[tdx][tdy], b_mc[tdx][tdy]);
		__syncthreads();
		for (int tk = 0; tk < w; tk++){
			mval +=  b_mr[tdx][tk] * b_mc[tdy][tk];
			printf("(%d, %d), tval=->%d\n", row, col, mval);
		}
		__syncthreads();
	}
	d_mout[pos] = mval;
}

template <class T> void diplayMatrix(T *m, int d){
	cout << "m={" << endl;
	for (int i = 0; i < d; i++){
		cout << "\t{";
		for (int j = 0; j < d - 1; j++){
			cout << setw(5) << m[i*d+j] << ", ";
		}
		cout << setw(5) << m[i*d + d - 1] <<
				((i==d-1)? "}" : "},") << endl;
	}
	cout << "};" << endl;
}

int main(int argc, char *argv[]){
	int h_m[d*d];
	int h_mout[d*d];
	for (int i = 0; i < d; i++){
		for (int j = 0; j < d; j++){
			h_m[i*d + j] = i * 100 + j;
		}
	}
	diplayMatrix(h_m, d);
	int *d_m, *d_mout;
	cudaMalloc((void **)&d_m, d*d*sizeof(int));
	cudaMalloc((void **)&d_mout, d*d*sizeof(int));

	cudaMemcpy(d_m, h_m, d*d*sizeof(int), cudaMemcpyHostToDevice);
	runMaxtrix<<<dim3(2,2,1), dim3(4,4,1)>>>(d_m, d_mout, d);
	cudaDeviceSynchronize();
	cudaMemcpy(h_mout, d_mout, d*d*sizeof(int), cudaMemcpyDeviceToHost);
	diplayMatrix(h_mout, d);
	cudaFree(d_m);
	cudaFree(d_mout);
	return 0;
}

	.file	"tmpxft_00308f94_00000000-6_ma.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3921:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3921:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_ZL39__device_stub__Z10runMaxtrixIiEvPT_S1_iPiS_i, @function
_ZL39__device_stub__Z10runMaxtrixIiEvPT_S1_iPiS_i:
.LFB3943:
	.cfi_startproc
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z10runMaxtrixIiEvPT_S1_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L2:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3943:
	.size	_ZL39__device_stub__Z10runMaxtrixIiEvPT_S1_iPiS_i, .-_ZL39__device_stub__Z10runMaxtrixIiEvPT_S1_iPiS_i
	.section	.text._Z10runMaxtrixIiEvPT_S1_i,"axG",@progbits,_Z10runMaxtrixIiEvPT_S1_i,comdat
	.weak	_Z10runMaxtrixIiEvPT_S1_i
	.type	_Z10runMaxtrixIiEvPT_S1_i, @function
_Z10runMaxtrixIiEvPT_S1_i:
.LFB4261:
	.cfi_startproc
	endbr64
	jmp	_ZL39__device_stub__Z10runMaxtrixIiEvPT_S1_iPiS_i
	.cfi_endproc
.LFE4261:
	.size	_Z10runMaxtrixIiEvPT_S1_i, .-_Z10runMaxtrixIiEvPT_S1_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z10runMaxtrixIiEvPT_S1_i"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3946:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z10runMaxtrixIiEvPT_S1_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3946:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.rodata._Z12diplayMatrixIiEvPT_i.str1.1,"aMS",@progbits,1
.LC1:
	.string	"}"
.LC2:
	.string	"},"
.LC3:
	.string	"m={"
.LC4:
	.string	"\t{"
.LC5:
	.string	", "
.LC6:
	.string	"};"
	.section	.text._Z12diplayMatrixIiEvPT_i,"axG",@progbits,_Z12diplayMatrixIiEvPT_i,comdat
	.weak	_Z12diplayMatrixIiEvPT_i
	.type	_Z12diplayMatrixIiEvPT_i, @function
_Z12diplayMatrixIiEvPT_i:
.LFB4260:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	xorl	%r15d, %r15d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rdi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	xorl	%r12d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%esi, %ebp
	leaq	.LC3(%rip), %rsi
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	leaq	_ZSt4cout(%rip), %rbx
	movq	%rbx, %rdi
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movslq	%ebp, %rax
	salq	$2, %rax
	movq	%rax, 8(%rsp)
	leaq	0(%r13,%rax), %r14
.L11:
	cmpl	%r12d, %ebp
	jle	.L18
	leaq	.LC4(%rip), %rsi
	movq	%rbx, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movslq	%r15d, %rax
	xorl	%edx, %edx
	leaq	0(%r13,%rax,4), %r8
.L12:
	movq	(%rbx), %rax
	leal	-1(%rbp), %ecx
	movq	-24(%rax), %rsi
	addq	%rbx, %rsi
	movq	%rsi, %rax
	cmpl	%edx, %ecx
	jle	.L19
	movq	$5, 16(%rax)
	movl	(%r8,%rdx,4), %esi
	movq	%rbx, %rdi
	movq	%r8, 24(%rsp)
	movq	%rdx, 16(%rsp)
	call	_ZNSolsEi@PLT
	leaq	.LC5(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	16(%rsp), %rdx
	movq	24(%rsp), %r8
	incq	%rdx
	jmp	.L12
.L19:
	movq	$5, 16(%rsi)
	movl	-4(%r14), %esi
	movq	%rbx, %rdi
	movl	%ecx, 16(%rsp)
	call	_ZNSolsEi@PLT
	movl	16(%rsp), %ecx
	leaq	.LC2(%rip), %rsi
	movq	%rax, %rdi
	leaq	.LC1(%rip), %rax
	cmpl	%r12d, %ecx
	cmove	%rax, %rsi
	incl	%r12d
	addl	%ebp, %r15d
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	call	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	movq	8(%rsp), %rax
	addq	%rax, %r14
	jmp	.L11
.L18:
	movq	%rbx, %rdi
	leaq	.LC6(%rip), %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	movq	%rax, %rdi
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@PLT
	.cfi_endproc
.LFE4260:
	.size	_Z12diplayMatrixIiEvPT_i, .-_Z12diplayMatrixIiEvPT_i
	.section	.text.startup
	.globl	main
	.type	main, @function
main:
.LFB3918:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	xorl	%edx, %edx
	subq	$560, %rsp
	.cfi_def_cfa_offset 576
	movq	%fs:40, %rax
	movq	%rax, 552(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rcx
	movq	%rcx, %rbx
.L21:
	imull	$100, %edx, %esi
	xorl	%eax, %eax
.L22:
	leal	(%rsi,%rax), %edi
	movl	%edi, (%rcx,%rax,4)
	incq	%rax
	cmpq	$8, %rax
	jne	.L22
	incl	%edx
	addq	$32, %rcx
	cmpl	$8, %edx
	jne	.L21
	movl	$8, %esi
	movq	%rbx, %rdi
	call	_Z12diplayMatrixIiEvPT_i
	movq	%rsp, %rdi
	movl	$256, %esi
	call	cudaMalloc@PLT
	leaq	8(%rsp), %rdi
	movl	$256, %esi
	call	cudaMalloc@PLT
	movq	(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rsi
	movl	$256, %edx
	call	cudaMemcpy@PLT
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$1, %ecx
	movabsq	$17179869188, %rdx
	movl	$1, %esi
	movabsq	$8589934594, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L24
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdi
	movl	$8, %edx
	call	_ZL39__device_stub__Z10runMaxtrixIiEvPT_S1_iPiS_i
.L24:
	call	cudaDeviceSynchronize@PLT
	movq	8(%rsp), %rsi
	movl	$2, %ecx
	leaq	296(%rsp), %rbx
	movl	$256, %edx
	movq	%rbx, %rdi
	call	cudaMemcpy@PLT
	movl	$8, %esi
	movq	%rbx, %rdi
	call	_Z12diplayMatrixIiEvPT_i
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	552(%rsp), %rax
	subq	%fs:40, %rax
	je	.L25
	call	__stack_chk_fail@PLT
.L25:
	addq	$560, %rsp
	.cfi_def_cfa_offset 16
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3918:
	.size	main, .-main
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <iostream>
#include <iomanip>
#include <cstdio>
using namespace std;

const int d = 8;
const int w = 4;

template <class T>
__global__  void runMaxtrix(T *d_m, T *d_mout, int d){
	__shared__ T b_mr[w][w];
	__shared__ T b_mc[w][w];
	int bdx = blockIdx.x;
	int bdy = blockIdx.y;
	int tdx = threadIdx.x;
	int tdy = threadIdx.y;
	int row = bdx * blockDim.x + tdx;
	int col = bdy * blockDim.y + tdy;
	int pos = row*d+col;
	//printf("(%d, %d) (%d, %d): (%d, %d) %d\n", bdx, bdy, tdx, tdy, row, col, d_m[pos]);
	T mval = 0;
	for (int bk = 0; bk < d/w; bk++){
		b_mr[tdx][tdy] = d_m[(bdx*w + tdx)*d + bk * w + tdy]; // (bdx*w+tdx, bk*w+tdy)
		b_mc[tdx][tdy] = d_m[(bdy*w + tdx)*d + bk * w + tdy];	// (bdy*w+tdx, bk*w+tdy)
//		printf("(%d, %d)\n", b_mr[tdx][tdy], b_mc[tdx][tdy]);
		__syncthreads();
		for (int tk = 0; tk < w; tk++){
			mval +=  b_mr[tdx][tk] * b_mc[tdy][tk];
			printf("(%d, %d), tval=->%d\n", row, col, mval);
		}
		__syncthreads();
	}
	d_mout[pos] = mval;
}

template <class T> void diplayMatrix(T *m, int d){
	cout << "m={" << endl;
	for (int i = 0; i < d; i++){
		cout << "\t{";
		for (int j = 0; j < d - 1; j++){
			cout << setw(5) << m[i*d+j] << ", ";
		}
		cout << setw(5) << m[i*d + d - 1] <<
				((i==d-1)? "}" : "},") << endl;
	}
	cout << "};" << endl;
}

int main(int argc, char *argv[]){
	int h_m[d*d];
	int h_mout[d*d];
	for (int i = 0; i < d; i++){
		for (int j = 0; j < d; j++){
			h_m[i*d + j] = i * 100 + j;
		}
	}
	diplayMatrix(h_m, d);
	int *d_m, *d_mout;
	hipMalloc((void **)&d_m, d*d*sizeof(int));
	hipMalloc((void **)&d_mout, d*d*sizeof(int));

	hipMemcpy(d_m, h_m, d*d*sizeof(int), hipMemcpyHostToDevice);
	runMaxtrix<<<dim3(2,2,1), dim3(4,4,1)>>>(d_m, d_mout, d);
	hipDeviceSynchronize();
	hipMemcpy(h_mout, d_mout, d*d*sizeof(int), hipMemcpyDeviceToHost);
	diplayMatrix(h_mout, d);
	hipFree(d_m);
	hipFree(d_mout);
	return 0;
}

	.text
	.file	"ma.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	subq	$536, %rsp                      # imm = 0x218
	.cfi_def_cfa_offset 560
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	leaq	16(%rsp), %rax
	xorl	%ecx, %ecx
	xorl	%edx, %edx
.LBB0_1:                                # %.preheader
                                        # =>This Loop Header: Depth=1
                                        #     Child Loop BB0_2 Depth 2
	xorl	%esi, %esi
.LBB0_2:                                #   Parent Loop BB0_1 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	leal	(%rcx,%rsi), %edi
	movl	%edi, (%rax,%rsi,4)
	incq	%rsi
	cmpq	$8, %rsi
	jne	.LBB0_2
# %bb.3:                                #   in Loop: Header=BB0_1 Depth=1
	incq	%rdx
	addq	$100, %rcx
	addq	$32, %rax
	cmpq	$8, %rdx
	jne	.LBB0_1
# %bb.4:
	leaq	16(%rsp), %rbx
	movq	%rbx, %rdi
	movl	$8, %esi
	callq	_Z12diplayMatrixIiEvPT_i
	leaq	8(%rsp), %r14
	movl	$256, %esi                      # imm = 0x100
	movq	%r14, %rdi
	callq	hipMalloc
	movq	%rsp, %rdi
	movl	$256, %esi                      # imm = 0x100
	callq	hipMalloc
	movq	(%r14), %rdi
	movl	$256, %edx                      # imm = 0x100
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movabsq	$8589934594, %rdi               # imm = 0x200000002
	movabsq	$17179869188, %rdx              # imm = 0x400000004
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_6
# %bb.5:
	movq	8(%rsp), %rdi
	movq	(%rsp), %rsi
	movl	$8, %edx
	callq	_Z25__device_stub__runMaxtrixIiEvPT_S1_i
.LBB0_6:
	callq	hipDeviceSynchronize
	movq	(%rsp), %rsi
	leaq	272(%rsp), %rbx
	movl	$256, %edx                      # imm = 0x100
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movq	%rbx, %rdi
	movl	$8, %esi
	callq	_Z12diplayMatrixIiEvPT_i
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	xorl	%eax, %eax
	addq	$536, %rsp                      # imm = 0x218
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	main, .Lfunc_end0-main
	.cfi_endproc
                                        # -- End function
	.section	.text._Z12diplayMatrixIiEvPT_i,"axG",@progbits,_Z12diplayMatrixIiEvPT_i,comdat
	.weak	_Z12diplayMatrixIiEvPT_i        # -- Begin function _Z12diplayMatrixIiEvPT_i
	.type	_Z12diplayMatrixIiEvPT_i,@function
_Z12diplayMatrixIiEvPT_i:               # @_Z12diplayMatrixIiEvPT_i
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$24, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%esi, %ebx
	movq	%rdi, (%rsp)                    # 8-byte Spill
	movl	$_ZSt4cout, %r14d
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$3, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%r14, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	testl	%ebx, %ebx
	jle	.LBB1_6
# %bb.1:                                # %.lr.ph24
	leal	-1(%rbx), %r13d
	movl	%ebx, %eax
	movq	%rax, 16(%rsp)                  # 8-byte Spill
	leaq	(,%rax,4), %rax
	movq	%rax, 8(%rsp)                   # 8-byte Spill
	xorl	%r12d, %r12d
	movq	(%rsp), %r14                    # 8-byte Reload
.LBB1_2:                                # =>This Loop Header: Depth=1
                                        #     Child Loop BB1_4 Depth 2
	movl	$_ZSt4cout, %edi
	movl	$.L.str.1, %esi
	movl	$2, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	cmpl	$1, %ebx
	je	.LBB1_5
# %bb.3:                                # %.lr.ph
                                        #   in Loop: Header=BB1_2 Depth=1
	xorl	%r15d, %r15d
.LBB1_4:                                #   Parent Loop BB1_2 Depth=1
                                        # =>  This Inner Loop Header: Depth=2
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rax
	movq	$5, _ZSt4cout+16(%rax)
	movl	(%r14,%r15,4), %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSolsEi
	movl	$.L.str.2, %esi
	movl	$2, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	incq	%r15
	cmpq	%r15, %r13
	jne	.LBB1_4
.LBB1_5:                                # %._crit_edge
                                        #   in Loop: Header=BB1_2 Depth=1
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rax
	movq	$5, _ZSt4cout+16(%rax)
	leaq	1(%r12), %rbp
	movl	%ebp, %eax
	imull	%ebx, %eax
	cltq
	movq	(%rsp), %rcx                    # 8-byte Reload
	movl	-4(%rcx,%rax,4), %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSolsEi
	movq	%rax, %r15
	xorl	%edx, %edx
	cmpq	%r13, %r12
	movl	$.L.str.4, %esi
	movl	$.L.str.3, %eax
	cmoveq	%rax, %rsi
	setne	%dl
	incq	%rdx
	movq	%r15, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	(%r15), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r15, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	addq	8(%rsp), %r14                   # 8-byte Folded Reload
	movq	%rbp, %r12
	cmpq	16(%rsp), %rbp                  # 8-byte Folded Reload
	jne	.LBB1_2
.LBB1_6:                                # %._crit_edge25
	movl	$_ZSt4cout, %edi
	movl	$.L.str.5, %esi
	movl	$2, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	movl	$_ZSt4cout, %eax
	addq	%rax, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	addq	$24, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_ZNSo5flushEv                   # TAILCALL
.Lfunc_end1:
	.size	_Z12diplayMatrixIiEvPT_i, .Lfunc_end1-_Z12diplayMatrixIiEvPT_i
	.cfi_endproc
                                        # -- End function
	.section	.text._Z25__device_stub__runMaxtrixIiEvPT_S1_i,"axG",@progbits,_Z25__device_stub__runMaxtrixIiEvPT_S1_i,comdat
	.weak	_Z25__device_stub__runMaxtrixIiEvPT_S1_i # -- Begin function _Z25__device_stub__runMaxtrixIiEvPT_S1_i
	.type	_Z25__device_stub__runMaxtrixIiEvPT_S1_i,@function
_Z25__device_stub__runMaxtrixIiEvPT_S1_i: # @_Z25__device_stub__runMaxtrixIiEvPT_S1_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10runMaxtrixIiEvPT_S1_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z25__device_stub__runMaxtrixIiEvPT_S1_i, .Lfunc_end2-_Z25__device_stub__runMaxtrixIiEvPT_S1_i
	.cfi_endproc
                                        # -- End function
	.text
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB3_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB3_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10runMaxtrixIiEvPT_S1_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end3:
	.size	__hip_module_ctor, .Lfunc_end3-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB4_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB4_2:
	retq
.Lfunc_end4:
	.size	__hip_module_dtor, .Lfunc_end4-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z10runMaxtrixIiEvPT_S1_i,@object # @_Z10runMaxtrixIiEvPT_S1_i
	.section	.rodata._Z10runMaxtrixIiEvPT_S1_i,"aG",@progbits,_Z10runMaxtrixIiEvPT_S1_i,comdat
	.weak	_Z10runMaxtrixIiEvPT_S1_i
	.p2align	3, 0x0
_Z10runMaxtrixIiEvPT_S1_i:
	.quad	_Z25__device_stub__runMaxtrixIiEvPT_S1_i
	.size	_Z10runMaxtrixIiEvPT_S1_i, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"m={"
	.size	.L.str, 4

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"\t{"
	.size	.L.str.1, 3

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	", "
	.size	.L.str.2, 3

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"}"
	.size	.L.str.3, 2

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"},"
	.size	.L.str.4, 3

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"};"
	.size	.L.str.5, 3

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z10runMaxtrixIiEvPT_S1_i"
	.size	.L__unnamed_1, 26

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub__runMaxtrixIiEvPT_S1_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z10runMaxtrixIiEvPT_S1_i
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.section	.text._Z10runMaxtrixIiEvPT_S1_i,"axG",@progbits,_Z10runMaxtrixIiEvPT_S1_i,comdat
	.protected	_Z10runMaxtrixIiEvPT_S1_i ; -- Begin function _Z10runMaxtrixIiEvPT_S1_i
	.globl	_Z10runMaxtrixIiEvPT_S1_i
	.p2align	8
	.type	_Z10runMaxtrixIiEvPT_S1_i,@function
_Z10runMaxtrixIiEvPT_S1_i:              ; @_Z10runMaxtrixIiEvPT_S1_i
; %bb.0:
	s_clause 0x2
	s_load_b32 s2, s[0:1], 0x24
	s_load_b32 s20, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	v_and_b32_e32 v35, 0x3ff, v0
	v_bfe_u32 v36, v0, 10, 10
	s_add_u32 s0, s0, 24
	s_addc_u32 s1, s1, 0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	v_mad_u64_u32 v[2:3], null, s15, s3, v[36:37]
	v_mad_u64_u32 v[33:34], null, s14, s2, v[35:36]
	v_mov_b32_e32 v34, 0
	s_cmp_lt_i32 s20, 4
	s_cbranch_scc1 .LBB0_230
; %bb.1:                                ; %.lr.ph
	s_load_b64 s[2:3], s[0:1], 0x50
	v_lshl_add_u32 v3, s15, 2, v35
	v_mov_b32_e32 v6, 0
	v_lshlrev_b32_e32 v0, 2, v36
	v_lshl_add_u32 v1, s14, 2, v35
	s_ashr_i32 s8, s20, 31
	v_mul_lo_u32 v40, v3, s20
	v_mov_b32_e32 v3, v6
	v_lshl_add_u32 v37, v35, 4, v0
	v_mul_lo_u32 v38, v1, s20
	s_lshr_b32 s0, s8, 30
	v_mbcnt_lo_u32_b32 v41, -1, 0
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_mov_b32 v4, 33 :: v_dual_add_nc_u32 v39, 64, v37
	v_dual_mov_b32 v42, v6 :: v_dual_mov_b32 v9, 2
	v_mov_b32_e32 v10, 1
	v_mov_b32_e32 v34, v6
	s_add_i32 s0, s20, s0
	s_mov_b32 s8, 0
	s_ashr_i32 s21, s0, 2
	s_mov_b32 s22, 0
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_3 Depth 2
                                        ;       Child Loop BB0_6 Depth 3
                                        ;       Child Loop BB0_14 Depth 3
                                        ;       Child Loop BB0_20 Depth 3
                                        ;       Child Loop BB0_29 Depth 3
                                        ;       Child Loop BB0_32 Depth 3
                                        ;         Child Loop BB0_35 Depth 4
                                        ;         Child Loop BB0_43 Depth 4
                                        ;         Child Loop BB0_51 Depth 4
                                        ;         Child Loop BB0_59 Depth 4
                                        ;         Child Loop BB0_67 Depth 4
                                        ;         Child Loop BB0_75 Depth 4
                                        ;         Child Loop BB0_83 Depth 4
                                        ;         Child Loop BB0_91 Depth 4
                                        ;         Child Loop BB0_99 Depth 4
                                        ;         Child Loop BB0_105 Depth 4
                                        ;         Child Loop BB0_114 Depth 4
                                        ;       Child Loop BB0_122 Depth 3
                                        ;       Child Loop BB0_130 Depth 3
                                        ;       Child Loop BB0_136 Depth 3
                                        ;       Child Loop BB0_145 Depth 3
                                        ;       Child Loop BB0_150 Depth 3
                                        ;       Child Loop BB0_158 Depth 3
                                        ;       Child Loop BB0_164 Depth 3
                                        ;       Child Loop BB0_173 Depth 3
                                        ;       Child Loop BB0_177 Depth 3
                                        ;       Child Loop BB0_185 Depth 3
                                        ;       Child Loop BB0_191 Depth 3
                                        ;       Child Loop BB0_200 Depth 3
                                        ;       Child Loop BB0_204 Depth 3
                                        ;       Child Loop BB0_212 Depth 3
                                        ;       Child Loop BB0_218 Depth 3
                                        ;       Child Loop BB0_227 Depth 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshl_add_u32 v1, s22, 2, v36
	s_mov_b32 s23, 0
	v_add_nc_u32_e32 v0, v1, v38
	v_add_nc_u32_e32 v7, v1, v40
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v1, 31, v0
	v_ashrrev_i32_e32 v8, 31, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v7, vcc_lo, s4, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s5, v8, vcc_lo
	s_clause 0x1
	global_load_b32 v0, v[0:1], off
	global_load_b32 v1, v[7:8], off
	s_waitcnt vmcnt(1)
	ds_store_b32 v39, v0
	s_waitcnt vmcnt(0)
	ds_store_b32 v37, v1
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB0_3:                                ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_6 Depth 3
                                        ;       Child Loop BB0_14 Depth 3
                                        ;       Child Loop BB0_20 Depth 3
                                        ;       Child Loop BB0_29 Depth 3
                                        ;       Child Loop BB0_32 Depth 3
                                        ;         Child Loop BB0_35 Depth 4
                                        ;         Child Loop BB0_43 Depth 4
                                        ;         Child Loop BB0_51 Depth 4
                                        ;         Child Loop BB0_59 Depth 4
                                        ;         Child Loop BB0_67 Depth 4
                                        ;         Child Loop BB0_75 Depth 4
                                        ;         Child Loop BB0_83 Depth 4
                                        ;         Child Loop BB0_91 Depth 4
                                        ;         Child Loop BB0_99 Depth 4
                                        ;         Child Loop BB0_105 Depth 4
                                        ;         Child Loop BB0_114 Depth 4
                                        ;       Child Loop BB0_122 Depth 3
                                        ;       Child Loop BB0_130 Depth 3
                                        ;       Child Loop BB0_136 Depth 3
                                        ;       Child Loop BB0_145 Depth 3
                                        ;       Child Loop BB0_150 Depth 3
                                        ;       Child Loop BB0_158 Depth 3
                                        ;       Child Loop BB0_164 Depth 3
                                        ;       Child Loop BB0_173 Depth 3
                                        ;       Child Loop BB0_177 Depth 3
                                        ;       Child Loop BB0_185 Depth 3
                                        ;       Child Loop BB0_191 Depth 3
                                        ;       Child Loop BB0_200 Depth 3
                                        ;       Child Loop BB0_204 Depth 3
                                        ;       Child Loop BB0_212 Depth 3
                                        ;       Child Loop BB0_218 Depth 3
                                        ;       Child Loop BB0_227 Depth 3
	s_lshl_b32 s0, s23, 2
	v_mov_b32_e32 v5, v41
	v_lshl_add_u32 v0, v35, 4, s0
	v_lshl_add_u32 v1, v36, 4, s0
	ds_load_b32 v43, v0 offset:64
	ds_load_b32 v44, v1
	v_mov_b32_e32 v0, 0
	;;#ASMSTART
	;;#ASMEND
	v_readfirstlane_b32 s0, v5
	v_mov_b32_e32 v1, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_eq_u32_e64 s0, s0, v5
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_9
; %bb.4:                                ;   in Loop: Header=BB0_3 Depth=2
	global_load_b64 v[13:14], v6, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v6, s[2:3] offset:40
	global_load_b64 v[7:8], v6, s[2:3]
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v14
	v_and_b32_e32 v0, v0, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v11, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v11, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v7, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v8, v1, vcc_lo
	global_load_b64 v[11:12], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v6, v[11:14], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[0:1], v[13:14]
	s_cbranch_execz .LBB0_8
; %bb.5:                                ; %.preheader3.i.i.i.preheader
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_mov_b32 s10, 0
.LBB0_6:                                ; %.preheader3.i.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_3 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[7:8], v6, s[2:3] offset:40
	global_load_b64 v[11:12], v6, s[2:3]
	v_dual_mov_b32 v14, v1 :: v_dual_mov_b32 v13, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v7, v13
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[0:1], null, v7, 24, v[11:12]
	v_and_b32_e32 v11, v8, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v11, 24, v[1:2]
	v_mov_b32_e32 v1, v7
	global_load_b64 v[11:12], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v6, v[11:14], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[13:14]
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_6
; %bb.7:                                ; %Flow521
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_8:                                ; %Flow523
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
.LBB0_9:                                ; %.loopexit4.i.i.i
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[7:8], v6, s[2:3] offset:40
	global_load_b128 v[11:14], v6, s[2:3]
	v_readfirstlane_b32 s12, v0
	v_readfirstlane_b32 s13, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v7
	v_readfirstlane_b32 s11, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[12:13], s[10:11]
	s_mul_i32 s1, s11, 24
	s_mul_hi_u32 s14, s10, 24
	s_mul_i32 s15, s10, 24
	s_and_saveexec_b32 s16, s0
	s_cbranch_execz .LBB0_11
; %bb.10:                               ;   in Loop: Header=BB0_3 Depth=2
	v_dual_mov_b32 v7, s9 :: v_dual_mov_b32 v8, v6
	s_add_i32 s9, s14, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v11, s15
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v12, vcc_lo
	global_store_b128 v[0:1], v[7:10], off offset:8
.LBB0_11:                               ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s16
	s_lshl_b64 s[10:11], s[10:11], 12
	v_lshlrev_b64 v[0:1], 6, v[5:6]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v13, s10
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v14, vcc_lo
	s_mov_b32 s11, s8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v5, v0
	s_mov_b32 s9, s8
	s_mov_b32 s10, s8
	v_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo
	v_dual_mov_b32 v5, v6 :: v_dual_mov_b32 v16, s11
	v_dual_mov_b32 v7, v6 :: v_dual_mov_b32 v14, s9
	v_mov_b32_e32 v15, s10
	v_mov_b32_e32 v13, s8
	s_clause 0x3
	global_store_b128 v[0:1], v[4:7], off
	global_store_b128 v[0:1], v[13:16], off offset:16
	global_store_b128 v[0:1], v[13:16], off offset:32
	global_store_b128 v[0:1], v[13:16], off offset:48
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB0_19
; %bb.12:                               ;   in Loop: Header=BB0_3 Depth=2
	s_clause 0x1
	global_load_b64 v[17:18], v6, s[2:3] offset:32 glc
	global_load_b64 v[7:8], v6, s[2:3] offset:40
	v_dual_mov_b32 v15, s12 :: v_dual_mov_b32 v16, s13
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v7
	v_readfirstlane_b32 s11, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[12:13]
	s_mul_i32 s11, s11, 24
	s_mul_hi_u32 s16, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s16, s16, s11
	v_add_co_u32 v7, vcc_lo, v11, s10
	v_add_co_ci_u32_e32 v8, vcc_lo, s16, v12, vcc_lo
	s_mov_b32 s10, exec_lo
	global_store_b64 v[7:8], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v6, v[15:18], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[15:16], v[17:18]
	s_cbranch_execz .LBB0_15
; %bb.13:                               ; %.preheader1.i.i.i.preheader
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_mov_b32 s11, 0
.LBB0_14:                               ; %.preheader1.i.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_3 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_dual_mov_b32 v13, s12 :: v_dual_mov_b32 v14, s13
	s_sleep 1
	global_store_b64 v[7:8], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v6, v[13:16], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[13:14], v[15:16]
	v_dual_mov_b32 v16, v14 :: v_dual_mov_b32 v15, v13
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_14
.LBB0_15:                               ; %Flow519
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
	global_load_b64 v[7:8], v6, s[2:3] offset:16
	s_mov_b32 s11, exec_lo
	s_mov_b32 s10, exec_lo
	v_mbcnt_lo_u32_b32 v5, s11, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v5
	s_cbranch_execz .LBB0_17
; %bb.16:                               ;   in Loop: Header=BB0_3 Depth=2
	s_bcnt1_i32_b32 s11, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v5, s11
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[7:8], v[5:6], off offset:8
.LBB0_17:                               ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
	s_waitcnt vmcnt(0)
	global_load_b64 v[13:14], v[7:8], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[13:14]
	s_cbranch_vccnz .LBB0_19
; %bb.18:                               ;   in Loop: Header=BB0_3 Depth=2
	global_load_b32 v5, v[7:8], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v5
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[13:14], v[5:6], off
	s_and_b32 m0, s10, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_19:                               ; %Flow520
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s9
	s_add_i32 s14, s14, s1
	v_add_co_u32 v5, vcc_lo, v11, s15
	v_add_co_ci_u32_e32 v8, vcc_lo, s14, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v5, 20
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
.LBB0_20:                               ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_3 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v5, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_22
; %bb.21:                               ;   in Loop: Header=BB0_20 Depth=3
	global_load_b32 v5, v[7:8], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v5, 1, v5
.LBB0_22:                               ;   in Loop: Header=BB0_20 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v5
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_24
; %bb.23:                               ;   in Loop: Header=BB0_20 Depth=3
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_25
.LBB0_24:                               ;   in Loop: Header=BB0_20 Depth=3
	s_mov_b32 s1, -1
.LBB0_25:                               ; %Flow514
                                        ;   in Loop: Header=BB0_20 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_20
; %bb.26:                               ;   in Loop: Header=BB0_3 Depth=2
	global_load_b64 v[11:12], v[0:1], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_30
; %bb.27:                               ;   in Loop: Header=BB0_3 Depth=2
	s_clause 0x2
	global_load_b64 v[0:1], v6, s[2:3] offset:40
	global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
	global_load_b64 v[15:16], v6, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v5, vcc_lo, v0, 1
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v13, vcc_lo, v5, s12
	v_add_co_ci_u32_e32 v14, vcc_lo, s13, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[13:14]
	v_cndmask_b32_e32 v13, v13, v5, vcc_lo
	v_cndmask_b32_e32 v14, v14, v17, vcc_lo
	v_and_b32_e32 v0, v13, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v5, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v15, v0
	v_mov_b32_e32 v15, v7
	v_and_b32_e32 v1, v14, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v1, v1, 24
	v_add_nc_u32_e32 v1, v5, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v1, vcc_lo, v16, v1, vcc_lo
	v_mov_b32_e32 v16, v8
	global_store_b64 v[0:1], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v6, v[13:16], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[15:16], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_30
; %bb.28:                               ; %.preheader.i.i.i.preheader
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_mov_b32 s0, 0
.LBB0_29:                               ; %.preheader.i.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_3 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	global_store_b64 v[0:1], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v6, v[13:16], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[15:16]
	v_dual_mov_b32 v16, v8 :: v_dual_mov_b32 v15, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_29
.LBB0_30:                               ; %__ockl_printf_begin.exit
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_getpc_b64 s[10:11]
	s_add_u32 s10, s10, .str@rel32@lo+4
	s_addc_u32 s11, s11, .str@rel32@hi+12
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u64 s[10:11], 0
	s_cbranch_scc0 .LBB0_117
; %bb.31:                               ;   in Loop: Header=BB0_3 Depth=2
	s_waitcnt vmcnt(0)
	v_dual_mov_b32 v14, v12 :: v_dual_and_b32 v45, 2, v11
	v_and_b32_e32 v13, -3, v11
	s_mov_b64 s[12:13], 21
.LBB0_32:                               ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_3 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_35 Depth 4
                                        ;         Child Loop BB0_43 Depth 4
                                        ;         Child Loop BB0_51 Depth 4
                                        ;         Child Loop BB0_59 Depth 4
                                        ;         Child Loop BB0_67 Depth 4
                                        ;         Child Loop BB0_75 Depth 4
                                        ;         Child Loop BB0_83 Depth 4
                                        ;         Child Loop BB0_91 Depth 4
                                        ;         Child Loop BB0_99 Depth 4
                                        ;         Child Loop BB0_105 Depth 4
                                        ;         Child Loop BB0_114 Depth 4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u64_e64 s0, s[12:13], 56
	s_and_b32 s0, s0, exec_lo
	s_cselect_b32 s14, s12, 56
	s_cselect_b32 s15, s13, 0
	s_cmp_gt_u32 s14, 7
	s_cbranch_scc1 .LBB0_37
; %bb.33:                               ;   in Loop: Header=BB0_32 Depth=3
	s_waitcnt vmcnt(0)
	v_mov_b32_e32 v15, 0
	v_mov_b32_e32 v16, 0
	s_cmp_eq_u32 s14, 0
	s_cbranch_scc1 .LBB0_36
; %bb.34:                               ; %.preheader31.i.preheader
                                        ;   in Loop: Header=BB0_32 Depth=3
	s_lshl_b64 s[0:1], s[14:15], 3
	s_mov_b64 s[16:17], 0
	s_mov_b64 s[18:19], s[10:11]
.LBB0_35:                               ; %.preheader31.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_3 Depth=2
                                        ;       Parent Loop BB0_32 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	global_load_u8 v0, v6, s[18:19]
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v5, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], s16, v[5:6]
	s_add_u32 s16, s16, 8
	s_addc_u32 s17, s17, 0
	s_add_u32 s18, s18, 1
	s_addc_u32 s19, s19, 0
	s_cmp_lg_u32 s0, s16
	v_or_b32_e32 v15, v0, v15
	v_or_b32_e32 v16, v1, v16
	s_cbranch_scc1 .LBB0_35
.LBB0_36:                               ; %Flow490
                                        ;   in Loop: Header=BB0_32 Depth=3
	s_mov_b32 s0, 0
	s_mov_b32 s9, 0
	s_branch .LBB0_38
.LBB0_37:                               ;   in Loop: Header=BB0_32 Depth=3
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr15_vgpr16
                                        ; implicit-def: $sgpr9
.LBB0_38:                               ; %Flow492
                                        ;   in Loop: Header=BB0_32 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_mov_b64 s[0:1], s[10:11]
	s_cbranch_vccnz .LBB0_40
; %bb.39:                               ;   in Loop: Header=BB0_32 Depth=3
	global_load_b64 v[15:16], v6, s[10:11]
	s_add_i32 s9, s14, -8
	s_add_u32 s0, s10, 8
	s_addc_u32 s1, s11, 0
.LBB0_40:                               ; %.loopexit32.i
                                        ;   in Loop: Header=BB0_32 Depth=3
	s_cmp_gt_u32 s9, 7
	s_cbranch_scc1 .LBB0_45
; %bb.41:                               ;   in Loop: Header=BB0_32 Depth=3
	v_mov_b32_e32 v17, 0
	v_mov_b32_e32 v18, 0
	s_cmp_eq_u32 s9, 0
	s_cbranch_scc1 .LBB0_44
; %bb.42:                               ; %.preheader29.i.preheader
                                        ;   in Loop: Header=BB0_32 Depth=3
	s_mov_b64 s[16:17], 0
	s_mov_b64 s[18:19], 0
.LBB0_43:                               ; %.preheader29.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_3 Depth=2
                                        ;       Parent Loop BB0_32 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s24, s0, s18
	s_addc_u32 s25, s1, s19
	s_add_u32 s18, s18, 1
	global_load_u8 v0, v6, s[24:25]
	s_addc_u32 s19, s19, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v5, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], s16, v[5:6]
	s_add_u32 s16, s16, 8
	s_addc_u32 s17, s17, 0
	s_cmp_lg_u32 s9, s18
	v_or_b32_e32 v17, v0, v17
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v18, v1, v18
	s_cbranch_scc1 .LBB0_43
.LBB0_44:                               ; %Flow485
                                        ;   in Loop: Header=BB0_32 Depth=3
	s_mov_b32 s16, 0
	s_mov_b32 s24, 0
	s_branch .LBB0_46
.LBB0_45:                               ;   in Loop: Header=BB0_32 Depth=3
	s_mov_b32 s16, -1
                                        ; implicit-def: $vgpr17_vgpr18
                                        ; implicit-def: $sgpr24
.LBB0_46:                               ; %Flow487
                                        ;   in Loop: Header=BB0_32 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB0_48
; %bb.47:                               ;   in Loop: Header=BB0_32 Depth=3
	global_load_b64 v[17:18], v6, s[0:1]
	s_add_i32 s24, s9, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_48:                               ; %.loopexit30.i
                                        ;   in Loop: Header=BB0_32 Depth=3
	s_cmp_gt_u32 s24, 7
	s_cbranch_scc1 .LBB0_53
; %bb.49:                               ;   in Loop: Header=BB0_32 Depth=3
	v_mov_b32_e32 v19, 0
	v_mov_b32_e32 v20, 0
	s_cmp_eq_u32 s24, 0
	s_cbranch_scc1 .LBB0_52
; %bb.50:                               ; %.preheader27.i.preheader
                                        ;   in Loop: Header=BB0_32 Depth=3
	s_mov_b64 s[16:17], 0
	s_mov_b64 s[18:19], 0
.LBB0_51:                               ; %.preheader27.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_3 Depth=2
                                        ;       Parent Loop BB0_32 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s26, s0, s18
	s_addc_u32 s27, s1, s19
	s_add_u32 s18, s18, 1
	global_load_u8 v0, v6, s[26:27]
	s_addc_u32 s19, s19, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v5, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], s16, v[5:6]
	s_add_u32 s16, s16, 8
	s_addc_u32 s17, s17, 0
	s_cmp_lg_u32 s24, s18
	v_or_b32_e32 v19, v0, v19
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v20, v1, v20
	s_cbranch_scc1 .LBB0_51
.LBB0_52:                               ; %Flow480
                                        ;   in Loop: Header=BB0_32 Depth=3
	s_mov_b32 s16, 0
	s_mov_b32 s9, 0
	s_branch .LBB0_54
.LBB0_53:                               ;   in Loop: Header=BB0_32 Depth=3
	s_mov_b32 s16, -1
                                        ; implicit-def: $sgpr9
.LBB0_54:                               ; %Flow482
                                        ;   in Loop: Header=BB0_32 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB0_56
; %bb.55:                               ;   in Loop: Header=BB0_32 Depth=3
	global_load_b64 v[19:20], v6, s[0:1]
	s_add_i32 s9, s24, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_56:                               ; %.loopexit28.i
                                        ;   in Loop: Header=BB0_32 Depth=3
	s_cmp_gt_u32 s9, 7
	s_cbranch_scc1 .LBB0_61
; %bb.57:                               ;   in Loop: Header=BB0_32 Depth=3
	v_mov_b32_e32 v21, 0
	v_mov_b32_e32 v22, 0
	s_cmp_eq_u32 s9, 0
	s_cbranch_scc1 .LBB0_60
; %bb.58:                               ; %.preheader25.i.preheader
                                        ;   in Loop: Header=BB0_32 Depth=3
	s_mov_b64 s[16:17], 0
	s_mov_b64 s[18:19], 0
.LBB0_59:                               ; %.preheader25.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_3 Depth=2
                                        ;       Parent Loop BB0_32 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s24, s0, s18
	s_addc_u32 s25, s1, s19
	s_add_u32 s18, s18, 1
	global_load_u8 v0, v6, s[24:25]
	s_addc_u32 s19, s19, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v5, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], s16, v[5:6]
	s_add_u32 s16, s16, 8
	s_addc_u32 s17, s17, 0
	s_cmp_lg_u32 s9, s18
	v_or_b32_e32 v21, v0, v21
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v22, v1, v22
	s_cbranch_scc1 .LBB0_59
.LBB0_60:                               ; %Flow475
                                        ;   in Loop: Header=BB0_32 Depth=3
	s_mov_b32 s16, 0
	s_mov_b32 s24, 0
	s_branch .LBB0_62
.LBB0_61:                               ;   in Loop: Header=BB0_32 Depth=3
	s_mov_b32 s16, -1
                                        ; implicit-def: $vgpr21_vgpr22
                                        ; implicit-def: $sgpr24
.LBB0_62:                               ; %Flow477
                                        ;   in Loop: Header=BB0_32 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB0_64
; %bb.63:                               ;   in Loop: Header=BB0_32 Depth=3
	global_load_b64 v[21:22], v6, s[0:1]
	s_add_i32 s24, s9, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_64:                               ; %.loopexit26.i
                                        ;   in Loop: Header=BB0_32 Depth=3
	s_cmp_gt_u32 s24, 7
	s_cbranch_scc1 .LBB0_69
; %bb.65:                               ;   in Loop: Header=BB0_32 Depth=3
	v_mov_b32_e32 v23, 0
	v_mov_b32_e32 v24, 0
	s_cmp_eq_u32 s24, 0
	s_cbranch_scc1 .LBB0_68
; %bb.66:                               ; %.preheader23.i.preheader
                                        ;   in Loop: Header=BB0_32 Depth=3
	s_mov_b64 s[16:17], 0
	s_mov_b64 s[18:19], 0
.LBB0_67:                               ; %.preheader23.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_3 Depth=2
                                        ;       Parent Loop BB0_32 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s26, s0, s18
	s_addc_u32 s27, s1, s19
	s_add_u32 s18, s18, 1
	global_load_u8 v0, v6, s[26:27]
	s_addc_u32 s19, s19, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v5, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], s16, v[5:6]
	s_add_u32 s16, s16, 8
	s_addc_u32 s17, s17, 0
	s_cmp_lg_u32 s24, s18
	v_or_b32_e32 v23, v0, v23
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v24, v1, v24
	s_cbranch_scc1 .LBB0_67
.LBB0_68:                               ; %Flow470
                                        ;   in Loop: Header=BB0_32 Depth=3
	s_mov_b32 s16, 0
	s_mov_b32 s9, 0
	s_branch .LBB0_70
.LBB0_69:                               ;   in Loop: Header=BB0_32 Depth=3
	s_mov_b32 s16, -1
                                        ; implicit-def: $sgpr9
.LBB0_70:                               ; %Flow472
                                        ;   in Loop: Header=BB0_32 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB0_72
; %bb.71:                               ;   in Loop: Header=BB0_32 Depth=3
	global_load_b64 v[23:24], v6, s[0:1]
	s_add_i32 s9, s24, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_72:                               ; %.loopexit24.i
                                        ;   in Loop: Header=BB0_32 Depth=3
	s_cmp_gt_u32 s9, 7
	s_cbranch_scc1 .LBB0_77
; %bb.73:                               ;   in Loop: Header=BB0_32 Depth=3
	v_mov_b32_e32 v25, 0
	v_mov_b32_e32 v26, 0
	s_cmp_eq_u32 s9, 0
	s_cbranch_scc1 .LBB0_76
; %bb.74:                               ; %.preheader21.i.preheader
                                        ;   in Loop: Header=BB0_32 Depth=3
	s_mov_b64 s[16:17], 0
	s_mov_b64 s[18:19], 0
.LBB0_75:                               ; %.preheader21.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_3 Depth=2
                                        ;       Parent Loop BB0_32 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s24, s0, s18
	s_addc_u32 s25, s1, s19
	s_add_u32 s18, s18, 1
	global_load_u8 v0, v6, s[24:25]
	s_addc_u32 s19, s19, 0
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v5, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], s16, v[5:6]
	s_add_u32 s16, s16, 8
	s_addc_u32 s17, s17, 0
	s_cmp_lg_u32 s9, s18
	v_or_b32_e32 v25, v0, v25
	s_delay_alu instid0(VALU_DEP_2)
	v_or_b32_e32 v26, v1, v26
	s_cbranch_scc1 .LBB0_75
.LBB0_76:                               ; %Flow465
                                        ;   in Loop: Header=BB0_32 Depth=3
	s_mov_b32 s16, 0
	s_mov_b32 s24, 0
	s_branch .LBB0_78
.LBB0_77:                               ;   in Loop: Header=BB0_32 Depth=3
	s_mov_b32 s16, -1
                                        ; implicit-def: $vgpr25_vgpr26
                                        ; implicit-def: $sgpr24
.LBB0_78:                               ; %Flow467
                                        ;   in Loop: Header=BB0_32 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s16
	s_cbranch_vccnz .LBB0_80
; %bb.79:                               ;   in Loop: Header=BB0_32 Depth=3
	global_load_b64 v[25:26], v6, s[0:1]
	s_add_i32 s24, s9, -8
	s_add_u32 s0, s0, 8
	s_addc_u32 s1, s1, 0
.LBB0_80:                               ; %.loopexit22.i
                                        ;   in Loop: Header=BB0_32 Depth=3
	s_cmp_gt_u32 s24, 7
	s_cbranch_scc1 .LBB0_85
; %bb.81:                               ;   in Loop: Header=BB0_32 Depth=3
	v_mov_b32_e32 v27, 0
	v_mov_b32_e32 v28, 0
	s_cmp_eq_u32 s24, 0
	s_cbranch_scc1 .LBB0_84
; %bb.82:                               ; %.preheader.i.preheader
                                        ;   in Loop: Header=BB0_32 Depth=3
	s_mov_b64 s[16:17], 0
	s_mov_b64 s[18:19], s[0:1]
.LBB0_83:                               ; %.preheader.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_3 Depth=2
                                        ;       Parent Loop BB0_32 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	global_load_u8 v0, v6, s[18:19]
	s_add_i32 s24, s24, -1
	s_waitcnt vmcnt(0)
	v_and_b32_e32 v5, 0xffff, v0
	s_delay_alu instid0(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], s16, v[5:6]
	s_add_u32 s16, s16, 8
	s_addc_u32 s17, s17, 0
	s_add_u32 s18, s18, 1
	s_addc_u32 s19, s19, 0
	s_cmp_lg_u32 s24, 0
	v_or_b32_e32 v27, v0, v27
	v_or_b32_e32 v28, v1, v28
	s_cbranch_scc1 .LBB0_83
.LBB0_84:                               ; %Flow460
                                        ;   in Loop: Header=BB0_32 Depth=3
	s_mov_b32 s9, 0
	s_branch .LBB0_86
.LBB0_85:                               ;   in Loop: Header=BB0_32 Depth=3
	s_mov_b32 s9, -1
.LBB0_86:                               ; %Flow462
                                        ;   in Loop: Header=BB0_32 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s9
	s_cbranch_vccnz .LBB0_88
; %bb.87:                               ;   in Loop: Header=BB0_32 Depth=3
	global_load_b64 v[27:28], v6, s[0:1]
.LBB0_88:                               ; %.loopexit.i
                                        ;   in Loop: Header=BB0_32 Depth=3
	v_dual_mov_b32 v5, v41 :: v_dual_mov_b32 v0, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v5
	v_mov_b32_e32 v1, 0
	v_cmp_eq_u32_e64 s0, s0, v5
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_94
; %bb.89:                               ;   in Loop: Header=BB0_32 Depth=3
	global_load_b64 v[31:32], v6, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v6, s[2:3] offset:40
	global_load_b64 v[7:8], v6, s[2:3]
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v32
	v_and_b32_e32 v0, v0, v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v29, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v29, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v7, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v8, v1, vcc_lo
	global_load_b64 v[29:30], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v6, v[29:32], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[0:1], v[31:32]
	s_cbranch_execz .LBB0_93
; %bb.90:                               ; %.preheader3.i.i19.i.preheader
                                        ;   in Loop: Header=BB0_32 Depth=3
	s_mov_b32 s16, 0
.LBB0_91:                               ; %.preheader3.i.i19.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_3 Depth=2
                                        ;       Parent Loop BB0_32 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[7:8], v6, s[2:3] offset:40
	global_load_b64 v[29:30], v6, s[2:3]
	v_dual_mov_b32 v32, v1 :: v_dual_mov_b32 v31, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v7, v31
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[0:1], null, v7, 24, v[29:30]
	v_and_b32_e32 v29, v8, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v29, 24, v[1:2]
	v_mov_b32_e32 v1, v7
	global_load_b64 v[29:30], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v6, v[29:32], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[31:32]
	s_or_b32 s16, vcc_lo, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s16
	s_cbranch_execnz .LBB0_91
; %bb.92:                               ; %Flow455
                                        ;   in Loop: Header=BB0_32 Depth=3
	s_or_b32 exec_lo, exec_lo, s16
.LBB0_93:                               ; %Flow457
                                        ;   in Loop: Header=BB0_32 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
.LBB0_94:                               ; %.loopexit4.i.i14.i
                                        ;   in Loop: Header=BB0_32 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[7:8], v6, s[2:3] offset:40
	global_load_b128 v[29:32], v6, s[2:3]
	v_readfirstlane_b32 s16, v0
	v_readfirstlane_b32 s17, v1
	s_mov_b32 s25, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s18, v7
	v_readfirstlane_b32 s19, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[18:19], s[16:17], s[18:19]
	s_mul_i32 s1, s19, 24
	s_mul_hi_u32 s9, s18, 24
	s_mul_i32 s24, s18, 24
	s_and_saveexec_b32 s26, s0
	s_cbranch_execz .LBB0_96
; %bb.95:                               ;   in Loop: Header=BB0_32 Depth=3
	v_dual_mov_b32 v7, s25 :: v_dual_mov_b32 v8, v6
	s_add_i32 s25, s9, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v29, s24
	v_add_co_ci_u32_e32 v1, vcc_lo, s25, v30, vcc_lo
	global_store_b128 v[0:1], v[7:10], off offset:8
.LBB0_96:                               ;   in Loop: Header=BB0_32 Depth=3
	s_or_b32 exec_lo, exec_lo, s26
	v_cmp_gt_u64_e64 vcc_lo, s[12:13], 56
	v_or_b32_e32 v0, 0, v14
	v_or_b32_e32 v1, v13, v45
	s_lshl_b64 s[18:19], s[18:19], 12
	s_lshl_b32 s25, s14, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s25, s25, 28
	v_dual_cndmask_b32 v14, v0, v14 :: v_dual_cndmask_b32 v7, v1, v13
	v_lshlrev_b64 v[0:1], 6, v[5:6]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v31, s18
	v_add_co_ci_u32_e32 v8, vcc_lo, s19, v32, vcc_lo
	s_and_b32 s25, s25, 0x1e0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v5, v0
	v_and_or_b32 v13, 0xffffff1f, v7, s25
	v_add_co_ci_u32_e32 v1, vcc_lo, v8, v1, vcc_lo
	s_clause 0x3
	global_store_b128 v[0:1], v[13:16], off
	global_store_b128 v[0:1], v[17:20], off offset:16
	global_store_b128 v[0:1], v[21:24], off offset:32
	global_store_b128 v[0:1], v[25:28], off offset:48
	s_and_saveexec_b32 s18, s0
	s_cbranch_execz .LBB0_104
; %bb.97:                               ;   in Loop: Header=BB0_32 Depth=3
	s_clause 0x1
	global_load_b64 v[17:18], v6, s[2:3] offset:32 glc
	global_load_b64 v[7:8], v6, s[2:3] offset:40
	v_dual_mov_b32 v15, s16 :: v_dual_mov_b32 v16, s17
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s26, v7
	v_readfirstlane_b32 s27, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[26:27], s[26:27], s[16:17]
	s_mul_i32 s19, s27, 24
	s_mul_hi_u32 s25, s26, 24
	s_mul_i32 s26, s26, 24
	s_add_i32 s25, s25, s19
	v_add_co_u32 v7, vcc_lo, v29, s26
	v_add_co_ci_u32_e32 v8, vcc_lo, s25, v30, vcc_lo
	s_mov_b32 s19, exec_lo
	global_store_b64 v[7:8], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v6, v[15:18], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[15:16], v[17:18]
	s_cbranch_execz .LBB0_100
; %bb.98:                               ; %.preheader1.i.i17.i.preheader
                                        ;   in Loop: Header=BB0_32 Depth=3
	s_mov_b32 s25, 0
.LBB0_99:                               ; %.preheader1.i.i17.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_3 Depth=2
                                        ;       Parent Loop BB0_32 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	v_dual_mov_b32 v13, s16 :: v_dual_mov_b32 v14, s17
	s_sleep 1
	global_store_b64 v[7:8], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v6, v[13:16], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[13:14], v[15:16]
	v_dual_mov_b32 v16, v14 :: v_dual_mov_b32 v15, v13
	s_or_b32 s25, vcc_lo, s25
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s25
	s_cbranch_execnz .LBB0_99
.LBB0_100:                              ; %Flow453
                                        ;   in Loop: Header=BB0_32 Depth=3
	s_or_b32 exec_lo, exec_lo, s19
	global_load_b64 v[7:8], v6, s[2:3] offset:16
	s_mov_b32 s25, exec_lo
	s_mov_b32 s19, exec_lo
	v_mbcnt_lo_u32_b32 v5, s25, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v5
	s_cbranch_execz .LBB0_102
; %bb.101:                              ;   in Loop: Header=BB0_32 Depth=3
	s_bcnt1_i32_b32 s25, s25
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v5, s25
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[7:8], v[5:6], off offset:8
.LBB0_102:                              ;   in Loop: Header=BB0_32 Depth=3
	s_or_b32 exec_lo, exec_lo, s19
	s_waitcnt vmcnt(0)
	global_load_b64 v[13:14], v[7:8], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[13:14]
	s_cbranch_vccnz .LBB0_104
; %bb.103:                              ;   in Loop: Header=BB0_32 Depth=3
	global_load_b32 v5, v[7:8], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s19, v5
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[13:14], v[5:6], off
	s_and_b32 m0, s19, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_104:                              ; %Flow454
                                        ;   in Loop: Header=BB0_32 Depth=3
	s_or_b32 exec_lo, exec_lo, s18
	s_add_i32 s9, s9, s1
	v_add_co_u32 v5, vcc_lo, v29, s24
	v_add_co_ci_u32_e32 v8, vcc_lo, s9, v30, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v5, 20
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
.LBB0_105:                              ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_3 Depth=2
                                        ;       Parent Loop BB0_32 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	v_mov_b32_e32 v5, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_107
; %bb.106:                              ;   in Loop: Header=BB0_105 Depth=4
	global_load_b32 v5, v[7:8], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v5, 1, v5
.LBB0_107:                              ;   in Loop: Header=BB0_105 Depth=4
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v5
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_109
; %bb.108:                              ;   in Loop: Header=BB0_105 Depth=4
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_110
.LBB0_109:                              ;   in Loop: Header=BB0_105 Depth=4
	s_mov_b32 s1, -1
.LBB0_110:                              ; %Flow448
                                        ;   in Loop: Header=BB0_105 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_105
; %bb.111:                              ;   in Loop: Header=BB0_32 Depth=3
	global_load_b128 v[13:16], v[0:1], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_115
; %bb.112:                              ;   in Loop: Header=BB0_32 Depth=3
	s_clause 0x2
	global_load_b64 v[0:1], v6, s[2:3] offset:40
	global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
	global_load_b64 v[17:18], v6, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v5, vcc_lo, v0, 1
	v_add_co_ci_u32_e32 v19, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v15, vcc_lo, v5, s16
	v_add_co_ci_u32_e32 v16, vcc_lo, s17, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[15:16]
	v_dual_cndmask_b32 v16, v16, v19 :: v_dual_cndmask_b32 v15, v15, v5
	v_and_b32_e32 v1, v16, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v15, v0
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v5, v0, 24
	v_mul_lo_u32 v0, v0, 24
	v_add_nc_u32_e32 v1, v5, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v17, v0
	v_mov_b32_e32 v17, v7
	v_add_co_ci_u32_e32 v1, vcc_lo, v18, v1, vcc_lo
	v_mov_b32_e32 v18, v8
	global_store_b64 v[0:1], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[17:18], v6, v[15:18], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[17:18], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_115
; %bb.113:                              ; %.preheader.i.i16.i.preheader
                                        ;   in Loop: Header=BB0_32 Depth=3
	s_mov_b32 s0, 0
.LBB0_114:                              ; %.preheader.i.i16.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_3 Depth=2
                                        ;       Parent Loop BB0_32 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_sleep 1
	global_store_b64 v[0:1], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v6, v[15:18], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[17:18]
	v_dual_mov_b32 v18, v8 :: v_dual_mov_b32 v17, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_114
.LBB0_115:                              ; %__ockl_hostcall_preview.exit20.i
                                        ;   in Loop: Header=BB0_32 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_sub_u32 s12, s12, s14
	s_subb_u32 s13, s13, s15
	s_add_u32 s10, s10, s14
	s_addc_u32 s11, s11, s15
	s_cmp_lg_u64 s[12:13], 0
	s_cbranch_scc1 .LBB0_32
; %bb.116:                              ; %Flow493
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_mov_b32 s0, 0
	s_branch .LBB0_118
.LBB0_117:                              ;   in Loop: Header=BB0_3 Depth=2
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr13_vgpr14
.LBB0_118:                              ; %Flow508
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB0_147
; %bb.119:                              ;   in Loop: Header=BB0_3 Depth=2
	v_dual_mov_b32 v5, v41 :: v_dual_mov_b32 v0, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v5
	v_mov_b32_e32 v1, 0
	v_cmp_eq_u32_e64 s0, s0, v5
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_125
; %bb.120:                              ;   in Loop: Header=BB0_3 Depth=2
	global_load_b64 v[15:16], v6, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v6, s[2:3] offset:40
	global_load_b64 v[7:8], v6, s[2:3]
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v16
	v_and_b32_e32 v0, v0, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v13, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v13, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v7, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v8, v1, vcc_lo
	global_load_b64 v[13:14], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v6, v[13:16], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[0:1], v[15:16]
	s_cbranch_execz .LBB0_124
; %bb.121:                              ; %.preheader3.i.i.i48.preheader
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_mov_b32 s10, 0
.LBB0_122:                              ; %.preheader3.i.i.i48
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_3 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[7:8], v6, s[2:3] offset:40
	global_load_b64 v[13:14], v6, s[2:3]
	v_dual_mov_b32 v16, v1 :: v_dual_mov_b32 v15, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v7, v15
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[0:1], null, v7, 24, v[13:14]
	v_and_b32_e32 v13, v8, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v13, 24, v[1:2]
	v_mov_b32_e32 v1, v7
	global_load_b64 v[13:14], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v6, v[13:16], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[15:16]
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_122
; %bb.123:                              ; %Flow505
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_124:                              ; %Flow507
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
.LBB0_125:                              ; %.loopexit4.i.i.i43
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[7:8], v6, s[2:3] offset:40
	global_load_b128 v[15:18], v6, s[2:3]
	v_readfirstlane_b32 s12, v0
	v_readfirstlane_b32 s13, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v7
	v_readfirstlane_b32 s11, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[12:13], s[10:11]
	s_mul_i32 s1, s11, 24
	s_mul_hi_u32 s14, s10, 24
	s_mul_i32 s15, s10, 24
	s_and_saveexec_b32 s16, s0
	s_cbranch_execz .LBB0_127
; %bb.126:                              ;   in Loop: Header=BB0_3 Depth=2
	v_dual_mov_b32 v7, s9 :: v_dual_mov_b32 v8, v6
	s_add_i32 s9, s14, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v15, s15
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v16, vcc_lo
	global_store_b128 v[0:1], v[7:10], off offset:8
.LBB0_127:                              ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s16
	s_lshl_b64 s[10:11], s[10:11], 12
	v_lshlrev_b64 v[0:1], 6, v[5:6]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v17, s10
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v18, vcc_lo
	s_mov_b32 s11, s8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v5, v0
	s_mov_b32 s9, s8
	s_mov_b32 s10, s8
	v_and_or_b32 v11, 0xffffff1f, v11, 32
	v_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo
	v_dual_mov_b32 v13, v6 :: v_dual_mov_b32 v20, s11
	v_dual_mov_b32 v14, v6 :: v_dual_mov_b32 v19, s10
	v_dual_mov_b32 v18, s9 :: v_dual_mov_b32 v17, s8
	s_clause 0x3
	global_store_b128 v[0:1], v[11:14], off
	global_store_b128 v[0:1], v[17:20], off offset:16
	global_store_b128 v[0:1], v[17:20], off offset:32
	global_store_b128 v[0:1], v[17:20], off offset:48
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB0_135
; %bb.128:                              ;   in Loop: Header=BB0_3 Depth=2
	s_clause 0x1
	global_load_b64 v[19:20], v6, s[2:3] offset:32 glc
	global_load_b64 v[7:8], v6, s[2:3] offset:40
	v_dual_mov_b32 v17, s12 :: v_dual_mov_b32 v18, s13
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v7
	v_readfirstlane_b32 s11, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[12:13]
	s_mul_i32 s11, s11, 24
	s_mul_hi_u32 s16, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s16, s16, s11
	v_add_co_u32 v7, vcc_lo, v15, s10
	v_add_co_ci_u32_e32 v8, vcc_lo, s16, v16, vcc_lo
	s_mov_b32 s10, exec_lo
	global_store_b64 v[7:8], v[19:20], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v6, v[17:20], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[13:14], v[19:20]
	s_cbranch_execz .LBB0_131
; %bb.129:                              ; %.preheader1.i.i.i46.preheader
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_mov_b32 s11, 0
.LBB0_130:                              ; %.preheader1.i.i.i46
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_3 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_dual_mov_b32 v11, s12 :: v_dual_mov_b32 v12, s13
	s_sleep 1
	global_store_b64 v[7:8], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v6, v[11:14], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[13:14]
	v_dual_mov_b32 v14, v12 :: v_dual_mov_b32 v13, v11
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_130
.LBB0_131:                              ; %Flow503
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
	global_load_b64 v[7:8], v6, s[2:3] offset:16
	s_mov_b32 s11, exec_lo
	s_mov_b32 s10, exec_lo
	v_mbcnt_lo_u32_b32 v5, s11, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v5
	s_cbranch_execz .LBB0_133
; %bb.132:                              ;   in Loop: Header=BB0_3 Depth=2
	s_bcnt1_i32_b32 s11, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v5, s11
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[7:8], v[5:6], off offset:8
.LBB0_133:                              ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
	s_waitcnt vmcnt(0)
	global_load_b64 v[11:12], v[7:8], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	s_cbranch_vccnz .LBB0_135
; %bb.134:                              ;   in Loop: Header=BB0_3 Depth=2
	global_load_b32 v5, v[7:8], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v5
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[11:12], v[5:6], off
	s_and_b32 m0, s10, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_135:                              ; %Flow504
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s9
	s_add_i32 s14, s14, s1
	v_add_co_u32 v5, vcc_lo, v15, s15
	v_add_co_ci_u32_e32 v8, vcc_lo, s14, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v5, 20
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
.LBB0_136:                              ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_3 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v5, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_138
; %bb.137:                              ;   in Loop: Header=BB0_136 Depth=3
	global_load_b32 v5, v[7:8], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v5, 1, v5
.LBB0_138:                              ;   in Loop: Header=BB0_136 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v5
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_140
; %bb.139:                              ;   in Loop: Header=BB0_136 Depth=3
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_141
.LBB0_140:                              ;   in Loop: Header=BB0_136 Depth=3
	s_mov_b32 s1, -1
.LBB0_141:                              ; %Flow498
                                        ;   in Loop: Header=BB0_136 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_136
; %bb.142:                              ;   in Loop: Header=BB0_3 Depth=2
	global_load_b128 v[13:16], v[0:1], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_146
; %bb.143:                              ;   in Loop: Header=BB0_3 Depth=2
	s_clause 0x2
	global_load_b64 v[0:1], v6, s[2:3] offset:40
	global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
	global_load_b64 v[11:12], v6, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v5, vcc_lo, v0, 1
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v1, vcc_lo
	s_waitcnt vmcnt(1)
	v_mov_b32_e32 v18, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v15, vcc_lo, v5, s12
	v_add_co_ci_u32_e32 v16, vcc_lo, s13, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[15:16]
	v_dual_cndmask_b32 v16, v16, v17 :: v_dual_mov_b32 v17, v7
	v_cndmask_b32_e32 v15, v15, v5, vcc_lo
	v_and_b32_e32 v1, v16, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v15, v0
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v5, v0, 24
	v_mul_lo_u32 v0, v0, 24
	v_add_nc_u32_e32 v1, v5, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v11, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, v12, v1, vcc_lo
	global_store_b64 v[0:1], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[17:18], v6, v[15:18], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[17:18], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_146
; %bb.144:                              ; %.preheader.i.i.i45.preheader
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_mov_b32 s0, 0
.LBB0_145:                              ; %.preheader.i.i.i45
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_3 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	global_store_b64 v[0:1], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v6, v[15:18], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[17:18]
	v_dual_mov_b32 v18, v8 :: v_dual_mov_b32 v17, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_145
.LBB0_146:                              ; %__ockl_hostcall_preview.exit.i
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
.LBB0_147:                              ; %__ockl_printf_append_string_n.exit
                                        ;   in Loop: Header=BB0_3 Depth=2
	v_dual_mov_b32 v5, v41 :: v_dual_mov_b32 v0, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v5
	v_mov_b32_e32 v1, 0
	v_cmp_eq_u32_e64 s0, s0, v5
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_153
; %bb.148:                              ;   in Loop: Header=BB0_3 Depth=2
	global_load_b64 v[17:18], v6, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v6, s[2:3] offset:40
	global_load_b64 v[7:8], v6, s[2:3]
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v18
	v_and_b32_e32 v0, v0, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v11, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v11, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v7, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v8, v1, vcc_lo
	global_load_b64 v[15:16], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v6, v[15:18], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[0:1], v[17:18]
	s_cbranch_execz .LBB0_152
; %bb.149:                              ; %.preheader3.i.i.i55.preheader
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_mov_b32 s10, 0
.LBB0_150:                              ; %.preheader3.i.i.i55
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_3 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[7:8], v6, s[2:3] offset:40
	global_load_b64 v[11:12], v6, s[2:3]
	v_dual_mov_b32 v18, v1 :: v_dual_mov_b32 v17, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v7, v17
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[0:1], null, v7, 24, v[11:12]
	v_and_b32_e32 v11, v8, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v11, 24, v[1:2]
	v_mov_b32_e32 v1, v7
	global_load_b64 v[15:16], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v6, v[15:18], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[17:18]
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_150
; %bb.151:                              ; %Flow441
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_152:                              ; %Flow443
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
.LBB0_153:                              ; %.loopexit4.i.i.i49
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[7:8], v6, s[2:3] offset:40
	global_load_b128 v[17:20], v6, s[2:3]
	v_readfirstlane_b32 s12, v0
	v_readfirstlane_b32 s13, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v7
	v_readfirstlane_b32 s11, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[12:13], s[10:11]
	s_mul_i32 s1, s11, 24
	s_mul_hi_u32 s14, s10, 24
	s_mul_i32 s15, s10, 24
	s_and_saveexec_b32 s16, s0
	s_cbranch_execz .LBB0_155
; %bb.154:                              ;   in Loop: Header=BB0_3 Depth=2
	v_dual_mov_b32 v7, s9 :: v_dual_mov_b32 v8, v6
	s_add_i32 s9, s14, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v17, s15
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v18, vcc_lo
	global_store_b128 v[0:1], v[7:10], off offset:8
.LBB0_155:                              ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s16
	s_lshl_b64 s[10:11], s[10:11], 12
	v_lshlrev_b64 v[0:1], 6, v[5:6]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v19, s10
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v20, vcc_lo
	s_mov_b32 s11, s8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v5, v0
	s_mov_b32 s9, s8
	s_mov_b32 s10, s8
	v_and_or_b32 v13, 0xffffff1f, v13, 32
	v_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo
	v_dual_mov_b32 v15, v33 :: v_dual_mov_b32 v16, v42
	v_dual_mov_b32 v22, s11 :: v_dual_mov_b32 v21, s10
	v_dual_mov_b32 v20, s9 :: v_dual_mov_b32 v19, s8
	s_clause 0x3
	global_store_b128 v[0:1], v[13:16], off
	global_store_b128 v[0:1], v[19:22], off offset:16
	global_store_b128 v[0:1], v[19:22], off offset:32
	global_store_b128 v[0:1], v[19:22], off offset:48
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB0_163
; %bb.156:                              ;   in Loop: Header=BB0_3 Depth=2
	s_clause 0x1
	global_load_b64 v[15:16], v6, s[2:3] offset:32 glc
	global_load_b64 v[7:8], v6, s[2:3] offset:40
	v_dual_mov_b32 v13, s12 :: v_dual_mov_b32 v14, s13
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v7
	v_readfirstlane_b32 s11, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[12:13]
	s_mul_i32 s11, s11, 24
	s_mul_hi_u32 s16, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s16, s16, s11
	v_add_co_u32 v7, vcc_lo, v17, s10
	v_add_co_ci_u32_e32 v8, vcc_lo, s16, v18, vcc_lo
	s_mov_b32 s10, exec_lo
	global_store_b64 v[7:8], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v6, v[13:16], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[13:14], v[15:16]
	s_cbranch_execz .LBB0_159
; %bb.157:                              ; %.preheader1.i.i.i53.preheader
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_mov_b32 s11, 0
.LBB0_158:                              ; %.preheader1.i.i.i53
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_3 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_dual_mov_b32 v11, s12 :: v_dual_mov_b32 v12, s13
	s_sleep 1
	global_store_b64 v[7:8], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[11:12], v6, v[11:14], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[11:12], v[13:14]
	v_dual_mov_b32 v14, v12 :: v_dual_mov_b32 v13, v11
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_158
.LBB0_159:                              ; %Flow439
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
	global_load_b64 v[7:8], v6, s[2:3] offset:16
	s_mov_b32 s11, exec_lo
	s_mov_b32 s10, exec_lo
	v_mbcnt_lo_u32_b32 v5, s11, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v5
	s_cbranch_execz .LBB0_161
; %bb.160:                              ;   in Loop: Header=BB0_3 Depth=2
	s_bcnt1_i32_b32 s11, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v5, s11
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[7:8], v[5:6], off offset:8
.LBB0_161:                              ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
	s_waitcnt vmcnt(0)
	global_load_b64 v[11:12], v[7:8], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	s_cbranch_vccnz .LBB0_163
; %bb.162:                              ;   in Loop: Header=BB0_3 Depth=2
	global_load_b32 v5, v[7:8], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v5
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[11:12], v[5:6], off
	s_and_b32 m0, s10, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_163:                              ; %Flow440
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s9
	s_add_i32 s14, s14, s1
	v_add_co_u32 v5, vcc_lo, v17, s15
	v_add_co_ci_u32_e32 v8, vcc_lo, s14, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v5, 20
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v8, vcc_lo
.LBB0_164:                              ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_3 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v5, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_166
; %bb.165:                              ;   in Loop: Header=BB0_164 Depth=3
	global_load_b32 v5, v[7:8], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v5, 1, v5
.LBB0_166:                              ;   in Loop: Header=BB0_164 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v5
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_168
; %bb.167:                              ;   in Loop: Header=BB0_164 Depth=3
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_169
.LBB0_168:                              ;   in Loop: Header=BB0_164 Depth=3
	s_mov_b32 s1, -1
.LBB0_169:                              ; %Flow434
                                        ;   in Loop: Header=BB0_164 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_164
; %bb.170:                              ;   in Loop: Header=BB0_3 Depth=2
	global_load_b64 v[0:1], v[0:1], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_174
; %bb.171:                              ;   in Loop: Header=BB0_3 Depth=2
	s_clause 0x2
	global_load_b64 v[7:8], v6, s[2:3] offset:40
	global_load_b64 v[15:16], v6, s[2:3] offset:24 glc
	global_load_b64 v[13:14], v6, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v5, vcc_lo, v7, 1
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v5, s12
	v_add_co_ci_u32_e32 v12, vcc_lo, s13, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	v_cndmask_b32_e32 v11, v11, v5, vcc_lo
	v_dual_cndmask_b32 v12, v12, v17 :: v_dual_and_b32 v7, v11, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v5, v12, v8
	v_mul_hi_u32 v8, v7, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v5, v5, 24
	v_mul_lo_u32 v7, v7, 24
	v_add_nc_u32_e32 v5, v8, v5
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v7, vcc_lo, v13, v7
	v_mov_b32_e32 v13, v15
	v_add_co_ci_u32_e32 v8, vcc_lo, v14, v5, vcc_lo
	v_mov_b32_e32 v14, v16
	global_store_b64 v[7:8], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v6, v[11:14], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[13:14], v[15:16]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_174
; %bb.172:                              ; %.preheader.i.i.i52.preheader
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_mov_b32 s0, 0
.LBB0_173:                              ; %.preheader.i.i.i52
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_3 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	global_store_b64 v[7:8], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v6, v[11:14], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[15:16], v[13:14]
	v_dual_mov_b32 v13, v15 :: v_dual_mov_b32 v14, v16
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_173
.LBB0_174:                              ; %__ockl_printf_append_args.exit
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	v_mov_b32_e32 v5, v41
	v_mov_b32_e32 v7, 0
	v_mov_b32_e32 v8, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s0, v5
	v_cmp_eq_u32_e64 s0, s0, v5
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_180
; %bb.175:                              ;   in Loop: Header=BB0_3 Depth=2
	global_load_b64 v[13:14], v6, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[7:8], v6, s[2:3] offset:40
	global_load_b64 v[11:12], v6, s[2:3]
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v8, v8, v14
	v_and_b32_e32 v7, v7, v13
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v8, v8, 24
	v_mul_hi_u32 v15, v7, 24
	v_mul_lo_u32 v7, v7, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v8, v15, v8
	s_waitcnt vmcnt(0)
	v_add_co_u32 v7, vcc_lo, v11, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, v12, v8, vcc_lo
	global_load_b64 v[11:12], v[7:8], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[7:8], v6, v[11:14], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[7:8], v[13:14]
	s_cbranch_execz .LBB0_179
; %bb.176:                              ; %.preheader3.i.i.i62.preheader
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_mov_b32 s10, 0
.LBB0_177:                              ; %.preheader3.i.i.i62
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_3 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[11:12], v6, s[2:3] offset:40
	global_load_b64 v[15:16], v6, s[2:3]
	v_dual_mov_b32 v14, v8 :: v_dual_mov_b32 v13, v7
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v11, v11, v13
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[7:8], null, v11, 24, v[15:16]
	v_and_b32_e32 v15, v12, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[11:12], null, v15, 24, v[8:9]
	v_mov_b32_e32 v8, v11
	global_load_b64 v[11:12], v[7:8], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[7:8], v6, v[11:14], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[13:14]
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_177
; %bb.178:                              ; %Flow427
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_179:                              ; %Flow429
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
.LBB0_180:                              ; %.loopexit4.i.i.i56
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[15:16], v6, s[2:3] offset:40
	global_load_b128 v[11:14], v6, s[2:3]
	v_readfirstlane_b32 s12, v7
	v_readfirstlane_b32 s13, v8
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v15
	v_readfirstlane_b32 s11, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[12:13], s[10:11]
	s_mul_i32 s1, s11, 24
	s_mul_hi_u32 s14, s10, 24
	s_mul_i32 s15, s10, 24
	s_and_saveexec_b32 s16, s0
	s_cbranch_execz .LBB0_182
; %bb.181:                              ;   in Loop: Header=BB0_3 Depth=2
	v_dual_mov_b32 v7, s9 :: v_dual_mov_b32 v8, v6
	s_add_i32 s9, s14, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v15, vcc_lo, v11, s15
	v_add_co_ci_u32_e32 v16, vcc_lo, s9, v12, vcc_lo
	global_store_b128 v[15:16], v[7:10], off offset:8
.LBB0_182:                              ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s16
	s_lshl_b64 s[10:11], s[10:11], 12
	v_lshlrev_b64 v[7:8], 6, v[5:6]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v13, vcc_lo, v13, s10
	v_add_co_ci_u32_e32 v14, vcc_lo, s11, v14, vcc_lo
	s_mov_b32 s11, s8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, v13, v7
	s_mov_b32 s9, s8
	s_mov_b32 s10, s8
	v_and_or_b32 v0, 0xffffff1f, v0, 32
	v_add_co_ci_u32_e32 v8, vcc_lo, v14, v8, vcc_lo
	v_dual_mov_b32 v16, s11 :: v_dual_mov_b32 v15, s10
	v_dual_mov_b32 v14, s9 :: v_dual_mov_b32 v13, s8
	s_clause 0x3
	global_store_b128 v[7:8], v[0:3], off
	global_store_b128 v[7:8], v[13:16], off offset:16
	global_store_b128 v[7:8], v[13:16], off offset:32
	global_store_b128 v[7:8], v[13:16], off offset:48
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB0_190
; %bb.183:                              ;   in Loop: Header=BB0_3 Depth=2
	s_clause 0x1
	global_load_b64 v[17:18], v6, s[2:3] offset:32 glc
	global_load_b64 v[0:1], v6, s[2:3] offset:40
	v_dual_mov_b32 v15, s12 :: v_dual_mov_b32 v16, s13
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v0
	v_readfirstlane_b32 s11, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[12:13]
	s_mul_i32 s11, s11, 24
	s_mul_hi_u32 s16, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s16, s16, s11
	v_add_co_u32 v0, vcc_lo, v11, s10
	v_add_co_ci_u32_e32 v1, vcc_lo, s16, v12, vcc_lo
	s_mov_b32 s10, exec_lo
	global_store_b64 v[0:1], v[17:18], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v6, v[15:18], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[15:16], v[17:18]
	s_cbranch_execz .LBB0_186
; %bb.184:                              ; %.preheader1.i.i.i60.preheader
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_mov_b32 s11, 0
.LBB0_185:                              ; %.preheader1.i.i.i60
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_3 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_dual_mov_b32 v13, s12 :: v_dual_mov_b32 v14, s13
	s_sleep 1
	global_store_b64 v[0:1], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v6, v[13:16], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[13:14], v[15:16]
	v_dual_mov_b32 v16, v14 :: v_dual_mov_b32 v15, v13
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_185
.LBB0_186:                              ; %Flow425
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
	global_load_b64 v[0:1], v6, s[2:3] offset:16
	s_mov_b32 s11, exec_lo
	s_mov_b32 s10, exec_lo
	v_mbcnt_lo_u32_b32 v5, s11, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v5
	s_cbranch_execz .LBB0_188
; %bb.187:                              ;   in Loop: Header=BB0_3 Depth=2
	s_bcnt1_i32_b32 s11, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v5, s11
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[5:6], off offset:8
.LBB0_188:                              ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
	s_waitcnt vmcnt(0)
	global_load_b64 v[13:14], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[13:14]
	s_cbranch_vccnz .LBB0_190
; %bb.189:                              ;   in Loop: Header=BB0_3 Depth=2
	global_load_b32 v5, v[0:1], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v5
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[13:14], v[5:6], off
	s_and_b32 m0, s10, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_190:                              ; %Flow426
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s9
	s_add_i32 s14, s14, s1
	v_add_co_u32 v0, vcc_lo, v11, s15
	v_add_co_ci_u32_e32 v1, vcc_lo, s14, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB0_191:                              ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_3 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v5, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_193
; %bb.192:                              ;   in Loop: Header=BB0_191 Depth=3
	global_load_b32 v5, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v5, 1, v5
.LBB0_193:                              ;   in Loop: Header=BB0_191 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v5
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_195
; %bb.194:                              ;   in Loop: Header=BB0_191 Depth=3
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_196
.LBB0_195:                              ;   in Loop: Header=BB0_191 Depth=3
	s_mov_b32 s1, -1
.LBB0_196:                              ; %Flow420
                                        ;   in Loop: Header=BB0_191 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_191
; %bb.197:                              ;   in Loop: Header=BB0_3 Depth=2
	global_load_b64 v[11:12], v[7:8], off
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_201
; %bb.198:                              ;   in Loop: Header=BB0_3 Depth=2
	s_clause 0x2
	global_load_b64 v[0:1], v6, s[2:3] offset:40
	global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
	global_load_b64 v[15:16], v6, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v5, vcc_lo, v0, 1
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v13, vcc_lo, v5, s12
	v_add_co_ci_u32_e32 v14, vcc_lo, s13, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[13:14]
	v_cndmask_b32_e32 v13, v13, v5, vcc_lo
	v_cndmask_b32_e32 v14, v14, v17, vcc_lo
	v_and_b32_e32 v0, v13, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v5, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v15, v0
	v_mov_b32_e32 v15, v7
	v_and_b32_e32 v1, v14, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v1, v1, 24
	v_add_nc_u32_e32 v1, v5, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_co_ci_u32_e32 v1, vcc_lo, v16, v1, vcc_lo
	v_mov_b32_e32 v16, v8
	global_store_b64 v[0:1], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[15:16], v6, v[13:16], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[15:16], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_201
; %bb.199:                              ; %.preheader.i.i.i59.preheader
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_mov_b32 s0, 0
.LBB0_200:                              ; %.preheader.i.i.i59
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_3 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	global_store_b64 v[0:1], v[15:16], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v6, v[13:16], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[15:16]
	v_dual_mov_b32 v16, v8 :: v_dual_mov_b32 v15, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_200
.LBB0_201:                              ; %__ockl_printf_append_args.exit63
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	v_dual_mov_b32 v5, v41 :: v_dual_mov_b32 v0, 0
	;;#ASMSTART
	;;#ASMEND
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s0, v5
	v_mov_b32_e32 v1, 0
	v_cmp_eq_u32_e64 s0, s0, v5
	s_delay_alu instid0(VALU_DEP_1)
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_207
; %bb.202:                              ;   in Loop: Header=BB0_3 Depth=2
	global_load_b64 v[15:16], v6, s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	s_clause 0x1
	global_load_b64 v[0:1], v6, s[2:3] offset:40
	global_load_b64 v[7:8], v6, s[2:3]
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_and_b32_e32 v1, v1, v16
	v_and_b32_e32 v0, v0, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v1, v1, 24
	v_mul_hi_u32 v13, v0, 24
	v_mul_lo_u32 v0, v0, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, v13, v1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v7, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, v8, v1, vcc_lo
	global_load_b64 v[13:14], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v6, v[13:16], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmpx_ne_u64_e64 v[0:1], v[15:16]
	s_cbranch_execz .LBB0_206
; %bb.203:                              ; %.preheader3.i.i.i70.preheader
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_mov_b32 s10, 0
.LBB0_204:                              ; %.preheader3.i.i.i70
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_3 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	s_clause 0x1
	global_load_b64 v[7:8], v6, s[2:3] offset:40
	global_load_b64 v[13:14], v6, s[2:3]
	v_dual_mov_b32 v16, v1 :: v_dual_mov_b32 v15, v0
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_and_b32_e32 v7, v7, v15
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[0:1], null, v7, 24, v[13:14]
	v_and_b32_e32 v13, v8, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, v13, 24, v[1:2]
	v_mov_b32_e32 v1, v7
	global_load_b64 v[13:14], v[0:1], off glc
	s_waitcnt vmcnt(0)
	global_atomic_cmpswap_b64 v[0:1], v6, v[13:16], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_cmp_eq_u64_e32 vcc_lo, v[0:1], v[15:16]
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_204
; %bb.205:                              ; %Flow413
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
.LBB0_206:                              ; %Flow415
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s9
.LBB0_207:                              ; %.loopexit4.i.i.i64
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s1
	s_clause 0x1
	global_load_b64 v[7:8], v6, s[2:3] offset:40
	global_load_b128 v[15:18], v6, s[2:3]
	v_readfirstlane_b32 s12, v0
	v_readfirstlane_b32 s13, v1
	s_mov_b32 s9, exec_lo
	s_waitcnt vmcnt(1)
	v_readfirstlane_b32 s10, v7
	v_readfirstlane_b32 s11, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[12:13], s[10:11]
	s_mul_i32 s1, s11, 24
	s_mul_hi_u32 s14, s10, 24
	s_mul_i32 s15, s10, 24
	s_and_saveexec_b32 s16, s0
	s_cbranch_execz .LBB0_209
; %bb.208:                              ;   in Loop: Header=BB0_3 Depth=2
	v_dual_mov_b32 v7, s9 :: v_dual_mov_b32 v8, v6
	s_add_i32 s9, s14, s1
	s_waitcnt vmcnt(0)
	v_add_co_u32 v0, vcc_lo, v15, s15
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v16, vcc_lo
	global_store_b128 v[0:1], v[7:10], off offset:8
.LBB0_209:                              ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s16
	s_lshl_b64 s[10:11], s[10:11], 12
	v_lshlrev_b64 v[0:1], 6, v[5:6]
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[13:14], null, v44, v43, v[34:35]
	s_waitcnt vmcnt(0)
	v_add_co_u32 v5, vcc_lo, v17, s10
	v_add_co_ci_u32_e32 v7, vcc_lo, s11, v18, vcc_lo
	s_mov_b32 s11, s8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v5, v0
	s_mov_b32 s9, s8
	s_mov_b32 s10, s8
	v_and_or_b32 v11, 0xffffff1d, v11, 34
	v_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo
	v_mov_b32_e32 v14, v6
	v_dual_mov_b32 v20, s11 :: v_dual_mov_b32 v17, s8
	v_dual_mov_b32 v34, v13 :: v_dual_mov_b32 v19, s10
	v_mov_b32_e32 v18, s9
	s_clause 0x3
	global_store_b128 v[0:1], v[11:14], off
	global_store_b128 v[0:1], v[17:20], off offset:16
	global_store_b128 v[0:1], v[17:20], off offset:32
	global_store_b128 v[0:1], v[17:20], off offset:48
	s_and_saveexec_b32 s9, s0
	s_cbranch_execz .LBB0_217
; %bb.210:                              ;   in Loop: Header=BB0_3 Depth=2
	s_clause 0x1
	global_load_b64 v[19:20], v6, s[2:3] offset:32 glc
	global_load_b64 v[0:1], v6, s[2:3] offset:40
	v_dual_mov_b32 v17, s12 :: v_dual_mov_b32 v18, s13
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v0
	v_readfirstlane_b32 s11, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b64 s[10:11], s[10:11], s[12:13]
	s_mul_i32 s11, s11, 24
	s_mul_hi_u32 s16, s10, 24
	s_mul_i32 s10, s10, 24
	s_add_i32 s16, s16, s11
	v_add_co_u32 v0, vcc_lo, v15, s10
	v_add_co_ci_u32_e32 v1, vcc_lo, s16, v16, vcc_lo
	s_mov_b32 s10, exec_lo
	global_store_b64 v[0:1], v[19:20], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v6, v[17:20], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmpx_ne_u64_e64 v[13:14], v[19:20]
	s_cbranch_execz .LBB0_213
; %bb.211:                              ; %.preheader1.i.i.i68.preheader
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_mov_b32 s11, 0
.LBB0_212:                              ; %.preheader1.i.i.i68
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_3 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_dual_mov_b32 v11, s12 :: v_dual_mov_b32 v12, s13
	s_sleep 1
	global_store_b64 v[0:1], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v6, v[11:14], s[2:3] offset:32 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[13:14]
	v_dual_mov_b32 v14, v8 :: v_dual_mov_b32 v13, v7
	s_or_b32 s11, vcc_lo, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_212
.LBB0_213:                              ; %Flow411
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
	global_load_b64 v[0:1], v6, s[2:3] offset:16
	s_mov_b32 s11, exec_lo
	s_mov_b32 s10, exec_lo
	v_mbcnt_lo_u32_b32 v5, s11, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_eq_u32_e32 0, v5
	s_cbranch_execz .LBB0_215
; %bb.214:                              ;   in Loop: Header=BB0_3 Depth=2
	s_bcnt1_i32_b32 s11, s11
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v5, s11
	s_waitcnt vmcnt(0)
	global_atomic_add_u64 v[0:1], v[5:6], off offset:8
.LBB0_215:                              ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s10
	s_waitcnt vmcnt(0)
	global_load_b64 v[7:8], v[0:1], off offset:16
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[7:8]
	s_cbranch_vccnz .LBB0_217
; %bb.216:                              ;   in Loop: Header=BB0_3 Depth=2
	global_load_b32 v5, v[0:1], off offset:24
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s10, v5
	s_waitcnt_vscnt null, 0x0
	global_store_b64 v[7:8], v[5:6], off
	s_and_b32 m0, s10, 0xff
	s_sendmsg sendmsg(MSG_INTERRUPT)
.LBB0_217:                              ; %Flow412
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s9
	s_add_i32 s14, s14, s1
	v_add_co_u32 v0, vcc_lo, v15, s15
	v_add_co_ci_u32_e32 v1, vcc_lo, s14, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, 20
	v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
.LBB0_218:                              ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_3 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	v_mov_b32_e32 v5, 1
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_220
; %bb.219:                              ;   in Loop: Header=BB0_218 Depth=3
	global_load_b32 v5, v[0:1], off glc
	s_waitcnt vmcnt(0)
	buffer_gl1_inv
	buffer_gl0_inv
	v_and_b32_e32 v5, 1, v5
.LBB0_220:                              ;   in Loop: Header=BB0_218 Depth=3
	s_or_b32 exec_lo, exec_lo, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s1, v5
	s_cmp_eq_u32 s1, 0
	s_cbranch_scc1 .LBB0_222
; %bb.221:                              ;   in Loop: Header=BB0_218 Depth=3
	s_mov_b32 s1, 0
	s_sleep 1
	s_branch .LBB0_223
.LBB0_222:                              ;   in Loop: Header=BB0_218 Depth=3
	s_mov_b32 s1, -1
.LBB0_223:                              ; %Flow406
                                        ;   in Loop: Header=BB0_218 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_218
; %bb.224:                              ;   in Loop: Header=BB0_3 Depth=2
	s_and_saveexec_b32 s1, s0
	s_cbranch_execz .LBB0_228
; %bb.225:                              ;   in Loop: Header=BB0_3 Depth=2
	s_clause 0x2
	global_load_b64 v[0:1], v6, s[2:3] offset:40
	global_load_b64 v[7:8], v6, s[2:3] offset:24 glc
	global_load_b64 v[13:14], v6, s[2:3]
	s_waitcnt vmcnt(2)
	v_add_co_u32 v5, vcc_lo, v0, 1
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, v5, s12
	v_add_co_ci_u32_e32 v12, vcc_lo, s13, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_eq_u64_e32 vcc_lo, 0, v[11:12]
	v_dual_cndmask_b32 v12, v12, v15 :: v_dual_cndmask_b32 v11, v11, v5
	v_and_b32_e32 v1, v12, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_and_b32_e32 v0, v11, v0
	v_mul_lo_u32 v1, v1, 24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v5, v0, 24
	v_mul_lo_u32 v0, v0, 24
	v_add_nc_u32_e32 v1, v5, v1
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v13, v0
	v_mov_b32_e32 v13, v7
	v_add_co_ci_u32_e32 v1, vcc_lo, v14, v1, vcc_lo
	v_mov_b32_e32 v14, v8
	global_store_b64 v[0:1], v[7:8], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[13:14], v6, v[11:14], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_ne_u64_e32 vcc_lo, v[13:14], v[7:8]
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_228
; %bb.226:                              ; %.preheader.i.i.i67.preheader
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_mov_b32 s0, 0
.LBB0_227:                              ; %.preheader.i.i.i67
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_3 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_sleep 1
	global_store_b64 v[0:1], v[13:14], off
	s_waitcnt_vscnt null, 0x0
	global_atomic_cmpswap_b64 v[7:8], v6, v[11:14], s[2:3] offset:24 glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u64_e32 vcc_lo, v[7:8], v[13:14]
	v_dual_mov_b32 v14, v8 :: v_dual_mov_b32 v13, v7
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_227
.LBB0_228:                              ; %__ockl_printf_append_args.exit71
                                        ;   in Loop: Header=BB0_3 Depth=2
	s_or_b32 exec_lo, exec_lo, s1
	s_add_i32 s23, s23, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s23, 4
	s_cbranch_scc0 .LBB0_3
; %bb.229:                              ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s22, s22, 1
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_cmp_eq_u32 s22, s21
	s_barrier
	buffer_gl0_inv
	s_cbranch_scc0 .LBB0_2
.LBB0_230:                              ; %Flow525
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[0:1], null, v33, s20, v[2:3]
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s6, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s7, v1, vcc_lo
	global_store_b32 v[0:1], v34, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10runMaxtrixIiEvPT_S1_i
		.amdhsa_group_segment_fixed_size 128
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 280
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 46
		.amdhsa_next_free_sgpr 28
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.section	.text._Z10runMaxtrixIiEvPT_S1_i,"axG",@progbits,_Z10runMaxtrixIiEvPT_S1_i,comdat
.Lfunc_end0:
	.size	_Z10runMaxtrixIiEvPT_S1_i, .Lfunc_end0-_Z10runMaxtrixIiEvPT_S1_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 9684
; NumSgprs: 30
; NumVgprs: 46
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 128 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 30
; NumVGPRsForWavesPerEU: 46
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	.str,@object                    ; @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.str:
	.asciz	"(%d, %d), tval=->%d\n"
	.size	.str, 21

	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         28
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         36
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         38
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         40
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         42
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         44
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         46
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         88
        .size:           2
        .value_kind:     hidden_grid_dims
      - .offset:         104
        .size:           8
        .value_kind:     hidden_hostcall_buffer
    .group_segment_fixed_size: 128
    .kernarg_segment_align: 8
    .kernarg_segment_size: 280
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10runMaxtrixIiEvPT_S1_i
    .private_segment_fixed_size: 0
    .sgpr_count:     30
    .sgpr_spill_count: 0
    .symbol:         _Z10runMaxtrixIiEvPT_S1_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     46
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
