#include <stdio.h>
#include <stdlib.h>
#include <time.h>


#include <cuda.h>
#include <curand_kernel.h>

#define N        100		// total number of items in vectors
#define nthreads 4	   // total number of threads in a block



__global__ void estimatepi(int n, int *sum)

{
	__shared__ int counter[nthreads];
	int threadID;
	threadID = blockIdx.x * blockDim.x + threadIdx.x;
	unsigned int seed = threadID;
	curandState s;
	curand_init(seed, 0, 0, &s);
	if(threadID < n){
		double x, y, diff, angle;
		int t;
		counter[threadIdx.x] = 0;
		for (t = 0; t<n; t++){
			x = curand_uniform(&s); //curand
			y = curand_uniform(&s); //curand
			while(x*x + y*y > 1){
				x = curand_uniform(&s); //curand
				y = curand_uniform(&s); //rand
			}

			angle = atan2 ( y, x ); //use inverse tan;
			diff = curand_uniform(&s);
			if(diff <= sin (angle) *2){
				counter[threadIdx.x] = counter[threadIdx.x] + 1;
			}
		}

		if(threadIdx.x == 0){
			sum[blockIdx.x] = 0;
			for(int i=0; i<nthreads; i++)	{
				sum[blockIdx.x] = sum[blockIdx.x] + counter[i];
			}
		}
	}
}

int main()
{	
		
		srand(time(NULL));	
		int  *sum_h;
		int *sum_d;
		
	
		sum_h   = (int*)malloc( N* sizeof(int));
	
		cudaMalloc((void**)&sum_d,   N * sizeof(int));


	
		int nblocks = (N + nthreads - 1)/nthreads; 
		estimatepi<<<nblocks,nthreads>>>(N,sum_d);

    
   		cudaMemcpy(sum_h, sum_d, N * sizeof(int), cudaMemcpyDeviceToHost);

	 
		int success = 0;
		for(int i = 0; i < nblocks; i++){
		success = sum_h[i] + success; 
}
		printf("trials === %d", N * nblocks * nthreads );		
		printf("  success === %d\n", success);
		double  pi_estimate = 2 * N * nthreads * nblocks/( double )success;
		printf("pi_estimate == %f", pi_estimate);
		

		printf("\n");
		cudaFree(sum_d);
		free(sum_h);
}
 	
	.file	"tmpxft_002426b7_00000000-6_buffon.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2244:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2244:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z31__device_stub__Z10estimatepiiPiiPi
	.type	_Z31__device_stub__Z10estimatepiiPiiPi, @function
_Z31__device_stub__Z10estimatepiiPiiPi:
.LFB2266:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movl	%edi, 12(%rsp)
	leaq	32(%rsp), %rcx
	leaq	24(%rsp), %rdx
	movq	%rsi, (%rsp)
	leaq	40(%rsp), %rdi
	leaq	52(%rsp), %rsi
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	12(%rsp), %rax
	movl	$1, 48(%rsp)
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 40(%rsp)
	movq	%rax, 52(%rsp)
	movl	$1, 60(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	32(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z10estimatepiiPi(%rip), %rdi
	pushq	32(%rsp)
	.cfi_def_cfa_offset 144
	movq	68(%rsp), %rcx
	movl	76(%rsp), %r8d
	movq	56(%rsp), %rsi
	movl	64(%rsp), %edx
	leaq	104(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L2:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2266:
	.size	_Z31__device_stub__Z10estimatepiiPiiPi, .-_Z31__device_stub__Z10estimatepiiPiiPi
	.globl	_Z10estimatepiiPi
	.type	_Z10estimatepiiPi, @function
_Z10estimatepiiPi:
.LFB2267:
	.cfi_startproc
	endbr64
	jmp	_Z31__device_stub__Z10estimatepiiPiiPi
	.cfi_endproc
.LFE2267:
	.size	_Z10estimatepiiPi, .-_Z10estimatepiiPi
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"trials === %d"
.LC1:
	.string	"  success === %d\n"
.LC3:
	.string	"pi_estimate == %f"
.LC4:
	.string	"\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2241:
	.cfi_startproc
	endbr64
	pushq	%rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	xorl	%edi, %edi
	pushq	%rbx
	.cfi_def_cfa_offset 24
	.cfi_offset 3, -24
	subq	$56, %rsp
	.cfi_def_cfa_offset 80
	movq	%fs:40, %rax
	movq	%rax, 40(%rsp)
	xorl	%eax, %eax
	call	time@PLT
	movl	%eax, %edi
	call	srand@PLT
	movl	$400, %edi
	call	malloc@PLT
	leaq	8(%rsp), %rdi
	movl	$400, %esi
	movq	%rax, %rbx
	call	cudaMalloc@PLT
	movl	$1073741825, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	salq	$2, %rdx
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$4294967321, %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L9
	movq	8(%rsp), %rsi
	movl	$100, %edi
	call	_Z31__device_stub__Z10estimatepiiPiiPi
.L9:
	movq	8(%rsp), %rsi
	movl	$2, %ecx
	movq	%rbx, %rdi
	xorl	%ebp, %ebp
	movl	$400, %edx
	call	cudaMemcpy@PLT
	xorl	%eax, %eax
.L10:
	addl	(%rbx,%rax,4), %ebp
	incq	%rax
	cmpq	$25, %rax
	jne	.L10
	movl	$10000, %edx
	leaq	.LC0(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movl	%ebp, %edx
	leaq	.LC1(%rip), %rsi
	xorl	%eax, %eax
	movl	$2, %edi
	call	__printf_chk@PLT
	cvtsi2sdl	%ebp, %xmm1
	movl	$2, %edi
	movb	$1, %al
	movsd	.LC2(%rip), %xmm0
	leaq	.LC3(%rip), %rsi
	divsd	%xmm1, %xmm0
	call	__printf_chk@PLT
	leaq	.LC4(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	%rbx, %rdi
	call	free@PLT
	movq	40(%rsp), %rax
	subq	%fs:40, %rax
	je	.L11
	call	__stack_chk_fail@PLT
.L11:
	addq	$56, %rsp
	.cfi_def_cfa_offset 24
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2241:
	.size	main, .-main
	.section	.rodata.str1.1
.LC5:
	.string	"_Z10estimatepiiPi"
.LC6:
	.string	"precalc_xorwow_matrix"
.LC7:
	.string	"precalc_xorwow_offset_matrix"
.LC8:
	.string	"mrg32k3aM1"
.LC9:
	.string	"mrg32k3aM2"
.LC10:
	.string	"mrg32k3aM1SubSeq"
.LC11:
	.string	"mrg32k3aM2SubSeq"
.LC12:
	.string	"mrg32k3aM1Seq"
.LC13:
	.string	"mrg32k3aM2Seq"
.LC14:
	.string	"__cr_lgamma_table"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2269:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z10estimatepiiPi(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC6(%rip), %rdx
	movl	$102400, %r9d
	leaq	_ZL21precalc_xorwow_matrix(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$102400, %r9d
	leaq	_ZL28precalc_xorwow_offset_matrix(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC8(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM1(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC9(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL10mrg32k3aM2(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM1SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC11(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2016, %r9d
	leaq	_ZL16mrg32k3aM2SubSeq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC12(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM1Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC13(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$2304, %r9d
	leaq	_ZL13mrg32k3aM2Seq(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$1
	.cfi_def_cfa_offset 32
	leaq	.LC14(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movl	$72, %r9d
	movq	%rdx, %rcx
	leaq	_ZL17__cr_lgamma_table(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2269:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.local	_ZL17__cr_lgamma_table
	.comm	_ZL17__cr_lgamma_table,72,32
	.local	_ZL13mrg32k3aM2Seq
	.comm	_ZL13mrg32k3aM2Seq,2304,32
	.local	_ZL13mrg32k3aM1Seq
	.comm	_ZL13mrg32k3aM1Seq,2304,32
	.local	_ZL16mrg32k3aM2SubSeq
	.comm	_ZL16mrg32k3aM2SubSeq,2016,32
	.local	_ZL16mrg32k3aM1SubSeq
	.comm	_ZL16mrg32k3aM1SubSeq,2016,32
	.local	_ZL10mrg32k3aM2
	.comm	_ZL10mrg32k3aM2,2304,32
	.local	_ZL10mrg32k3aM1
	.comm	_ZL10mrg32k3aM1,2304,32
	.local	_ZL28precalc_xorwow_offset_matrix
	.comm	_ZL28precalc_xorwow_offset_matrix,102400,32
	.local	_ZL21precalc_xorwow_matrix
	.comm	_ZL21precalc_xorwow_matrix,102400,32
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC2:
	.long	0
	.long	1087604736
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <stdlib.h>
#include <time.h>


#include <hip/hip_runtime.h>
#include <hiprand/hiprand_kernel.h>

#define N        100		// total number of items in vectors
#define nthreads 4	   // total number of threads in a block



__global__ void estimatepi(int n, int *sum)

{
	__shared__ int counter[nthreads];
	int threadID;
	threadID = blockIdx.x * blockDim.x + threadIdx.x;
	unsigned int seed = threadID;
	hiprandState s;
	hiprand_init(seed, 0, 0, &s);
	if(threadID < n){
		double x, y, diff, angle;
		int t;
		counter[threadIdx.x] = 0;
		for (t = 0; t<n; t++){
			x = hiprand_uniform(&s); //curand
			y = hiprand_uniform(&s); //curand
			while(x*x + y*y > 1){
				x = hiprand_uniform(&s); //curand
				y = hiprand_uniform(&s); //rand
			}

			angle = atan2 ( y, x ); //use inverse tan;
			diff = hiprand_uniform(&s);
			if(diff <= sin (angle) *2){
				counter[threadIdx.x] = counter[threadIdx.x] + 1;
			}
		}

		if(threadIdx.x == 0){
			sum[blockIdx.x] = 0;
			for(int i=0; i<nthreads; i++)	{
				sum[blockIdx.x] = sum[blockIdx.x] + counter[i];
			}
		}
	}
}

int main()
{	
		
		srand(time(NULL));	
		int  *sum_h;
		int *sum_d;
		
	
		sum_h   = (int*)malloc( N* sizeof(int));
	
		hipMalloc((void**)&sum_d,   N * sizeof(int));


	
		int nblocks = (N + nthreads - 1)/nthreads; 
		estimatepi<<<nblocks,nthreads>>>(N,sum_d);

    
   		hipMemcpy(sum_h, sum_d, N * sizeof(int), hipMemcpyDeviceToHost);

	 
		int success = 0;
		for(int i = 0; i < nblocks; i++){
		success = sum_h[i] + success; 
}
		printf("trials === %d", N * nblocks * nthreads );		
		printf("  success === %d\n", success);
		double  pi_estimate = 2 * N * nthreads * nblocks/( double )success;
		printf("pi_estimate == %f", pi_estimate);
		

		printf("\n");
		hipFree(sum_d);
		free(sum_h);
}
 	
	.text
	.file	"buffon.hip"
	.globl	_Z25__device_stub__estimatepiiPi # -- Begin function _Z25__device_stub__estimatepiiPi
	.type	_Z25__device_stub__estimatepiiPi,@function
_Z25__device_stub__estimatepiiPi:       # @_Z25__device_stub__estimatepiiPi
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$80, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	4(%rsp), %rax
	movl	%edi, (%rax)
	leaq	24(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10estimatepiiPi, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$96, %rsp
	.cfi_adjust_cfa_offset -96
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z25__device_stub__estimatepiiPi, .Lfunc_end0-_Z25__device_stub__estimatepiiPi
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0                          # -- Begin function main
.LCPI1_0:
	.quad	0x40d3880000000000              # double 2.0E+4
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%r14
	.cfi_def_cfa_offset 16
	pushq	%rbx
	.cfi_def_cfa_offset 24
	pushq	%rax
	.cfi_def_cfa_offset 32
	.cfi_offset %rbx, -24
	.cfi_offset %r14, -16
	xorl	%r14d, %r14d
	xorl	%edi, %edi
	callq	time
	movl	%eax, %edi
	callq	srand
	movl	$400, %edi                      # imm = 0x190
	callq	malloc
	movq	%rax, %rbx
	movq	%rsp, %rdi
	movl	$400, %esi                      # imm = 0x190
	callq	hipMalloc
	movabsq	$4294967300, %rdx               # imm = 0x100000004
	leaq	21(%rdx), %rdi
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_2
# %bb.1:
	movq	(%rsp), %rsi
	movl	$100, %edi
	callq	_Z25__device_stub__estimatepiiPi
.LBB1_2:
	movq	(%rsp), %rsi
	movl	$400, %edx                      # imm = 0x190
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	xorl	%eax, %eax
.LBB1_3:                                # =>This Inner Loop Header: Depth=1
	addl	(%rbx,%rax,4), %r14d
	incq	%rax
	cmpq	$25, %rax
	jne	.LBB1_3
# %bb.4:
	movl	$.L.str, %edi
	movl	$10000, %esi                    # imm = 0x2710
	xorl	%eax, %eax
	callq	printf
	movl	$.L.str.1, %edi
	movl	%r14d, %esi
	xorl	%eax, %eax
	callq	printf
	cvtsi2sd	%r14d, %xmm1
	movsd	.LCPI1_0(%rip), %xmm0           # xmm0 = mem[0],zero
	divsd	%xmm1, %xmm0
	movl	$.L.str.2, %edi
	movb	$1, %al
	callq	printf
	movl	$10, %edi
	callq	putchar@PLT
	movq	(%rsp), %rdi
	callq	hipFree
	movq	%rbx, %rdi
	callq	free
	xorl	%eax, %eax
	addq	$8, %rsp
	.cfi_def_cfa_offset 24
	popq	%rbx
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10estimatepiiPi, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z10estimatepiiPi,@object       # @_Z10estimatepiiPi
	.section	.rodata,"a",@progbits
	.globl	_Z10estimatepiiPi
	.p2align	3, 0x0
_Z10estimatepiiPi:
	.quad	_Z25__device_stub__estimatepiiPi
	.size	_Z10estimatepiiPi, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"trials === %d"
	.size	.L.str, 14

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"  success === %d\n"
	.size	.L.str.1, 18

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"pi_estimate == %f"
	.size	.L.str.2, 18

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z10estimatepiiPi"
	.size	.L__unnamed_1, 18

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub__estimatepiiPi
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z10estimatepiiPi
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z10estimatepiiPi       ; -- Begin function _Z10estimatepiiPi
	.globl	_Z10estimatepiiPi
	.p2align	8
	.type	_Z10estimatepiiPi,@function
_Z10estimatepiiPi:                      ; @_Z10estimatepiiPi
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x1c
	s_load_b32 s7, s[0:1], 0x0
	s_mov_b32 s6, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[2:3], null, s6, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s7, v2
	s_cbranch_execz .LBB0_18
; %bb.1:
	v_lshlrev_b32_e32 v9, 2, v0
	v_mov_b32_e32 v1, 0
	s_cmp_lt_i32 s7, 1
	ds_store_b32 v9, v1
	s_cbranch_scc1 .LBB0_14
; %bb.2:                                ; %.lr.ph81.preheader
	v_xor_b32_e32 v2, 0x2c7f967f, v2
	v_mov_b32_e32 v11, 0x8f14727c
	v_dual_mov_b32 v10, 0xa96f9d04 :: v_dual_mov_b32 v15, 0
	v_mov_b32_e32 v12, 0x7f3321d2
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_lo_u32 v2, 0x493c4aa1, v2
	v_mov_b32_e32 v13, 0x4002d97c
	s_mov_b32 s8, 0xbd3237f4
	s_mov_b32 s10, 0xb5e68a13
	s_mov_b32 s12, 0x69efb384
	s_mov_b32 s14, 0xaf56de9b
	s_mov_b32 s16, 0xa595c56f
	s_mov_b32 s18, 0xa57d9582
	v_add_nc_u32_e32 v16, 0x75bcd15, v2
	v_xor_b32_e32 v14, 0x159a55e5, v2
	v_add_nc_u32_e32 v6, 0x583f19, v2
	v_add_nc_u32_e32 v7, 0x8ac25218, v2
	s_mov_b32 s20, 0x5f08b19f
	s_mov_b32 s22, 0xfc27006a
	s_mov_b32 s24, 0x5711927a
	s_mov_b32 s26, 0xe82d3ff0
	s_mov_b32 s28, 0x6ef28734
	s_mov_b32 s30, 0x6a214619
	s_mov_b32 s34, 0x8427b883
	s_mov_b32 s36, 0x8b207f05
	s_mov_b32 s38, 0x57b87036
	s_mov_b32 s40, 0x19378e4f
	s_mov_b32 s42, 0x17e1913c
	s_mov_b32 s44, 0x92376b7d
	s_mov_b32 s46, 0x999952cc
	s_mov_b32 s48, 0x55555523
	s_mov_b32 s50, 0x54442d18
	s_mov_b32 s54, 0x6dc9c883
	s_mov_b32 s56, 0x33145c00
	s_mov_b32 s58, 0x252049c0
	s_mov_b32 s60, 0x9037ab78
	s_mov_b32 s62, 0x46cc5e42
	s_mov_b32 s64, 0xa17f65f6
	s_mov_b32 s66, 0x19f4ec90
	s_mov_b32 s68, 0x16c16967
	s_mov_b32 s70, 0x55555555
	s_mov_b32 s72, 0xb42fdfa7
	s_mov_b32 s74, 0xf9a43bb8
	s_mov_b32 s76, 0x796cde01
	s_mov_b32 s78, 0x19e83e5c
	s_mov_b32 s80, 0x11110bb3
	s_mov_b32 s33, 0
	s_mov_b32 s9, 0xbf23e260
	s_mov_b32 s11, 0x3eeba404
	s_mov_b32 s13, 0x3f4b2bb0
	s_mov_b32 s15, 0xbf67952d
	s_mov_b32 s17, 0x3f7d6d43
	s_mov_b32 s19, 0xbf8c6ea4
	s_mov_b32 s21, 0x3f967e29
	s_mov_b32 s23, 0xbf9e9ae6
	s_mov_b32 s25, 0x3fa2c15b
	s_mov_b32 s27, 0xbfa59976
	s_mov_b32 s29, 0x3fa82d5d
	s_mov_b32 s31, 0xbfaae5ce
	s_mov_b32 s35, 0x3fae1bb4
	s_mov_b32 s37, 0xbfb110e4
	s_mov_b32 s39, 0x3fb3b136
	s_mov_b32 s41, 0xbfb745d1
	s_mov_b32 s43, 0x3fbc71c7
	s_mov_b32 s45, 0xbfc24924
	s_mov_b32 s47, 0x3fc99999
	s_mov_b32 s49, 0xbfd55555
	s_mov_b32 s51, 0x3ff921fb
	s_mov_b32 s5, 0x400921fb
	s_mov_b32 s53, 0x3c91a626
	s_mov_b32 s55, 0x3fe45f30
	s_mov_b32 s57, 0xbc91a626
	s_mov_b32 s59, 0xb97b839a
	s_mov_b32 s61, 0x3e21eeb6
	s_mov_b32 s63, 0xbda907db
	s_mov_b32 s65, 0xbe927e4f
	s_mov_b32 s67, 0x3efa01a0
	s_mov_b32 s69, 0xbf56c16c
	s_mov_b32 s71, 0x3fa55555
	s_mov_b32 s73, 0xbe5ae600
	s_mov_b32 s75, 0x3de5e0b2
	s_mov_b32 s77, 0x3ec71de3
	s_mov_b32 s79, 0xbf2a01a0
	s_mov_b32 s81, 0x3f811111
	s_mov_b32 s82, 0x33145c07
	s_mov_b32 s85, 0xbff921fb
	s_mov_b32 s87, 0xbfc55555
.LBB0_3:                                ; %.lr.ph81
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_5 Depth 2
	v_lshrrev_b32_e32 v2, 2, v16
	v_lshlrev_b32_e32 v3, 4, v6
	v_add_nc_u32_e32 v17, 0xb0f8a, v7
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v2, v2, v16
	v_lshlrev_b32_e32 v4, 1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v3, v4, v3
	v_lshrrev_b32_e32 v4, 2, v14
	v_xor3_b32 v20, v3, v2, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v4, v4, v14
	v_add3_u32 v2, v7, v20, 0x587c5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v14, 1, v4
	v_lshlrev_b32_e32 v5, 4, v20
	v_cvt_f32_u32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v5, v14, v5
	v_fmaak_f32 v8, 0x2f800000, v2, 0x2f800000
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor3_b32 v21, v5, v4, v20
	v_cvt_f64_f32_e32 v[2:3], v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, v21, v17
	v_cvt_f32_u32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v19, 0x2f800000, v4, 0x2f800000
	v_cvt_f64_f32_e32 v[4:5], v19
	v_mul_f64 v[22:23], v[2:3], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[22:23], v[4:5], v[4:5], v[22:23]
	v_cmpx_lt_f64_e32 1.0, v[22:23]
	s_cbranch_execz .LBB0_7
; %bb.4:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB0_3 Depth=1
	v_add_nc_u32_e32 v14, 0x161f14, v7
	s_mov_b32 s3, 0
.LBB0_5:                                ; %.lr.ph
                                        ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_mov_b32_e32 v2, v10
	v_dual_mov_b32 v10, v6 :: v_dual_mov_b32 v7, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v6, v21 :: v_dual_mov_b32 v17, v14
	v_lshrrev_b32_e32 v3, 2, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v14, 0xb0f8a, v17
	v_xor_b32_e32 v2, v3, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v3, 4, v6
	v_lshlrev_b32_e32 v4, 1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v3, v4, v3
	v_lshrrev_b32_e32 v4, 2, v11
	v_xor3_b32 v20, v3, v2, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v4, v4, v11
	v_add3_u32 v2, v17, v20, 0xfffa783b
	v_lshlrev_b32_e32 v11, 4, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v5, 1, v4
	v_cvt_f32_u32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v5, v5, v11
	v_dual_mov_b32 v11, v7 :: v_dual_fmaak_f32 v8, 0x2f800000, v2, 0x2f800000
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor3_b32 v21, v5, v4, v20
	v_cvt_f64_f32_e32 v[2:3], v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, v17, v21
	v_cvt_f32_u32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v19, 0x2f800000, v4, 0x2f800000
	v_cvt_f64_f32_e32 v[4:5], v19
	v_mul_f64 v[22:23], v[2:3], v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[22:23], v[4:5], v[4:5], v[22:23]
	v_cmp_nlt_f64_e32 vcc_lo, 1.0, v[22:23]
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB0_5
; %bb.6:                                ; %Flow133
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	v_mov_b32_e32 v11, v7
.LBB0_7:                                ; %Flow134
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	v_mov_b32_e32 v14, v6
	v_max_f64 v[4:5], v[4:5], v[4:5]
	v_max_f64 v[6:7], v[2:3], v[2:3]
	v_dual_mov_b32 v16, v11 :: v_dual_mov_b32 v11, v21
	v_mov_b32_e32 v18, v10
	v_mov_b32_e32 v10, v20
	s_mov_b32 s4, s50
	v_ashrrev_i32_e32 v2, 31, v3
	v_cmp_eq_f32_e64 s2, 0, v19
	v_cmp_eq_f32_e64 s3, 0x7f800000, v19
	v_max_f64 v[20:21], v[6:7], v[4:5]
	v_min_f64 v[4:5], v[6:7], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[6:7], null, v[20:21], v[20:21], v[4:5]
	v_div_scale_f64 v[26:27], vcc_lo, v[4:5], v[20:21], v[4:5]
	v_rcp_f64_e32 v[22:23], v[6:7]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[24:25], -v[6:7], v[22:23], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[22:23], v[22:23], v[24:25], v[22:23]
	v_fma_f64 v[24:25], -v[6:7], v[22:23], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[22:23], v[22:23], v[24:25], v[22:23]
	v_mul_f64 v[24:25], v[26:27], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[6:7], -v[6:7], v[24:25], v[26:27]
	v_div_fmas_f64 v[6:7], v[6:7], v[22:23], v[24:25]
	v_cmp_lt_f32_e32 vcc_lo, v8, v19
                                        ; implicit-def: $vgpr19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[4:5], v[6:7], v[20:21], v[4:5]
	v_mul_f64 v[6:7], v[4:5], v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[6:7], s[10:11], s[8:9]
	v_fma_f64 v[20:21], v[6:7], v[20:21], s[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[6:7], v[20:21], s[14:15]
	v_fma_f64 v[20:21], v[6:7], v[20:21], s[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[6:7], v[20:21], s[18:19]
	v_fma_f64 v[20:21], v[6:7], v[20:21], s[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[6:7], v[20:21], s[22:23]
	v_fma_f64 v[20:21], v[6:7], v[20:21], s[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[6:7], v[20:21], s[26:27]
	v_fma_f64 v[20:21], v[6:7], v[20:21], s[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[6:7], v[20:21], s[30:31]
	v_fma_f64 v[20:21], v[6:7], v[20:21], s[34:35]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[6:7], v[20:21], s[36:37]
	v_fma_f64 v[20:21], v[6:7], v[20:21], s[38:39]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[6:7], v[20:21], s[40:41]
	v_fma_f64 v[20:21], v[6:7], v[20:21], s[42:43]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[6:7], v[20:21], s[44:45]
	v_fma_f64 v[20:21], v[6:7], v[20:21], s[46:47]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[6:7], v[20:21], s[48:49]
	v_mul_f64 v[6:7], v[6:7], v[20:21]
	v_and_b32_e32 v20, 0x400921fb, v2
	v_and_b32_e32 v2, 0x54442d18, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
	v_add_f64 v[6:7], -v[4:5], s[50:51]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v5, v5, v7 :: v_dual_cndmask_b32 v4, v4, v6
	v_cmp_gt_i32_e32 vcc_lo, 0, v3
	v_add_f64 v[6:7], -v[4:5], s[4:5]
	v_cmp_eq_f32_e64 s4, 0x7f800000, v8
	v_cndmask_b32_e32 v3, 0x54442d18, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_cndmask_b32 v5, v5, v7 :: v_dual_cndmask_b32 v4, v4, v6
	v_cndmask_b32_e32 v6, 0x3fe921fb, v13, vcc_lo
	s_and_b32 vcc_lo, s3, s4
	s_mov_b32 s3, exec_lo
                                        ; implicit-def: $vgpr7_vgpr8
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v2, v4, v2, s2
	v_cndmask_b32_e64 v4, v5, v20, s2
	v_dual_cndmask_b32 v3, v2, v3 :: v_dual_cndmask_b32 v4, v4, v6
                                        ; implicit-def: $vgpr5_vgpr6
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ngt_f64_e64 0x41d00000, |v[3:4]|
	s_xor_b32 s3, exec_lo, s3
	s_cbranch_execz .LBB0_9
; %bb.8:                                ;   in Loop: Header=BB0_3 Depth=1
	v_ldexp_f64 v[5:6], |v[3:4]|, 0xffffff80
	v_cmp_le_f64_e64 vcc_lo, 0x7b000000, |v[3:4]|
	v_trig_preop_f64 v[7:8], |v[3:4]|, 0
	v_and_b32_e32 v2, 0x7fffffff, v4
	v_trig_preop_f64 v[19:20], |v[3:4]|, 1
	v_trig_preop_f64 v[29:30], |v[3:4]|, 2
	s_mov_b32 s83, s53
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v5, v3, v5 :: v_dual_cndmask_b32 v6, v2, v6
	v_mul_f64 v[21:22], v[7:8], v[5:6]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[23:24], v[19:20], v[5:6]
	v_fma_f64 v[7:8], v[7:8], v[5:6], -v[21:22]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[19:20], v[19:20], v[5:6], -v[23:24]
	v_add_f64 v[25:26], v[23:24], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[27:28], v[25:26], -v[23:24]
	v_add_f64 v[33:34], v[21:22], v[25:26]
	v_add_f64 v[31:32], v[25:26], -v[27:28]
	v_add_f64 v[7:8], v[7:8], -v[27:28]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_ldexp_f64 v[27:28], v[33:34], -2
	v_add_f64 v[21:22], v[33:34], -v[21:22]
	v_add_f64 v[23:24], v[23:24], -v[31:32]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_neq_f64_e64 vcc_lo, 0x7ff00000, |v[27:28]|
	v_add_f64 v[21:22], v[25:26], -v[21:22]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[7:8], v[7:8], v[23:24]
	v_fract_f64_e32 v[23:24], v[27:28]
	v_cndmask_b32_e32 v23, 0, v23, vcc_lo
	v_mul_f64 v[35:36], v[29:30], v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v24, 0, v24, vcc_lo
	v_ldexp_f64 v[23:24], v[23:24], 2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[31:32], v[35:36], v[19:20]
	v_fma_f64 v[5:6], v[29:30], v[5:6], -v[35:36]
	v_add_f64 v[25:26], v[31:32], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[27:28], v[21:22], v[25:26]
	v_add_f64 v[37:38], v[25:26], -v[31:32]
	v_add_f64 v[33:34], v[27:28], v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_f64 v[43:44], v[25:26], -v[37:38]
	v_add_f64 v[7:8], v[7:8], -v[37:38]
	v_add_f64 v[21:22], v[27:28], -v[21:22]
	v_cmp_gt_f64_e32 vcc_lo, 0, v[33:34]
	v_add_f64 v[33:34], v[31:32], -v[35:36]
	v_cndmask_b32_e64 v2, 0, 0x40100000, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_f64 v[41:42], v[31:32], -v[33:34]
	v_add_f64 v[19:20], v[19:20], -v[33:34]
	v_add_f64 v[31:32], v[31:32], -v[43:44]
	v_add_f64 v[23:24], v[23:24], v[1:2]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[33:34], v[35:36], -v[41:42]
	v_add_f64 v[7:8], v[7:8], v[31:32]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[39:40], v[27:28], v[23:24]
	v_add_f64 v[19:20], v[19:20], v[33:34]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f64_e32 v2, v[39:40]
	v_add_f64 v[7:8], v[19:20], v[7:8]
	v_add_f64 v[19:20], v[25:26], -v[21:22]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f64_i32_e32 v[37:38], v2
	v_add_f64 v[5:6], v[5:6], v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[23:24], v[23:24], -v[37:38]
	v_add_f64 v[5:6], v[19:20], v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[29:30], v[27:28], v[23:24]
	v_add_f64 v[7:8], v[29:30], -v[23:24]
	v_cmp_le_f64_e32 vcc_lo, 0.5, v[29:30]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f64 v[7:8], v[27:28], -v[7:8]
	v_add_co_ci_u32_e64 v19, s2, 0, v2, vcc_lo
	v_cndmask_b32_e64 v2, 0, 0x3ff00000, vcc_lo
	v_add_f64 v[5:6], v[5:6], v[7:8]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[7:8], v[29:30], -v[1:2]
	v_add_f64 v[20:21], v[7:8], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f64 v[22:23], v[20:21], s[50:51]
	v_add_f64 v[7:8], v[20:21], -v[7:8]
	v_fma_f64 v[24:25], v[20:21], s[50:51], -v[22:23]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[5:6], v[5:6], -v[7:8]
	v_fma_f64 v[7:8], v[20:21], s[82:83], v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[7:8], v[5:6], s[50:51], v[7:8]
	v_add_f64 v[5:6], v[22:23], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[20:21], v[5:6], -v[22:23]
	v_add_f64 v[7:8], v[7:8], -v[20:21]
.LBB0_9:                                ; %Flow132
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_and_not1_saveexec_b32 s2, s3
	s_cbranch_execz .LBB0_11
; %bb.10:                               ;   in Loop: Header=BB0_3 Depth=1
	v_mul_f64 v[5:6], |v[3:4]|, s[54:55]
	s_mov_b32 s84, s50
	s_mov_b32 s52, s56
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f64_e32 v[19:20], v[5:6]
	v_fma_f64 v[5:6], v[19:20], s[84:85], |v[3:4]|
	v_mul_f64 v[7:8], v[19:20], s[56:57]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[23:24], v[19:20], s[56:57], v[5:6]
	v_add_f64 v[21:22], v[5:6], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[5:6], v[5:6], -v[21:22]
	v_add_f64 v[21:22], v[21:22], -v[23:24]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f64 v[5:6], v[5:6], v[7:8]
	v_fma_f64 v[7:8], v[19:20], s[52:53], v[7:8]
	v_add_f64 v[5:6], v[21:22], v[5:6]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[5:6], v[5:6], -v[7:8]
	v_fma_f64 v[7:8], v[19:20], s[58:59], v[5:6]
	v_cvt_i32_f64_e32 v19, v[19:20]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[5:6], v[23:24], v[7:8]
	v_add_f64 v[21:22], v[5:6], -v[23:24]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[7:8], v[7:8], -v[21:22]
.LBB0_11:                               ; %_ZL3sind.exit
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	v_mul_f64 v[20:21], v[5:6], v[5:6]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_mul_f64 v[30:31], v[7:8], 0.5
	s_mov_b32 s86, s70
	v_cmp_class_f64_e64 s2, v[3:4], 0x1f8
	v_and_b32_e32 v4, 0x7fffffff, v4
	v_fma_f64 v[22:23], v[20:21], s[74:75], s[72:73]
	v_fma_f64 v[24:25], v[20:21], s[62:63], s[60:61]
	v_mul_f64 v[26:27], v[20:21], 0.5
	v_mul_f64 v[32:33], v[5:6], -v[20:21]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[22:23], v[20:21], v[22:23], s[76:77]
	v_fma_f64 v[24:25], v[20:21], v[24:25], s[64:65]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[28:29], -v[26:27], 1.0
	v_fma_f64 v[22:23], v[20:21], v[22:23], s[78:79]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[24:25], v[20:21], v[24:25], s[66:67]
	v_add_f64 v[34:35], -v[28:29], 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f64 v[22:23], v[20:21], v[22:23], s[80:81]
	v_fma_f64 v[24:25], v[20:21], v[24:25], s[68:69]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[26:27], v[34:35], -v[26:27]
	v_fma_f64 v[22:23], v[32:33], v[22:23], v[30:31]
	v_mul_f64 v[30:31], v[20:21], v[20:21]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f64 v[24:25], v[20:21], v[24:25], s[70:71]
	v_fma_f64 v[26:27], v[5:6], -v[7:8], v[26:27]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[7:8], v[20:21], v[22:23], -v[7:8]
	v_fma_f64 v[20:21], v[30:31], v[24:25], v[26:27]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f64 v[7:8], v[32:33], s[86:87], v[7:8]
	v_add_f64 v[20:21], v[28:29], v[20:21]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_f64 v[7:8], v[5:6], -v[7:8]
	v_lshrrev_b32_e32 v5, 2, v18
	v_and_b32_e32 v2, 1, v19
	v_xor_b32_e32 v3, v5, v18
	v_lshlrev_b32_e32 v5, 4, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cmp_eq_u32_e32 vcc_lo, 0, v2
	v_lshlrev_b32_e32 v18, 30, v19
	v_lshlrev_b32_e32 v6, 1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v5, v6, v5
	v_xor3_b32 v6, v5, v3, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v3, v18, v4
	v_and_b32_e32 v3, 0x80000000, v3
	v_dual_cndmask_b32 v2, v20, v7 :: v_dual_add_nc_u32 v7, 0x587c5, v17
	v_cndmask_b32_e32 v5, v21, v8, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v2, 0, v2, s2
	v_add_nc_u32_e32 v4, v6, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v3, v5, v3
	v_cvt_f32_u32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v3, 0x7ff80000, v3, s2
	s_mov_b32 s2, exec_lo
	v_fmaak_f32 v4, 0x2f800000, v4, 0x2f800000
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f64 v[2:3], v[2:3], v[2:3]
	v_cvt_f64_f32_e32 v[4:5], v4
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ge_f64_e32 v[2:3], v[4:5]
	s_cbranch_execz .LBB0_13
; %bb.12:                               ;   in Loop: Header=BB0_3 Depth=1
	v_add_nc_u32_e32 v15, 1, v15
	ds_store_b32 v9, v15
.LBB0_13:                               ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_add_i32 s33, s33, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s33, s7
	s_cbranch_scc1 .LBB0_3
.LBB0_14:                               ; %._crit_edge82
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	s_mov_b32 s2, 0
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_18
; %bb.15:
	v_mov_b32_e32 v0, 0
.LBB0_16:                               ; =>This Inner Loop Header: Depth=1
	v_mov_b32_e32 v1, s2
	s_add_i32 s2, s2, 4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s2, 16
	ds_load_b32 v1, v1
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v0, v1, v0
	s_cbranch_scc1 .LBB0_16
; %bb.17:                               ; %.loopexit
	s_load_b64 s[0:1], s[0:1], 0x8
	s_mov_b32 s7, 0
	v_mov_b32_e32 v1, 0
	s_lshl_b64 s[2:3], s[6:7], 2
	s_waitcnt lgkmcnt(0)
	s_add_u32 s0, s0, s2
	s_addc_u32 s1, s1, s3
	global_store_b32 v1, v0, s[0:1]
.LBB0_18:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10estimatepiiPi
		.amdhsa_group_segment_fixed_size 16
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 45
		.amdhsa_next_free_sgpr 88
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z10estimatepiiPi, .Lfunc_end0-_Z10estimatepiiPi
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3164
; NumSgprs: 90
; NumVgprs: 45
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 16 bytes/workgroup (compile time only)
; SGPRBlocks: 11
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 90
; NumVGPRsForWavesPerEU: 45
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 16
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10estimatepiiPi
    .private_segment_fixed_size: 0
    .sgpr_count:     90
    .sgpr_spill_count: 0
    .symbol:         _Z10estimatepiiPi.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     45
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
