/// Convolution 1D Parallel.
///
/// Implementation of a 1-dimensional convolution in CUDA, with a placeholding
/// mask and shared memory usage.
///
/// Authors:
///     Lucas Oliveira David.
///     Paulo Finardi.
///
/// Note (in Brazilian Portuguese):
/// Como nosso trabalho final e' relacionado `a redes convolucionais,
/// possuindo um operador convolucao implementado em CUDA, ambos os alunos
/// fizeram esta ultima tarefa juntos.
///
/// ___________________________________________________________________________
/// |                            Performance Analysis                         |
/// ___________________________________________________________________________
/// | input   | CPU_Serial  | GPU_NOShared | GPU_Shared | Speedup (CPU/GPUSM) |
/// ___________________________________________________________________________
/// | arq1.in |  0.080165   |  0.110547    | 0.104868   | 0.7644371972384331  |
/// ___________________________________________________________________________
/// | arq2.in |  9.934354   |  8.289333    | 8.235395   | 1.2062996371151598  |
/// ___________________________________________________________________________
/// | arq3.in |  100.419526 |  96.001373   | 91.386422  | 1.0988451435378443  |
/// ___________________________________________________________________________
///
/// License: MIT (c) 2016
///

#include<stdio.h>
#include<stdlib.h>
#include<cuda.h>
#include <math.h>
#include<cuda_runtime_api.h>

#define MASK_WIDTH     101
#define OUT_TILE_WIDTH 512


__global__ void _k_conv1d(int *N, int *M, int *out, int n)
{
    __shared__ int mask_s[MASK_WIDTH];
    __shared__ int N_s[OUT_TILE_WIDTH + MASK_WIDTH - 1];

    int i_out    = blockIdx.x*OUT_TILE_WIDTH + threadIdx.x,
        i_in     = i_out - (MASK_WIDTH -1) / 2,
        i_shared = threadIdx.x;

    while (i_shared < OUT_TILE_WIDTH + MASK_WIDTH -1)
    {
        // Loads N into the shared memory.
        if (i_in > -1 && i_in < n)
            N_s[i_shared] = N[i_in];
        else
            N_s[i_shared] = 0;

        i_in += OUT_TILE_WIDTH;
        i_shared += OUT_TILE_WIDTH;
    }

    i_shared = threadIdx.x;
    while (i_shared < MASK_WIDTH)
    {
        mask_s[i_shared] = M[i_shared];
        i_shared += OUT_TILE_WIDTH;
    }

    __syncthreads();

    if (i_out < n)
    {
        int output = 0;
        for(int j = 0; j < MASK_WIDTH; j++)
            output += N_s[threadIdx.x + j] * mask_s[j];

         out[i_out] = output;
    }
}

int main()
{
    int n;
    scanf("%d",&n);
    int size = n*sizeof(int);

    int *input  = (int *)malloc(size);
    int *mask   = (int *)malloc(sizeof(int)*MASK_WIDTH);
    int *output = (int *)malloc(size);

    int *d_input;
    int *d_mask;
    int *d_output;

    cudaMalloc((void **)&d_input, size);
    cudaMalloc((void **)&d_mask, sizeof(int)*MASK_WIDTH);
    cudaMalloc((void **)&d_output, size);

    for(int i = 0; i < n; i++)
    scanf("%d", &input[i]);

    for(int i = 0; i < MASK_WIDTH; i++)
    mask[i] = i;

    cudaMemcpy(d_input, input, size, cudaMemcpyHostToDevice);
    cudaMemcpy(d_mask, mask, sizeof(int)*MASK_WIDTH, cudaMemcpyHostToDevice);

    dim3 dimGrid((n-1) / OUT_TILE_WIDTH + 1, 1, 1);
    dim3 dimBlock(OUT_TILE_WIDTH, 1, 1);
    _k_conv1d<<<dimGrid, dimBlock>>>(d_input, d_mask, d_output, n);
    cudaDeviceSynchronize();
    cudaMemcpy(output, d_output, size, cudaMemcpyDeviceToHost);

    for(int i = 0; i < n; i++)
    printf("%d ", output[i]);
    printf("\n");

    cudaFree(d_input);
    cudaFree(d_mask);
    free(input);
    free(output);
    free(mask);

    return 0;
}

	.file	"tmpxft_0030011f_00000000-6_convolution1D_parallel.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2030:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2030:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z33__device_stub__Z9_k_conv1dPiS_S_iPiS_S_i
	.type	_Z33__device_stub__Z9_k_conv1dPiS_S_iPiS_S_i, @function
_Z33__device_stub__Z9_k_conv1dPiS_S_iPiS_S_i:
.LFB2052:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z9_k_conv1dPiS_S_i(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L2:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2052:
	.size	_Z33__device_stub__Z9_k_conv1dPiS_S_iPiS_S_i, .-_Z33__device_stub__Z9_k_conv1dPiS_S_iPiS_S_i
	.globl	_Z9_k_conv1dPiS_S_i
	.type	_Z9_k_conv1dPiS_S_i, @function
_Z9_k_conv1dPiS_S_i:
.LFB2053:
	.cfi_startproc
	endbr64
	jmp	_Z33__device_stub__Z9_k_conv1dPiS_S_iPiS_S_i
	.cfi_endproc
.LFE2053:
	.size	_Z9_k_conv1dPiS_S_i, .-_Z9_k_conv1dPiS_S_i
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"%d"
.LC1:
	.string	"%d "
.LC2:
	.string	"\n"
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	leaq	.LC0(%rip), %rdi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	xorl	%r14d, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	leaq	4(%rsp), %rsi
	call	__isoc23_scanf@PLT
	movl	4(%rsp), %eax
	leal	0(,%rax,4), %ebx
	movslq	%ebx, %rbx
	movq	%rbx, %rdi
	call	malloc@PLT
	movl	$404, %edi
	movq	%rax, %r13
	call	malloc@PLT
	movq	%rbx, %rdi
	movq	%r13, %r15
	movq	%rax, %rbp
	call	malloc@PLT
	leaq	8(%rsp), %rdi
	movq	%rbx, %rsi
	movq	%rax, %r12
	call	cudaMalloc@PLT
	leaq	16(%rsp), %rdi
	movl	$404, %esi
	call	cudaMalloc@PLT
	leaq	24(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
.L9:
	cmpl	%r14d, 4(%rsp)
	jle	.L18
	movq	%r15, %rsi
	leaq	.LC0(%rip), %rdi
	xorl	%eax, %eax
	incl	%r14d
	call	__isoc23_scanf@PLT
	addq	$4, %r15
	jmp	.L9
.L18:
	xorl	%eax, %eax
.L11:
	movl	%eax, 0(%rbp,%rax,4)
	incq	%rax
	cmpq	$101, %rax
	jne	.L11
	movq	8(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbx, %rdx
	movq	%r13, %rsi
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdi
	movl	$1, %ecx
	movq	%rbp, %rsi
	movl	$404, %edx
	call	cudaMemcpy@PLT
	movl	4(%rsp), %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	$512, %ecx
	decl	%eax
	cltd
	idivl	%ecx
	movl	$8388609, %edx
	movl	$1, %ecx
	salq	$9, %rdx
	incl	%eax
	movl	%eax, 32(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 36(%rsp)
	movq	32(%rsp), %rdi
	movl	40(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L12
	movl	4(%rsp), %ecx
	movq	24(%rsp), %rdx
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdi
	call	_Z33__device_stub__Z9_k_conv1dPiS_S_iPiS_S_i
.L12:
	call	cudaDeviceSynchronize@PLT
	movq	24(%rsp), %rsi
	movq	%rbx, %rdx
	movq	%r12, %rdi
	movl	$2, %ecx
	xorl	%ebx, %ebx
	leaq	.LC1(%rip), %r14
	call	cudaMemcpy@PLT
.L13:
	cmpl	%ebx, 4(%rsp)
	jle	.L19
	movl	(%r12,%rbx,4), %edx
	movq	%r14, %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	incq	%rbx
	call	__printf_chk@PLT
	jmp	.L13
.L19:
	leaq	.LC2(%rip), %rsi
	movl	$2, %edi
	xorl	%eax, %eax
	call	__printf_chk@PLT
	movq	8(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	%r13, %rdi
	call	free@PLT
	movq	%r12, %rdi
	call	free@PLT
	movq	%rbp, %rdi
	call	free@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	xorl	%eax, %eax
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2027:
	.size	main, .-main
	.section	.rodata.str1.1
.LC3:
	.string	"_Z9_k_conv1dPiS_S_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2055:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC3(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z9_k_conv1dPiS_S_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2055:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

/// Convolution 1D Parallel.
///
/// Implementation of a 1-dimensional convolution in CUDA, with a placeholding
/// mask and shared memory usage.
///
/// Authors:
///     Lucas Oliveira David.
///     Paulo Finardi.
///
/// Note (in Brazilian Portuguese):
/// Como nosso trabalho final e' relacionado `a redes convolucionais,
/// possuindo um operador convolucao implementado em CUDA, ambos os alunos
/// fizeram esta ultima tarefa juntos.
///
/// ___________________________________________________________________________
/// |                            Performance Analysis                         |
/// ___________________________________________________________________________
/// | input   | CPU_Serial  | GPU_NOShared | GPU_Shared | Speedup (CPU/GPUSM) |
/// ___________________________________________________________________________
/// | arq1.in |  0.080165   |  0.110547    | 0.104868   | 0.7644371972384331  |
/// ___________________________________________________________________________
/// | arq2.in |  9.934354   |  8.289333    | 8.235395   | 1.2062996371151598  |
/// ___________________________________________________________________________
/// | arq3.in |  100.419526 |  96.001373   | 91.386422  | 1.0988451435378443  |
/// ___________________________________________________________________________
///
/// License: MIT (c) 2016
///

#include<stdio.h>
#include<stdlib.h>
#include<hip/hip_runtime.h>
#include <math.h>
#include<hip/hip_runtime_api.h>

#define MASK_WIDTH     101
#define OUT_TILE_WIDTH 512


__global__ void _k_conv1d(int *N, int *M, int *out, int n)
{
    __shared__ int mask_s[MASK_WIDTH];
    __shared__ int N_s[OUT_TILE_WIDTH + MASK_WIDTH - 1];

    int i_out    = blockIdx.x*OUT_TILE_WIDTH + threadIdx.x,
        i_in     = i_out - (MASK_WIDTH -1) / 2,
        i_shared = threadIdx.x;

    while (i_shared < OUT_TILE_WIDTH + MASK_WIDTH -1)
    {
        // Loads N into the shared memory.
        if (i_in > -1 && i_in < n)
            N_s[i_shared] = N[i_in];
        else
            N_s[i_shared] = 0;

        i_in += OUT_TILE_WIDTH;
        i_shared += OUT_TILE_WIDTH;
    }

    i_shared = threadIdx.x;
    while (i_shared < MASK_WIDTH)
    {
        mask_s[i_shared] = M[i_shared];
        i_shared += OUT_TILE_WIDTH;
    }

    __syncthreads();

    if (i_out < n)
    {
        int output = 0;
        for(int j = 0; j < MASK_WIDTH; j++)
            output += N_s[threadIdx.x + j] * mask_s[j];

         out[i_out] = output;
    }
}

int main()
{
    int n;
    scanf("%d",&n);
    int size = n*sizeof(int);

    int *input  = (int *)malloc(size);
    int *mask   = (int *)malloc(sizeof(int)*MASK_WIDTH);
    int *output = (int *)malloc(size);

    int *d_input;
    int *d_mask;
    int *d_output;

    hipMalloc((void **)&d_input, size);
    hipMalloc((void **)&d_mask, sizeof(int)*MASK_WIDTH);
    hipMalloc((void **)&d_output, size);

    for(int i = 0; i < n; i++)
    scanf("%d", &input[i]);

    for(int i = 0; i < MASK_WIDTH; i++)
    mask[i] = i;

    hipMemcpy(d_input, input, size, hipMemcpyHostToDevice);
    hipMemcpy(d_mask, mask, sizeof(int)*MASK_WIDTH, hipMemcpyHostToDevice);

    dim3 dimGrid((n-1) / OUT_TILE_WIDTH + 1, 1, 1);
    dim3 dimBlock(OUT_TILE_WIDTH, 1, 1);
    _k_conv1d<<<dimGrid, dimBlock>>>(d_input, d_mask, d_output, n);
    hipDeviceSynchronize();
    hipMemcpy(output, d_output, size, hipMemcpyDeviceToHost);

    for(int i = 0; i < n; i++)
    printf("%d ", output[i]);
    printf("\n");

    hipFree(d_input);
    hipFree(d_mask);
    free(input);
    free(output);
    free(mask);

    return 0;
}

	.text
	.file	"convolution1D_parallel.hip"
	.globl	_Z24__device_stub___k_conv1dPiS_S_i # -- Begin function _Z24__device_stub___k_conv1dPiS_S_i
	.type	_Z24__device_stub___k_conv1dPiS_S_i,@function
_Z24__device_stub___k_conv1dPiS_S_i:    # @_Z24__device_stub___k_conv1dPiS_S_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z9_k_conv1dPiS_S_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z24__device_stub___k_conv1dPiS_S_i, .Lfunc_end0-_Z24__device_stub___k_conv1dPiS_S_i
	.cfi_endproc
                                        # -- End function
	.globl	main                            # -- Begin function main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	leaq	12(%rsp), %r13
	movl	$.L.str, %edi
	movq	%r13, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	movl	(%r13), %eax
	shll	$2, %eax
	movslq	%eax, %r12
	movq	%r12, %rdi
	callq	malloc
	movq	%rax, %r14
	movl	$404, %edi                      # imm = 0x194
	callq	malloc
	movq	%rax, %rbx
	movq	%r12, %rdi
	callq	malloc
	movq	%rax, %r15
	leaq	24(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	leaq	16(%rsp), %rdi
	movl	$404, %esi                      # imm = 0x194
	callq	hipMalloc
	leaq	32(%rsp), %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	cmpl	$0, (%r13)
	jle	.LBB1_3
# %bb.1:                                # %.lr.ph.preheader
	movq	%r14, %r13
	xorl	%ebp, %ebp
.LBB1_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movl	$.L.str, %edi
	movq	%r13, %rsi
	xorl	%eax, %eax
	callq	__isoc23_scanf
	incq	%rbp
	movslq	12(%rsp), %rax
	addq	$4, %r13
	cmpq	%rax, %rbp
	jl	.LBB1_2
.LBB1_3:                                # %.preheader.preheader
	xorl	%eax, %eax
.LBB1_4:                                # %.preheader
                                        # =>This Inner Loop Header: Depth=1
	movl	%eax, (%rbx,%rax,4)
	incq	%rax
	cmpq	$101, %rax
	jne	.LBB1_4
# %bb.5:
	movq	24(%rsp), %rdi
	movq	%r14, %rsi
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rdi
	movl	$404, %edx                      # imm = 0x194
	movq	%rbx, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	movl	12(%rsp), %edi
	leal	-1(%rdi), %eax
	addl	$510, %edi                      # imm = 0x1FE
	testl	%eax, %eax
	cmovnsl	%eax, %edi
	sarl	$9, %edi
	incl	%edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$512, %rdx                      # imm = 0x200
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_7
# %bb.6:
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	32(%rsp), %rdx
	movl	12(%rsp), %ecx
	callq	_Z24__device_stub___k_conv1dPiS_S_i
.LBB1_7:
	callq	hipDeviceSynchronize
	movq	32(%rsp), %rsi
	movq	%r15, %rdi
	movq	%r12, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	cmpl	$0, 12(%rsp)
	jle	.LBB1_10
# %bb.8:                                # %.lr.ph37.preheader
	xorl	%r12d, %r12d
.LBB1_9:                                # %.lr.ph37
                                        # =>This Inner Loop Header: Depth=1
	movl	(%r15,%r12,4), %esi
	movl	$.L.str.1, %edi
	xorl	%eax, %eax
	callq	printf
	incq	%r12
	movslq	12(%rsp), %rax
	cmpq	%rax, %r12
	jl	.LBB1_9
.LBB1_10:                               # %._crit_edge
	movl	$10, %edi
	callq	putchar@PLT
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	%r14, %rdi
	callq	free
	movq	%r15, %rdi
	callq	free
	movq	%rbx, %rdi
	callq	free
	xorl	%eax, %eax
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	main, .Lfunc_end1-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z9_k_conv1dPiS_S_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z9_k_conv1dPiS_S_i,@object     # @_Z9_k_conv1dPiS_S_i
	.section	.rodata,"a",@progbits
	.globl	_Z9_k_conv1dPiS_S_i
	.p2align	3, 0x0
_Z9_k_conv1dPiS_S_i:
	.quad	_Z24__device_stub___k_conv1dPiS_S_i
	.size	_Z9_k_conv1dPiS_S_i, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"%d"
	.size	.L.str, 3

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"%d "
	.size	.L.str.1, 4

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z9_k_conv1dPiS_S_i"
	.size	.L__unnamed_1, 20

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z24__device_stub___k_conv1dPiS_S_i
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z9_k_conv1dPiS_S_i
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z9_k_conv1dPiS_S_i     ; -- Begin function _Z9_k_conv1dPiS_S_i
	.globl	_Z9_k_conv1dPiS_S_i
	.p2align	8
	.type	_Z9_k_conv1dPiS_S_i,@function
_Z9_k_conv1dPiS_S_i:                    ; @_Z9_k_conv1dPiS_S_i
; %bb.0:
	s_clause 0x2
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	s_load_b32 s1, s[0:1], 0x18
	v_lshlrev_b32_e32 v4, 2, v0
	s_lshl_b32 s8, s15, 9
	s_mov_b32 s9, exec_lo
	v_cmpx_gt_u32_e32 0x264, v0
	s_cbranch_execz .LBB0_5
; %bb.1:                                ; %.lr.ph.preheader
	v_dual_mov_b32 v2, 0 :: v_dual_add_nc_u32 v3, 0xfffffe00, v0
	v_mov_b32_e32 v5, v4
	s_mov_b32 s10, 0
.LBB0_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add3_u32 v1, s8, v3, 0x1ce
	v_mov_b32_e32 v6, 0
	v_cmp_lt_i32_e32 vcc_lo, -1, v1
	s_waitcnt lgkmcnt(0)
	v_cmp_gt_i32_e64 s0, s1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s11, vcc_lo, s0
	s_and_saveexec_b32 s0, s11
	s_cbranch_execz .LBB0_4
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
	v_lshlrev_b64 v[6:7], 2, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, s4, v6
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v7, vcc_lo
	global_load_b32 v6, v[6:7], off
.LBB0_4:                                ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v3, 0x200, v3
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v6
	v_add_nc_u32_e32 v5, 0x800, v5
	v_cmp_lt_u32_e32 vcc_lo, 0x63, v3
	s_or_b32 s10, vcc_lo, s10
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s10
	s_cbranch_execnz .LBB0_2
.LBB0_5:                                ; %Flow57
	s_or_b32 exec_lo, exec_lo, s9
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_u32_e32 0x65, v0
	s_cbranch_execz .LBB0_7
; %bb.6:                                ; %.lr.ph36
	s_waitcnt lgkmcnt(0)
	global_load_b32 v1, v4, s[6:7]
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v1 offset:2448
.LBB0_7:                                ; %._crit_edge
	s_or_b32 exec_lo, exec_lo, s0
	v_add_nc_u32_e32 v0, s8, v0
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	s_mov_b32 s0, exec_lo
	v_cmpx_gt_i32_e64 s1, v0
	s_cbranch_execz .LBB0_11
; %bb.8:                                ; %.preheader.preheader
	v_mov_b32_e32 v1, 0
	s_mov_b32 s0, 0
.LBB0_9:                                ; %.preheader
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v3, s0 :: v_dual_add_nc_u32 v2, s0, v4
	s_add_i32 s0, s0, 4
	ds_load_b32 v5, v2
	ds_load_b32 v6, v3 offset:2448
	s_cmpk_eq_i32 s0, 0x194
	s_waitcnt lgkmcnt(0)
	v_mad_u64_u32 v[2:3], null, v6, v5, v[1:2]
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v1, v2
	s_cbranch_scc0 .LBB0_9
; %bb.10:
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s2, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s3, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB0_11:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z9_k_conv1dPiS_S_i
		.amdhsa_group_segment_fixed_size 2852
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 28
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z9_k_conv1dPiS_S_i, .Lfunc_end0-_Z9_k_conv1dPiS_S_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 420
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 2852 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 2852
    .kernarg_segment_align: 8
    .kernarg_segment_size: 28
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z9_k_conv1dPiS_S_i
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z9_k_conv1dPiS_S_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
