#include <iostream>
#include "mandel.cuh"
#define INTER_LIMIT 255

__device__ int get_inter (thrust::complex<float> c) {
    int i;
    thrust::complex<float> z(0.0, 0.0);

    for (i = 0; i < INTER_LIMIT; ++i) {
        if (thrust::abs(z) > 2 ) {
            break;
        }
        z = thrust::pow(z, 2) + c;
    }
    return i;
}

__global__ void fill_matrix (int *res, const int w, const int h, thrust::complex<float> c0, const float del_y, const float del_x, const int threads, const int blocks, const int offset) {
    thrust::complex<float> del(0, 0);
    unsigned int k = threadIdx.x + blockIdx.x*threads + blocks*threads*offset;
    if (k >= w*h)
        return;
    del.real(del_x * (k%w));
    del.imag(del_y * (k/w));
    res[k] = get_inter(c0 + del);
    return;
}

__host__ void prepare (int *res_matrix, const int w, const int h, thrust::complex<float> c0, const float del_y, const float del_x, const int threads) {
    int *d_res_matrix; 
    int *d_w; 
    int *d_h;
    thrust::complex<float> *d_c0; 
    float *d_del_y; 
    float *d_del_x; 
    
    cudaSetDevice(0);

    if (cudaSuccess != cudaMallocManaged((void **) &d_res_matrix, sizeof(int)*w*h)) {
        std::cerr << "Could not allocate memory";
        exit(EXIT_FAILURE);
    }
    if (cudaSuccess != cudaMallocManaged((void **) &d_w, sizeof(int))) {
        std::cerr << "Could not allocate memory";
        exit(EXIT_FAILURE);
    }
    if (cudaSuccess != cudaMallocManaged((void **) &d_h, sizeof(int))) {
        std::cerr << "Could not allocate memory";
        exit(EXIT_FAILURE);
    }
    if (cudaSuccess != cudaMallocManaged((void **) &d_c0, sizeof(thrust::complex<float>)) ) {
        std::cerr << "Could not allocate memory";
        exit(EXIT_FAILURE);
    }
    if (cudaSuccess != cudaMallocManaged((void **) &d_del_y, sizeof(float))) {
        std::cerr << "Could not allocate memory";
        exit(EXIT_FAILURE);
    }
    if (cudaSuccess != cudaMallocManaged((void **) &d_del_x, sizeof(float))) {
        std::cerr << "Could not allocate memory";
        exit(EXIT_FAILURE);
    }

    if (cudaSuccess != cudaMemcpy(d_w, &w, sizeof(int), cudaMemcpyHostToDevice)) {
        std::cerr << "Could not copy memory";
        exit(EXIT_FAILURE);
    }
    if (cudaSuccess != cudaMemcpy(d_h, &h, sizeof(int), cudaMemcpyHostToDevice)) {
        std::cerr << "Could not copy memory";
        exit(EXIT_FAILURE);
    }
    if (cudaSuccess != cudaMemcpy(d_c0, &c0, sizeof(thrust::complex<float>), cudaMemcpyHostToDevice)) {
        std::cerr << "Could not copy memory";
        exit(EXIT_FAILURE);
    }
    if (cudaSuccess != cudaMemcpy(d_del_y, &del_y, sizeof(float), cudaMemcpyHostToDevice)) {
        std::cerr << "Could not copy memory";
        exit(EXIT_FAILURE);
    }
    if (cudaSuccess != cudaMemcpy(d_del_x, &del_x, sizeof(float), cudaMemcpyHostToDevice)) {
        std::cerr << "Could not copy memory";
        exit(EXIT_FAILURE);
    }
    
    int block = 1024;
    int max = ((w*h) / (threads*block)) + 1;
    for (int i = 0; i < max; ++i) {
        fill_matrix<<<block, threads>>> (d_res_matrix, *d_w, *d_h, *d_c0, *d_del_y, *d_del_x, threads, block, i);
        cudaDeviceSynchronize();
    }
    
    if (cudaSuccess != cudaMemcpy(res_matrix, d_res_matrix, sizeof(int)*w*h, cudaMemcpyDeviceToHost)) {
        std::cerr << "Could not copy memory";
        exit(EXIT_FAILURE);
    }
    return;
}

	.file	"tmpxft_0027d55b_00000000-6_mandel.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB5944:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE5944:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.type	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.isra.0, @function
_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.isra.0:
.LFB6644:
	.cfi_startproc
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	movq	%rdi, %rbx
	subq	$16, %rsp
	.cfi_def_cfa_offset 32
	testq	%rsi, %rsi
	jne	.L3
	movq	(%rdi), %rax
	movl	$1, %esi
	addq	-24(%rax), %rbx
	addq	$16, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	_ZNSt9basic_iosIcSt11char_traitsIcEE8setstateESt12_Ios_Iostate@PLT
.L3:
	.cfi_restore_state
	movq	%rsi, %rdi
	movq	%rsi, 8(%rsp)
	call	strlen@PLT
	movq	8(%rsp), %rsi
	addq	$16, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	movq	%rax, %rdx
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l@PLT
	.cfi_endproc
.LFE6644:
	.size	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.isra.0, .-_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.isra.0
	.globl	_Z9get_interN6thrust20THRUST_200700_890_NS7complexIfEE
	.type	_Z9get_interN6thrust20THRUST_200700_890_NS7complexIfEE, @function
_Z9get_interN6thrust20THRUST_200700_890_NS7complexIfEE:
.LFB5940:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE5940:
	.size	_Z9get_interN6thrust20THRUST_200700_890_NS7complexIfEE, .-_Z9get_interN6thrust20THRUST_200700_890_NS7complexIfEE
	.globl	_Z80__device_stub__Z11fill_matrixPiiiN6thrust20THRUST_200700_890_NS7complexIfEEffiiiPiiiRN6thrust20THRUST_200700_890_NS7complexIfEEffiii
	.type	_Z80__device_stub__Z11fill_matrixPiiiN6thrust20THRUST_200700_890_NS7complexIfEEffiiiPiiiRN6thrust20THRUST_200700_890_NS7complexIfEEffiii, @function
_Z80__device_stub__Z11fill_matrixPiiiN6thrust20THRUST_200700_890_NS7complexIfEEffiiiPiiiRN6thrust20THRUST_200700_890_NS7complexIfEEffiii:
.LFB5966:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	32(%rsp), %rdx
	movl	%r8d, 4(%rsp)
	movl	%r9d, (%rsp)
	movss	%xmm0, 12(%rsp)
	movss	%xmm1, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movq	%rcx, 120(%rsp)
	leaq	40(%rsp), %rcx
	movq	%rax, 96(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 144(%rsp)
	movq	%rsp, %rax
	movq	%rax, 152(%rsp)
	leaq	192(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movl	$1, 56(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	40(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z11fill_matrixPiiiN6thrust20THRUST_200700_890_NS7complexIfEEffiii(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 208
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L8:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE5966:
	.size	_Z80__device_stub__Z11fill_matrixPiiiN6thrust20THRUST_200700_890_NS7complexIfEEffiiiPiiiRN6thrust20THRUST_200700_890_NS7complexIfEEffiii, .-_Z80__device_stub__Z11fill_matrixPiiiN6thrust20THRUST_200700_890_NS7complexIfEEffiiiPiiiRN6thrust20THRUST_200700_890_NS7complexIfEEffiii
	.globl	_Z11fill_matrixPiiiN6thrust20THRUST_200700_890_NS7complexIfEEffiii
	.type	_Z11fill_matrixPiiiN6thrust20THRUST_200700_890_NS7complexIfEEffiii, @function
_Z11fill_matrixPiiiN6thrust20THRUST_200700_890_NS7complexIfEEffiii:
.LFB5967:
	.cfi_startproc
	endbr64
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	%ecx, %eax
	movq	%xmm0, 8(%rsp)
	leaq	8(%rsp), %rcx
	movaps	%xmm1, %xmm0
	movaps	%xmm2, %xmm1
	pushq	%r10
	.cfi_def_cfa_offset 40
	pushq	%r9
	.cfi_def_cfa_offset 48
	movl	%r8d, %r9d
	movl	%eax, %r8d
	call	_Z80__device_stub__Z11fill_matrixPiiiN6thrust20THRUST_200700_890_NS7complexIfEEffiiiPiiiRN6thrust20THRUST_200700_890_NS7complexIfEEffiii
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE5967:
	.size	_Z11fill_matrixPiiiN6thrust20THRUST_200700_890_NS7complexIfEEffiii, .-_Z11fill_matrixPiiiN6thrust20THRUST_200700_890_NS7complexIfEEffiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Could not allocate memory"
.LC1:
	.string	"Could not copy memory"
	.text
	.globl	_Z7preparePiiiN6thrust20THRUST_200700_890_NS7complexIfEEffi
	.type	_Z7preparePiiiN6thrust20THRUST_200700_890_NS7complexIfEEffi, @function
_Z7preparePiiiN6thrust20THRUST_200700_890_NS7complexIfEEffi:
.LFB5941:
	.cfi_startproc
	endbr64
	pushq	%r14
	.cfi_def_cfa_offset 16
	.cfi_offset 14, -16
	pushq	%r13
	.cfi_def_cfa_offset 24
	.cfi_offset 13, -24
	pushq	%r12
	.cfi_def_cfa_offset 32
	.cfi_offset 12, -32
	pushq	%rbp
	.cfi_def_cfa_offset 40
	.cfi_offset 6, -40
	movq	%rdi, %rbp
	xorl	%edi, %edi
	pushq	%rbx
	.cfi_def_cfa_offset 48
	.cfi_offset 3, -48
	movl	%ecx, %ebx
	addq	$-128, %rsp
	.cfi_def_cfa_offset 176
	movl	%esi, 28(%rsp)
	movl	%edx, 24(%rsp)
	movq	%xmm0, 16(%rsp)
	movss	%xmm1, 12(%rsp)
	movss	%xmm2, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	call	cudaSetDevice@PLT
	movslq	28(%rsp), %rsi
	movslq	24(%rsp), %rax
	leaq	40(%rsp), %rdi
	movl	$1, %edx
	imulq	%rax, %rsi
	salq	$2, %rsi
	call	cudaMallocManaged@PLT
	testl	%eax, %eax
	je	.L15
.L16:
	leaq	.LC0(%rip), %rsi
	jmp	.L24
.L15:
	leaq	48(%rsp), %rdi
	movl	$1, %edx
	movl	$4, %esi
	call	cudaMallocManaged@PLT
	testl	%eax, %eax
	jne	.L16
	leaq	56(%rsp), %rdi
	movl	$1, %edx
	movl	$4, %esi
	call	cudaMallocManaged@PLT
	testl	%eax, %eax
	jne	.L16
	leaq	64(%rsp), %rdi
	movl	$1, %edx
	movl	$8, %esi
	call	cudaMallocManaged@PLT
	testl	%eax, %eax
	jne	.L16
	leaq	72(%rsp), %rdi
	movl	$1, %edx
	movl	$4, %esi
	call	cudaMallocManaged@PLT
	testl	%eax, %eax
	jne	.L16
	leaq	80(%rsp), %rdi
	movl	$1, %edx
	movl	$4, %esi
	call	cudaMallocManaged@PLT
	testl	%eax, %eax
	jne	.L16
	movq	48(%rsp), %rdi
	leaq	28(%rsp), %rsi
	movl	$1, %ecx
	movl	$4, %edx
	call	cudaMemcpy@PLT
	testl	%eax, %eax
	je	.L17
.L18:
	leaq	.LC1(%rip), %rsi
.L24:
	leaq	_ZSt4cerr(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.isra.0
	movl	$1, %edi
	call	exit@PLT
.L17:
	movq	56(%rsp), %rdi
	leaq	24(%rsp), %rsi
	movl	$1, %ecx
	movl	$4, %edx
	call	cudaMemcpy@PLT
	testl	%eax, %eax
	jne	.L18
	movq	64(%rsp), %rdi
	leaq	16(%rsp), %rsi
	movl	$1, %ecx
	movl	$8, %edx
	call	cudaMemcpy@PLT
	testl	%eax, %eax
	jne	.L18
	movq	72(%rsp), %rdi
	leaq	12(%rsp), %rsi
	movl	$1, %ecx
	movl	$4, %edx
	call	cudaMemcpy@PLT
	testl	%eax, %eax
	jne	.L18
	movq	80(%rsp), %rdi
	leaq	8(%rsp), %rsi
	movl	$1, %ecx
	movl	$4, %edx
	call	cudaMemcpy@PLT
	testl	%eax, %eax
	jne	.L18
	movl	28(%rsp), %eax
	movl	%ebx, %ecx
	xorl	%r12d, %r12d
	movabsq	$4294967297, %r14
	imull	24(%rsp), %eax
	sall	$10, %ecx
	cltd
	idivl	%ecx
	movl	%eax, %r13d
.L19:
	cmpl	%r12d, %r13d
	jl	.L25
	movq	%r14, 112(%rsp)
	movl	$4194305, %edi
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movl	%ebx, 108(%rsp)
	movl	116(%rsp), %ecx
	salq	$10, %rdi
	movl	$1, %esi
	movq	108(%rsp), %rdx
	movq	%rdi, 96(%rsp)
	movl	$1, 104(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L20
	movq	80(%rsp), %rax
	leaq	88(%rsp), %rcx
	movl	$1024, %r9d
	movl	%ebx, %r8d
	movss	(%rax), %xmm1
	movq	72(%rsp), %rax
	movss	(%rax), %xmm0
	movq	56(%rsp), %rax
	movl	(%rax), %edx
	movq	48(%rsp), %rax
	movl	(%rax), %esi
	movq	64(%rsp), %rax
	movq	(%rax), %rax
	movq	%rax, 88(%rsp)
	pushq	%rax
	.cfi_def_cfa_offset 184
	pushq	%r12
	.cfi_def_cfa_offset 192
	movq	56(%rsp), %rdi
	call	_Z80__device_stub__Z11fill_matrixPiiiN6thrust20THRUST_200700_890_NS7complexIfEEffiiiPiiiRN6thrust20THRUST_200700_890_NS7complexIfEEffiii
	popq	%rdx
	.cfi_def_cfa_offset 184
	popq	%rcx
	.cfi_def_cfa_offset 176
.L20:
	call	cudaDeviceSynchronize@PLT
	incl	%r12d
	jmp	.L19
.L25:
	movslq	28(%rsp), %rdx
	movslq	24(%rsp), %rax
	movl	$2, %ecx
	movq	%rbp, %rdi
	movq	40(%rsp), %rsi
	imulq	%rax, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	testl	%eax, %eax
	jne	.L18
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L22
	call	__stack_chk_fail@PLT
.L22:
	subq	$-128, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%rbp
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r13
	.cfi_def_cfa_offset 16
	popq	%r14
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE5941:
	.size	_Z7preparePiiiN6thrust20THRUST_200700_890_NS7complexIfEEffi, .-_Z7preparePiiiN6thrust20THRUST_200700_890_NS7complexIfEEffi
	.section	.rodata.str1.1
.LC2:
	.string	"_Z11fill_matrixPiiiN6thrust20THRUST_200700_890_NS7complexIfEEffiii"
.LC3:
	.string	"_ZN39_INTERNAL_fcd8a815_9_mandel_cu_dfe59f8e4cuda3std3__45__cpo5beginE"
.LC4:
	.string	"_ZN39_INTERNAL_fcd8a815_9_mandel_cu_dfe59f8e4cuda3std3__45__cpo3endE"
.LC5:
	.string	"_ZN39_INTERNAL_fcd8a815_9_mandel_cu_dfe59f8e4cuda3std3__45__cpo6cbeginE"
.LC6:
	.string	"_ZN39_INTERNAL_fcd8a815_9_mandel_cu_dfe59f8e4cuda3std3__45__cpo4cendE"
.LC7:
	.string	"_ZN39_INTERNAL_fcd8a815_9_mandel_cu_dfe59f8e4cuda3std3__441_GLOBAL__N__fcd8a815_9_mandel_cu_dfe59f8e6ignoreE"
.LC8:
	.string	"_ZN39_INTERNAL_fcd8a815_9_mandel_cu_dfe59f8e4cuda3std3__419piecewise_constructE"
.LC9:
	.string	"_ZN39_INTERNAL_fcd8a815_9_mandel_cu_dfe59f8e4cuda3std3__48in_placeE"
.LC10:
	.string	"_ZN39_INTERNAL_fcd8a815_9_mandel_cu_dfe59f8e4cuda3std6ranges3__45__cpo4swapE"
.LC11:
	.string	"_ZN39_INTERNAL_fcd8a815_9_mandel_cu_dfe59f8e4cuda3std6ranges3__45__cpo9iter_moveE"
.LC12:
	.string	"_ZN39_INTERNAL_fcd8a815_9_mandel_cu_dfe59f8e4cuda3std6ranges3__45__cpo7advanceE"
.LC13:
	.string	"_ZN39_INTERNAL_fcd8a815_9_mandel_cu_dfe59f8e6thrust20THRUST_200700_890_NS6system6detail10sequential3seqE"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB5969:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC2(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z11fill_matrixPiiiN6thrust20THRUST_200700_890_NS7complexIfEEffiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__45__cpo5beginE(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC4(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__45__cpo3endE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC5(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__45__cpo6cbeginE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC6(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__45__cpo4cendE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC7(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__441_GLOBAL__N__fcd8a815_9_mandel_cu_dfe59f8e6ignoreE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC8(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__419piecewise_constructE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC9(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std3__48in_placeE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rcx
	.cfi_def_cfa_offset 24
	popq	%rsi
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC10(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo4swapE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%rdi
	.cfi_def_cfa_offset 24
	popq	%r8
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC11(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo9iter_moveE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r9
	.cfi_def_cfa_offset 24
	popq	%r10
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC12(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN4cuda3std6ranges3__45__cpo7advanceE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	popq	%r11
	.cfi_def_cfa_offset 24
	popq	%rax
	.cfi_def_cfa_offset 16
	pushq	$0
	.cfi_def_cfa_offset 24
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC13(%rip), %rdx
	movq	%rbx, %rdi
	xorl	%r8d, %r8d
	movq	%rdx, %rcx
	movl	$1, %r9d
	leaq	_ZN6thrust20THRUST_200700_890_NS6system6detail10sequentialL3seqE(%rip), %rsi
	call	__cudaRegisterVar@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	popq	%rax
	.cfi_def_cfa_offset 24
	popq	%rdx
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE5969:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata
	.type	_ZN6thrust20THRUST_200700_890_NS6system6detail10sequentialL3seqE, @object
	.size	_ZN6thrust20THRUST_200700_890_NS6system6detail10sequentialL3seqE, 1
_ZN6thrust20THRUST_200700_890_NS6system6detail10sequentialL3seqE:
	.zero	1
	.weak	_ZN4cuda3std6ranges3__45__cpo7advanceE
	.section	.rodata._ZN4cuda3std6ranges3__45__cpo7advanceE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo7advanceE,comdat
	.type	_ZN4cuda3std6ranges3__45__cpo7advanceE, @gnu_unique_object
	.size	_ZN4cuda3std6ranges3__45__cpo7advanceE, 1
_ZN4cuda3std6ranges3__45__cpo7advanceE:
	.zero	1
	.hidden	_ZN4cuda3std3__441_GLOBAL__N__fcd8a815_9_mandel_cu_dfe59f8e6ignoreE
	.weak	_ZN4cuda3std3__441_GLOBAL__N__fcd8a815_9_mandel_cu_dfe59f8e6ignoreE
	.section	.rodata._ZN4cuda3std3__441_GLOBAL__N__fcd8a815_9_mandel_cu_dfe59f8e6ignoreE,"aG",@progbits,_ZN4cuda3std3__441_GLOBAL__N__fcd8a815_9_mandel_cu_dfe59f8e6ignoreE,comdat
	.type	_ZN4cuda3std3__441_GLOBAL__N__fcd8a815_9_mandel_cu_dfe59f8e6ignoreE, @gnu_unique_object
	.size	_ZN4cuda3std3__441_GLOBAL__N__fcd8a815_9_mandel_cu_dfe59f8e6ignoreE, 1
_ZN4cuda3std3__441_GLOBAL__N__fcd8a815_9_mandel_cu_dfe59f8e6ignoreE:
	.zero	1
	.weak	_ZN4cuda3std3__48in_placeE
	.section	.rodata._ZN4cuda3std3__48in_placeE,"aG",@progbits,_ZN4cuda3std3__48in_placeE,comdat
	.type	_ZN4cuda3std3__48in_placeE, @gnu_unique_object
	.size	_ZN4cuda3std3__48in_placeE, 1
_ZN4cuda3std3__48in_placeE:
	.zero	1
	.weak	_ZN4cuda3std3__45__cpo4cendE
	.section	.rodata._ZN4cuda3std3__45__cpo4cendE,"aG",@progbits,_ZN4cuda3std3__45__cpo4cendE,comdat
	.type	_ZN4cuda3std3__45__cpo4cendE, @gnu_unique_object
	.size	_ZN4cuda3std3__45__cpo4cendE, 1
_ZN4cuda3std3__45__cpo4cendE:
	.zero	1
	.weak	_ZN4cuda3std3__45__cpo6cbeginE
	.section	.rodata._ZN4cuda3std3__45__cpo6cbeginE,"aG",@progbits,_ZN4cuda3std3__45__cpo6cbeginE,comdat
	.type	_ZN4cuda3std3__45__cpo6cbeginE, @gnu_unique_object
	.size	_ZN4cuda3std3__45__cpo6cbeginE, 1
_ZN4cuda3std3__45__cpo6cbeginE:
	.zero	1
	.weak	_ZN4cuda3std3__45__cpo3endE
	.section	.rodata._ZN4cuda3std3__45__cpo3endE,"aG",@progbits,_ZN4cuda3std3__45__cpo3endE,comdat
	.type	_ZN4cuda3std3__45__cpo3endE, @gnu_unique_object
	.size	_ZN4cuda3std3__45__cpo3endE, 1
_ZN4cuda3std3__45__cpo3endE:
	.zero	1
	.weak	_ZN4cuda3std3__45__cpo5beginE
	.section	.rodata._ZN4cuda3std3__45__cpo5beginE,"aG",@progbits,_ZN4cuda3std3__45__cpo5beginE,comdat
	.type	_ZN4cuda3std3__45__cpo5beginE, @gnu_unique_object
	.size	_ZN4cuda3std3__45__cpo5beginE, 1
_ZN4cuda3std3__45__cpo5beginE:
	.zero	1
	.weak	_ZN4cuda3std3__419piecewise_constructE
	.section	.rodata._ZN4cuda3std3__419piecewise_constructE,"aG",@progbits,_ZN4cuda3std3__419piecewise_constructE,comdat
	.type	_ZN4cuda3std3__419piecewise_constructE, @gnu_unique_object
	.size	_ZN4cuda3std3__419piecewise_constructE, 1
_ZN4cuda3std3__419piecewise_constructE:
	.zero	1
	.weak	_ZN4cuda3std6ranges3__45__cpo9iter_moveE
	.section	.rodata._ZN4cuda3std6ranges3__45__cpo9iter_moveE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo9iter_moveE,comdat
	.type	_ZN4cuda3std6ranges3__45__cpo9iter_moveE, @gnu_unique_object
	.size	_ZN4cuda3std6ranges3__45__cpo9iter_moveE, 1
_ZN4cuda3std6ranges3__45__cpo9iter_moveE:
	.zero	1
	.weak	_ZN4cuda3std6ranges3__45__cpo4swapE
	.section	.rodata._ZN4cuda3std6ranges3__45__cpo4swapE,"aG",@progbits,_ZN4cuda3std6ranges3__45__cpo4swapE,comdat
	.type	_ZN4cuda3std6ranges3__45__cpo4swapE, @gnu_unique_object
	.size	_ZN4cuda3std6ranges3__45__cpo4swapE, 1
_ZN4cuda3std6ranges3__45__cpo4swapE:
	.zero	1
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <iostream>
#include "mandel.cuh"
#define INTER_LIMIT 255

__device__ int get_inter (thrust::complex<float> c) {
    int i;
    thrust::complex<float> z(0.0, 0.0);

    for (i = 0; i < INTER_LIMIT; ++i) {
        if (thrust::abs(z) > 2 ) {
            break;
        }
        z = thrust::pow(z, 2) + c;
    }
    return i;
}

__global__ void fill_matrix (int *res, const int w, const int h, thrust::complex<float> c0, const float del_y, const float del_x, const int threads, const int blocks, const int offset) {
    thrust::complex<float> del(0, 0);
    unsigned int k = threadIdx.x + blockIdx.x*threads + blocks*threads*offset;
    if (k >= w*h)
        return;
    del.real(del_x * (k%w));
    del.imag(del_y * (k/w));
    res[k] = get_inter(c0 + del);
    return;
}

__host__ void prepare (int *res_matrix, const int w, const int h, thrust::complex<float> c0, const float del_y, const float del_x, const int threads) {
    int *d_res_matrix; 
    int *d_w; 
    int *d_h;
    thrust::complex<float> *d_c0; 
    float *d_del_y; 
    float *d_del_x; 
    
    hipSetDevice(0);

    if (hipSuccess != hipMallocManaged((void **) &d_res_matrix, sizeof(int)*w*h)) {
        std::cerr << "Could not allocate memory";
        exit(EXIT_FAILURE);
    }
    if (hipSuccess != hipMallocManaged((void **) &d_w, sizeof(int))) {
        std::cerr << "Could not allocate memory";
        exit(EXIT_FAILURE);
    }
    if (hipSuccess != hipMallocManaged((void **) &d_h, sizeof(int))) {
        std::cerr << "Could not allocate memory";
        exit(EXIT_FAILURE);
    }
    if (hipSuccess != hipMallocManaged((void **) &d_c0, sizeof(thrust::complex<float>)) ) {
        std::cerr << "Could not allocate memory";
        exit(EXIT_FAILURE);
    }
    if (hipSuccess != hipMallocManaged((void **) &d_del_y, sizeof(float))) {
        std::cerr << "Could not allocate memory";
        exit(EXIT_FAILURE);
    }
    if (hipSuccess != hipMallocManaged((void **) &d_del_x, sizeof(float))) {
        std::cerr << "Could not allocate memory";
        exit(EXIT_FAILURE);
    }

    if (hipSuccess != hipMemcpy(d_w, &w, sizeof(int), hipMemcpyHostToDevice)) {
        std::cerr << "Could not copy memory";
        exit(EXIT_FAILURE);
    }
    if (hipSuccess != hipMemcpy(d_h, &h, sizeof(int), hipMemcpyHostToDevice)) {
        std::cerr << "Could not copy memory";
        exit(EXIT_FAILURE);
    }
    if (hipSuccess != hipMemcpy(d_c0, &c0, sizeof(thrust::complex<float>), hipMemcpyHostToDevice)) {
        std::cerr << "Could not copy memory";
        exit(EXIT_FAILURE);
    }
    if (hipSuccess != hipMemcpy(d_del_y, &del_y, sizeof(float), hipMemcpyHostToDevice)) {
        std::cerr << "Could not copy memory";
        exit(EXIT_FAILURE);
    }
    if (hipSuccess != hipMemcpy(d_del_x, &del_x, sizeof(float), hipMemcpyHostToDevice)) {
        std::cerr << "Could not copy memory";
        exit(EXIT_FAILURE);
    }
    
    int block = 1024;
    int max = ((w*h) / (threads*block)) + 1;
    for (int i = 0; i < max; ++i) {
        fill_matrix<<<block, threads>>> (d_res_matrix, *d_w, *d_h, *d_c0, *d_del_y, *d_del_x, threads, block, i);
        hipDeviceSynchronize();
    }
    
    if (hipSuccess != hipMemcpy(res_matrix, d_res_matrix, sizeof(int)*w*h, hipMemcpyDeviceToHost)) {
        std::cerr << "Could not copy memory";
        exit(EXIT_FAILURE);
    }
    return;
}

	.text
	.file	"mandel.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z26__device_stub__fill_matrixPiiiN6thrust7complexIfEEffiii # -- Begin function _Z26__device_stub__fill_matrixPiiiN6thrust7complexIfEEffiii
	.type	_Z26__device_stub__fill_matrixPiiiN6thrust7complexIfEEffiii,@function
_Z26__device_stub__fill_matrixPiiiN6thrust7complexIfEEffiii: # @_Z26__device_stub__fill_matrixPiiiN6thrust7complexIfEEffiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movlps	%xmm0, (%rax)
	leaq	48(%rsp), %r10
	movq	%rdi, (%r10)
	leaq	28(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	24(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	20(%rsp), %rdx
	movss	%xmm1, (%rdx)
	leaq	16(%rsp), %r11
	movss	%xmm2, (%r11)
	leaq	12(%rsp), %r14
	movl	%ecx, (%r14)
	leaq	8(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	4(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%r10, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rax, 24(%rbx)
	movq	%rdx, 32(%rbx)
	movq	%r11, 40(%rbx)
	movq	%r14, 48(%rbx)
	movq	%rcx, 56(%rbx)
	movq	%r8, 64(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z11fill_matrixPiiiN6thrust7complexIfEEffiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z26__device_stub__fill_matrixPiiiN6thrust7complexIfEEffiii, .Lfunc_end0-_Z26__device_stub__fill_matrixPiiiN6thrust7complexIfEEffiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z7preparePiiiN6thrust7complexIfEEffi # -- Begin function _Z7preparePiiiN6thrust7complexIfEEffi
	.type	_Z7preparePiiiN6thrust7complexIfEEffi,@function
_Z7preparePiiiN6thrust7complexIfEEffi:  # @_Z7preparePiiiN6thrust7complexIfEEffi
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%ecx, %ebp
	movl	%edx, %r14d
	movl	%esi, %r15d
	movq	%rdi, %rbx
	movlps	%xmm0, 64(%rsp)
	movl	%esi, 4(%rsp)
	movl	%edx, (%rsp)
	movss	%xmm1, 12(%rsp)
	movss	%xmm2, 8(%rsp)
	xorl	%edi, %edi
	callq	hipSetDevice
	movslq	%r15d, %rax
	movslq	%r14d, %rsi
	imulq	%rax, %rsi
	shlq	$2, %rsi
	leaq	56(%rsp), %rdi
	movl	$1, %edx
	callq	hipMallocManaged
	testl	%eax, %eax
	jne	.LBB1_1
# %bb.3:
	leaq	48(%rsp), %rdi
	movl	$4, %esi
	movl	$1, %edx
	callq	hipMallocManaged
	testl	%eax, %eax
	jne	.LBB1_1
# %bb.4:
	leaq	40(%rsp), %rdi
	movl	$4, %esi
	movl	$1, %edx
	callq	hipMallocManaged
	testl	%eax, %eax
	jne	.LBB1_1
# %bb.5:
	leaq	32(%rsp), %rdi
	movl	$8, %esi
	movl	$1, %edx
	callq	hipMallocManaged
	testl	%eax, %eax
	jne	.LBB1_1
# %bb.6:
	leaq	24(%rsp), %rdi
	movl	$4, %esi
	movl	$1, %edx
	callq	hipMallocManaged
	testl	%eax, %eax
	jne	.LBB1_1
# %bb.7:
	leaq	16(%rsp), %rdi
	movl	$4, %esi
	movl	$1, %edx
	callq	hipMallocManaged
	testl	%eax, %eax
	jne	.LBB1_1
# %bb.8:
	movq	48(%rsp), %rdi
	leaq	4(%rsp), %rsi
	movl	$4, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB1_9
# %bb.10:
	movq	40(%rsp), %rdi
	movq	%rsp, %rsi
	movl	$4, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB1_9
# %bb.11:
	movq	32(%rsp), %rdi
	leaq	64(%rsp), %rsi
	movl	$8, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB1_9
# %bb.12:
	movq	24(%rsp), %rdi
	leaq	12(%rsp), %rsi
	movl	$4, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB1_9
# %bb.13:
	movq	16(%rsp), %rdi
	leaq	8(%rsp), %rsi
	movl	$4, %edx
	movl	$1, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB1_9
# %bb.14:
	movl	4(%rsp), %ecx
	movl	(%rsp), %edi
	movl	%edi, %eax
	imull	%ecx, %eax
	movl	%ebp, %esi
	shll	$10, %esi
	cltd
	idivl	%esi
	testl	%eax, %eax
	js	.LBB1_20
# %bb.15:                               # %.lr.ph
	movl	%eax, %r14d
	movabsq	$4294967296, %r15               # imm = 0x100000000
	movl	%ebp, %r12d
	btsq	$32, %r12
	incl	%r14d
	xorl	%r13d, %r13d
	addq	$1024, %r15                     # imm = 0x400
.LBB1_16:                               # =>This Inner Loop Header: Depth=1
	movq	%r15, %rdi
	movl	$1, %esi
	movq	%r12, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_18
# %bb.17:                               #   in Loop: Header=BB1_16 Depth=1
	movq	56(%rsp), %rdi
	movq	48(%rsp), %rax
	movl	(%rax), %esi
	movq	40(%rsp), %rax
	movl	(%rax), %edx
	movq	32(%rsp), %rax
	movsd	(%rax), %xmm0                   # xmm0 = mem[0],zero
	movq	24(%rsp), %rax
	movss	(%rax), %xmm1                   # xmm1 = mem[0],zero,zero,zero
	movq	16(%rsp), %rax
	movss	(%rax), %xmm2                   # xmm2 = mem[0],zero,zero,zero
	movl	%ebp, %ecx
	movl	$1024, %r8d                     # imm = 0x400
	movl	%r13d, %r9d
	callq	_Z26__device_stub__fill_matrixPiiiN6thrust7complexIfEEffiii
.LBB1_18:                               #   in Loop: Header=BB1_16 Depth=1
	callq	hipDeviceSynchronize
	incl	%r13d
	cmpl	%r13d, %r14d
	jne	.LBB1_16
# %bb.19:                               # %._crit_edge.loopexit
	movl	4(%rsp), %ecx
	movl	(%rsp), %edi
.LBB1_20:                               # %._crit_edge
	movq	56(%rsp), %rsi
	movslq	%ecx, %rax
	movslq	%edi, %rdx
	imulq	%rax, %rdx
	shlq	$2, %rdx
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	testl	%eax, %eax
	jne	.LBB1_9
# %bb.21:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB1_1:
	.cfi_def_cfa_offset 128
	movl	$_ZSt4cerr, %edi
	movl	$.L.str, %esi
	jmp	.LBB1_2
.LBB1_9:
	movl	$_ZSt4cerr, %edi
	movl	$.L.str.1, %esi
.LBB1_2:
	callq	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc
	movl	$1, %edi
	callq	exit
.Lfunc_end1:
	.size	_Z7preparePiiiN6thrust7complexIfEEffi, .Lfunc_end1-_Z7preparePiiiN6thrust7complexIfEEffi
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z11fill_matrixPiiiN6thrust7complexIfEEffiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z11fill_matrixPiiiN6thrust7complexIfEEffiii,@object # @_Z11fill_matrixPiiiN6thrust7complexIfEEffiii
	.section	.rodata,"a",@progbits
	.globl	_Z11fill_matrixPiiiN6thrust7complexIfEEffiii
	.p2align	3, 0x0
_Z11fill_matrixPiiiN6thrust7complexIfEEffiii:
	.quad	_Z26__device_stub__fill_matrixPiiiN6thrust7complexIfEEffiii
	.size	_Z11fill_matrixPiiiN6thrust7complexIfEEffiii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Could not allocate memory"
	.size	.L.str, 26

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"Could not copy memory"
	.size	.L.str.1, 22

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z11fill_matrixPiiiN6thrust7complexIfEEffiii"
	.size	.L__unnamed_1, 45

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z26__device_stub__fill_matrixPiiiN6thrust7complexIfEEffiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z11fill_matrixPiiiN6thrust7complexIfEEffiii
	.addrsig_sym _ZSt4cerr
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z11fill_matrixPiiiN6thrust7complexIfEEffiii ; -- Begin function _Z11fill_matrixPiiiN6thrust7complexIfEEffiii
	.globl	_Z11fill_matrixPiiiN6thrust7complexIfEEffiii
	.p2align	8
	.type	_Z11fill_matrixPiiiN6thrust7complexIfEEffiii,@function
_Z11fill_matrixPiiiN6thrust7complexIfEEffiii: ; @_Z11fill_matrixPiiiN6thrust7complexIfEEffiii
; %bb.0:
	s_clause 0x2
	s_load_b128 s[4:7], s[0:1], 0x18
	s_load_b32 s8, s[0:1], 0x28
	s_load_b64 s[2:3], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s7, s8, s7
	s_mul_i32 s3, s3, s2
	s_add_i32 s7, s7, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[12:13], null, s7, s6, v[0:1]
	v_cmp_gt_u32_e32 vcc_lo, s3, v12
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB0_88
; %bb.1:
	v_cvt_f32_u32_e32 v0, s2
	s_sub_i32 s3, 0, s2
	s_load_b64 s[12:13], s[0:1], 0x10
	v_mov_b32_e32 v16, 0x4016cbe4
	v_mov_b32_e32 v14, 0
	v_rcp_iflag_f32_e32 v0, v0
	s_mov_b32 s6, 0
	s_mov_b32 s7, 0x3e9b6dac
	s_mov_b32 s8, 0x3b2d2a58
	s_mov_b32 s9, 0x7fffff
	s_mov_b32 s10, 0xb94c1982
	s_mov_b32 s11, 0x7f000000
	v_mov_b32_e32 v15, 0
	s_waitcnt_depctr 0xfff
	v_dual_mov_b32 v19, 0 :: v_dual_mul_f32 v0, 0x4f7ffffe, v0
	v_mov_b32_e32 v13, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v0, v0
	v_mul_lo_u32 v1, s3, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v1, v0, v1
	v_add_nc_u32_e32 v0, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v0, v12, v0
	v_mul_lo_u32 v1, v0, s2
	v_add_nc_u32_e32 v2, 1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v1, v12, v1
	v_subrev_nc_u32_e32 v3, s2, v1
	v_cmp_le_u32_e32 vcc_lo, s2, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v0, v0, v2 :: v_dual_cndmask_b32 v1, v1, v3
	v_add_nc_u32_e32 v2, 1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s2, v1
	v_cndmask_b32_e32 v0, v0, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v1, v0, s2
	v_cvt_f32_u32_e32 v0, v0
	s_waitcnt lgkmcnt(0)
	v_fma_f32 v17, v0, s4, s13
                                        ; implicit-def: $sgpr13
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v1, v12, v1
	v_cvt_f32_u32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f32 v18, v1, s5, s12
	s_mov_b32 s5, 0x37d75334
	s_mov_b32 s12, 0
.LBB0_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_14 Depth 2
                                        ;       Child Loop BB0_15 Depth 3
                                        ;     Child Loop BB0_18 Depth 2
	v_max_f32_e64 v22, |v14|, |v14|
	v_max_f32_e64 v21, |v19|, |v19|
	s_or_b32 s13, s13, exec_lo
	s_mov_b32 s14, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_f32_e32 v23, v21, v22
	v_frexp_exp_i32_f32_e32 v20, v23
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v23|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, 0, v20
	v_ldexp_f32 v1, |v14|, v0
	v_ldexp_f32 v0, |v19|, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v1, v1, v1
	v_fmac_f32_e32 v1, v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sqrt_f32_e32 v0, v1
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v0, v0, v20
	v_cndmask_b32_e32 v3, 0x7f800000, v0, vcc_lo
	v_mov_b32_e32 v0, s12
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_nlt_f32_e32 2.0, v3
	s_cbranch_execz .LBB0_86
; %bb.3:                                ;   in Loop: Header=BB0_2 Depth=1
                                        ; implicit-def: $vgpr2
                                        ; implicit-def: $vgpr0
	s_mov_b32 s2, exec_lo
	v_cmpx_o_f32_e32 v14, v19
	s_xor_b32 s15, exec_lo, s2
	s_cbranch_execz .LBB0_35
; %bb.4:                                ;   in Loop: Header=BB0_2 Depth=1
	v_cmp_lt_f32_e64 s2, |v19|, |v14|
                                        ; implicit-def: $vgpr2
                                        ; implicit-def: $vgpr0
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v1, |v14|, |v19|, s2
	v_cmpx_nlt_f32_e32 0x77f684df, v1
	s_xor_b32 s16, exec_lo, s3
	s_cbranch_execz .LBB0_32
; %bb.5:                                ;   in Loop: Header=BB0_2 Depth=1
	v_cndmask_b32_e64 v4, |v19|, |v14|, s2
                                        ; implicit-def: $vgpr2
                                        ; implicit-def: $vgpr0
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_neq_f32_e32 1.0, v4
	s_xor_b32 s4, exec_lo, s3
	s_cbranch_execz .LBB0_25
; %bb.6:                                ;   in Loop: Header=BB0_2 Depth=1
	v_max_f32_e32 v0, v1, v1
	v_max_f32_e32 v2, v4, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_min_f32_e32 v5, v2, v0
	v_max_f32_e32 v0, v2, v0
                                        ; implicit-def: $vgpr2
	v_cmp_ngt_f32_e32 vcc_lo, 0x358637bd, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_nlt_f32_e64 s3, 0x49742400, v0
                                        ; implicit-def: $vgpr0
	s_and_b32 s3, s3, vcc_lo
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s17, s3
	s_xor_b32 s17, exec_lo, s17
	s_cbranch_execz .LBB0_22
; %bb.7:                                ;   in Loop: Header=BB0_2 Depth=1
                                        ; implicit-def: $vgpr2
                                        ; implicit-def: $vgpr0
	s_mov_b32 s3, exec_lo
	v_cmpx_le_f32_e32 1.0, v4
	s_xor_b32 s18, exec_lo, s3
	s_cbranch_execz .LBB0_9
; %bb.8:                                ;   in Loop: Header=BB0_2 Depth=1
	v_add_f32_e32 v0, -1.0, v4
	v_add_f32_e32 v2, 1.0, v4
	v_cmp_class_f32_e64 s19, v19, 0x204
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v0, v0, v2
	v_fmac_f32_e32 v0, v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, 1.0, v0
	v_frexp_mant_f32_e32 v2, v1
	v_frexp_exp_i32_f32_e32 v3, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v2
	v_subrev_co_ci_u32_e32 v2, vcc_lo, 0, v3, vcc_lo
	v_add_f32_e32 v3, -1.0, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v4, 0, v2
	v_cvt_f32_i32_e32 v2, v2
	v_sub_f32_e32 v5, v3, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_ldexp_f32 v1, v1, v4
	v_sub_f32_e32 v3, v0, v3
	v_add_f32_e32 v5, 1.0, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v6, 1.0, v1
	v_add_f32_e32 v3, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f32_e32 v5, -1.0, v6
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v0
	v_ldexp_f32 v3, v3, v4
	v_add_f32_e32 v4, -1.0, v1
	v_cmp_neq_f32_e64 s3, -1.0, v0
	v_sub_f32_e32 v5, v1, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v7, 1.0, v4
	v_sub_f32_e32 v1, v1, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v3, v1
	v_add_f32_e32 v8, v4, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v4, v8, v4 :: v_dual_add_f32 v5, v3, v5
	v_add_f32_e32 v7, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v3, v7
	v_sub_f32_e32 v6, v7, v6
	v_sub_f32_e32 v5, v5, v6
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v9, v8, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v10, v7, v9
	v_fma_f32 v6, v9, v7, -v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, v9, v5
	v_add_f32_e32 v11, v10, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v24, v8, v11
	v_sub_f32_e32 v8, v8, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v8, v8, v11 :: v_dual_sub_f32 v1, v1, v4
	v_sub_f32_e32 v4, v11, v10
	v_dual_sub_f32 v4, v4, v6 :: v_dual_add_f32 v1, v1, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v4, v1
	v_add_f32_e32 v4, v24, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v6, v3, v4
	v_dual_sub_f32 v11, v24, v4 :: v_dual_mul_f32 v8, v7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v7, v6, v7, -v8
	v_fmac_f32_e32 v7, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v8, v7
	v_sub_f32_e32 v8, v5, v8
	v_dual_sub_f32 v10, v4, v5 :: v_dual_add_f32 v1, v1, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v4, v4, v10
	v_sub_f32_e32 v4, v4, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v5, v8, v7 :: v_dual_min_f32 v8, v21, v22
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr22
	v_add_f32_e32 v1, v1, v4
	v_add_f32_e32 v4, v9, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v1, v5, v1
	v_sub_f32_e32 v5, v4, v9
	v_mul_f32_e32 v9, 0x3f317218, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v1, v10, v1
	v_sub_f32_e32 v5, v6, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v10, 0x3f317218, v2, -v9
	v_dual_mul_f32 v1, v3, v1 :: v_dual_fmac_f32 v10, 0xb102e308, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v5, v1
	v_add_f32_e32 v3, v4, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v3, v3
	v_fmaak_f32 v6, s7, v5, 0x3ecc95a3
	v_mul_f32_e32 v7, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmaak_f32 v5, v5, v6, 0x3f2aaada
	v_ldexp_f32 v6, v3, 1
	v_mul_f32_e32 v5, v7, v5
	v_sub_f32_e32 v3, v3, v4
	v_frexp_mant_f32_e32 v7, v23
                                        ; implicit-def: $vgpr23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v4, v6, v5 :: v_dual_sub_f32 v1, v1, v3
	v_sub_f32_e32 v3, v4, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_rcp_f32_e32 v6, v7
	v_frexp_exp_i32_f32_e32 v7, v8
	v_ldexp_f32 v1, v1, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v3, v5, v3
	v_frexp_mant_f32_e32 v5, v8
	v_sub_nc_u32_e32 v7, v7, v20
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v2, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v2, v2, v7
	v_mul_f32_e32 v7, v2, v2
	v_add_f32_e32 v1, v1, v3
	v_add_f32_e32 v3, v9, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmaak_f32 v11, s8, v7, 0xbc7a590c
	v_add_f32_e32 v5, v4, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmaak_f32 v11, v7, v11, 0x3d29fb3f
	v_add_f32_e32 v6, v3, v5
	v_dual_sub_f32 v9, v3, v9 :: v_dual_sub_f32 v4, v5, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v8, v6, v3
	v_sub_f32_e32 v9, v10, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v1, v1, v4
	v_sub_f32_e32 v20, v6, v8
	v_dual_sub_f32 v4, v5, v8 :: v_dual_fmaak_f32 v5, v7, v11, 0xbd97d4d7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v8, v9, v1 :: v_dual_sub_f32 v3, v3, v20
                                        ; implicit-def: $vgpr20
	v_dual_add_f32 v3, v4, v3 :: v_dual_fmaak_f32 v4, v7, v5, 0x3dd931b2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v5, v8, v9
	v_dual_add_f32 v3, v8, v3 :: v_dual_fmaak_f32 v4, v7, v4, 0xbe1160e6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v8, v8, v5
	v_dual_sub_f32 v1, v1, v5 :: v_dual_add_f32 v10, v6, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmaak_f32 v4, v7, v4, 0x3e4cb8bf
	v_dual_sub_f32 v5, v9, v8 :: v_dual_sub_f32 v6, v10, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmaak_f32 v4, v7, v4, 0xbeaaaa62 :: v_dual_add_f32 v1, v1, v5
	v_sub_f32_e32 v3, v3, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v4, v7, v4 :: v_dual_add_f32 v1, v1, v3
	v_fmac_f32_e32 v2, v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v1, v10, v1
	v_sub_f32_e32 v3, 0x3fc90fdb, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v1, v1, v0, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, 0, v19
	v_cndmask_b32_e64 v2, v2, v3, s2
	v_cndmask_b32_e64 v3, 0, 0x40490fdb, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, -1.0, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v4, 0x40490fdb, v2
	v_cndmask_b32_e32 v1, 0x7fc00000, v1, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0, v19
                                        ; implicit-def: $vgpr19
	v_cndmask_b32_e64 v1, 0xff800000, v1, s3
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e32 v2, v2, v4, vcc_lo
	v_cndmask_b32_e32 v4, 0x3f490fdb, v16, vcc_lo
	v_cmp_gt_f32_e64 vcc_lo, 0x33800000, |v0|
	v_cmp_class_f32_e64 s3, v14, 0x204
	v_cndmask_b32_e32 v0, v1, v0, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0, v14
	v_cndmask_b32_e32 v1, v2, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	s_and_b32 vcc_lo, s3, s19
	v_mul_f32_e32 v2, 0.5, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v0, v1, v4, vcc_lo
                                        ; implicit-def: $vgpr1
                                        ; implicit-def: $vgpr4
.LBB0_9:                                ; %Flow81
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s18, s18
	s_cbranch_execz .LBB0_21
; %bb.10:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mul_f32_e32 v3, v1, v1
                                        ; implicit-def: $vgpr2
                                        ; implicit-def: $vgpr0
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v3, v4, v4
	v_cmpx_ge_f32_e32 0x3f333333, v3
	s_xor_b32 s19, exec_lo, s3
	s_cbranch_execz .LBB0_12
; %bb.11:                               ;   in Loop: Header=BB0_2 Depth=1
	v_cmp_gt_f32_e32 vcc_lo, 0x800000, v3
	v_frexp_mant_f32_e32 v0, v23
	v_cmp_gt_i32_e64 s3, 0, v19
	v_cmp_class_f32_e64 s20, v19, 0x204
	v_cmp_class_f32_e64 s21, v14, 0x204
	v_cndmask_b32_e64 v4, 1.0, 0x4f800000, vcc_lo
	v_rcp_f32_e32 v0, v0
	v_cndmask_b32_e64 v5, 0, 0x41b17218, vcc_lo
                                        ; implicit-def: $vgpr23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v3, v3, v4
	v_log_f32_e32 v3, v3
	v_min_f32_e32 v1, v21, v22
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr22
	s_delay_alu instid0(VALU_DEP_1)
	v_frexp_exp_i32_f32_e32 v2, v1
	v_frexp_mant_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v3|
	v_sub_nc_u32_e32 v2, v2, v20
	v_mul_f32_e32 v0, v1, v0
                                        ; implicit-def: $vgpr20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v0, v0, v2
	v_mul_f32_e32 v1, v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v2, s8, v1, 0xbc7a590c
	v_fmaak_f32 v2, v1, v2, 0x3d29fb3f
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v2, v1, v2, 0xbd97d4d7
	v_fmaak_f32 v2, v1, v2, 0x3dd931b2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v2, v1, v2, 0xbe1160e6
	v_fmaak_f32 v2, v1, v2, 0x3e4cb8bf
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v2, v1, v2, 0xbeaaaa62
	v_dual_mul_f32 v1, v1, v2 :: v_dual_mul_f32 v2, 0x3f317217, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v0, v0, v1
	v_fma_f32 v1, 0x3f317217, v3, -v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v1, 0x3377d1cf, v3
	v_add_f32_e32 v1, v2, v1
	v_cndmask_b32_e64 v2, 0, 0x40490fdb, s3
	v_cmp_eq_f32_e64 s3, 0, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v3, v1, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0, v19
                                        ; implicit-def: $vgpr19
	v_sub_f32_e32 v1, v1, v5
	v_cndmask_b32_e32 v3, 0x3f490fdb, v16, vcc_lo
	v_sub_f32_e32 v4, 0x3fc90fdb, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v0, v0, v4, s2
	v_sub_f32_e32 v4, 0x40490fdb, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v4, vcc_lo
	s_and_b32 vcc_lo, s21, s20
                                        ; implicit-def: $vgpr4
	v_cndmask_b32_e64 v0, v0, v2, s3
	v_mul_f32_e32 v2, 0.5, v1
                                        ; implicit-def: $vgpr1
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v0, v0, v3, vcc_lo
.LBB0_12:                               ; %Flow79
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s19, s19
	s_cbranch_execz .LBB0_20
; %bb.13:                               ;   in Loop: Header=BB0_2 Depth=1
	v_and_b32_e32 v3, 0xffff0000, v1
	v_and_b32_e32 v2, 0xffff0000, v4
	s_mov_b32 s3, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v5, v1, v3 :: v_dual_sub_f32 v4, v4, v2
	v_mul_f32_e32 v0, v2, v2
	v_dual_add_f32 v8, v2, v2 :: v_dual_mul_f32 v1, v3, v3
	v_and_b32_e32 v7, 0xffff0000, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v9, v3, v3 :: v_dual_and_b32 v6, 0xffff0000, v4
	v_dual_sub_f32 v11, v5, v7 :: v_dual_sub_f32 v10, v4, v6
	v_dual_mul_f32 v4, v6, v6 :: v_dual_add_f32 v25, v7, v7
	v_dual_add_f32 v24, v6, v6 :: v_dual_mul_f32 v5, v7, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_dual_mul_f32 v2, v8, v6 :: v_dual_mul_f32 v3, v9, v7
	v_dual_mul_f32 v6, v8, v10 :: v_dual_mul_f32 v7, v9, v11
	s_delay_alu instid0(VALU_DEP_3)
	v_dual_mul_f32 v8, v24, v10 :: v_dual_mul_f32 v9, v25, v11
	v_dual_mul_f32 v10, v10, v10 :: v_dual_mul_f32 v11, v11, v11
.LBB0_14:                               ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_15 Depth 3
	v_dual_mov_b32 v24, 1 :: v_dual_mov_b32 v25, v0
	s_mov_b32 s20, 0
.LBB0_15:                               ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_14 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_add_i32 s21, s20, 1
	v_dual_mov_b32 v37, v11 :: v_dual_mov_b32 v36, v10
	s_mov_b32 m0, s21
	v_dual_mov_b32 v27, v1 :: v_dual_mov_b32 v26, v0
	v_movrels_b32_e32 v38, v0
	s_mov_b32 m0, s20
	v_dual_mov_b32 v35, v9 :: v_dual_mov_b32 v34, v8
	v_dual_mov_b32 v33, v7 :: v_dual_mov_b32 v32, v6
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_lt_f32_e32 vcc_lo, v25, v38
	v_dual_mov_b32 v31, v5 :: v_dual_mov_b32 v30, v4
	v_dual_mov_b32 v29, v3 :: v_dual_mov_b32 v28, v2
	v_movreld_b32_e32 v26, v38
	s_mov_b32 m0, s21
	v_cndmask_b32_e64 v24, v24, 0, vcc_lo
	v_movreld_b32_e32 v26, v25
	v_dual_cndmask_b32 v11, v11, v37 :: v_dual_cndmask_b32 v10, v10, v36
	v_dual_cndmask_b32 v9, v9, v35 :: v_dual_cndmask_b32 v8, v8, v34
	v_dual_cndmask_b32 v7, v7, v33 :: v_dual_cndmask_b32 v6, v6, v32
	v_dual_cndmask_b32 v5, v5, v31 :: v_dual_cndmask_b32 v4, v4, v30
	v_dual_cndmask_b32 v3, v3, v29 :: v_dual_cndmask_b32 v2, v2, v28
	v_dual_cndmask_b32 v1, v1, v27 :: v_dual_cndmask_b32 v0, v0, v26
	v_cndmask_b32_e32 v25, v38, v25, vcc_lo
	s_cmp_lg_u32 s21, 11
	s_mov_b32 s20, s21
	s_cbranch_scc1 .LBB0_15
; %bb.16:                               ;   in Loop: Header=BB0_14 Depth=2
	v_cmp_ne_u32_e32 vcc_lo, 0, v24
	s_or_b32 s3, vcc_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s3
	s_cbranch_execnz .LBB0_14
; %bb.17:                               ; %.preheader.i.i.i.i.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	v_mov_b32_e32 v24, -1.0
	s_mov_b32 s3, 0
.LBB0_18:                               ; %.preheader.i.i.i.i
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	s_mov_b32 m0, s3
	s_add_i32 s3, s3, 1
	v_movrels_b32_e32 v25, v0
	s_cmp_lg_u32 s3, 12
	v_add_f32_e32 v24, v24, v25
	s_cbranch_scc1 .LBB0_18
; %bb.19:                               ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_f32_e32 v0, 1.0, v24
	v_cmp_neq_f32_e64 s3, -1.0, v24
	v_cmp_class_f32_e64 s20, v19, 0x204
	v_frexp_mant_f32_e32 v1, v0
	v_frexp_exp_i32_f32_e32 v2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v1
	v_subrev_co_ci_u32_e32 v1, vcc_lo, 0, v2, vcc_lo
	v_add_f32_e32 v2, -1.0, v0
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v3, 0, v1
	v_cvt_f32_i32_e32 v1, v1
	v_sub_f32_e32 v4, v2, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_ldexp_f32 v0, v0, v3
	v_sub_f32_e32 v2, v24, v2
	v_add_f32_e32 v4, 1.0, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v5, 1.0, v0
	v_add_f32_e32 v2, v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v4, -1.0, v5
	v_ldexp_f32 v2, v2, v3
	v_add_f32_e32 v3, -1.0, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v4, v0, v4
	v_add_f32_e32 v6, 1.0, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v4, v2, v4
	v_sub_f32_e32 v0, v0, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v6, v5, v4
	v_add_f32_e32 v0, v2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v2, v6
	v_sub_f32_e32 v5, v6, v5
	v_dual_add_f32 v7, v3, v0 :: v_dual_sub_f32 v4, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v3, v7, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v8, v7, v2
	v_dual_sub_f32 v0, v0, v3 :: v_dual_mul_f32 v9, v6, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v5, v8, v6, -v9
	v_fmac_f32_e32 v5, v8, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v10, v9, v5
	v_sub_f32_e32 v11, v7, v10
	v_sub_f32_e32 v3, v10, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v7, v7, v11
	v_sub_f32_e32 v3, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v7, v7, v10
	v_add_f32_e32 v0, v0, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v3, v0
	v_add_f32_e32 v3, v11, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v2, v3
	v_dual_sub_f32 v10, v11, v3 :: v_dual_mul_f32 v7, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v6, v5, v6, -v7
	v_fmac_f32_e32 v6, v5, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v4, v7, v6
	v_sub_f32_e32 v9, v3, v4
	v_sub_f32_e32 v7, v4, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v0, v0, v10 :: v_dual_sub_f32 v3, v3, v9
	v_sub_f32_e32 v3, v3, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v0, v0, v3
	v_dual_add_f32 v3, v8, v5 :: v_dual_sub_f32 v4, v7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_min_f32 v7, v21, v22 :: v_dual_add_f32 v0, v4, v0
	v_sub_f32_e32 v4, v3, v8
	v_mul_f32_e32 v8, 0x3f317218, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v0, v9, v0
	v_sub_f32_e32 v4, v5, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v9, 0x3f317218, v1, -v8
	v_dual_mul_f32 v0, v2, v0 :: v_dual_fmac_f32 v9, 0xb102e308, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v0, v4, v0
	v_add_f32_e32 v2, v3, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v4, v2, v2
	v_fmaak_f32 v5, s7, v4, 0x3ecc95a3
	v_mul_f32_e32 v6, v2, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fmaak_f32 v4, v4, v5, 0x3f2aaada
	v_ldexp_f32 v5, v2, 1
	v_sub_f32_e32 v2, v2, v3
	v_mul_f32_e32 v4, v6, v4
	v_frexp_mant_f32_e32 v6, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v0, v0, v2 :: v_dual_add_f32 v3, v5, v4
	v_ldexp_f32 v0, v0, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v2, v3, v5
	v_rcp_f32_e32 v5, v6
	v_frexp_exp_i32_f32_e32 v6, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v2, v4, v2
	v_frexp_mant_f32_e32 v4, v7
	v_sub_nc_u32_e32 v6, v6, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_add_f32_e32 v0, v0, v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, v4, v5
	v_add_f32_e32 v2, v8, v9
	v_add_f32_e32 v4, v3, v0
	v_ldexp_f32 v1, v1, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_add_f32 v5, v2, v4 :: v_dual_mul_f32 v6, v1, v1
	v_dual_sub_f32 v8, v2, v8 :: v_dual_sub_f32 v3, v4, v3
	v_sub_f32_e32 v7, v5, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmaak_f32 v10, s8, v6, 0xbc7a590c
	v_sub_f32_e32 v8, v9, v8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v0, v0, v3
	v_dual_sub_f32 v11, v5, v7 :: v_dual_fmaak_f32 v10, v6, v10, 0x3d29fb3f
	v_sub_f32_e32 v3, v4, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v7, v8, v0 :: v_dual_sub_f32 v2, v2, v11
	v_fmaak_f32 v4, v6, v10, 0xbd97d4d7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_add_f32 v2, v3, v2 :: v_dual_fmaak_f32 v3, v6, v4, 0x3dd931b2
	v_sub_f32_e32 v4, v7, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_add_f32 v2, v7, v2 :: v_dual_fmaak_f32 v3, v6, v3, 0xbe1160e6
	v_sub_f32_e32 v7, v7, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v0, v0, v4 :: v_dual_add_f32 v9, v5, v2
	v_fmaak_f32 v3, v6, v3, 0x3e4cb8bf
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v4, v8, v7 :: v_dual_sub_f32 v5, v9, v5
	v_dual_fmaak_f32 v3, v6, v3, 0xbeaaaa62 :: v_dual_add_f32 v0, v0, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v2, v2, v5
	v_dual_mul_f32 v3, v6, v3 :: v_dual_add_f32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v1, v1, v3
	v_add_f32_e32 v0, v9, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v2, 0x3fc90fdb, v1
	v_cndmask_b32_e32 v0, v0, v24, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, 0, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v1, v1, v2, s2
	v_cndmask_b32_e64 v2, 0, 0x40490fdb, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, -1.0, v24
	v_sub_f32_e32 v3, 0x40490fdb, v1
	v_cndmask_b32_e32 v0, 0x7fc00000, v0, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v0, 0xff800000, v0, s3
	v_cndmask_b32_e32 v1, v1, v3, vcc_lo
	v_cndmask_b32_e32 v3, 0x3f490fdb, v16, vcc_lo
	v_cmp_gt_f32_e64 vcc_lo, 0x33800000, |v24|
	v_cmp_class_f32_e64 s3, v14, 0x204
	v_cndmask_b32_e32 v0, v0, v24, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0, v14
	v_cndmask_b32_e32 v1, v1, v2, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	s_and_b32 vcc_lo, s3, s20
	v_mul_f32_e32 v2, 0.5, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v0, v1, v3, vcc_lo
.LBB0_20:                               ; %Flow80
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s19
.LBB0_21:                               ; %Flow82
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s18
                                        ; implicit-def: $vgpr3
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr23
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr19
.LBB0_22:                               ; %Flow83
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s17, s17
	s_cbranch_execz .LBB0_24
; %bb.23:                               ;   in Loop: Header=BB0_2 Depth=1
	v_frexp_mant_f32_e32 v0, v23
	v_cmp_gt_f32_e32 vcc_lo, 0x800000, v3
	v_min_f32_e32 v1, v21, v22
	v_cmp_gt_i32_e64 s3, 0, v19
	v_cmp_class_f32_e64 s18, v19, 0x204
	v_rcp_f32_e32 v0, v0
	v_cndmask_b32_e64 v4, 1.0, 0x4f800000, vcc_lo
	v_frexp_exp_i32_f32_e32 v2, v1
	v_frexp_mant_f32_e32 v1, v1
	v_cmp_class_f32_e64 s19, v14, 0x204
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v3, v3, v4
	v_sub_nc_u32_e32 v2, v2, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(TRANS32_DEP_2)
	v_log_f32_e32 v3, v3
	v_mul_f32_e32 v0, v1, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ldexp_f32 v0, v0, v2
	v_mul_f32_e32 v1, v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v2, s8, v1, 0xbc7a590c
	v_fmaak_f32 v2, v1, v2, 0x3d29fb3f
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v2, v1, v2, 0xbd97d4d7
	v_fmaak_f32 v2, v1, v2, 0x3dd931b2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v2, v1, v2, 0xbe1160e6
	v_fmaak_f32 v2, v1, v2, 0x3e4cb8bf
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v2, v1, v2, 0xbeaaaa62
	v_mul_f32_e32 v1, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v0, v0, v1 :: v_dual_mul_f32 v1, 0x3f317217, v3
	v_sub_f32_e32 v2, 0x3fc90fdb, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v4, 0x3f317217, v3, -v1
	v_cndmask_b32_e64 v0, v0, v2, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v4, 0x3377d1cf, v3
	v_cndmask_b32_e64 v2, 0, 0x40490fdb, s3
	v_cmp_gt_f32_e64 s3, 0, v19
	v_add_f32_e32 v1, v1, v4
	v_cndmask_b32_e64 v4, 0, 0x41b17218, vcc_lo
	v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v3|
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v3, v1, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0, v14
	v_sub_f32_e32 v5, 0x40490fdb, v0
	v_cndmask_b32_e64 v3, 0x3f490fdb, v16, s3
	v_cndmask_b32_e64 v0, v0, v5, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v0, v0, v2, vcc_lo
	s_and_b32 vcc_lo, s19, s18
	v_sub_f32_e32 v2, v1, v4
	v_cndmask_b32_e32 v0, v0, v3, vcc_lo
.LBB0_24:                               ; %Flow84
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
                                        ; implicit-def: $vgpr1
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr23
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr19
.LBB0_25:                               ; %Flow87
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s17, s4
	s_cbranch_execz .LBB0_31
; %bb.26:                               ;   in Loop: Header=BB0_2 Depth=1
                                        ; implicit-def: $vgpr2
                                        ; implicit-def: $vgpr0
	s_mov_b32 s3, exec_lo
	v_cmpx_ngt_f32_e32 0x1fec1e4a, v1
	s_xor_b32 s18, exec_lo, s3
	s_cbranch_execz .LBB0_28
; %bb.27:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mul_f32_e32 v0, v1, v1
	v_cmp_gt_f32_e64 s3, 0, v19
	v_cmp_class_f32_e64 s19, v19, 0x204
	v_cmp_class_f32_e64 s20, v14, 0x204
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, 1.0, v0
	v_frexp_mant_f32_e32 v2, v1
	v_frexp_exp_i32_f32_e32 v3, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_f32_e32 vcc_lo, 0x3f2aaaab, v2
	v_subrev_co_ci_u32_e32 v2, vcc_lo, 0, v3, vcc_lo
	v_add_f32_e32 v3, -1.0, v1
	v_cmp_gt_i32_e32 vcc_lo, 0, v19
                                        ; implicit-def: $vgpr19
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_nc_u32_e32 v4, 0, v2
	v_cvt_f32_i32_e32 v2, v2
	v_sub_f32_e32 v5, v3, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_ldexp_f32 v1, v1, v4
	v_sub_f32_e32 v3, v0, v3
	v_add_f32_e32 v5, 1.0, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v6, 1.0, v1
	v_add_f32_e32 v3, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f32_e32 v5, -1.0, v6
	v_cmp_gt_f32_e64 s4, 0x33800000, v0
	v_ldexp_f32 v3, v3, v4
	v_add_f32_e32 v4, -1.0, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v5, v1, v5
	v_add_f32_e32 v7, 1.0, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v5, v3, v5
	v_sub_f32_e32 v1, v1, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v7, v6, v5
	v_add_f32_e32 v1, v3, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v3, v7
	v_sub_f32_e32 v6, v6, v7
	v_dual_add_f32 v8, v4, v1 :: v_dual_add_f32 v5, v5, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v4, v4, v8
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v9, v8, v3
	v_dual_add_f32 v1, v1, v4 :: v_dual_mul_f32 v10, v7, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v6, v9, v7, -v10
	v_fmac_f32_e32 v6, v9, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v11, v10, v6
	v_sub_f32_e32 v24, v8, v11
	v_sub_f32_e32 v4, v11, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v8, v8, v24
	v_sub_f32_e32 v4, v4, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v8, v8, v11
	v_add_f32_e32 v1, v1, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v4, v1
	v_add_f32_e32 v4, v24, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v6, v3, v4
	v_dual_sub_f32 v11, v24, v4 :: v_dual_mul_f32 v8, v7, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v7, v6, v7, -v8
	v_fmac_f32_e32 v7, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, v8, v7
	v_sub_f32_e32 v10, v4, v5
	v_sub_f32_e32 v8, v5, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_add_f32 v1, v1, v11 :: v_dual_sub_f32 v4, v4, v10
	v_sub_f32_e32 v4, v4, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v1, v1, v4
	v_dual_add_f32 v4, v9, v6 :: v_dual_sub_f32 v5, v8, v7
	v_min_f32_e32 v8, v21, v22
	v_frexp_mant_f32_e32 v7, v23
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v1, v5, v1
	v_sub_f32_e32 v5, v4, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v1, v10, v1
	v_sub_f32_e32 v5, v6, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v1, v3, v1
	v_add_f32_e32 v1, v5, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v3, v4, v1
	v_mul_f32_e32 v5, v3, v3
	v_ldexp_f32 v10, v3, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fmaak_f32 v6, s7, v5, 0x3ecc95a3
	v_mul_f32_e32 v9, v3, v5
	v_sub_f32_e32 v3, v3, v4
	v_fmaak_f32 v5, v5, v6, 0x3f2aaada
	v_rcp_f32_e32 v6, v7
	v_frexp_exp_i32_f32_e32 v7, v8
	v_frexp_mant_f32_e32 v8, v8
	v_sub_f32_e32 v1, v1, v3
	v_mul_f32_e32 v5, v9, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v7, v7, v20
	v_ldexp_f32 v1, v1, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(TRANS32_DEP_1)
	v_add_f32_e32 v4, v10, v5
	v_mul_f32_e32 v6, v8, v6
	v_mul_f32_e32 v8, 0x3f317218, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v3, v4, v10
	v_ldexp_f32 v6, v6, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v7, 0x3f317218, v2, -v8
	v_sub_f32_e32 v3, v5, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v7, 0xb102e308, v2
	v_add_f32_e32 v1, v1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v3, v8, v7
	v_dual_add_f32 v9, v4, v1 :: v_dual_sub_f32 v8, v3, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f32_e32 v10, v3, v9
	v_sub_f32_e32 v4, v9, v4
	v_sub_f32_e32 v7, v7, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v11, v10, v3
	v_dual_sub_f32 v1, v1, v4 :: v_dual_sub_f32 v20, v10, v11
	v_sub_f32_e32 v4, v9, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v8, v7, v1
	v_sub_f32_e32 v3, v3, v20
                                        ; implicit-def: $vgpr20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f32_e32 v3, v4, v3
	v_sub_f32_e32 v4, v8, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f32_e32 v3, v8, v3
	v_mul_f32_e32 v5, v6, v6
	v_dual_sub_f32 v1, v1, v4 :: v_dual_fmaak_f32 v2, s8, v5, 0xbc7a590c
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v2, v5, v2, 0x3d29fb3f
	v_fmaak_f32 v2, v5, v2, 0xbd97d4d7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v2, v5, v2, 0x3dd931b2
	v_fmaak_f32 v2, v5, v2, 0xbe1160e6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v2, v5, v2, 0x3e4cb8bf
	v_fmaak_f32 v2, v5, v2, 0xbeaaaa62
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v2, v5, v2 :: v_dual_sub_f32 v5, v8, v4
	v_add_f32_e32 v8, v10, v3
	v_fmac_f32_e32 v6, v6, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v2, v7, v5
	v_sub_f32_e32 v4, v8, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v5, 0x3fc90fdb, v6
	v_dual_add_f32 v1, v1, v2 :: v_dual_sub_f32 v2, v3, v4
	v_cndmask_b32_e64 v4, 0, 0x40490fdb, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0x7f800000, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v3, v6, v5, s2
	v_add_f32_e32 v1, v1, v2
	s_or_b32 vcc_lo, s4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v2, 0x40490fdb, v3 :: v_dual_add_f32 v1, v8, v1
	v_cndmask_b32_e64 v2, v3, v2, s3
	v_cndmask_b32_e64 v3, 0x3f490fdb, v16, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v0, v1, v0, vcc_lo
	v_cmp_eq_f32_e32 vcc_lo, 0, v14
	v_cndmask_b32_e32 v1, v2, v4, vcc_lo
	s_and_b32 vcc_lo, s20, s19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v2, 0.5, v0
	v_cndmask_b32_e32 v0, v1, v3, vcc_lo
                                        ; implicit-def: $vgpr1
.LBB0_28:                               ; %Flow85
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s4, s18
	s_cbranch_execz .LBB0_30
; %bb.29:                               ;   in Loop: Header=BB0_2 Depth=1
	v_frexp_mant_f32_e32 v0, v23
	v_min_f32_e32 v2, v21, v22
	v_cmp_gt_i32_e32 vcc_lo, 0, v19
	v_cmp_eq_f32_e64 s3, 0, v14
	v_cmp_class_f32_e64 s18, v19, 0x204
	v_rcp_f32_e32 v0, v0
	v_frexp_exp_i32_f32_e32 v3, v2
	v_frexp_mant_f32_e32 v2, v2
	v_cmp_class_f32_e64 s19, v14, 0x204
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v3, v20
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, v2, v0
	v_ldexp_f32 v0, v0, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, v0, v0
	v_fmaak_f32 v3, s8, v2, 0xbc7a590c
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v3, v2, v3, 0x3d29fb3f
	v_fmaak_f32 v3, v2, v3, 0xbd97d4d7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v3, v2, v3, 0x3dd931b2
	v_fmaak_f32 v3, v2, v3, 0xbe1160e6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v3, v2, v3, 0x3e4cb8bf
	v_fmaak_f32 v3, v2, v3, 0xbeaaaa62
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v2, v2, v3
	v_cndmask_b32_e64 v3, 0, 0x40490fdb, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, 0, v19
	v_fmac_f32_e32 v0, v0, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v2, 0x3fc90fdb, v0
	v_cndmask_b32_e64 v0, v0, v2, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v2, 0x40490fdb, v0
	v_cndmask_b32_e32 v0, v0, v2, vcc_lo
	v_mul_f32_e32 v2, 0.5, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v0, v0, v3, s3
	v_dual_mul_f32 v2, v1, v2 :: v_dual_cndmask_b32 v3, 0x3f490fdb, v16
	s_and_b32 vcc_lo, s19, s18
	s_delay_alu instid0(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v3, vcc_lo
.LBB0_30:                               ; %Flow86
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_31:                               ; %Flow88
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s17
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr23
                                        ; implicit-def: $vgpr20
.LBB0_32:                               ; %Flow89
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s4, s16
	s_cbranch_execz .LBB0_34
; %bb.33:                               ;   in Loop: Header=BB0_2 Depth=1
	v_div_scale_f32 v0, null, 0x402df854, 0x402df854, v19
	v_div_scale_f32 v1, null, 0x402df854, 0x402df854, v14
	v_div_scale_f32 v6, vcc_lo, v19, 0x402df854, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v2, v0
	v_rcp_f32_e32 v3, v1
	v_cmp_class_f32_e64 s16, v14, 0x204
	s_waitcnt_depctr 0xfff
	v_fma_f32 v4, -v0, v2, 1.0
	v_fma_f32 v5, -v1, v3, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v2, v4, v2 :: v_dual_fmac_f32 v3, v5, v3
	v_div_scale_f32 v4, s3, v14, 0x402df854, v14
	v_mul_f32_e32 v5, v6, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v7, v4, v3
	v_fma_f32 v8, -v0, v5, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v9, -v1, v7, v4
	v_fmac_f32_e32 v5, v8, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v7, v9, v3
	v_fma_f32 v0, -v0, v5, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v1, -v1, v7, v4
	v_div_fmas_f32 v0, v0, v2, v5
	s_mov_b32 vcc_lo, s3
	v_min_f32_e32 v5, v21, v22
	s_delay_alu instid0(VALU_DEP_3)
	v_div_fmas_f32 v1, v1, v3, v7
	v_frexp_mant_f32_e32 v3, v23
	v_div_fixup_f32 v0, v0, 0x402df854, v19
	v_cmp_class_f32_e64 s3, v19, 0x204
	v_frexp_exp_i32_f32_e32 v7, v5
	v_div_fixup_f32 v1, v1, 0x402df854, v14
	v_rcp_f32_e32 v3, v3
	v_frexp_mant_f32_e32 v5, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v7, v7, v20
	v_max_f32_e64 v2, |v0|, |v1|
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_frexp_exp_i32_f32_e32 v4, v2
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, v5, v3
	v_cmp_neq_f32_e64 vcc_lo, 0x7f800000, |v2|
	v_sub_nc_u32_e32 v6, 0, v4
	v_ldexp_f32 v3, v3, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_ldexp_f32 v1, |v1|, v6
	v_ldexp_f32 v0, |v0|, v6
	v_mul_f32_e32 v1, v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v1, v0, v0 :: v_dual_mul_f32 v0, v3, v3
	v_sqrt_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmaak_f32 v5, s8, v0, 0xbc7a590c
	v_fmaak_f32 v5, v0, v5, 0x3d29fb3f
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v1, v1, v4
	v_fmaak_f32 v4, v0, v5, 0xbd97d4d7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, 0x7f800000, v1, vcc_lo
	v_fmaak_f32 v2, v0, v4, 0x3dd931b2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_f32_e32 vcc_lo, 0x800000, v1
	v_fmaak_f32 v2, v0, v2, 0xbe1160e6
	v_cndmask_b32_e64 v4, 1.0, 0x4f800000, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmaak_f32 v2, v0, v2, 0x3e4cb8bf
	v_cndmask_b32_e64 v5, 0, 0x41b17218, vcc_lo
	v_dual_mul_f32 v1, v1, v4 :: v_dual_fmaak_f32 v2, v0, v2, 0xbeaaaa62
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_log_f32_e32 v1, v1
	v_mul_f32_e32 v0, v0, v2
	s_waitcnt_depctr 0xfff
	v_dual_fmac_f32 v3, v3, v0 :: v_dual_mul_f32 v2, 0x3f317217, v1
	v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v1|
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v0, 0x3f317217, v1, -v2
	v_fmac_f32_e32 v0, 0x3377d1cf, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v4, 0x3fc90fdb, v3
	v_add_f32_e32 v0, v2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v3, v3, v4, s2
	v_cmp_gt_i32_e64 s2, 0, v19
	v_cndmask_b32_e32 v0, v1, v0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v2, 0x40490fdb, v3
	v_cndmask_b32_e64 v4, 0, 0x40490fdb, s2
	v_cmp_gt_f32_e64 s2, 0, v19
	v_cmp_eq_f32_e32 vcc_lo, 0, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v1, v3, v2, s2
	v_cndmask_b32_e64 v3, 0x3f490fdb, v16, s2
	v_dual_sub_f32 v0, v0, v5 :: v_dual_cndmask_b32 v1, v1, v4
	s_and_b32 vcc_lo, s16, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_f32_e32 v2, 1.0, v0
	v_cndmask_b32_e32 v0, v1, v3, vcc_lo
.LBB0_34:                               ; %Flow90
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
                                        ; implicit-def: $vgpr19
.LBB0_35:                               ; %Flow92
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s2, s15
	s_cbranch_execz .LBB0_41
; %bb.36:                               ;   in Loop: Header=BB0_2 Depth=1
	v_cmp_ngt_f32_e64 s3, 0x20000000, |v19|
	v_cmp_ngt_f32_e64 s4, 0x20000000, |v14|
                                        ; implicit-def: $vgpr0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s3, s4, s3
	s_and_saveexec_b32 s4, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s3, exec_lo, s4
; %bb.37:                               ; %._crit_edge.i.i.i.i.i
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_mul_f32_e32 v0, v19, v19
                                        ; implicit-def: $vgpr19
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v0, v14, v14
; %bb.38:                               ; %Flow91
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s3, s3
; %bb.39:                               ;   in Loop: Header=BB0_2 Depth=1
	v_dual_mul_f32 v0, 4.0, v19 :: v_dual_mul_f32 v1, 4.0, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v0, v0, v0
	v_fmac_f32_e32 v0, v1, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v0, 0x3d800000, v0
; %bb.40:                               ; %_ZN6thrust4normIfEET_RKNS_7complexIS1_EE.exit.i.i.i.i
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
	v_cndmask_b32_e64 v1, 1.0, 0x4f800000, vcc_lo
	v_mul_f32_e32 v0, v0, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_log_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x3f317217, v0
	v_fma_f32 v2, 0x3f317217, v0, -v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v2, 0x3377d1cf, v0
	v_add_f32_e32 v1, v1, v2
	v_cndmask_b32_e64 v2, 0, 0x41b17218, vcc_lo
	v_cmp_gt_f32_e64 vcc_lo, 0x7f800000, |v0|
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v1, vcc_lo
	v_sub_f32_e32 v2, v0, v2
	v_mov_b32_e32 v0, 0x7fc00000
.LBB0_41:                               ; %Flow93
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_bfi_b32 v0, 0x7fffffff, v0, v14
                                        ; implicit-def: $vgpr3
	s_mov_b32 s2, exec_lo
	v_add_f32_e32 v2, v2, v2
	v_add_f32_e32 v0, v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_b32_e32 v1, 0x7fffffff, v0
	v_cmpx_ne_u32_e32 0, v1
	s_xor_b32 s4, exec_lo, s2
	s_cbranch_execz .LBB0_83
; %bb.42:                               ;   in Loop: Header=BB0_2 Depth=1
	v_and_b32_e32 v4, 0x7fffffff, v2
                                        ; implicit-def: $vgpr3
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ne_u32_e32 0, v4
	s_xor_b32 s15, exec_lo, s2
	s_cbranch_execz .LBB0_72
; %bb.43:                               ;   in Loop: Header=BB0_2 Depth=1
                                        ; implicit-def: $vgpr3
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_u32_e32 0x7f800000, v1
	s_xor_b32 s16, exec_lo, s2
	s_cbranch_execz .LBB0_65
; %bb.44:                               ;   in Loop: Header=BB0_2 Depth=1
	v_add_nc_u32_e32 v3, 0xbd4e8de8, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_lt_u32_e32 vcc_lo, 0x8e8e5c, v3
                                        ; implicit-def: $vgpr3
	s_and_saveexec_b32 s2, vcc_lo
	s_xor_b32 s17, exec_lo, s2
	s_cbranch_execz .LBB0_54
; %bb.45:                               ;   in Loop: Header=BB0_2 Depth=1
	v_cmp_ngt_f32_e64 s18, 0x48000000, |v0|
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s2, s18
	s_xor_b32 s19, exec_lo, s2
	s_cbranch_execz .LBB0_47
; %bb.46:                               ;   in Loop: Header=BB0_2 Depth=1
	v_and_or_b32 v11, v1, s9, 0x800000
	v_lshrrev_b32_e32 v8, 23, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[3:4], null, 0xfe5163ab, v11, 0
	v_add_nc_u32_e32 v9, 0xffffff88, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v9
	v_mov_b32_e32 v14, v4
	v_cndmask_b32_e64 v10, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[4:5], null, 0x3c439041, v11, v[14:15]
	v_add_nc_u32_e32 v10, v10, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u32_e64 s2, 31, v10
	v_cndmask_b32_e64 v19, 0, 0xffffffe0, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v14, v5 :: v_dual_add_nc_u32 v19, v19, v10
	v_mad_u64_u32 v[5:6], null, 0xdb629599, v11, v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s3, 31, v19
	v_dual_mov_b32 v14, v6 :: v_dual_cndmask_b32 v3, v5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, 0xf534ddc0, v11, v[14:15]
	v_mov_b32_e32 v14, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v4, v6, v4, vcc_lo
	v_mad_u64_u32 v[7:8], null, 0xfc2757d1, v11, v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v3, v4, v3, s2
	v_mov_b32_e32 v14, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, 0x4e441529, v11, v[14:15]
	v_mov_b32_e32 v14, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[9:10], null, 0xa2f9836e, v11, v[14:15]
	v_cndmask_b32_e64 v11, 0, 0xffffffe0, s3
	v_dual_cndmask_b32 v14, v8, v6 :: v_dual_cndmask_b32 v9, v9, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v8, v10, v8 :: v_dual_cndmask_b32 v7, v7, v5
	v_add_nc_u32_e32 v10, v11, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v6, v9, v14, s2
	v_cndmask_b32_e64 v8, v8, v9, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v9, v14, v7, s2
	v_sub_nc_u32_e32 v11, 32, v10
	v_cndmask_b32_e64 v7, v7, v4, s2
	v_cmp_eq_u32_e32 vcc_lo, 0, v10
	v_cndmask_b32_e64 v8, v8, v6, s3
	v_cndmask_b32_e64 v6, v6, v9, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v9, v9, v7, s3
	v_cndmask_b32_e64 v3, v7, v3, s3
	v_alignbit_b32 v14, v8, v6, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v5, v6, v9, v11
	v_alignbit_b32 v10, v9, v3, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v8, v14, v8, vcc_lo
	v_dual_cndmask_b32 v4, v5, v6 :: v_dual_cndmask_b32 v9, v10, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_bfe_u32 v5, v8, 29, 1
	v_alignbit_b32 v6, v8, v4, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_alignbit_b32 v4, v4, v9, 30
	v_alignbit_b32 v3, v9, v3, 30
	v_sub_nc_u32_e32 v7, 0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v6, v6, v7
	v_xor_b32_e32 v4, v4, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v3, v3, v7
	v_lshrrev_b32_e32 v7, 29, v8
	v_clz_i32_u32_e32 v10, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v7, 31, v7
	v_min_u32_e32 v10, 32, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v11, 0.5, v7
	v_sub_nc_u32_e32 v9, 31, v10
	v_lshlrev_b32_e32 v14, 23, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v6, v6, v4, v9
	v_alignbit_b32 v3, v4, v3, v9
	v_sub_nc_u32_e32 v11, v11, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v4, v6, v3, 9
	v_lshrrev_b32_e32 v6, 9, v6
	v_clz_i32_u32_e32 v9, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v9, 32, v9
	v_sub_nc_u32_e32 v19, 31, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_alignbit_b32 v3, v4, v3, v19
	v_or_b32_e32 v4, v6, v11
	v_add_lshl_u32 v6, v9, v10, 23
	v_lshrrev_b32_e32 v3, 9, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v9, 0x3fc90fda, v4
	v_sub_nc_u32_e32 v3, v3, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v6, 0x3fc90fda, v4, -v9
	v_add_nc_u32_e32 v3, 0x33000000, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v6, 0x33a22168, v4
	v_lshrrev_b32_e32 v4, 30, v8
	v_or_b32_e32 v3, v3, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v5, v4
	v_fmac_f32_e32 v6, 0x3fc90fda, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v3, v9, v6
.LBB0_47:                               ; %Flow65
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s2, s19
; %bb.48:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mul_f32_e64 v3, 0x3f22f983, |v0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v4, v3
	v_fma_f32 v3, 0xbfc90fda, v4, |v0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v3, 0xb3a22168, v4
	v_fmac_f32_e32 v3, 0xa7c234c4, v4
	v_cvt_i32_f32_e32 v4, v4
; %bb.49:                               ; %_ZL3cosf.exit21.i.i.i.i
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
                                        ; implicit-def: $vgpr6
                                        ; implicit-def: $vgpr5
	s_and_saveexec_b32 s2, s18
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s18, exec_lo, s2
	s_cbranch_execz .LBB0_51
; %bb.50:                               ;   in Loop: Header=BB0_2 Depth=1
	v_and_or_b32 v21, v1, s9, 0x800000
	v_lshrrev_b32_e32 v10, 23, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[5:6], null, 0xfe5163ab, v21, 0
	v_add_nc_u32_e32 v11, 0xffffff88, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v11
	v_mov_b32_e32 v14, v6
	v_cndmask_b32_e64 v19, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[6:7], null, 0x3c439041, v21, v[14:15]
	v_add_nc_u32_e32 v19, v19, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u32_e64 s2, 31, v19
	v_cndmask_b32_e64 v20, 0, 0xffffffe0, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v14, v7
	v_mad_u64_u32 v[7:8], null, 0xdb629599, v21, v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v14, v8
	v_mad_u64_u32 v[8:9], null, 0xf534ddc0, v21, v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v14, v9
	v_cndmask_b32_e32 v6, v8, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, 0xfc2757d1, v21, v[14:15]
	v_mov_b32_e32 v14, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[10:11], null, 0x4e441529, v21, v[14:15]
	v_dual_mov_b32 v14, v11 :: v_dual_add_nc_u32 v11, v20, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[19:20], null, 0xa2f9836e, v21, v[14:15]
	v_cmp_lt_u32_e64 s3, 31, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v21, v10, v8, vcc_lo
	v_cndmask_b32_e64 v14, 0, 0xffffffe0, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v19, v19, v9 :: v_dual_cndmask_b32 v10, v20, v10
	v_cndmask_b32_e32 v9, v9, v7, vcc_lo
	v_add_nc_u32_e32 v11, v14, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v8, v19, v21, s2
	v_cndmask_b32_e64 v10, v10, v19, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v14, v21, v9, s2
	v_cndmask_b32_e64 v9, v9, v6, s2
	v_sub_nc_u32_e32 v19, 32, v11
	v_cndmask_b32_e64 v10, v10, v8, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v8, v8, v14, s3
	v_cndmask_b32_e64 v14, v14, v9, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_alignbit_b32 v20, v10, v8, v19
	v_cndmask_b32_e32 v5, v7, v5, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v11
	v_alignbit_b32 v7, v8, v14, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v10, v20, v10, vcc_lo
	v_cndmask_b32_e64 v5, v6, v5, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v6, v7, v8, vcc_lo
	v_bfe_u32 v7, v10, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v5, v9, v5, s3
	v_alignbit_b32 v8, v10, v6, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v9, 0, v7
	v_alignbit_b32 v11, v14, v5, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v8, v8, v9
	v_cndmask_b32_e32 v11, v11, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_clz_i32_u32_e32 v14, v8
	v_alignbit_b32 v6, v6, v11, 30
	v_alignbit_b32 v5, v11, v5, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_min_u32_e32 v14, 32, v14
	v_xor_b32_e32 v6, v6, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v5, v5, v9
	v_lshrrev_b32_e32 v9, 29, v10
	v_sub_nc_u32_e32 v11, 31, v14
	v_lshlrev_b32_e32 v20, 23, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v9, 31, v9
	v_alignbit_b32 v8, v8, v6, v11
	v_alignbit_b32 v5, v6, v5, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v19, 0.5, v9
	v_alignbit_b32 v6, v8, v5, 9
	v_lshrrev_b32_e32 v8, 9, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v19, v19, v20
	v_clz_i32_u32_e32 v11, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v11, 32, v11
	v_sub_nc_u32_e32 v21, 31, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_alignbit_b32 v5, v6, v5, v21
	v_or_b32_e32 v6, v8, v19
	v_add_lshl_u32 v8, v11, v14, 23
	v_lshrrev_b32_e32 v5, 9, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v11, 0x3fc90fda, v6
	v_sub_nc_u32_e32 v5, v5, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v8, 0x3fc90fda, v6, -v11
	v_add_nc_u32_e32 v5, 0x33000000, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v8, 0x33a22168, v6
	v_lshrrev_b32_e32 v6, 30, v10
	v_or_b32_e32 v5, v5, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, v7, v6
	v_fmac_f32_e32 v8, 0x3fc90fda, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v5, v11, v8
.LBB0_51:                               ; %Flow
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s2, s18
; %bb.52:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mul_f32_e64 v5, 0x3f22f983, |v0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v6, v5
	v_fma_f32 v5, 0xbfc90fda, v6, |v0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, 0xb3a22168, v6
	v_fmac_f32_e32 v5, 0xa7c234c4, v6
	v_cvt_i32_f32_e32 v6, v6
; %bb.53:                               ; %_ZL3sinf.exit29.i.i.i.i
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	v_dual_mul_f32 v7, 0x3fb8aa3b, v2 :: v_dual_mul_f32 v8, v3, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v14, v5, v5 :: v_dual_and_b32 v9, 1, v4
	v_and_b32_e32 v19, 1, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_rndne_f32_e32 v10, v7
	v_fmaak_f32 v20, s10, v8, 0x3c0881c4
	v_fma_f32 v11, 0x3fb8aa3b, v2, -v7
	v_lshlrev_b32_e32 v4, 30, v4
	v_dual_fmaak_f32 v21, s5, v8, 0xbab64f3b :: v_dual_lshlrev_b32 v6, 30, v6
	v_sub_f32_e32 v7, v7, v10
	s_delay_alu instid0(VALU_DEP_4)
	v_fmac_f32_e32 v11, 0x32a5705f, v2
	v_fmaak_f32 v22, s10, v14, 0x3c0881c4
	v_fmaak_f32 v23, s5, v14, 0xbab64f3b
	v_cmp_eq_u32_e32 vcc_lo, 0, v9
	v_cvt_i32_f32_e32 v10, v10
	v_add_f32_e32 v7, v7, v11
	v_fmaak_f32 v11, v8, v20, 0xbe2aaa9d
	v_and_or_b32 v1, 0x80000000, v6, v1
	v_cmp_nlt_f32_e64 s2, 0x42b17218, v2
	v_and_b32_e32 v4, 0x80000000, v4
	v_exp_f32_e32 v7, v7
	v_mul_f32_e32 v11, v8, v11
	v_fmaak_f32 v20, v8, v21, 0x3d2aabf7
	v_fmaak_f32 v21, v14, v22, 0xbe2aaa9d
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v21, v14, v21
	v_fmaak_f32 v22, v14, v23, 0x3d2aabf7
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v7, v7, v10
	v_dual_fmac_f32 v5, v5, v21 :: v_dual_fmaak_f32 v22, v14, v22, 0xbf000004
	v_fmac_f32_e32 v3, v3, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f32 v11, v14, v22, 1.0
	v_fmaak_f32 v20, v8, v20, 0xbf000004
	v_fma_f32 v8, v8, v20, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v3, -v3, v8, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v19
	v_xor_b32_e32 v3, v4, v3
	v_cndmask_b32_e32 v5, v11, v5, vcc_lo
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v2
	v_cndmask_b32_e32 v6, 0, v7, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v0, 0x1f8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor3_b32 v0, v1, v5, v0
	v_cndmask_b32_e64 v1, 0x7f800000, v6, s2
	v_cndmask_b32_e32 v2, 0x7fc00000, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v0, 0x7fc00000, v0 :: v_dual_mul_f32 v3, v1, v2
	v_mul_f32_e32 v0, v1, v0
                                        ; implicit-def: $vgpr2
                                        ; implicit-def: $vgpr1
.LBB0_54:                               ; %Flow68
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s17, s17
	s_cbranch_execz .LBB0_64
; %bb.55:                               ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ngt_f32_e64 s18, 0x48000000, |v0|
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr3
	s_and_saveexec_b32 s2, s18
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s19, exec_lo, s2
	s_cbranch_execz .LBB0_57
; %bb.56:                               ;   in Loop: Header=BB0_2 Depth=1
	v_and_or_b32 v11, v1, s9, 0x800000
	v_lshrrev_b32_e32 v8, 23, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[3:4], null, 0xfe5163ab, v11, 0
	v_add_nc_u32_e32 v9, 0xffffff88, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v9
	v_mov_b32_e32 v14, v4
	v_cndmask_b32_e64 v10, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[4:5], null, 0x3c439041, v11, v[14:15]
	v_add_nc_u32_e32 v10, v10, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u32_e64 s2, 31, v10
	v_cndmask_b32_e64 v19, 0, 0xffffffe0, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v14, v5 :: v_dual_add_nc_u32 v19, v19, v10
	v_mad_u64_u32 v[5:6], null, 0xdb629599, v11, v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s3, 31, v19
	v_dual_mov_b32 v14, v6 :: v_dual_cndmask_b32 v3, v5, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, 0xf534ddc0, v11, v[14:15]
	v_mov_b32_e32 v14, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v4, v6, v4, vcc_lo
	v_mad_u64_u32 v[7:8], null, 0xfc2757d1, v11, v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v3, v4, v3, s2
	v_mov_b32_e32 v14, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, 0x4e441529, v11, v[14:15]
	v_mov_b32_e32 v14, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[9:10], null, 0xa2f9836e, v11, v[14:15]
	v_cndmask_b32_e64 v11, 0, 0xffffffe0, s3
	v_dual_cndmask_b32 v14, v8, v6 :: v_dual_cndmask_b32 v9, v9, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v8, v10, v8 :: v_dual_cndmask_b32 v7, v7, v5
	v_add_nc_u32_e32 v10, v11, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v6, v9, v14, s2
	v_cndmask_b32_e64 v8, v8, v9, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v9, v14, v7, s2
	v_sub_nc_u32_e32 v11, 32, v10
	v_cndmask_b32_e64 v7, v7, v4, s2
	v_cmp_eq_u32_e32 vcc_lo, 0, v10
	v_cndmask_b32_e64 v8, v8, v6, s3
	v_cndmask_b32_e64 v6, v6, v9, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v9, v9, v7, s3
	v_cndmask_b32_e64 v3, v7, v3, s3
	v_alignbit_b32 v14, v8, v6, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v5, v6, v9, v11
	v_alignbit_b32 v10, v9, v3, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v8, v14, v8, vcc_lo
	v_dual_cndmask_b32 v4, v5, v6 :: v_dual_cndmask_b32 v9, v10, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_bfe_u32 v5, v8, 29, 1
	v_alignbit_b32 v6, v8, v4, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_alignbit_b32 v4, v4, v9, 30
	v_alignbit_b32 v3, v9, v3, 30
	v_sub_nc_u32_e32 v7, 0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v6, v6, v7
	v_xor_b32_e32 v4, v4, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v3, v3, v7
	v_lshrrev_b32_e32 v7, 29, v8
	v_clz_i32_u32_e32 v10, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v7, 31, v7
	v_min_u32_e32 v10, 32, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v11, 0.5, v7
	v_sub_nc_u32_e32 v9, 31, v10
	v_lshlrev_b32_e32 v14, 23, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v6, v6, v4, v9
	v_alignbit_b32 v3, v4, v3, v9
	v_sub_nc_u32_e32 v11, v11, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v4, v6, v3, 9
	v_lshrrev_b32_e32 v6, 9, v6
	v_clz_i32_u32_e32 v9, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v9, 32, v9
	v_sub_nc_u32_e32 v19, 31, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_alignbit_b32 v3, v4, v3, v19
	v_or_b32_e32 v4, v6, v11
	v_add_lshl_u32 v6, v9, v10, 23
	v_lshrrev_b32_e32 v3, 9, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v9, 0x3fc90fda, v4
	v_sub_nc_u32_e32 v3, v3, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v6, 0x3fc90fda, v4, -v9
	v_add_nc_u32_e32 v3, 0x33000000, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v6, 0x33a22168, v4
	v_lshrrev_b32_e32 v4, 30, v8
	v_or_b32_e32 v3, v3, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v5, v4
	v_fmac_f32_e32 v6, 0x3fc90fda, v3
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v3, v9, v6
.LBB0_57:                               ; %Flow67
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s2, s19
; %bb.58:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mul_f32_e64 v3, 0x3f22f983, |v0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v4, v3
	v_fma_f32 v3, 0xbfc90fda, v4, |v0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v3, 0xb3a22168, v4
	v_fmac_f32_e32 v3, 0xa7c234c4, v4
	v_cvt_i32_f32_e32 v4, v4
; %bb.59:                               ; %_ZL3cosf.exit.i.i.i.i.i
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
                                        ; implicit-def: $vgpr6
                                        ; implicit-def: $vgpr5
	s_and_saveexec_b32 s2, s18
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s18, exec_lo, s2
	s_cbranch_execz .LBB0_61
; %bb.60:                               ;   in Loop: Header=BB0_2 Depth=1
	v_and_or_b32 v21, v1, s9, 0x800000
	v_lshrrev_b32_e32 v10, 23, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[5:6], null, 0xfe5163ab, v21, 0
	v_add_nc_u32_e32 v11, 0xffffff88, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e32 vcc_lo, 63, v11
	v_mov_b32_e32 v14, v6
	v_cndmask_b32_e64 v19, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[6:7], null, 0x3c439041, v21, v[14:15]
	v_add_nc_u32_e32 v19, v19, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_u32_e64 s2, 31, v19
	v_cndmask_b32_e64 v20, 0, 0xffffffe0, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v14, v7
	v_mad_u64_u32 v[7:8], null, 0xdb629599, v21, v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v14, v8
	v_mad_u64_u32 v[8:9], null, 0xf534ddc0, v21, v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v14, v9
	v_cndmask_b32_e32 v6, v8, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, 0xfc2757d1, v21, v[14:15]
	v_mov_b32_e32 v14, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[10:11], null, 0x4e441529, v21, v[14:15]
	v_dual_mov_b32 v14, v11 :: v_dual_add_nc_u32 v11, v20, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[19:20], null, 0xa2f9836e, v21, v[14:15]
	v_cmp_lt_u32_e64 s3, 31, v11
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v21, v10, v8, vcc_lo
	v_cndmask_b32_e64 v14, 0, 0xffffffe0, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v19, v19, v9 :: v_dual_cndmask_b32 v10, v20, v10
	v_cndmask_b32_e32 v9, v9, v7, vcc_lo
	v_add_nc_u32_e32 v11, v14, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v8, v19, v21, s2
	v_cndmask_b32_e64 v10, v10, v19, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v14, v21, v9, s2
	v_cndmask_b32_e64 v9, v9, v6, s2
	v_sub_nc_u32_e32 v19, 32, v11
	v_cndmask_b32_e64 v10, v10, v8, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v8, v8, v14, s3
	v_cndmask_b32_e64 v14, v14, v9, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_alignbit_b32 v20, v10, v8, v19
	v_cndmask_b32_e32 v5, v7, v5, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v11
	v_alignbit_b32 v7, v8, v14, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v10, v20, v10, vcc_lo
	v_cndmask_b32_e64 v5, v6, v5, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v6, v7, v8, vcc_lo
	v_bfe_u32 v7, v10, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v5, v9, v5, s3
	v_alignbit_b32 v8, v10, v6, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v9, 0, v7
	v_alignbit_b32 v11, v14, v5, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v8, v8, v9
	v_cndmask_b32_e32 v11, v11, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_clz_i32_u32_e32 v14, v8
	v_alignbit_b32 v6, v6, v11, 30
	v_alignbit_b32 v5, v11, v5, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_min_u32_e32 v14, 32, v14
	v_xor_b32_e32 v6, v6, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v5, v5, v9
	v_lshrrev_b32_e32 v9, 29, v10
	v_sub_nc_u32_e32 v11, 31, v14
	v_lshlrev_b32_e32 v20, 23, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b32_e32 v9, 31, v9
	v_alignbit_b32 v8, v8, v6, v11
	v_alignbit_b32 v5, v6, v5, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v19, 0.5, v9
	v_alignbit_b32 v6, v8, v5, 9
	v_lshrrev_b32_e32 v8, 9, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v19, v19, v20
	v_clz_i32_u32_e32 v11, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v11, 32, v11
	v_sub_nc_u32_e32 v21, 31, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_alignbit_b32 v5, v6, v5, v21
	v_or_b32_e32 v6, v8, v19
	v_add_lshl_u32 v8, v11, v14, 23
	v_lshrrev_b32_e32 v5, 9, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v11, 0x3fc90fda, v6
	v_sub_nc_u32_e32 v5, v5, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v8, 0x3fc90fda, v6, -v11
	v_add_nc_u32_e32 v5, 0x33000000, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v8, 0x33a22168, v6
	v_lshrrev_b32_e32 v6, 30, v10
	v_or_b32_e32 v5, v5, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v6, v7, v6
	v_fmac_f32_e32 v8, 0x3fc90fda, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f32_e32 v5, v11, v8
.LBB0_61:                               ; %Flow66
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s2, s18
; %bb.62:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mul_f32_e64 v5, 0x3f22f983, |v0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v6, v5
	v_fma_f32 v5, 0xbfc90fda, v6, |v0|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, 0xb3a22168, v6
	v_fmac_f32_e32 v5, 0xa7c234c4, v6
	v_cvt_i32_f32_e32 v6, v6
; %bb.63:                               ; %_ZN6thrust6detail7complex11ldexp_cexpfENS_7complexIfEEi.exit.i.i.i.i
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	v_add_f32_e32 v2, 0xc322e3bc, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v10, v3, v3 :: v_dual_mul_f32 v11, v5, v5
	v_mul_f32_e32 v7, 0x3fb8aa3b, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmaak_f32 v19, s10, v10, 0x3c0881c4 :: v_dual_fmaak_f32 v20, s10, v11, 0x3c0881c4
	v_fmaak_f32 v14, s5, v10, 0xbab64f3b
	v_fma_f32 v8, 0x3fb8aa3b, v2, -v7
	v_rndne_f32_e32 v9, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmaak_f32 v20, v11, v20, 0xbe2aaa9d
	v_dual_sub_f32 v7, v7, v9 :: v_dual_fmac_f32 v8, 0x32a5705f, v2
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v20, v11, v20
	v_add_f32_e32 v7, v7, v8
	v_cvt_i32_f32_e32 v8, v9
	v_lshlrev_b32_e32 v9, 30, v4
	v_and_b32_e32 v4, 1, v4
	v_fmac_f32_e32 v5, v5, v20
	v_exp_f32_e32 v7, v7
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v7, v7, v8
	v_and_b32_e32 v8, 1, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v7, 0, v7 :: v_dual_lshlrev_b32 v6, 30, v6
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v2
	v_and_or_b32 v1, 0x80000000, v6, v1
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e32 v2, 0x7f800000, v7, vcc_lo
	v_fmaak_f32 v7, s5, v11, 0xbab64f3b
	v_fmaak_f32 v6, v10, v14, 0x3d2aabf7
	v_fmaak_f32 v14, v10, v19, 0xbe2aaa9d
	v_and_b32_e32 v9, 0x80000000, v9
	v_cmp_eq_u32_e32 vcc_lo, 0, v4
	v_fmaak_f32 v7, v11, v7, 0x3d2aabf7
	v_fmaak_f32 v6, v10, v6, 0xbf000004
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v14, v10, v14 :: v_dual_fmaak_f32 v7, v11, v7, 0xbf000004
	v_fma_f32 v6, v10, v6, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v3, v3, v14
	v_lshrrev_b32_e32 v19, 23, v2
	v_and_or_b32 v2, 0x7fffff, v2, s11
	v_fma_f32 v7, v11, v7, 1.0
	v_cndmask_b32_e64 v3, -v3, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_subrev_nc_u32_e32 v19, 19, v19
	v_cmp_eq_u32_e32 vcc_lo, 0, v8
	v_xor_b32_e32 v3, v9, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_lshrrev_b16 v10, 15, v19
	v_cndmask_b32_e32 v5, v7, v5, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v0, 0x1f8
	v_add_nc_u16 v4, v19, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor3_b32 v1, v1, v5, v0
	v_ashrrev_i16 v4, 1, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v1, 0x7fc00000, v1, vcc_lo
	v_dual_mul_f32 v1, v1, v2 :: v_dual_cndmask_b32 v0, 0x7fc00000, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_bfe_i32 v3, v4, 0, 16
	v_lshl_add_u32 v4, v3, 23, 1.0
	v_sub_nc_u32_e32 v3, v19, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v1, v1, v4 :: v_dual_mul_f32 v0, v0, v2
	v_lshl_add_u32 v2, v3, 23, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v0, v0, v4
	v_mul_f32_e32 v3, v0, v2
	s_delay_alu instid0(VALU_DEP_4)
	v_mul_f32_e32 v0, v1, v2
.LBB0_64:                               ; %Flow69
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s17
                                        ; implicit-def: $vgpr2
                                        ; implicit-def: $vgpr4
.LBB0_65:                               ; %Flow72
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s2, s16
	s_cbranch_execz .LBB0_71
; %bb.66:                               ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_sub_f32_e32 v0, v0, v0
	s_mov_b32 s3, exec_lo
	v_cmpx_ne_u32_e32 0x7f800000, v4
	s_xor_b32 s3, exec_lo, s3
; %bb.67:                               ;   in Loop: Header=BB0_2 Depth=1
                                        ; implicit-def: $vgpr2
; %bb.68:                               ; %Flow70
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_saveexec_b32 s3, s3
	v_mov_b32_e32 v3, v0
	s_xor_b32 exec_lo, exec_lo, s3
; %bb.69:                               ;   in Loop: Header=BB0_2 Depth=1
	v_cmp_lt_i32_e32 vcc_lo, -1, v2
	v_dual_cndmask_b32 v3, 0, v2 :: v_dual_cndmask_b32 v0, 0, v0
; %bb.70:                               ; %Flow71
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
.LBB0_71:                               ; %Flow73
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s2
                                        ; implicit-def: $vgpr1
.LBB0_72:                               ; %Flow76
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s15, s15
	s_cbranch_execz .LBB0_82
; %bb.73:                               ;   in Loop: Header=BB0_2 Depth=1
	v_lshrrev_b32_e32 v2, 23, v1
	v_cmp_ngt_f32_e64 s16, 0x48000000, |v0|
	v_and_or_b32 v4, v1, s9, 0x800000
                                        ; implicit-def: $vgpr3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v5, 0xffffff88, v2
                                        ; implicit-def: $vgpr2
	s_and_saveexec_b32 s2, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s17, exec_lo, s2
	s_cbranch_execz .LBB0_75
; %bb.74:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mad_u64_u32 v[2:3], null, 0xfe5163ab, v4, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v14, v3
	v_cndmask_b32_e64 v3, 0, 0xffffffc0, vcc_lo
	v_mad_u64_u32 v[6:7], null, 0x3c439041, v4, v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v3, v3, v5
	v_cmp_lt_u32_e64 s2, 31, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v14, v7
	v_cndmask_b32_e64 v19, 0, 0xffffffe0, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[7:8], null, 0xdb629599, v4, v[14:15]
	v_dual_mov_b32 v14, v8 :: v_dual_add_nc_u32 v3, v19, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v2, v7, v2, vcc_lo
	v_cmp_lt_u32_e64 s3, 31, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[8:9], null, 0xf534ddc0, v4, v[14:15]
	v_mov_b32_e32 v14, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v6, v8, v6, vcc_lo
	v_mad_u64_u32 v[9:10], null, 0xfc2757d1, v4, v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v2, v6, v2, s2
	v_mov_b32_e32 v14, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[10:11], null, 0x4e441529, v4, v[14:15]
	v_mov_b32_e32 v14, v11
	v_cndmask_b32_e64 v11, 0, 0xffffffe0, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[19:20], null, 0xa2f9836e, v4, v[14:15]
	v_dual_cndmask_b32 v14, v10, v8 :: v_dual_add_nc_u32 v3, v11, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v19, v19, v9 :: v_dual_cndmask_b32 v10, v20, v10
	v_cndmask_b32_e32 v9, v9, v7, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v8, v19, v14, s2
	v_cndmask_b32_e64 v10, v10, v19, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v11, v14, v9, s2
	v_sub_nc_u32_e32 v14, 32, v3
	v_cndmask_b32_e64 v9, v9, v6, s2
	v_cndmask_b32_e64 v10, v10, v8, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v8, v8, v11, s3
	v_cndmask_b32_e64 v11, v11, v9, s3
	v_cndmask_b32_e64 v2, v9, v2, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v19, v10, v8, v14
	v_alignbit_b32 v7, v8, v11, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v3, v19, v10, vcc_lo
	v_alignbit_b32 v10, v11, v2, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v6, v7, v8, vcc_lo
	v_cndmask_b32_e32 v10, v10, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v7, v3, 29, 1
	v_alignbit_b32 v8, v3, v6, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v6, v6, v10, 30
	v_sub_nc_u32_e32 v9, 0, v7
	v_alignbit_b32 v2, v10, v2, 30
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v8, v8, v9
	v_xor_b32_e32 v6, v6, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v2, v2, v9
	v_lshrrev_b32_e32 v9, 29, v3
	v_lshrrev_b32_e32 v3, 30, v3
	v_clz_i32_u32_e32 v11, v8
	v_lshlrev_b32_e32 v9, 31, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v3, v7, v3
	v_min_u32_e32 v11, 32, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v14, 0.5, v9
	v_sub_nc_u32_e32 v10, 31, v11
	v_lshlrev_b32_e32 v19, 23, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v8, v8, v6, v10
	v_alignbit_b32 v2, v6, v2, v10
	v_sub_nc_u32_e32 v14, v14, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v6, v8, v2, 9
	v_lshrrev_b32_e32 v8, 9, v8
	v_clz_i32_u32_e32 v10, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v10, 32, v10
	v_sub_nc_u32_e32 v20, 31, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_alignbit_b32 v2, v6, v2, v20
	v_or_b32_e32 v6, v8, v14
	v_add_lshl_u32 v8, v10, v11, 23
	v_lshrrev_b32_e32 v2, 9, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v10, 0x3fc90fda, v6
	v_sub_nc_u32_e32 v2, v2, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v8, 0x3fc90fda, v6, -v10
	v_add_nc_u32_e32 v2, 0x33000000, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v8, 0x33a22168, v6
	v_or_b32_e32 v2, v2, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v8, 0x3fc90fda, v2
	v_add_f32_e32 v2, v10, v8
.LBB0_75:                               ; %Flow75
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_saveexec_b32 s2, s17
	v_mul_f32_e64 v6, 0x3f22f983, |v0|
	s_delay_alu instid0(VALU_DEP_1)
	v_rndne_f32_e32 v8, v6
	s_xor_b32 exec_lo, exec_lo, s2
; %bb.76:                               ;   in Loop: Header=BB0_2 Depth=1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v2, 0xbfc90fda, v8, |v0|
	v_cvt_i32_f32_e32 v3, v8
	v_fmac_f32_e32 v2, 0xb3a22168, v8
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v2, 0xa7c234c4, v8
; %bb.77:                               ; %_ZL3cosf.exit.i.i.i.i
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
                                        ; implicit-def: $vgpr7
                                        ; implicit-def: $vgpr6
	s_and_saveexec_b32 s2, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s16, exec_lo, s2
	s_cbranch_execz .LBB0_79
; %bb.78:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mad_u64_u32 v[6:7], null, 0xfe5163ab, v4, 0
	v_cmp_lt_u32_e32 vcc_lo, 63, v5
	v_cndmask_b32_e64 v19, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v14, v7
	v_add_nc_u32_e32 v5, v19, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[7:8], null, 0x3c439041, v4, v[14:15]
	v_cmp_lt_u32_e64 s2, 31, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mov_b32_e32 v14, v8
	v_mad_u64_u32 v[8:9], null, 0xdb629599, v4, v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v14, v9
	v_cndmask_b32_e32 v6, v8, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[9:10], null, 0xf534ddc0, v4, v[14:15]
	v_mov_b32_e32 v14, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[10:11], null, 0xfc2757d1, v4, v[14:15]
	v_mov_b32_e32 v14, v11
	v_cndmask_b32_e64 v11, 0, 0xffffffe0, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[19:20], null, 0x4e441529, v4, v[14:15]
	v_add_nc_u32_e32 v5, v11, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s3, 31, v5
	v_dual_mov_b32 v14, v20 :: v_dual_cndmask_b32 v11, v19, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[20:21], null, 0xa2f9836e, v4, v[14:15]
	v_cndmask_b32_e64 v4, 0, 0xffffffe0, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v4, v4, v5
	v_dual_cndmask_b32 v14, v20, v10 :: v_dual_cndmask_b32 v19, v21, v19
	v_dual_cndmask_b32 v10, v10, v8 :: v_dual_cndmask_b32 v5, v9, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_eq_u32_e32 vcc_lo, 0, v4
	v_cndmask_b32_e64 v7, v14, v11, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v9, v19, v14, s2
	v_cndmask_b32_e64 v11, v11, v10, s2
	v_sub_nc_u32_e32 v14, 32, v4
	v_cndmask_b32_e64 v10, v10, v5, s2
	v_cndmask_b32_e64 v5, v5, v6, s2
	v_cndmask_b32_e64 v9, v9, v7, s3
	v_cndmask_b32_e64 v7, v7, v11, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v11, v11, v10, s3
	v_cndmask_b32_e64 v5, v10, v5, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v19, v9, v7, v14
	v_alignbit_b32 v8, v7, v11, v14
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v10, v11, v5, v14
	v_cndmask_b32_e32 v4, v19, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v6, v8, v7, vcc_lo
	v_cndmask_b32_e32 v10, v10, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_bfe_u32 v7, v4, 29, 1
	v_alignbit_b32 v8, v4, v6, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_alignbit_b32 v6, v6, v10, 30
	v_alignbit_b32 v5, v10, v5, 30
	v_sub_nc_u32_e32 v9, 0, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v8, v8, v9
	v_xor_b32_e32 v6, v6, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v5, v5, v9
	v_lshrrev_b32_e32 v9, 29, v4
	v_lshrrev_b32_e32 v4, 30, v4
	v_clz_i32_u32_e32 v11, v8
	v_lshlrev_b32_e32 v9, 31, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v7, v7, v4
	v_min_u32_e32 v11, 32, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v14, 0.5, v9
	v_sub_nc_u32_e32 v10, 31, v11
	v_lshlrev_b32_e32 v19, 23, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v8, v8, v6, v10
	v_alignbit_b32 v5, v6, v5, v10
	v_sub_nc_u32_e32 v14, v14, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v6, v8, v5, 9
	v_lshrrev_b32_e32 v8, 9, v8
	v_clz_i32_u32_e32 v10, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v10, 32, v10
	v_sub_nc_u32_e32 v20, 31, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_alignbit_b32 v5, v6, v5, v20
	v_or_b32_e32 v6, v8, v14
	v_add_lshl_u32 v8, v10, v11, 23
	v_lshrrev_b32_e32 v5, 9, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v10, 0x3fc90fda, v6
	v_sub_nc_u32_e32 v5, v5, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v8, 0x3fc90fda, v6, -v10
	v_add_nc_u32_e32 v5, 0x33000000, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v8, 0x33a22168, v6
	v_or_b32_e32 v5, v5, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v8, 0x3fc90fda, v5
	v_add_f32_e32 v6, v10, v8
                                        ; implicit-def: $vgpr8
.LBB0_79:                               ; %Flow74
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s2, s16
; %bb.80:                               ;   in Loop: Header=BB0_2 Depth=1
	v_fma_f32 v6, 0xbfc90fda, v8, |v0|
	v_cvt_i32_f32_e32 v7, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, 0xb3a22168, v8
	v_fmac_f32_e32 v6, 0xa7c234c4, v8
; %bb.81:                               ; %_ZL3sinf.exit.i.i.i.i
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	v_dual_mul_f32 v5, v2, v2 :: v_dual_and_b32 v8, 1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_mul_f32 v4, v6, v6 :: v_dual_lshlrev_b32 v3, 30, v3
	v_and_b32_e32 v19, 1, v7
	v_fmaak_f32 v11, s10, v5, 0x3c0881c4
	v_dual_fmaak_f32 v14, s5, v5, 0xbab64f3b :: v_dual_lshlrev_b32 v7, 30, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmaak_f32 v10, s5, v4, 0xbab64f3b
	v_and_b32_e32 v3, 0x80000000, v3
	v_fmaak_f32 v11, v5, v11, 0xbe2aaa9d
	v_cmp_eq_u32_e32 vcc_lo, 0, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_fmaak_f32 v10, v4, v10, 0x3d2aabf7 :: v_dual_mul_f32 v11, v5, v11
	v_fmaak_f32 v9, s10, v4, 0x3c0881c4
	v_fmaak_f32 v10, v4, v10, 0xbf000004
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v2, v2, v11 :: v_dual_fmaak_f32 v9, v4, v9, 0xbe2aaa9d
	v_dual_fmaak_f32 v14, v5, v14, 0x3d2aabf7 :: v_dual_mul_f32 v9, v4, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmaak_f32 v14, v5, v14, 0xbf000004
	v_fma_f32 v4, v4, v10, 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v6, v6, v9 :: v_dual_and_b32 v7, 0x80000000, v7
	v_fma_f32 v5, v5, v14, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v4, v4, v6, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v8
	v_xor_b32_e32 v4, v7, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v2, -v2, v5, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v0, 0x1f8
	v_xor3_b32 v1, v4, v0, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v2, v3, v2
	v_cndmask_b32_e32 v0, 0x7fc00000, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v3, 0x7fc00000, v2, vcc_lo
.LBB0_82:                               ; %Flow77
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s15
                                        ; implicit-def: $vgpr2
.LBB0_83:                               ; %Flow78
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_and_not1_saveexec_b32 s2, s4
	s_cbranch_execz .LBB0_85
; %bb.84:                               ;   in Loop: Header=BB0_2 Depth=1
	v_mul_f32_e32 v1, 0x3fb8aa3b, v2
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v3, v1
	v_fma_f32 v4, 0x3fb8aa3b, v2, -v1
	v_dual_sub_f32 v1, v1, v3 :: v_dual_fmac_f32 v4, 0x32a5705f, v2
	v_cvt_i32_f32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v1, v1, v4
	v_exp_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v1, v1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, 0, v1, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v2
	v_cndmask_b32_e32 v3, 0x7f800000, v1, vcc_lo
.LBB0_85:                               ; %_ZN6thrust3powIfiEENS_7complexINS_6detail23promoted_numerical_typeIT_T0_vE4typeEEERKNS1_IS4_EERKS5_.exit.i
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_add_i32 s12, s12, 1
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_add_f32 v19, v18, v3 :: v_dual_add_f32 v14, v17, v0
	s_cmpk_eq_i32 s12, 0xff
	v_mov_b32_e32 v0, 0xff
	s_cselect_b32 s2, -1, 0
	s_and_not1_b32 s3, s13, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s13, s3, s2
.LBB0_86:                               ; %Flow94
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, exec_lo, s13
	s_or_b32 s6, s2, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s6
	s_cbranch_execnz .LBB0_2
; %bb.87:                               ; %_Z9get_interN6thrust7complexIfEE.exit
	s_or_b32 exec_lo, exec_lo, s6
	s_load_b64 s[0:1], s[0:1], 0x0
	v_lshlrev_b64 v[1:2], 2, v[12:13]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v1, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s1, v2, vcc_lo
	global_store_b32 v[1:2], v0, off
.LBB0_88:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z11fill_matrixPiiiN6thrust7complexIfEEffiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 44
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 39
		.amdhsa_next_free_sgpr 22
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z11fill_matrixPiiiN6thrust7complexIfEEffiii, .Lfunc_end0-_Z11fill_matrixPiiiN6thrust7complexIfEEffiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 11852
; NumSgprs: 24
; NumVgprs: 39
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 24
; NumVGPRsForWavesPerEU: 39
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           8
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 44
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z11fill_matrixPiiiN6thrust7complexIfEEffiii
    .private_segment_fixed_size: 0
    .sgpr_count:     24
    .sgpr_spill_count: 0
    .symbol:         _Z11fill_matrixPiiiN6thrust7complexIfEEffiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     39
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
