#include <iostream>
#include <stdlib.h>
#include <math.h>

using namespace std;
__global__ void maximum(int *a, int *b, int n)
{
	int max=0;
	int index = 256 * blockIdx.x;
	for(int i=index;i<min(256+index,n);i++)
	{
		if(a[i]>max)
		{
			max=a[i];
		}
	}
	b[blockIdx.x]=max;
}

__global__ void minimum(int *a, int *b, int n)
{
	int mini=999999;
	int index = 256 * blockIdx.x;
	for(int i=index;i<min(256+index,n);i++)
	{
		if(a[i]<mini)
		{
			mini=a[i];
		}
	}
	b[blockIdx.x]=mini;
}

__global__ void sum(int *a, int *b, int n)
{
	int sum=0;
	int index = 256 * blockIdx.x;
	for(int i=index;i<min(256+index,n);i++)
	{
		sum+=a[i];
	}
	b[blockIdx.x]=sum;
}

__global__ void standard_deviation(int *a, int *b, int n,double mean)
{
	double sum=0;
	int index = 256 * blockIdx.x;
	for(int i=index;i<min(256+index,n);i++)
	{
		sum+=(a[i]-mean)*(a[i]-mean);
	}
	b[blockIdx.x]=sum;
}

int main()
{
	int n,nmin,nsum,nmean,nsd;
	cout<<"\nEnter n:";
	cin>>n;
	int *hostA=(int*)malloc(sizeof(int)*n);

	nmin=n;
	nsum=n;
	nmean=n;
	nsd=n;

	float timeS=0.0,timeP=0.0;

	cudaEvent_t startS,endS,startP,endP;
	cudaEventCreate(&startS);
	cudaEventCreate(&endS);
	cudaEventCreate(&startP);
	cudaEventCreate(&endP);

	cudaEventRecord(startS);

	int max=0,min=9999999,ssum=0;
	double sd_sum=0.0f;
	for(int i=0;i<n;i++)
	{
		hostA[i]=rand()%n;
		cout<<hostA[i]<<"\t";
		if(hostA[i]>max)
		{
			max=hostA[i];
		}

		if(hostA[i]<min)
		{
			min=hostA[i];
		}
		ssum+=hostA[i];
	}
	double means=(ssum*1.0f)/(nmean*1.0f);
	for(int i=0;i<n;i++)
	{
		sd_sum+=(hostA[i]-means)*(hostA[i]-means);
	}

	cudaEventRecord(endS);
	cudaEventSynchronize(endS);
	cudaEventElapsedTime(&timeS,startS,endS);


	cudaEventRecord(startP);

	int *deviceA;
	cudaMalloc(&deviceA, sizeof(int)*n);
	cudaMemcpy(deviceA,hostA,sizeof(int)*n,cudaMemcpyHostToDevice);

	int *deviceB;	
	int grids=ceil(n*1.0f/256*1.0f);
	cudaMalloc(&deviceB, sizeof(int)*grids);

	dim3 grid(grids,1);
	dim3 block(1,1);

	while(n>1)
	{
		maximum<<<grid,block>>>(deviceA,deviceB,n);
		n=ceil(n*1.0f/256*1.0f);
		cudaMemcpy(deviceA,deviceB,n*sizeof(int),cudaMemcpyDeviceToDevice);
	}

	int maxi[2];
	cudaMemcpy(maxi,deviceA,4,cudaMemcpyDeviceToHost);
	cout<<"\nParallel Max="<<maxi[0]<<endl<<"Sequential Max="<<max<<endl;

//----------------------------------min----------------------------------------------------------

	cudaMemcpy(deviceA,hostA,sizeof(int)*nmin,cudaMemcpyHostToDevice);
	while(nmin>1)
	{
		minimum<<<grid,block>>>(deviceA,deviceB,nmin);
		nmin=ceil(nmin*1.0f/256*1.0f);
		cudaMemcpy(deviceA,deviceB,nmin*sizeof(int),cudaMemcpyDeviceToDevice);
	}

	int mini[2];
	cudaMemcpy(mini,deviceA,4,cudaMemcpyDeviceToHost);
	cout<<"\nParallel Min="<<mini[0]<<endl<<"Sequential Min="<<min<<endl;

//--------------------------------sum------------------------------------------------------------

	cudaMemcpy(deviceA,hostA,sizeof(int)*nsum,cudaMemcpyHostToDevice);
	while(nsum>1)
	{
		sum<<<grid,block>>>(deviceA,deviceB,nsum);
		nsum=ceil(nsum*1.0f/256*1.0f);
		cudaMemcpy(deviceA,deviceB,nsum*sizeof(int),cudaMemcpyDeviceToDevice);
	}

	int sums[2];
	cudaMemcpy(sums,deviceA,4,cudaMemcpyDeviceToHost);
	cout<<"\nParallel Sum="<<sums[0]<<endl<<"Sequential sum="<<ssum<<endl;

	double mean=(double)(sums[0]*1.0f/nmean*1.0f);

	cout<<"\nParallel Mean="<<mean<<endl<<"Sequential mean="<<means<<endl;


//--------------------------------sd-------------------------------------------------------------

	cudaMemcpy(deviceA,hostA,sizeof(int)*nsd,cudaMemcpyHostToDevice);
	while(nsd>1)
	{
		standard_deviation<<<grid,block>>>(deviceA,deviceB,nsd,mean);
		nsd=ceil(nsd*1.0f/256*1.0f);
		cudaMemcpy(deviceA,deviceB,nsd*sizeof(int),cudaMemcpyDeviceToDevice);
	}

	int sdp[2];
	cudaMemcpy(sdp,deviceA,4,cudaMemcpyDeviceToHost);
	cout<<"\nParallel SD="<<(double)sqrt((sdp[0]*1.0f)/(nmean*1.0f))<<endl<<"Sequential SD="<<(double)sqrt((sd_sum*1.0f)/(nmean*1.0f))<<endl;


	cudaEventRecord(endP);
	cudaEventSynchronize(endP);
	cudaEventElapsedTime(&timeP,startP,endP);

	cout<<"\nSequential Time="<<timeS;
	cout<<"\nParallel Time="<<timeP<<endl;

	return cudaDeviceSynchronize();
}

	.file	"tmpxft_0039b37f_00000000-6_all_in_one.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3638:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z29__device_stub__Z7maximumPiS_iPiS_i
	.type	_Z29__device_stub__Z7maximumPiS_iPiS_i, @function
_Z29__device_stub__Z7maximumPiS_iPiS_i:
.LFB3660:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z7maximumPiS_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L2:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3660:
	.size	_Z29__device_stub__Z7maximumPiS_iPiS_i, .-_Z29__device_stub__Z7maximumPiS_iPiS_i
	.globl	_Z7maximumPiS_i
	.type	_Z7maximumPiS_i, @function
_Z7maximumPiS_i:
.LFB3661:
	.cfi_startproc
	endbr64
	jmp	_Z29__device_stub__Z7maximumPiS_iPiS_i
	.cfi_endproc
.LFE3661:
	.size	_Z7maximumPiS_i, .-_Z7maximumPiS_i
	.globl	_Z29__device_stub__Z7minimumPiS_iPiS_i
	.type	_Z29__device_stub__Z7minimumPiS_iPiS_i, @function
_Z29__device_stub__Z7minimumPiS_iPiS_i:
.LFB3662:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z7minimumPiS_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L8:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3662:
	.size	_Z29__device_stub__Z7minimumPiS_iPiS_i, .-_Z29__device_stub__Z7minimumPiS_iPiS_i
	.globl	_Z7minimumPiS_i
	.type	_Z7minimumPiS_i, @function
_Z7minimumPiS_i:
.LFB3663:
	.cfi_startproc
	endbr64
	jmp	_Z29__device_stub__Z7minimumPiS_iPiS_i
	.cfi_endproc
.LFE3663:
	.size	_Z7minimumPiS_i, .-_Z7minimumPiS_i
	.globl	_Z25__device_stub__Z3sumPiS_iPiS_i
	.type	_Z25__device_stub__Z3sumPiS_iPiS_i, @function
_Z25__device_stub__Z3sumPiS_iPiS_i:
.LFB3664:
	.cfi_startproc
	endbr64
	subq	$136, %rsp
	.cfi_def_cfa_offset 144
	movq	%rdi, 24(%rsp)
	leaq	40(%rsp), %rcx
	leaq	48(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	60(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	32(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 120(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 56(%rsp)
	movq	%rax, 96(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 104(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 112(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 48(%rsp)
	movq	%rax, 60(%rsp)
	movl	$1, 68(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	40(%rsp)
	.cfi_def_cfa_offset 152
	leaq	_Z3sumPiS_i(%rip), %rdi
	pushq	40(%rsp)
	.cfi_def_cfa_offset 160
	movq	76(%rsp), %rcx
	movl	84(%rsp), %r8d
	movq	64(%rsp), %rsi
	movl	72(%rsp), %edx
	leaq	112(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 152
	popq	%rdx
	.cfi_def_cfa_offset 144
.L13:
	movq	120(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$136, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3664:
	.size	_Z25__device_stub__Z3sumPiS_iPiS_i, .-_Z25__device_stub__Z3sumPiS_iPiS_i
	.globl	_Z3sumPiS_i
	.type	_Z3sumPiS_i, @function
_Z3sumPiS_i:
.LFB3665:
	.cfi_startproc
	endbr64
	jmp	_Z25__device_stub__Z3sumPiS_iPiS_i
	.cfi_endproc
.LFE3665:
	.size	_Z3sumPiS_i, .-_Z3sumPiS_i
	.globl	_Z42__device_stub__Z18standard_deviationPiS_idPiS_id
	.type	_Z42__device_stub__Z18standard_deviationPiS_idPiS_id, @function
_Z42__device_stub__Z18standard_deviationPiS_idPiS_id:
.LFB3666:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 12(%rsp)
	leaq	40(%rsp), %rdx
	movsd	%xmm0, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 120(%rsp)
	movq	%rsp, %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L18
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z18standard_deviationPiS_id(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L18:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L20
	call	__stack_chk_fail@PLT
.L20:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3666:
	.size	_Z42__device_stub__Z18standard_deviationPiS_idPiS_id, .-_Z42__device_stub__Z18standard_deviationPiS_idPiS_id
	.globl	_Z18standard_deviationPiS_id
	.type	_Z18standard_deviationPiS_id, @function
_Z18standard_deviationPiS_id:
.LFB3667:
	.cfi_startproc
	endbr64
	jmp	_Z42__device_stub__Z18standard_deviationPiS_idPiS_id
	.cfi_endproc
.LFE3667:
	.size	_Z18standard_deviationPiS_id, .-_Z18standard_deviationPiS_id
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"\nEnter n:"
.LC3:
	.string	"\t"
.LC5:
	.string	"\nParallel Max="
.LC6:
	.string	"Sequential Max="
.LC7:
	.string	"\nParallel Min="
.LC8:
	.string	"Sequential Min="
.LC9:
	.string	"\nParallel Sum="
.LC10:
	.string	"Sequential sum="
.LC11:
	.string	"\nParallel Mean="
.LC12:
	.string	"Sequential mean="
.LC13:
	.string	"\nParallel SD="
.LC14:
	.string	"Sequential SD="
.LC15:
	.string	"\nSequential Time="
.LC16:
	.string	"\nParallel Time="
	.section	.text.startup,"ax",@progbits
	.globl	main
	.type	main, @function
main:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	leaq	.LC1(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	xorl	%r15d, %r15d
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	xorl	%r14d, %r14d
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movl	$9999999, %r13d
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	xorl	%r12d, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$168, %rsp
	.cfi_def_cfa_offset 224
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	leaq	36(%rsp), %rsi
	leaq	_ZSt3cin(%rip), %rdi
	call	_ZNSirsERi@PLT
	movslq	36(%rsp), %rax
	movq	%rax, %rbx
	salq	$2, %rax
	movq	%rax, %rdi
	movq	%rax, (%rsp)
	call	malloc@PLT
	leaq	48(%rsp), %rdi
	movl	$0x00000000, 40(%rsp)
	movl	$0x00000000, 44(%rsp)
	movq	%rax, %rbp
	call	cudaEventCreate@PLT
	leaq	56(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	64(%rsp), %rdi
	call	cudaEventCreate@PLT
	leaq	72(%rsp), %rdi
	call	cudaEventCreate@PLT
	movq	48(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
.L24:
	movl	36(%rsp), %edx
	cmpl	%r15d, %edx
	jle	.L43
	call	rand@PLT
	leaq	_ZSt4cout(%rip), %rdi
	cltd
	idivl	36(%rsp)
	movl	%edx, 0(%rbp,%r15,4)
	movl	%edx, %esi
	call	_ZNSolsEi@PLT
	leaq	.LC3(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	0(%rbp,%r15,4), %eax
	cmpl	%eax, %r14d
	cmovl	%eax, %r14d
	cmpl	%eax, %r13d
	cmovg	%eax, %r13d
	addl	%eax, %r12d
	incq	%r15
	jmp	.L24
.L43:
	movq	$0x000000000, 16(%rsp)
	cvtsi2ssl	%ebx, %xmm2
	xorl	%eax, %eax
	cvtsi2ssl	%r12d, %xmm0
	movss	%xmm2, 12(%rsp)
	divss	%xmm2, %xmm0
	cvtss2sd	%xmm0, %xmm4
	movsd	%xmm4, 24(%rsp)
.L26:
	cmpl	%eax, %edx
	jle	.L44
	cvtsi2sdl	0(%rbp,%rax,4), %xmm0
	subsd	24(%rsp), %xmm0
	incq	%rax
	mulsd	%xmm0, %xmm0
	addsd	16(%rsp), %xmm0
	movsd	%xmm0, 16(%rsp)
	jmp	.L26
.L44:
	movq	56(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	56(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	56(%rsp), %rdx
	movq	48(%rsp), %rsi
	leaq	40(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	movq	64(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movslq	36(%rsp), %rsi
	leaq	80(%rsp), %rdi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movslq	36(%rsp), %rdx
	movq	80(%rsp), %rdi
	movq	%rbp, %rsi
	movl	$1, %ecx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	cvtsi2ssl	36(%rsp), %xmm0
	mulss	.LC4(%rip), %xmm0
	call	ceilf@PLT
	leaq	88(%rsp), %rdi
	cvttss2sil	%xmm0, %r15d
	movslq	%r15d, %rsi
	salq	$2, %rsi
	call	cudaMalloc@PLT
	movl	%r15d, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 100(%rsp)
	movq	%rax, 108(%rsp)
	movl	$1, 116(%rsp)
.L28:
	cmpl	$1, 36(%rsp)
	jle	.L45
	movl	116(%rsp), %ecx
	movq	108(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	96(%rsp), %rdi
	movl	104(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L29
	movl	36(%rsp), %edx
	movq	88(%rsp), %rsi
	movq	80(%rsp), %rdi
	call	_Z29__device_stub__Z7maximumPiS_iPiS_i
.L29:
	cvtsi2ssl	36(%rsp), %xmm0
	mulss	.LC4(%rip), %xmm0
	call	ceilf@PLT
	movq	88(%rsp), %rsi
	movq	80(%rsp), %rdi
	movl	$3, %ecx
	cvttss2sil	%xmm0, %edx
	movl	%edx, 36(%rsp)
	movslq	%edx, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	jmp	.L28
.L45:
	movq	80(%rsp), %rsi
	movl	$2, %ecx
	movl	$4, %edx
	leaq	120(%rsp), %rdi
	call	cudaMemcpy@PLT
	leaq	.LC5(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	120(%rsp), %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E@PLT
	leaq	.LC6(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%r14d, %esi
	movl	%ebx, %r14d
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E@PLT
	movq	(%rsp), %rdx
	movq	80(%rsp), %rdi
	movq	%rbp, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
.L31:
	cmpl	$1, %r14d
	jle	.L46
	movl	116(%rsp), %ecx
	movq	108(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	96(%rsp), %rdi
	movl	104(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L32
	movq	88(%rsp), %rsi
	movq	80(%rsp), %rdi
	movl	%r14d, %edx
	call	_Z29__device_stub__Z7minimumPiS_iPiS_i
.L32:
	cvtsi2ssl	%r14d, %xmm0
	mulss	.LC4(%rip), %xmm0
	call	ceilf@PLT
	movq	88(%rsp), %rsi
	movq	80(%rsp), %rdi
	movl	$3, %ecx
	cvttss2sil	%xmm0, %r14d
	movslq	%r14d, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	jmp	.L31
.L46:
	movq	80(%rsp), %rsi
	movl	$2, %ecx
	movl	$4, %edx
	leaq	128(%rsp), %rdi
	call	cudaMemcpy@PLT
	leaq	.LC7(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	128(%rsp), %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E@PLT
	leaq	.LC8(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%r13d, %esi
	movl	%ebx, %r13d
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E@PLT
	movq	(%rsp), %rdx
	movq	80(%rsp), %rdi
	movq	%rbp, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
.L34:
	cmpl	$1, %r13d
	jle	.L47
	movl	116(%rsp), %ecx
	movq	108(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	96(%rsp), %rdi
	movl	104(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L35
	movq	88(%rsp), %rsi
	movq	80(%rsp), %rdi
	movl	%r13d, %edx
	call	_Z25__device_stub__Z3sumPiS_iPiS_i
.L35:
	cvtsi2ssl	%r13d, %xmm0
	mulss	.LC4(%rip), %xmm0
	call	ceilf@PLT
	movq	88(%rsp), %rsi
	movq	80(%rsp), %rdi
	movl	$3, %ecx
	cvttss2sil	%xmm0, %r13d
	movslq	%r13d, %rdx
	salq	$2, %rdx
	call	cudaMemcpy@PLT
	jmp	.L34
.L47:
	movq	80(%rsp), %rsi
	movl	$2, %ecx
	movl	$4, %edx
	leaq	136(%rsp), %rdi
	call	cudaMemcpy@PLT
	leaq	.LC9(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	136(%rsp), %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E@PLT
	leaq	.LC10(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movl	%r12d, %esi
	movq	%rax, %rdi
	call	_ZNSolsEi@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E@PLT
	leaq	.LC11(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	cvtsi2ssl	136(%rsp), %xmm0
	divss	12(%rsp), %xmm0
	cvtss2sd	%xmm0, %xmm2
	movq	%xmm2, %r12
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%r12, %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E@PLT
	leaq	.LC12(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movsd	24(%rsp), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E@PLT
	movq	(%rsp), %rdx
	movl	$1, %ecx
	movq	%rbp, %rsi
.L42:
	movq	80(%rsp), %rdi
	call	cudaMemcpy@PLT
	cmpl	$1, %ebx
	jle	.L48
	movl	116(%rsp), %ecx
	movq	108(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	96(%rsp), %rdi
	movl	104(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L38
	movq	88(%rsp), %rsi
	movq	80(%rsp), %rdi
	movq	%r12, %xmm0
	movl	%ebx, %edx
	call	_Z42__device_stub__Z18standard_deviationPiS_idPiS_id
.L38:
	cvtsi2ssl	%ebx, %xmm0
	mulss	.LC4(%rip), %xmm0
	call	ceilf@PLT
	movq	88(%rsp), %rsi
	movl	$3, %ecx
	cvttss2sil	%xmm0, %ebx
	movslq	%ebx, %rdx
	salq	$2, %rdx
	jmp	.L42
.L48:
	movq	80(%rsp), %rsi
	movl	$2, %ecx
	movl	$4, %edx
	leaq	144(%rsp), %rdi
	call	cudaMemcpy@PLT
	leaq	.LC13(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	cvtsi2ssl	144(%rsp), %xmm0
	divss	12(%rsp), %xmm0
	movq	%rax, %rbx
	call	sqrtf@PLT
	movq	%rbx, %rdi
	cvtss2sd	%xmm0, %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E@PLT
	leaq	.LC14(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movsd	16(%rsp), %xmm1
	cvtss2sd	12(%rsp), %xmm0
	movq	%rax, %rbx
	divsd	%xmm0, %xmm1
	movaps	%xmm1, %xmm0
	call	sqrt@PLT
	movq	%rbx, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E@PLT
	movq	72(%rsp), %rdi
	xorl	%esi, %esi
	call	cudaEventRecord@PLT
	movq	72(%rsp), %rdi
	call	cudaEventSynchronize@PLT
	movq	72(%rsp), %rdx
	movq	64(%rsp), %rsi
	leaq	44(%rsp), %rdi
	call	cudaEventElapsedTime@PLT
	leaq	.LC15(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	cvtss2sd	40(%rsp), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC16(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	cvtss2sd	44(%rsp), %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E@PLT
	call	cudaDeviceSynchronize@PLT
	movq	152(%rsp), %rdx
	subq	%fs:40, %rdx
	je	.L40
	call	__stack_chk_fail@PLT
.L40:
	addq	$168, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	main, .-main
	.section	.rodata.str1.1
.LC17:
	.string	"_Z18standard_deviationPiS_id"
.LC18:
	.string	"_Z3sumPiS_i"
.LC19:
	.string	"_Z7minimumPiS_i"
.LC20:
	.string	"_Z7maximumPiS_i"
	.section	.text.startup
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3669:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC17(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z18standard_deviationPiS_id(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC18(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z3sumPiS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC19(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z7minimumPiS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC20(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z7maximumPiS_i(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3669:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC4:
	.long	998244352
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <iostream>
#include <stdlib.h>
#include <math.h>

using namespace std;
__global__ void maximum(int *a, int *b, int n)
{
	int max=0;
	int index = 256 * blockIdx.x;
	for(int i=index;i<min(256+index,n);i++)
	{
		if(a[i]>max)
		{
			max=a[i];
		}
	}
	b[blockIdx.x]=max;
}

__global__ void minimum(int *a, int *b, int n)
{
	int mini=999999;
	int index = 256 * blockIdx.x;
	for(int i=index;i<min(256+index,n);i++)
	{
		if(a[i]<mini)
		{
			mini=a[i];
		}
	}
	b[blockIdx.x]=mini;
}

__global__ void sum(int *a, int *b, int n)
{
	int sum=0;
	int index = 256 * blockIdx.x;
	for(int i=index;i<min(256+index,n);i++)
	{
		sum+=a[i];
	}
	b[blockIdx.x]=sum;
}

__global__ void standard_deviation(int *a, int *b, int n,double mean)
{
	double sum=0;
	int index = 256 * blockIdx.x;
	for(int i=index;i<min(256+index,n);i++)
	{
		sum+=(a[i]-mean)*(a[i]-mean);
	}
	b[blockIdx.x]=sum;
}

int main()
{
	int n,nmin,nsum,nmean,nsd;
	cout<<"\nEnter n:";
	cin>>n;
	int *hostA=(int*)malloc(sizeof(int)*n);

	nmin=n;
	nsum=n;
	nmean=n;
	nsd=n;

	float timeS=0.0,timeP=0.0;

	hipEvent_t startS,endS,startP,endP;
	hipEventCreate(&startS);
	hipEventCreate(&endS);
	hipEventCreate(&startP);
	hipEventCreate(&endP);

	hipEventRecord(startS);

	int max=0,min=9999999,ssum=0;
	double sd_sum=0.0f;
	for(int i=0;i<n;i++)
	{
		hostA[i]=rand()%n;
		cout<<hostA[i]<<"\t";
		if(hostA[i]>max)
		{
			max=hostA[i];
		}

		if(hostA[i]<min)
		{
			min=hostA[i];
		}
		ssum+=hostA[i];
	}
	double means=(ssum*1.0f)/(nmean*1.0f);
	for(int i=0;i<n;i++)
	{
		sd_sum+=(hostA[i]-means)*(hostA[i]-means);
	}

	hipEventRecord(endS);
	hipEventSynchronize(endS);
	hipEventElapsedTime(&timeS,startS,endS);


	hipEventRecord(startP);

	int *deviceA;
	hipMalloc(&deviceA, sizeof(int)*n);
	hipMemcpy(deviceA,hostA,sizeof(int)*n,hipMemcpyHostToDevice);

	int *deviceB;	
	int grids=ceil(n*1.0f/256*1.0f);
	hipMalloc(&deviceB, sizeof(int)*grids);

	dim3 grid(grids,1);
	dim3 block(1,1);

	while(n>1)
	{
		maximum<<<grid,block>>>(deviceA,deviceB,n);
		n=ceil(n*1.0f/256*1.0f);
		hipMemcpy(deviceA,deviceB,n*sizeof(int),hipMemcpyDeviceToDevice);
	}

	int maxi[2];
	hipMemcpy(maxi,deviceA,4,hipMemcpyDeviceToHost);
	cout<<"\nParallel Max="<<maxi[0]<<endl<<"Sequential Max="<<max<<endl;

//----------------------------------min----------------------------------------------------------

	hipMemcpy(deviceA,hostA,sizeof(int)*nmin,hipMemcpyHostToDevice);
	while(nmin>1)
	{
		minimum<<<grid,block>>>(deviceA,deviceB,nmin);
		nmin=ceil(nmin*1.0f/256*1.0f);
		hipMemcpy(deviceA,deviceB,nmin*sizeof(int),hipMemcpyDeviceToDevice);
	}

	int mini[2];
	hipMemcpy(mini,deviceA,4,hipMemcpyDeviceToHost);
	cout<<"\nParallel Min="<<mini[0]<<endl<<"Sequential Min="<<min<<endl;

//--------------------------------sum------------------------------------------------------------

	hipMemcpy(deviceA,hostA,sizeof(int)*nsum,hipMemcpyHostToDevice);
	while(nsum>1)
	{
		sum<<<grid,block>>>(deviceA,deviceB,nsum);
		nsum=ceil(nsum*1.0f/256*1.0f);
		hipMemcpy(deviceA,deviceB,nsum*sizeof(int),hipMemcpyDeviceToDevice);
	}

	int sums[2];
	hipMemcpy(sums,deviceA,4,hipMemcpyDeviceToHost);
	cout<<"\nParallel Sum="<<sums[0]<<endl<<"Sequential sum="<<ssum<<endl;

	double mean=(double)(sums[0]*1.0f/nmean*1.0f);

	cout<<"\nParallel Mean="<<mean<<endl<<"Sequential mean="<<means<<endl;


//--------------------------------sd-------------------------------------------------------------

	hipMemcpy(deviceA,hostA,sizeof(int)*nsd,hipMemcpyHostToDevice);
	while(nsd>1)
	{
		standard_deviation<<<grid,block>>>(deviceA,deviceB,nsd,mean);
		nsd=ceil(nsd*1.0f/256*1.0f);
		hipMemcpy(deviceA,deviceB,nsd*sizeof(int),hipMemcpyDeviceToDevice);
	}

	int sdp[2];
	hipMemcpy(sdp,deviceA,4,hipMemcpyDeviceToHost);
	cout<<"\nParallel SD="<<(double)sqrt((sdp[0]*1.0f)/(nmean*1.0f))<<endl<<"Sequential SD="<<(double)sqrt((sd_sum*1.0f)/(nmean*1.0f))<<endl;


	hipEventRecord(endP);
	hipEventSynchronize(endP);
	hipEventElapsedTime(&timeP,startP,endP);

	cout<<"\nSequential Time="<<timeS;
	cout<<"\nParallel Time="<<timeP<<endl;

	return hipDeviceSynchronize();
}

	.text
	.file	"all_in_one.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z22__device_stub__maximumPiS_i # -- Begin function _Z22__device_stub__maximumPiS_i
	.type	_Z22__device_stub__maximumPiS_i,@function
_Z22__device_stub__maximumPiS_i:        # @_Z22__device_stub__maximumPiS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7maximumPiS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z22__device_stub__maximumPiS_i, .Lfunc_end0-_Z22__device_stub__maximumPiS_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z22__device_stub__minimumPiS_i # -- Begin function _Z22__device_stub__minimumPiS_i
	.type	_Z22__device_stub__minimumPiS_i,@function
_Z22__device_stub__minimumPiS_i:        # @_Z22__device_stub__minimumPiS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7minimumPiS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z22__device_stub__minimumPiS_i, .Lfunc_end1-_Z22__device_stub__minimumPiS_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z18__device_stub__sumPiS_i     # -- Begin function _Z18__device_stub__sumPiS_i
	.type	_Z18__device_stub__sumPiS_i,@function
_Z18__device_stub__sumPiS_i:            # @_Z18__device_stub__sumPiS_i
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	12(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z3sumPiS_i, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z18__device_stub__sumPiS_i, .Lfunc_end2-_Z18__device_stub__sumPiS_i
	.cfi_endproc
                                        # -- End function
	.globl	_Z33__device_stub__standard_deviationPiS_id # -- Begin function _Z33__device_stub__standard_deviationPiS_id
	.type	_Z33__device_stub__standard_deviationPiS_id,@function
_Z33__device_stub__standard_deviationPiS_id: # @_Z33__device_stub__standard_deviationPiS_id
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rcx
	movq	%rsi, (%rcx)
	leaq	4(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	24(%rsp), %rdx
	movsd	%xmm0, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z18standard_deviationPiS_id, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z33__device_stub__standard_deviationPiS_id, .Lfunc_end3-_Z33__device_stub__standard_deviationPiS_id
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function main
.LCPI4_0:
	.long	0x3b800000                      # float 0.00390625
	.text
	.globl	main
	.type	main,@function
main:                                   # @main
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$152, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$9, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	leaq	4(%rsp), %r14
	movl	$_ZSt3cin, %edi
	movq	%r14, %rsi
	callq	_ZNSirsERi
	movslq	(%r14), %rbx
	movq	%rbx, %rdi
	shlq	$2, %rdi
	movq	%rdi, 64(%rsp)                  # 8-byte Spill
	callq	malloc
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	xorl	%r15d, %r15d
	movl	%r15d, 44(%rsp)
	movl	%r15d, 92(%rsp)
	leaq	112(%rsp), %r12
	movq	%r12, %rdi
	callq	hipEventCreate
	leaq	80(%rsp), %rdi
	callq	hipEventCreate
	leaq	104(%rsp), %rdi
	callq	hipEventCreate
	leaq	72(%rsp), %rdi
	callq	hipEventCreate
	movq	(%r12), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	cmpl	%r15d, (%r14)
	jle	.LBB4_5
# %bb.1:                                # %.lr.ph.preheader
	movq	%rbx, 48(%rsp)                  # 8-byte Spill
	movl	$9999999, %r14d                 # imm = 0x98967F
	xorl	%r13d, %r13d
	xorl	%r15d, %r15d
	xorl	%ebp, %ebp
	movq	32(%rsp), %rbx                  # 8-byte Reload
.LBB4_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	callq	rand
	cltd
	idivl	4(%rsp)
	movl	%edx, %r12d
	movl	%edx, (%rbx,%r13,4)
	movl	$_ZSt4cout, %edi
	movl	%edx, %esi
	callq	_ZNSolsEi
	movl	$.L.str.1, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	cmpl	%r15d, %r12d
	cmovgl	%r12d, %r15d
	cmpl	%r14d, %r12d
	cmovll	%r12d, %r14d
	addl	%r12d, %ebp
	incq	%r13
	movslq	4(%rsp), %rax
	cmpq	%rax, %r13
	jl	.LBB4_2
# %bb.3:                                # %._crit_edge
	cvtsi2ss	%ebp, %xmm0
	movq	48(%rsp), %rbx                  # 8-byte Reload
	cvtsi2ss	%ebx, %xmm1
	movl	%eax, %eax
	movss	%xmm1, 20(%rsp)                 # 4-byte Spill
	divss	%xmm1, %xmm0
	cvtss2sd	%xmm0, %xmm2
	testl	%eax, %eax
	movsd	%xmm2, 96(%rsp)                 # 8-byte Spill
	jle	.LBB4_4
# %bb.27:                               # %.lr.ph128.preheader
	xorps	%xmm1, %xmm1
	xorl	%ecx, %ecx
	movq	32(%rsp), %r12                  # 8-byte Reload
.LBB4_28:                               # %.lr.ph128
                                        # =>This Inner Loop Header: Depth=1
	xorps	%xmm0, %xmm0
	cvtsi2sdl	(%r12,%rcx,4), %xmm0
	subsd	%xmm2, %xmm0
	mulsd	%xmm0, %xmm0
	addsd	%xmm0, %xmm1
	incq	%rcx
	cmpq	%rcx, %rax
	jne	.LBB4_28
# %bb.29:
	movsd	%xmm1, 56(%rsp)                 # 8-byte Spill
	jmp	.LBB4_7
.LBB4_5:                                # %._crit_edge.thread
	cvtsi2ss	%ebx, %xmm1
	xorps	%xmm0, %xmm0
	movss	%xmm1, 20(%rsp)                 # 4-byte Spill
	divss	%xmm1, %xmm0
	cvtss2sd	%xmm0, %xmm0
	movsd	%xmm0, 96(%rsp)                 # 8-byte Spill
	xorps	%xmm0, %xmm0
	movsd	%xmm0, 56(%rsp)                 # 8-byte Spill
	movl	$9999999, %r14d                 # imm = 0x98967F
	xorl	%ebp, %ebp
	jmp	.LBB4_6
.LBB4_4:
	xorps	%xmm0, %xmm0
	movsd	%xmm0, 56(%rsp)                 # 8-byte Spill
.LBB4_6:                                # %._crit_edge129
	movq	32(%rsp), %r12                  # 8-byte Reload
.LBB4_7:                                # %._crit_edge129
	movq	80(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	80(%rsp), %rdi
	callq	hipEventSynchronize
	movq	112(%rsp), %rsi
	movq	80(%rsp), %rdx
	leaq	44(%rsp), %rdi
	callq	hipEventElapsedTime
	movq	104(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movslq	4(%rsp), %rsi
	shlq	$2, %rsi
	leaq	8(%rsp), %r13
	movq	%r13, %rdi
	callq	hipMalloc
	movq	(%r13), %rdi
	movslq	4(%rsp), %rdx
	shlq	$2, %rdx
	movq	%r12, %rsi
	movl	$1, %ecx
	callq	hipMemcpy
	xorps	%xmm0, %xmm0
	cvtsi2ssl	4(%rsp), %xmm0
	mulss	.LCPI4_0(%rip), %xmm0
	callq	ceilf@PLT
	cvttss2si	%xmm0, %r12d
	movslq	%r12d, %rsi
	shlq	$2, %rsi
	leaq	24(%rsp), %rdi
	callq	hipMalloc
	movabsq	$4294967297, %rax               # imm = 0x100000001
	leaq	(%r12,%rax), %r13
	decq	%r13
	cmpl	$2, 4(%rsp)
	jl	.LBB4_11
.LBB4_8:                                # %.lr.ph132
                                        # =>This Inner Loop Header: Depth=1
	movq	%r13, %rdi
	movl	$1, %esi
	movabsq	$4294967297, %rdx               # imm = 0x100000001
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_10
# %bb.9:                                #   in Loop: Header=BB4_8 Depth=1
	movq	8(%rsp), %rdi
	movq	24(%rsp), %rsi
	movl	4(%rsp), %edx
	callq	_Z22__device_stub__maximumPiS_i
.LBB4_10:                               #   in Loop: Header=BB4_8 Depth=1
	xorps	%xmm0, %xmm0
	cvtsi2ssl	4(%rsp), %xmm0
	mulss	.LCPI4_0(%rip), %xmm0
	callq	ceilf@PLT
	cvttss2si	%xmm0, %eax
	movl	%eax, 4(%rsp)
	movq	8(%rsp), %rdi
	movq	24(%rsp), %rsi
	movslq	%eax, %rdx
	shlq	$2, %rdx
	movl	$3, %ecx
	callq	hipMemcpy
	cmpl	$1, 4(%rsp)
	jg	.LBB4_8
.LBB4_11:                               # %._crit_edge133
	movq	8(%rsp), %rsi
	leaq	144(%rsp), %r12
	movl	$4, %edx
	movq	%r12, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$_ZSt4cout, %edi
	movl	$.L.str.2, %esi
	movl	$14, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	(%r12), %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSolsEi
	movq	%rax, %r12
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r12, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r12, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	%rax, %r12
	movl	$.L.str.3, %esi
	movl	$15, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r12, %rdi
	movl	%r15d, %esi
	callq	_ZNSolsEi
	movq	%rax, %r15
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r15, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	8(%rsp), %rdi
	movq	32(%rsp), %rsi                  # 8-byte Reload
	movq	64(%rsp), %rdx                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	cmpl	$2, %ebx
	jl	.LBB4_16
# %bb.12:                               # %.lr.ph136.preheader
	movl	%ebx, %r15d
.LBB4_13:                               # %.lr.ph136
                                        # =>This Inner Loop Header: Depth=1
	movq	%r13, %rdi
	movl	$1, %esi
	movabsq	$4294967297, %rdx               # imm = 0x100000001
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_15
# %bb.14:                               #   in Loop: Header=BB4_13 Depth=1
	movq	8(%rsp), %rdi
	movq	24(%rsp), %rsi
	movl	%r15d, %edx
	callq	_Z22__device_stub__minimumPiS_i
.LBB4_15:                               #   in Loop: Header=BB4_13 Depth=1
	xorps	%xmm0, %xmm0
	cvtsi2ss	%r15d, %xmm0
	mulss	.LCPI4_0(%rip), %xmm0
	callq	ceilf@PLT
	cvttss2si	%xmm0, %r15d
	movq	8(%rsp), %rdi
	movq	24(%rsp), %rsi
	movslq	%r15d, %r12
	leaq	(,%r12,4), %rdx
	movl	$3, %ecx
	callq	hipMemcpy
	cmpl	$1, %r12d
	jg	.LBB4_13
.LBB4_16:                               # %._crit_edge137
	movq	8(%rsp), %rsi
	leaq	136(%rsp), %r15
	movl	$4, %edx
	movq	%r15, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$_ZSt4cout, %edi
	movl	$.L.str.4, %esi
	movl	$14, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	(%r15), %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSolsEi
	movq	%rax, %r15
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r15, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	%rax, %r15
	movl	$.L.str.5, %esi
	movl	$15, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r15, %rdi
	movl	%r14d, %esi
	callq	_ZNSolsEi
	movq	%rax, %r14
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r14, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r14, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	8(%rsp), %rdi
	movq	32(%rsp), %r12                  # 8-byte Reload
	movq	%r12, %rsi
	movq	64(%rsp), %rdx                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	cmpl	$2, %ebx
	jl	.LBB4_21
# %bb.17:                               # %.lr.ph140.preheader
	movl	%ebx, %r14d
.LBB4_18:                               # %.lr.ph140
                                        # =>This Inner Loop Header: Depth=1
	movq	%r13, %rdi
	movl	$1, %esi
	movabsq	$4294967297, %rdx               # imm = 0x100000001
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_20
# %bb.19:                               #   in Loop: Header=BB4_18 Depth=1
	movq	8(%rsp), %rdi
	movq	24(%rsp), %rsi
	movl	%r14d, %edx
	callq	_Z18__device_stub__sumPiS_i
.LBB4_20:                               #   in Loop: Header=BB4_18 Depth=1
	xorps	%xmm0, %xmm0
	cvtsi2ss	%r14d, %xmm0
	mulss	.LCPI4_0(%rip), %xmm0
	callq	ceilf@PLT
	cvttss2si	%xmm0, %r14d
	movq	8(%rsp), %rdi
	movq	24(%rsp), %rsi
	movslq	%r14d, %r15
	leaq	(,%r15,4), %rdx
	movl	$3, %ecx
	callq	hipMemcpy
	cmpl	$1, %r15d
	jg	.LBB4_18
.LBB4_21:                               # %._crit_edge141
	movq	8(%rsp), %rsi
	leaq	128(%rsp), %r14
	movl	$4, %edx
	movq	%r14, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$_ZSt4cout, %edi
	movl	$.L.str.6, %esi
	movl	$14, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	(%r14), %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSolsEi
	movq	%rax, %r15
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r15, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	%rax, %r15
	movl	$.L.str.7, %esi
	movl	$15, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r15, %rdi
	movl	%ebp, %esi
	callq	_ZNSolsEi
	movq	%rax, %r15
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r15, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r15, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	xorps	%xmm0, %xmm0
	cvtsi2ssl	(%r14), %xmm0
	divss	20(%rsp), %xmm0                 # 4-byte Folded Reload
	cvtss2sd	%xmm0, %xmm0
	movsd	%xmm0, 48(%rsp)                 # 8-byte Spill
	movl	$_ZSt4cout, %edi
	movl	$.L.str.8, %esi
	movl	$15, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movsd	48(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r14
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r14, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r14, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	%rax, %r14
	movl	$.L.str.9, %esi
	movl	$16, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	%r14, %rdi
	movsd	96(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r14
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%r14, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%r14, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	8(%rsp), %rdi
	movq	%r12, %rsi
	movq	64(%rsp), %rdx                  # 8-byte Reload
	movl	$1, %ecx
	callq	hipMemcpy
	cmpl	$2, %ebx
	jl	.LBB4_25
.LBB4_22:                               # %.lr.ph144
                                        # =>This Inner Loop Header: Depth=1
	movq	%r13, %rdi
	movl	$1, %esi
	movabsq	$4294967297, %rdx               # imm = 0x100000001
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB4_24
# %bb.23:                               #   in Loop: Header=BB4_22 Depth=1
	movq	8(%rsp), %rdi
	movq	24(%rsp), %rsi
	movl	%ebx, %edx
	movsd	48(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	callq	_Z33__device_stub__standard_deviationPiS_id
.LBB4_24:                               #   in Loop: Header=BB4_22 Depth=1
	xorps	%xmm0, %xmm0
	cvtsi2ss	%ebx, %xmm0
	mulss	.LCPI4_0(%rip), %xmm0
	callq	ceilf@PLT
	cvttss2si	%xmm0, %ebx
	movq	8(%rsp), %rdi
	movq	24(%rsp), %rsi
	movslq	%ebx, %r14
	leaq	(,%r14,4), %rdx
	movl	$3, %ecx
	callq	hipMemcpy
	cmpl	$1, %r14d
	jg	.LBB4_22
.LBB4_25:                               # %._crit_edge145
	movq	8(%rsp), %rsi
	leaq	120(%rsp), %rbx
	movl	$4, %edx
	movq	%rbx, %rdi
	movl	$2, %ecx
	callq	hipMemcpy
	movl	$_ZSt4cout, %edi
	movl	$.L.str.10, %esi
	movl	$13, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorps	%xmm0, %xmm0
	cvtsi2ssl	(%rbx), %xmm0
	divss	20(%rsp), %xmm0                 # 4-byte Folded Reload
	xorps	%xmm1, %xmm1
	ucomiss	%xmm1, %xmm0
	jb	.LBB4_30
# %bb.26:
	sqrtss	%xmm0, %xmm0
	jmp	.LBB4_31
.LBB4_30:                               # %call.sqrt
	callq	sqrtf
.LBB4_31:                               # %._crit_edge145.split
	cvtss2sd	%xmm0, %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	%rax, %rbx
	movl	$.L.str.11, %esi
	movl	$14, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorps	%xmm1, %xmm1
	cvtss2sd	20(%rsp), %xmm1                 # 4-byte Folded Reload
	movsd	56(%rsp), %xmm0                 # 8-byte Reload
                                        # xmm0 = mem[0],zero
	divsd	%xmm1, %xmm0
	xorpd	%xmm1, %xmm1
	ucomisd	%xmm1, %xmm0
	jb	.LBB4_33
# %bb.32:
	sqrtsd	%xmm0, %xmm0
	jmp	.LBB4_34
.LBB4_33:                               # %call.sqrt169
	callq	sqrt
.LBB4_34:                               # %._crit_edge145.split.split
	movq	%rbx, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	72(%rsp), %rdi
	xorl	%esi, %esi
	callq	hipEventRecord
	movq	72(%rsp), %rdi
	callq	hipEventSynchronize
	movq	104(%rsp), %rsi
	movq	72(%rsp), %rdx
	leaq	92(%rsp), %rbx
	movq	%rbx, %rdi
	callq	hipEventElapsedTime
	movl	$_ZSt4cout, %edi
	movl	$.L.str.12, %esi
	movl	$17, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorps	%xmm0, %xmm0
	cvtss2sd	44(%rsp), %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movl	$_ZSt4cout, %edi
	movl	$.L.str.13, %esi
	movl	$15, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	xorps	%xmm0, %xmm0
	cvtss2sd	(%rbx), %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	callq	hipDeviceSynchronize
	addq	$152, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	main, .Lfunc_end4-main
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB5_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB5_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7maximumPiS_i, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7minimumPiS_i, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z3sumPiS_i, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z18standard_deviationPiS_id, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end5:
	.size	__hip_module_ctor, .Lfunc_end5-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB6_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB6_2:
	retq
.Lfunc_end6:
	.size	__hip_module_dtor, .Lfunc_end6-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z7maximumPiS_i,@object         # @_Z7maximumPiS_i
	.section	.rodata,"a",@progbits
	.globl	_Z7maximumPiS_i
	.p2align	3, 0x0
_Z7maximumPiS_i:
	.quad	_Z22__device_stub__maximumPiS_i
	.size	_Z7maximumPiS_i, 8

	.type	_Z7minimumPiS_i,@object         # @_Z7minimumPiS_i
	.globl	_Z7minimumPiS_i
	.p2align	3, 0x0
_Z7minimumPiS_i:
	.quad	_Z22__device_stub__minimumPiS_i
	.size	_Z7minimumPiS_i, 8

	.type	_Z3sumPiS_i,@object             # @_Z3sumPiS_i
	.globl	_Z3sumPiS_i
	.p2align	3, 0x0
_Z3sumPiS_i:
	.quad	_Z18__device_stub__sumPiS_i
	.size	_Z3sumPiS_i, 8

	.type	_Z18standard_deviationPiS_id,@object # @_Z18standard_deviationPiS_id
	.globl	_Z18standard_deviationPiS_id
	.p2align	3, 0x0
_Z18standard_deviationPiS_id:
	.quad	_Z33__device_stub__standard_deviationPiS_id
	.size	_Z18standard_deviationPiS_id, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"\nEnter n:"
	.size	.L.str, 10

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	"\t"
	.size	.L.str.1, 2

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"\nParallel Max="
	.size	.L.str.2, 15

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	"Sequential Max="
	.size	.L.str.3, 16

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	"\nParallel Min="
	.size	.L.str.4, 15

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	"Sequential Min="
	.size	.L.str.5, 16

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	"\nParallel Sum="
	.size	.L.str.6, 15

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"Sequential sum="
	.size	.L.str.7, 16

	.type	.L.str.8,@object                # @.str.8
.L.str.8:
	.asciz	"\nParallel Mean="
	.size	.L.str.8, 16

	.type	.L.str.9,@object                # @.str.9
.L.str.9:
	.asciz	"Sequential mean="
	.size	.L.str.9, 17

	.type	.L.str.10,@object               # @.str.10
.L.str.10:
	.asciz	"\nParallel SD="
	.size	.L.str.10, 14

	.type	.L.str.11,@object               # @.str.11
.L.str.11:
	.asciz	"Sequential SD="
	.size	.L.str.11, 15

	.type	.L.str.12,@object               # @.str.12
.L.str.12:
	.asciz	"\nSequential Time="
	.size	.L.str.12, 18

	.type	.L.str.13,@object               # @.str.13
.L.str.13:
	.asciz	"\nParallel Time="
	.size	.L.str.13, 16

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z7maximumPiS_i"
	.size	.L__unnamed_1, 16

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z7minimumPiS_i"
	.size	.L__unnamed_2, 16

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z3sumPiS_i"
	.size	.L__unnamed_3, 12

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z18standard_deviationPiS_id"
	.size	.L__unnamed_4, 29

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z22__device_stub__maximumPiS_i
	.addrsig_sym _Z22__device_stub__minimumPiS_i
	.addrsig_sym _Z18__device_stub__sumPiS_i
	.addrsig_sym _Z33__device_stub__standard_deviationPiS_id
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z7maximumPiS_i
	.addrsig_sym _Z7minimumPiS_i
	.addrsig_sym _Z3sumPiS_i
	.addrsig_sym _Z18standard_deviationPiS_id
	.addrsig_sym _ZSt4cout
	.addrsig_sym _ZSt3cin
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z7maximumPiS_i         ; -- Begin function _Z7maximumPiS_i
	.globl	_Z7maximumPiS_i
	.p2align	8
	.type	_Z7maximumPiS_i,@function
_Z7maximumPiS_i:                        ; @_Z7maximumPiS_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	s_lshl_b32 s6, s15, 8
	s_mov_b32 s4, s15
	s_mov_b32 s7, 0
	s_waitcnt lgkmcnt(0)
	s_cmp_ge_i32 s6, s5
	s_cbranch_scc1 .LBB0_3
; %bb.1:                                ; %.lr.ph.preheader
	s_ashr_i32 s7, s6, 31
	s_add_i32 s10, s6, 0x100
	s_lshl_b64 s[8:9], s[6:7], 2
	s_min_i32 s5, s10, s5
	s_add_u32 s0, s0, s8
	s_addc_u32 s1, s1, s9
	s_mov_b32 s7, 0
.LBB0_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_load_b32 s8, s[0:1], 0x0
	s_add_i32 s6, s6, 1
	s_waitcnt lgkmcnt(0)
	s_max_i32 s7, s8, s7
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_cmp_ge_i32 s6, s5
	s_cbranch_scc0 .LBB0_2
.LBB0_3:                                ; %Flow25
	s_mov_b32 s5, 0
	v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s7
	s_lshl_b64 s[0:1], s[4:5], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	global_store_b32 v0, v1, s[0:1]
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7maximumPiS_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 20
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 2
		.amdhsa_next_free_sgpr 16
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z7maximumPiS_i, .Lfunc_end0-_Z7maximumPiS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 160
; NumSgprs: 16
; NumVgprs: 2
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 16
; NumVGPRsForWavesPerEU: 2
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z7minimumPiS_i         ; -- Begin function _Z7minimumPiS_i
	.globl	_Z7minimumPiS_i
	.p2align	8
	.type	_Z7minimumPiS_i,@function
_Z7minimumPiS_i:                        ; @_Z7minimumPiS_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	s_lshl_b32 s6, s15, 8
	s_mov_b32 s4, s15
	s_mov_b32 s7, 0xf423f
	s_waitcnt lgkmcnt(0)
	s_cmp_ge_i32 s6, s5
	s_cbranch_scc1 .LBB1_3
; %bb.1:                                ; %.lr.ph.preheader
	s_ashr_i32 s7, s6, 31
	s_add_i32 s10, s6, 0x100
	s_lshl_b64 s[8:9], s[6:7], 2
	s_min_i32 s5, s10, s5
	s_add_u32 s0, s0, s8
	s_addc_u32 s1, s1, s9
	s_mov_b32 s7, 0xf423f
.LBB1_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_load_b32 s8, s[0:1], 0x0
	s_add_i32 s6, s6, 1
	s_waitcnt lgkmcnt(0)
	s_min_i32 s7, s8, s7
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_cmp_ge_i32 s6, s5
	s_cbranch_scc0 .LBB1_2
.LBB1_3:                                ; %Flow25
	s_mov_b32 s5, 0
	v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s7
	s_lshl_b64 s[0:1], s[4:5], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	global_store_b32 v0, v1, s[0:1]
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7minimumPiS_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 20
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 2
		.amdhsa_next_free_sgpr 16
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z7minimumPiS_i, .Lfunc_end1-_Z7minimumPiS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 168
; NumSgprs: 16
; NumVgprs: 2
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 16
; NumVGPRsForWavesPerEU: 2
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z3sumPiS_i             ; -- Begin function _Z3sumPiS_i
	.globl	_Z3sumPiS_i
	.p2align	8
	.type	_Z3sumPiS_i,@function
_Z3sumPiS_i:                            ; @_Z3sumPiS_i
; %bb.0:
	s_clause 0x1
	s_load_b32 s5, s[0:1], 0x10
	s_load_b128 s[0:3], s[0:1], 0x0
	s_lshl_b32 s6, s15, 8
	s_mov_b32 s4, s15
	s_mov_b32 s7, 0
	s_waitcnt lgkmcnt(0)
	s_cmp_ge_i32 s6, s5
	s_cbranch_scc1 .LBB2_3
; %bb.1:                                ; %.lr.ph.preheader
	s_ashr_i32 s7, s6, 31
	s_add_i32 s10, s6, 0x100
	s_lshl_b64 s[8:9], s[6:7], 2
	s_min_i32 s5, s10, s5
	s_add_u32 s0, s0, s8
	s_addc_u32 s1, s1, s9
	s_mov_b32 s7, 0
.LBB2_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_load_b32 s8, s[0:1], 0x0
	s_add_i32 s6, s6, 1
	s_waitcnt lgkmcnt(0)
	s_add_i32 s7, s8, s7
	s_add_u32 s0, s0, 4
	s_addc_u32 s1, s1, 0
	s_cmp_ge_i32 s6, s5
	s_cbranch_scc0 .LBB2_2
.LBB2_3:                                ; %Flow22
	s_mov_b32 s5, 0
	v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s7
	s_lshl_b64 s[0:1], s[4:5], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s2, s0
	s_addc_u32 s1, s3, s1
	global_store_b32 v0, v1, s[0:1]
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z3sumPiS_i
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 20
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 2
		.amdhsa_next_free_sgpr 16
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z3sumPiS_i, .Lfunc_end2-_Z3sumPiS_i
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 160
; NumSgprs: 16
; NumVgprs: 2
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 16
; NumVGPRsForWavesPerEU: 2
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	_Z18standard_deviationPiS_id ; -- Begin function _Z18standard_deviationPiS_id
	.globl	_Z18standard_deviationPiS_id
	.p2align	8
	.type	_Z18standard_deviationPiS_id,@function
_Z18standard_deviationPiS_id:           ; @_Z18standard_deviationPiS_id
; %bb.0:
	s_clause 0x1
	s_load_b32 s3, s[0:1], 0x10
	s_load_b128 s[4:7], s[0:1], 0x0
	v_mov_b32_e32 v0, 0
	s_lshl_b32 s8, s15, 8
	s_mov_b32 s2, s15
	s_waitcnt lgkmcnt(0)
	s_cmp_ge_i32 s8, s3
	s_cbranch_scc1 .LBB3_4
; %bb.1:                                ; %.lr.ph.preheader
	s_load_b64 s[0:1], s[0:1], 0x18
	s_ashr_i32 s9, s8, 31
	s_add_i32 s12, s8, 0x100
	v_mov_b32_e32 v0, 0
	v_mov_b32_e32 v1, 0
	s_lshl_b64 s[10:11], s[8:9], 2
	s_min_i32 s3, s12, s3
	s_add_u32 s4, s4, s10
	s_addc_u32 s5, s5, s11
.LBB3_2:                                ; %.lr.ph
                                        ; =>This Inner Loop Header: Depth=1
	s_load_b32 s9, s[4:5], 0x0
	s_add_i32 s8, s8, 1
	s_add_u32 s4, s4, 4
	s_addc_u32 s5, s5, 0
	s_cmp_ge_i32 s8, s3
	s_waitcnt lgkmcnt(0)
	v_cvt_f64_i32_e32 v[2:3], s9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[2:3], v[2:3], -s[0:1]
	v_fma_f64 v[0:1], v[2:3], v[2:3], v[0:1]
	s_cbranch_scc0 .LBB3_2
; %bb.3:                                ; %._crit_edge.loopexit
	s_delay_alu instid0(VALU_DEP_1)
	v_cvt_i32_f64_e32 v0, v[0:1]
.LBB3_4:                                ; %Flow
	s_mov_b32 s3, 0
	v_mov_b32_e32 v1, 0
	s_lshl_b64 s[0:1], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	global_store_b32 v1, v0, s[0:1]
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z18standard_deviationPiS_id
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 32
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_reserve_vcc 0
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z18standard_deviationPiS_id, .Lfunc_end3-_Z18standard_deviationPiS_id
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 196
; NumSgprs: 16
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 1
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 16
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 20
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7maximumPiS_i
    .private_segment_fixed_size: 0
    .sgpr_count:     16
    .sgpr_spill_count: 0
    .symbol:         _Z7maximumPiS_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     2
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 20
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7minimumPiS_i
    .private_segment_fixed_size: 0
    .sgpr_count:     16
    .sgpr_spill_count: 0
    .symbol:         _Z7minimumPiS_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     2
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 20
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z3sumPiS_i
    .private_segment_fixed_size: 0
    .sgpr_count:     16
    .sgpr_spill_count: 0
    .symbol:         _Z3sumPiS_i.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     2
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           8
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 32
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z18standard_deviationPiS_id
    .private_segment_fixed_size: 0
    .sgpr_count:     16
    .sgpr_spill_count: 0
    .symbol:         _Z18standard_deviationPiS_id.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     4
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
