#include <math.h>
#include <malloc.h>
#define ABS(a) (a>0?a:-(a))
#define MAX(a,b) (a>b?a:b)
#define MIN(a,b) (a<b?a:b)

#define BLOCK_SIZE_x 16
#define BLOCK_SIZE_y 16

const float eps=1e-8;

extern "C" void Atx_cone_mf_gpu_new(float *X,float *y,float *sc,float cos_phi,float sin_phi,float *y_det,float *z_det,
	float SO,float OD,float scale,float dy_det,float dz_det,float dz,int nx,int ny,int nz,int na,int nb);


inline __device__ float find_l(float x1_0,float y1_0,float x2_0,float y2_0,float dx,float dy,float x,float y)
{   
	float l=0,dx2,dy2,a,b,slope,tmp,tmp2,xi[2],yi[2],x1,y1;
	int i;

	a=x2_0-x1_0;
	b=y2_0-y1_0;
	dx2=dx/2.0f;
	dy2=dy/2.0f;

	if(a==0)
	{   
		tmp=ABS(x1_0-x);
		if(tmp<=dx2){l=dy;}
	}
	else
	{   
		if(b==0)
		{   
			tmp=ABS(y1_0-y);
		if(tmp<=dy2)
		{
			l=dx;
		}
	}
	else
	{   
		x1=x1_0-x;y1=y1_0-y;
		i=0;
		if(ABS(a)>ABS(b))
		{   
			slope=b/a;
			tmp=slope*(-x1)+y1;
			tmp2=slope*dx2;
			if(ABS(tmp-tmp2)<=dy2)
			{
				xi[i]=-dx2;yi[i]=tmp-tmp2;i++;
			}
			if(ABS(tmp+tmp2)<=dy2)
			{
				xi[i]=dx2;yi[i]=tmp+tmp2;i++;
			}

			if(i<2)
			{   
				slope=a/b;
				tmp=slope*(-y1)+x1;
				tmp2=slope*dy2;
				if(ABS(tmp-tmp2)<=dx2)
				{
					yi[i]=-dy2;xi[i]=tmp-tmp2;i++;
				}
				if(i<2)
				{   
					if(ABS(tmp+tmp2)<=dx2)
					{
					yi[i]=dy2;xi[i]=tmp+tmp2;i++;
					}
				}
			}
	}
	else
	{   
		slope=a/b;
		tmp=slope*(-y1)+x1;
		tmp2=slope*dy2;
		if(ABS(tmp-tmp2)<=dx2)
		{
			yi[i]=-dy2;xi[i]=tmp-tmp2;i++;
		}
		if(ABS(tmp+tmp2)<=dx2)
		{
			yi[i]=dy2;xi[i]=tmp+tmp2;i++;
		}

		if(i<2)
		{   
			slope=b/a;
			tmp=slope*(-x1)+y1;
			tmp2=slope*dx2;
			if(ABS(tmp-tmp2)<=dy2)
			{
				xi[i]=-dx2;yi[i]=tmp-tmp2;i++;
			}
			if(i<2)
			{   
				if(ABS(tmp+tmp2)<=dy2)
				{
					xi[i]=dx2;yi[i]=tmp+tmp2;i++;
				}
			}
		}
		}

		if(i==2)
		{   tmp=xi[1]-xi[0];tmp2=yi[1]-yi[0];
		l=(float)sqrt(tmp*tmp+tmp2*tmp2);
		}
		}
	}
	return l;
}


inline __device__ float find_l_3d(float x1_0,float y1_0,float z1_0,float x2_0,float y2_0,float z2_0,float dx,float dy,float dz,float x,float y,float z)
	// assuming c~=0
	// A method for computing the intersecting length of a voxel with a infinitely-narrow beam
	// A better formula will be supplied to improve the speed.
{   
	float l=0,dx2,dy2,dz2,a,b,c,slope,tmp[2],tmp2[2],tmpx,tmpy,tmpz,xi[2],yi[2],zi[2],x1,y1,z1;
	int i;

	a=x2_0-x1_0;b=y2_0-y1_0;c=z2_0-z1_0;
	dx2=dx/2.0f;dy2=dy/2.0f;dz2=dz/2.0f;

	if(a==0)
	{l=find_l(y1_0,z1_0,y2_0,z2_0,dy,dz,y,z);}
	else
	{   if(b==0)
		{l=find_l(x1_0,z1_0,x2_0,z2_0,dx,dz,x,z);}
	else
	{   x1=x1_0-x;y1=y1_0-y;z1=z1_0-z;
	//            x2=x2_0-x;y2=y2_0-y;z2=z2_0-z;

	i=0;
	if(ABS(a)>ABS(b))
	{   slope=b/a;tmp[0]=slope*(-x1)+y1;tmp2[0]=slope*dx2;
	slope=c/a;tmp[1]=slope*(-x1)+z1;tmp2[1]=slope*dx2;
	if(ABS(tmp[0]-tmp2[0])<=dy2&&ABS(tmp[1]-tmp2[1])<=dz2)
	{xi[i]=-dx2;yi[i]=tmp[0]-tmp2[0];zi[i]=tmp[1]-tmp2[1];i++;}
	if(ABS(tmp[0]+tmp2[0])<=dy2&&ABS(tmp[1]+tmp2[1])<=dz2)
	{xi[i]=dx2;yi[i]=tmp[0]+tmp2[0];zi[i]=tmp[1]+tmp2[1];i++;}

	if(i<2)
	{   slope=a/b;tmp[0]=slope*(-y1)+x1;tmp2[0]=slope*dy2;
	slope=c/b;tmp[1]=slope*(-y1)+z1;tmp2[1]=slope*dy2;
	if(ABS(tmp[0]-tmp2[0])<=dx2&&ABS(tmp[1]-tmp2[1])<=dz2)
	{xi[i]=tmp[0]-tmp2[0];yi[i]=-dy2;zi[i]=tmp[1]-tmp2[1];i++;}
	if(i<2)
	{   if(ABS(tmp[0]+tmp2[0])<=dx2&&ABS(tmp[1]+tmp2[1])<=dz2)
	{xi[i]=tmp[0]+tmp2[0];yi[i]=dy2;zi[i]=tmp[1]+tmp2[1];i++;}
	}
	}

	if(i<2)
	{   slope=a/c;tmp[0]=slope*(-z1)+x1;tmp2[0]=slope*dz2;
	slope=b/c;tmp[1]=slope*(-z1)+y1;tmp2[1]=slope*dz2;
	if(ABS(tmp[0]-tmp2[0])<=dx2&&ABS(tmp[1]-tmp2[1])<=dy2)
	{xi[i]=tmp[0]-tmp2[0];yi[i]=tmp[1]-tmp2[1];zi[i]=-dz2;i++;}
	if(i<2)
	{   if(ABS(tmp[0]+tmp2[0])<=dx2&&ABS(tmp[1]+tmp2[1])<=dy2)
	{xi[i]=tmp[0]+tmp2[0];yi[i]=tmp[1]+tmp2[1];zi[i]=dz2;i++;}
	}
	}
	}
	else
	{   slope=a/b;tmp[0]=slope*(-y1)+x1;tmp2[0]=slope*dy2;
	slope=c/b;tmp[1]=slope*(-y1)+z1;tmp2[1]=slope*dy2;
	if(ABS(tmp[0]-tmp2[0])<=dx2&&ABS(tmp[1]-tmp2[1])<=dz2)
	{xi[i]=tmp[0]-tmp2[0];yi[i]=-dy2;zi[i]=tmp[1]-tmp2[1];i++;}
	if(ABS(tmp[0]+tmp2[0])<=dx2&&ABS(tmp[1]+tmp2[1])<=dz2)
	{xi[i]=tmp[0]+tmp2[0];yi[i]=dy2;zi[i]=tmp[1]+tmp2[1];i++;}

	if(i<2)
	{   slope=b/a;tmp[0]=slope*(-x1)+y1;tmp2[0]=slope*dx2;
	slope=c/a;tmp[1]=slope*(-x1)+z1;tmp2[1]=slope*dx2;
	if(ABS(tmp[0]-tmp2[0])<=dy2&&ABS(tmp[1]-tmp2[1])<=dz2)
	{xi[i]=-dx2;yi[i]=tmp[0]-tmp2[0];zi[i]=tmp[1]-tmp2[1];i++;}
	if(i<2)
	{   if(ABS(tmp[0]+tmp2[0])<=dy2&&ABS(tmp[1]+tmp2[1])<=dz2)
	{xi[i]=dx2;yi[i]=tmp[0]+tmp2[0];zi[i]=tmp[1]+tmp2[1];i++;}
	}
	}

	if(i<2)
	{   slope=a/c;tmp[0]=slope*(-z1)+x1;tmp2[0]=slope*dz2;
	slope=b/c;tmp[1]=slope*(-z1)+y1;tmp2[1]=slope*dz2;
	if(ABS(tmp[0]-tmp2[0])<=dx2&&ABS(tmp[1]-tmp2[1])<=dy2)
	{xi[i]=tmp[0]-tmp2[0];yi[i]=tmp[1]-tmp2[1];zi[i]=-dz2;i++;}
	if(i<2)
	{   if(ABS(tmp[0]+tmp2[0])<=dx2&&ABS(tmp[1]+tmp2[1])<=dy2)
	{xi[i]=tmp[0]+tmp2[0];yi[i]=tmp[1]+tmp2[1];zi[i]=dz2;i++;}
	}
	}
	}

	if(i==2)
	{   tmpx=xi[1]-xi[0];tmpy=yi[1]-yi[0];tmpz=zi[1]-zi[0];
	l=(float)sqrt(tmpx*tmpx+tmpy*tmpy+tmpz*tmpz);
	}
	}
	}
	return l;
}




__global__ void Atx_cone_mf_gpu_new_kernel(float *x,float *y,float *sc,float cos_phi,float sin_phi,float *y_det,float *z_det,
	float SO,float OD,float scale,float dy_det,float dz_det,float dz,int nx,int ny,int nz,int na,int nb)
{
	int bx=blockIdx.x;
	int by=blockIdx.y;
	int tx=threadIdx.x;
	int ty=threadIdx.y;

	int ix=bx*BLOCK_SIZE_x+tx;
	int iy2=by*BLOCK_SIZE_y+ty;

	if(ix<nx&&iy2<ny*nz)
	{   
		int nx2,ny2,nz2,na2,nb2,ia,ib,iy,iz,na_min,na_max,nb_min,nb_max,idx;
		float xc,yc,zc,xr,yr,SD,l,tmp,x1,y1,z1,x2,y2,z2,d;

		SD=SO+OD;
		na2=na/2;nb2=nb/2;
		nx2=nx/2;ny2=ny/2;nz2=nz/2;
		d=(float)sqrt((1+dz*dz)/2);

		iz=(int)floor((float)iy2/(float)ny);
		iy=iy2-iz*ny;
		idx=iz*ny*nx+iy*nx+ix;

		zc=(float)(iz+0.5-nz2)*dz;
		yc=(float)(iy+0.5-ny2);
		xc=(float)(ix+0.5-nx2);


		xr=cos_phi*xc+sin_phi*yc;
		yr=-sin_phi*xc+cos_phi*yc;

		tmp=SD/((xr+SO)*dy_det);
		na_max=(int)floor((yr+1)*tmp+na2);
		na_min=(int)floor((yr-1)*tmp+na2);

		tmp=SD/((xr+SO)*dz_det);
		nb_max=(int)floor((zc+d)*tmp+nb2);
		nb_min=(int)floor((zc-d)*tmp+nb2);

		for(ib=MAX(0,nb_min);ib<=MIN(nb_max,nb-1);ib++)
		{   
			for(ia=MAX(0,na_min);ia<=MIN(na_max,na-1);ia++)
			{   
				x1=cos_phi*(-SO);
				y1=sin_phi*(-SO);
				z1=0.0;
				x2=cos_phi*OD-sin_phi*y_det[ia];
				y2=sin_phi*OD+cos_phi*y_det[ia];
				z2=z_det[ib];
				l=find_l_3d(x1,y1,z1,x2,y2,z2,1.0,1.0,dz,xc,yc,zc);
				x[idx]+=l*y[ib*na+ia];
				sc[idx]+=l;
			}
		}
	 }
}

__global__ void set2zero(float *x,int nx,int nyz)
{	int bx=blockIdx.x;
int by=blockIdx.y;
int tx=threadIdx.x;
int ty=threadIdx.y;

int ix=bx*BLOCK_SIZE_x+tx;
int iy=by*BLOCK_SIZE_y+ty;

if(ix<nx&&iy<nyz)
{x[iy*nx+ix]=0;}
}

__global__ void scalex(float *x,int nx,int nyz,float scale)
{	int bx=blockIdx.x;
int by=blockIdx.y;
int tx=threadIdx.x;
int ty=threadIdx.y;

int ix=bx*BLOCK_SIZE_x+tx;
int iy=by*BLOCK_SIZE_y+ty;

if(ix<nx&&iy<nyz)
{x[iy*nx+ix]*=scale;}
}

extern "C" void Atx_cone_mf_gpu_new(float *X,float *y,float *sc,float cos_phi,float sin_phi,float *y_det,float *z_det,
	float SO,float OD,float scale,float dy_det,float dz_det,float dz,int nx,int ny,int nz,int na,int nb)
{   
	float *x_d,*y_d,*sc_d,*y_det_d,*z_det_d;
	int nd,N;

	N=nx*ny*nz;
	nd=na*nb;

	cudaMalloc(&y_d,nd*sizeof(float));
	cudaMalloc(&x_d,N*sizeof(float));
	cudaMalloc(&sc_d,N*sizeof(float));
	cudaMalloc(&y_det_d,na*sizeof(float));cudaMemcpy(y_det_d,y_det,na*sizeof(float),cudaMemcpyHostToDevice);
	cudaMalloc(&z_det_d,nb*sizeof(float));cudaMemcpy(z_det_d,z_det,nb*sizeof(float),cudaMemcpyHostToDevice);
	cudaMemcpy(y_d,y,nd*sizeof(float),cudaMemcpyHostToDevice);

	dim3 dimBlock(BLOCK_SIZE_x,BLOCK_SIZE_y);
	dim3 dimGrid_t((nx+dimBlock.x-1)/dimBlock.x,(ny*nz+dimBlock.y-1)/dimBlock.y);

	set2zero<<<dimGrid_t, dimBlock>>>(x_d,nx,ny*nz);
	set2zero<<<dimGrid_t, dimBlock>>>(sc_d,nx,ny*nz);

	
	Atx_cone_mf_gpu_new_kernel<<<dimGrid_t, dimBlock>>>(x_d,y_d,sc_d,cos_phi,sin_phi,y_det_d,z_det_d,
		SO,OD,scale,dy_det,dz_det,dz,nx,ny,nz,na,nb);
	cudaThreadSynchronize();
	scalex<<<dimGrid_t, dimBlock>>>(x_d,nx,ny*nz,scale);
	scalex<<<dimGrid_t, dimBlock>>>(sc_d,nx,ny*nz,scale);
	cudaMemcpy(X,x_d,N*sizeof(float),cudaMemcpyDeviceToHost);
	cudaMemcpy(sc,sc_d,N*sizeof(float),cudaMemcpyDeviceToHost);

	cudaFree(x_d);cudaFree(y_d);cudaFree(sc_d);cudaFree(y_det_d);cudaFree(z_det_d);
}




extern "C" void Ax_cone_mf_gpu_new(float *X,float *y,float *sr,float cos_phi,float sin_phi,float *y_det,float *z_det,
float SO,float OD,float scale,float dz,int nx,int ny,int nz,int na,int nb);

__global__ void Ax_cone_mf_gpu_kernel_new(float *x,float *y,float *sr,float cos_phi,float sin_phi,float *y_det,float *z_det,
float SO,float OD,float scale,float dz,int nx,int ny,int nz,int na,int nb)
{
	int bx=blockIdx.x;
	int by=blockIdx.y;
	int tx0=threadIdx.x;
	int ty0=threadIdx.y;

	int ia=bx*BLOCK_SIZE_x+tx0;
	int ib=by*BLOCK_SIZE_y+ty0;

    if(ia<na&&ib<nb)
    {
		int nx2,ny2,nz2,id,ix,iy,iz,cx1,cx2,cy1,cy2,cz1,cz2;
		float x1,y1,x2,y2,z1,z2,xx1,yy1,zz1,xx2,yy2,zz2,slope1,slope2,l,d,tmp,rx,ry,rz;

		nx2=nx/2;
        ny2=ny/2;
        nz2=nz/2;


		id=ib*na+ia;

        x1=cos_phi*(-SO);
        y1=sin_phi*(-SO);
        z1=0.0;
		x2=cos_phi*OD-sin_phi*y_det[ia];
        y2=sin_phi*OD+cos_phi*y_det[ia];
		z2=z_det[ib];

		y[id]=0;
		sr[id]=0;
        // assuming z1-z2 is small
        if(ABS(x1-x2)>ABS(y1-y2))
        {   slope1=(y2-y1)/(x2-x1);
            slope2=(z2-z1)/(x2-x1);
            for(ix=0;ix<nx;ix++)
            {   xx1=(float)(ix-nx2);xx2=xx1+1;
                if(slope1>=0)
                {   yy1=y1+slope1*(xx1-x1)+ny2;
                    yy2=y1+slope1*(xx2-x1)+ny2;
                }
                else
                {   yy1=y1+slope1*(xx2-x1)+ny2;
                    yy2=y1+slope1*(xx1-x1)+ny2;
                }
                cy1=(int)floor(yy1);
                cy2=(int)floor(yy2);
                if(slope2>=0)
                {   zz1=(z1+slope2*(xx1-x1))/dz+nz2;
                    zz2=(z1+slope2*(xx2-x1))/dz+nz2;
                }
                else
                {   zz1=(z1+slope2*(xx2-x1))/dz+nz2;
                    zz2=(z1+slope2*(xx1-x1))/dz+nz2;
                }
                cz1=(int)floor(zz1);
                cz2=(int)floor(zz2);

                if(cy2==cy1)
                {   if(cy1>=0&&cy1<=ny-1)
                    {   if(cz2==cz1)
                        {   if(cz1>=0&&cz1<=nz-1)// 11
                            {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                iy=cy1;iz=cz1;y[id]+=l*x[iz*ny*nx+iy*nx+ix];sr[id]+=l;
                            }
                        }
                        else
                        {   if(cz2>0&&cz2<nz)// 12
                            {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                rz=(cz2-zz1)/(zz2-zz1);
                                iy=cy1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=rz*l;
                                iy=cy1;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-rz)*l;
                            }
                            else
                            {   if(cz2==0)// 13
                                {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    rz=(cz2-zz1)/(zz2-zz1);
                                    iy=cy1;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-rz)*l;
                                }
                                if(cz2==nz)// 14
                                {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    rz=(cz2-zz1)/(zz2-zz1);
                                    iy=cy1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=rz*l;
                                }
                            }
                        }
                    }
                }
                else
                {   if(cy2>0&&cy2<ny)
                    {   if(cz2==cz1)
                        {   if(cz1>=0&&cz1<=nz-1)// 21
                            {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                ry=(cy2-yy1)/d;
                                iy=cy1;iz=cz1;y[id]+=ry*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=ry*l;
                                iy=cy2;iz=cz1;y[id]+=(1-ry)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-ry)*l;
                            }
                        }
                        else
                        {   if(cz2>0&&cz2<nz)// 22
                            {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                ry=(cy2-yy1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                if(ry>rz)
                                {   iy=cy1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=rz*l;
                                    iy=cy1;iz=cz2;y[id]+=(ry-rz)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(ry-rz)*l;
                                    iy=cy2;iz=cz2;y[id]+=(1-ry)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-ry)*l;
                                }
                                else
                                {   iy=cy1;iz=cz1;y[id]+=ry*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=ry*l;
                                    iy=cy2;iz=cz1;y[id]+=(rz-ry)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(rz-ry)*l;
                                    iy=cy2;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-rz)*l;
                                }
                            }
                            else
                            {   if(cz2==0)// 23
                                {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    ry=(cy2-yy1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                    if(ry>rz)
                                    {   iy=cy1;iz=cz2;y[id]+=(ry-rz)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(ry-rz)*l;
                                        iy=cy2;iz=cz2;y[id]+=(1-ry)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-ry)*l;
                                    }
                                    else
                                    {   iy=cy2;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-rz)*l;
                                    }
                                }
                                if(cz2==nz)// 24
                                {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    ry=(cy2-yy1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                    if(ry>rz)
                                    {   iy=cy1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=rz*l;
                                    }
                                    else
                                    {   iy=cy1;iz=cz1;y[id]+=ry*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=ry*l;
                                        iy=cy2;iz=cz1;y[id]+=(rz-ry)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(rz-ry)*l;
                                    }
                                }
                            }
                        }
                    }
                    else
                    {   if(cy2==0)
                        {   if(cz2==cz1)
                            {   if(cz1>=0&&cz1<=nz-1)// 31
                                {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    ry=(cy2-yy1)/d;
                                    iy=cy2;iz=cz1;y[id]+=(1-ry)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-ry)*l;
                                }
                            }
                            else
                            {   if(cz2>0&&cz2<nz)// 32
                                {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    ry=(cy2-yy1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                    if(ry>rz)
                                    {   iy=cy2;iz=cz2;y[id]+=(1-ry)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-ry)*l;
                                    }
                                    else
                                    {   iy=cy2;iz=cz1;y[id]+=(rz-ry)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(rz-ry)*l;
                                        iy=cy2;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-rz)*l;
                                    }
                                }
                                else
                                {   if(cz2==0)// 33
                                    {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                        ry=(cy2-yy1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                        if(ry>rz)
                                        {   iy=cy2;iz=cz2;y[id]+=(1-ry)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-ry)*l;
                                        }
                                        else
                                        {   iy=cy2;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-rz)*l;
                                        }
                                    }
                                    if(cz2==nz)// 34
                                    {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                        ry=(cy2-yy1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                        if(ry>rz)
                                        {
                                        }
                                        else
                                        {   iy=cy2;iz=cz1;y[id]+=(rz-ry)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(rz-ry)*l;
                                        }
                                    }
                                }
                            }
                        }

                        if(cy2==ny)
                        {   if(cz2==cz1)
                            {   if(cz1>=0&&cz1<=nz-1)// 41
                                {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    ry=(cy2-yy1)/d;
                                    iy=cy1;iz=cz1;y[id]+=ry*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=ry*l;
                                }
                            }
                            else
                            {   if(cz2>0&&cz2<nz)// 42
                                {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    ry=(cy2-yy1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                    if(ry>rz)
                                    {   iy=cy1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=rz*l;
                                        iy=cy1;iz=cz2;y[id]+=(ry-rz)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(ry-rz)*l;
                                    }
                                    else
                                    {   iy=cy1;iz=cz1;y[id]+=ry*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=ry*l;
                                    }
                                }
                                else
                                {   if(cz2==0)// 43
                                    {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                        ry=(cy2-yy1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                        if(ry>rz)
                                        {   iy=cy1;iz=cz2;y[id]+=(ry-rz)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(ry-rz)*l;
                                        }
                                        else
                                        {
                                        }
                                    }
                                    if(cz2==nz)// 44
                                    {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                        ry=(cy2-yy1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                        if(ry>rz)
                                        {   iy=cy1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=rz*l;
                                        }
                                        else
                                        {   iy=cy1;iz=cz1;y[id]+=ry*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=ry*l;
                                        }
                                    }
                                }
                            }
                        }
                    }
                }
            }
        }
        else
        {   slope1=(x2-x1)/(y2-y1);
            slope2=(z2-z1)/(y2-y1);
            for(iy=0;iy<ny;iy++)
            {   yy1=(float)(iy-ny2);yy2=yy1+1;
                if(slope1>=0)
                {   xx1=x1+slope1*(yy1-y1)+nx2;
                    xx2=x1+slope1*(yy2-y1)+nx2;
                }
                else
                {   xx1=x1+slope1*(yy2-y1)+nx2;
                    xx2=x1+slope1*(yy1-y1)+nx2;
                }
                cx1=(int)floor(xx1);
                cx2=(int)floor(xx2);
                if(slope2>=0)
                {   zz1=(z1+slope2*(yy1-y1))/dz+nz2;
                    zz2=(z1+slope2*(yy2-y1))/dz+nz2;
                }
                else
                {   zz1=(z1+slope2*(yy2-y1))/dz+nz2;
                    zz2=(z1+slope2*(yy1-y1))/dz+nz2;
                }
                cz1=(int)floor(zz1);
                cz2=(int)floor(zz2);

                if(cx2==cx1)
                {   if(cx1>=0&&cx1<=nx-1)
                    {   if(cz2==cz1)
                        {   if(cz1>=0&&cz1<=nz-1)// 11
                            {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                ix=cx1;iz=cz1;y[id]+=l*x[iz*ny*nx+iy*nx+ix];sr[id]+=l;
                            }
                        }
                        else
                        {   if(cz2>0&&cz2<nz)// 12
                            {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                rz=(cz2-zz1)/(zz2-zz1);
                                ix=cx1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=rz*l;
                                ix=cx1;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-rz)*l;
                            }
                            else
                            {   if(cz2==0)// 13
                                {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    rz=(cz2-zz1)/(zz2-zz1);
                                    ix=cx1;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-rz)*l;
                                }
                                if(cz2==nz)// 14
                                {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    rz=(cz2-zz1)/(zz2-zz1);
                                    ix=cx1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=rz*l;
                                }
                            }
                        }
                    }
                }
                else
                {   if(cx2>0&&cx2<nx)
                    {   if(cz2==cz1)
                        {   if(cz1>=0&&cz1<=nz-1)// 21
                            {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                rx=(cx2-xx1)/d;
                                ix=cx1;iz=cz1;y[id]+=rx*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=rx*l;
                                ix=cx2;iz=cz1;y[id]+=(1-rx)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-rx)*l;
                            }
                        }
                        else
                        {   if(cz2>0&&cz2<nz)// 22
                            {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                rx=(cx2-xx1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                if(rx>rz)
                                {   ix=cx1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=rz*l;
                                    ix=cx1;iz=cz2;y[id]+=(rx-rz)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(rx-rz)*l;
                                    ix=cx2;iz=cz2;y[id]+=(1-rx)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-rx)*l;
                                }
                                else
                                {   ix=cx1;iz=cz1;y[id]+=rx*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=rx*l;
                                    ix=cx2;iz=cz1;y[id]+=(rz-rx)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(rz-rx)*l;
                                    ix=cx2;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-rz)*l;
                                }
                            }
                            else
                            {   if(cz2==0)// 23
                                {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    rx=(cx2-xx1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                    if(rx>rz)
                                    {   ix=cx1;iz=cz2;y[id]+=(rx-rz)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(rx-rz)*l;
                                        ix=cx2;iz=cz2;y[id]+=(1-rx)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-rx)*l;
                                    }
                                    else
                                    {   ix=cx2;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-rz)*l;
                                    }
                                }
                                if(cz2==nz)// 24
                                {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    rx=(cx2-xx1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                    if(rx>rz)
                                    {   ix=cx1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=rz*l;
                                    }
                                    else
                                    {   ix=cx1;iz=cz1;y[id]+=rx*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=rx*l;
                                        ix=cx2;iz=cz1;y[id]+=(rz-rx)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(rz-rx)*l;
                                    }
                                }
                            }
                        }
                    }
                    else
                    {   if(cx2==0)
                        {   if(cz2==cz1)
                            {   if(cz1>=0&&cz1<=nz-1)// 31
                                {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    rx=(cx2-xx1)/d;
                                    ix=cx2;iz=cz1;y[id]+=(1-rx)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-rx)*l;
                                }
                            }
                            else
                            {   if(cz2>0&&cz2<nz)// 32
                                {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    rx=(cx2-xx1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                    if(rx>rz)
                                    {   ix=cx2;iz=cz2;y[id]+=(1-rx)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-rx)*l;
                                    }
                                    else
                                    {   ix=cx2;iz=cz1;y[id]+=(rz-rx)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(rz-rx)*l;
                                        ix=cx2;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-rz)*l;
                                    }
                                }
                                else
                                {   if(cz2==0)// 33
                                    {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                        rx=(cx2-xx1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                        if(rx>rz)
                                        {   ix=cx2;iz=cz2;y[id]+=(1-rx)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-rx)*l;
                                        }
                                        else
                                        {   ix=cx2;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-rz)*l;
                                        }
                                    }
                                    if(cz2==nz)// 34
                                    {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                        rx=(cx2-xx1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                        if(rx>rz)
                                        {
                                        }
                                        else
                                        {   ix=cx2;iz=cz1;y[id]+=(rz-rx)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(rz-rx)*l;
                                        }
                                    }
                                }
                            }
                        }

                        if(cx2==nx)
                        {   if(cz2==cz1)
                            {   if(cz1>=0&&cz1<=nz-1)// 41
                                {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    rx=(cx2-xx1)/d;
                                    ix=cx1;iz=cz1;y[id]+=rx*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=rx*l;
                                }
                            }
                            else
                            {   if(cz2>0&&cz2<nz)// 42
                                {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    rx=(cx2-xx1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                    if(rx>rz)
                                    {   ix=cx1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=rz*l;
                                        ix=cx1;iz=cz2;y[id]+=(rx-rz)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(rx-rz)*l;
                                    }
                                    else
                                    {   ix=cx1;iz=cz1;y[id]+=rx*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=rx*l;
                                    }
                                }
                                else
                                {   if(cz2==0)// 43
                                    {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                        rx=(cx2-xx1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                        if(rx>rz)
                                        {   ix=cx1;iz=cz2;y[id]+=(rx-rz)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(rx-rz)*l;
                                        }
                                        else
                                        {
                                        }
                                    }
                                    if(cz2==nz)// 44
                                    {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                        rx=(cx2-xx1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                        if(rx>rz)
                                        {   ix=cx1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=rz*l;
                                        }
                                        else
                                        {   ix=cx1;iz=cz1;y[id]+=rx*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=rx*l;
                                        }
                                    }
                                }
                            }
                        }
                    }
                }
            }
        }
        y[id]*=scale;sr[id]*=scale;
    }
}

extern "C" void Ax_cone_mf_gpu_new(float *X,float *y,float *sr,float cos_phi,float sin_phi,float *y_det,float *z_det,
float SO,float OD,float scale,float dz,int nx,int ny,int nz,int na,int nb)
{   
	float *y_d,*x_d,*sr_d,*y_det_d,*z_det_d;
	int nd,N;

	N=nx*ny*nz;
	nd=na*nb;

	cudaMalloc((void**)&y_d,nd*sizeof(float));
	cudaMalloc((void**)&x_d,N*sizeof(float));cudaMemcpy(x_d,X,N*sizeof(float),cudaMemcpyHostToDevice);
	cudaMalloc((void**)&sr_d,nd*sizeof(float));
	cudaMalloc((void**)&y_det_d,na*sizeof(float));cudaMemcpy(y_det_d,y_det,na*sizeof(float),cudaMemcpyHostToDevice);
	cudaMalloc((void**)&z_det_d,nb*sizeof(float));cudaMemcpy(z_det_d,z_det,nb*sizeof(float),cudaMemcpyHostToDevice);
	
	//
	dim3 dimBlock(BLOCK_SIZE_x,BLOCK_SIZE_y);
	dim3 dimGrid_t((na+dimBlock.x-1)/dimBlock.x,(nb+dimBlock.y-1)/dimBlock.y);
	Ax_cone_mf_gpu_kernel_new<<<dimGrid_t, dimBlock>>>(x_d,y_d,sr_d,cos_phi,sin_phi,y_det_d,z_det_d,
		SO,OD,scale,dz,nx,ny,nz,na,nb);
	cudaThreadSynchronize();
	cudaMemcpy(y,y_d,na*nb*sizeof(float),cudaMemcpyDeviceToHost);
	cudaMemcpy(sr,sr_d,na*nb*sizeof(float),cudaMemcpyDeviceToHost);

	
	//
    cudaFree(y_d);cudaFree(x_d);cudaFree(y_det_d);cudaFree(z_det_d);cudaFree(sr_d);
}




	.file	"tmpxft_0030f4e3_00000000-6_Ax_cone_gpu.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2033:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2033:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z67__device_stub__Z26Atx_cone_mf_gpu_new_kernelPfS_S_ffS_S_ffffffiiiiiPfS_S_ffS_S_ffffffiiiii
	.type	_Z67__device_stub__Z26Atx_cone_mf_gpu_new_kernelPfS_S_ffS_S_ffffffiiiiiPfS_S_ffS_S_ffffffiiiii, @function
_Z67__device_stub__Z26Atx_cone_mf_gpu_new_kernelPfS_S_ffS_S_ffffffiiiiiPfS_S_ffS_S_ffffffiiiii:
.LFB2055:
	.cfi_startproc
	endbr64
	subq	$312, %rsp
	.cfi_def_cfa_offset 320
	movq	%rdi, 72(%rsp)
	leaq	104(%rsp), %rdi
	movq	%rsi, 64(%rsp)
	leaq	116(%rsp), %rsi
	movq	%rdx, 56(%rsp)
	leaq	88(%rsp), %rdx
	movq	%rcx, 40(%rsp)
	leaq	96(%rsp), %rcx
	movq	%r8, 32(%rsp)
	movl	%r9d, 4(%rsp)
	movss	%xmm0, 52(%rsp)
	movss	%xmm1, 48(%rsp)
	movss	%xmm2, 28(%rsp)
	movss	%xmm3, 24(%rsp)
	movss	%xmm4, 20(%rsp)
	movss	%xmm5, 16(%rsp)
	movss	%xmm6, 12(%rsp)
	movss	%xmm7, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 296(%rsp)
	xorl	%eax, %eax
	leaq	72(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	52(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	320(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	328(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	336(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	344(%rsp), %rax
	movq	%rax, 288(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 104(%rsp)
	movl	$1, 112(%rsp)
	movq	%rax, 116(%rsp)
	movl	$1, 124(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	96(%rsp)
	.cfi_def_cfa_offset 328
	leaq	_Z26Atx_cone_mf_gpu_new_kernelPfS_S_ffS_S_ffffffiiiii(%rip), %rdi
	pushq	96(%rsp)
	.cfi_def_cfa_offset 336
	movq	132(%rsp), %rcx
	movl	140(%rsp), %r8d
	movq	120(%rsp), %rsi
	movl	128(%rsp), %edx
	leaq	168(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 328
	popq	%rdx
	.cfi_def_cfa_offset 320
.L2:
	movq	296(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$312, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2055:
	.size	_Z67__device_stub__Z26Atx_cone_mf_gpu_new_kernelPfS_S_ffS_S_ffffffiiiiiPfS_S_ffS_S_ffffffiiiii, .-_Z67__device_stub__Z26Atx_cone_mf_gpu_new_kernelPfS_S_ffS_S_ffffffiiiiiPfS_S_ffS_S_ffffffiiiii
	.globl	_Z26Atx_cone_mf_gpu_new_kernelPfS_S_ffS_S_ffffffiiiii
	.type	_Z26Atx_cone_mf_gpu_new_kernelPfS_S_ffS_S_ffffffiiiii, @function
_Z26Atx_cone_mf_gpu_new_kernelPfS_S_ffS_S_ffffffiiiii:
.LFB2056:
	.cfi_startproc
	endbr64
	jmp	_Z67__device_stub__Z26Atx_cone_mf_gpu_new_kernelPfS_S_ffS_S_ffffffiiiiiPfS_S_ffS_S_ffffffiiiii
	.cfi_endproc
.LFE2056:
	.size	_Z26Atx_cone_mf_gpu_new_kernelPfS_S_ffS_S_ffffffiiiii, .-_Z26Atx_cone_mf_gpu_new_kernelPfS_S_ffS_S_ffffffiiiii
	.globl	_Z29__device_stub__Z8set2zeroPfiiPfii
	.type	_Z29__device_stub__Z8set2zeroPfiiPfii, @function
_Z29__device_stub__Z8set2zeroPfiiPfii:
.LFB2057:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	32(%rsp), %rdi
	movl	%esi, 4(%rsp)
	leaq	44(%rsp), %rsi
	movl	%edx, (%rsp)
	leaq	16(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	24(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z8set2zeroPfii(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 144
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L8:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2057:
	.size	_Z29__device_stub__Z8set2zeroPfiiPfii, .-_Z29__device_stub__Z8set2zeroPfiiPfii
	.globl	_Z8set2zeroPfii
	.type	_Z8set2zeroPfii, @function
_Z8set2zeroPfii:
.LFB2058:
	.cfi_startproc
	endbr64
	jmp	_Z29__device_stub__Z8set2zeroPfiiPfii
	.cfi_endproc
.LFE2058:
	.size	_Z8set2zeroPfii, .-_Z8set2zeroPfii
	.globl	_Z28__device_stub__Z6scalexPfiifPfiif
	.type	_Z28__device_stub__Z6scalexPfiifPfiif, @function
_Z28__device_stub__Z6scalexPfiifPfiif:
.LFB2059:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	48(%rsp), %rcx
	leaq	56(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	40(%rsp), %rdx
	movss	%xmm0, 12(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z6scalexPfiif(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L13:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2059:
	.size	_Z28__device_stub__Z6scalexPfiifPfiif, .-_Z28__device_stub__Z6scalexPfiifPfiif
	.globl	_Z6scalexPfiif
	.type	_Z6scalexPfiif, @function
_Z6scalexPfiif:
.LFB2060:
	.cfi_startproc
	endbr64
	jmp	_Z28__device_stub__Z6scalexPfiifPfiif
	.cfi_endproc
.LFE2060:
	.size	_Z6scalexPfiif, .-_Z6scalexPfiif
	.globl	Atx_cone_mf_gpu_new
	.type	Atx_cone_mf_gpu_new, @function
Atx_cone_mf_gpu_new:
.LFB2029:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%r9d, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%r9d, %ebx
	subq	$184, %rsp
	.cfi_def_cfa_offset 240
	movq	%r8, 64(%rsp)
	movl	240(%rsp), %r13d
	movq	%rdx, 40(%rsp)
	movl	256(%rsp), %r14d
	movq	%rcx, 56(%rsp)
	movl	264(%rsp), %r15d
	imull	%r13d, %ebp
	movq	%rdi, 24(%rsp)
	movl	248(%rsp), %r12d
	leaq	112(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	movss	%xmm0, 52(%rsp)
	imull	%r12d, %ebp
	movss	%xmm1, 72(%rsp)
	movss	%xmm2, 76(%rsp)
	movss	%xmm3, 80(%rsp)
	movslq	%ebp, %rbp
	movss	%xmm4, 48(%rsp)
	movss	%xmm5, 84(%rsp)
	movss	%xmm6, 88(%rsp)
	movss	%xmm7, 92(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	movl	%r14d, %eax
	imull	%r15d, %eax
	cltq
	salq	$2, %rax
	movq	%rax, %rsi
	movq	%rax, 16(%rsp)
	call	cudaMalloc@PLT
	leaq	0(,%rbp,4), %rax
	leaq	104(%rsp), %rdi
	movslq	%r14d, %rbp
	movq	%rax, %rsi
	movq	%rax, 8(%rsp)
	salq	$2, %rbp
	call	cudaMalloc@PLT
	movq	8(%rsp), %rsi
	leaq	120(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	%rbp, %rsi
	leaq	128(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	%rbp, %rdx
	movq	56(%rsp), %rsi
	movq	128(%rsp), %rdi
	movslq	%r15d, %rbp
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	salq	$2, %rbp
	leaq	136(%rsp), %rdi
	movq	%rbp, %rsi
	call	cudaMalloc@PLT
	movq	64(%rsp), %rsi
	movq	%rbp, %rdx
	movq	136(%rsp), %rdi
	movl	$1, %ecx
	movl	%r13d, %ebp
	call	cudaMemcpy@PLT
	movq	16(%rsp), %rdx
	movq	32(%rsp), %rsi
	imull	%r12d, %ebp
	movq	112(%rsp), %rdi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	leal	15(%rbx), %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	shrl	$4, %eax
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$68719476752, %rdx
	movl	%eax, 156(%rsp)
	leal	15(%rbp), %eax
	shrl	$4, %eax
	movl	$1, 164(%rsp)
	movl	%eax, 160(%rsp)
	movq	156(%rsp), %rdi
	movq	%rdx, 144(%rsp)
	movl	$1, 152(%rsp)
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	movq	104(%rsp), %rdi
	movl	%ebp, %edx
	movl	%ebx, %esi
	call	_Z29__device_stub__Z8set2zeroPfiiPfii
.L19:
	movl	152(%rsp), %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	144(%rsp), %rdx
	movq	156(%rsp), %rdi
	movl	164(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L20
	movq	120(%rsp), %rdi
	movl	%ebp, %edx
	movl	%ebx, %esi
	call	_Z29__device_stub__Z8set2zeroPfiiPfii
.L20:
	movl	152(%rsp), %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	144(%rsp), %rdx
	movq	156(%rsp), %rdi
	movl	164(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L21
	pushq	%r15
	.cfi_def_cfa_offset 248
	movl	%ebx, %r9d
	pushq	%r14
	.cfi_def_cfa_offset 256
	pushq	%r12
	.cfi_def_cfa_offset 264
	pushq	%r13
	.cfi_def_cfa_offset 272
	movss	124(%rsp), %xmm7
	movss	120(%rsp), %xmm6
	movss	116(%rsp), %xmm5
	movss	80(%rsp), %xmm4
	movss	112(%rsp), %xmm3
	movss	108(%rsp), %xmm2
	movq	168(%rsp), %r8
	movq	160(%rsp), %rcx
	movss	104(%rsp), %xmm1
	movss	84(%rsp), %xmm0
	movq	152(%rsp), %rdx
	movq	144(%rsp), %rsi
	movq	136(%rsp), %rdi
	call	_Z67__device_stub__Z26Atx_cone_mf_gpu_new_kernelPfS_S_ffS_S_ffffffiiiiiPfS_S_ffS_S_ffffffiiiii
	addq	$32, %rsp
	.cfi_def_cfa_offset 240
.L21:
	call	cudaThreadSynchronize@PLT
	movl	152(%rsp), %ecx
	xorl	%r9d, %r9d
	movq	144(%rsp), %rdx
	movq	156(%rsp), %rdi
	movl	164(%rsp), %esi
	xorl	%r8d, %r8d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L22
	movss	48(%rsp), %xmm0
	movq	104(%rsp), %rdi
	movl	%ebp, %edx
	movl	%ebx, %esi
	call	_Z28__device_stub__Z6scalexPfiifPfiif
.L22:
	movl	152(%rsp), %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	144(%rsp), %rdx
	movq	156(%rsp), %rdi
	movl	164(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L23
	movss	48(%rsp), %xmm0
	movq	120(%rsp), %rdi
	movl	%ebp, %edx
	movl	%ebx, %esi
	call	_Z28__device_stub__Z6scalexPfiifPfiif
.L23:
	movq	8(%rsp), %rdx
	movq	104(%rsp), %rsi
	movl	$2, %ecx
	movq	24(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdx
	movq	120(%rsp), %rsi
	movl	$2, %ecx
	movq	40(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	104(%rsp), %rdi
	call	cudaFree@PLT
	movq	112(%rsp), %rdi
	call	cudaFree@PLT
	movq	120(%rsp), %rdi
	call	cudaFree@PLT
	movq	128(%rsp), %rdi
	call	cudaFree@PLT
	movq	136(%rsp), %rdi
	call	cudaFree@PLT
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L24
	call	__stack_chk_fail@PLT
.L24:
	addq	$184, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2029:
	.size	Atx_cone_mf_gpu_new, .-Atx_cone_mf_gpu_new
	.globl	_Z64__device_stub__Z25Ax_cone_mf_gpu_kernel_newPfS_S_ffS_S_ffffiiiiiPfS_S_ffS_S_ffffiiiii
	.type	_Z64__device_stub__Z25Ax_cone_mf_gpu_kernel_newPfS_S_ffS_S_ffffiiiiiPfS_S_ffS_S_ffffiiiii, @function
_Z64__device_stub__Z25Ax_cone_mf_gpu_kernel_newPfS_S_ffS_S_ffffiiiiiPfS_S_ffS_S_ffffiiiii:
.LFB2061:
	.cfi_startproc
	endbr64
	subq	$296, %rsp
	.cfi_def_cfa_offset 304
	movq	%rdi, 72(%rsp)
	leaq	104(%rsp), %rdi
	movq	%rsi, 64(%rsp)
	leaq	116(%rsp), %rsi
	movq	%rdx, 56(%rsp)
	leaq	88(%rsp), %rdx
	movq	%rcx, 40(%rsp)
	leaq	96(%rsp), %rcx
	movq	%r8, 32(%rsp)
	movl	%r9d, 12(%rsp)
	movss	%xmm0, 52(%rsp)
	movss	%xmm1, 48(%rsp)
	movss	%xmm2, 28(%rsp)
	movss	%xmm3, 24(%rsp)
	movss	%xmm4, 20(%rsp)
	movss	%xmm5, 16(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 280(%rsp)
	xorl	%eax, %eax
	leaq	72(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	52(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	304(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	312(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	320(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	328(%rsp), %rax
	movq	%rax, 272(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 104(%rsp)
	movl	$1, 112(%rsp)
	movq	%rax, 116(%rsp)
	movl	$1, 124(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L26
	pushq	96(%rsp)
	.cfi_def_cfa_offset 312
	leaq	_Z25Ax_cone_mf_gpu_kernel_newPfS_S_ffS_S_ffffiiiii(%rip), %rdi
	pushq	96(%rsp)
	.cfi_def_cfa_offset 320
	movq	132(%rsp), %rcx
	movl	140(%rsp), %r8d
	movq	120(%rsp), %rsi
	movl	128(%rsp), %edx
	leaq	168(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 312
	popq	%rdx
	.cfi_def_cfa_offset 304
.L26:
	movq	280(%rsp), %rax
	subq	%fs:40, %rax
	je	.L28
	call	__stack_chk_fail@PLT
.L28:
	addq	$296, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2061:
	.size	_Z64__device_stub__Z25Ax_cone_mf_gpu_kernel_newPfS_S_ffS_S_ffffiiiiiPfS_S_ffS_S_ffffiiiii, .-_Z64__device_stub__Z25Ax_cone_mf_gpu_kernel_newPfS_S_ffS_S_ffffiiiiiPfS_S_ffS_S_ffffiiiii
	.globl	_Z25Ax_cone_mf_gpu_kernel_newPfS_S_ffS_S_ffffiiiii
	.type	_Z25Ax_cone_mf_gpu_kernel_newPfS_S_ffS_S_ffffiiiii, @function
_Z25Ax_cone_mf_gpu_kernel_newPfS_S_ffS_S_ffffiiiii:
.LFB2062:
	.cfi_startproc
	endbr64
	jmp	_Z64__device_stub__Z25Ax_cone_mf_gpu_kernel_newPfS_S_ffS_S_ffffiiiiiPfS_S_ffS_S_ffffiiiii
	.cfi_endproc
.LFE2062:
	.size	_Z25Ax_cone_mf_gpu_kernel_newPfS_S_ffS_S_ffffiiiii, .-_Z25Ax_cone_mf_gpu_kernel_newPfS_S_ffS_S_ffffiiiii
	.globl	Ax_cone_mf_gpu_new
	.type	Ax_cone_mf_gpu_new, @function
Ax_cone_mf_gpu_new:
.LFB2030:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movq	%rcx, %r15
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rdi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%r9d, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	subq	$152, %rsp
	.cfi_def_cfa_offset 208
	movq	%r8, 32(%rsp)
	movl	224(%rsp), %r14d
	leaq	72(%rsp), %rdi
	movq	%rdx, 24(%rsp)
	movl	232(%rsp), %r13d
	movq	%rsi, 16(%rsp)
	movl	208(%rsp), %ebx
	movss	%xmm0, 60(%rsp)
	movss	%xmm1, 56(%rsp)
	imull	%r9d, %ebx
	movss	%xmm2, 52(%rsp)
	imull	216(%rsp), %ebx
	movss	%xmm3, 48(%rsp)
	movss	%xmm4, 44(%rsp)
	movss	%xmm5, 40(%rsp)
	movslq	%ebx, %rbx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	movl	%r14d, %eax
	salq	$2, %rbx
	imull	%r13d, %eax
	cltq
	salq	$2, %rax
	movq	%rax, %rsi
	movq	%rax, 8(%rsp)
	call	cudaMalloc@PLT
	movq	%rbx, %rsi
	leaq	80(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	80(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r12, %rsi
	movl	$1, %ecx
	movslq	%r14d, %rbx
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rsi
	salq	$2, %rbx
	leaq	88(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	%rbx, %rsi
	leaq	96(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	%rbx, %rdx
	movq	96(%rsp), %rdi
	movslq	%r13d, %rbx
	movl	$1, %ecx
	salq	$2, %rbx
	movq	%r15, %rsi
	call	cudaMemcpy@PLT
	leaq	104(%rsp), %rdi
	movq	%rbx, %rsi
	call	cudaMalloc@PLT
	movq	32(%rsp), %rsi
	movq	104(%rsp), %rdi
	movq	%rbx, %rdx
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	leal	15(%r14), %eax
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	shrl	$4, %eax
	movl	$1, %ecx
	movl	$1, %esi
	movabsq	$68719476752, %rdx
	movl	%eax, 124(%rsp)
	leal	15(%r13), %eax
	shrl	$4, %eax
	movl	%eax, 128(%rsp)
	movq	124(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	movss	40(%rsp), %xmm5
	movss	44(%rsp), %xmm4
	testl	%eax, %eax
	movss	48(%rsp), %xmm3
	movss	52(%rsp), %xmm2
	movss	56(%rsp), %xmm1
	movss	60(%rsp), %xmm0
	jne	.L32
	pushq	%r13
	.cfi_def_cfa_offset 216
	movl	%ebp, %r9d
	pushq	%r14
	.cfi_def_cfa_offset 224
	movl	232(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 232
	movl	232(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 240
	movq	136(%rsp), %r8
	movq	128(%rsp), %rcx
	movq	120(%rsp), %rdx
	movq	104(%rsp), %rsi
	movq	112(%rsp), %rdi
	call	_Z64__device_stub__Z25Ax_cone_mf_gpu_kernel_newPfS_S_ffS_S_ffffiiiiiPfS_S_ffS_S_ffffiiiii
	addq	$32, %rsp
	.cfi_def_cfa_offset 208
.L32:
	call	cudaThreadSynchronize@PLT
	movq	8(%rsp), %rdx
	movq	72(%rsp), %rsi
	movl	$2, %ecx
	movq	16(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdx
	movq	88(%rsp), %rsi
	movl	$2, %ecx
	movq	24(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	72(%rsp), %rdi
	call	cudaFree@PLT
	movq	80(%rsp), %rdi
	call	cudaFree@PLT
	movq	96(%rsp), %rdi
	call	cudaFree@PLT
	movq	104(%rsp), %rdi
	call	cudaFree@PLT
	movq	88(%rsp), %rdi
	call	cudaFree@PLT
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L33
	call	__stack_chk_fail@PLT
.L33:
	addq	$152, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2030:
	.size	Ax_cone_mf_gpu_new, .-Ax_cone_mf_gpu_new
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z25Ax_cone_mf_gpu_kernel_newPfS_S_ffS_S_ffffiiiii"
.LC1:
	.string	"_Z6scalexPfiif"
.LC2:
	.string	"_Z8set2zeroPfii"
.LC3:
	.string	"_Z26Atx_cone_mf_gpu_new_kernelPfS_S_ffS_S_ffffffiiiii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2064:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z25Ax_cone_mf_gpu_kernel_newPfS_S_ffS_S_ffffiiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z6scalexPfiif(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z8set2zeroPfii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC3(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z26Atx_cone_mf_gpu_new_kernelPfS_S_ffS_S_ffffffiiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2064:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include <math.h>
#include <malloc.h>
#define ABS(a) (a>0?a:-(a))
#define MAX(a,b) (a>b?a:b)
#define MIN(a,b) (a<b?a:b)

#define BLOCK_SIZE_x 16
#define BLOCK_SIZE_y 16

const float eps=1e-8;

extern "C" void Atx_cone_mf_gpu_new(float *X,float *y,float *sc,float cos_phi,float sin_phi,float *y_det,float *z_det,
	float SO,float OD,float scale,float dy_det,float dz_det,float dz,int nx,int ny,int nz,int na,int nb);


inline __device__ float find_l(float x1_0,float y1_0,float x2_0,float y2_0,float dx,float dy,float x,float y)
{   
	float l=0,dx2,dy2,a,b,slope,tmp,tmp2,xi[2],yi[2],x1,y1;
	int i;

	a=x2_0-x1_0;
	b=y2_0-y1_0;
	dx2=dx/2.0f;
	dy2=dy/2.0f;

	if(a==0)
	{   
		tmp=ABS(x1_0-x);
		if(tmp<=dx2){l=dy;}
	}
	else
	{   
		if(b==0)
		{   
			tmp=ABS(y1_0-y);
		if(tmp<=dy2)
		{
			l=dx;
		}
	}
	else
	{   
		x1=x1_0-x;y1=y1_0-y;
		i=0;
		if(ABS(a)>ABS(b))
		{   
			slope=b/a;
			tmp=slope*(-x1)+y1;
			tmp2=slope*dx2;
			if(ABS(tmp-tmp2)<=dy2)
			{
				xi[i]=-dx2;yi[i]=tmp-tmp2;i++;
			}
			if(ABS(tmp+tmp2)<=dy2)
			{
				xi[i]=dx2;yi[i]=tmp+tmp2;i++;
			}

			if(i<2)
			{   
				slope=a/b;
				tmp=slope*(-y1)+x1;
				tmp2=slope*dy2;
				if(ABS(tmp-tmp2)<=dx2)
				{
					yi[i]=-dy2;xi[i]=tmp-tmp2;i++;
				}
				if(i<2)
				{   
					if(ABS(tmp+tmp2)<=dx2)
					{
					yi[i]=dy2;xi[i]=tmp+tmp2;i++;
					}
				}
			}
	}
	else
	{   
		slope=a/b;
		tmp=slope*(-y1)+x1;
		tmp2=slope*dy2;
		if(ABS(tmp-tmp2)<=dx2)
		{
			yi[i]=-dy2;xi[i]=tmp-tmp2;i++;
		}
		if(ABS(tmp+tmp2)<=dx2)
		{
			yi[i]=dy2;xi[i]=tmp+tmp2;i++;
		}

		if(i<2)
		{   
			slope=b/a;
			tmp=slope*(-x1)+y1;
			tmp2=slope*dx2;
			if(ABS(tmp-tmp2)<=dy2)
			{
				xi[i]=-dx2;yi[i]=tmp-tmp2;i++;
			}
			if(i<2)
			{   
				if(ABS(tmp+tmp2)<=dy2)
				{
					xi[i]=dx2;yi[i]=tmp+tmp2;i++;
				}
			}
		}
		}

		if(i==2)
		{   tmp=xi[1]-xi[0];tmp2=yi[1]-yi[0];
		l=(float)sqrt(tmp*tmp+tmp2*tmp2);
		}
		}
	}
	return l;
}


inline __device__ float find_l_3d(float x1_0,float y1_0,float z1_0,float x2_0,float y2_0,float z2_0,float dx,float dy,float dz,float x,float y,float z)
	// assuming c~=0
	// A method for computing the intersecting length of a voxel with a infinitely-narrow beam
	// A better formula will be supplied to improve the speed.
{   
	float l=0,dx2,dy2,dz2,a,b,c,slope,tmp[2],tmp2[2],tmpx,tmpy,tmpz,xi[2],yi[2],zi[2],x1,y1,z1;
	int i;

	a=x2_0-x1_0;b=y2_0-y1_0;c=z2_0-z1_0;
	dx2=dx/2.0f;dy2=dy/2.0f;dz2=dz/2.0f;

	if(a==0)
	{l=find_l(y1_0,z1_0,y2_0,z2_0,dy,dz,y,z);}
	else
	{   if(b==0)
		{l=find_l(x1_0,z1_0,x2_0,z2_0,dx,dz,x,z);}
	else
	{   x1=x1_0-x;y1=y1_0-y;z1=z1_0-z;
	//            x2=x2_0-x;y2=y2_0-y;z2=z2_0-z;

	i=0;
	if(ABS(a)>ABS(b))
	{   slope=b/a;tmp[0]=slope*(-x1)+y1;tmp2[0]=slope*dx2;
	slope=c/a;tmp[1]=slope*(-x1)+z1;tmp2[1]=slope*dx2;
	if(ABS(tmp[0]-tmp2[0])<=dy2&&ABS(tmp[1]-tmp2[1])<=dz2)
	{xi[i]=-dx2;yi[i]=tmp[0]-tmp2[0];zi[i]=tmp[1]-tmp2[1];i++;}
	if(ABS(tmp[0]+tmp2[0])<=dy2&&ABS(tmp[1]+tmp2[1])<=dz2)
	{xi[i]=dx2;yi[i]=tmp[0]+tmp2[0];zi[i]=tmp[1]+tmp2[1];i++;}

	if(i<2)
	{   slope=a/b;tmp[0]=slope*(-y1)+x1;tmp2[0]=slope*dy2;
	slope=c/b;tmp[1]=slope*(-y1)+z1;tmp2[1]=slope*dy2;
	if(ABS(tmp[0]-tmp2[0])<=dx2&&ABS(tmp[1]-tmp2[1])<=dz2)
	{xi[i]=tmp[0]-tmp2[0];yi[i]=-dy2;zi[i]=tmp[1]-tmp2[1];i++;}
	if(i<2)
	{   if(ABS(tmp[0]+tmp2[0])<=dx2&&ABS(tmp[1]+tmp2[1])<=dz2)
	{xi[i]=tmp[0]+tmp2[0];yi[i]=dy2;zi[i]=tmp[1]+tmp2[1];i++;}
	}
	}

	if(i<2)
	{   slope=a/c;tmp[0]=slope*(-z1)+x1;tmp2[0]=slope*dz2;
	slope=b/c;tmp[1]=slope*(-z1)+y1;tmp2[1]=slope*dz2;
	if(ABS(tmp[0]-tmp2[0])<=dx2&&ABS(tmp[1]-tmp2[1])<=dy2)
	{xi[i]=tmp[0]-tmp2[0];yi[i]=tmp[1]-tmp2[1];zi[i]=-dz2;i++;}
	if(i<2)
	{   if(ABS(tmp[0]+tmp2[0])<=dx2&&ABS(tmp[1]+tmp2[1])<=dy2)
	{xi[i]=tmp[0]+tmp2[0];yi[i]=tmp[1]+tmp2[1];zi[i]=dz2;i++;}
	}
	}
	}
	else
	{   slope=a/b;tmp[0]=slope*(-y1)+x1;tmp2[0]=slope*dy2;
	slope=c/b;tmp[1]=slope*(-y1)+z1;tmp2[1]=slope*dy2;
	if(ABS(tmp[0]-tmp2[0])<=dx2&&ABS(tmp[1]-tmp2[1])<=dz2)
	{xi[i]=tmp[0]-tmp2[0];yi[i]=-dy2;zi[i]=tmp[1]-tmp2[1];i++;}
	if(ABS(tmp[0]+tmp2[0])<=dx2&&ABS(tmp[1]+tmp2[1])<=dz2)
	{xi[i]=tmp[0]+tmp2[0];yi[i]=dy2;zi[i]=tmp[1]+tmp2[1];i++;}

	if(i<2)
	{   slope=b/a;tmp[0]=slope*(-x1)+y1;tmp2[0]=slope*dx2;
	slope=c/a;tmp[1]=slope*(-x1)+z1;tmp2[1]=slope*dx2;
	if(ABS(tmp[0]-tmp2[0])<=dy2&&ABS(tmp[1]-tmp2[1])<=dz2)
	{xi[i]=-dx2;yi[i]=tmp[0]-tmp2[0];zi[i]=tmp[1]-tmp2[1];i++;}
	if(i<2)
	{   if(ABS(tmp[0]+tmp2[0])<=dy2&&ABS(tmp[1]+tmp2[1])<=dz2)
	{xi[i]=dx2;yi[i]=tmp[0]+tmp2[0];zi[i]=tmp[1]+tmp2[1];i++;}
	}
	}

	if(i<2)
	{   slope=a/c;tmp[0]=slope*(-z1)+x1;tmp2[0]=slope*dz2;
	slope=b/c;tmp[1]=slope*(-z1)+y1;tmp2[1]=slope*dz2;
	if(ABS(tmp[0]-tmp2[0])<=dx2&&ABS(tmp[1]-tmp2[1])<=dy2)
	{xi[i]=tmp[0]-tmp2[0];yi[i]=tmp[1]-tmp2[1];zi[i]=-dz2;i++;}
	if(i<2)
	{   if(ABS(tmp[0]+tmp2[0])<=dx2&&ABS(tmp[1]+tmp2[1])<=dy2)
	{xi[i]=tmp[0]+tmp2[0];yi[i]=tmp[1]+tmp2[1];zi[i]=dz2;i++;}
	}
	}
	}

	if(i==2)
	{   tmpx=xi[1]-xi[0];tmpy=yi[1]-yi[0];tmpz=zi[1]-zi[0];
	l=(float)sqrt(tmpx*tmpx+tmpy*tmpy+tmpz*tmpz);
	}
	}
	}
	return l;
}




__global__ void Atx_cone_mf_gpu_new_kernel(float *x,float *y,float *sc,float cos_phi,float sin_phi,float *y_det,float *z_det,
	float SO,float OD,float scale,float dy_det,float dz_det,float dz,int nx,int ny,int nz,int na,int nb)
{
	int bx=blockIdx.x;
	int by=blockIdx.y;
	int tx=threadIdx.x;
	int ty=threadIdx.y;

	int ix=bx*BLOCK_SIZE_x+tx;
	int iy2=by*BLOCK_SIZE_y+ty;

	if(ix<nx&&iy2<ny*nz)
	{   
		int nx2,ny2,nz2,na2,nb2,ia,ib,iy,iz,na_min,na_max,nb_min,nb_max,idx;
		float xc,yc,zc,xr,yr,SD,l,tmp,x1,y1,z1,x2,y2,z2,d;

		SD=SO+OD;
		na2=na/2;nb2=nb/2;
		nx2=nx/2;ny2=ny/2;nz2=nz/2;
		d=(float)sqrt((1+dz*dz)/2);

		iz=(int)floor((float)iy2/(float)ny);
		iy=iy2-iz*ny;
		idx=iz*ny*nx+iy*nx+ix;

		zc=(float)(iz+0.5-nz2)*dz;
		yc=(float)(iy+0.5-ny2);
		xc=(float)(ix+0.5-nx2);


		xr=cos_phi*xc+sin_phi*yc;
		yr=-sin_phi*xc+cos_phi*yc;

		tmp=SD/((xr+SO)*dy_det);
		na_max=(int)floor((yr+1)*tmp+na2);
		na_min=(int)floor((yr-1)*tmp+na2);

		tmp=SD/((xr+SO)*dz_det);
		nb_max=(int)floor((zc+d)*tmp+nb2);
		nb_min=(int)floor((zc-d)*tmp+nb2);

		for(ib=MAX(0,nb_min);ib<=MIN(nb_max,nb-1);ib++)
		{   
			for(ia=MAX(0,na_min);ia<=MIN(na_max,na-1);ia++)
			{   
				x1=cos_phi*(-SO);
				y1=sin_phi*(-SO);
				z1=0.0;
				x2=cos_phi*OD-sin_phi*y_det[ia];
				y2=sin_phi*OD+cos_phi*y_det[ia];
				z2=z_det[ib];
				l=find_l_3d(x1,y1,z1,x2,y2,z2,1.0,1.0,dz,xc,yc,zc);
				x[idx]+=l*y[ib*na+ia];
				sc[idx]+=l;
			}
		}
	 }
}

__global__ void set2zero(float *x,int nx,int nyz)
{	int bx=blockIdx.x;
int by=blockIdx.y;
int tx=threadIdx.x;
int ty=threadIdx.y;

int ix=bx*BLOCK_SIZE_x+tx;
int iy=by*BLOCK_SIZE_y+ty;

if(ix<nx&&iy<nyz)
{x[iy*nx+ix]=0;}
}

__global__ void scalex(float *x,int nx,int nyz,float scale)
{	int bx=blockIdx.x;
int by=blockIdx.y;
int tx=threadIdx.x;
int ty=threadIdx.y;

int ix=bx*BLOCK_SIZE_x+tx;
int iy=by*BLOCK_SIZE_y+ty;

if(ix<nx&&iy<nyz)
{x[iy*nx+ix]*=scale;}
}

extern "C" void Atx_cone_mf_gpu_new(float *X,float *y,float *sc,float cos_phi,float sin_phi,float *y_det,float *z_det,
	float SO,float OD,float scale,float dy_det,float dz_det,float dz,int nx,int ny,int nz,int na,int nb)
{   
	float *x_d,*y_d,*sc_d,*y_det_d,*z_det_d;
	int nd,N;

	N=nx*ny*nz;
	nd=na*nb;

	hipMalloc(&y_d,nd*sizeof(float));
	hipMalloc(&x_d,N*sizeof(float));
	hipMalloc(&sc_d,N*sizeof(float));
	hipMalloc(&y_det_d,na*sizeof(float));hipMemcpy(y_det_d,y_det,na*sizeof(float),hipMemcpyHostToDevice);
	hipMalloc(&z_det_d,nb*sizeof(float));hipMemcpy(z_det_d,z_det,nb*sizeof(float),hipMemcpyHostToDevice);
	hipMemcpy(y_d,y,nd*sizeof(float),hipMemcpyHostToDevice);

	dim3 dimBlock(BLOCK_SIZE_x,BLOCK_SIZE_y);
	dim3 dimGrid_t((nx+dimBlock.x-1)/dimBlock.x,(ny*nz+dimBlock.y-1)/dimBlock.y);

	set2zero<<<dimGrid_t, dimBlock>>>(x_d,nx,ny*nz);
	set2zero<<<dimGrid_t, dimBlock>>>(sc_d,nx,ny*nz);

	
	Atx_cone_mf_gpu_new_kernel<<<dimGrid_t, dimBlock>>>(x_d,y_d,sc_d,cos_phi,sin_phi,y_det_d,z_det_d,
		SO,OD,scale,dy_det,dz_det,dz,nx,ny,nz,na,nb);
	hipDeviceSynchronize();
	scalex<<<dimGrid_t, dimBlock>>>(x_d,nx,ny*nz,scale);
	scalex<<<dimGrid_t, dimBlock>>>(sc_d,nx,ny*nz,scale);
	hipMemcpy(X,x_d,N*sizeof(float),hipMemcpyDeviceToHost);
	hipMemcpy(sc,sc_d,N*sizeof(float),hipMemcpyDeviceToHost);

	hipFree(x_d);hipFree(y_d);hipFree(sc_d);hipFree(y_det_d);hipFree(z_det_d);
}




extern "C" void Ax_cone_mf_gpu_new(float *X,float *y,float *sr,float cos_phi,float sin_phi,float *y_det,float *z_det,
float SO,float OD,float scale,float dz,int nx,int ny,int nz,int na,int nb);

__global__ void Ax_cone_mf_gpu_kernel_new(float *x,float *y,float *sr,float cos_phi,float sin_phi,float *y_det,float *z_det,
float SO,float OD,float scale,float dz,int nx,int ny,int nz,int na,int nb)
{
	int bx=blockIdx.x;
	int by=blockIdx.y;
	int tx0=threadIdx.x;
	int ty0=threadIdx.y;

	int ia=bx*BLOCK_SIZE_x+tx0;
	int ib=by*BLOCK_SIZE_y+ty0;

    if(ia<na&&ib<nb)
    {
		int nx2,ny2,nz2,id,ix,iy,iz,cx1,cx2,cy1,cy2,cz1,cz2;
		float x1,y1,x2,y2,z1,z2,xx1,yy1,zz1,xx2,yy2,zz2,slope1,slope2,l,d,tmp,rx,ry,rz;

		nx2=nx/2;
        ny2=ny/2;
        nz2=nz/2;


		id=ib*na+ia;

        x1=cos_phi*(-SO);
        y1=sin_phi*(-SO);
        z1=0.0;
		x2=cos_phi*OD-sin_phi*y_det[ia];
        y2=sin_phi*OD+cos_phi*y_det[ia];
		z2=z_det[ib];

		y[id]=0;
		sr[id]=0;
        // assuming z1-z2 is small
        if(ABS(x1-x2)>ABS(y1-y2))
        {   slope1=(y2-y1)/(x2-x1);
            slope2=(z2-z1)/(x2-x1);
            for(ix=0;ix<nx;ix++)
            {   xx1=(float)(ix-nx2);xx2=xx1+1;
                if(slope1>=0)
                {   yy1=y1+slope1*(xx1-x1)+ny2;
                    yy2=y1+slope1*(xx2-x1)+ny2;
                }
                else
                {   yy1=y1+slope1*(xx2-x1)+ny2;
                    yy2=y1+slope1*(xx1-x1)+ny2;
                }
                cy1=(int)floor(yy1);
                cy2=(int)floor(yy2);
                if(slope2>=0)
                {   zz1=(z1+slope2*(xx1-x1))/dz+nz2;
                    zz2=(z1+slope2*(xx2-x1))/dz+nz2;
                }
                else
                {   zz1=(z1+slope2*(xx2-x1))/dz+nz2;
                    zz2=(z1+slope2*(xx1-x1))/dz+nz2;
                }
                cz1=(int)floor(zz1);
                cz2=(int)floor(zz2);

                if(cy2==cy1)
                {   if(cy1>=0&&cy1<=ny-1)
                    {   if(cz2==cz1)
                        {   if(cz1>=0&&cz1<=nz-1)// 11
                            {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                iy=cy1;iz=cz1;y[id]+=l*x[iz*ny*nx+iy*nx+ix];sr[id]+=l;
                            }
                        }
                        else
                        {   if(cz2>0&&cz2<nz)// 12
                            {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                rz=(cz2-zz1)/(zz2-zz1);
                                iy=cy1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=rz*l;
                                iy=cy1;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-rz)*l;
                            }
                            else
                            {   if(cz2==0)// 13
                                {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    rz=(cz2-zz1)/(zz2-zz1);
                                    iy=cy1;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-rz)*l;
                                }
                                if(cz2==nz)// 14
                                {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    rz=(cz2-zz1)/(zz2-zz1);
                                    iy=cy1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=rz*l;
                                }
                            }
                        }
                    }
                }
                else
                {   if(cy2>0&&cy2<ny)
                    {   if(cz2==cz1)
                        {   if(cz1>=0&&cz1<=nz-1)// 21
                            {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                ry=(cy2-yy1)/d;
                                iy=cy1;iz=cz1;y[id]+=ry*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=ry*l;
                                iy=cy2;iz=cz1;y[id]+=(1-ry)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-ry)*l;
                            }
                        }
                        else
                        {   if(cz2>0&&cz2<nz)// 22
                            {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                ry=(cy2-yy1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                if(ry>rz)
                                {   iy=cy1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=rz*l;
                                    iy=cy1;iz=cz2;y[id]+=(ry-rz)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(ry-rz)*l;
                                    iy=cy2;iz=cz2;y[id]+=(1-ry)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-ry)*l;
                                }
                                else
                                {   iy=cy1;iz=cz1;y[id]+=ry*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=ry*l;
                                    iy=cy2;iz=cz1;y[id]+=(rz-ry)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(rz-ry)*l;
                                    iy=cy2;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-rz)*l;
                                }
                            }
                            else
                            {   if(cz2==0)// 23
                                {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    ry=(cy2-yy1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                    if(ry>rz)
                                    {   iy=cy1;iz=cz2;y[id]+=(ry-rz)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(ry-rz)*l;
                                        iy=cy2;iz=cz2;y[id]+=(1-ry)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-ry)*l;
                                    }
                                    else
                                    {   iy=cy2;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-rz)*l;
                                    }
                                }
                                if(cz2==nz)// 24
                                {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    ry=(cy2-yy1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                    if(ry>rz)
                                    {   iy=cy1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=rz*l;
                                    }
                                    else
                                    {   iy=cy1;iz=cz1;y[id]+=ry*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=ry*l;
                                        iy=cy2;iz=cz1;y[id]+=(rz-ry)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(rz-ry)*l;
                                    }
                                }
                            }
                        }
                    }
                    else
                    {   if(cy2==0)
                        {   if(cz2==cz1)
                            {   if(cz1>=0&&cz1<=nz-1)// 31
                                {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    ry=(cy2-yy1)/d;
                                    iy=cy2;iz=cz1;y[id]+=(1-ry)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-ry)*l;
                                }
                            }
                            else
                            {   if(cz2>0&&cz2<nz)// 32
                                {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    ry=(cy2-yy1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                    if(ry>rz)
                                    {   iy=cy2;iz=cz2;y[id]+=(1-ry)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-ry)*l;
                                    }
                                    else
                                    {   iy=cy2;iz=cz1;y[id]+=(rz-ry)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(rz-ry)*l;
                                        iy=cy2;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-rz)*l;
                                    }
                                }
                                else
                                {   if(cz2==0)// 33
                                    {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                        ry=(cy2-yy1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                        if(ry>rz)
                                        {   iy=cy2;iz=cz2;y[id]+=(1-ry)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-ry)*l;
                                        }
                                        else
                                        {   iy=cy2;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-rz)*l;
                                        }
                                    }
                                    if(cz2==nz)// 34
                                    {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                        ry=(cy2-yy1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                        if(ry>rz)
                                        {
                                        }
                                        else
                                        {   iy=cy2;iz=cz1;y[id]+=(rz-ry)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(rz-ry)*l;
                                        }
                                    }
                                }
                            }
                        }

                        if(cy2==ny)
                        {   if(cz2==cz1)
                            {   if(cz1>=0&&cz1<=nz-1)// 41
                                {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    ry=(cy2-yy1)/d;
                                    iy=cy1;iz=cz1;y[id]+=ry*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=ry*l;
                                }
                            }
                            else
                            {   if(cz2>0&&cz2<nz)// 42
                                {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    ry=(cy2-yy1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                    if(ry>rz)
                                    {   iy=cy1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=rz*l;
                                        iy=cy1;iz=cz2;y[id]+=(ry-rz)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(ry-rz)*l;
                                    }
                                    else
                                    {   iy=cy1;iz=cz1;y[id]+=ry*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=ry*l;
                                    }
                                }
                                else
                                {   if(cz2==0)// 43
                                    {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                        ry=(cy2-yy1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                        if(ry>rz)
                                        {   iy=cy1;iz=cz2;y[id]+=(ry-rz)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(ry-rz)*l;
                                        }
                                        else
                                        {
                                        }
                                    }
                                    if(cz2==nz)// 44
                                    {   d=yy2-yy1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                        ry=(cy2-yy1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                        if(ry>rz)
                                        {   iy=cy1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=rz*l;
                                        }
                                        else
                                        {   iy=cy1;iz=cz1;y[id]+=ry*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=ry*l;
                                        }
                                    }
                                }
                            }
                        }
                    }
                }
            }
        }
        else
        {   slope1=(x2-x1)/(y2-y1);
            slope2=(z2-z1)/(y2-y1);
            for(iy=0;iy<ny;iy++)
            {   yy1=(float)(iy-ny2);yy2=yy1+1;
                if(slope1>=0)
                {   xx1=x1+slope1*(yy1-y1)+nx2;
                    xx2=x1+slope1*(yy2-y1)+nx2;
                }
                else
                {   xx1=x1+slope1*(yy2-y1)+nx2;
                    xx2=x1+slope1*(yy1-y1)+nx2;
                }
                cx1=(int)floor(xx1);
                cx2=(int)floor(xx2);
                if(slope2>=0)
                {   zz1=(z1+slope2*(yy1-y1))/dz+nz2;
                    zz2=(z1+slope2*(yy2-y1))/dz+nz2;
                }
                else
                {   zz1=(z1+slope2*(yy2-y1))/dz+nz2;
                    zz2=(z1+slope2*(yy1-y1))/dz+nz2;
                }
                cz1=(int)floor(zz1);
                cz2=(int)floor(zz2);

                if(cx2==cx1)
                {   if(cx1>=0&&cx1<=nx-1)
                    {   if(cz2==cz1)
                        {   if(cz1>=0&&cz1<=nz-1)// 11
                            {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                ix=cx1;iz=cz1;y[id]+=l*x[iz*ny*nx+iy*nx+ix];sr[id]+=l;
                            }
                        }
                        else
                        {   if(cz2>0&&cz2<nz)// 12
                            {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                rz=(cz2-zz1)/(zz2-zz1);
                                ix=cx1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=rz*l;
                                ix=cx1;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-rz)*l;
                            }
                            else
                            {   if(cz2==0)// 13
                                {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    rz=(cz2-zz1)/(zz2-zz1);
                                    ix=cx1;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-rz)*l;
                                }
                                if(cz2==nz)// 14
                                {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    rz=(cz2-zz1)/(zz2-zz1);
                                    ix=cx1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=rz*l;
                                }
                            }
                        }
                    }
                }
                else
                {   if(cx2>0&&cx2<nx)
                    {   if(cz2==cz1)
                        {   if(cz1>=0&&cz1<=nz-1)// 21
                            {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                rx=(cx2-xx1)/d;
                                ix=cx1;iz=cz1;y[id]+=rx*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=rx*l;
                                ix=cx2;iz=cz1;y[id]+=(1-rx)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-rx)*l;
                            }
                        }
                        else
                        {   if(cz2>0&&cz2<nz)// 22
                            {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                rx=(cx2-xx1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                if(rx>rz)
                                {   ix=cx1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=rz*l;
                                    ix=cx1;iz=cz2;y[id]+=(rx-rz)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(rx-rz)*l;
                                    ix=cx2;iz=cz2;y[id]+=(1-rx)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-rx)*l;
                                }
                                else
                                {   ix=cx1;iz=cz1;y[id]+=rx*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=rx*l;
                                    ix=cx2;iz=cz1;y[id]+=(rz-rx)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(rz-rx)*l;
                                    ix=cx2;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-rz)*l;
                                }
                            }
                            else
                            {   if(cz2==0)// 23
                                {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    rx=(cx2-xx1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                    if(rx>rz)
                                    {   ix=cx1;iz=cz2;y[id]+=(rx-rz)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(rx-rz)*l;
                                        ix=cx2;iz=cz2;y[id]+=(1-rx)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-rx)*l;
                                    }
                                    else
                                    {   ix=cx2;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-rz)*l;
                                    }
                                }
                                if(cz2==nz)// 24
                                {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    rx=(cx2-xx1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                    if(rx>rz)
                                    {   ix=cx1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=rz*l;
                                    }
                                    else
                                    {   ix=cx1;iz=cz1;y[id]+=rx*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=rx*l;
                                        ix=cx2;iz=cz1;y[id]+=(rz-rx)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(rz-rx)*l;
                                    }
                                }
                            }
                        }
                    }
                    else
                    {   if(cx2==0)
                        {   if(cz2==cz1)
                            {   if(cz1>=0&&cz1<=nz-1)// 31
                                {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    rx=(cx2-xx1)/d;
                                    ix=cx2;iz=cz1;y[id]+=(1-rx)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-rx)*l;
                                }
                            }
                            else
                            {   if(cz2>0&&cz2<nz)// 32
                                {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    rx=(cx2-xx1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                    if(rx>rz)
                                    {   ix=cx2;iz=cz2;y[id]+=(1-rx)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-rx)*l;
                                    }
                                    else
                                    {   ix=cx2;iz=cz1;y[id]+=(rz-rx)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(rz-rx)*l;
                                        ix=cx2;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-rz)*l;
                                    }
                                }
                                else
                                {   if(cz2==0)// 33
                                    {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                        rx=(cx2-xx1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                        if(rx>rz)
                                        {   ix=cx2;iz=cz2;y[id]+=(1-rx)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-rx)*l;
                                        }
                                        else
                                        {   ix=cx2;iz=cz2;y[id]+=(1-rz)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(1-rz)*l;
                                        }
                                    }
                                    if(cz2==nz)// 34
                                    {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                        rx=(cx2-xx1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                        if(rx>rz)
                                        {
                                        }
                                        else
                                        {   ix=cx2;iz=cz1;y[id]+=(rz-rx)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(rz-rx)*l;
                                        }
                                    }
                                }
                            }
                        }

                        if(cx2==nx)
                        {   if(cz2==cz1)
                            {   if(cz1>=0&&cz1<=nz-1)// 41
                                {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    rx=(cx2-xx1)/d;
                                    ix=cx1;iz=cz1;y[id]+=rx*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=rx*l;
                                }
                            }
                            else
                            {   if(cz2>0&&cz2<nz)// 42
                                {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                    rx=(cx2-xx1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                    if(rx>rz)
                                    {   ix=cx1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=rz*l;
                                        ix=cx1;iz=cz2;y[id]+=(rx-rz)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(rx-rz)*l;
                                    }
                                    else
                                    {   ix=cx1;iz=cz1;y[id]+=rx*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=rx*l;
                                    }
                                }
                                else
                                {   if(cz2==0)// 43
                                    {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                        rx=(cx2-xx1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                        if(rx>rz)
                                        {   ix=cx1;iz=cz2;y[id]+=(rx-rz)*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=(rx-rz)*l;
                                        }
                                        else
                                        {
                                        }
                                    }
                                    if(cz2==nz)// 44
                                    {   d=xx2-xx1;tmp=(x1-x2)*(x1-x2)+(y1-y2)*(y1-y2);l=(float)sqrt((d*d+1)*(tmp+(z1-z2)*(z1-z2))/tmp);
                                        rx=(cx2-xx1)/d;rz=(cz2-zz1)/(zz2-zz1);
                                        if(rx>rz)
                                        {   ix=cx1;iz=cz1;y[id]+=rz*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=rz*l;
                                        }
                                        else
                                        {   ix=cx1;iz=cz1;y[id]+=rx*l*x[iz*ny*nx+iy*nx+ix];sr[id]+=rx*l;
                                        }
                                    }
                                }
                            }
                        }
                    }
                }
            }
        }
        y[id]*=scale;sr[id]*=scale;
    }
}

extern "C" void Ax_cone_mf_gpu_new(float *X,float *y,float *sr,float cos_phi,float sin_phi,float *y_det,float *z_det,
float SO,float OD,float scale,float dz,int nx,int ny,int nz,int na,int nb)
{   
	float *y_d,*x_d,*sr_d,*y_det_d,*z_det_d;
	int nd,N;

	N=nx*ny*nz;
	nd=na*nb;

	hipMalloc((void**)&y_d,nd*sizeof(float));
	hipMalloc((void**)&x_d,N*sizeof(float));hipMemcpy(x_d,X,N*sizeof(float),hipMemcpyHostToDevice);
	hipMalloc((void**)&sr_d,nd*sizeof(float));
	hipMalloc((void**)&y_det_d,na*sizeof(float));hipMemcpy(y_det_d,y_det,na*sizeof(float),hipMemcpyHostToDevice);
	hipMalloc((void**)&z_det_d,nb*sizeof(float));hipMemcpy(z_det_d,z_det,nb*sizeof(float),hipMemcpyHostToDevice);
	
	//
	dim3 dimBlock(BLOCK_SIZE_x,BLOCK_SIZE_y);
	dim3 dimGrid_t((na+dimBlock.x-1)/dimBlock.x,(nb+dimBlock.y-1)/dimBlock.y);
	Ax_cone_mf_gpu_kernel_new<<<dimGrid_t, dimBlock>>>(x_d,y_d,sr_d,cos_phi,sin_phi,y_det_d,z_det_d,
		SO,OD,scale,dz,nx,ny,nz,na,nb);
	hipDeviceSynchronize();
	hipMemcpy(y,y_d,na*nb*sizeof(float),hipMemcpyDeviceToHost);
	hipMemcpy(sr,sr_d,na*nb*sizeof(float),hipMemcpyDeviceToHost);

	
	//
    hipFree(y_d);hipFree(x_d);hipFree(y_det_d);hipFree(z_det_d);hipFree(sr_d);
}




	.text
	.file	"Ax_cone_gpu.hip"
	.globl	_Z41__device_stub__Atx_cone_mf_gpu_new_kernelPfS_S_ffS_S_ffffffiiiii # -- Begin function _Z41__device_stub__Atx_cone_mf_gpu_new_kernelPfS_S_ffS_S_ffffffiiiii
	.type	_Z41__device_stub__Atx_cone_mf_gpu_new_kernelPfS_S_ffS_S_ffffffiiiii,@function
_Z41__device_stub__Atx_cone_mf_gpu_new_kernelPfS_S_ffS_S_ffffffiiiii: # @_Z41__device_stub__Atx_cone_mf_gpu_new_kernelPfS_S_ffS_S_ffffffiiiii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$280, %rsp                      # imm = 0x118
	.cfi_def_cfa_offset 336
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%rsp, %rax
	movq	%rdi, (%rax)
	leaq	88(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	80(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	44(%rsp), %rdx
	movss	%xmm0, (%rdx)
	leaq	40(%rsp), %r10
	movss	%xmm1, (%r10)
	leaq	72(%rsp), %r11
	movq	%rcx, (%r11)
	leaq	64(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	36(%rsp), %r8
	movss	%xmm2, (%r8)
	leaq	32(%rsp), %r14
	movss	%xmm3, (%r14)
	leaq	28(%rsp), %r15
	movss	%xmm4, (%r15)
	leaq	24(%rsp), %r12
	movss	%xmm5, (%r12)
	leaq	20(%rsp), %r13
	movss	%xmm6, (%r13)
	leaq	16(%rsp), %rbp
	movss	%xmm7, (%rbp)
	leaq	12(%rsp), %rax
	movl	%r9d, (%rax)
	leaq	128(%rsp), %rbx
	movq	%rsp, %r9
	movq	%r9, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r10, 32(%rbx)
	movq	%r11, 40(%rbx)
	movq	%rcx, 48(%rbx)
	movq	%r8, 56(%rbx)
	movq	%r14, 64(%rbx)
	movq	%r15, 72(%rbx)
	movq	%r12, 80(%rbx)
	movq	%r13, 88(%rbx)
	movq	%rbp, 96(%rbx)
	movq	%rax, 104(%rbx)
	leaq	336(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	344(%rsp), %rax
	movq	%rax, 120(%rbx)
	leaq	352(%rsp), %rax
	movq	%rax, 128(%rbx)
	leaq	360(%rsp), %rax
	movq	%rax, 136(%rbx)
	leaq	112(%rsp), %r14
	leaq	96(%rsp), %r15
	leaq	56(%rsp), %r12
	leaq	48(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z26Atx_cone_mf_gpu_new_kernelPfS_S_ffS_S_ffffffiiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$296, %rsp                      # imm = 0x128
	.cfi_adjust_cfa_offset -296
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z41__device_stub__Atx_cone_mf_gpu_new_kernelPfS_S_ffS_S_ffffffiiiii, .Lfunc_end0-_Z41__device_stub__Atx_cone_mf_gpu_new_kernelPfS_S_ffS_S_ffffffiiiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__set2zeroPfii # -- Begin function _Z23__device_stub__set2zeroPfii
	.type	_Z23__device_stub__set2zeroPfii,@function
_Z23__device_stub__set2zeroPfii:        # @_Z23__device_stub__set2zeroPfii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$96, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	movq	%rsp, %rsi
	movl	%edx, (%rsi)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8set2zeroPfii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$112, %rsp
	.cfi_adjust_cfa_offset -112
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z23__device_stub__set2zeroPfii, .Lfunc_end1-_Z23__device_stub__set2zeroPfii
	.cfi_endproc
                                        # -- End function
	.globl	_Z21__device_stub__scalexPfiif  # -- Begin function _Z21__device_stub__scalexPfiif
	.type	_Z21__device_stub__scalexPfiif,@function
_Z21__device_stub__scalexPfiif:         # @_Z21__device_stub__scalexPfiif
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rcx
	movl	%esi, (%rcx)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movss	%xmm0, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6scalexPfiif, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z21__device_stub__scalexPfiif, .Lfunc_end2-_Z21__device_stub__scalexPfiif
	.cfi_endproc
                                        # -- End function
	.globl	Atx_cone_mf_gpu_new             # -- Begin function Atx_cone_mf_gpu_new
	.type	Atx_cone_mf_gpu_new,@function
Atx_cone_mf_gpu_new:                    # @Atx_cone_mf_gpu_new
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$136, %rsp
	.cfi_def_cfa_offset 192
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, %r13d
	movss	%xmm7, 68(%rsp)                 # 4-byte Spill
	movss	%xmm6, 64(%rsp)                 # 4-byte Spill
	movss	%xmm5, 60(%rsp)                 # 4-byte Spill
	movss	%xmm4, 4(%rsp)                  # 4-byte Spill
	movss	%xmm3, 56(%rsp)                 # 4-byte Spill
	movss	%xmm2, 52(%rsp)                 # 4-byte Spill
	movq	%r8, 96(%rsp)                   # 8-byte Spill
	movq	%rcx, 24(%rsp)                  # 8-byte Spill
	movss	%xmm1, 48(%rsp)                 # 4-byte Spill
	movss	%xmm0, 44(%rsp)                 # 4-byte Spill
	movq	%rdx, 128(%rsp)                 # 8-byte Spill
	movq	%rsi, 104(%rsp)                 # 8-byte Spill
	movq	%rdi, 120(%rsp)                 # 8-byte Spill
	movslq	216(%rsp), %r12
	movslq	208(%rsp), %r14
	movl	200(%rsp), %r15d
	movl	192(%rsp), %eax
                                        # kill: def $r15d killed $r15d killed $r15 def $r15
	imull	%eax, %r15d
	movl	%r15d, %ebx
	imull	%r9d, %ebx
	movl	%r12d, %eax
	imull	%r14d, %eax
	movslq	%eax, %rbp
	shlq	$2, %rbp
	leaq	32(%rsp), %rdi
	movq	%rbp, %rsi
	callq	hipMalloc
	movslq	%ebx, %rbx
	shlq	$2, %rbx
	leaq	16(%rsp), %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movq	%rbx, 112(%rsp)                 # 8-byte Spill
	movq	%rbx, %rsi
	callq	hipMalloc
	movq	%r14, 88(%rsp)                  # 8-byte Spill
	movq	%r14, %rbx
	shlq	$2, %rbx
	leaq	80(%rsp), %r14
	movq	%r14, %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	movq	(%r14), %rdi
	movq	24(%rsp), %rsi                  # 8-byte Reload
	movq	%rbx, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%r12, 24(%rsp)                  # 8-byte Spill
	shlq	$2, %r12
	leaq	72(%rsp), %r14
	movq	%r14, %rdi
	movq	%r12, %rsi
	callq	hipMalloc
	movq	(%r14), %rdi
	movq	%r13, %r14
	movabsq	$68719476752, %r13              # imm = 0x1000000010
	movq	96(%rsp), %rsi                  # 8-byte Reload
	movq	%r12, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leaq	32(%rsp), %rax
	movq	(%rax), %rdi
	movq	104(%rsp), %rsi                 # 8-byte Reload
	movq	%rbp, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leal	15(%r14), %eax
	shrl	$4, %eax
	leal	15(%r15), %ebx
	shrl	$4, %ebx
	shlq	$32, %rbx
	orq	%rax, %rbx
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_2
# %bb.1:
	movq	16(%rsp), %rdi
	movl	%r14d, %esi
	movl	%r15d, %edx
	callq	_Z23__device_stub__set2zeroPfii
.LBB3_2:
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_4
# %bb.3:
	movq	8(%rsp), %rdi
	movl	%r14d, %esi
	movl	%r15d, %edx
	callq	_Z23__device_stub__set2zeroPfii
.LBB3_4:
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_6
# %bb.5:
	movq	16(%rsp), %rdi
	movq	32(%rsp), %rsi
	movq	8(%rsp), %rdx
	movq	80(%rsp), %rcx
	movq	72(%rsp), %r8
	movss	44(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movss	48(%rsp), %xmm1                 # 4-byte Reload
                                        # xmm1 = mem[0],zero,zero,zero
	movss	52(%rsp), %xmm2                 # 4-byte Reload
                                        # xmm2 = mem[0],zero,zero,zero
	movss	56(%rsp), %xmm3                 # 4-byte Reload
                                        # xmm3 = mem[0],zero,zero,zero
	movss	4(%rsp), %xmm4                  # 4-byte Reload
                                        # xmm4 = mem[0],zero,zero,zero
	movss	60(%rsp), %xmm5                 # 4-byte Reload
                                        # xmm5 = mem[0],zero,zero,zero
	movss	64(%rsp), %xmm6                 # 4-byte Reload
                                        # xmm6 = mem[0],zero,zero,zero
	movss	68(%rsp), %xmm7                 # 4-byte Reload
                                        # xmm7 = mem[0],zero,zero,zero
	movl	%r14d, %r9d
	pushq	24(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	pushq	96(%rsp)                        # 8-byte Folded Reload
	.cfi_adjust_cfa_offset 8
	movl	216(%rsp), %eax
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	movl	216(%rsp), %eax
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	callq	_Z41__device_stub__Atx_cone_mf_gpu_new_kernelPfS_S_ffS_S_ffffffiiiii
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
.LBB3_6:
	callq	hipDeviceSynchronize
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_8
# %bb.7:
	movq	16(%rsp), %rdi
	movl	%r14d, %esi
	movl	%r15d, %edx
	movss	4(%rsp), %xmm0                  # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	callq	_Z21__device_stub__scalexPfiif
.LBB3_8:
	movq	%rbx, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB3_10
# %bb.9:
	movq	8(%rsp), %rdi
	movl	%r14d, %esi
	movl	%r15d, %edx
	movss	4(%rsp), %xmm0                  # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	callq	_Z21__device_stub__scalexPfiif
.LBB3_10:
	movq	16(%rsp), %rsi
	movq	120(%rsp), %rdi                 # 8-byte Reload
	movq	112(%rsp), %rbx                 # 8-byte Reload
	movq	%rbx, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rsi
	movq	128(%rsp), %rdi                 # 8-byte Reload
	movq	%rbx, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	16(%rsp), %rdi
	callq	hipFree
	movq	32(%rsp), %rdi
	callq	hipFree
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	80(%rsp), %rdi
	callq	hipFree
	movq	72(%rsp), %rdi
	callq	hipFree
	addq	$136, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	Atx_cone_mf_gpu_new, .Lfunc_end3-Atx_cone_mf_gpu_new
	.cfi_endproc
                                        # -- End function
	.globl	_Z40__device_stub__Ax_cone_mf_gpu_kernel_newPfS_S_ffS_S_ffffiiiii # -- Begin function _Z40__device_stub__Ax_cone_mf_gpu_kernel_newPfS_S_ffS_S_ffffiiiii
	.type	_Z40__device_stub__Ax_cone_mf_gpu_kernel_newPfS_S_ffS_S_ffffiiiii,@function
_Z40__device_stub__Ax_cone_mf_gpu_kernel_newPfS_S_ffS_S_ffffiiiii: # @_Z40__device_stub__Ax_cone_mf_gpu_kernel_newPfS_S_ffS_S_ffffiiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$256, %rsp                      # imm = 0x100
	.cfi_def_cfa_offset 304
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	88(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	80(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	72(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	36(%rsp), %rdx
	movss	%xmm0, (%rdx)
	leaq	32(%rsp), %r10
	movss	%xmm1, (%r10)
	leaq	64(%rsp), %r11
	movq	%rcx, (%r11)
	leaq	56(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	28(%rsp), %r8
	movss	%xmm2, (%r8)
	leaq	24(%rsp), %r14
	movss	%xmm3, (%r14)
	leaq	20(%rsp), %r15
	movss	%xmm4, (%r15)
	leaq	16(%rsp), %r12
	movss	%xmm5, (%r12)
	leaq	12(%rsp), %r13
	movl	%r9d, (%r13)
	leaq	128(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r10, 32(%rbx)
	movq	%r11, 40(%rbx)
	movq	%rcx, 48(%rbx)
	movq	%r8, 56(%rbx)
	movq	%r14, 64(%rbx)
	movq	%r15, 72(%rbx)
	movq	%r12, 80(%rbx)
	movq	%r13, 88(%rbx)
	leaq	304(%rsp), %rax
	movq	%rax, 96(%rbx)
	leaq	312(%rsp), %rax
	movq	%rax, 104(%rbx)
	leaq	320(%rsp), %rax
	movq	%rax, 112(%rbx)
	leaq	328(%rsp), %rax
	movq	%rax, 120(%rbx)
	leaq	112(%rsp), %r14
	leaq	96(%rsp), %r15
	leaq	48(%rsp), %r12
	leaq	40(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z25Ax_cone_mf_gpu_kernel_newPfS_S_ffS_S_ffffiiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$272, %rsp                      # imm = 0x110
	.cfi_adjust_cfa_offset -272
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end4:
	.size	_Z40__device_stub__Ax_cone_mf_gpu_kernel_newPfS_S_ffS_S_ffffiiiii, .Lfunc_end4-_Z40__device_stub__Ax_cone_mf_gpu_kernel_newPfS_S_ffS_S_ffffiiiii
	.cfi_endproc
                                        # -- End function
	.globl	Ax_cone_mf_gpu_new              # -- Begin function Ax_cone_mf_gpu_new
	.type	Ax_cone_mf_gpu_new,@function
Ax_cone_mf_gpu_new:                     # @Ax_cone_mf_gpu_new
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$104, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movss	%xmm5, 40(%rsp)                 # 4-byte Spill
	movss	%xmm4, 36(%rsp)                 # 4-byte Spill
	movss	%xmm3, 32(%rsp)                 # 4-byte Spill
	movss	%xmm2, 28(%rsp)                 # 4-byte Spill
	movq	%r8, 80(%rsp)                   # 8-byte Spill
	movq	%rcx, 72(%rsp)                  # 8-byte Spill
	movss	%xmm1, 24(%rsp)                 # 4-byte Spill
	movss	%xmm0, 20(%rsp)                 # 4-byte Spill
	movq	%rdx, 96(%rsp)                  # 8-byte Spill
	movq	%rsi, 88(%rsp)                  # 8-byte Spill
	movq	%rdi, %rbx
	movslq	184(%rsp), %r13
	movslq	176(%rsp), %r12
	movl	168(%rsp), %ecx
	movl	160(%rsp), %eax
	movl	%eax, %ebp
	movl	%r9d, 44(%rsp)                  # 4-byte Spill
	imull	%r9d, %ebp
	imull	%ecx, %ebp
	movl	%r13d, %eax
	imull	%r12d, %eax
	movslq	%eax, %r15
	shlq	$2, %r15
	leaq	8(%rsp), %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	movslq	%ebp, %r14
	shlq	$2, %r14
	leaq	64(%rsp), %rbp
	movq	%rbp, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	movq	(%rbp), %rdi
	movq	%rbx, %rsi
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%rsp, %rdi
	movq	%r15, %rsi
	callq	hipMalloc
	movq	%r12, %rbx
	shlq	$2, %rbx
	leaq	56(%rsp), %r14
	movq	%r14, %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	movq	(%r14), %rdi
	movq	72(%rsp), %rsi                  # 8-byte Reload
	movq	%rbx, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movq	%r13, %rbx
	shlq	$2, %rbx
	leaq	48(%rsp), %r14
	movq	%r14, %rdi
	movq	%rbx, %rsi
	callq	hipMalloc
	movq	(%r14), %rdi
	movq	80(%rsp), %rsi                  # 8-byte Reload
	movq	%rbx, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	leal	15(%r12), %eax
	shrl	$4, %eax
	leal	15(%r13), %edi
	shrl	$4, %edi
	shlq	$32, %rdi
	orq	%rax, %rdi
	movabsq	$68719476752, %rdx              # imm = 0x1000000010
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB5_2
# %bb.1:
	movq	64(%rsp), %rdi
	movq	8(%rsp), %rsi
	movq	(%rsp), %rdx
	movq	56(%rsp), %rcx
	movq	48(%rsp), %r8
	movss	20(%rsp), %xmm0                 # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movss	24(%rsp), %xmm1                 # 4-byte Reload
                                        # xmm1 = mem[0],zero,zero,zero
	movss	28(%rsp), %xmm2                 # 4-byte Reload
                                        # xmm2 = mem[0],zero,zero,zero
	movss	32(%rsp), %xmm3                 # 4-byte Reload
                                        # xmm3 = mem[0],zero,zero,zero
	movss	36(%rsp), %xmm4                 # 4-byte Reload
                                        # xmm4 = mem[0],zero,zero,zero
	movss	40(%rsp), %xmm5                 # 4-byte Reload
                                        # xmm5 = mem[0],zero,zero,zero
	movl	44(%rsp), %r9d                  # 4-byte Reload
	pushq	%r13
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	movl	184(%rsp), %eax
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	movl	184(%rsp), %eax
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	callq	_Z40__device_stub__Ax_cone_mf_gpu_kernel_newPfS_S_ffS_S_ffffiiiii
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
.LBB5_2:
	callq	hipDeviceSynchronize
	movq	8(%rsp), %rsi
	movq	88(%rsp), %rdi                  # 8-byte Reload
	movq	%r15, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	(%rsp), %rsi
	movq	96(%rsp), %rdi                  # 8-byte Reload
	movq	%r15, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rdi
	callq	hipFree
	movq	64(%rsp), %rdi
	callq	hipFree
	movq	56(%rsp), %rdi
	callq	hipFree
	movq	48(%rsp), %rdi
	callq	hipFree
	movq	(%rsp), %rdi
	callq	hipFree
	addq	$104, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end5:
	.size	Ax_cone_mf_gpu_new, .Lfunc_end5-Ax_cone_mf_gpu_new
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB6_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB6_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z26Atx_cone_mf_gpu_new_kernelPfS_S_ffS_S_ffffffiiiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8set2zeroPfii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6scalexPfiif, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z25Ax_cone_mf_gpu_kernel_newPfS_S_ffS_S_ffffiiiii, %esi
	movl	$.L__unnamed_4, %edx
	movl	$.L__unnamed_4, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end6:
	.size	__hip_module_ctor, .Lfunc_end6-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB7_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB7_2:
	retq
.Lfunc_end7:
	.size	__hip_module_dtor, .Lfunc_end7-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z26Atx_cone_mf_gpu_new_kernelPfS_S_ffS_S_ffffffiiiii,@object # @_Z26Atx_cone_mf_gpu_new_kernelPfS_S_ffS_S_ffffffiiiii
	.section	.rodata,"a",@progbits
	.globl	_Z26Atx_cone_mf_gpu_new_kernelPfS_S_ffS_S_ffffffiiiii
	.p2align	3, 0x0
_Z26Atx_cone_mf_gpu_new_kernelPfS_S_ffS_S_ffffffiiiii:
	.quad	_Z41__device_stub__Atx_cone_mf_gpu_new_kernelPfS_S_ffS_S_ffffffiiiii
	.size	_Z26Atx_cone_mf_gpu_new_kernelPfS_S_ffS_S_ffffffiiiii, 8

	.type	_Z8set2zeroPfii,@object         # @_Z8set2zeroPfii
	.globl	_Z8set2zeroPfii
	.p2align	3, 0x0
_Z8set2zeroPfii:
	.quad	_Z23__device_stub__set2zeroPfii
	.size	_Z8set2zeroPfii, 8

	.type	_Z6scalexPfiif,@object          # @_Z6scalexPfiif
	.globl	_Z6scalexPfiif
	.p2align	3, 0x0
_Z6scalexPfiif:
	.quad	_Z21__device_stub__scalexPfiif
	.size	_Z6scalexPfiif, 8

	.type	_Z25Ax_cone_mf_gpu_kernel_newPfS_S_ffS_S_ffffiiiii,@object # @_Z25Ax_cone_mf_gpu_kernel_newPfS_S_ffS_S_ffffiiiii
	.globl	_Z25Ax_cone_mf_gpu_kernel_newPfS_S_ffS_S_ffffiiiii
	.p2align	3, 0x0
_Z25Ax_cone_mf_gpu_kernel_newPfS_S_ffS_S_ffffiiiii:
	.quad	_Z40__device_stub__Ax_cone_mf_gpu_kernel_newPfS_S_ffS_S_ffffiiiii
	.size	_Z25Ax_cone_mf_gpu_kernel_newPfS_S_ffS_S_ffffiiiii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z26Atx_cone_mf_gpu_new_kernelPfS_S_ffS_S_ffffffiiiii"
	.size	.L__unnamed_1, 54

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z8set2zeroPfii"
	.size	.L__unnamed_2, 16

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z6scalexPfiif"
	.size	.L__unnamed_3, 15

	.type	.L__unnamed_4,@object           # @3
.L__unnamed_4:
	.asciz	"_Z25Ax_cone_mf_gpu_kernel_newPfS_S_ffS_S_ffffiiiii"
	.size	.L__unnamed_4, 51

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z41__device_stub__Atx_cone_mf_gpu_new_kernelPfS_S_ffS_S_ffffffiiiii
	.addrsig_sym _Z23__device_stub__set2zeroPfii
	.addrsig_sym _Z21__device_stub__scalexPfiif
	.addrsig_sym _Z40__device_stub__Ax_cone_mf_gpu_kernel_newPfS_S_ffS_S_ffffiiiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z26Atx_cone_mf_gpu_new_kernelPfS_S_ffS_S_ffffffiiiii
	.addrsig_sym _Z8set2zeroPfii
	.addrsig_sym _Z6scalexPfiif
	.addrsig_sym _Z25Ax_cone_mf_gpu_kernel_newPfS_S_ffS_S_ffffiiiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z26Atx_cone_mf_gpu_new_kernelPfS_S_ffS_S_ffffffiiiii ; -- Begin function _Z26Atx_cone_mf_gpu_new_kernelPfS_S_ffS_S_ffffffiiiii
	.globl	_Z26Atx_cone_mf_gpu_new_kernelPfS_S_ffS_S_ffffffiiiii
	.p2align	8
	.type	_Z26Atx_cone_mf_gpu_new_kernelPfS_S_ffS_S_ffffffiiiii,@function
_Z26Atx_cone_mf_gpu_new_kernelPfS_S_ffS_S_ffffffiiiii: ; @_Z26Atx_cone_mf_gpu_new_kernelPfS_S_ffS_S_ffffffiiiii
; %bb.0:
	s_load_b256 s[4:11], s[0:1], 0x3c
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v1, s14, 4, v1
	v_lshl_add_u32 v2, s15, 4, v0
	s_waitcnt lgkmcnt(0)
	s_mul_i32 s2, s9, s8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s7, v1
	v_cmp_gt_i32_e64 s2, s2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB0_133
; %bb.1:
	v_cvt_f32_i32_e32 v0, v2
	v_cvt_f32_i32_e32 v3, s8
	s_lshr_b32 s2, s8, 31
	s_lshr_b32 s3, s7, 31
	s_add_i32 s2, s8, s2
	s_add_i32 s3, s7, s3
	v_div_scale_f32 v4, null, v3, v3, v0
	v_div_scale_f32 v7, vcc_lo, v0, v3, v0
	s_ashr_i32 s2, s2, 1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v5, v4
	s_waitcnt_depctr 0xfff
	v_fma_f32 v6, -v4, v5, 1.0
	v_fmac_f32_e32 v5, v6, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v6, v7, v5
	v_fma_f32 v8, -v4, v6, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v6, v8, v5
	v_fma_f32 v4, -v4, v6, v7
	v_cvt_f64_i32_e32 v[7:8], s2
	s_ashr_i32 s2, s3, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f64_i32_e32 v[9:10], s2
	v_div_fmas_f32 v4, v4, v5, v6
	v_cvt_f64_i32_e32 v[5:6], v1
	s_lshr_b32 s2, s9, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_add_i32 s2, s9, s2
	v_div_fixup_f32 v0, v4, v3, v0
	s_ashr_i32 s2, s2, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_floor_f32_e32 v0, v0
	v_cvt_i32_f32_e32 v0, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v3, v0, s8
	v_cvt_f64_i32_e32 v[11:12], v0
	s_clause 0x1
	s_load_b64 s[8:9], s[0:1], 0x18
	s_load_b64 s[20:21], s[0:1], 0x30
	v_sub_nc_u32_e32 v3, v2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_f64_i32_e32 v[3:4], v3
	v_add_f64 v[5:6], v[5:6], 0.5
	v_add_f64 v[3:4], v[3:4], 0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_f64 v[5:6], v[5:6], -v[9:10]
	v_add_f64 v[9:10], v[11:12], 0.5
	v_add_f64 v[3:4], v[3:4], -v[7:8]
	v_cvt_f64_i32_e32 v[7:8], s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f32_f64_e32 v5, v[5:6]
	v_cvt_f32_f64_e32 v4, v[3:4]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_f64 v[7:8], v[9:10], -v[7:8]
	v_fma_f32 v3, s6, s6, 1.0
	v_mul_f32_e32 v9, 0.5, v3
	s_waitcnt lgkmcnt(0)
	v_add_f32_e64 v3, s20, s21
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v9
	v_mul_f32_e32 v0, s9, v4
	v_cvt_f32_f64_e32 v7, v[7:8]
	v_fmac_f32_e32 v0, s8, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v6, s20, v0
	v_mul_f32_e32 v0, 0x4f800000, v9
	v_mul_f32_e32 v10, s5, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v0, v9, v0, vcc_lo
	v_div_scale_f32 v9, null, v10, v10, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v11, v0
	v_div_scale_f32 v17, s2, v3, v10, v3
	v_rcp_f32_e32 v12, v9
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v13, -1, v11
	v_add_nc_u32_e32 v8, 1, v11
	v_fma_f32 v14, -v9, v12, 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v15, -v13, v11, v0
	v_fma_f32 v16, -v8, v11, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v12, v14, v12
	v_cmp_ge_f32_e64 s3, 0, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v11, v11, v13, s3
	v_cmp_lt_f32_e64 s3, 0, v16
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v13, v17, v12
	v_cndmask_b32_e64 v8, v11, v8, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_fma_f32 v11, -v9, v13, v17
	s_lshr_b32 s3, s11, 31
	s_add_i32 s3, s11, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v14, 0x37800000, v8
	v_dual_fmac_f32 v13, v11, v12 :: v_dual_cndmask_b32 v8, v8, v14
	v_cmp_class_f32_e64 vcc_lo, v0, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v9, -v9, v13, v17
	v_cndmask_b32_e32 v0, v8, v0, vcc_lo
	s_mov_b32 vcc_lo, s2
	s_ashr_i32 s2, s3, 1
	s_delay_alu instid0(VALU_DEP_2)
	v_div_fmas_f32 v8, v9, v12, v13
	v_cvt_f32_i32_e32 v9, s2
	v_fma_f32 v11, s6, v7, v0
	v_fma_f32 v0, v7, s6, -v0
	s_add_i32 s2, s11, -1
	v_div_fixup_f32 v8, v8, v10, v3
	s_mov_b32 s11, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v10, v11, v8, v9
	v_fmac_f32_e32 v9, v0, v8
	v_floor_f32_e32 v8, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_floor_f32_e32 v0, v9
	v_cvt_i32_f32_e32 v8, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f32_e32 v0, v0
	v_min_i32_e32 v22, s2, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_max_i32_e32 v0, 0, v0
	v_cmp_le_i32_e32 vcc_lo, v0, v22
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_133
; %bb.2:                                ; %.lr.ph133
	v_mul_f32_e32 v8, s4, v6
	s_clause 0x2
	s_load_b128 s[12:15], s[0:1], 0x0
	s_load_b64 s[2:3], s[0:1], 0x10
	s_load_b128 s[16:19], s[0:1], 0x20
	s_lshr_b32 s0, s10, 31
	v_fma_f32 v28, -s20, s8, -v5
	s_add_i32 s0, s10, s0
	v_div_scale_f32 v9, null, v8, v8, v3
	v_div_scale_f32 v11, vcc_lo, v3, v8, v3
	v_mul_f32_e32 v12, s6, v7
	s_delay_alu instid0(VALU_DEP_3)
	v_rcp_f32_e32 v10, v9
	s_ashr_i32 s0, s0, 1
	v_fma_f32 v29, -s20, s9, -v4
	v_mul_f32_e64 v27, s6, 0.5
	s_add_i32 s4, s10, -1
	v_mul_lo_u32 v30, s10, v0
	v_mul_f32_e64 v23, -s20, s8
	v_mul_f32_e64 v24, -s20, s9
	v_mul_f32_e64 v25, s8, s21
	v_mul_f32_e64 v26, s9, s21
	v_fma_f32 v6, -v9, v10, 1.0
	v_xor_b32_e32 v32, 0x80000000, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v31, 0, v12 :: v_dual_fmac_f32 v10, v6, v10
	v_mad_u64_u32 v[6:7], null, v2, s7, v[1:2]
	v_mul_f32_e32 v13, v11, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v1, -v9, v13, v11
	v_dual_mul_f32 v14, s9, v5 :: v_dual_fmac_f32 v13, v1, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_fma_f32 v2, v4, s8, -v14
	v_cvt_f32_i32_e32 v4, s0
	v_cmp_gt_f32_e64 s0, -v12, 0
	v_fma_f32 v1, -v9, v13, v11
	v_mov_b32_e32 v11, 0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v1, v1, v10, v13
	v_cmp_lt_f32_e32 vcc_lo, 0, v29
	v_div_fixup_f32 v7, v1, v8, v3
	v_add_f32_e32 v5, -1.0, v2
	v_dual_mov_b32 v1, 0 :: v_dual_add_f32 v2, 1.0, v2
	v_cndmask_b32_e64 v8, -v29, v29, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v5, v5, v7, v4
	v_dual_mov_b32 v3, v1 :: v_dual_fmac_f32 v4, v2, v7
	v_ashrrev_i32_e32 v7, 31, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_floor_f32_e32 v2, v5
	v_cndmask_b32_e64 v5, -v31, v31, s0
	v_floor_f32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_4)
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_cmp_ge_f32_e64 s0, 0.5, v8
	v_cvt_i32_f32_e32 v2, v2
	v_cmp_le_f32_e64 s1, v5, v27
	v_cvt_i32_f32_e32 v8, v4
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s12, v6
	v_max_i32_e32 v2, 0, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_min_i32_e32 v33, s4, v8
	v_add_co_ci_u32_e32 v5, vcc_lo, s13, v7, vcc_lo
	v_add_co_u32 v6, vcc_lo, s2, v6
	v_lshlrev_b64 v[8:9], 2, v[2:3]
	v_add_co_ci_u32_e32 v7, vcc_lo, s3, v7, vcc_lo
	v_cmp_le_i32_e64 s2, v2, v33
	s_mov_b32 s12, -0.5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v8, vcc_lo, s16, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s17, v9, vcc_lo
.LBB0_3:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_5 Depth 2
	s_delay_alu instid0(VALU_DEP_3)
	s_and_saveexec_b32 s7, s2
	s_cbranch_execz .LBB0_132
; %bb.4:                                ; %.lr.ph
                                        ;   in Loop: Header=BB0_3 Depth=1
	v_lshlrev_b64 v[14:15], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v13, v9 :: v_dual_mov_b32 v12, v8
	v_mov_b32_e32 v3, v2
	s_mov_b32 s13, 0
	v_add_co_u32 v14, vcc_lo, s18, v14
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v15, vcc_lo, s19, v15, vcc_lo
.LBB0_5:                                ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	global_load_b32 v10, v[12:13], off
	global_load_b32 v34, v[14:15], off
	s_mov_b32 s4, exec_lo
	s_waitcnt vmcnt(1)
	v_fma_f32 v16, -v10, s9, v25
	v_fma_f32 v10, s8, v10, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v36, v16, v23 :: v_dual_sub_f32 v35, v10, v24
                                        ; implicit-def: $vgpr10
	v_cmp_neq_f32_e64 s3, 0, v35
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_neq_f32_e32 0, v36
	s_xor_b32 s16, exec_lo, s4
	s_cbranch_execz .LBB0_101
; %bb.6:                                ;   in Loop: Header=BB0_5 Depth=2
                                        ; implicit-def: $vgpr10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_saveexec_b32 s4, s3
	s_xor_b32 s5, exec_lo, s4
	s_cbranch_execz .LBB0_76
; %bb.7:                                ;   in Loop: Header=BB0_5 Depth=2
	v_cmp_lt_f32_e32 vcc_lo, 0, v36
                                        ; implicit-def: $vgpr37
                                        ; implicit-def: $vgpr18_vgpr19
                                        ; implicit-def: $vgpr20_vgpr21
	v_cndmask_b32_e64 v10, -v36, v36, vcc_lo
	v_cmp_lt_f32_e32 vcc_lo, 0, v35
	v_cndmask_b32_e64 v16, -v35, v35, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ngt_f32_e32 vcc_lo, v10, v16
                                        ; implicit-def: $vgpr16_vgpr17
	s_and_saveexec_b32 s4, vcc_lo
	s_xor_b32 s17, exec_lo, s4
	s_cbranch_execz .LBB0_41
; %bb.8:                                ;   in Loop: Header=BB0_5 Depth=2
	v_div_scale_f32 v10, null, v35, v35, v36
	s_waitcnt vmcnt(0)
	v_div_scale_f32 v17, null, v35, v35, v34
	v_div_scale_f32 v20, vcc_lo, v36, v35, v36
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v16, v10
	v_rcp_f32_e32 v19, v17
	v_div_scale_f32 v38, s4, v34, v35, v34
	s_waitcnt_depctr 0xfff
	v_fma_f32 v18, -v10, v16, 1.0
	v_fma_f32 v21, -v17, v19, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v16, v18, v16 :: v_dual_fmac_f32 v19, v21, v19
	v_mul_f32_e32 v18, v20, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v37, -v10, v18, v20
	v_dual_fmac_f32 v18, v37, v16 :: v_dual_mul_f32 v37, v38, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v10, -v10, v18, v20
	v_fma_f32 v20, -v17, v37, v38
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v37, v20, v19
	v_div_fmas_f32 v10, v10, v16, v18
	s_mov_b32 vcc_lo, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v20, v10, v35, v36
	v_fma_f32 v10, -v17, v37, v38
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v21, -v29, v20, v28
	v_div_fmas_f32 v10, v10, v19, v37
	v_mov_b32_e32 v37, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v18, -0.5, v20, v21
	v_div_fixup_f32 v16, v10, v35, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_f32_e32 vcc_lo, 0, v18
	v_fma_f32 v10, -v29, v16, v31
	v_mul_f32_e32 v38, 0.5, v16
	v_cndmask_b32_e64 v17, -v18, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ge_f32_e32 vcc_lo, 0.5, v17
                                        ; implicit-def: $vgpr16_vgpr17
	s_and_saveexec_b32 s4, vcc_lo
	s_cbranch_execz .LBB0_12
; %bb.9:                                ;   in Loop: Header=BB0_5 Depth=2
	v_dual_sub_f32 v16, v10, v38 :: v_dual_mov_b32 v37, 0
	s_mov_b32 s20, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e32 vcc_lo, 0, v16
	v_cndmask_b32_e64 v17, -v16, v16, vcc_lo
	v_cmpx_le_f32_e32 v17, v27
; %bb.10:                               ;   in Loop: Header=BB0_5 Depth=2
	v_mov_b32_e32 v37, 1
; %bb.11:                               ; %Flow196
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s20
.LBB0_12:                               ;   in Loop: Header=BB0_5 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s4
	v_mul_f32_e32 v20, 0.5, v20
	v_add_f32_e32 v39, v20, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e32 vcc_lo, 0, v39
	v_cndmask_b32_e64 v20, -v39, v39, vcc_lo
	v_cmp_ge_f32_e32 vcc_lo, 0.5, v20
	v_dual_mov_b32 v21, s13 :: v_dual_mov_b32 v20, s12
	s_and_saveexec_b32 s20, vcc_lo
	s_cbranch_execz .LBB0_16
; %bb.13:                               ;   in Loop: Header=BB0_5 Depth=2
	v_dual_add_f32 v38, v38, v10 :: v_dual_mov_b32 v21, s13
	v_mov_b32_e32 v20, s12
	s_mov_b32 s21, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e32 vcc_lo, 0, v38
	v_cndmask_b32_e64 v10, -v38, v38, vcc_lo
	v_cmpx_le_f32_e32 v10, v27
; %bb.14:                               ;   in Loop: Header=BB0_5 Depth=2
	v_cmp_eq_u32_e32 vcc_lo, 0, v37
	v_cmp_ne_u32_e64 s4, 0, v37
	v_add_nc_u32_e32 v37, 1, v37
	v_cndmask_b32_e64 v10, -0.5, 0.5, vcc_lo
	v_dual_cndmask_b32 v16, v16, v38 :: v_dual_mov_b32 v21, v11
	v_cndmask_b32_e32 v18, v18, v39, vcc_lo
	v_cndmask_b32_e64 v19, v19, v39, s4
	v_cndmask_b32_e64 v17, v17, v38, s4
	v_mov_b32_e32 v20, v10
; %bb.15:                               ; %Flow195
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s21
.LBB0_16:                               ;   in Loop: Header=BB0_5 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s20
	v_mov_b32_e32 v10, 2
	s_mov_b32 s20, exec_lo
	v_cmpx_gt_u32_e32 2, v37
	s_cbranch_execz .LBB0_28
; %bb.17:                               ;   in Loop: Header=BB0_5 Depth=2
	v_div_scale_f32 v10, null, v36, v36, v35
	v_div_scale_f32 v39, null, v36, v36, v34
	v_div_scale_f32 v41, vcc_lo, v35, v36, v35
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v38, v10
	v_rcp_f32_e32 v42, v39
	v_div_scale_f32 v45, s4, v34, v36, v34
	s_mov_b32 s21, exec_lo
	s_waitcnt_depctr 0xfff
	v_fma_f32 v40, -v10, v38, 1.0
	v_fma_f32 v43, -v39, v42, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v38, v40, v38
	v_fmac_f32_e32 v42, v43, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v40, v41, v38
	v_mul_f32_e32 v43, v45, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v44, -v10, v40, v41
	v_fmac_f32_e32 v40, v44, v38
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v10, -v10, v40, v41
	v_fma_f32 v41, -v39, v43, v45
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v10, v10, v38, v40
	v_fmac_f32_e32 v43, v41, v42
	s_mov_b32 vcc_lo, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v40, v10, v36, v35
	v_fma_f32 v10, -v39, v43, v45
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v41, -v28, v40, v29
	v_div_fmas_f32 v38, v10, v42, v43
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v10, -0.5, v40, v41
	v_div_fixup_f32 v39, v38, v36, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_f32_e32 vcc_lo, 0, v10
	v_fma_f32 v38, -v28, v39, v31
	v_mul_f32_e32 v39, 0.5, v39
	v_cndmask_b32_e64 v42, -v10, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ge_f32_e32 0.5, v42
	s_cbranch_execz .LBB0_21
; %bb.18:                               ;   in Loop: Header=BB0_5 Depth=2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v42, v38, v39
	s_mov_b32 s22, exec_lo
	v_cmp_lt_f32_e32 vcc_lo, 0, v42
	v_cndmask_b32_e64 v43, -v42, v42, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_le_f32_e32 v43, v27
; %bb.19:                               ;   in Loop: Header=BB0_5 Depth=2
	v_cmp_eq_u32_e32 vcc_lo, 1, v37
	v_cmp_eq_u32_e64 s4, 0, v37
	v_add_nc_u32_e32 v37, 1, v37
	v_cndmask_b32_e64 v19, v19, -0.5, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e64 v18, v18, -0.5, s4
	v_cndmask_b32_e32 v21, v21, v10, vcc_lo
	v_cndmask_b32_e64 v20, v20, v10, s4
	v_cndmask_b32_e32 v17, v17, v42, vcc_lo
	v_cndmask_b32_e64 v16, v16, v42, s4
; %bb.20:                               ; %Flow193
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s22
.LBB0_21:                               ;   in Loop: Header=BB0_5 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s21
	v_mov_b32_e32 v10, 2
	s_mov_b32 s21, exec_lo
	v_cmpx_gt_u32_e32 2, v37
	s_cbranch_execz .LBB0_27
; %bb.22:                               ;   in Loop: Header=BB0_5 Depth=2
	v_mul_f32_e32 v10, 0.5, v40
	s_mov_b32 s22, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v10, v10, v41
	v_cmp_lt_f32_e32 vcc_lo, 0, v10
	v_cndmask_b32_e64 v40, -v10, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ge_f32_e32 0.5, v40
	s_cbranch_execz .LBB0_26
; %bb.23:                               ;   in Loop: Header=BB0_5 Depth=2
	v_add_f32_e32 v38, v39, v38
	s_mov_b32 s23, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e32 vcc_lo, 0, v38
	v_cndmask_b32_e64 v39, -v38, v38, vcc_lo
	v_cmpx_le_f32_e32 v39, v27
; %bb.24:                               ;   in Loop: Header=BB0_5 Depth=2
	v_cmp_eq_u32_e32 vcc_lo, 1, v37
	v_cmp_eq_u32_e64 s4, 0, v37
	v_add_nc_u32_e32 v37, 1, v37
	v_cndmask_b32_e64 v19, v19, 0.5, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e64 v18, v18, 0.5, s4
	v_cndmask_b32_e32 v21, v21, v10, vcc_lo
	v_cndmask_b32_e64 v20, v20, v10, s4
	v_cndmask_b32_e32 v17, v17, v38, vcc_lo
	v_cndmask_b32_e64 v16, v16, v38, s4
; %bb.25:                               ; %Flow190
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s23
.LBB0_26:                               ; %Flow191
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s22
	v_mov_b32_e32 v10, v37
.LBB0_27:                               ; %Flow192
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s21
.LBB0_28:                               ; %Flow194
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s20
	v_mov_b32_e32 v37, 2
	s_mov_b32 s20, exec_lo
	v_cmpx_gt_u32_e32 2, v10
	s_cbranch_execz .LBB0_40
; %bb.29:                               ;   in Loop: Header=BB0_5 Depth=2
	v_div_scale_f32 v37, null, v34, v34, v36
	v_div_scale_f32 v39, null, v34, v34, v35
	v_div_scale_f32 v42, vcc_lo, v36, v34, v36
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v38, v37
	v_rcp_f32_e32 v41, v39
	v_div_scale_f32 v45, s4, v35, v34, v35
	s_mov_b32 s21, exec_lo
	s_waitcnt_depctr 0xfff
	v_fma_f32 v40, -v37, v38, 1.0
	v_fma_f32 v43, -v39, v41, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v38, v40, v38 :: v_dual_fmac_f32 v41, v43, v41
	v_dual_mul_f32 v40, v42, v38 :: v_dual_mul_f32 v43, v45, v41
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v44, -v37, v40, v42
	v_fmac_f32_e32 v40, v44, v38
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v37, -v37, v40, v42
	v_fma_f32 v42, -v39, v43, v45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v43, v42, v41
	v_div_fmas_f32 v37, v37, v38, v40
	s_mov_b32 vcc_lo, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v36, v37, v34, v36
	v_fma_f32 v37, -v39, v43, v45
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v38, -v31, v36, v28
	v_div_fmas_f32 v39, v37, v41, v43
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v37, -v27, v36, v38
	v_div_fixup_f32 v35, v39, v34, v35
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_f32_e32 vcc_lo, 0, v37
	v_fma_f32 v34, -v31, v35, v29
	v_mul_f32_e32 v35, v27, v35
	v_cndmask_b32_e64 v39, -v37, v37, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ge_f32_e32 0.5, v39
	s_cbranch_execz .LBB0_33
; %bb.30:                               ;   in Loop: Header=BB0_5 Depth=2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v39, v34, v35
	s_mov_b32 s22, exec_lo
	v_cmp_lt_f32_e32 vcc_lo, 0, v39
	v_cndmask_b32_e64 v40, -v39, v39, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ge_f32_e32 0.5, v40
; %bb.31:                               ;   in Loop: Header=BB0_5 Depth=2
	v_cmp_eq_u32_e32 vcc_lo, 1, v10
	v_cmp_eq_u32_e64 s4, 0, v10
	v_dual_cndmask_b32 v19, v19, v37 :: v_dual_add_nc_u32 v10, 1, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e64 v18, v18, v37, s4
	v_cndmask_b32_e32 v21, v21, v39, vcc_lo
	v_cndmask_b32_e64 v20, v20, v39, s4
	v_cndmask_b32_e64 v17, v17, -v27, vcc_lo
	v_cndmask_b32_e64 v16, v16, -v27, s4
; %bb.32:                               ; %Flow188
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s22
.LBB0_33:                               ;   in Loop: Header=BB0_5 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s21
	v_mov_b32_e32 v37, 2
	s_mov_b32 s21, exec_lo
	v_cmpx_gt_u32_e32 2, v10
	s_cbranch_execz .LBB0_39
; %bb.34:                               ;   in Loop: Header=BB0_5 Depth=2
	v_mul_f32_e32 v36, v27, v36
	s_mov_b32 s22, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v36, v36, v38
	v_cmp_lt_f32_e32 vcc_lo, 0, v36
	v_cndmask_b32_e64 v37, -v36, v36, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ge_f32_e32 0.5, v37
	s_cbranch_execz .LBB0_38
; %bb.35:                               ;   in Loop: Header=BB0_5 Depth=2
	v_add_f32_e32 v34, v35, v34
	s_mov_b32 s23, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e32 vcc_lo, 0, v34
	v_cndmask_b32_e64 v35, -v34, v34, vcc_lo
	v_cmpx_ge_f32_e32 0.5, v35
; %bb.36:                               ;   in Loop: Header=BB0_5 Depth=2
	v_cmp_eq_u32_e32 vcc_lo, 1, v10
	v_cmp_eq_u32_e64 s4, 0, v10
	v_dual_cndmask_b32 v19, v19, v36 :: v_dual_add_nc_u32 v10, 1, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e64 v18, v18, v36, s4
	v_cndmask_b32_e32 v21, v21, v34, vcc_lo
	v_cndmask_b32_e64 v20, v20, v34, s4
	v_cndmask_b32_e32 v17, v17, v27, vcc_lo
	v_cndmask_b32_e64 v16, v16, v27, s4
; %bb.37:                               ; %Flow
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s23
.LBB0_38:                               ; %Flow186
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s22
	v_mov_b32_e32 v37, v10
.LBB0_39:                               ; %Flow187
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s21
.LBB0_40:                               ; %Flow189
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s20
                                        ; implicit-def: $vgpr34
                                        ; implicit-def: $vgpr36
                                        ; implicit-def: $vgpr35
.LBB0_41:                               ; %Flow209
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_and_not1_saveexec_b32 s17, s17
	s_cbranch_execz .LBB0_75
; %bb.42:                               ;   in Loop: Header=BB0_5 Depth=2
	v_div_scale_f32 v10, null, v36, v36, v35
	s_waitcnt vmcnt(0)
	v_div_scale_f32 v17, null, v36, v36, v34
	v_div_scale_f32 v19, vcc_lo, v35, v36, v35
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v16, v10
	v_rcp_f32_e32 v20, v17
	v_div_scale_f32 v38, s4, v34, v36, v34
	s_waitcnt_depctr 0xfff
	v_fma_f32 v18, -v10, v16, 1.0
	v_fma_f32 v21, -v17, v20, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v16, v18, v16
	v_fmac_f32_e32 v20, v21, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v18, v19, v16
	v_mul_f32_e32 v21, v38, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v37, -v10, v18, v19
	v_dual_fmac_f32 v18, v37, v16 :: v_dual_mov_b32 v37, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v10, -v10, v18, v19
	v_fma_f32 v19, -v17, v21, v38
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v10, v10, v16, v18
	v_fmac_f32_e32 v21, v19, v20
	s_mov_b32 vcc_lo, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v18, v10, v36, v35
	v_fma_f32 v10, -v17, v21, v38
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v19, -v28, v18, v29
	v_div_fmas_f32 v10, v10, v20, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v20, -0.5, v18, v19
	v_div_fixup_f32 v16, v10, v36, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_f32_e32 vcc_lo, 0, v20
	v_fma_f32 v10, -v28, v16, v31
	v_mul_f32_e32 v38, 0.5, v16
	v_cndmask_b32_e64 v17, -v20, v20, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ge_f32_e32 vcc_lo, 0.5, v17
                                        ; implicit-def: $vgpr16_vgpr17
	s_and_saveexec_b32 s4, vcc_lo
	s_cbranch_execz .LBB0_46
; %bb.43:                               ;   in Loop: Header=BB0_5 Depth=2
	v_dual_sub_f32 v16, v10, v38 :: v_dual_mov_b32 v37, 0
	s_mov_b32 s20, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e32 vcc_lo, 0, v16
	v_cndmask_b32_e64 v17, -v16, v16, vcc_lo
	v_cmpx_le_f32_e32 v17, v27
; %bb.44:                               ;   in Loop: Header=BB0_5 Depth=2
	v_mov_b32_e32 v37, 1
; %bb.45:                               ; %Flow208
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s20
.LBB0_46:                               ;   in Loop: Header=BB0_5 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s4
	v_mul_f32_e32 v18, 0.5, v18
	v_add_f32_e32 v39, v18, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e32 vcc_lo, 0, v39
	v_cndmask_b32_e64 v18, -v39, v39, vcc_lo
	v_cmp_ge_f32_e32 vcc_lo, 0.5, v18
	v_dual_mov_b32 v19, s13 :: v_dual_mov_b32 v18, s12
	s_and_saveexec_b32 s20, vcc_lo
	s_cbranch_execz .LBB0_50
; %bb.47:                               ;   in Loop: Header=BB0_5 Depth=2
	v_dual_add_f32 v38, v38, v10 :: v_dual_mov_b32 v19, s13
	v_mov_b32_e32 v18, s12
	s_mov_b32 s21, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e32 vcc_lo, 0, v38
	v_cndmask_b32_e64 v10, -v38, v38, vcc_lo
	v_cmpx_le_f32_e32 v10, v27
; %bb.48:                               ;   in Loop: Header=BB0_5 Depth=2
	v_cmp_eq_u32_e32 vcc_lo, 0, v37
	v_cmp_ne_u32_e64 s4, 0, v37
	v_add_nc_u32_e32 v37, 1, v37
	v_cndmask_b32_e64 v10, -0.5, 0.5, vcc_lo
	v_dual_cndmask_b32 v16, v16, v38 :: v_dual_mov_b32 v19, v11
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v21, v21, v39, s4
	v_cndmask_b32_e32 v20, v20, v39, vcc_lo
	v_cndmask_b32_e64 v17, v17, v38, s4
	v_mov_b32_e32 v18, v10
; %bb.49:                               ; %Flow207
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s21
.LBB0_50:                               ;   in Loop: Header=BB0_5 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s20
	v_mov_b32_e32 v10, 2
	s_mov_b32 s20, exec_lo
	v_cmpx_gt_u32_e32 2, v37
	s_cbranch_execz .LBB0_62
; %bb.51:                               ;   in Loop: Header=BB0_5 Depth=2
	v_div_scale_f32 v10, null, v35, v35, v36
	v_div_scale_f32 v39, null, v35, v35, v34
	v_div_scale_f32 v41, vcc_lo, v36, v35, v36
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v38, v10
	v_rcp_f32_e32 v42, v39
	v_div_scale_f32 v45, s4, v34, v35, v34
	s_mov_b32 s21, exec_lo
	s_waitcnt_depctr 0xfff
	v_fma_f32 v40, -v10, v38, 1.0
	v_fma_f32 v43, -v39, v42, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v38, v40, v38
	v_fmac_f32_e32 v42, v43, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v40, v41, v38
	v_mul_f32_e32 v43, v45, v42
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v44, -v10, v40, v41
	v_fmac_f32_e32 v40, v44, v38
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v10, -v10, v40, v41
	v_fma_f32 v41, -v39, v43, v45
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v10, v10, v38, v40
	v_fmac_f32_e32 v43, v41, v42
	s_mov_b32 vcc_lo, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v40, v10, v35, v36
	v_fma_f32 v10, -v39, v43, v45
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v41, -v29, v40, v28
	v_div_fmas_f32 v38, v10, v42, v43
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v10, -0.5, v40, v41
	v_div_fixup_f32 v39, v38, v35, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_f32_e32 vcc_lo, 0, v10
	v_fma_f32 v38, -v29, v39, v31
	v_mul_f32_e32 v39, 0.5, v39
	v_cndmask_b32_e64 v42, -v10, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ge_f32_e32 0.5, v42
	s_cbranch_execz .LBB0_55
; %bb.52:                               ;   in Loop: Header=BB0_5 Depth=2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v42, v38, v39
	s_mov_b32 s22, exec_lo
	v_cmp_lt_f32_e32 vcc_lo, 0, v42
	v_cndmask_b32_e64 v43, -v42, v42, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_le_f32_e32 v43, v27
; %bb.53:                               ;   in Loop: Header=BB0_5 Depth=2
	v_cmp_eq_u32_e32 vcc_lo, 1, v37
	v_cmp_eq_u32_e64 s4, 0, v37
	v_add_nc_u32_e32 v37, 1, v37
	v_cndmask_b32_e32 v19, v19, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e64 v18, v18, v10, s4
	v_cndmask_b32_e64 v21, v21, -0.5, vcc_lo
	v_cndmask_b32_e64 v20, v20, -0.5, s4
	v_cndmask_b32_e32 v17, v17, v42, vcc_lo
	v_cndmask_b32_e64 v16, v16, v42, s4
; %bb.54:                               ; %Flow205
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s22
.LBB0_55:                               ;   in Loop: Header=BB0_5 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s21
	v_mov_b32_e32 v10, 2
	s_mov_b32 s21, exec_lo
	v_cmpx_gt_u32_e32 2, v37
	s_cbranch_execz .LBB0_61
; %bb.56:                               ;   in Loop: Header=BB0_5 Depth=2
	v_mul_f32_e32 v10, 0.5, v40
	s_mov_b32 s22, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v10, v10, v41
	v_cmp_lt_f32_e32 vcc_lo, 0, v10
	v_cndmask_b32_e64 v40, -v10, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ge_f32_e32 0.5, v40
	s_cbranch_execz .LBB0_60
; %bb.57:                               ;   in Loop: Header=BB0_5 Depth=2
	v_add_f32_e32 v38, v39, v38
	s_mov_b32 s23, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e32 vcc_lo, 0, v38
	v_cndmask_b32_e64 v39, -v38, v38, vcc_lo
	v_cmpx_le_f32_e32 v39, v27
; %bb.58:                               ;   in Loop: Header=BB0_5 Depth=2
	v_cmp_eq_u32_e32 vcc_lo, 1, v37
	v_cmp_eq_u32_e64 s4, 0, v37
	v_add_nc_u32_e32 v37, 1, v37
	v_cndmask_b32_e32 v19, v19, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e64 v18, v18, v10, s4
	v_cndmask_b32_e64 v21, v21, 0.5, vcc_lo
	v_cndmask_b32_e64 v20, v20, 0.5, s4
	v_cndmask_b32_e32 v17, v17, v38, vcc_lo
	v_cndmask_b32_e64 v16, v16, v38, s4
; %bb.59:                               ; %Flow202
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s23
.LBB0_60:                               ; %Flow203
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s22
	v_mov_b32_e32 v10, v37
.LBB0_61:                               ; %Flow204
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s21
.LBB0_62:                               ; %Flow206
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s20
	v_mov_b32_e32 v37, 2
	s_mov_b32 s20, exec_lo
	v_cmpx_gt_u32_e32 2, v10
	s_cbranch_execz .LBB0_74
; %bb.63:                               ;   in Loop: Header=BB0_5 Depth=2
	v_div_scale_f32 v37, null, v34, v34, v36
	v_div_scale_f32 v39, null, v34, v34, v35
	v_div_scale_f32 v42, vcc_lo, v36, v34, v36
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v38, v37
	v_rcp_f32_e32 v41, v39
	v_div_scale_f32 v45, s4, v35, v34, v35
	s_mov_b32 s21, exec_lo
	s_waitcnt_depctr 0xfff
	v_fma_f32 v40, -v37, v38, 1.0
	v_fma_f32 v43, -v39, v41, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v38, v40, v38 :: v_dual_fmac_f32 v41, v43, v41
	v_dual_mul_f32 v40, v42, v38 :: v_dual_mul_f32 v43, v45, v41
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v44, -v37, v40, v42
	v_fmac_f32_e32 v40, v44, v38
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v37, -v37, v40, v42
	v_fma_f32 v42, -v39, v43, v45
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v43, v42, v41
	v_div_fmas_f32 v37, v37, v38, v40
	s_mov_b32 vcc_lo, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v36, v37, v34, v36
	v_fma_f32 v37, -v39, v43, v45
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v38, -v31, v36, v28
	v_div_fmas_f32 v39, v37, v41, v43
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v37, -v27, v36, v38
	v_div_fixup_f32 v35, v39, v34, v35
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_f32_e32 vcc_lo, 0, v37
	v_fma_f32 v34, -v31, v35, v29
	v_mul_f32_e32 v35, v27, v35
	v_cndmask_b32_e64 v39, -v37, v37, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ge_f32_e32 0.5, v39
	s_cbranch_execz .LBB0_67
; %bb.64:                               ;   in Loop: Header=BB0_5 Depth=2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v39, v34, v35
	s_mov_b32 s22, exec_lo
	v_cmp_lt_f32_e32 vcc_lo, 0, v39
	v_cndmask_b32_e64 v40, -v39, v39, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ge_f32_e32 0.5, v40
; %bb.65:                               ;   in Loop: Header=BB0_5 Depth=2
	v_cmp_eq_u32_e32 vcc_lo, 1, v10
	v_cmp_eq_u32_e64 s4, 0, v10
	v_dual_cndmask_b32 v19, v19, v37 :: v_dual_add_nc_u32 v10, 1, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e64 v18, v18, v37, s4
	v_cndmask_b32_e32 v21, v21, v39, vcc_lo
	v_cndmask_b32_e64 v20, v20, v39, s4
	v_cndmask_b32_e64 v17, v17, -v27, vcc_lo
	v_cndmask_b32_e64 v16, v16, -v27, s4
; %bb.66:                               ; %Flow200
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s22
.LBB0_67:                               ;   in Loop: Header=BB0_5 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s21
	v_mov_b32_e32 v37, 2
	s_mov_b32 s21, exec_lo
	v_cmpx_gt_u32_e32 2, v10
	s_cbranch_execz .LBB0_73
; %bb.68:                               ;   in Loop: Header=BB0_5 Depth=2
	v_mul_f32_e32 v36, v27, v36
	s_mov_b32 s22, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v36, v36, v38
	v_cmp_lt_f32_e32 vcc_lo, 0, v36
	v_cndmask_b32_e64 v37, -v36, v36, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ge_f32_e32 0.5, v37
	s_cbranch_execz .LBB0_72
; %bb.69:                               ;   in Loop: Header=BB0_5 Depth=2
	v_add_f32_e32 v34, v35, v34
	s_mov_b32 s23, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e32 vcc_lo, 0, v34
	v_cndmask_b32_e64 v35, -v34, v34, vcc_lo
	v_cmpx_ge_f32_e32 0.5, v35
; %bb.70:                               ;   in Loop: Header=BB0_5 Depth=2
	v_cmp_eq_u32_e32 vcc_lo, 1, v10
	v_cmp_eq_u32_e64 s4, 0, v10
	v_dual_cndmask_b32 v19, v19, v36 :: v_dual_add_nc_u32 v10, 1, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e64 v18, v18, v36, s4
	v_cndmask_b32_e32 v21, v21, v34, vcc_lo
	v_cndmask_b32_e64 v20, v20, v34, s4
	v_cndmask_b32_e32 v17, v17, v27, vcc_lo
	v_cndmask_b32_e64 v16, v16, v27, s4
; %bb.71:                               ; %Flow197
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s23
.LBB0_72:                               ; %Flow198
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s22
	v_mov_b32_e32 v37, v10
.LBB0_73:                               ; %Flow199
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s21
.LBB0_74:                               ; %Flow201
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s20
.LBB0_75:                               ; %Flow210
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	s_or_b32 exec_lo, exec_lo, s17
	v_sub_f32_e32 v10, v19, v18
	v_sub_f32_e32 v18, v21, v20
	v_sub_f32_e32 v16, v17, v16
                                        ; implicit-def: $vgpr34
                                        ; implicit-def: $vgpr36
	v_mul_f32_e32 v10, v10, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v10, v18, v18
	v_fmac_f32_e32 v10, v16, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v16, 0x4f800000, v10
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v10
	v_cndmask_b32_e32 v10, v10, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v16, v10
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v17, -1, v16
	v_add_nc_u32_e32 v18, 1, v16
	v_fma_f32 v19, -v17, v16, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v20, -v18, v16, v10
	v_cmp_ge_f32_e64 s4, 0, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v16, v16, v17, s4
	v_cmp_lt_f32_e64 s4, 0, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v16, v16, v18, s4
	v_mul_f32_e32 v17, 0x37800000, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v16, v16, v17, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v10, 0x260
	v_cndmask_b32_e32 v10, v16, v10, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 2, v37
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v10, 0, v10, vcc_lo
.LBB0_76:                               ; %Flow223
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_and_not1_saveexec_b32 s17, s5
	s_cbranch_execz .LBB0_100
; %bb.77:                               ;   in Loop: Header=BB0_5 Depth=2
                                        ; implicit-def: $vgpr10
	s_mov_b32 s4, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_neq_f32_e32 0, v34
	s_xor_b32 s20, exec_lo, s4
	s_cbranch_execz .LBB0_95
; %bb.78:                               ;   in Loop: Header=BB0_5 Depth=2
	v_cmp_lt_f32_e32 vcc_lo, 0, v36
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr18_vgpr19
	v_cndmask_b32_e64 v10, -v36, v36, vcc_lo
	v_cmp_lt_f32_e32 vcc_lo, 0, v34
	v_cndmask_b32_e64 v16, -v34, v34, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ngt_f32_e32 vcc_lo, v10, v16
                                        ; implicit-def: $vgpr16_vgpr17
	s_and_saveexec_b32 s4, vcc_lo
	s_xor_b32 s5, exec_lo, s4
	s_cbranch_execz .LBB0_86
; %bb.79:                               ;   in Loop: Header=BB0_5 Depth=2
	v_div_scale_f32 v10, null, v34, v34, v36
	v_div_scale_f32 v18, vcc_lo, v36, v34, v36
	s_mov_b32 s21, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v16, v10
	s_waitcnt_depctr 0xfff
	v_fma_f32 v17, -v10, v16, 1.0
	v_fmac_f32_e32 v16, v17, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v17, v18, v16
	v_fma_f32 v19, -v10, v17, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v17, v19, v16
	v_fma_f32 v10, -v10, v17, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v10, v10, v16, v17
	v_div_fixup_f32 v10, v10, v34, v36
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v19, -v31, v10, v28
	v_fma_f32 v18, -v27, v10, v19
	v_fmac_f32_e32 v19, v27, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_f32_e32 vcc_lo, 0, v18
	v_cmp_lt_f32_e64 s4, 0, v19
	v_cndmask_b32_e64 v16, -v18, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v10, -v19, v19, s4
	v_cmp_ge_f32_e32 vcc_lo, 0.5, v16
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_nge_f32_e64 s4, 0.5, v10
	v_cndmask_b32_e64 v16, 0, 1, vcc_lo
	v_cndmask_b32_e32 v17, s0, v27, vcc_lo
	v_cndmask_b32_e64 v20, 1, 2, vcc_lo
	v_cndmask_b32_e32 v21, v27, v32, vcc_lo
	v_cndmask_b32_e32 v35, v19, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v17, v17, s0, s4
	v_cndmask_b32_e64 v10, v20, v16, s4
	v_mov_b32_e32 v20, 2
	v_cndmask_b32_e64 v16, v21, v32, s4
	v_cndmask_b32_e64 v18, v35, v18, s4
	s_delay_alu instid0(VALU_DEP_4)
	v_cmpx_gt_u32_e32 2, v10
	s_cbranch_execz .LBB0_85
; %bb.80:                               ;   in Loop: Header=BB0_5 Depth=2
	v_div_scale_f32 v20, null, v36, v36, v34
	v_div_scale_f32 v37, vcc_lo, v34, v36, v34
	s_mov_b32 s22, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v21, v20
	s_waitcnt_depctr 0xfff
	v_fma_f32 v35, -v20, v21, 1.0
	v_fmac_f32_e32 v21, v35, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v35, v37, v21
	v_fma_f32 v38, -v20, v35, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v35, v38, v21
	v_fma_f32 v20, -v20, v35, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v20, v20, v21, v35
	v_cmp_eq_u32_e32 vcc_lo, 1, v10
	v_div_fixup_f32 v34, v20, v36, v34
	v_cndmask_b32_e64 v36, v19, -0.5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v21, -v28, v34, v31
	v_fma_f32 v20, -0.5, v34, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cmp_lt_f32_e64 s4, 0, v20
	v_cndmask_b32_e32 v37, v17, v20, vcc_lo
	v_cndmask_b32_e64 v35, -v20, v20, s4
	v_cmp_eq_u32_e64 s4, 0, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_f32_e32 vcc_lo, v35, v27
	v_cndmask_b32_e64 v35, v18, -0.5, s4
	v_cndmask_b32_e64 v20, v16, v20, s4
	v_add_co_ci_u32_e64 v10, s4, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v18, v18, v35 :: v_dual_cndmask_b32 v17, v17, v37
	v_cndmask_b32_e32 v16, v16, v20, vcc_lo
	v_dual_cndmask_b32 v19, v19, v36 :: v_dual_mov_b32 v20, 2
	s_delay_alu instid0(VALU_DEP_4)
	v_cmpx_gt_u32_e32 2, v10
	s_cbranch_execz .LBB0_84
; %bb.81:                               ;   in Loop: Header=BB0_5 Depth=2
	v_mul_f32_e32 v20, 0.5, v34
	s_mov_b32 s23, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v20, v20, v21
	v_cmp_lt_f32_e32 vcc_lo, 0, v20
	v_cndmask_b32_e64 v21, -v20, v20, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_le_f32_e32 v21, v27
; %bb.82:                               ;   in Loop: Header=BB0_5 Depth=2
	v_cmp_eq_u32_e32 vcc_lo, 1, v10
	v_cmp_eq_u32_e64 s4, 0, v10
	v_dual_cndmask_b32 v17, v17, v20 :: v_dual_add_nc_u32 v10, 1, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e64 v16, v16, v20, s4
	v_cndmask_b32_e64 v19, v19, 0.5, vcc_lo
	v_cndmask_b32_e64 v18, v18, 0.5, s4
; %bb.83:                               ; %Flow211
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s23
	v_mov_b32_e32 v20, v10
.LBB0_84:                               ; %Flow212
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s22
.LBB0_85:                               ; %Flow213
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s21
                                        ; implicit-def: $vgpr36
                                        ; implicit-def: $vgpr34
.LBB0_86:                               ; %Flow217
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_and_not1_saveexec_b32 s21, s5
	s_cbranch_execz .LBB0_94
; %bb.87:                               ;   in Loop: Header=BB0_5 Depth=2
	v_div_scale_f32 v10, null, v36, v36, v34
	v_div_scale_f32 v18, vcc_lo, v34, v36, v34
	s_mov_b32 s22, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v16, v10
	s_waitcnt_depctr 0xfff
	v_fma_f32 v17, -v10, v16, 1.0
	v_fmac_f32_e32 v16, v17, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v17, v18, v16
	v_fma_f32 v19, -v10, v17, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v17, v19, v16
	v_fma_f32 v10, -v10, v17, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v10, v10, v16, v17
	v_div_fixup_f32 v10, v10, v36, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v17, -v28, v10, v31
	v_fma_f32 v16, -0.5, v10, v17
	v_fmac_f32_e32 v17, 0.5, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_f32_e32 vcc_lo, 0, v16
	v_cmp_lt_f32_e64 s4, 0, v17
	v_cndmask_b32_e64 v18, -v16, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v10, -v17, v17, s4
	v_cmp_le_f32_e32 vcc_lo, v18, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_cmp_nle_f32_e64 s4, v10, v27
	v_cndmask_b32_e64 v10, 0.5, -0.5, vcc_lo
	v_cndmask_b32_e64 v18, 0, 1, vcc_lo
	v_cndmask_b32_e32 v19, v17, v16, vcc_lo
	v_cndmask_b32_e64 v20, 1, 2, vcc_lo
	v_cndmask_b32_e64 v10, v10, -0.5, s4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v16, v19, v16, s4
	v_cndmask_b32_e64 v21, v20, v18, s4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v19, v11 :: v_dual_mov_b32 v18, v10
	v_mov_b32_e32 v20, 2
	v_cmpx_gt_u32_e32 2, v21
	s_cbranch_execz .LBB0_93
; %bb.88:                               ;   in Loop: Header=BB0_5 Depth=2
	v_div_scale_f32 v18, null, v34, v34, v36
	v_div_scale_f32 v35, vcc_lo, v36, v34, v36
	v_cmp_eq_u32_e64 s4, 1, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v19, v18
	s_waitcnt_depctr 0xfff
	v_fma_f32 v20, -v18, v19, 1.0
	v_fmac_f32_e32 v19, v20, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v20, v35, v19
	v_fma_f32 v37, -v18, v20, v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v20, v37, v19
	v_fma_f32 v18, -v18, v20, v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v18, v18, v19, v20
	v_cndmask_b32_e64 v20, v17, -v27, s4
	v_div_fixup_f32 v35, v18, v34, v36
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v34, -v31, v35, v28
	v_fma_f32 v18, -v27, v35, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_lt_f32_e32 vcc_lo, 0, v18
	v_cndmask_b32_e64 v19, -v18, v18, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v21
	v_cmp_ge_f32_e64 s5, 0.5, v19
	v_cndmask_b32_e32 v37, v10, v18, vcc_lo
	v_cndmask_b32_e64 v36, v16, -v27, vcc_lo
	v_cndmask_b32_e64 v18, 0.5, v18, s4
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v17, v17, v20, s5
	v_add_co_ci_u32_e64 v21, vcc_lo, 0, v21, s5
	v_cndmask_b32_e64 v16, v16, v36, s5
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v19, 0.5, v18, s5
	v_cndmask_b32_e64 v18, v10, v37, s5
	v_mov_b32_e32 v20, 2
	s_mov_b32 s5, exec_lo
	v_cmpx_gt_u32_e32 2, v21
	s_cbranch_execz .LBB0_92
; %bb.89:                               ;   in Loop: Header=BB0_5 Depth=2
	v_mul_f32_e32 v10, v27, v35
	s_mov_b32 s23, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v10, v10, v34
	v_cmp_lt_f32_e32 vcc_lo, 0, v10
	v_cndmask_b32_e64 v20, -v10, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ge_f32_e32 0.5, v20
; %bb.90:                               ;   in Loop: Header=BB0_5 Depth=2
	v_cmp_eq_u32_e32 vcc_lo, 1, v21
	v_cmp_eq_u32_e64 s4, 0, v21
	v_add_nc_u32_e32 v21, 1, v21
	v_cndmask_b32_e32 v19, v19, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e64 v18, v18, v10, s4
	v_cndmask_b32_e32 v17, v17, v27, vcc_lo
	v_cndmask_b32_e64 v16, v16, v27, s4
; %bb.91:                               ; %Flow214
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s23
	v_mov_b32_e32 v20, v21
.LBB0_92:                               ; %Flow215
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_93:                               ; %Flow216
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s22
.LBB0_94:                               ;   in Loop: Header=BB0_5 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s21
	v_sub_f32_e32 v10, v19, v18
	v_sub_f32_e32 v16, v17, v16
	v_mul_f32_e32 v10, v10, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v10, v16, v16
	v_mul_f32_e32 v16, 0x4f800000, v10
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v10, v10, v16, vcc_lo
	v_sqrt_f32_e32 v16, v10
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v17, -1, v16
	v_add_nc_u32_e32 v18, 1, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v19, -v17, v16, v10
	v_fma_f32 v21, -v18, v16, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s4, 0, v19
	v_cndmask_b32_e64 v16, v16, v17, s4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s4, 0, v21
	v_cndmask_b32_e64 v16, v16, v18, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v17, 0x37800000, v16
	v_cndmask_b32_e32 v16, v16, v17, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v10, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v10, v16, v10, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 2, v20
	v_cndmask_b32_e32 v10, 0, v10, vcc_lo
.LBB0_95:                               ; %Flow220
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_and_not1_saveexec_b32 s4, s20
	s_cbranch_execz .LBB0_99
; %bb.96:                               ;   in Loop: Header=BB0_5 Depth=2
	v_mov_b32_e32 v10, 0
	s_and_saveexec_b32 s5, s1
; %bb.97:                               ;   in Loop: Header=BB0_5 Depth=2
	v_mov_b32_e32 v10, 1.0
; %bb.98:                               ; %Flow218
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s5
.LBB0_99:                               ; %Flow221
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_100:                              ; %Flow224
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s17
                                        ; implicit-def: $vgpr34
                                        ; implicit-def: $vgpr35
.LBB0_101:                              ; %Flow241
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_and_not1_saveexec_b32 s5, s16
	s_cbranch_execz .LBB0_131
; %bb.102:                              ;   in Loop: Header=BB0_5 Depth=2
                                        ; implicit-def: $vgpr10
	s_and_saveexec_b32 s4, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s16, exec_lo, s4
	s_cbranch_execz .LBB0_126
; %bb.103:                              ;   in Loop: Header=BB0_5 Depth=2
                                        ; implicit-def: $vgpr10
	s_mov_b32 s3, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_neq_f32_e32 0, v34
	s_xor_b32 s17, exec_lo, s3
	s_cbranch_execz .LBB0_121
; %bb.104:                              ;   in Loop: Header=BB0_5 Depth=2
	v_cmp_lt_f32_e32 vcc_lo, 0, v35
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr18_vgpr19
	v_cndmask_b32_e64 v10, -v35, v35, vcc_lo
	v_cmp_lt_f32_e32 vcc_lo, 0, v34
	v_cndmask_b32_e64 v16, -v34, v34, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_ngt_f32_e32 vcc_lo, v10, v16
                                        ; implicit-def: $vgpr16_vgpr17
	s_and_saveexec_b32 s3, vcc_lo
	s_xor_b32 s4, exec_lo, s3
	s_cbranch_execz .LBB0_112
; %bb.105:                              ;   in Loop: Header=BB0_5 Depth=2
	v_div_scale_f32 v10, null, v34, v34, v35
	v_div_scale_f32 v18, vcc_lo, v35, v34, v35
	s_mov_b32 s20, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v16, v10
	s_waitcnt_depctr 0xfff
	v_fma_f32 v17, -v10, v16, 1.0
	v_fmac_f32_e32 v16, v17, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v17, v18, v16
	v_fma_f32 v19, -v10, v17, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v17, v19, v16
	v_fma_f32 v10, -v10, v17, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v10, v10, v16, v17
	v_div_fixup_f32 v10, v10, v34, v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v19, -v31, v10, v29
	v_fma_f32 v18, -v27, v10, v19
	v_fmac_f32_e32 v19, v27, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_f32_e32 vcc_lo, 0, v18
	v_cmp_lt_f32_e64 s3, 0, v19
	v_cndmask_b32_e64 v16, -v18, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v10, -v19, v19, s3
	v_cmp_ge_f32_e32 vcc_lo, 0.5, v16
	s_delay_alu instid0(VALU_DEP_2)
	v_cmp_nge_f32_e64 s3, 0.5, v10
	v_cndmask_b32_e64 v16, 0, 1, vcc_lo
	v_cndmask_b32_e32 v17, s0, v27, vcc_lo
	v_cndmask_b32_e64 v20, 1, 2, vcc_lo
	v_cndmask_b32_e32 v21, v27, v32, vcc_lo
	v_cndmask_b32_e32 v36, v19, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v17, v17, s0, s3
	v_cndmask_b32_e64 v10, v20, v16, s3
	v_mov_b32_e32 v20, 2
	v_cndmask_b32_e64 v16, v21, v32, s3
	v_cndmask_b32_e64 v18, v36, v18, s3
	s_delay_alu instid0(VALU_DEP_4)
	v_cmpx_gt_u32_e32 2, v10
	s_cbranch_execz .LBB0_111
; %bb.106:                              ;   in Loop: Header=BB0_5 Depth=2
	v_div_scale_f32 v20, null, v35, v35, v34
	v_div_scale_f32 v37, vcc_lo, v34, v35, v34
	s_mov_b32 s21, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v21, v20
	s_waitcnt_depctr 0xfff
	v_fma_f32 v36, -v20, v21, 1.0
	v_fmac_f32_e32 v21, v36, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v36, v37, v21
	v_fma_f32 v38, -v20, v36, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v36, v38, v21
	v_fma_f32 v20, -v20, v36, v37
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v20, v20, v21, v36
	v_cmp_eq_u32_e32 vcc_lo, 1, v10
	v_div_fixup_f32 v34, v20, v35, v34
	v_cndmask_b32_e64 v36, v19, -0.5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v21, -v29, v34, v31
	v_fma_f32 v20, -0.5, v34, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v37, v17, v20, vcc_lo
	v_cmp_lt_f32_e64 s3, 0, v20
	v_cndmask_b32_e64 v35, -v20, v20, s3
	v_cmp_eq_u32_e64 s3, 0, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_f32_e32 vcc_lo, v35, v27
	v_cndmask_b32_e64 v35, v18, -0.5, s3
	v_cndmask_b32_e64 v20, v16, v20, s3
	v_cndmask_b32_e32 v17, v17, v37, vcc_lo
	v_add_co_ci_u32_e64 v10, s3, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_cndmask_b32_e32 v16, v16, v20, vcc_lo
	v_dual_cndmask_b32 v19, v19, v36 :: v_dual_mov_b32 v20, 2
	v_cndmask_b32_e32 v18, v18, v35, vcc_lo
	v_cmpx_gt_u32_e32 2, v10
	s_cbranch_execz .LBB0_110
; %bb.107:                              ;   in Loop: Header=BB0_5 Depth=2
	v_mul_f32_e32 v20, 0.5, v34
	s_mov_b32 s22, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v20, v20, v21
	v_cmp_lt_f32_e32 vcc_lo, 0, v20
	v_cndmask_b32_e64 v21, -v20, v20, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_le_f32_e32 v21, v27
; %bb.108:                              ;   in Loop: Header=BB0_5 Depth=2
	v_cmp_eq_u32_e32 vcc_lo, 1, v10
	v_cmp_eq_u32_e64 s3, 0, v10
	v_dual_cndmask_b32 v17, v17, v20 :: v_dual_add_nc_u32 v10, 1, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e64 v16, v16, v20, s3
	v_cndmask_b32_e64 v19, v19, 0.5, vcc_lo
	v_cndmask_b32_e64 v18, v18, 0.5, s3
; %bb.109:                              ; %Flow226
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s22
	v_mov_b32_e32 v20, v10
.LBB0_110:                              ; %Flow227
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s21
.LBB0_111:                              ; %Flow228
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s20
                                        ; implicit-def: $vgpr35
                                        ; implicit-def: $vgpr34
.LBB0_112:                              ; %Flow234
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_and_not1_saveexec_b32 s20, s4
	s_cbranch_execz .LBB0_120
; %bb.113:                              ;   in Loop: Header=BB0_5 Depth=2
	v_div_scale_f32 v10, null, v35, v35, v34
	v_div_scale_f32 v18, vcc_lo, v34, v35, v34
	s_mov_b32 s21, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v16, v10
	s_waitcnt_depctr 0xfff
	v_fma_f32 v17, -v10, v16, 1.0
	v_fmac_f32_e32 v16, v17, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v17, v18, v16
	v_fma_f32 v19, -v10, v17, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v17, v19, v16
	v_fma_f32 v10, -v10, v17, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v10, v10, v16, v17
	v_div_fixup_f32 v10, v10, v35, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v17, -v29, v10, v31
	v_fma_f32 v16, -0.5, v10, v17
	v_fmac_f32_e32 v17, 0.5, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_f32_e32 vcc_lo, 0, v16
	v_cmp_lt_f32_e64 s3, 0, v17
	v_cndmask_b32_e64 v18, -v16, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v10, -v17, v17, s3
	v_cmp_le_f32_e32 vcc_lo, v18, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_cmp_nle_f32_e64 s3, v10, v27
	v_cndmask_b32_e64 v10, 0.5, -0.5, vcc_lo
	v_cndmask_b32_e64 v18, 0, 1, vcc_lo
	v_cndmask_b32_e32 v19, v17, v16, vcc_lo
	v_cndmask_b32_e64 v20, 1, 2, vcc_lo
	v_cndmask_b32_e64 v10, v10, -0.5, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v16, v19, v16, s3
	v_cndmask_b32_e64 v21, v20, v18, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_mov_b32 v19, v11 :: v_dual_mov_b32 v18, v10
	v_mov_b32_e32 v20, 2
	v_cmpx_gt_u32_e32 2, v21
	s_cbranch_execz .LBB0_119
; %bb.114:                              ;   in Loop: Header=BB0_5 Depth=2
	v_div_scale_f32 v18, null, v34, v34, v35
	v_div_scale_f32 v36, vcc_lo, v35, v34, v35
	v_cmp_eq_u32_e64 s3, 1, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v19, v18
	s_waitcnt_depctr 0xfff
	v_fma_f32 v20, -v18, v19, 1.0
	v_fmac_f32_e32 v19, v20, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v20, v36, v19
	v_fma_f32 v37, -v18, v20, v36
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v20, v37, v19
	v_fma_f32 v18, -v18, v20, v36
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v18, v18, v19, v20
	v_cndmask_b32_e64 v20, v17, -v27, s3
	v_div_fixup_f32 v35, v18, v34, v35
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v34, -v31, v35, v29
	v_fma_f32 v18, -v27, v35, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_lt_f32_e32 vcc_lo, 0, v18
	v_cndmask_b32_e64 v19, -v18, v18, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 0, v21
	v_cmp_ge_f32_e64 s4, 0.5, v19
	v_cndmask_b32_e32 v37, v10, v18, vcc_lo
	v_cndmask_b32_e64 v36, v16, -v27, vcc_lo
	v_cndmask_b32_e64 v18, 0.5, v18, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v17, v17, v20, s4
	v_add_co_ci_u32_e64 v21, vcc_lo, 0, v21, s4
	v_cndmask_b32_e64 v16, v16, v36, s4
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e64 v19, 0.5, v18, s4
	v_cndmask_b32_e64 v18, v10, v37, s4
	v_mov_b32_e32 v20, 2
	s_mov_b32 s4, exec_lo
	v_cmpx_gt_u32_e32 2, v21
	s_cbranch_execz .LBB0_118
; %bb.115:                              ;   in Loop: Header=BB0_5 Depth=2
	v_mul_f32_e32 v10, v27, v35
	s_mov_b32 s22, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v10, v10, v34
	v_cmp_lt_f32_e32 vcc_lo, 0, v10
	v_cndmask_b32_e64 v20, -v10, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ge_f32_e32 0.5, v20
; %bb.116:                              ;   in Loop: Header=BB0_5 Depth=2
	v_cmp_eq_u32_e32 vcc_lo, 1, v21
	v_cmp_eq_u32_e64 s3, 0, v21
	v_add_nc_u32_e32 v21, 1, v21
	v_cndmask_b32_e32 v19, v19, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e64 v18, v18, v10, s3
	v_cndmask_b32_e32 v17, v17, v27, vcc_lo
	v_cndmask_b32_e64 v16, v16, v27, s3
; %bb.117:                              ; %Flow230
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s22
	v_mov_b32_e32 v20, v21
.LBB0_118:                              ; %Flow231
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_119:                              ; %Flow232
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s21
.LBB0_120:                              ;   in Loop: Header=BB0_5 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s20
	v_sub_f32_e32 v10, v19, v18
	v_sub_f32_e32 v16, v17, v16
	v_mul_f32_e32 v10, v10, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v10, v16, v16
	v_mul_f32_e32 v16, 0x4f800000, v10
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v10, v10, v16, vcc_lo
	v_sqrt_f32_e32 v16, v10
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v17, -1, v16
	v_add_nc_u32_e32 v18, 1, v16
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v19, -v17, v16, v10
	v_fma_f32 v21, -v18, v16, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s3, 0, v19
	v_cndmask_b32_e64 v16, v16, v17, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s3, 0, v21
	v_cndmask_b32_e64 v16, v16, v18, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v17, 0x37800000, v16
	v_cndmask_b32_e32 v16, v16, v17, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v10, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v10, v16, v10, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, 2, v20
	v_cndmask_b32_e32 v10, 0, v10, vcc_lo
.LBB0_121:                              ; %Flow236
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_and_not1_saveexec_b32 s3, s17
	s_cbranch_execz .LBB0_125
; %bb.122:                              ;   in Loop: Header=BB0_5 Depth=2
	v_mov_b32_e32 v10, 0
	s_and_saveexec_b32 s4, s1
; %bb.123:                              ;   in Loop: Header=BB0_5 Depth=2
	v_mov_b32_e32 v10, 1.0
; %bb.124:                              ; %Flow235
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_125:                              ; %Flow237
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
.LBB0_126:                              ; %Flow239
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_and_not1_saveexec_b32 s3, s16
	s_cbranch_execz .LBB0_130
; %bb.127:                              ;   in Loop: Header=BB0_5 Depth=2
	v_mov_b32_e32 v10, 0
	s_and_saveexec_b32 s4, s0
; %bb.128:                              ;   in Loop: Header=BB0_5 Depth=2
	v_mov_b32_e32 v10, s6
; %bb.129:                              ; %Flow238
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s4
.LBB0_130:                              ; %Flow240
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s3
.LBB0_131:                              ; %_Z9find_l_3dffffffffffff.exit
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_or_b32 exec_lo, exec_lo, s5
	v_add_nc_u32_e32 v16, v30, v3
	v_add_co_u32 v12, s3, v12, 4
	v_add_co_ci_u32_e64 v13, s3, 0, v13, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v17, 31, v16
	v_lshlrev_b64 v[16:17], 2, v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v16, vcc_lo, s14, v16
	v_add_co_ci_u32_e32 v17, vcc_lo, s15, v17, vcc_lo
	v_cmp_ge_i32_e32 vcc_lo, v3, v33
	global_load_b32 v18, v[4:5], off
	global_load_b32 v16, v[16:17], off
	v_add_nc_u32_e32 v17, 1, v3
	s_or_b32 s13, vcc_lo, s13
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v3, v17 :: v_dual_fmac_f32 v18, v10, v16
	global_store_b32 v[4:5], v18, off
	global_load_b32 v16, v[6:7], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v10, v10, v16
	global_store_b32 v[6:7], v10, off
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_5
.LBB0_132:                              ; %Flow243
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s7
	v_add_nc_u32_e32 v3, 1, v0
	v_cmp_ge_i32_e32 vcc_lo, v0, v22
	v_add_nc_u32_e32 v30, s10, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_mov_b32_e32 v0, v3
	s_or_b32 s11, vcc_lo, s11
	s_and_not1_b32 exec_lo, exec_lo, s11
	s_cbranch_execnz .LBB0_3
.LBB0_133:                              ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z26Atx_cone_mf_gpu_new_kernelPfS_S_ffS_S_ffffffiiiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 92
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 46
		.amdhsa_next_free_sgpr 24
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z26Atx_cone_mf_gpu_new_kernelPfS_S_ffS_S_ffffffiiiii, .Lfunc_end0-_Z26Atx_cone_mf_gpu_new_kernelPfS_S_ffS_S_ffffffiiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 7784
; NumSgprs: 26
; NumVgprs: 46
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 26
; NumVGPRsForWavesPerEU: 46
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z8set2zeroPfii         ; -- Begin function _Z8set2zeroPfii
	.globl	_Z8set2zeroPfii
	.p2align	8
	.type	_Z8set2zeroPfii,@function
_Z8set2zeroPfii:                        ; @_Z8set2zeroPfii
; %bb.0:
	s_load_b64 s[4:5], s[0:1], 0x8
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v2, v0, 10, 10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v0, s14, 4, v1
	v_lshl_add_u32 v1, s15, 4, v2
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s4, v0
	v_cmp_gt_i32_e64 s2, s5, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_2
; %bb.1:
	s_load_b64 s[0:1], s[0:1], 0x0
	v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	v_mov_b32_e32 v2, 0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b32 v[0:1], v2, off
.LBB1_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8set2zeroPfii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 16
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z8set2zeroPfii, .Lfunc_end1-_Z8set2zeroPfii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 156
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z6scalexPfiif          ; -- Begin function _Z6scalexPfiif
	.globl	_Z6scalexPfiif
	.p2align	8
	.type	_Z6scalexPfiif,@function
_Z6scalexPfiif:                         ; @_Z6scalexPfiif
; %bb.0:
	s_load_b128 s[4:7], s[0:1], 0x8
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v2, v0, 10, 10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v0, s14, 4, v1
	v_lshl_add_u32 v1, s15, 4, v2
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s4, v0
	v_cmp_gt_i32_e64 s2, s5, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB2_2
; %bb.1:
	s_load_b64 s[0:1], s[0:1], 0x0
	v_mad_u64_u32 v[2:3], null, v1, s4, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_load_b32 v2, v[0:1], off
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v2, s6, v2
	global_store_b32 v[0:1], v2, off
.LBB2_2:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6scalexPfiif
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 20
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 4
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z6scalexPfiif, .Lfunc_end2-_Z6scalexPfiif
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 168
; NumSgprs: 18
; NumVgprs: 4
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 4
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z25Ax_cone_mf_gpu_kernel_newPfS_S_ffS_S_ffffiiiii ; -- Begin function _Z25Ax_cone_mf_gpu_kernel_newPfS_S_ffS_S_ffffiiiii
	.globl	_Z25Ax_cone_mf_gpu_kernel_newPfS_S_ffS_S_ffffiiiii
	.p2align	8
	.type	_Z25Ax_cone_mf_gpu_kernel_newPfS_S_ffS_S_ffffiiiii,@function
_Z25Ax_cone_mf_gpu_kernel_newPfS_S_ffS_S_ffffiiiii: ; @_Z25Ax_cone_mf_gpu_kernel_newPfS_S_ffS_S_ffffiiiii
; %bb.0:
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x30
	s_load_b32 s2, s[0:1], 0x50
	v_and_b32_e32 v1, 0x3ff, v0
	v_bfe_u32 v0, v0, 10, 10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v1, s14, 4, v1
	v_lshl_add_u32 v0, s15, 4, v0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_gt_i32_e32 vcc_lo, s11, v1
	v_cmp_gt_i32_e64 s2, s2, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB3_208
; %bb.1:
	s_load_b256 s[12:19], s[0:1], 0x10
	v_mad_u64_u32 v[5:6], null, v0, s11, v[1:2]
	v_ashrrev_i32_e32 v2, 31, v1
	s_lshr_b32 s2, s10, 31
	v_mov_b32_e32 v8, 0
	s_add_i32 s2, s10, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[1:2], 2, v[1:2]
	v_ashrrev_i32_e32 v6, 31, v5
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v1, vcc_lo, s16, v1
	v_add_co_ci_u32_e32 v2, vcc_lo, s17, v2, vcc_lo
	v_mul_f32_e64 v7, -s4, s15
	global_load_b32 v2, v[1:2], off
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	v_add_co_u32 v0, vcc_lo, s18, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s19, v1, vcc_lo
	s_load_b128 s[16:19], s[0:1], 0x0
	s_lshr_b32 s0, s8, 31
	s_lshr_b32 s1, s9, 31
	global_load_b32 v4, v[0:1], off
	s_add_i32 s0, s8, s0
	s_add_i32 s1, s9, s1
	s_ashr_i32 s11, s0, 1
	s_mov_b32 s0, exec_lo
	s_waitcnt lgkmcnt(0)
	s_mov_b32 s20, s16
	s_mov_b32 s21, s17
	s_waitcnt vmcnt(1)
	v_mul_f32_e32 v0, s15, v2
	v_mul_f32_e32 v18, s14, v2
	v_lshlrev_b64 v[2:3], 2, v[5:6]
	v_mul_f32_e64 v6, -s4, s14
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v19, s14, s5, -v0
	v_fmac_f32_e64 v18, s15, s5
	s_ashr_i32 s5, s2, 1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, s18, v2
	v_fma_f32 v5, -s4, s14, -v19
	v_add_co_ci_u32_e32 v1, vcc_lo, s19, v3, vcc_lo
	v_fma_f32 v17, -s4, s15, -v18
	s_ashr_i32 s15, s1, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_lt_f32_e32 vcc_lo, 0, v5
	v_cndmask_b32_e64 v9, -v5, v5, vcc_lo
	v_cmp_lt_f32_e32 vcc_lo, 0, v17
	v_cndmask_b32_e64 v10, -v17, v17, vcc_lo
	v_add_co_u32 v2, vcc_lo, s12, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s13, v3, vcc_lo
	global_store_b32 v[0:1], v8, off
	global_store_b32 v[2:3], v8, off
	v_cmpx_ngt_f32_e32 v9, v10
	s_xor_b32 s18, exec_lo, s0
	s_cbranch_execz .LBB3_104
; %bb.2:
	s_cmp_lt_i32 s9, 1
	s_cbranch_scc1 .LBB3_104
; %bb.3:                                ; %.lr.ph
	v_dual_sub_f32 v11, v19, v6 :: v_dual_sub_f32 v12, v18, v7
	s_mov_b32 s12, 0
	s_sub_i32 s19, 0, s15
	s_mov_b32 s14, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_div_scale_f32 v9, null, v12, v12, v11
	s_waitcnt vmcnt(0)
	v_div_scale_f32 v10, null, v12, v12, v4
	v_div_scale_f32 v16, vcc_lo, v11, v12, v11
	v_rcp_f32_e32 v13, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v14, v10
	v_div_scale_f32 v18, s0, v4, v12, v4
	s_waitcnt_depctr 0xfff
	v_fma_f32 v8, -v9, v13, 1.0
	v_fma_f32 v15, -v10, v14, 1.0
	v_dual_fmac_f32 v13, v8, v13 :: v_dual_fmac_f32 v14, v15, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v15, v16, v13
	v_mul_f32_e32 v19, v18, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v8, -v9, v15, v16
	v_fma_f32 v20, -v10, v19, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v15, v8, v13
	v_fmac_f32_e32 v19, v20, v14
	v_cvt_f32_i32_e32 v8, s11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v16, -v9, v15, v16
	v_fma_f32 v10, -v10, v19, v18
	v_mul_f32_e32 v9, v17, v17
	s_delay_alu instid0(VALU_DEP_3)
	v_div_fmas_f32 v13, v16, v13, v15
	v_mov_b32_e32 v16, 0
	s_mov_b32 vcc_lo, s0
	v_sub_f32_e32 v15, 0, v4
	v_div_fmas_f32 v14, v10, v14, v19
	v_fmac_f32_e32 v9, v5, v5
	v_div_fixup_f32 v11, v13, v12, v11
	v_cvt_f32_i32_e32 v10, s5
	v_cvt_f32_i32_e32 v13, s10
	v_div_fixup_f32 v12, v14, v12, v4
	v_cvt_f32_i32_e32 v14, s8
	v_fma_f32 v15, v15, v15, v9
	v_cmp_nle_f32_e64 s0, 0, v11
	s_delay_alu instid0(VALU_DEP_4)
	v_cmp_nle_f32_e64 s1, 0, v12
.LBB3_4:                                ; =>This Inner Loop Header: Depth=1
	s_add_i32 s2, s19, s14
	s_mov_b32 s4, 0
	s_waitcnt vmcnt(1)
	v_cvt_f32_i32_e32 v4, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, 1.0, v4
	v_cndmask_b32_e64 v18, v4, v5, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v18, v18, v7
	v_cndmask_b32_e64 v17, v5, v4, s1
	v_cndmask_b32_e64 v28, v4, v5, s0
	v_cndmask_b32_e64 v4, v5, v4, s0
	v_fma_f32 v19, v12, v18, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v5, v28, v7
	v_sub_f32_e32 v4, v4, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_scale_f32 v20, null, s7, s7, v19
	v_fma_f32 v5, v11, v5, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v4, v11, v4, v6
	v_rcp_f32_e32 v22, v20
	s_waitcnt_depctr 0xfff
	v_fma_f32 v24, -v20, v22, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v17, v17, v7 :: v_dual_fmac_f32 v22, v24, v22
	v_fma_f32 v17, v12, v17, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v18, null, s7, s7, v17
	v_div_scale_f32 v25, vcc_lo, v17, s7, v17
	v_rcp_f32_e32 v21, v18
	s_waitcnt vmcnt(0)
	s_waitcnt_depctr 0xfff
	v_fma_f32 v23, -v18, v21, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v21, v23, v21
	v_div_scale_f32 v23, s2, v19, s7, v19
	v_mul_f32_e32 v26, v23, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v29, -v20, v26, v23
	v_fmac_f32_e32 v26, v29, v22
	v_mul_f32_e32 v24, v25, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v20, -v20, v26, v23
	v_fma_f32 v27, -v18, v24, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v24, v27, v21
	v_fma_f32 v18, -v18, v24, v25
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fmas_f32 v21, v18, v21, v24
	s_mov_b32 vcc_lo, s2
	v_add_f32_e32 v18, v5, v8
	v_div_fmas_f32 v20, v20, v22, v26
                                        ; implicit-def: $vgpr24
	s_mov_b32 s2, exec_lo
	v_div_fixup_f32 v5, v21, s7, v17
	v_add_f32_e32 v21, v4, v8
	v_floor_f32_e32 v4, v18
	v_div_fixup_f32 v17, v20, s7, v19
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_f32_e32 v22, v5, v10
	v_floor_f32_e32 v5, v21
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_i32_f32_e32 v4, v4
	v_add_f32_e32 v19, v17, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_floor_f32_e32 v17, v22
	v_cvt_i32_f32_e32 v5, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_floor_f32_e32 v23, v19
	v_cvt_i32_f32_e32 v20, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_i32_f32_e32 v17, v23
                                        ; implicit-def: $vgpr23
	v_cmpx_ne_u32_e64 v5, v4
	s_xor_b32 s22, exec_lo, s2
	s_cbranch_execz .LBB3_83
; %bb.5:                                ;   in Loop: Header=BB3_4 Depth=1
	v_cmp_gt_i32_e32 vcc_lo, 1, v5
	v_cmp_le_i32_e64 s2, s8, v5
	s_mov_b32 s13, 0
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s23, exec_lo, s3
	s_cbranch_execz .LBB3_54
; %bb.6:                                ;   in Loop: Header=BB3_4 Depth=1
	s_mov_b32 s24, exec_lo
	v_cmpx_eq_u32_e32 0, v5
	s_cbranch_execz .LBB3_29
; %bb.7:                                ;   in Loop: Header=BB3_4 Depth=1
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
	s_mov_b32 s2, exec_lo
	v_cmpx_ne_u32_e64 v20, v17
	s_xor_b32 s25, exec_lo, s2
	s_cbranch_execz .LBB3_23
; %bb.8:                                ;   in Loop: Header=BB3_4 Depth=1
	v_cmp_gt_i32_e32 vcc_lo, 1, v20
	v_cmp_le_i32_e64 s2, s10, v20
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s26, exec_lo, s3
	s_cbranch_execz .LBB3_16
; %bb.9:                                ;   in Loop: Header=BB3_4 Depth=1
	s_mov_b32 s27, exec_lo
	v_cmpx_eq_u32_e32 0, v20
	s_cbranch_execz .LBB3_11
; %bb.10:                               ; %.sink.split2416
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_ashr_i32 s13, s12, 31
	v_sub_f32_e32 v25, v21, v18
	s_lshl_b64 s[2:3], s[12:13], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_add_u32 s2, s16, s2
	s_addc_u32 s3, s17, s3
	v_fma_f32 v26, v25, v25, 1.0
	global_load_b32 v23, v16, s[2:3]
	global_load_b32 v24, v[0:1], off
	v_mul_f32_e32 v26, v15, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v27, null, v9, v9, v26
	v_rcp_f32_e32 v28, v27
	s_waitcnt_depctr 0xfff
	v_fma_f32 v29, -v27, v28, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v28, v29, v28
	v_div_scale_f32 v29, vcc_lo, v26, v9, v26
	v_mul_f32_e32 v30, v29, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v31, -v27, v30, v29
	v_fmac_f32_e32 v30, v31, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v27, -v27, v30, v29
	v_div_scale_f32 v29, null, v25, v25, -v18
	v_div_fmas_f32 v27, v27, v28, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v26, v27, v9, v26
	v_dual_sub_f32 v27, v22, v19 :: v_dual_mul_f32 v28, 0x4f800000, v26
	v_cmp_gt_f32_e64 s2, 0xf800000, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f32 v30, null, v27, v27, -v19
	v_cndmask_b32_e64 v26, v26, v28, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v31, v30
	v_rcp_f32_e32 v28, v29
	v_sqrt_f32_e32 v32, v26
	s_delay_alu instid0(TRANS32_DEP_3)
	v_fma_f32 v34, -v30, v31, 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v33, -v29, v28, 1.0
	v_add_nc_u32_e32 v35, -1, v32
	v_fmac_f32_e32 v31, v34, v31
	v_div_scale_f32 v34, s3, -v19, v27, -v19
	v_add_nc_u32_e32 v36, 1, v32
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v38, -v35, v32, v26
	v_mul_f32_e32 v39, v34, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v40, -v36, v32, v26
	v_cmp_ge_f32_e64 s4, 0, v38
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v32, v32, v35, s4
	v_fma_f32 v35, -v30, v39, v34
	v_fmac_f32_e32 v28, v33, v28
	v_div_scale_f32 v33, vcc_lo, -v18, v25, -v18
	v_cmp_lt_f32_e64 s4, 0, v40
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v39, v35, v31
	v_mul_f32_e32 v37, v33, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v30, -v30, v39, v34
	v_fma_f32 v41, -v29, v37, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v37, v41, v28
	v_fma_f32 v29, -v29, v37, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v28, v29, v28, v37
	s_mov_b32 vcc_lo, s3
	v_div_fmas_f32 v29, v30, v31, v39
	v_cmp_class_f32_e64 vcc_lo, v26, 0x260
	v_div_fixup_f32 v25, v28, v25, -v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v27, v29, v27, -v19
	v_sub_f32_e32 v29, 1.0, v25
	v_cndmask_b32_e64 v32, v32, v36, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v28, 1.0, v27 :: v_dual_mul_f32 v33, 0x37800000, v32
	v_cndmask_b32_e64 v30, v32, v33, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v26, v30, v26, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, v25, v27
	v_dual_cndmask_b32 v25, v28, v26 :: v_dual_cndmask_b32 v26, v26, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v27, v26, v25
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v24, v27, v23
	global_store_b32 v[0:1], v24, off
	global_load_b32 v23, v[2:3], off
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v23, v26, v25
	global_store_b32 v[2:3], v23, off
.LBB3_11:                               ;   in Loop: Header=BB3_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s27
	s_mov_b32 s2, 0
	s_mov_b32 s3, exec_lo
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
	v_cmpx_eq_u32_e64 s10, v20
	s_cbranch_execz .LBB3_15
; %bb.12:                               ;   in Loop: Header=BB3_4 Depth=1
	v_dual_sub_f32 v25, v21, v18 :: v_dual_sub_f32 v24, v22, v19
	s_mov_b32 s4, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v26, null, v25, v25, -v18
	v_div_scale_f32 v32, vcc_lo, -v18, v25, -v18
	v_rcp_f32_e32 v28, v26
	s_waitcnt_depctr 0xfff
	v_fma_f32 v30, -v26, v28, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v23, v13, v19 :: v_dual_fmac_f32 v28, v30, v28
	v_div_scale_f32 v27, null, v24, v24, v23
	v_div_scale_f32 v30, s2, v23, v24, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v29, v27
	s_waitcnt_depctr 0xfff
	v_fma_f32 v31, -v27, v29, 1.0
	v_fmac_f32_e32 v29, v31, v29
	v_mul_f32_e32 v31, v32, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v33, v30, v29
	v_fma_f32 v34, -v26, v31, v32
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v35, -v27, v33, v30
	v_fmac_f32_e32 v31, v34, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v33, v35, v29
	v_fma_f32 v26, -v26, v31, v32
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v27, -v27, v33, v30
	v_div_fmas_f32 v26, v26, v28, v31
	s_mov_b32 vcc_lo, s2
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v27, v27, v29, v33
	v_div_fixup_f32 v26, v26, v25, -v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v27, v27, v24, v23
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
	v_cmpx_ngt_f32_e32 v26, v27
	s_xor_b32 s13, exec_lo, s2
	s_cbranch_execz .LBB3_14
; %bb.13:                               ;   in Loop: Header=BB3_4 Depth=1
	v_mad_u64_u32 v[23:24], null, v17, s9, s[14:15]
	s_mov_b32 s4, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v23, v23, s8
	v_ashrrev_i32_e32 v24, 31, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[23:24], 2, v[23:24]
	v_add_co_u32 v23, vcc_lo, s16, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v24, vcc_lo, s17, v24, vcc_lo
	global_load_b32 v28, v[23:24], off
	global_load_b32 v23, v[0:1], off
	v_fma_f32 v24, v25, v25, 1.0
	v_mul_f32_e32 v24, v15, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v25, null, v9, v9, v24
	v_rcp_f32_e32 v29, v25
	s_waitcnt_depctr 0xfff
	v_fma_f32 v30, -v25, v29, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v29, v30, v29
	v_div_scale_f32 v30, vcc_lo, v24, v9, v24
	v_mul_f32_e32 v31, v30, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v32, -v25, v31, v30
	v_fmac_f32_e32 v31, v32, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v25, -v25, v31, v30
	v_div_fmas_f32 v25, v25, v29, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v24, v25, v9, v24
	v_mul_f32_e32 v25, 0x4f800000, v24
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v24, v24, v25, vcc_lo
	v_sqrt_f32_e32 v25, v24
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v29, -1, v25
	v_add_nc_u32_e32 v30, 1, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v31, -v29, v25, v24
	v_fma_f32 v32, -v30, v25, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s2, 0, v31
	v_cndmask_b32_e64 v25, v25, v29, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s2, 0, v32
	v_cndmask_b32_e64 v25, v25, v30, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v29, 0x37800000, v25
	v_cndmask_b32_e32 v25, v25, v29, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v24, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v24, v25, v24 :: v_dual_sub_f32 v25, v27, v26
	v_mul_f32_e32 v24, v24, v25
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v23, v24, v28
.LBB3_14:                               ; %Flow2497
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s2, s4, exec_lo
.LBB3_15:                               ; %Flow2496
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s13, s2, exec_lo
.LBB3_16:                               ; %Flow2495
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_and_not1_saveexec_b32 s26, s26
	s_cbranch_execz .LBB3_22
; %bb.17:                               ;   in Loop: Header=BB3_4 Depth=1
	global_load_b32 v23, v[0:1], off
	v_sub_f32_e32 v24, v21, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v25, v24, v24, 1.0
	v_mul_f32_e32 v25, v15, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v26, null, v9, v9, v25
	v_rcp_f32_e32 v27, v26
	s_waitcnt_depctr 0xfff
	v_fma_f32 v28, -v26, v27, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v27, v28, v27
	v_div_scale_f32 v28, vcc_lo, v25, v9, v25
	v_mul_f32_e32 v29, v28, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v30, -v26, v29, v28
	v_fmac_f32_e32 v29, v30, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v26, -v26, v29, v28
	v_div_fmas_f32 v26, v26, v27, v29
	v_cvt_f32_i32_e32 v27, v20
	v_div_scale_f32 v29, null, v24, v24, -v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v25, v26, v9, v25
	v_dual_sub_f32 v27, v27, v19 :: v_dual_mul_f32 v26, 0x4f800000, v25
	v_cmp_gt_f32_e64 s2, 0xf800000, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v25, v25, v26, s2
	v_rcp_f32_e32 v26, v29
	v_sqrt_f32_e32 v32, v25
	v_sub_f32_e32 v28, v22, v19
	s_waitcnt_depctr 0xfff
	v_fma_f32 v33, -v29, v26, 1.0
	v_add_nc_u32_e32 v35, -1, v32
	v_div_scale_f32 v30, null, v28, v28, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v26, v33, v26
	v_div_scale_f32 v33, vcc_lo, -v18, v24, -v18
	v_rcp_f32_e32 v31, v30
	v_add_nc_u32_e32 v36, 1, v32
	v_fma_f32 v38, -v35, v32, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v37, v33, v26
	v_fma_f32 v40, -v36, v32, v25
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_ge_f32_e64 s4, 0, v38
	v_fma_f32 v41, -v29, v37, v33
	s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v34, -v30, v31, 1.0
	v_cndmask_b32_e64 v32, v32, v35, s4
	v_cmp_lt_f32_e64 s4, 0, v40
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v37, v41, v26
	v_fmac_f32_e32 v31, v34, v31
	v_div_scale_f32 v34, s3, v27, v28, v27
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v32, v32, v36, s4
	v_fma_f32 v29, -v29, v37, v33
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v39, v34, v31
	v_mul_f32_e32 v33, 0x37800000, v32
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v26, v29, v26, v37
	s_mov_b32 vcc_lo, s3
	v_fma_f32 v35, -v30, v39, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v26, v26, v24, -v18
                                        ; implicit-def: $vgpr24
	v_fmac_f32_e32 v39, v35, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v30, -v30, v39, v34
	v_div_fmas_f32 v29, v30, v31, v39
	v_cndmask_b32_e64 v30, v32, v33, s2
	v_cmp_class_f32_e64 vcc_lo, v25, 0x260
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_fixup_f32 v27, v29, v28, v27
	v_cndmask_b32_e32 v25, v30, v25, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_ngt_f32_e32 v26, v27
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB3_19
; %bb.18:                               ;   in Loop: Header=BB3_4 Depth=1
	v_mad_u64_u32 v[28:29], null, v17, s9, s[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v28, v28, s8
	v_ashrrev_i32_e32 v29, 31, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[28:29], 2, v[28:29]
	v_add_co_u32 v28, vcc_lo, s16, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v29, vcc_lo, s17, v29, vcc_lo
	global_load_b32 v24, v[28:29], off
	v_sub_f32_e32 v26, v27, v26
	v_mul_f32_e32 v28, v25, v26
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v23, v28, v24
	global_store_b32 v[0:1], v23, off
	global_load_b32 v28, v[2:3], off
	v_mad_u64_u32 v[23:24], null, v20, s9, s[14:15]
	v_mul_lo_u32 v23, v23, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v24, 31, v23
	v_lshlrev_b64 v[23:24], 2, v[23:24]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v23, vcc_lo, s16, v23
	v_add_co_ci_u32_e32 v24, vcc_lo, s17, v24, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v28, v25, v26
	global_store_b32 v[2:3], v28, off
	global_load_b32 v26, v[23:24], off
	global_load_b32 v23, v[0:1], off
	v_sub_f32_e32 v24, 1.0, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v24, v25, v24
                                        ; implicit-def: $vgpr25
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v23, v24, v26
                                        ; implicit-def: $vgpr26
.LBB3_19:                               ; %Flow2491
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_and_not1_saveexec_b32 s2, s2
	s_cbranch_execz .LBB3_21
; %bb.20:                               ;   in Loop: Header=BB3_4 Depth=1
	v_mad_u64_u32 v[27:28], null, v20, s9, s[14:15]
	v_sub_f32_e32 v24, 1.0, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v24, v24, v25
	v_mul_lo_u32 v27, v27, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v28, 31, v27
	v_lshlrev_b64 v[27:28], 2, v[27:28]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v27, vcc_lo, s16, v27
	v_add_co_ci_u32_e32 v28, vcc_lo, s17, v28, vcc_lo
	global_load_b32 v27, v[27:28], off
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v23, v24, v27
.LBB3_21:                               ; %Flow2492
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s13, s13, exec_lo
.LBB3_22:                               ; %Flow2498
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s26
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s4, s13, exec_lo
.LBB3_23:                               ; %Flow2494
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_and_not1_saveexec_b32 s13, s25
	s_cbranch_execz .LBB3_27
; %bb.24:                               ;   in Loop: Header=BB3_4 Depth=1
	v_cmp_lt_i32_e32 vcc_lo, -1, v17
	v_cmp_gt_i32_e64 s2, s10, v17
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s3, vcc_lo, s2
	s_mov_b32 s2, s4
	s_and_saveexec_b32 s25, s3
	s_cbranch_execz .LBB3_26
; %bb.25:                               ;   in Loop: Header=BB3_4 Depth=1
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[23:24], null, v17, s9, s[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v23, v23, s8
	v_ashrrev_i32_e32 v24, 31, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[23:24], 2, v[23:24]
	v_add_co_u32 v23, vcc_lo, s16, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v24, vcc_lo, s17, v24, vcc_lo
	global_load_b32 v25, v[23:24], off
	global_load_b32 v23, v[0:1], off
	v_sub_f32_e32 v24, v21, v18
	v_fma_f32 v26, v24, v24, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v26, v15, v26
	v_div_scale_f32 v27, null, v9, v9, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v28, v27
	s_waitcnt_depctr 0xfff
	v_fma_f32 v29, -v27, v28, 1.0
	v_fmac_f32_e32 v28, v29, v28
	v_div_scale_f32 v29, vcc_lo, v26, v9, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v30, v29, v28
	v_fma_f32 v31, -v27, v30, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v30, v31, v28
	v_fma_f32 v27, -v27, v30, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v27, v27, v28, v30
	v_div_fixup_f32 v26, v27, v9, v26
	v_div_scale_f32 v27, null, v24, v24, -v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v28, 0x4f800000, v26
	v_cmp_gt_f32_e64 s2, 0xf800000, v26
	v_rcp_f32_e32 v29, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v26, v26, v28, s2
	v_sqrt_f32_e32 v28, v26
	s_waitcnt_depctr 0xfff
	v_fma_f32 v30, -v27, v29, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v29, v30, v29
	v_div_scale_f32 v30, vcc_lo, -v18, v24, -v18
	v_add_nc_u32_e32 v31, -1, v28
	v_dual_mul_f32 v33, v30, v29 :: v_dual_add_nc_u32 v32, 1, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v34, -v31, v28, v26
	v_fma_f32 v35, -v32, v28, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v36, -v27, v33, v30
	v_cmp_ge_f32_e64 s3, 0, v34
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v33, v36, v29
	v_cndmask_b32_e64 v28, v28, v31, s3
	v_cmp_lt_f32_e64 s3, 0, v35
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v27, -v27, v33, v30
	v_cndmask_b32_e64 v28, v28, v32, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v27, v27, v29, v33
	v_cmp_class_f32_e64 vcc_lo, v26, 0x260
	v_mul_f32_e32 v30, 0x37800000, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v24, v27, v24, -v18
	v_cndmask_b32_e64 v28, v28, v30, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v24, 1.0, v24
	s_or_b32 s2, s4, exec_lo
	v_cndmask_b32_e32 v26, v28, v26, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v24, v24, v26
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v23, v24, v25
.LBB3_26:                               ; %Flow2500
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s25
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s3, s4, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_or_b32 s4, s3, s2
.LBB3_27:                               ; %Flow2499
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s4
	s_cbranch_execz .LBB3_29
; %bb.28:                               ; %.sink.split2423
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v23, off
	global_load_b32 v23, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v23, v24, v23
	global_store_b32 v[2:3], v23, off
.LBB3_29:                               ;   in Loop: Header=BB3_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s24
	s_mov_b32 s2, 0
	s_mov_b32 s13, exec_lo
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
	v_cmpx_eq_u32_e64 s8, v5
	s_cbranch_execz .LBB3_53
; %bb.30:                               ;   in Loop: Header=BB3_4 Depth=1
	s_mov_b32 s4, 0
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
	s_mov_b32 s2, exec_lo
	v_cmpx_ne_u32_e64 v20, v17
	s_xor_b32 s24, exec_lo, s2
	s_cbranch_execz .LBB3_48
; %bb.31:                               ;   in Loop: Header=BB3_4 Depth=1
	v_cmp_gt_i32_e32 vcc_lo, 1, v20
	v_cmp_le_i32_e64 s2, s10, v20
	s_mov_b32 s26, 0
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s25, exec_lo, s3
	s_cbranch_execz .LBB3_41
; %bb.32:                               ;   in Loop: Header=BB3_4 Depth=1
	v_sub_f32_e32 v5, v21, v18
	v_sub_f32_e32 v21, v22, v19
	v_sub_f32_e32 v18, v14, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v24, null, v21, v21, -v19
	v_div_scale_f32 v29, s3, -v19, v21, -v19
	v_rcp_f32_e32 v27, v24
	s_waitcnt_depctr 0xfff
	v_fma_f32 v26, -v24, v27, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v27, v26, v27
	v_mul_f32_e32 v30, v29, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v31, -v24, v30, v29
	v_fmac_f32_e32 v30, v31, v27
	s_waitcnt vmcnt(0)
	v_div_scale_f32 v23, null, v5, v5, v18
	v_div_scale_f32 v28, s2, v18, v5, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_mov_b32 vcc_lo, s2
	v_rcp_f32_e32 v22, v23
	s_waitcnt_depctr 0xfff
	v_fma_f32 v25, -v23, v22, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v22, v25, v22
	v_mul_f32_e32 v25, v28, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v26, -v23, v25, v28
	v_fmac_f32_e32 v25, v26, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v26, -v23, v25, v28
	v_fma_f32 v23, -v24, v30, v29
	v_div_fmas_f32 v24, v26, v22, v25
	s_mov_b32 vcc_lo, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v27, v23, v27, v30
	v_cmp_eq_u32_e32 vcc_lo, 0, v20
	v_div_fixup_f32 v23, v24, v5, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v24, v27, v21, -v19
	v_cmp_gt_f32_e64 s3, v23, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s3
	s_and_saveexec_b32 s4, s3
	s_cbranch_execz .LBB3_34
; %bb.33:                               ;   in Loop: Header=BB3_4 Depth=1
	v_add_nc_u32_e32 v27, s12, v4
	v_fma_f32 v29, v5, v5, 1.0
	v_sub_f32_e32 v23, v23, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v28, 31, v27
	v_mul_f32_e32 v29, v15, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[27:28], 2, v[27:28]
	v_div_scale_f32 v30, null, v9, v9, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v31, v30
	v_add_co_u32 v27, vcc_lo, s16, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v28, vcc_lo, s17, v28, vcc_lo
	global_load_b32 v27, v[27:28], off
	global_load_b32 v28, v[0:1], off
	v_fma_f32 v32, -v30, v31, 1.0
	v_fmac_f32_e32 v31, v32, v31
	v_div_scale_f32 v32, vcc_lo, v29, v9, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v33, v32, v31
	v_fma_f32 v34, -v30, v33, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v33, v34, v31
	v_fma_f32 v30, -v30, v33, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v30, v30, v31, v33
	v_div_fixup_f32 v29, v30, v9, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v30, 0x4f800000, v29
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v29
	v_cndmask_b32_e32 v29, v29, v30, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v30, v29
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v31, -1, v30
	v_add_nc_u32_e32 v32, 1, v30
	v_fma_f32 v33, -v31, v30, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v34, -v32, v30, v29
	v_cmp_ge_f32_e64 s3, 0, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v30, v30, v31, s3
	v_cmp_lt_f32_e64 s3, 0, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v30, v30, v32, s3
	v_mul_f32_e32 v31, 0x37800000, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v30, v30, v31, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v29, 0x260
	v_cndmask_b32_e32 v29, v30, v29, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v24, v29, v23
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v28, v24, v27
	global_store_b32 v[0:1], v28, off
	global_load_b32 v24, v[2:3], off
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v24, v29, v23
	global_store_b32 v[2:3], v24, off
.LBB3_34:                               ;   in Loop: Header=BB3_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
	s_mov_b32 s3, 0
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
	s_mov_b32 s4, exec_lo
	v_cmpx_eq_u32_e64 s10, v20
	s_xor_b32 s26, exec_lo, s4
	s_cbranch_execz .LBB3_40
; %bb.35:                               ;   in Loop: Header=BB3_4 Depth=1
	v_mad_u64_u32 v[23:24], null, v17, s9, s[14:15]
	v_fma_f32 v17, v5, v5, 1.0
	v_sub_f32_e32 v19, v13, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v17, v15, v17
	v_mad_u64_u32 v[27:28], null, v23, s8, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f32 v20, null, v9, v9, v17
	v_ashrrev_i32_e32 v28, 31, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[23:24], 2, v[27:28]
	v_add_co_u32 v23, vcc_lo, s16, v23
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v24, vcc_lo, s17, v24, vcc_lo
	global_load_b32 v4, v[23:24], off
	global_load_b32 v23, v[0:1], off
	v_rcp_f32_e32 v24, v20
	s_waitcnt_depctr 0xfff
	v_fma_f32 v27, -v20, v24, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v24, v27, v24
	v_div_scale_f32 v27, vcc_lo, v17, v9, v17
	v_mul_f32_e32 v28, v27, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v29, -v20, v28, v27
	v_fmac_f32_e32 v28, v29, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v20, -v20, v28, v27
	v_div_fmas_f32 v20, v20, v24, v28
	v_div_scale_f32 v24, null, v21, v21, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v17, v20, v9, v17
	v_mul_f32_e32 v20, 0x4f800000, v17
	v_cmp_gt_f32_e64 s3, 0xf800000, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v20, v17, v20, s3
	v_rcp_f32_e32 v17, v24
	v_sqrt_f32_e32 v27, v20
	s_waitcnt_depctr 0xfff
	v_fma_f32 v28, -v24, v17, 1.0
	v_add_nc_u32_e32 v29, -1, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v17, v28, v17 :: v_dual_add_nc_u32 v30, 1, v27
	v_div_scale_f32 v28, s4, v19, v21, v19
	v_fma_f32 v31, -v29, v27, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v33, -v30, v27, v20
	v_cmp_ge_f32_e32 vcc_lo, 0, v31
	v_cndmask_b32_e32 v27, v27, v29, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_f32_e32 vcc_lo, 0, v33
	v_dual_cndmask_b32 v27, v27, v30 :: v_dual_mul_f32 v32, v28, v17
	s_mov_b32 vcc_lo, s2
	s_mov_b32 s2, exec_lo
	v_div_fmas_f32 v22, v26, v22, v25
	s_mov_b32 vcc_lo, s4
	v_fma_f32 v29, -v24, v32, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v18, v22, v5, v18
	v_dual_fmac_f32 v32, v29, v17 :: v_dual_mul_f32 v29, 0x37800000, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v24, -v24, v32, v28
	v_div_fmas_f32 v17, v24, v17, v32
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v24, v27, v29, s3
	v_cmp_class_f32_e64 vcc_lo, v20, 0x260
	v_div_fixup_f32 v17, v17, v21, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v5, v24, v20, vcc_lo
                                        ; implicit-def: $vgpr24
	v_cmpx_ngt_f32_e32 v18, v17
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB3_37
; %bb.36:                               ;   in Loop: Header=BB3_4 Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v24, v18, v5
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr17
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v23, v24, v4
                                        ; implicit-def: $vgpr4
.LBB3_37:                               ; %Flow
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_and_not1_saveexec_b32 s2, s2
	s_cbranch_execz .LBB3_39
; %bb.38:                               ;   in Loop: Header=BB3_4 Depth=1
	v_mul_f32_e32 v24, v5, v17
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v23, v24, v4
.LBB3_39:                               ; %Flow2488
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
.LBB3_40:                               ; %Flow2516
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s26
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s26, s3, exec_lo
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr17
.LBB3_41:                               ; %Flow2515
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_and_not1_saveexec_b32 s25, s25
	s_cbranch_execz .LBB3_47
; %bb.42:                               ;   in Loop: Header=BB3_4 Depth=1
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[23:24], null, v17, s9, s[14:15]
	v_dual_sub_f32 v17, v21, v18 :: v_dual_sub_f32 v22, v22, v19
	v_sub_f32_e32 v18, v14, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v21, v17, v17, 1.0
	v_mad_u64_u32 v[24:25], null, v23, s8, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v21, v15, v21
	v_ashrrev_i32_e32 v25, 31, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[23:24], 2, v[24:25]
	v_add_co_u32 v23, vcc_lo, s16, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v24, vcc_lo, s17, v24, vcc_lo
	global_load_b32 v5, v[23:24], off
	global_load_b32 v23, v[0:1], off
	v_div_scale_f32 v24, null, v9, v9, v21
	v_rcp_f32_e32 v25, v24
	s_waitcnt_depctr 0xfff
	v_fma_f32 v26, -v24, v25, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v25, v26, v25
	v_div_scale_f32 v26, vcc_lo, v21, v9, v21
	v_mul_f32_e32 v27, v26, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v28, -v24, v27, v26
	v_fmac_f32_e32 v27, v28, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v24, -v24, v27, v26
	v_div_fmas_f32 v24, v24, v25, v27
	v_cvt_f32_i32_e32 v25, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v21, v24, v9, v21
	v_sub_f32_e32 v24, v25, v19
	v_div_scale_f32 v25, null, v17, v17, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v19, 0x4f800000, v21
	v_cmp_gt_f32_e64 s2, 0xf800000, v21
	v_div_scale_f32 v26, null, v22, v22, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v21, v21, v19, s2
	v_rcp_f32_e32 v19, v25
	v_rcp_f32_e32 v27, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_3)
	v_sqrt_f32_e32 v28, v21
	v_fma_f32 v29, -v25, v19, 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v30, -v26, v27, 1.0
	v_add_nc_u32_e32 v31, -1, v28
	v_fmac_f32_e32 v19, v29, v19
	v_div_scale_f32 v29, vcc_lo, v18, v17, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v27, v30, v27
	v_div_scale_f32 v30, s3, v24, v22, v24
	v_add_nc_u32_e32 v32, 1, v28
	v_fma_f32 v34, -v31, v28, v21
	v_mul_f32_e32 v33, v29, v19
	v_mul_f32_e32 v35, v30, v27
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v36, -v32, v28, v21
	v_cmp_ge_f32_e64 s4, 0, v34
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v37, -v25, v33, v29
	v_cndmask_b32_e64 v28, v28, v31, s4
	v_fma_f32 v31, -v26, v35, v30
	v_cmp_lt_f32_e64 s4, 0, v36
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v33, v37, v19
	v_fmac_f32_e32 v35, v31, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v28, v28, v32, s4
	v_fma_f32 v25, -v25, v33, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v26, -v26, v35, v30
	v_mul_f32_e32 v29, 0x37800000, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v19, v25, v19, v33
	s_mov_b32 vcc_lo, s3
	v_div_fmas_f32 v25, v26, v27, v35
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e64 v26, v28, v29, s2
	v_cmp_class_f32_e64 vcc_lo, v21, 0x260
	v_div_fixup_f32 v19, v19, v17, v18
	s_mov_b32 s2, exec_lo
	v_div_fixup_f32 v18, v25, v22, v24
                                        ; implicit-def: $vgpr24
	v_cndmask_b32_e32 v17, v26, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_ngt_f32_e32 v19, v18
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB3_44
; %bb.43:                               ;   in Loop: Header=BB3_4 Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v24, v19, v17
                                        ; implicit-def: $vgpr17
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr4
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v23, v24, v5
                                        ; implicit-def: $vgpr5
.LBB3_44:                               ; %Flow2489
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_and_not1_saveexec_b32 s2, s2
	s_cbranch_execz .LBB3_46
; %bb.45:                               ;   in Loop: Header=BB3_4 Depth=1
	v_mul_f32_e32 v21, v17, v18
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v23, v21, v5
	v_mad_u64_u32 v[21:22], null, v20, s9, s[14:15]
	global_store_b32 v[0:1], v23, off
	global_load_b32 v24, v[2:3], off
	v_mad_u64_u32 v[22:23], null, v21, s8, v[4:5]
	v_ashrrev_i32_e32 v23, 31, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[22:23]
	v_add_co_u32 v4, vcc_lo, s16, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s17, v5, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v24, v17, v18
	global_store_b32 v[2:3], v24, off
	global_load_b32 v4, v[4:5], off
	global_load_b32 v23, v[0:1], off
	v_sub_f32_e32 v5, v19, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v24, v17, v5
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v23, v24, v4
.LBB3_46:                               ; %Flow2490
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s26, s26, exec_lo
.LBB3_47:                               ; %Flow2517
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s25
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s4, s26, exec_lo
                                        ; implicit-def: $vgpr17
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $vgpr4
.LBB3_48:                               ; %Flow2514
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_and_not1_saveexec_b32 s24, s24
	s_cbranch_execz .LBB3_52
; %bb.49:                               ;   in Loop: Header=BB3_4 Depth=1
	v_cmp_lt_i32_e32 vcc_lo, -1, v17
	v_cmp_gt_i32_e64 s2, s10, v17
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s2
	s_mov_b32 s2, s4
	s_and_saveexec_b32 s25, s3
	s_xor_b32 s25, exec_lo, s25
	s_cbranch_execz .LBB3_51
; %bb.50:                               ;   in Loop: Header=BB3_4 Depth=1
	v_mad_u64_u32 v[19:20], null, v17, s9, s[14:15]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[22:23], null, v19, s8, v[4:5]
	v_ashrrev_i32_e32 v23, 31, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[22:23]
	v_add_co_u32 v4, vcc_lo, s16, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, s17, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	global_load_b32 v23, v[0:1], off
	v_sub_f32_e32 v5, v21, v18
	v_fma_f32 v17, v5, v5, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v17, v15, v17
	v_div_scale_f32 v19, null, v9, v9, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v20, v19
	s_waitcnt_depctr 0xfff
	v_fma_f32 v21, -v19, v20, 1.0
	v_fmac_f32_e32 v20, v21, v20
	v_div_scale_f32 v21, vcc_lo, v17, v9, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v22, v21, v20
	v_fma_f32 v24, -v19, v22, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v22, v24, v20
	v_fma_f32 v19, -v19, v22, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v19, v19, v20, v22
	v_div_fixup_f32 v17, v19, v9, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v19, 0x4f800000, v17
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v17
	v_dual_sub_f32 v18, v14, v18 :: v_dual_cndmask_b32 v17, v17, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f32 v20, null, v5, v5, v18
	v_sqrt_f32_e32 v21, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v19, v20
	s_waitcnt_depctr 0xfff
	v_fma_f32 v22, -v20, v19, 1.0
	v_dual_fmac_f32 v19, v22, v19 :: v_dual_add_nc_u32 v24, -1, v21
	v_div_scale_f32 v22, s2, v18, v5, v18
	v_add_nc_u32_e32 v25, 1, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v26, -v24, v21, v17
	v_mul_f32_e32 v28, v22, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v27, -v25, v21, v17
	v_cmp_ge_f32_e64 s3, 0, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v21, v21, v24, s3
	v_cmp_lt_f32_e64 s3, 0, v27
	v_fma_f32 v24, -v20, v28, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v21, v21, v25, s3
	v_fmac_f32_e32 v28, v24, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v24, 0x37800000, v21
	v_cndmask_b32_e32 v21, v21, v24, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_fma_f32 v20, -v20, v28, v22
	s_mov_b32 vcc_lo, s2
	s_or_b32 s2, s4, exec_lo
	v_div_fmas_f32 v19, v20, v19, v28
	v_cmp_class_f32_e64 vcc_lo, v17, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v5, v19, v5, v18
	v_cndmask_b32_e32 v17, v21, v17, vcc_lo
	v_mul_f32_e32 v24, v5, v17
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v23, v24, v4
.LBB3_51:                               ; %Flow2519
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s25
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s3, s4, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_or_b32 s4, s3, s2
.LBB3_52:                               ; %Flow2518
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s24
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s2, s4, exec_lo
.LBB3_53:                               ; %Flow2513
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s13, s2, exec_lo
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr17
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr22
.LBB3_54:                               ; %Flow2512
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_and_not1_saveexec_b32 s23, s23
	s_cbranch_execz .LBB3_82
; %bb.55:                               ;   in Loop: Header=BB3_4 Depth=1
	s_mov_b32 s4, s13
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
	s_mov_b32 s2, exec_lo
	v_cmpx_ne_u32_e64 v20, v17
	s_xor_b32 s24, exec_lo, s2
	s_cbranch_execz .LBB3_77
; %bb.56:                               ;   in Loop: Header=BB3_4 Depth=1
	v_cmp_gt_i32_e32 vcc_lo, 1, v20
	v_cmp_le_i32_e64 s2, s10, v20
	s_mov_b32 s26, s13
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s25, exec_lo, s3
	s_cbranch_execz .LBB3_70
; %bb.57:                               ;   in Loop: Header=BB3_4 Depth=1
	s_mov_b32 s26, exec_lo
	v_cmpx_eq_u32_e32 0, v20
	s_cbranch_execz .LBB3_63
; %bb.58:                               ;   in Loop: Header=BB3_4 Depth=1
	global_load_b32 v23, v[0:1], off
	v_sub_f32_e32 v24, v21, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v25, v24, v24, 1.0
	v_mul_f32_e32 v25, v15, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v26, null, v9, v9, v25
	v_rcp_f32_e32 v27, v26
	s_waitcnt_depctr 0xfff
	v_fma_f32 v28, -v26, v27, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v27, v28, v27
	v_div_scale_f32 v28, vcc_lo, v25, v9, v25
	v_mul_f32_e32 v29, v28, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v30, -v26, v29, v28
	v_fmac_f32_e32 v29, v30, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v26, -v26, v29, v28
	v_div_fmas_f32 v26, v26, v27, v29
	s_waitcnt vmcnt(2)
	v_cvt_f32_i32_e32 v27, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v25, v26, v9, v25
	v_dual_sub_f32 v26, v27, v18 :: v_dual_sub_f32 v27, v22, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v28, 0x4f800000, v25
	v_cmp_gt_f32_e64 s2, 0xf800000, v25
	v_div_scale_f32 v29, null, v24, v24, v26
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_scale_f32 v30, null, v27, v27, -v19
	v_cndmask_b32_e64 v28, v25, v28, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v25, v29
	v_rcp_f32_e32 v31, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_3)
	v_sqrt_f32_e32 v32, v28
	v_fma_f32 v33, -v29, v25, 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v34, -v30, v31, 1.0
	v_add_nc_u32_e32 v36, 1, v32
	v_add_nc_u32_e32 v35, -1, v32
	v_fmac_f32_e32 v25, v33, v25
	v_div_scale_f32 v33, vcc_lo, v26, v24, v26
	v_fmac_f32_e32 v31, v34, v31
	v_div_scale_f32 v34, s3, -v19, v27, -v19
	v_fma_f32 v38, -v35, v32, v28
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v37, v33, v25
	v_fma_f32 v40, -v36, v32, v28
	v_mul_f32_e32 v39, v34, v31
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_ge_f32_e64 s4, 0, v38
	v_fma_f32 v41, -v29, v37, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v32, v32, v35, s4
	v_fma_f32 v35, -v30, v39, v34
	v_cmp_lt_f32_e64 s4, 0, v40
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v37, v41, v25
	v_fmac_f32_e32 v39, v35, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v32, v32, v36, s4
	v_fma_f32 v29, -v29, v37, v33
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v30, -v30, v39, v34
	v_mul_f32_e32 v33, 0x37800000, v32
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v25, v29, v25, v37
	s_mov_b32 vcc_lo, s3
	v_div_fmas_f32 v29, v30, v31, v39
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e64 v30, v32, v33, s2
	v_cmp_class_f32_e64 vcc_lo, v28, 0x260
	v_div_fixup_f32 v25, v25, v24, v26
	s_mov_b32 s2, exec_lo
	v_div_fixup_f32 v26, v29, v27, -v19
                                        ; implicit-def: $vgpr27
	v_cndmask_b32_e32 v24, v30, v28, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_ngt_f32_e32 v25, v26
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB3_60
; %bb.59:                               ;   in Loop: Header=BB3_4 Depth=1
	v_dual_sub_f32 v26, 1.0, v26 :: v_dual_add_nc_u32 v27, s12, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v28, 31, v27
	v_lshlrev_b64 v[27:28], 2, v[27:28]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v27, vcc_lo, s16, v27
	v_add_co_ci_u32_e32 v28, vcc_lo, s17, v28, vcc_lo
	global_load_b32 v25, v[27:28], off
	v_mul_f32_e32 v27, v24, v26
                                        ; implicit-def: $vgpr26
                                        ; implicit-def: $vgpr24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v23, v27, v25
                                        ; implicit-def: $vgpr25
.LBB3_60:                               ; %Flow2504
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_and_not1_saveexec_b32 s2, s2
	s_cbranch_execz .LBB3_62
; %bb.61:                               ;   in Loop: Header=BB3_4 Depth=1
	v_add_nc_u32_e32 v27, s12, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v28, 31, v27
	v_lshlrev_b64 v[27:28], 2, v[27:28]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v27, vcc_lo, s16, v27
	v_add_co_ci_u32_e32 v28, vcc_lo, s17, v28, vcc_lo
	global_load_b32 v27, v[27:28], off
	v_dual_sub_f32 v28, v25, v26 :: v_dual_sub_f32 v25, 1.0, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v26, v24, v28
	s_waitcnt vmcnt(0)
	v_dual_fmac_f32 v23, v26, v27 :: v_dual_add_nc_u32 v26, s12, v5
	global_store_b32 v[0:1], v23, off
	global_load_b32 v23, v[2:3], off
	v_ashrrev_i32_e32 v27, 31, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[26:27], 2, v[26:27]
	v_add_co_u32 v26, vcc_lo, s16, v26
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v27, vcc_lo, s17, v27, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v23, v24, v28
	global_store_b32 v[2:3], v23, off
	global_load_b32 v26, v[26:27], off
	global_load_b32 v23, v[0:1], off
	v_mul_f32_e32 v27, v25, v24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v23, v27, v26
.LBB3_62:                               ; %.sink.split2411
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v23, off
	global_load_b32 v23, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v23, v27, v23
	global_store_b32 v[2:3], v23, off
.LBB3_63:                               ; %Flow2505
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s26
	s_mov_b32 s2, s13
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
	s_mov_b32 s3, exec_lo
	v_cmpx_eq_u32_e64 s10, v20
	s_xor_b32 s26, exec_lo, s3
	s_cbranch_execz .LBB3_69
; %bb.64:                               ;   in Loop: Header=BB3_4 Depth=1
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[23:24], null, v17, s9, s[14:15]
	v_sub_f32_e32 v20, v21, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v21, v20, v20, 1.0
	v_mul_lo_u32 v17, v23, s8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v21, v15, v21
	v_add_nc_u32_e32 v23, v17, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v24, 31, v23
	v_lshlrev_b64 v[23:24], 2, v[23:24]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v23, vcc_lo, s16, v23
	v_add_co_ci_u32_e32 v24, vcc_lo, s17, v24, vcc_lo
	global_load_b32 v4, v[23:24], off
	global_load_b32 v23, v[0:1], off
	v_div_scale_f32 v24, null, v9, v9, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v25, v24
	s_waitcnt_depctr 0xfff
	v_fma_f32 v26, -v24, v25, 1.0
	v_fmac_f32_e32 v25, v26, v25
	v_div_scale_f32 v26, vcc_lo, v21, v9, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v27, v26, v25
	v_fma_f32 v28, -v24, v27, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v27, v28, v25
	v_fma_f32 v24, -v24, v27, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v24, v24, v25, v27
	v_cvt_f32_i32_e32 v25, v5
	v_div_fixup_f32 v21, v24, v9, v21
	v_sub_f32_e32 v24, v13, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v19, v22, v19 :: v_dual_sub_f32 v18, v25, v18
	v_mul_f32_e32 v22, 0x4f800000, v21
	v_cmp_gt_f32_e64 s2, 0xf800000, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f32 v25, null, v20, v20, v18
	v_cndmask_b32_e64 v21, v21, v22, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v22, v25
	v_sqrt_f32_e32 v28, v21
	s_waitcnt_depctr 0xfff
	v_fma_f32 v29, -v25, v22, 1.0
	v_add_nc_u32_e32 v32, 1, v28
	v_div_scale_f32 v26, null, v19, v19, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v22, v29, v22 :: v_dual_add_nc_u32 v31, -1, v28
	v_div_scale_f32 v29, vcc_lo, v18, v20, v18
	v_rcp_f32_e32 v27, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v34, -v31, v28, v21
	v_fma_f32 v36, -v32, v28, v21
	v_mul_f32_e32 v33, v29, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ge_f32_e64 s4, 0, v34
	v_fma_f32 v37, -v25, v33, v29
	s_waitcnt_depctr 0xfff
	v_fma_f32 v30, -v26, v27, 1.0
	v_cndmask_b32_e64 v28, v28, v31, s4
	v_cmp_lt_f32_e64 s4, 0, v36
	v_fmac_f32_e32 v33, v37, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v27, v30, v27
	v_div_scale_f32 v30, s3, v24, v19, v24
	v_cndmask_b32_e64 v28, v28, v32, s4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v25, -v25, v33, v29
	v_mul_f32_e32 v35, v30, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v29, 0x37800000, v28
	v_div_fmas_f32 v22, v25, v22, v33
	s_mov_b32 vcc_lo, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v31, -v26, v35, v30
	v_div_fixup_f32 v20, v22, v20, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v35, v31, v27
	v_fma_f32 v26, -v26, v35, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v25, v26, v27, v35
	v_cndmask_b32_e64 v26, v28, v29, s2
	v_cmp_class_f32_e64 vcc_lo, v21, 0x260
	s_mov_b32 s2, exec_lo
	v_div_fixup_f32 v19, v25, v19, v24
                                        ; implicit-def: $vgpr24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v18, v26, v21, vcc_lo
	v_cmpx_ngt_f32_e32 v20, v19
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB3_66
; %bb.65:                               ;   in Loop: Header=BB3_4 Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v21, v20, v18
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v23, v21, v4
	v_add_nc_u32_e32 v4, v17, v5
	global_store_b32 v[0:1], v23, off
	global_load_b32 v21, v[2:3], off
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v4, vcc_lo, s16, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s17, v5, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v21, v20, v18
	global_store_b32 v[2:3], v21, off
	global_load_b32 v4, v[4:5], off
	global_load_b32 v23, v[0:1], off
	v_sub_f32_e32 v5, v19, v20
                                        ; implicit-def: $vgpr19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v24, v18, v5
                                        ; implicit-def: $vgpr18
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v23, v24, v4
                                        ; implicit-def: $vgpr4
.LBB3_66:                               ; %Flow2502
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_and_not1_saveexec_b32 s2, s2
	s_cbranch_execz .LBB3_68
; %bb.67:                               ;   in Loop: Header=BB3_4 Depth=1
	v_mul_f32_e32 v24, v18, v19
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v23, v24, v4
.LBB3_68:                               ; %Flow2503
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s2, s13, exec_lo
.LBB3_69:                               ; %Flow2523
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s26
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s3, s13, exec_lo
	s_and_b32 s2, s2, exec_lo
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr17
	s_or_b32 s26, s3, s2
.LBB3_70:                               ; %Flow2522
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_and_not1_saveexec_b32 s25, s25
	s_cbranch_execz .LBB3_76
; %bb.71:                               ;   in Loop: Header=BB3_4 Depth=1
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[23:24], null, v17, s9, s[14:15]
	v_dual_sub_f32 v17, v21, v18 :: v_dual_sub_f32 v22, v22, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v21, v17, v17, 1.0
	v_mul_lo_u32 v27, v23, s8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v21, v15, v21
	v_add_nc_u32_e32 v23, v27, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v24, 31, v23
	v_lshlrev_b64 v[23:24], 2, v[23:24]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v23, vcc_lo, s16, v23
	v_add_co_ci_u32_e32 v24, vcc_lo, s17, v24, vcc_lo
	global_load_b32 v25, v[23:24], off
	global_load_b32 v26, v[0:1], off
	v_div_scale_f32 v23, null, v9, v9, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v24, v23
	s_waitcnt_depctr 0xfff
	v_fma_f32 v28, -v23, v24, 1.0
	v_fmac_f32_e32 v24, v28, v24
	v_div_scale_f32 v28, vcc_lo, v21, v9, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v29, v28, v24
	v_fma_f32 v30, -v23, v29, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v29, v30, v24
	v_fma_f32 v23, -v23, v29, v28
	v_cvt_f32_i32_e32 v28, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v23, v23, v24, v29
	v_cvt_f32_i32_e32 v24, v5
	v_div_fixup_f32 v21, v23, v9, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v18, v24, v18
	v_sub_f32_e32 v23, v28, v19
	v_mul_f32_e32 v19, 0x4f800000, v21
	v_cmp_gt_f32_e64 s2, 0xf800000, v21
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_scale_f32 v24, null, v17, v17, v18
	v_div_scale_f32 v28, null, v22, v22, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v21, v21, v19, s2
	v_rcp_f32_e32 v19, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v29, v28
	v_sqrt_f32_e32 v30, v21
	s_delay_alu instid0(TRANS32_DEP_3)
	v_fma_f32 v31, -v24, v19, 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v32, -v28, v29, 1.0
	v_add_nc_u32_e32 v34, 1, v30
	v_add_nc_u32_e32 v33, -1, v30
	v_fmac_f32_e32 v19, v31, v19
	v_div_scale_f32 v31, vcc_lo, v18, v17, v18
	v_fmac_f32_e32 v29, v32, v29
	v_div_scale_f32 v32, s3, v23, v22, v23
	v_fma_f32 v36, -v33, v30, v21
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v35, v31, v19
	v_fma_f32 v38, -v34, v30, v21
	v_mul_f32_e32 v37, v32, v29
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_ge_f32_e64 s4, 0, v36
	v_fma_f32 v39, -v24, v35, v31
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v30, v30, v33, s4
	v_fma_f32 v33, -v28, v37, v32
	v_cmp_lt_f32_e64 s4, 0, v38
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v35, v39, v19
	v_fmac_f32_e32 v37, v33, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v30, v30, v34, s4
	v_fma_f32 v24, -v24, v35, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v28, -v28, v37, v32
	v_mul_f32_e32 v31, 0x37800000, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v19, v24, v19, v35
	s_mov_b32 vcc_lo, s3
	v_div_fmas_f32 v24, v28, v29, v37
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e64 v28, v30, v31, s2
	v_cmp_class_f32_e64 vcc_lo, v21, 0x260
	v_div_fixup_f32 v19, v19, v17, v18
	s_mov_b32 s2, exec_lo
	v_div_fixup_f32 v18, v24, v22, v23
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
	v_cndmask_b32_e32 v17, v28, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_ngt_f32_e32 v19, v18
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB3_73
; %bb.72:                               ;   in Loop: Header=BB3_4 Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v4, v19, v17 :: v_dual_sub_f32 v23, v18, v19
	v_add_nc_u32_e32 v21, v27, v5
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v26, v4, v25
                                        ; implicit-def: $vgpr25
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v22, 31, v21
	global_store_b32 v[0:1], v26, off
	global_load_b32 v4, v[2:3], off
	v_lshlrev_b64 v[21:22], 2, v[21:22]
                                        ; implicit-def: $vgpr26
	v_add_co_u32 v21, vcc_lo, s16, v21
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v22, vcc_lo, s17, v22, vcc_lo
	s_waitcnt vmcnt(0)
	v_dual_fmac_f32 v4, v19, v17 :: v_dual_mul_f32 v19, v17, v23
	global_store_b32 v[2:3], v4, off
	global_load_b32 v4, v[21:22], off
	global_load_b32 v21, v[0:1], off
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v21, v19, v4
	global_store_b32 v[0:1], v21, off
	global_load_b32 v24, v[2:3], off
	v_mad_u64_u32 v[21:22], null, v20, s9, s[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[19:20], null, v21, s8, v[5:6]
	v_ashrrev_i32_e32 v20, 31, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[19:20]
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr20
	v_add_co_u32 v4, vcc_lo, s16, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s17, v5, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v24, v17, v23
	global_store_b32 v[2:3], v24, off
	global_load_b32 v4, v[4:5], off
	global_load_b32 v23, v[0:1], off
	v_sub_f32_e32 v5, 1.0, v18
                                        ; implicit-def: $vgpr18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v24, v17, v5
                                        ; implicit-def: $vgpr17
                                        ; implicit-def: $vgpr5
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v23, v24, v4
                                        ; implicit-def: $vgpr4
.LBB3_73:                               ; %Flow2506
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_and_not1_saveexec_b32 s2, s2
	s_cbranch_execz .LBB3_75
; %bb.74:                               ;   in Loop: Header=BB3_4 Depth=1
	v_mul_f32_e32 v21, v17, v18
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v26, v21, v25
	v_mad_u64_u32 v[21:22], null, v20, s9, s[14:15]
	global_store_b32 v[0:1], v26, off
	global_load_b32 v23, v[2:3], off
	v_mul_lo_u32 v22, v21, s8
	v_add_nc_u32_e32 v20, v22, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v21, 31, v20
	v_lshlrev_b64 v[20:21], 2, v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v20, vcc_lo, s16, v20
	v_add_co_ci_u32_e32 v21, vcc_lo, s17, v21, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v23, v17, v18
	v_sub_f32_e32 v18, v19, v18
	global_store_b32 v[2:3], v23, off
	global_load_b32 v4, v[20:21], off
	global_load_b32 v20, v[0:1], off
	v_mul_f32_e32 v21, v17, v18
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v20, v21, v4
	v_add_nc_u32_e32 v4, v22, v5
	global_store_b32 v[0:1], v20, off
	global_load_b32 v20, v[2:3], off
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s16, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s17, v5, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v20, v17, v18
	global_store_b32 v[2:3], v20, off
	global_load_b32 v4, v[4:5], off
	global_load_b32 v23, v[0:1], off
	v_sub_f32_e32 v5, 1.0, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v24, v5, v17
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v23, v24, v4
.LBB3_75:                               ; %Flow2507
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s26, s26, exec_lo
.LBB3_76:                               ; %Flow2524
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s25
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s2, s13, exec_lo
	s_and_b32 s3, s26, exec_lo
                                        ; implicit-def: $vgpr17
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr4
	s_or_b32 s4, s2, s3
.LBB3_77:                               ; %Flow2521
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_and_not1_saveexec_b32 s24, s24
	s_cbranch_execz .LBB3_81
; %bb.78:                               ;   in Loop: Header=BB3_4 Depth=1
	v_cmp_lt_i32_e32 vcc_lo, -1, v17
	v_cmp_gt_i32_e64 s2, s10, v17
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s2
	s_mov_b32 s2, s4
	s_and_saveexec_b32 s25, s3
	s_xor_b32 s25, exec_lo, s25
	s_cbranch_execz .LBB3_80
; %bb.79:                               ;   in Loop: Header=BB3_4 Depth=1
	v_mad_u64_u32 v[19:20], null, v17, s9, s[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v17, v19, s8
	s_waitcnt vmcnt(1)
	v_add_nc_u32_e32 v19, v17, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v20, 31, v19
	v_lshlrev_b64 v[19:20], 2, v[19:20]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v19, vcc_lo, s16, v19
	v_add_co_ci_u32_e32 v20, vcc_lo, s17, v20, vcc_lo
	global_load_b32 v4, v[0:1], off
	global_load_b32 v19, v[19:20], off
	v_sub_f32_e32 v20, v21, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v21, v20, v20, 1.0
	v_mul_f32_e32 v21, v15, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_div_scale_f32 v22, null, v9, v9, v21
	v_div_scale_f32 v25, vcc_lo, v21, v9, v21
	s_waitcnt vmcnt(2)
	v_rcp_f32_e32 v23, v22
	s_waitcnt_depctr 0xfff
	v_fma_f32 v24, -v22, v23, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v23, v24, v23
	v_mul_f32_e32 v24, v25, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v26, -v22, v24, v25
	v_fmac_f32_e32 v24, v26, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f32 v22, -v22, v24, v25
	v_cvt_f32_i32_e32 v25, v5
	v_sub_f32_e32 v18, v25, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v22, v22, v23, v24
	v_div_scale_f32 v26, vcc_lo, v18, v20, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v21, v22, v9, v21
	v_div_scale_f32 v22, null, v20, v20, v18
	v_mul_f32_e32 v23, 0x4f800000, v21
	v_cmp_gt_f32_e64 s2, 0xf800000, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v24, v22
	v_cndmask_b32_e64 v21, v21, v23, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sqrt_f32_e32 v23, v21
	s_waitcnt_depctr 0xfff
	v_fma_f32 v25, -v22, v24, 1.0
	v_dual_fmac_f32 v24, v25, v24 :: v_dual_add_nc_u32 v25, -1, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v27, v26, v24 :: v_dual_add_nc_u32 v28, 1, v23
	v_fma_f32 v29, -v25, v23, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v30, -v22, v27, v26
	v_fma_f32 v31, -v28, v23, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s3, 0, v29
	v_cndmask_b32_e64 v23, v23, v25, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s3, 0, v31
	v_cndmask_b32_e64 v23, v23, v28, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v25, 0x37800000, v23
	v_cndmask_b32_e64 v23, v23, v25, s2
	v_fmac_f32_e32 v27, v30, v24
	s_or_b32 s2, s4, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v22, -v22, v27, v26
	v_div_fmas_f32 v22, v22, v24, v27
	v_cmp_class_f32_e64 vcc_lo, v21, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v18, v22, v20, v18
	v_cndmask_b32_e32 v20, v23, v21, vcc_lo
	v_mul_f32_e32 v21, v18, v20
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v21, v19
	global_store_b32 v[0:1], v4, off
	global_load_b32 v19, v[2:3], off
	v_add_nc_u32_e32 v4, v17, v5
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v4, vcc_lo, s16, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s17, v5, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v19, v18, v20
	global_store_b32 v[2:3], v19, off
	global_load_b32 v4, v[4:5], off
	global_load_b32 v23, v[0:1], off
	v_sub_f32_e32 v5, 1.0, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v24, v5, v20
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v23, v24, v4
.LBB3_80:                               ; %Flow2526
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s25
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s3, s4, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_or_b32 s4, s3, s2
.LBB3_81:                               ; %Flow2525
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s24
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s2, s13, exec_lo
	s_and_b32 s3, s4, exec_lo
	s_or_b32 s13, s2, s3
.LBB3_82:                               ; %Flow2520
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s23
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s4, s13, exec_lo
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr17
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr22
.LBB3_83:                               ; %Flow2511
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_and_not1_saveexec_b32 s13, s22
	s_cbranch_execz .LBB3_101
; %bb.84:                               ;   in Loop: Header=BB3_4 Depth=1
	s_waitcnt vmcnt(1)
	v_cmp_lt_i32_e32 vcc_lo, -1, v4
	v_cmp_gt_i32_e64 s2, s8, v4
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s3, vcc_lo, s2
	s_mov_b32 s2, s4
	s_and_saveexec_b32 s22, s3
	s_cbranch_execz .LBB3_100
; %bb.85:                               ;   in Loop: Header=BB3_4 Depth=1
	s_mov_b32 s3, s4
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
	s_mov_b32 s2, exec_lo
	v_cmpx_ne_u32_e64 v20, v17
	s_xor_b32 s23, exec_lo, s2
	s_cbranch_execz .LBB3_95
; %bb.86:                               ;   in Loop: Header=BB3_4 Depth=1
	v_cmp_gt_i32_e32 vcc_lo, 1, v20
	v_cmp_le_i32_e64 s2, s10, v20
	s_mov_b32 s25, s4
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s24, exec_lo, s3
	s_cbranch_execz .LBB3_92
; %bb.87:                               ;   in Loop: Header=BB3_4 Depth=1
	s_mov_b32 s25, exec_lo
	v_cmpx_eq_u32_e32 0, v20
	s_cbranch_execz .LBB3_89
; %bb.88:                               ;   in Loop: Header=BB3_4 Depth=1
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v23, s12, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v24, 31, v23
	v_lshlrev_b64 v[23:24], 2, v[23:24]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v23, vcc_lo, s16, v23
	v_add_co_ci_u32_e32 v24, vcc_lo, s17, v24, vcc_lo
	global_load_b32 v5, v[23:24], off
	global_load_b32 v23, v[0:1], off
	v_sub_f32_e32 v24, v21, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v24, v24, v24, 1.0
	v_mul_f32_e32 v24, v15, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v25, null, v9, v9, v24
	v_rcp_f32_e32 v26, v25
	s_waitcnt_depctr 0xfff
	v_fma_f32 v27, -v25, v26, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v26, v27, v26
	v_div_scale_f32 v27, vcc_lo, v24, v9, v24
	v_mul_f32_e32 v28, v27, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v29, -v25, v28, v27
	v_fmac_f32_e32 v28, v29, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v25, -v25, v28, v27
	v_div_fmas_f32 v25, v25, v26, v28
	v_sub_f32_e32 v26, v22, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v24, v25, v9, v24
	v_div_scale_f32 v25, null, v26, v26, -v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v27, 0x4f800000, v24
	v_cmp_gt_f32_e64 s2, 0xf800000, v24
	v_rcp_f32_e32 v28, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v24, v24, v27, s2
	v_sqrt_f32_e32 v27, v24
	s_waitcnt_depctr 0xfff
	v_fma_f32 v29, -v25, v28, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v28, v29, v28
	v_div_scale_f32 v29, vcc_lo, -v19, v26, -v19
	v_add_nc_u32_e32 v30, -1, v27
	v_dual_mul_f32 v32, v29, v28 :: v_dual_add_nc_u32 v31, 1, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v33, -v30, v27, v24
	v_fma_f32 v34, -v31, v27, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v35, -v25, v32, v29
	v_cmp_ge_f32_e64 s3, 0, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v32, v35, v28
	v_cndmask_b32_e64 v27, v27, v30, s3
	v_cmp_lt_f32_e64 s3, 0, v34
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v25, -v25, v32, v29
	v_cndmask_b32_e64 v27, v27, v31, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v25, v25, v28, v32
	v_cmp_class_f32_e64 vcc_lo, v24, 0x260
	v_mul_f32_e32 v29, 0x37800000, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v25, v25, v26, -v19
	v_cndmask_b32_e64 v27, v27, v29, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v25, 1.0, v25 :: v_dual_cndmask_b32 v24, v27, v24
	v_mul_f32_e32 v26, v24, v25
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v23, v26, v5
	global_store_b32 v[0:1], v23, off
	global_load_b32 v5, v[2:3], off
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v5, v24, v25
	global_store_b32 v[2:3], v5, off
.LBB3_89:                               ;   in Loop: Header=BB3_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s25
	s_mov_b32 s2, s4
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
	s_mov_b32 s3, exec_lo
	v_cmpx_eq_u32_e64 s10, v20
	s_xor_b32 s25, exec_lo, s3
	s_cbranch_execz .LBB3_91
; %bb.90:                               ;   in Loop: Header=BB3_4 Depth=1
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[23:24], null, v17, s9, s[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[24:25], null, v23, s8, v[4:5]
	v_ashrrev_i32_e32 v25, 31, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[24:25]
	v_add_co_u32 v4, vcc_lo, s16, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, s17, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	global_load_b32 v23, v[0:1], off
	v_sub_f32_e32 v5, v21, v18
	v_fma_f32 v5, v5, v5, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v15, v5
	v_div_scale_f32 v17, null, v9, v9, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v18, v17
	s_waitcnt_depctr 0xfff
	v_fma_f32 v20, -v17, v18, 1.0
	v_fmac_f32_e32 v18, v20, v18
	v_div_scale_f32 v20, vcc_lo, v5, v9, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v21, v20, v18
	v_fma_f32 v24, -v17, v21, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v21, v24, v18
	v_fma_f32 v17, -v17, v21, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v17, v17, v18, v21
	v_sub_f32_e32 v18, v22, v19
	v_div_fixup_f32 v5, v17, v9, v5
	v_sub_f32_e32 v17, v13, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v19, 0x4f800000, v5
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v5
	v_cndmask_b32_e32 v5, v5, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v21, v5
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v24, -1, v21
	v_div_scale_f32 v20, null, v18, v18, v17
	v_fma_f32 v26, -v24, v21, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v19, v20
	v_cmp_ge_f32_e64 s3, 0, v26
	s_waitcnt_depctr 0xfff
	v_fma_f32 v22, -v20, v19, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v19, v22, v19
	v_div_scale_f32 v22, s2, v17, v18, v17
	v_dual_mul_f32 v28, v22, v19 :: v_dual_add_nc_u32 v25, 1, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v27, -v25, v21, v5
	v_cndmask_b32_e64 v21, v21, v24, s3
	v_fma_f32 v24, -v20, v28, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_f32_e64 s3, 0, v27
	v_fmac_f32_e32 v28, v24, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v21, v21, v25, s3
	v_fma_f32 v20, -v20, v28, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v24, 0x37800000, v21
	v_cndmask_b32_e32 v21, v21, v24, vcc_lo
	s_mov_b32 vcc_lo, s2
	s_or_b32 s2, s4, exec_lo
	v_div_fmas_f32 v19, v20, v19, v28
	v_cmp_class_f32_e64 vcc_lo, v5, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v17, v19, v18, v17
	v_cndmask_b32_e32 v5, v21, v5, vcc_lo
	v_mul_f32_e32 v24, v5, v17
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v23, v24, v4
.LBB3_91:                               ; %Flow2531
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s25
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s3, s4, exec_lo
	s_and_b32 s2, s2, exec_lo
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr17
                                        ; implicit-def: $vgpr4
	s_or_b32 s25, s3, s2
.LBB3_92:                               ; %Flow2530
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_and_not1_saveexec_b32 s24, s24
	s_cbranch_execz .LBB3_94
; %bb.93:                               ;   in Loop: Header=BB3_4 Depth=1
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[23:24], null, v17, s9, s[14:15]
	v_sub_f32_e32 v18, v21, v18
	v_sub_f32_e32 v22, v22, v19
	s_or_b32 s25, s25, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v18, v18, v18, 1.0
	v_mad_u64_u32 v[24:25], null, v23, s8, v[4:5]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v18, v15, v18
	v_ashrrev_i32_e32 v25, 31, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f32 v21, null, v9, v9, v18
	v_lshlrev_b64 v[23:24], 2, v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v23, vcc_lo, s16, v23
	v_add_co_ci_u32_e32 v24, vcc_lo, s17, v24, vcc_lo
	v_div_scale_f32 v25, vcc_lo, v18, v9, v18
	global_load_b32 v5, v[0:1], off
	global_load_b32 v17, v[23:24], off
	v_rcp_f32_e32 v23, v21
	s_waitcnt_depctr 0xfff
	v_fma_f32 v24, -v21, v23, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v23, v24, v23
	v_mul_f32_e32 v24, v25, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v26, -v21, v24, v25
	v_fmac_f32_e32 v24, v26, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v21, -v21, v24, v25
	v_cvt_f32_i32_e32 v25, v20
	v_div_fmas_f32 v21, v21, v23, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v19, v25, v19
	v_div_fixup_f32 v18, v21, v9, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_scale_f32 v21, null, v22, v22, v19
	v_div_scale_f32 v26, vcc_lo, v19, v22, v19
	v_mul_f32_e32 v23, 0x4f800000, v18
	v_cmp_gt_f32_e64 s2, 0xf800000, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v24, v21
	v_cndmask_b32_e64 v18, v18, v23, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sqrt_f32_e32 v23, v18
	s_waitcnt_depctr 0xfff
	v_fma_f32 v25, -v21, v24, 1.0
	v_dual_fmac_f32 v24, v25, v24 :: v_dual_add_nc_u32 v25, -1, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v27, v26, v24 :: v_dual_add_nc_u32 v28, 1, v23
	v_fma_f32 v29, -v25, v23, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v30, -v21, v27, v26
	v_fma_f32 v31, -v28, v23, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s3, 0, v29
	v_cndmask_b32_e64 v23, v23, v25, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s3, 0, v31
	v_cndmask_b32_e64 v23, v23, v28, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v25, 0x37800000, v23
	v_cndmask_b32_e64 v23, v23, v25, s2
	v_fmac_f32_e32 v27, v30, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v21, -v21, v27, v26
	v_div_fmas_f32 v21, v21, v24, v27
	v_cmp_class_f32_e64 vcc_lo, v18, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v21, v21, v22, v19
	v_cndmask_b32_e32 v22, v23, v18, vcc_lo
	v_mul_f32_e32 v18, v22, v21
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v5, v18, v17
	v_mad_u64_u32 v[17:18], null, v20, s9, s[14:15]
	global_store_b32 v[0:1], v5, off
	global_load_b32 v23, v[2:3], off
	v_mad_u64_u32 v[18:19], null, v17, s8, v[4:5]
	v_ashrrev_i32_e32 v19, 31, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[18:19]
	v_add_co_u32 v4, vcc_lo, s16, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s17, v5, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v23, v22, v21
	global_store_b32 v[2:3], v23, off
	global_load_b32 v4, v[4:5], off
	global_load_b32 v23, v[0:1], off
	v_sub_f32_e32 v5, 1.0, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v24, v22, v5
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v23, v24, v4
.LBB3_94:                               ; %Flow2532
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s24
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s2, s4, exec_lo
	s_and_b32 s3, s25, exec_lo
                                        ; implicit-def: $vgpr17
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $vgpr4
	s_or_b32 s3, s2, s3
.LBB3_95:                               ; %Flow2529
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_and_not1_saveexec_b32 s23, s23
	s_cbranch_execz .LBB3_99
; %bb.96:                               ;   in Loop: Header=BB3_4 Depth=1
	v_cmp_lt_i32_e32 vcc_lo, -1, v17
	v_cmp_gt_i32_e64 s2, s10, v17
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s25, vcc_lo, s2
	s_mov_b32 s2, s3
	s_and_saveexec_b32 s24, s25
	s_cbranch_execz .LBB3_98
; %bb.97:                               ;   in Loop: Header=BB3_4 Depth=1
	v_mad_u64_u32 v[19:20], null, v17, s9, s[14:15]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[22:23], null, v19, s8, v[4:5]
	v_ashrrev_i32_e32 v23, 31, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[22:23]
	v_add_co_u32 v4, vcc_lo, s16, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, s17, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	global_load_b32 v23, v[0:1], off
	v_sub_f32_e32 v5, v21, v18
	v_fma_f32 v5, v5, v5, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v15, v5
	v_div_scale_f32 v17, null, v9, v9, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v18, v17
	s_waitcnt_depctr 0xfff
	v_fma_f32 v19, -v17, v18, 1.0
	v_fmac_f32_e32 v18, v19, v18
	v_div_scale_f32 v19, vcc_lo, v5, v9, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v20, v19, v18
	v_fma_f32 v21, -v17, v20, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v20, v21, v18
	v_fma_f32 v17, -v17, v20, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v17, v17, v18, v20
	v_div_fixup_f32 v5, v17, v9, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v17, 0x4f800000, v5
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v5
	v_cndmask_b32_e32 v5, v5, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v17, v5
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v18, -1, v17
	v_add_nc_u32_e32 v19, 1, v17
	v_fma_f32 v20, -v18, v17, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v21, -v19, v17, v5
	v_cmp_ge_f32_e64 s2, 0, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v17, v17, v18, s2
	v_cmp_lt_f32_e64 s2, 0, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v17, v17, v19, s2
	s_or_b32 s2, s3, exec_lo
	v_mul_f32_e32 v18, 0x37800000, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v17, v17, v18, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v5, 0x260
	v_cndmask_b32_e32 v24, v17, v5, vcc_lo
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v23, v24, v4
.LBB3_98:                               ; %Flow2534
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s24
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s3, s3, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_or_b32 s3, s3, s2
.LBB3_99:                               ; %Flow2533
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s23
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s2, s4, exec_lo
	s_and_b32 s3, s3, exec_lo
	s_or_b32 s2, s2, s3
.LBB3_100:                              ; %Flow2528
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s3, s4, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_or_b32 s4, s3, s2
.LBB3_101:                              ; %Flow2527
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s13
	s_and_saveexec_b32 s2, s4
	s_cbranch_execz .LBB3_103
; %bb.102:                              ; %.sink.split2428
                                        ;   in Loop: Header=BB3_4 Depth=1
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v23, off
	global_load_b32 v4, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v4, v24, v4
	global_store_b32 v[2:3], v4, off
.LBB3_103:                              ;   in Loop: Header=BB3_4 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_add_i32 s14, s14, 1
	s_add_i32 s12, s12, s8
	s_cmp_lg_u32 s9, s14
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr17
                                        ; implicit-def: $vgpr5
	s_cbranch_scc1 .LBB3_4
.LBB3_104:                              ; %Flow2587
	s_and_not1_saveexec_b32 s13, s18
	s_cbranch_execz .LBB3_207
; %bb.105:
	s_cmp_lt_i32 s8, 1
	s_cbranch_scc1 .LBB3_207
; %bb.106:                              ; %.lr.ph2355
	v_dual_sub_f32 v11, v18, v7 :: v_dual_sub_f32 v12, v19, v6
	s_mov_b32 s12, 0
	s_sub_i32 s11, 0, s11
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_div_scale_f32 v9, null, v12, v12, v11
	s_waitcnt vmcnt(0)
	v_div_scale_f32 v10, null, v12, v12, v4
	v_div_scale_f32 v16, vcc_lo, v11, v12, v11
	v_rcp_f32_e32 v13, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v14, v10
	v_div_scale_f32 v18, s0, v4, v12, v4
	s_waitcnt_depctr 0xfff
	v_fma_f32 v8, -v9, v13, 1.0
	v_fma_f32 v15, -v10, v14, 1.0
	v_dual_fmac_f32 v13, v8, v13 :: v_dual_fmac_f32 v14, v15, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v15, v16, v13
	v_mul_f32_e32 v19, v18, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v8, -v9, v15, v16
	v_fma_f32 v20, -v10, v19, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v15, v8, v13
	v_fmac_f32_e32 v19, v20, v14
	v_cvt_f32_i32_e32 v8, s15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v16, -v9, v15, v16
	v_fma_f32 v10, -v10, v19, v18
	v_mul_f32_e32 v9, v17, v17
	s_delay_alu instid0(VALU_DEP_3)
	v_div_fmas_f32 v13, v16, v13, v15
	v_mov_b32_e32 v16, 0
	s_mov_b32 vcc_lo, s0
	v_sub_f32_e32 v15, 0, v4
	v_div_fmas_f32 v14, v10, v14, v19
	v_fmac_f32_e32 v9, v5, v5
	v_div_fixup_f32 v11, v13, v12, v11
	v_cvt_f32_i32_e32 v10, s5
	v_cvt_f32_i32_e32 v13, s10
	v_div_fixup_f32 v12, v14, v12, v4
	v_cvt_f32_i32_e32 v14, s9
	v_fma_f32 v15, v15, v15, v9
	v_cmp_nle_f32_e64 s0, 0, v11
	s_mul_i32 s5, s9, s8
	v_cmp_nle_f32_e64 s1, 0, v12
.LBB3_107:                              ; =>This Inner Loop Header: Depth=1
	s_add_i32 s2, s11, s12
	s_mov_b32 s4, 0
	s_waitcnt vmcnt(1)
	v_cvt_f32_i32_e32 v4, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e32 v5, 1.0, v4
	v_cndmask_b32_e64 v18, v4, v5, s1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v18, v18, v6
	v_cndmask_b32_e64 v17, v5, v4, s1
	v_cndmask_b32_e64 v28, v4, v5, s0
	v_cndmask_b32_e64 v4, v5, v4, s0
	v_fma_f32 v18, v12, v18, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v17, v17, v6
	v_sub_f32_e32 v5, v28, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_sub_f32_e32 v4, v4, v6
	v_div_scale_f32 v20, null, s7, s7, v18
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v19, v12, v17, 0
	v_fma_f32 v4, v11, v4, v7
	v_fma_f32 v5, v11, v5, v7
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_rcp_f32_e32 v22, v20
	v_div_scale_f32 v17, null, s7, s7, v19
	v_div_scale_f32 v25, vcc_lo, v19, s7, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v21, v17
	s_waitcnt_depctr 0xfff
	v_fma_f32 v24, -v20, v22, 1.0
	v_fmac_f32_e32 v22, v24, v22
	s_waitcnt vmcnt(0)
	v_fma_f32 v23, -v17, v21, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v21, v23, v21
	v_div_scale_f32 v23, s2, v18, s7, v18
	v_mul_f32_e32 v24, v25, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v26, v23, v22
	v_fma_f32 v27, -v17, v24, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v24, v27, v21
	v_fma_f32 v17, -v17, v24, v25
	s_delay_alu instid0(VALU_DEP_1)
	v_div_fmas_f32 v21, v17, v21, v24
	v_add_f32_e32 v17, v5, v8
	v_fma_f32 v29, -v20, v26, v23
	s_mov_b32 vcc_lo, s2
                                        ; implicit-def: $vgpr24
	s_mov_b32 s2, exec_lo
	v_div_fixup_f32 v5, v21, s7, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_add_f32 v21, v4, v8 :: v_dual_fmac_f32 v26, v29, v22
	v_floor_f32_e32 v4, v17
	v_fma_f32 v20, -v20, v26, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f32_e32 v4, v4
	v_div_fmas_f32 v20, v20, v22, v26
	v_add_f32_e32 v22, v5, v10
	v_floor_f32_e32 v5, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v18, v20, s7, v18
	v_cvt_i32_f32_e32 v5, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_f32_e32 v19, v18, v10
	v_floor_f32_e32 v18, v22
	v_floor_f32_e32 v23, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f32_e32 v20, v18
	v_cvt_i32_f32_e32 v18, v23
                                        ; implicit-def: $vgpr23
	v_cmpx_ne_u32_e64 v5, v4
	s_xor_b32 s14, exec_lo, s2
	s_cbranch_execz .LBB3_186
; %bb.108:                              ;   in Loop: Header=BB3_107 Depth=1
	v_cmp_gt_i32_e32 vcc_lo, 1, v5
	v_cmp_le_i32_e64 s2, s9, v5
	s_mov_b32 s18, 0
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s15, exec_lo, s3
	s_cbranch_execz .LBB3_157
; %bb.109:                              ;   in Loop: Header=BB3_107 Depth=1
	s_mov_b32 s18, exec_lo
	v_cmpx_eq_u32_e32 0, v5
	s_cbranch_execz .LBB3_132
; %bb.110:                              ;   in Loop: Header=BB3_107 Depth=1
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
	s_mov_b32 s2, exec_lo
	v_cmpx_ne_u32_e64 v20, v18
	s_xor_b32 s19, exec_lo, s2
	s_cbranch_execz .LBB3_126
; %bb.111:                              ;   in Loop: Header=BB3_107 Depth=1
	v_cmp_gt_i32_e32 vcc_lo, 1, v20
	v_cmp_le_i32_e64 s2, s10, v20
	s_mov_b32 s23, 0
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s22, exec_lo, s3
	s_cbranch_execz .LBB3_119
; %bb.112:                              ;   in Loop: Header=BB3_107 Depth=1
	s_mov_b32 s23, exec_lo
	v_cmpx_eq_u32_e32 0, v20
	s_cbranch_execz .LBB3_114
; %bb.113:                              ; %.sink.split2392
                                        ;   in Loop: Header=BB3_107 Depth=1
	global_load_b32 v23, v16, s[20:21]
	global_load_b32 v24, v[0:1], off
	v_sub_f32_e32 v25, v21, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v26, v25, v25, 1.0
	v_mul_f32_e32 v26, v15, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v27, null, v9, v9, v26
	v_rcp_f32_e32 v28, v27
	s_waitcnt_depctr 0xfff
	v_fma_f32 v29, -v27, v28, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v28, v29, v28
	v_div_scale_f32 v29, vcc_lo, v26, v9, v26
	v_mul_f32_e32 v30, v29, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v31, -v27, v30, v29
	v_fmac_f32_e32 v30, v31, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v27, -v27, v30, v29
	v_div_scale_f32 v29, null, v25, v25, -v17
	v_div_fmas_f32 v27, v27, v28, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v26, v27, v9, v26
	v_dual_sub_f32 v27, v22, v19 :: v_dual_mul_f32 v28, 0x4f800000, v26
	v_cmp_gt_f32_e64 s2, 0xf800000, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f32 v30, null, v27, v27, -v19
	v_cndmask_b32_e64 v26, v26, v28, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v31, v30
	v_rcp_f32_e32 v28, v29
	v_sqrt_f32_e32 v32, v26
	s_delay_alu instid0(TRANS32_DEP_3)
	v_fma_f32 v34, -v30, v31, 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v33, -v29, v28, 1.0
	v_add_nc_u32_e32 v35, -1, v32
	v_fmac_f32_e32 v31, v34, v31
	v_div_scale_f32 v34, s3, -v19, v27, -v19
	v_add_nc_u32_e32 v36, 1, v32
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v38, -v35, v32, v26
	v_mul_f32_e32 v39, v34, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v40, -v36, v32, v26
	v_cmp_ge_f32_e64 s4, 0, v38
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v32, v32, v35, s4
	v_fma_f32 v35, -v30, v39, v34
	v_fmac_f32_e32 v28, v33, v28
	v_div_scale_f32 v33, vcc_lo, -v17, v25, -v17
	v_cmp_lt_f32_e64 s4, 0, v40
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v39, v35, v31
	v_mul_f32_e32 v37, v33, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v30, -v30, v39, v34
	v_fma_f32 v41, -v29, v37, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v37, v41, v28
	v_fma_f32 v29, -v29, v37, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v28, v29, v28, v37
	s_mov_b32 vcc_lo, s3
	v_div_fmas_f32 v29, v30, v31, v39
	v_cmp_class_f32_e64 vcc_lo, v26, 0x260
	v_div_fixup_f32 v25, v28, v25, -v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v27, v29, v27, -v19
	v_sub_f32_e32 v29, 1.0, v25
	v_cndmask_b32_e64 v32, v32, v36, s4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v28, 1.0, v27 :: v_dual_mul_f32 v33, 0x37800000, v32
	v_cndmask_b32_e64 v30, v32, v33, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v26, v30, v26, vcc_lo
	v_cmp_gt_f32_e32 vcc_lo, v25, v27
	v_dual_cndmask_b32 v25, v28, v26 :: v_dual_cndmask_b32 v26, v26, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v27, v26, v25
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v24, v27, v23
	global_store_b32 v[0:1], v24, off
	global_load_b32 v23, v[2:3], off
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v23, v26, v25
	global_store_b32 v[2:3], v23, off
.LBB3_114:                              ;   in Loop: Header=BB3_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s23
	s_mov_b32 s2, 0
	s_mov_b32 s3, exec_lo
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
	v_cmpx_eq_u32_e64 s10, v20
	s_cbranch_execz .LBB3_118
; %bb.115:                              ;   in Loop: Header=BB3_107 Depth=1
	v_dual_sub_f32 v25, v21, v17 :: v_dual_sub_f32 v24, v22, v19
	s_mov_b32 s4, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v26, null, v25, v25, -v17
	v_div_scale_f32 v32, vcc_lo, -v17, v25, -v17
	v_rcp_f32_e32 v28, v26
	s_waitcnt_depctr 0xfff
	v_fma_f32 v30, -v26, v28, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v23, v13, v19 :: v_dual_fmac_f32 v28, v30, v28
	v_div_scale_f32 v27, null, v24, v24, v23
	v_div_scale_f32 v30, s2, v23, v24, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v29, v27
	s_waitcnt_depctr 0xfff
	v_fma_f32 v31, -v27, v29, 1.0
	v_fmac_f32_e32 v29, v31, v29
	v_mul_f32_e32 v31, v32, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v33, v30, v29
	v_fma_f32 v34, -v26, v31, v32
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v35, -v27, v33, v30
	v_fmac_f32_e32 v31, v34, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v33, v35, v29
	v_fma_f32 v26, -v26, v31, v32
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v27, -v27, v33, v30
	v_div_fmas_f32 v26, v26, v28, v31
	s_mov_b32 vcc_lo, s2
	s_mov_b32 s2, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v27, v27, v29, v33
	v_div_fixup_f32 v26, v26, v25, -v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v27, v27, v24, v23
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
	v_cmpx_ngt_f32_e32 v26, v27
	s_xor_b32 s23, exec_lo, s2
	s_cbranch_execz .LBB3_117
; %bb.116:                              ;   in Loop: Header=BB3_107 Depth=1
	v_mad_u64_u32 v[23:24], null, s5, v18, s[12:13]
	s_mov_b32 s4, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v24, 31, v23
	v_lshlrev_b64 v[23:24], 2, v[23:24]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v23, vcc_lo, s16, v23
	v_add_co_ci_u32_e32 v24, vcc_lo, s17, v24, vcc_lo
	global_load_b32 v28, v[23:24], off
	global_load_b32 v23, v[0:1], off
	v_fma_f32 v24, v25, v25, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v24, v15, v24
	v_div_scale_f32 v25, null, v9, v9, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v29, v25
	s_waitcnt_depctr 0xfff
	v_fma_f32 v30, -v25, v29, 1.0
	v_fmac_f32_e32 v29, v30, v29
	v_div_scale_f32 v30, vcc_lo, v24, v9, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v31, v30, v29
	v_fma_f32 v32, -v25, v31, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v31, v32, v29
	v_fma_f32 v25, -v25, v31, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v25, v25, v29, v31
	v_div_fixup_f32 v24, v25, v9, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v25, 0x4f800000, v24
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v24
	v_cndmask_b32_e32 v24, v24, v25, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v25, v24
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v29, -1, v25
	v_add_nc_u32_e32 v30, 1, v25
	v_fma_f32 v31, -v29, v25, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v32, -v30, v25, v24
	v_cmp_ge_f32_e64 s2, 0, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v25, v25, v29, s2
	v_cmp_lt_f32_e64 s2, 0, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v25, v25, v30, s2
	v_mul_f32_e32 v29, 0x37800000, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v25, v25, v29, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v24, 0x260
	v_dual_cndmask_b32 v24, v25, v24 :: v_dual_sub_f32 v25, v27, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v24, v24, v25
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v23, v24, v28
.LBB3_117:                              ; %Flow2547
                                        ;   in Loop: Header=BB3_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s23
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s2, s4, exec_lo
.LBB3_118:                              ; %Flow2546
                                        ;   in Loop: Header=BB3_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s23, s2, exec_lo
.LBB3_119:                              ; %Flow2545
                                        ;   in Loop: Header=BB3_107 Depth=1
	s_and_not1_saveexec_b32 s22, s22
	s_cbranch_execz .LBB3_125
; %bb.120:                              ;   in Loop: Header=BB3_107 Depth=1
	global_load_b32 v23, v[0:1], off
	v_sub_f32_e32 v24, v21, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v25, v24, v24, 1.0
	v_mul_f32_e32 v25, v15, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v26, null, v9, v9, v25
	v_rcp_f32_e32 v27, v26
	s_waitcnt_depctr 0xfff
	v_fma_f32 v28, -v26, v27, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v27, v28, v27
	v_div_scale_f32 v28, vcc_lo, v25, v9, v25
	v_mul_f32_e32 v29, v28, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v30, -v26, v29, v28
	v_fmac_f32_e32 v29, v30, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v26, -v26, v29, v28
	v_sub_f32_e32 v28, v22, v19
	v_div_fmas_f32 v26, v26, v27, v29
	v_cvt_f32_i32_e32 v27, v20
	v_div_scale_f32 v29, null, v24, v24, -v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v25, v26, v9, v25
	v_mul_f32_e32 v26, 0x4f800000, v25
	v_cmp_gt_f32_e64 s2, 0xf800000, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v25, v25, v26, s2
	v_rcp_f32_e32 v26, v29
	v_sqrt_f32_e32 v32, v25
	v_sub_f32_e32 v27, v27, v19
	s_waitcnt_depctr 0xfff
	v_fma_f32 v33, -v29, v26, 1.0
	v_add_nc_u32_e32 v36, 1, v32
	v_div_scale_f32 v30, null, v28, v28, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v26, v33, v26 :: v_dual_add_nc_u32 v35, -1, v32
	v_div_scale_f32 v33, vcc_lo, -v17, v24, -v17
	v_rcp_f32_e32 v31, v30
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v38, -v35, v32, v25
	v_fma_f32 v40, -v36, v32, v25
	v_mul_f32_e32 v37, v33, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ge_f32_e64 s4, 0, v38
	v_fma_f32 v41, -v29, v37, v33
	s_waitcnt_depctr 0xfff
	v_fma_f32 v34, -v30, v31, 1.0
	v_cndmask_b32_e64 v32, v32, v35, s4
	v_cmp_lt_f32_e64 s4, 0, v40
	v_fmac_f32_e32 v37, v41, v26
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v31, v34, v31
	v_div_scale_f32 v34, s3, v27, v28, v27
	v_cndmask_b32_e64 v32, v32, v36, s4
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v29, -v29, v37, v33
	v_mul_f32_e32 v39, v34, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v33, 0x37800000, v32
	v_div_fmas_f32 v26, v29, v26, v37
	s_mov_b32 vcc_lo, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v35, -v30, v39, v34
	v_div_fixup_f32 v26, v26, v24, -v17
                                        ; implicit-def: $vgpr24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v39, v35, v31
	v_fma_f32 v30, -v30, v39, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v29, v30, v31, v39
	v_cndmask_b32_e64 v30, v32, v33, s2
	v_cmp_class_f32_e64 vcc_lo, v25, 0x260
	s_mov_b32 s2, exec_lo
	v_div_fixup_f32 v27, v29, v28, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v25, v30, v25, vcc_lo
	v_cmpx_ngt_f32_e32 v26, v27
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB3_122
; %bb.121:                              ;   in Loop: Header=BB3_107 Depth=1
	v_mad_u64_u32 v[28:29], null, s5, v18, s[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v29, 31, v28
	v_lshlrev_b64 v[28:29], 2, v[28:29]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v28, vcc_lo, s16, v28
	v_add_co_ci_u32_e32 v29, vcc_lo, s17, v29, vcc_lo
	global_load_b32 v24, v[28:29], off
	v_sub_f32_e32 v26, v27, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v28, v25, v26
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v23, v28, v24
	global_store_b32 v[0:1], v23, off
	global_load_b32 v28, v[2:3], off
	v_mad_u64_u32 v[23:24], null, s5, v20, s[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v24, 31, v23
	v_lshlrev_b64 v[23:24], 2, v[23:24]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v23, vcc_lo, s16, v23
	v_add_co_ci_u32_e32 v24, vcc_lo, s17, v24, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v28, v25, v26
	global_store_b32 v[2:3], v28, off
	global_load_b32 v26, v[23:24], off
	global_load_b32 v23, v[0:1], off
	v_sub_f32_e32 v24, 1.0, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v24, v25, v24
                                        ; implicit-def: $vgpr25
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v23, v24, v26
                                        ; implicit-def: $vgpr26
.LBB3_122:                              ; %Flow2541
                                        ;   in Loop: Header=BB3_107 Depth=1
	s_and_not1_saveexec_b32 s2, s2
	s_cbranch_execz .LBB3_124
; %bb.123:                              ;   in Loop: Header=BB3_107 Depth=1
	v_mad_u64_u32 v[27:28], null, s5, v20, s[12:13]
	v_sub_f32_e32 v24, 1.0, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v24, v24, v25
	v_ashrrev_i32_e32 v28, 31, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[27:28], 2, v[27:28]
	v_add_co_u32 v27, vcc_lo, s16, v27
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v28, vcc_lo, s17, v28, vcc_lo
	global_load_b32 v27, v[27:28], off
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v23, v24, v27
.LBB3_124:                              ; %Flow2542
                                        ;   in Loop: Header=BB3_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s23, s23, exec_lo
.LBB3_125:                              ; %Flow2548
                                        ;   in Loop: Header=BB3_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s4, s23, exec_lo
.LBB3_126:                              ; %Flow2544
                                        ;   in Loop: Header=BB3_107 Depth=1
	s_and_not1_saveexec_b32 s19, s19
	s_cbranch_execz .LBB3_130
; %bb.127:                              ;   in Loop: Header=BB3_107 Depth=1
	v_cmp_lt_i32_e32 vcc_lo, -1, v18
	v_cmp_gt_i32_e64 s2, s10, v18
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s3, vcc_lo, s2
	s_mov_b32 s2, s4
	s_and_saveexec_b32 s22, s3
	s_cbranch_execz .LBB3_129
; %bb.128:                              ;   in Loop: Header=BB3_107 Depth=1
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[23:24], null, s5, v18, s[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v24, 31, v23
	v_lshlrev_b64 v[23:24], 2, v[23:24]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v23, vcc_lo, s16, v23
	v_add_co_ci_u32_e32 v24, vcc_lo, s17, v24, vcc_lo
	global_load_b32 v25, v[23:24], off
	global_load_b32 v23, v[0:1], off
	v_sub_f32_e32 v24, v21, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v26, v24, v24, 1.0
	v_mul_f32_e32 v26, v15, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v27, null, v9, v9, v26
	v_rcp_f32_e32 v28, v27
	s_waitcnt_depctr 0xfff
	v_fma_f32 v29, -v27, v28, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v28, v29, v28
	v_div_scale_f32 v29, vcc_lo, v26, v9, v26
	v_mul_f32_e32 v30, v29, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v31, -v27, v30, v29
	v_fmac_f32_e32 v30, v31, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v27, -v27, v30, v29
	v_div_fmas_f32 v27, v27, v28, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v26, v27, v9, v26
	v_mul_f32_e32 v28, 0x4f800000, v26
	v_cmp_gt_f32_e64 s2, 0xf800000, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v26, v26, v28, s2
	v_sqrt_f32_e32 v28, v26
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v31, -1, v28
	v_div_scale_f32 v27, null, v24, v24, -v17
	v_add_nc_u32_e32 v32, 1, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v34, -v31, v28, v26
	v_rcp_f32_e32 v29, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v35, -v32, v28, v26
	v_cmp_ge_f32_e64 s3, 0, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v28, v28, v31, s3
	s_waitcnt_depctr 0xfff
	v_fma_f32 v30, -v27, v29, 1.0
	v_cmp_lt_f32_e64 s3, 0, v35
	v_fmac_f32_e32 v29, v30, v29
	v_div_scale_f32 v30, vcc_lo, -v17, v24, -v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v28, v28, v32, s3
	v_mul_f32_e32 v33, v30, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v36, -v27, v33, v30
	v_fmac_f32_e32 v33, v36, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v27, -v27, v33, v30
	v_mul_f32_e32 v30, 0x37800000, v28
	v_div_fmas_f32 v27, v27, v29, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v28, v28, v30, s2
	v_cmp_class_f32_e64 vcc_lo, v26, 0x260
	s_or_b32 s2, s4, exec_lo
	v_div_fixup_f32 v24, v27, v24, -v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v26, v28, v26, vcc_lo
	v_sub_f32_e32 v24, 1.0, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v24, v24, v26
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v23, v24, v25
.LBB3_129:                              ; %Flow2550
                                        ;   in Loop: Header=BB3_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s3, s4, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_or_b32 s4, s3, s2
.LBB3_130:                              ; %Flow2549
                                        ;   in Loop: Header=BB3_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s19
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 exec_lo, exec_lo, s4
	s_cbranch_execz .LBB3_132
; %bb.131:                              ; %.sink.split2399
                                        ;   in Loop: Header=BB3_107 Depth=1
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v23, off
	global_load_b32 v23, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v23, v24, v23
	global_store_b32 v[2:3], v23, off
.LBB3_132:                              ;   in Loop: Header=BB3_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s18
	s_mov_b32 s2, 0
	s_mov_b32 s18, exec_lo
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
	v_cmpx_eq_u32_e64 s9, v5
	s_cbranch_execz .LBB3_156
; %bb.133:                              ;   in Loop: Header=BB3_107 Depth=1
	s_mov_b32 s4, 0
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
	s_mov_b32 s2, exec_lo
	v_cmpx_ne_u32_e64 v20, v18
	s_xor_b32 s19, exec_lo, s2
	s_cbranch_execz .LBB3_151
; %bb.134:                              ;   in Loop: Header=BB3_107 Depth=1
	v_cmp_gt_i32_e32 vcc_lo, 1, v20
	v_cmp_le_i32_e64 s2, s10, v20
	s_mov_b32 s23, 0
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s22, exec_lo, s3
	s_cbranch_execz .LBB3_144
; %bb.135:                              ;   in Loop: Header=BB3_107 Depth=1
	v_sub_f32_e32 v5, v21, v17
	v_sub_f32_e32 v21, v22, v19
	v_sub_f32_e32 v17, v14, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v24, null, v21, v21, -v19
	v_div_scale_f32 v29, s3, -v19, v21, -v19
	v_rcp_f32_e32 v27, v24
	s_waitcnt_depctr 0xfff
	v_fma_f32 v26, -v24, v27, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v27, v26, v27
	v_mul_f32_e32 v30, v29, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v31, -v24, v30, v29
	v_fmac_f32_e32 v30, v31, v27
	s_waitcnt vmcnt(0)
	v_div_scale_f32 v23, null, v5, v5, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v22, v23
	s_waitcnt_depctr 0xfff
	v_fma_f32 v25, -v23, v22, 1.0
	v_fmac_f32_e32 v22, v25, v22
	v_div_scale_f32 v28, s2, v17, v5, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mov_b32 vcc_lo, s2
	v_mul_f32_e32 v25, v28, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v26, -v23, v25, v28
	v_fmac_f32_e32 v25, v26, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v26, -v23, v25, v28
	v_fma_f32 v23, -v24, v30, v29
	v_div_fmas_f32 v24, v26, v22, v25
	s_mov_b32 vcc_lo, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v27, v23, v27, v30
	v_cmp_eq_u32_e32 vcc_lo, 0, v20
	v_div_fixup_f32 v23, v24, v5, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v24, v27, v21, -v19
	v_cmp_gt_f32_e64 s3, v23, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s3
	s_and_saveexec_b32 s4, s3
	s_cbranch_execz .LBB3_137
; %bb.136:                              ;   in Loop: Header=BB3_107 Depth=1
	v_mad_u64_u32 v[27:28], null, v4, s8, s[12:13]
	v_fma_f32 v29, v5, v5, 1.0
	v_sub_f32_e32 v23, v23, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_f32_e32 v29, v15, v29
	v_ashrrev_i32_e32 v28, 31, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f32 v30, null, v9, v9, v29
	v_lshlrev_b64 v[27:28], 2, v[27:28]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v31, v30
	v_add_co_u32 v27, vcc_lo, s16, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v28, vcc_lo, s17, v28, vcc_lo
	global_load_b32 v27, v[27:28], off
	global_load_b32 v28, v[0:1], off
	v_fma_f32 v32, -v30, v31, 1.0
	v_fmac_f32_e32 v31, v32, v31
	v_div_scale_f32 v32, vcc_lo, v29, v9, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v33, v32, v31
	v_fma_f32 v34, -v30, v33, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v33, v34, v31
	v_fma_f32 v30, -v30, v33, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v30, v30, v31, v33
	v_div_fixup_f32 v29, v30, v9, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v30, 0x4f800000, v29
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v29
	v_cndmask_b32_e32 v29, v29, v30, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v30, v29
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v31, -1, v30
	v_add_nc_u32_e32 v32, 1, v30
	v_fma_f32 v33, -v31, v30, v29
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v34, -v32, v30, v29
	v_cmp_ge_f32_e64 s3, 0, v33
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v30, v30, v31, s3
	v_cmp_lt_f32_e64 s3, 0, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v30, v30, v32, s3
	v_mul_f32_e32 v31, 0x37800000, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v30, v30, v31, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v29, 0x260
	v_cndmask_b32_e32 v29, v30, v29, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v24, v29, v23
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v28, v24, v27
	global_store_b32 v[0:1], v28, off
	global_load_b32 v24, v[2:3], off
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v24, v29, v23
	global_store_b32 v[2:3], v24, off
.LBB3_137:                              ;   in Loop: Header=BB3_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s4
	s_mov_b32 s3, 0
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
	s_mov_b32 s4, exec_lo
	v_cmpx_eq_u32_e64 s10, v20
	s_xor_b32 s23, exec_lo, s4
	s_cbranch_execz .LBB3_143
; %bb.138:                              ;   in Loop: Header=BB3_107 Depth=1
	v_mad_u64_u32 v[23:24], null, v18, s9, v[4:5]
	v_fma_f32 v18, v5, v5, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_sub_f32 v19, v13, v19 :: v_dual_mul_f32 v18, v15, v18
	v_mad_u64_u32 v[27:28], null, v23, s8, s[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f32 v20, null, v9, v9, v18
	v_ashrrev_i32_e32 v28, 31, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[23:24], 2, v[27:28]
	v_add_co_u32 v23, vcc_lo, s16, v23
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v24, vcc_lo, s17, v24, vcc_lo
	global_load_b32 v4, v[23:24], off
	global_load_b32 v23, v[0:1], off
	v_rcp_f32_e32 v24, v20
	s_waitcnt_depctr 0xfff
	v_fma_f32 v27, -v20, v24, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v24, v27, v24
	v_div_scale_f32 v27, vcc_lo, v18, v9, v18
	v_mul_f32_e32 v28, v27, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v29, -v20, v28, v27
	v_fmac_f32_e32 v28, v29, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v20, -v20, v28, v27
	v_div_fmas_f32 v20, v20, v24, v28
	v_div_scale_f32 v24, null, v21, v21, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v18, v20, v9, v18
	v_mul_f32_e32 v20, 0x4f800000, v18
	v_cmp_gt_f32_e64 s3, 0xf800000, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v20, v18, v20, s3
	v_rcp_f32_e32 v18, v24
	v_sqrt_f32_e32 v27, v20
	s_waitcnt_depctr 0xfff
	v_fma_f32 v28, -v24, v18, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_dual_fmac_f32 v18, v28, v18 :: v_dual_add_nc_u32 v29, -1, v27
	v_div_scale_f32 v28, s4, v19, v21, v19
	v_add_nc_u32_e32 v30, 1, v27
	v_fma_f32 v31, -v29, v27, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v32, v28, v18
	v_fma_f32 v33, -v30, v27, v20
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cmp_ge_f32_e32 vcc_lo, 0, v31
	v_cndmask_b32_e32 v27, v27, v29, vcc_lo
	v_fma_f32 v29, -v24, v32, v28
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_f32_e32 vcc_lo, 0, v33
	v_fmac_f32_e32 v32, v29, v18
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e32 v27, v27, v30, vcc_lo
	s_mov_b32 vcc_lo, s2
	s_mov_b32 s2, exec_lo
	v_div_fmas_f32 v22, v26, v22, v25
	v_fma_f32 v24, -v24, v32, v28
	v_mul_f32_e32 v29, 0x37800000, v27
	s_mov_b32 vcc_lo, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v24, v24, v18, v32
	v_cndmask_b32_e64 v25, v27, v29, s3
	v_cmp_class_f32_e64 vcc_lo, v20, 0x260
	v_div_fixup_f32 v18, v22, v5, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_fixup_f32 v17, v24, v21, v19
                                        ; implicit-def: $vgpr24
	v_cndmask_b32_e32 v5, v25, v20, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_ngt_f32_e32 v18, v17
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB3_140
; %bb.139:                              ;   in Loop: Header=BB3_107 Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v24, v18, v5
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr17
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v23, v24, v4
                                        ; implicit-def: $vgpr4
.LBB3_140:                              ; %Flow2537
                                        ;   in Loop: Header=BB3_107 Depth=1
	s_and_not1_saveexec_b32 s2, s2
	s_cbranch_execz .LBB3_142
; %bb.141:                              ;   in Loop: Header=BB3_107 Depth=1
	v_mul_f32_e32 v24, v5, v17
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v23, v24, v4
.LBB3_142:                              ; %Flow2538
                                        ;   in Loop: Header=BB3_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s3, exec_lo
.LBB3_143:                              ; %Flow2566
                                        ;   in Loop: Header=BB3_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s23
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s23, s3, exec_lo
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr17
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr18
.LBB3_144:                              ; %Flow2565
                                        ;   in Loop: Header=BB3_107 Depth=1
	s_and_not1_saveexec_b32 s22, s22
	s_cbranch_execz .LBB3_150
; %bb.145:                              ;   in Loop: Header=BB3_107 Depth=1
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[23:24], null, v18, s9, v[4:5]
	v_sub_f32_e32 v18, v21, v17
	v_sub_f32_e32 v17, v14, v17
	v_sub_f32_e32 v22, v22, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v21, v18, v18, 1.0
	v_mad_u64_u32 v[24:25], null, v23, s8, s[12:13]
	v_mul_f32_e32 v21, v15, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v25, 31, v24
	v_lshlrev_b64 v[23:24], 2, v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v23, vcc_lo, s16, v23
	v_add_co_ci_u32_e32 v24, vcc_lo, s17, v24, vcc_lo
	global_load_b32 v5, v[23:24], off
	global_load_b32 v23, v[0:1], off
	v_div_scale_f32 v24, null, v9, v9, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v25, v24
	s_waitcnt_depctr 0xfff
	v_fma_f32 v26, -v24, v25, 1.0
	v_fmac_f32_e32 v25, v26, v25
	v_div_scale_f32 v26, vcc_lo, v21, v9, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v27, v26, v25
	v_fma_f32 v28, -v24, v27, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v27, v28, v25
	v_fma_f32 v24, -v24, v27, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v24, v24, v25, v27
	v_cvt_f32_i32_e32 v25, v20
	v_div_fixup_f32 v21, v24, v9, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_sub_f32 v24, v25, v19 :: v_dual_mul_f32 v19, 0x4f800000, v21
	v_cmp_gt_f32_e64 s2, 0xf800000, v21
	v_div_scale_f32 v26, null, v22, v22, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v21, v21, v19, s2
	v_rcp_f32_e32 v27, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3)
	v_sqrt_f32_e32 v28, v21
	s_waitcnt_depctr 0xfff
	v_fma_f32 v30, -v26, v27, 1.0
	v_add_nc_u32_e32 v31, -1, v28
	v_div_scale_f32 v25, null, v18, v18, v17
	v_fmac_f32_e32 v27, v30, v27
	v_div_scale_f32 v30, s3, v24, v22, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_rcp_f32_e32 v19, v25
	v_add_nc_u32_e32 v32, 1, v28
	v_fma_f32 v34, -v31, v28, v21
	v_mul_f32_e32 v35, v30, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v36, -v32, v28, v21
	v_cmp_ge_f32_e64 s4, 0, v34
	s_waitcnt_depctr 0xfff
	v_fma_f32 v29, -v25, v19, 1.0
	v_cndmask_b32_e64 v28, v28, v31, s4
	v_fma_f32 v31, -v26, v35, v30
	v_cmp_lt_f32_e64 s4, 0, v36
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v19, v29, v19
	v_div_scale_f32 v29, vcc_lo, v17, v18, v17
	v_fmac_f32_e32 v35, v31, v27
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v28, v28, v32, s4
	v_mul_f32_e32 v33, v29, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v26, -v26, v35, v30
	v_fma_f32 v37, -v25, v33, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v33, v37, v19
	v_fma_f32 v25, -v25, v33, v29
	v_mul_f32_e32 v29, 0x37800000, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v19, v25, v19, v33
	s_mov_b32 vcc_lo, s3
	v_div_fmas_f32 v25, v26, v27, v35
	v_cndmask_b32_e64 v26, v28, v29, s2
	v_cmp_class_f32_e64 vcc_lo, v21, 0x260
	v_div_fixup_f32 v19, v19, v18, v17
	s_mov_b32 s2, exec_lo
	v_div_fixup_f32 v18, v25, v22, v24
                                        ; implicit-def: $vgpr24
	v_cndmask_b32_e32 v17, v26, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_ngt_f32_e32 v19, v18
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB3_147
; %bb.146:                              ;   in Loop: Header=BB3_107 Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v24, v19, v17
                                        ; implicit-def: $vgpr17
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr20
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v23, v24, v5
                                        ; implicit-def: $vgpr5
.LBB3_147:                              ; %Flow2539
                                        ;   in Loop: Header=BB3_107 Depth=1
	s_and_not1_saveexec_b32 s2, s2
	s_cbranch_execz .LBB3_149
; %bb.148:                              ;   in Loop: Header=BB3_107 Depth=1
	v_mul_f32_e32 v21, v17, v18
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v23, v21, v5
	v_mad_u64_u32 v[21:22], null, v20, s9, v[4:5]
	global_store_b32 v[0:1], v23, off
	global_load_b32 v23, v[2:3], off
	v_mad_u64_u32 v[4:5], null, v21, s8, s[12:13]
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v4, vcc_lo, s16, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s17, v5, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v23, v17, v18
	global_store_b32 v[2:3], v23, off
	global_load_b32 v4, v[4:5], off
	global_load_b32 v23, v[0:1], off
	v_sub_f32_e32 v5, v19, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v24, v17, v5
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v23, v24, v4
.LBB3_149:                              ; %Flow2540
                                        ;   in Loop: Header=BB3_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s23, s23, exec_lo
.LBB3_150:                              ; %Flow2567
                                        ;   in Loop: Header=BB3_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s4, s23, exec_lo
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr17
                                        ; implicit-def: $vgpr4
.LBB3_151:                              ; %Flow2564
                                        ;   in Loop: Header=BB3_107 Depth=1
	s_and_not1_saveexec_b32 s19, s19
	s_cbranch_execz .LBB3_155
; %bb.152:                              ;   in Loop: Header=BB3_107 Depth=1
	v_cmp_lt_i32_e32 vcc_lo, -1, v18
	v_cmp_gt_i32_e64 s2, s10, v18
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s2
	s_mov_b32 s2, s4
	s_and_saveexec_b32 s22, s3
	s_xor_b32 s22, exec_lo, s22
	s_cbranch_execz .LBB3_154
; %bb.153:                              ;   in Loop: Header=BB3_107 Depth=1
	s_waitcnt vmcnt(1)
	v_mad_u64_u32 v[19:20], null, v18, s9, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v19, s8, s[12:13]
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v4, vcc_lo, s16, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s17, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	global_load_b32 v23, v[0:1], off
	v_sub_f32_e32 v5, v21, v17
	v_sub_f32_e32 v17, v14, v17
	v_fma_f32 v18, v5, v5, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v18, v15, v18
	v_div_scale_f32 v19, null, v9, v9, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v20, v19
	s_waitcnt_depctr 0xfff
	v_fma_f32 v21, -v19, v20, 1.0
	v_fmac_f32_e32 v20, v21, v20
	v_div_scale_f32 v21, vcc_lo, v18, v9, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v22, v21, v20
	v_fma_f32 v24, -v19, v22, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v22, v24, v20
	v_fma_f32 v19, -v19, v22, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v19, v19, v20, v22
	v_div_scale_f32 v20, null, v5, v5, v17
	v_div_fixup_f32 v18, v19, v9, v18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v19, 0x4f800000, v18
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v18
	v_cndmask_b32_e32 v18, v18, v19, vcc_lo
	v_rcp_f32_e32 v19, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sqrt_f32_e32 v21, v18
	s_waitcnt_depctr 0xfff
	v_fma_f32 v22, -v20, v19, 1.0
	v_dual_fmac_f32 v19, v22, v19 :: v_dual_add_nc_u32 v24, -1, v21
	v_add_nc_u32_e32 v25, 1, v21
	v_div_scale_f32 v22, s2, v17, v5, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v26, -v24, v21, v18
	v_fma_f32 v27, -v25, v21, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v28, v22, v19
	v_cmp_ge_f32_e64 s3, 0, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v21, v21, v24, s3
	v_cmp_lt_f32_e64 s3, 0, v27
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v24, -v20, v28, v22
	v_cndmask_b32_e64 v21, v21, v25, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v28, v24, v19
	v_mul_f32_e32 v24, 0x37800000, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v20, -v20, v28, v22
	v_cndmask_b32_e32 v21, v21, v24, vcc_lo
	s_mov_b32 vcc_lo, s2
	s_or_b32 s2, s4, exec_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v19, v20, v19, v28
	v_cmp_class_f32_e64 vcc_lo, v18, 0x260
	v_div_fixup_f32 v5, v19, v5, v17
	v_cndmask_b32_e32 v18, v21, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v24, v5, v18
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v23, v24, v4
.LBB3_154:                              ; %Flow2569
                                        ;   in Loop: Header=BB3_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s3, s4, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_or_b32 s4, s3, s2
.LBB3_155:                              ; %Flow2568
                                        ;   in Loop: Header=BB3_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s19
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s2, s4, exec_lo
.LBB3_156:                              ; %Flow2563
                                        ;   in Loop: Header=BB3_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s18
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s18, s2, exec_lo
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr17
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr22
.LBB3_157:                              ; %Flow2562
                                        ;   in Loop: Header=BB3_107 Depth=1
	s_and_not1_saveexec_b32 s15, s15
	s_cbranch_execz .LBB3_185
; %bb.158:                              ;   in Loop: Header=BB3_107 Depth=1
	s_mov_b32 s4, s18
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
	s_mov_b32 s2, exec_lo
	v_cmpx_ne_u32_e64 v20, v18
	s_xor_b32 s19, exec_lo, s2
	s_cbranch_execz .LBB3_180
; %bb.159:                              ;   in Loop: Header=BB3_107 Depth=1
	v_cmp_gt_i32_e32 vcc_lo, 1, v20
	v_cmp_le_i32_e64 s2, s10, v20
	s_mov_b32 s23, s18
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s22, exec_lo, s3
	s_cbranch_execz .LBB3_173
; %bb.160:                              ;   in Loop: Header=BB3_107 Depth=1
	s_mov_b32 s23, exec_lo
	v_cmpx_eq_u32_e32 0, v20
	s_cbranch_execz .LBB3_166
; %bb.161:                              ;   in Loop: Header=BB3_107 Depth=1
	global_load_b32 v23, v[0:1], off
	v_sub_f32_e32 v24, v21, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v25, v24, v24, 1.0
	v_mul_f32_e32 v25, v15, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v26, null, v9, v9, v25
	v_rcp_f32_e32 v27, v26
	s_waitcnt_depctr 0xfff
	v_fma_f32 v28, -v26, v27, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v27, v28, v27
	v_div_scale_f32 v28, vcc_lo, v25, v9, v25
	v_mul_f32_e32 v29, v28, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v30, -v26, v29, v28
	v_fmac_f32_e32 v29, v30, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v26, -v26, v29, v28
	v_div_fmas_f32 v26, v26, v27, v29
	s_waitcnt vmcnt(2)
	v_cvt_f32_i32_e32 v27, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v25, v26, v9, v25
	v_dual_sub_f32 v26, v27, v17 :: v_dual_sub_f32 v27, v22, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v28, 0x4f800000, v25
	v_cmp_gt_f32_e64 s2, 0xf800000, v25
	v_div_scale_f32 v29, null, v24, v24, v26
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_scale_f32 v30, null, v27, v27, -v19
	v_cndmask_b32_e64 v28, v25, v28, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v25, v29
	v_rcp_f32_e32 v31, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_3)
	v_sqrt_f32_e32 v32, v28
	v_fma_f32 v33, -v29, v25, 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v34, -v30, v31, 1.0
	v_add_nc_u32_e32 v35, -1, v32
	v_fmac_f32_e32 v25, v33, v25
	v_div_scale_f32 v33, vcc_lo, v26, v24, v26
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v31, v34, v31
	v_div_scale_f32 v34, s3, -v19, v27, -v19
	v_add_nc_u32_e32 v36, 1, v32
	v_fma_f32 v38, -v35, v32, v28
	v_mul_f32_e32 v37, v33, v25
	v_mul_f32_e32 v39, v34, v31
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v40, -v36, v32, v28
	v_cmp_ge_f32_e64 s4, 0, v38
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v41, -v29, v37, v33
	v_cndmask_b32_e64 v32, v32, v35, s4
	v_fma_f32 v35, -v30, v39, v34
	v_cmp_lt_f32_e64 s4, 0, v40
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v37, v41, v25
	v_fmac_f32_e32 v39, v35, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v32, v32, v36, s4
	v_fma_f32 v29, -v29, v37, v33
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v30, -v30, v39, v34
	v_mul_f32_e32 v33, 0x37800000, v32
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v25, v29, v25, v37
	s_mov_b32 vcc_lo, s3
	v_div_fmas_f32 v29, v30, v31, v39
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e64 v30, v32, v33, s2
	v_cmp_class_f32_e64 vcc_lo, v28, 0x260
	v_div_fixup_f32 v25, v25, v24, v26
	s_mov_b32 s2, exec_lo
	v_div_fixup_f32 v26, v29, v27, -v19
                                        ; implicit-def: $vgpr27
	v_cndmask_b32_e32 v24, v30, v28, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_ngt_f32_e32 v25, v26
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB3_163
; %bb.162:                              ;   in Loop: Header=BB3_107 Depth=1
	v_mad_u64_u32 v[27:28], null, v5, s8, s[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v28, 31, v27
	v_lshlrev_b64 v[27:28], 2, v[27:28]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v27, vcc_lo, s16, v27
	v_add_co_ci_u32_e32 v28, vcc_lo, s17, v28, vcc_lo
	global_load_b32 v25, v[27:28], off
	v_sub_f32_e32 v26, 1.0, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v27, v24, v26
                                        ; implicit-def: $vgpr26
                                        ; implicit-def: $vgpr24
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v23, v27, v25
                                        ; implicit-def: $vgpr25
.LBB3_163:                              ; %Flow2554
                                        ;   in Loop: Header=BB3_107 Depth=1
	s_and_not1_saveexec_b32 s2, s2
	s_cbranch_execz .LBB3_165
; %bb.164:                              ;   in Loop: Header=BB3_107 Depth=1
	v_mad_u64_u32 v[27:28], null, v4, s8, s[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v28, 31, v27
	v_lshlrev_b64 v[27:28], 2, v[27:28]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v27, vcc_lo, s16, v27
	v_add_co_ci_u32_e32 v28, vcc_lo, s17, v28, vcc_lo
	global_load_b32 v27, v[27:28], off
	v_dual_sub_f32 v28, v25, v26 :: v_dual_sub_f32 v25, 1.0, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v26, v24, v28
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v23, v26, v27
	v_mad_u64_u32 v[26:27], null, v5, s8, s[12:13]
	global_store_b32 v[0:1], v23, off
	global_load_b32 v23, v[2:3], off
	v_ashrrev_i32_e32 v27, 31, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[26:27], 2, v[26:27]
	v_add_co_u32 v26, vcc_lo, s16, v26
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v27, vcc_lo, s17, v27, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v23, v24, v28
	global_store_b32 v[2:3], v23, off
	global_load_b32 v26, v[26:27], off
	global_load_b32 v23, v[0:1], off
	v_mul_f32_e32 v27, v25, v24
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v23, v27, v26
.LBB3_165:                              ; %.sink.split
                                        ;   in Loop: Header=BB3_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v23, off
	global_load_b32 v23, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v23, v27, v23
	global_store_b32 v[2:3], v23, off
.LBB3_166:                              ; %Flow2555
                                        ;   in Loop: Header=BB3_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s23
	s_mov_b32 s2, s18
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
	s_mov_b32 s3, exec_lo
	v_cmpx_eq_u32_e64 s10, v20
	s_xor_b32 s23, exec_lo, s3
	s_cbranch_execz .LBB3_172
; %bb.167:                              ;   in Loop: Header=BB3_107 Depth=1
	v_mul_lo_u32 v18, v18, s9
	v_sub_f32_e32 v20, v21, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f32 v21, v20, v20, 1.0
	s_waitcnt vmcnt(1)
	v_dual_mul_f32 v21, v15, v21 :: v_dual_add_nc_u32 v4, v18, v4
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[23:24], null, v4, s8, s[12:13]
	v_ashrrev_i32_e32 v24, 31, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[23:24], 2, v[23:24]
	v_add_co_u32 v23, vcc_lo, s16, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v24, vcc_lo, s17, v24, vcc_lo
	global_load_b32 v4, v[23:24], off
	global_load_b32 v23, v[0:1], off
	v_div_scale_f32 v24, null, v9, v9, v21
	v_rcp_f32_e32 v25, v24
	s_waitcnt_depctr 0xfff
	v_fma_f32 v26, -v24, v25, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v25, v26, v25
	v_div_scale_f32 v26, vcc_lo, v21, v9, v21
	v_mul_f32_e32 v27, v26, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v28, -v24, v27, v26
	v_fmac_f32_e32 v27, v28, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v24, -v24, v27, v26
	v_div_fmas_f32 v24, v24, v25, v27
	v_cvt_f32_i32_e32 v25, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v21, v24, v9, v21
	v_sub_f32_e32 v17, v25, v17
	v_sub_f32_e32 v24, v13, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_dual_sub_f32 v19, v22, v19 :: v_dual_mul_f32 v22, 0x4f800000, v21
	v_cmp_gt_f32_e64 s2, 0xf800000, v21
	v_div_scale_f32 v25, null, v20, v20, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_scale_f32 v26, null, v19, v19, v24
	v_cndmask_b32_e64 v21, v21, v22, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v22, v25
	v_rcp_f32_e32 v27, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(TRANS32_DEP_3)
	v_sqrt_f32_e32 v28, v21
	v_fma_f32 v29, -v25, v22, 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v30, -v26, v27, 1.0
	v_dual_fmac_f32 v22, v29, v22 :: v_dual_add_nc_u32 v31, -1, v28
	v_div_scale_f32 v29, vcc_lo, v17, v20, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v27, v30, v27
	v_div_scale_f32 v30, s3, v24, v19, v24
	v_add_nc_u32_e32 v32, 1, v28
	v_fma_f32 v34, -v31, v28, v21
	v_mul_f32_e32 v33, v29, v22
	v_mul_f32_e32 v35, v30, v27
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v36, -v32, v28, v21
	v_cmp_ge_f32_e64 s4, 0, v34
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v37, -v25, v33, v29
	v_cndmask_b32_e64 v28, v28, v31, s4
	v_fma_f32 v31, -v26, v35, v30
	v_cmp_lt_f32_e64 s4, 0, v36
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v33, v37, v22
	v_fmac_f32_e32 v35, v31, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v28, v28, v32, s4
	v_fma_f32 v25, -v25, v33, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v26, -v26, v35, v30
	v_mul_f32_e32 v29, 0x37800000, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v22, v25, v22, v33
	s_mov_b32 vcc_lo, s3
	v_div_fmas_f32 v25, v26, v27, v35
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e64 v26, v28, v29, s2
	v_cmp_class_f32_e64 vcc_lo, v21, 0x260
	v_div_fixup_f32 v20, v22, v20, v17
	s_mov_b32 s2, exec_lo
	v_div_fixup_f32 v19, v25, v19, v24
                                        ; implicit-def: $vgpr24
	v_cndmask_b32_e32 v17, v26, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_ngt_f32_e32 v20, v19
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB3_169
; %bb.168:                              ;   in Loop: Header=BB3_107 Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v21, v20, v17
	s_waitcnt vmcnt(0)
	v_dual_fmac_f32 v23, v21, v4 :: v_dual_add_nc_u32 v18, v18, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v18, s8, s[12:13]
	global_store_b32 v[0:1], v23, off
	global_load_b32 v21, v[2:3], off
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s16, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s17, v5, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v21, v20, v17
	global_store_b32 v[2:3], v21, off
	global_load_b32 v4, v[4:5], off
	global_load_b32 v23, v[0:1], off
	v_sub_f32_e32 v5, v19, v20
                                        ; implicit-def: $vgpr19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v24, v17, v5
                                        ; implicit-def: $vgpr17
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v23, v24, v4
                                        ; implicit-def: $vgpr4
.LBB3_169:                              ; %Flow2552
                                        ;   in Loop: Header=BB3_107 Depth=1
	s_and_not1_saveexec_b32 s2, s2
	s_cbranch_execz .LBB3_171
; %bb.170:                              ;   in Loop: Header=BB3_107 Depth=1
	v_mul_f32_e32 v24, v17, v19
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v23, v24, v4
.LBB3_171:                              ; %Flow2553
                                        ;   in Loop: Header=BB3_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s2, s18, exec_lo
.LBB3_172:                              ; %Flow2573
                                        ;   in Loop: Header=BB3_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s23
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s3, s18, exec_lo
	s_and_b32 s2, s2, exec_lo
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr17
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr18
	s_or_b32 s23, s3, s2
.LBB3_173:                              ; %Flow2572
                                        ;   in Loop: Header=BB3_107 Depth=1
	s_and_not1_saveexec_b32 s22, s22
	s_cbranch_execz .LBB3_179
; %bb.174:                              ;   in Loop: Header=BB3_107 Depth=1
	v_mul_lo_u32 v27, v18, s9
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v18, v27, v4
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[23:24], null, v18, s8, s[12:13]
	v_sub_f32_e32 v18, v21, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v21, v18, v18, 1.0
	v_ashrrev_i32_e32 v24, 31, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v21, v15, v21
	v_lshlrev_b64 v[23:24], 2, v[23:24]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v23, vcc_lo, s16, v23
	v_add_co_ci_u32_e32 v24, vcc_lo, s17, v24, vcc_lo
	global_load_b32 v25, v[23:24], off
	global_load_b32 v26, v[0:1], off
	v_div_scale_f32 v23, null, v9, v9, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v24, v23
	s_waitcnt_depctr 0xfff
	v_fma_f32 v28, -v23, v24, 1.0
	v_fmac_f32_e32 v24, v28, v24
	v_div_scale_f32 v28, vcc_lo, v21, v9, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v29, v28, v24
	v_fma_f32 v30, -v23, v29, v28
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v29, v30, v24
	v_fma_f32 v23, -v23, v29, v28
	v_cvt_f32_i32_e32 v28, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v23, v23, v24, v29
	v_cvt_f32_i32_e32 v24, v5
	v_div_fixup_f32 v21, v23, v9, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_f32_e32 v17, v24, v17
	v_sub_f32_e32 v23, v28, v19
	v_dual_sub_f32 v22, v22, v19 :: v_dual_mul_f32 v19, 0x4f800000, v21
	v_cmp_gt_f32_e64 s2, 0xf800000, v21
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_div_scale_f32 v24, null, v18, v18, v17
	v_div_scale_f32 v28, null, v22, v22, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v21, v21, v19, s2
	v_rcp_f32_e32 v19, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v29, v28
	v_sqrt_f32_e32 v30, v21
	s_delay_alu instid0(TRANS32_DEP_3)
	v_fma_f32 v31, -v24, v19, 1.0
	s_waitcnt_depctr 0xfff
	v_fma_f32 v32, -v28, v29, 1.0
	v_add_nc_u32_e32 v33, -1, v30
	v_fmac_f32_e32 v19, v31, v19
	v_div_scale_f32 v31, vcc_lo, v17, v18, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v29, v32, v29
	v_div_scale_f32 v32, s3, v23, v22, v23
	v_add_nc_u32_e32 v34, 1, v30
	v_fma_f32 v36, -v33, v30, v21
	v_mul_f32_e32 v35, v31, v19
	v_mul_f32_e32 v37, v32, v29
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fma_f32 v38, -v34, v30, v21
	v_cmp_ge_f32_e64 s4, 0, v36
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v39, -v24, v35, v31
	v_cndmask_b32_e64 v30, v30, v33, s4
	v_fma_f32 v33, -v28, v37, v32
	v_cmp_lt_f32_e64 s4, 0, v38
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v35, v39, v19
	v_fmac_f32_e32 v37, v33, v29
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v30, v30, v34, s4
	v_fma_f32 v24, -v24, v35, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v28, -v28, v37, v32
	v_mul_f32_e32 v31, 0x37800000, v30
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v19, v24, v19, v35
	s_mov_b32 vcc_lo, s3
	v_div_fmas_f32 v24, v28, v29, v37
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e64 v28, v30, v31, s2
	v_cmp_class_f32_e64 vcc_lo, v21, 0x260
	v_div_fixup_f32 v19, v19, v18, v17
	s_mov_b32 s2, exec_lo
	v_div_fixup_f32 v18, v24, v22, v23
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
	v_cndmask_b32_e32 v17, v28, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cmpx_ngt_f32_e32 v19, v18
	s_xor_b32 s2, exec_lo, s2
	s_cbranch_execz .LBB3_176
; %bb.175:                              ;   in Loop: Header=BB3_107 Depth=1
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v4, v19, v17
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v26, v4, v25
                                        ; implicit-def: $vgpr25
	global_store_b32 v[0:1], v26, off
	global_load_b32 v4, v[2:3], off
                                        ; implicit-def: $vgpr26
	s_waitcnt vmcnt(0)
	v_dual_fmac_f32 v4, v19, v17 :: v_dual_sub_f32 v19, v18, v19
	v_add_nc_u32_e32 v23, v27, v5
	global_store_b32 v[2:3], v4, off
	v_mad_u64_u32 v[21:22], null, v23, s8, s[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v22, 31, v21
	v_lshlrev_b64 v[21:22], 2, v[21:22]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v21, vcc_lo, s16, v21
	v_add_co_ci_u32_e32 v22, vcc_lo, s17, v22, vcc_lo
	global_load_b32 v4, v[21:22], off
	global_load_b32 v21, v[0:1], off
	v_mul_f32_e32 v22, v17, v19
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v21, v22, v4
	global_store_b32 v[0:1], v21, off
	global_load_b32 v23, v[2:3], off
	v_mad_u64_u32 v[21:22], null, v20, s9, v[5:6]
                                        ; implicit-def: $vgpr20
	v_mad_u64_u32 v[4:5], null, v21, s8, s[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s16, v4
	v_add_co_ci_u32_e32 v5, vcc_lo, s17, v5, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v23, v17, v19
                                        ; implicit-def: $vgpr19
	global_store_b32 v[2:3], v23, off
	global_load_b32 v4, v[4:5], off
	global_load_b32 v23, v[0:1], off
	v_sub_f32_e32 v5, 1.0, v18
                                        ; implicit-def: $vgpr18
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v24, v17, v5
                                        ; implicit-def: $vgpr17
                                        ; implicit-def: $vgpr5
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v23, v24, v4
                                        ; implicit-def: $vgpr4
.LBB3_176:                              ; %Flow2556
                                        ;   in Loop: Header=BB3_107 Depth=1
	s_and_not1_saveexec_b32 s2, s2
	s_cbranch_execz .LBB3_178
; %bb.177:                              ;   in Loop: Header=BB3_107 Depth=1
	v_mul_lo_u32 v23, v20, s9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_dual_mul_f32 v21, v17, v18 :: v_dual_add_nc_u32 v4, v23, v4
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v26, v21, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[20:21], null, v4, s8, s[12:13]
	global_store_b32 v[0:1], v26, off
	global_load_b32 v22, v[2:3], off
	v_ashrrev_i32_e32 v21, 31, v20
	v_lshlrev_b64 v[20:21], 2, v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v20, vcc_lo, s16, v20
	v_add_co_ci_u32_e32 v21, vcc_lo, s17, v21, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v22, v17, v18
	v_sub_f32_e32 v18, v19, v18
	global_store_b32 v[2:3], v22, off
	global_load_b32 v4, v[20:21], off
	global_load_b32 v20, v[0:1], off
	v_mul_f32_e32 v21, v17, v18
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v20, v21, v4 :: v_dual_add_nc_u32 v21, v23, v5
	global_store_b32 v[0:1], v20, off
	global_load_b32 v20, v[2:3], off
	v_mad_u64_u32 v[4:5], null, v21, s8, s[12:13]
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v4, vcc_lo, s16, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s17, v5, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v20, v17, v18
	global_store_b32 v[2:3], v20, off
	global_load_b32 v4, v[4:5], off
	global_load_b32 v23, v[0:1], off
	v_sub_f32_e32 v5, 1.0, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v24, v5, v17
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v23, v24, v4
.LBB3_178:                              ; %Flow2557
                                        ;   in Loop: Header=BB3_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_or_b32 s23, s23, exec_lo
.LBB3_179:                              ; %Flow2574
                                        ;   in Loop: Header=BB3_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s2, s18, exec_lo
	s_and_b32 s3, s23, exec_lo
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr17
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr4
	s_or_b32 s4, s2, s3
.LBB3_180:                              ; %Flow2571
                                        ;   in Loop: Header=BB3_107 Depth=1
	s_and_not1_saveexec_b32 s19, s19
	s_cbranch_execz .LBB3_184
; %bb.181:                              ;   in Loop: Header=BB3_107 Depth=1
	v_cmp_lt_i32_e32 vcc_lo, -1, v18
	v_cmp_gt_i32_e64 s2, s10, v18
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s2
	s_mov_b32 s2, s4
	s_and_saveexec_b32 s22, s3
	s_xor_b32 s22, exec_lo, s22
	s_cbranch_execz .LBB3_183
; %bb.182:                              ;   in Loop: Header=BB3_107 Depth=1
	v_mul_lo_u32 v20, v18, s9
	s_waitcnt vmcnt(1)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v20, v4
	v_add_nc_u32_e32 v20, v20, v5
	v_mad_u64_u32 v[18:19], null, v4, s8, s[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v19, 31, v18
	v_lshlrev_b64 v[18:19], 2, v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v18, vcc_lo, s16, v18
	v_add_co_ci_u32_e32 v19, vcc_lo, s17, v19, vcc_lo
	global_load_b32 v4, v[0:1], off
	global_load_b32 v18, v[18:19], off
	v_sub_f32_e32 v19, v21, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v21, v19, v19, 1.0
	v_mul_f32_e32 v21, v15, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_div_scale_f32 v22, null, v9, v9, v21
	v_div_scale_f32 v25, vcc_lo, v21, v9, v21
	s_waitcnt vmcnt(2)
	v_rcp_f32_e32 v23, v22
	s_waitcnt_depctr 0xfff
	v_fma_f32 v24, -v22, v23, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v23, v24, v23
	v_mul_f32_e32 v24, v25, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v26, -v22, v24, v25
	v_fmac_f32_e32 v24, v26, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f32 v22, -v22, v24, v25
	v_cvt_f32_i32_e32 v25, v5
	v_sub_f32_e32 v17, v25, v17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v22, v22, v23, v24
	v_div_scale_f32 v26, vcc_lo, v17, v19, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v21, v22, v9, v21
	v_div_scale_f32 v22, null, v19, v19, v17
	v_mul_f32_e32 v23, 0x4f800000, v21
	v_cmp_gt_f32_e64 s2, 0xf800000, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v24, v22
	v_cndmask_b32_e64 v21, v21, v23, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sqrt_f32_e32 v23, v21
	s_waitcnt_depctr 0xfff
	v_fma_f32 v25, -v22, v24, 1.0
	v_dual_fmac_f32 v24, v25, v24 :: v_dual_add_nc_u32 v25, -1, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mul_f32 v27, v26, v24 :: v_dual_add_nc_u32 v28, 1, v23
	v_fma_f32 v29, -v25, v23, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v30, -v22, v27, v26
	v_fma_f32 v31, -v28, v23, v21
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_ge_f32_e64 s3, 0, v29
	v_fmac_f32_e32 v27, v30, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v23, v23, v25, s3
	v_cmp_lt_f32_e64 s3, 0, v31
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v22, -v22, v27, v26
	v_cndmask_b32_e64 v23, v23, v28, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v22, v22, v24, v27
	v_cmp_class_f32_e64 vcc_lo, v21, 0x260
	v_mul_f32_e32 v25, 0x37800000, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v17, v22, v19, v17
	v_cndmask_b32_e64 v23, v23, v25, s2
	s_or_b32 s2, s4, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v19, v23, v21, vcc_lo
	v_mul_f32_e32 v21, v17, v19
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v4, v21, v18
	global_store_b32 v[0:1], v4, off
	global_load_b32 v18, v[2:3], off
	v_mad_u64_u32 v[4:5], null, v20, s8, s[12:13]
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v4, vcc_lo, s16, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s17, v5, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v18, v17, v19
	global_store_b32 v[2:3], v18, off
	global_load_b32 v4, v[4:5], off
	global_load_b32 v23, v[0:1], off
	v_sub_f32_e32 v5, 1.0, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v24, v5, v19
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v23, v24, v4
.LBB3_183:                              ; %Flow2576
                                        ;   in Loop: Header=BB3_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s3, s4, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_or_b32 s4, s3, s2
.LBB3_184:                              ; %Flow2575
                                        ;   in Loop: Header=BB3_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s19
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s2, s18, exec_lo
	s_and_b32 s3, s4, exec_lo
	s_or_b32 s18, s2, s3
.LBB3_185:                              ; %Flow2570
                                        ;   in Loop: Header=BB3_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s15
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 s4, s18, exec_lo
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr17
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr22
.LBB3_186:                              ; %Flow2561
                                        ;   in Loop: Header=BB3_107 Depth=1
	s_and_not1_saveexec_b32 s14, s14
	s_cbranch_execz .LBB3_204
; %bb.187:                              ;   in Loop: Header=BB3_107 Depth=1
	s_waitcnt vmcnt(1)
	v_cmp_lt_i32_e32 vcc_lo, -1, v4
	v_cmp_gt_i32_e64 s2, s9, v4
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s3, vcc_lo, s2
	s_mov_b32 s2, s4
	s_and_saveexec_b32 s15, s3
	s_cbranch_execz .LBB3_203
; %bb.188:                              ;   in Loop: Header=BB3_107 Depth=1
	s_mov_b32 s3, s4
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
	s_mov_b32 s2, exec_lo
	v_cmpx_ne_u32_e64 v20, v18
	s_xor_b32 s18, exec_lo, s2
	s_cbranch_execz .LBB3_198
; %bb.189:                              ;   in Loop: Header=BB3_107 Depth=1
	v_cmp_gt_i32_e32 vcc_lo, 1, v20
	v_cmp_le_i32_e64 s2, s10, v20
	s_mov_b32 s22, s4
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s2, vcc_lo, s2
	s_and_saveexec_b32 s3, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_xor_b32 s19, exec_lo, s3
	s_cbranch_execz .LBB3_195
; %bb.190:                              ;   in Loop: Header=BB3_107 Depth=1
	s_mov_b32 s22, exec_lo
	v_cmpx_eq_u32_e32 0, v20
	s_cbranch_execz .LBB3_192
; %bb.191:                              ;   in Loop: Header=BB3_107 Depth=1
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[23:24], null, v4, s8, s[12:13]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v24, 31, v23
	v_lshlrev_b64 v[23:24], 2, v[23:24]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v23, vcc_lo, s16, v23
	v_add_co_ci_u32_e32 v24, vcc_lo, s17, v24, vcc_lo
	global_load_b32 v5, v[23:24], off
	global_load_b32 v23, v[0:1], off
	v_sub_f32_e32 v24, v21, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v24, v24, v24, 1.0
	v_mul_f32_e32 v24, v15, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f32 v25, null, v9, v9, v24
	v_rcp_f32_e32 v26, v25
	s_waitcnt_depctr 0xfff
	v_fma_f32 v27, -v25, v26, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v26, v27, v26
	v_div_scale_f32 v27, vcc_lo, v24, v9, v24
	v_mul_f32_e32 v28, v27, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v29, -v25, v28, v27
	v_fmac_f32_e32 v28, v29, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v25, -v25, v28, v27
	v_div_fmas_f32 v25, v25, v26, v28
	v_sub_f32_e32 v26, v22, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v24, v25, v9, v24
	v_div_scale_f32 v25, null, v26, v26, -v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v27, 0x4f800000, v24
	v_cmp_gt_f32_e64 s2, 0xf800000, v24
	v_rcp_f32_e32 v28, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v24, v24, v27, s2
	v_sqrt_f32_e32 v27, v24
	s_waitcnt_depctr 0xfff
	v_fma_f32 v29, -v25, v28, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v28, v29, v28
	v_div_scale_f32 v29, vcc_lo, -v19, v26, -v19
	v_add_nc_u32_e32 v30, -1, v27
	v_dual_mul_f32 v32, v29, v28 :: v_dual_add_nc_u32 v31, 1, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v33, -v30, v27, v24
	v_fma_f32 v34, -v31, v27, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v35, -v25, v32, v29
	v_cmp_ge_f32_e64 s3, 0, v33
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v32, v35, v28
	v_cndmask_b32_e64 v27, v27, v30, s3
	v_cmp_lt_f32_e64 s3, 0, v34
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v25, -v25, v32, v29
	v_cndmask_b32_e64 v27, v27, v31, s3
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_div_fmas_f32 v25, v25, v28, v32
	v_cmp_class_f32_e64 vcc_lo, v24, 0x260
	v_mul_f32_e32 v29, 0x37800000, v27
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v25, v25, v26, -v19
	v_cndmask_b32_e64 v27, v27, v29, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v25, 1.0, v25 :: v_dual_cndmask_b32 v24, v27, v24
	v_mul_f32_e32 v26, v24, v25
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v23, v26, v5
	global_store_b32 v[0:1], v23, off
	global_load_b32 v5, v[2:3], off
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v5, v24, v25
	global_store_b32 v[2:3], v5, off
.LBB3_192:                              ;   in Loop: Header=BB3_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	s_mov_b32 s2, s4
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
	s_mov_b32 s3, exec_lo
	v_cmpx_eq_u32_e64 s10, v20
	s_xor_b32 s22, exec_lo, s3
	s_cbranch_execz .LBB3_194
; %bb.193:                              ;   in Loop: Header=BB3_107 Depth=1
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[23:24], null, v18, s9, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v23, s8, s[12:13]
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v4, vcc_lo, s16, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, s17, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	global_load_b32 v23, v[0:1], off
	v_sub_f32_e32 v5, v21, v17
	v_fma_f32 v5, v5, v5, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v15, v5
	v_div_scale_f32 v17, null, v9, v9, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v18, v17
	s_waitcnt_depctr 0xfff
	v_fma_f32 v20, -v17, v18, 1.0
	v_fmac_f32_e32 v18, v20, v18
	v_div_scale_f32 v20, vcc_lo, v5, v9, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v21, v20, v18
	v_fma_f32 v24, -v17, v21, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v21, v24, v18
	v_fma_f32 v17, -v17, v21, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v17, v17, v18, v21
	v_sub_f32_e32 v18, v22, v19
	v_div_fixup_f32 v5, v17, v9, v5
	v_sub_f32_e32 v17, v13, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v19, 0x4f800000, v5
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v5
	v_cndmask_b32_e32 v5, v5, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v21, v5
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v24, -1, v21
	v_div_scale_f32 v20, null, v18, v18, v17
	v_fma_f32 v26, -v24, v21, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v19, v20
	v_cmp_ge_f32_e64 s3, 0, v26
	s_waitcnt_depctr 0xfff
	v_fma_f32 v22, -v20, v19, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v19, v22, v19
	v_div_scale_f32 v22, s2, v17, v18, v17
	v_dual_mul_f32 v28, v22, v19 :: v_dual_add_nc_u32 v25, 1, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v27, -v25, v21, v5
	v_cndmask_b32_e64 v21, v21, v24, s3
	v_fma_f32 v24, -v20, v28, v22
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_f32_e64 s3, 0, v27
	v_fmac_f32_e32 v28, v24, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v21, v21, v25, s3
	v_fma_f32 v20, -v20, v28, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v24, 0x37800000, v21
	v_cndmask_b32_e32 v21, v21, v24, vcc_lo
	s_mov_b32 vcc_lo, s2
	s_or_b32 s2, s4, exec_lo
	v_div_fmas_f32 v19, v20, v19, v28
	v_cmp_class_f32_e64 vcc_lo, v5, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v17, v19, v18, v17
	v_cndmask_b32_e32 v5, v21, v5, vcc_lo
	v_mul_f32_e32 v24, v5, v17
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v23, v24, v4
.LBB3_194:                              ; %Flow2581
                                        ;   in Loop: Header=BB3_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s22
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s3, s4, exec_lo
	s_and_b32 s2, s2, exec_lo
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr17
                                        ; implicit-def: $vgpr20
                                        ; implicit-def: $vgpr19
                                        ; implicit-def: $vgpr22
                                        ; implicit-def: $vgpr4
                                        ; implicit-def: $vgpr18
	s_or_b32 s22, s3, s2
.LBB3_195:                              ; %Flow2580
                                        ;   in Loop: Header=BB3_107 Depth=1
	s_and_not1_saveexec_b32 s19, s19
	s_cbranch_execz .LBB3_197
; %bb.196:                              ;   in Loop: Header=BB3_107 Depth=1
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[23:24], null, v18, s9, v[4:5]
	v_sub_f32_e32 v17, v21, v17
	s_or_b32 s22, s22, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v17, v17, v17, 1.0
	v_mad_u64_u32 v[24:25], null, v23, s8, s[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v17, v15, v17
	v_ashrrev_i32_e32 v25, 31, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f32 v21, null, v9, v9, v17
	v_lshlrev_b64 v[23:24], 2, v[24:25]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v23, vcc_lo, s16, v23
	v_add_co_ci_u32_e32 v24, vcc_lo, s17, v24, vcc_lo
	v_div_scale_f32 v25, vcc_lo, v17, v9, v17
	global_load_b32 v5, v[0:1], off
	global_load_b32 v18, v[23:24], off
	v_rcp_f32_e32 v23, v21
	s_waitcnt_depctr 0xfff
	v_fma_f32 v24, -v21, v23, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v23, v24, v23
	v_mul_f32_e32 v24, v25, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v26, -v21, v24, v25
	v_fmac_f32_e32 v24, v26, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fma_f32 v21, -v21, v24, v25
	v_cvt_f32_i32_e32 v25, v20
	v_div_fmas_f32 v21, v21, v23, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_div_fixup_f32 v17, v21, v9, v17
	v_sub_f32_e32 v22, v22, v19
	v_sub_f32_e32 v19, v25, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v23, 0x4f800000, v17
	v_cmp_gt_f32_e64 s2, 0xf800000, v17
	v_div_scale_f32 v21, null, v22, v22, v19
	v_div_scale_f32 v26, vcc_lo, v19, v22, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v17, v17, v23, s2
	v_rcp_f32_e32 v24, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v23, v17
	s_waitcnt_depctr 0xfff
	v_fma_f32 v25, -v21, v24, 1.0
	v_add_nc_u32_e32 v28, 1, v23
	v_dual_fmac_f32 v24, v25, v24 :: v_dual_add_nc_u32 v25, -1, v23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v31, -v28, v23, v17
	v_mul_f32_e32 v27, v26, v24
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v29, -v25, v23, v17
	v_fma_f32 v30, -v21, v27, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ge_f32_e64 s3, 0, v29
	v_fmac_f32_e32 v27, v30, v24
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v23, v23, v25, s3
	v_cmp_lt_f32_e64 s3, 0, v31
	v_fma_f32 v21, -v21, v27, v26
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v23, v23, v28, s3
	v_div_fmas_f32 v21, v21, v24, v27
	v_cmp_class_f32_e64 vcc_lo, v17, 0x260
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v25, 0x37800000, v23
	v_div_fixup_f32 v19, v21, v22, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v23, v23, v25, s2
	v_cndmask_b32_e32 v21, v23, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v17, v21, v19
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v5, v17, v18
	global_store_b32 v[0:1], v5, off
	global_load_b32 v22, v[2:3], off
	v_mad_u64_u32 v[17:18], null, v20, s9, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v17, s8, s[12:13]
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v4, vcc_lo, s16, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s17, v5, vcc_lo
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v22, v21, v19
	global_store_b32 v[2:3], v22, off
	global_load_b32 v4, v[4:5], off
	global_load_b32 v23, v[0:1], off
	v_sub_f32_e32 v5, 1.0, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v24, v21, v5
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v23, v24, v4
.LBB3_197:                              ; %Flow2582
                                        ;   in Loop: Header=BB3_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s19
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s2, s4, exec_lo
	s_and_b32 s3, s22, exec_lo
                                        ; implicit-def: $vgpr18
                                        ; implicit-def: $vgpr21
                                        ; implicit-def: $vgpr17
                                        ; implicit-def: $vgpr4
	s_or_b32 s3, s2, s3
.LBB3_198:                              ; %Flow2579
                                        ;   in Loop: Header=BB3_107 Depth=1
	s_and_not1_saveexec_b32 s18, s18
	s_cbranch_execz .LBB3_202
; %bb.199:                              ;   in Loop: Header=BB3_107 Depth=1
	v_cmp_lt_i32_e32 vcc_lo, -1, v18
	v_cmp_gt_i32_e64 s2, s10, v18
                                        ; implicit-def: $vgpr24
                                        ; implicit-def: $vgpr23
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 s22, vcc_lo, s2
	s_mov_b32 s2, s3
	s_and_saveexec_b32 s19, s22
	s_cbranch_execz .LBB3_201
; %bb.200:                              ;   in Loop: Header=BB3_107 Depth=1
	v_mad_u64_u32 v[19:20], null, v18, s9, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, v19, s8, s[12:13]
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	v_add_co_u32 v4, vcc_lo, s16, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e32 v5, vcc_lo, s17, v5, vcc_lo
	global_load_b32 v4, v[4:5], off
	global_load_b32 v23, v[0:1], off
	v_sub_f32_e32 v5, v21, v17
	v_fma_f32 v5, v5, v5, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v5, v15, v5
	v_div_scale_f32 v17, null, v9, v9, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v18, v17
	s_waitcnt_depctr 0xfff
	v_fma_f32 v19, -v17, v18, 1.0
	v_fmac_f32_e32 v18, v19, v18
	v_div_scale_f32 v19, vcc_lo, v5, v9, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v20, v19, v18
	v_fma_f32 v21, -v17, v20, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v20, v21, v18
	v_fma_f32 v17, -v17, v20, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v17, v17, v18, v20
	v_div_fixup_f32 v5, v17, v9, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v17, 0x4f800000, v5
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v5
	v_cndmask_b32_e32 v5, v5, v17, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v17, v5
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v18, -1, v17
	v_add_nc_u32_e32 v19, 1, v17
	v_fma_f32 v20, -v18, v17, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v21, -v19, v17, v5
	v_cmp_ge_f32_e64 s2, 0, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v17, v17, v18, s2
	v_cmp_lt_f32_e64 s2, 0, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v17, v17, v19, s2
	s_or_b32 s2, s3, exec_lo
	v_mul_f32_e32 v18, 0x37800000, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v17, v17, v18, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v5, 0x260
	v_cndmask_b32_e32 v24, v17, v5, vcc_lo
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v23, v24, v4
.LBB3_201:                              ; %Flow2584
                                        ;   in Loop: Header=BB3_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s19
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s3, s3, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_or_b32 s3, s3, s2
.LBB3_202:                              ; %Flow2583
                                        ;   in Loop: Header=BB3_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s18
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s2, s4, exec_lo
	s_and_b32 s3, s3, exec_lo
	s_or_b32 s2, s2, s3
.LBB3_203:                              ; %Flow2578
                                        ;   in Loop: Header=BB3_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s15
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_and_not1_b32 s3, s4, exec_lo
	s_and_b32 s2, s2, exec_lo
	s_or_b32 s4, s3, s2
.LBB3_204:                              ; %Flow2577
                                        ;   in Loop: Header=BB3_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	s_and_saveexec_b32 s2, s4
	s_cbranch_execz .LBB3_206
; %bb.205:                              ; %.sink.split2404
                                        ;   in Loop: Header=BB3_107 Depth=1
	s_waitcnt vmcnt(0)
	global_store_b32 v[0:1], v23, off
	global_load_b32 v4, v[2:3], off
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v4, v24, v4
	global_store_b32 v[2:3], v4, off
.LBB3_206:                              ;   in Loop: Header=BB3_107 Depth=1
	s_or_b32 exec_lo, exec_lo, s2
	s_add_i32 s12, s12, 1
	s_add_u32 s20, s20, 4
	s_addc_u32 s21, s21, 0
	s_cmp_eq_u32 s8, s12
	s_cbranch_scc0 .LBB3_107
.LBB3_207:                              ; %.loopexit
	s_or_b32 exec_lo, exec_lo, s13
	global_load_b32 v4, v[0:1], off
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v4, s6, v4
	global_store_b32 v[0:1], v4, off
	global_load_b32 v0, v[2:3], off
	s_waitcnt vmcnt(0)
	v_mul_f32_e32 v0, s6, v0
	global_store_b32 v[2:3], v0, off
.LBB3_208:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z25Ax_cone_mf_gpu_kernel_newPfS_S_ffS_S_ffffiiiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 84
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 42
		.amdhsa_next_free_sgpr 28
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end3:
	.size	_Z25Ax_cone_mf_gpu_kernel_newPfS_S_ffS_S_ffffiiiii, .Lfunc_end3-_Z25Ax_cone_mf_gpu_kernel_newPfS_S_ffS_S_ffffiiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 22932
; NumSgprs: 30
; NumVgprs: 42
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 5
; NumSGPRsForWavesPerEU: 30
; NumVGPRsForWavesPerEU: 42
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         60
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     by_value
      - .offset:         68
        .size:           4
        .value_kind:     by_value
      - .offset:         72
        .size:           4
        .value_kind:     by_value
      - .offset:         76
        .size:           4
        .value_kind:     by_value
      - .offset:         80
        .size:           4
        .value_kind:     by_value
      - .offset:         84
        .size:           4
        .value_kind:     by_value
      - .offset:         88
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 92
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z26Atx_cone_mf_gpu_new_kernelPfS_S_ffS_S_ffffffiiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     26
    .sgpr_spill_count: 0
    .symbol:         _Z26Atx_cone_mf_gpu_new_kernelPfS_S_ffS_S_ffffffiiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     46
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 16
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8set2zeroPfii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z8set2zeroPfii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     4
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 20
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6scalexPfiif
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z6scalexPfiif.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     4
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         60
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     by_value
      - .offset:         68
        .size:           4
        .value_kind:     by_value
      - .offset:         72
        .size:           4
        .value_kind:     by_value
      - .offset:         76
        .size:           4
        .value_kind:     by_value
      - .offset:         80
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 84
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z25Ax_cone_mf_gpu_kernel_newPfS_S_ffS_S_ffffiiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     30
    .sgpr_spill_count: 0
    .symbol:         _Z25Ax_cone_mf_gpu_kernel_newPfS_S_ffS_S_ffffiiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     42
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
