
__device__ void HSV2RGB(float h, float s, float v, float &r, float &g, float &b) {
		if(h < 0) {
			r=v;
			g=v;
			b=v;
			return;
		}
		h *= .0166666666666667; // convert from 360 to 0-6;		
		int i = (int) floor(h);
		float f = h - i;
		f = (!(i&1)) ?  1-f : f; // if even
		float m = v * (1-s); 
		float n = v * (1-s * f); 
		switch(i) {
			case 6:
			case 0:
				r = v;
				g= n;
				b = m;
				return;
			case 1:
				r = n;
				g= v;
				b = m;
				return;
			case 2:
				r = m;
				g= v;
				b = n;
				return;
			case 3:
				r = m;
				g= n;
				b = v;
				return;

			case 4:
				r = n;
				g= m;
				b = v;
				return;
			case 5:
				r = v;
				g= n;
				b = m;
				return;
		}

	}



__global__ void gpu_calcColor_kernel(int pointCnt, float* pixels, float minZ, float diffZ, float minC1, float minC2, float minC3, float diffC1, float diffC2, float diffC3, bool hsv, bool quads, float* colors) {

	int i = (blockIdx.x * blockDim.x) + threadIdx.x;	
	
	
	bool validPoint = ((i > 0) && (i < pointCnt))? true : false;
	i *=3;	
	float z = validPoint ? pixels[i+2] : 0.0;
	if(z != 0.0) { // only equal to 0.0 if set as invalid in cloud contructor	
		float distZ = z - minZ;
		float percent = distZ/diffZ;
		percent = percent<=0.0 ? 0.01 : percent;
		percent = percent>=1.0 ? 1.0 : percent;
	
		float r; 	
		float g; 
		float b;
		if(hsv) {
			if(percent == 0.0) {
				HSV2RGB(minC1 , minC2, minC3 , r,g,b); 		
				
			} else {
				HSV2RGB(minC1 + percent * diffC1, minC2 + percent * diffC2, minC3 + percent * diffC3, r,g,b); 		
			}
		} else {
			r= minC1 + percent * diffC1;
			g= minC2 + percent * diffC2;
			b= minC3 + percent * diffC3;
		}
		
		if(quads) {
			i*=4;
			colors[i++] = r;
			colors[i++] = g;
			colors[i++] = b;

			colors[i++] = r;
			colors[i++] = g;
			colors[i++] = b;

			colors[i++] = r;
			colors[i++] = g;
			colors[i++] = b;

			colors[i++] = r;
			colors[i++] = g;
			colors[i] = b;
			
		} else {
			colors[i++] = r;
			colors[i++] = g;
			colors[i] = b;
		}



	}

} 

extern "C" void gpu_calcColor(int pointCnt, float* pixels, float minZ, float diffZ, float minC1, float minC2, float minC3, float diffC1, float diffC2, float diffC3, bool hsv, bool quads, float* colors)
{
	int theadsPerBlock = 256;
	int blocks = (int) ceilf(pointCnt/(float) theadsPerBlock);
	gpu_calcColor_kernel <<<blocks,theadsPerBlock>>> (pointCnt, pixels, minZ, diffZ, minC1, minC2, minC3, diffC1, diffC2, diffC3, hsv, quads, colors);

};


	.file	"tmpxft_00313a49_00000000-6_pointCloudRender.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2012:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2012:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z7HSV2RGBfffRfS_S_
	.type	_Z7HSV2RGBfffRfS_S_, @function
_Z7HSV2RGBfffRfS_S_:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2008:
	.size	_Z7HSV2RGBfffRfS_S_, .-_Z7HSV2RGBfffRfS_S_
	.globl	_Z53__device_stub__Z20gpu_calcColor_kerneliPfffffffffbbS_iPfffffffffbbS_
	.type	_Z53__device_stub__Z20gpu_calcColor_kerneliPfffffffffbbS_iPfffffffffbbS_, @function
_Z53__device_stub__Z20gpu_calcColor_kerneliPfffffffffbbS_iPfffffffffbbS_:
.LFB2034:
	.cfi_startproc
	endbr64
	subq	$248, %rsp
	.cfi_def_cfa_offset 256
	movl	%edi, 60(%rsp)
	leaq	80(%rsp), %rdi
	movq	%rsi, 48(%rsp)
	leaq	92(%rsp), %rsi
	movb	%dl, 16(%rsp)
	leaq	64(%rsp), %rdx
	movb	%cl, 12(%rsp)
	leaq	72(%rsp), %rcx
	movq	%r8, (%rsp)
	movss	%xmm0, 56(%rsp)
	movss	%xmm1, 44(%rsp)
	movss	%xmm2, 40(%rsp)
	movss	%xmm3, 36(%rsp)
	movss	%xmm4, 32(%rsp)
	movss	%xmm5, 28(%rsp)
	movss	%xmm6, 24(%rsp)
	movss	%xmm7, 20(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 232(%rsp)
	xorl	%eax, %eax
	leaq	60(%rsp), %rax
	movl	$1, 88(%rsp)
	movq	%rax, 128(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	44(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 216(%rsp)
	movq	%rsp, %rax
	movq	%rax, 224(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 80(%rsp)
	movq	%rax, 92(%rsp)
	movl	$1, 100(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	72(%rsp)
	.cfi_def_cfa_offset 264
	leaq	_Z20gpu_calcColor_kerneliPfffffffffbbS_(%rip), %rdi
	pushq	72(%rsp)
	.cfi_def_cfa_offset 272
	movq	108(%rsp), %rcx
	movl	116(%rsp), %r8d
	movq	96(%rsp), %rsi
	movl	104(%rsp), %edx
	leaq	144(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 264
	popq	%rdx
	.cfi_def_cfa_offset 256
.L4:
	movq	232(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$248, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2034:
	.size	_Z53__device_stub__Z20gpu_calcColor_kerneliPfffffffffbbS_iPfffffffffbbS_, .-_Z53__device_stub__Z20gpu_calcColor_kerneliPfffffffffbbS_iPfffffffffbbS_
	.globl	_Z20gpu_calcColor_kerneliPfffffffffbbS_
	.type	_Z20gpu_calcColor_kerneliPfffffffffbbS_, @function
_Z20gpu_calcColor_kerneliPfffffffffbbS_:
.LFB2035:
	.cfi_startproc
	endbr64
	movzbl	%cl, %ecx
	movzbl	%dl, %edx
	jmp	_Z53__device_stub__Z20gpu_calcColor_kerneliPfffffffffbbS_iPfffffffffbbS_
	.cfi_endproc
.LFE2035:
	.size	_Z20gpu_calcColor_kerneliPfffffffffbbS_, .-_Z20gpu_calcColor_kerneliPfffffffffbbS_
	.globl	gpu_calcColor
	.type	gpu_calcColor, @function
gpu_calcColor:
.LFB2009:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movd	%xmm0, %r15d
	cvtsi2ssl	%edi, %xmm0
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	movq	%r8, %r14
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rsi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movl	%edi, %r12d
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	movl	%ecx, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movl	%edx, %ebx
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	mulss	.LC0(%rip), %xmm0
	movss	%xmm1, 28(%rsp)
	movss	%xmm2, 24(%rsp)
	movss	%xmm3, 20(%rsp)
	movss	%xmm4, 16(%rsp)
	movss	%xmm5, 12(%rsp)
	movss	%xmm6, 8(%rsp)
	movss	%xmm7, 4(%rsp)
	call	ceilf@PLT
	movl	$16777217, %edx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	cvttss2sil	%xmm0, %eax
	salq	$8, %rdx
	movl	$1, %ecx
	movl	%eax, 40(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 44(%rsp)
	movq	40(%rsp), %rdi
	movl	48(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	movss	4(%rsp), %xmm7
	movss	8(%rsp), %xmm6
	testl	%eax, %eax
	movss	12(%rsp), %xmm5
	movss	16(%rsp), %xmm4
	movss	20(%rsp), %xmm3
	movss	24(%rsp), %xmm2
	movss	28(%rsp), %xmm1
	jne	.L10
	addq	$72, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 56
	movzbl	%bpl, %ecx
	movzbl	%bl, %edx
	movq	%r14, %r8
	popq	%rbx
	.cfi_def_cfa_offset 48
	movd	%r15d, %xmm0
	popq	%rbp
	.cfi_def_cfa_offset 40
	movq	%r13, %rsi
	movl	%r12d, %edi
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z53__device_stub__Z20gpu_calcColor_kerneliPfffffffffbbS_iPfffffffffbbS_
.L10:
	.cfi_restore_state
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2009:
	.size	gpu_calcColor, .-gpu_calcColor
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC1:
	.string	"_Z20gpu_calcColor_kerneliPfffffffffbbS_"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2037:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC1(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z20gpu_calcColor_kerneliPfffffffffbbS_(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2037:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst4,"aM",@progbits,4
	.align 4
.LC0:
	.long	998244352
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>

__device__ void HSV2RGB(float h, float s, float v, float &r, float &g, float &b) {
		if(h < 0) {
			r=v;
			g=v;
			b=v;
			return;
		}
		h *= .0166666666666667; // convert from 360 to 0-6;		
		int i = (int) floor(h);
		float f = h - i;
		f = (!(i&1)) ?  1-f : f; // if even
		float m = v * (1-s); 
		float n = v * (1-s * f); 
		switch(i) {
			case 6:
			case 0:
				r = v;
				g= n;
				b = m;
				return;
			case 1:
				r = n;
				g= v;
				b = m;
				return;
			case 2:
				r = m;
				g= v;
				b = n;
				return;
			case 3:
				r = m;
				g= n;
				b = v;
				return;

			case 4:
				r = n;
				g= m;
				b = v;
				return;
			case 5:
				r = v;
				g= n;
				b = m;
				return;
		}

	}



__global__ void gpu_calcColor_kernel(int pointCnt, float* pixels, float minZ, float diffZ, float minC1, float minC2, float minC3, float diffC1, float diffC2, float diffC3, bool hsv, bool quads, float* colors) {

	int i = (blockIdx.x * blockDim.x) + threadIdx.x;	
	
	
	bool validPoint = ((i > 0) && (i < pointCnt))? true : false;
	i *=3;	
	float z = validPoint ? pixels[i+2] : 0.0;
	if(z != 0.0) { // only equal to 0.0 if set as invalid in cloud contructor	
		float distZ = z - minZ;
		float percent = distZ/diffZ;
		percent = percent<=0.0 ? 0.01 : percent;
		percent = percent>=1.0 ? 1.0 : percent;
	
		float r; 	
		float g; 
		float b;
		if(hsv) {
			if(percent == 0.0) {
				HSV2RGB(minC1 , minC2, minC3 , r,g,b); 		
				
			} else {
				HSV2RGB(minC1 + percent * diffC1, minC2 + percent * diffC2, minC3 + percent * diffC3, r,g,b); 		
			}
		} else {
			r= minC1 + percent * diffC1;
			g= minC2 + percent * diffC2;
			b= minC3 + percent * diffC3;
		}
		
		if(quads) {
			i*=4;
			colors[i++] = r;
			colors[i++] = g;
			colors[i++] = b;

			colors[i++] = r;
			colors[i++] = g;
			colors[i++] = b;

			colors[i++] = r;
			colors[i++] = g;
			colors[i++] = b;

			colors[i++] = r;
			colors[i++] = g;
			colors[i] = b;
			
		} else {
			colors[i++] = r;
			colors[i++] = g;
			colors[i] = b;
		}



	}

} 

extern "C" void gpu_calcColor(int pointCnt, float* pixels, float minZ, float diffZ, float minC1, float minC2, float minC3, float diffC1, float diffC2, float diffC3, bool hsv, bool quads, float* colors)
{
	int theadsPerBlock = 256;
	int blocks = (int) ceilf(pointCnt/(float) theadsPerBlock);
	gpu_calcColor_kernel <<<blocks,theadsPerBlock>>> (pointCnt, pixels, minZ, diffZ, minC1, minC2, minC3, diffC1, diffC2, diffC3, hsv, quads, colors);

};


	.text
	.file	"pointCloudRender.hip"
	.globl	_Z35__device_stub__gpu_calcColor_kerneliPfffffffffbbS_ # -- Begin function _Z35__device_stub__gpu_calcColor_kerneliPfffffffffbbS_
	.type	_Z35__device_stub__gpu_calcColor_kerneliPfffffffffbbS_,@function
_Z35__device_stub__gpu_calcColor_kerneliPfffffffffbbS_: # @_Z35__device_stub__gpu_calcColor_kerneliPfffffffffbbS_
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$216, %rsp
	.cfi_def_cfa_offset 272
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	leaq	44(%rsp), %rax
	movl	%edi, (%rax)
	leaq	72(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movss	%xmm0, (%rsi)
	leaq	36(%rsp), %r9
	movss	%xmm1, (%r9)
	leaq	32(%rsp), %r10
	movss	%xmm2, (%r10)
	leaq	28(%rsp), %r11
	movss	%xmm3, (%r11)
	leaq	24(%rsp), %r14
	movss	%xmm4, (%r14)
	leaq	20(%rsp), %r15
	movss	%xmm5, (%r15)
	leaq	16(%rsp), %r12
	movss	%xmm6, (%r12)
	leaq	12(%rsp), %r13
	movss	%xmm7, (%r13)
	leaq	11(%rsp), %rbp
	movb	%dl, (%rbp)
	leaq	10(%rsp), %rdx
	movb	%cl, (%rdx)
	leaq	64(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	112(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%r9, 24(%rbx)
	movq	%r10, 32(%rbx)
	movq	%r11, 40(%rbx)
	movq	%r14, 48(%rbx)
	movq	%r15, 56(%rbx)
	movq	%r12, 64(%rbx)
	movq	%r13, 72(%rbx)
	movq	%rbp, 80(%rbx)
	movq	%rdx, 88(%rbx)
	movq	%rcx, 96(%rbx)
	leaq	96(%rsp), %r14
	leaq	80(%rsp), %r15
	leaq	56(%rsp), %r12
	leaq	48(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z20gpu_calcColor_kerneliPfffffffffbbS_, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$232, %rsp
	.cfi_adjust_cfa_offset -232
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z35__device_stub__gpu_calcColor_kerneliPfffffffffbbS_, .Lfunc_end0-_Z35__device_stub__gpu_calcColor_kerneliPfffffffffbbS_
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst4,"aM",@progbits,4
	.p2align	2, 0x0                          # -- Begin function gpu_calcColor
.LCPI1_0:
	.long	0x3b800000                      # float 0.00390625
	.text
	.globl	gpu_calcColor
	.type	gpu_calcColor,@function
gpu_calcColor:                          # @gpu_calcColor
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$32, %rsp
	.cfi_def_cfa_offset 80
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movq	%r8, %rbx
	movl	%ecx, %ebp
	movl	%edx, %r14d
	movss	%xmm7, 28(%rsp)                 # 4-byte Spill
	movss	%xmm6, 24(%rsp)                 # 4-byte Spill
	movss	%xmm5, 20(%rsp)                 # 4-byte Spill
	movss	%xmm4, 16(%rsp)                 # 4-byte Spill
	movss	%xmm3, 12(%rsp)                 # 4-byte Spill
	movss	%xmm2, 8(%rsp)                  # 4-byte Spill
	movss	%xmm1, 4(%rsp)                  # 4-byte Spill
	movl	%edi, %r15d
	xorps	%xmm1, %xmm1
	cvtsi2ss	%edi, %xmm1
	movss	%xmm0, (%rsp)                   # 4-byte Spill
	movq	%rsi, %r12
	mulss	.LCPI1_0(%rip), %xmm1
	movaps	%xmm1, %xmm0
	callq	ceilf@PLT
	cvttss2si	%xmm0, %edi
	btsq	$32, %rdi
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$256, %rdx                      # imm = 0x100
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB1_2
# %bb.1:
	addq	$32, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.LBB1_2:
	.cfi_def_cfa_offset 80
	movzbl	%r14b, %edx
	movzbl	%bpl, %ecx
	movl	%r15d, %edi
	movq	%r12, %rsi
	movss	(%rsp), %xmm0                   # 4-byte Reload
                                        # xmm0 = mem[0],zero,zero,zero
	movss	4(%rsp), %xmm1                  # 4-byte Reload
                                        # xmm1 = mem[0],zero,zero,zero
	movss	8(%rsp), %xmm2                  # 4-byte Reload
                                        # xmm2 = mem[0],zero,zero,zero
	movss	12(%rsp), %xmm3                 # 4-byte Reload
                                        # xmm3 = mem[0],zero,zero,zero
	movss	16(%rsp), %xmm4                 # 4-byte Reload
                                        # xmm4 = mem[0],zero,zero,zero
	movss	20(%rsp), %xmm5                 # 4-byte Reload
                                        # xmm5 = mem[0],zero,zero,zero
	movss	24(%rsp), %xmm6                 # 4-byte Reload
                                        # xmm6 = mem[0],zero,zero,zero
	movss	28(%rsp), %xmm7                 # 4-byte Reload
                                        # xmm7 = mem[0],zero,zero,zero
	movq	%rbx, %r8
	addq	$32, %rsp
	.cfi_def_cfa_offset 48
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	jmp	_Z35__device_stub__gpu_calcColor_kerneliPfffffffffbbS_ # TAILCALL
.Lfunc_end1:
	.size	gpu_calcColor, .Lfunc_end1-gpu_calcColor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z20gpu_calcColor_kerneliPfffffffffbbS_, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z20gpu_calcColor_kerneliPfffffffffbbS_,@object # @_Z20gpu_calcColor_kerneliPfffffffffbbS_
	.section	.rodata,"a",@progbits
	.globl	_Z20gpu_calcColor_kerneliPfffffffffbbS_
	.p2align	3, 0x0
_Z20gpu_calcColor_kerneliPfffffffffbbS_:
	.quad	_Z35__device_stub__gpu_calcColor_kerneliPfffffffffbbS_
	.size	_Z20gpu_calcColor_kerneliPfffffffffbbS_, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z20gpu_calcColor_kerneliPfffffffffbbS_"
	.size	.L__unnamed_1, 40

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z35__device_stub__gpu_calcColor_kerneliPfffffffffbbS_
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z20gpu_calcColor_kerneliPfffffffffbbS_
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z20gpu_calcColor_kerneliPfffffffffbbS_ ; -- Begin function _Z20gpu_calcColor_kerneliPfffffffffbbS_
	.globl	_Z20gpu_calcColor_kerneliPfffffffffbbS_
	.p2align	8
	.type	_Z20gpu_calcColor_kerneliPfffffffffbbS_,@function
_Z20gpu_calcColor_kerneliPfffffffffbbS_: ; @_Z20gpu_calcColor_kerneliPfffffffffbbS_
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x4c
	s_load_b32 s3, s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[3:4], null, s15, s2, v[0:1]
	v_mov_b32_e32 v0, 0
	v_cmp_lt_i32_e32 vcc_lo, 0, v3
	v_cmp_gt_i32_e64 s2, s3, v3
	v_lshl_add_u32 v4, v3, 1, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_and_b32 s3, vcc_lo, s2
	s_and_saveexec_b32 s2, s3
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_load_b64 s[4:5], s[0:1], 0x8
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[0:1], 2, v[4:5]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s4, v0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo
	global_load_b32 v0, v[0:1], off offset:8
.LBB0_2:
	s_or_b32 exec_lo, exec_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	s_waitcnt vmcnt(0)
	v_cmpx_neq_f32_e32 0, v0
	s_cbranch_execz .LBB0_32
; %bb.3:
	s_clause 0x1
	s_load_b256 s[4:11], s[0:1], 0x10
	s_load_b32 s2, s[0:1], 0x30
	s_mov_b32 s3, 0
	s_waitcnt lgkmcnt(0)
	v_subrev_f32_e32 v0, s4, v0
	s_bitcmp0_b32 s2, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v1, null, s5, s5, v0
	v_div_scale_f32 v6, vcc_lo, v0, s5, v0
	v_rcp_f32_e32 v2, v1
	s_waitcnt_depctr 0xfff
	v_fma_f32 v5, -v1, v2, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v2, v5, v2
	v_mul_f32_e32 v5, v6, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v7, -v1, v5, v6
	v_fmac_f32_e32 v5, v7, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v1, -v1, v5, v6
	v_div_fmas_f32 v1, v1, v2, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v0, v1, s5, v0
	v_cmp_nge_f32_e32 vcc_lo, 0, v0
	v_cndmask_b32_e32 v0, 0x3c23d70a, v0, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cmp_nle_f32_e32 vcc_lo, 1.0, v0
	v_cndmask_b32_e32 v6, 1.0, v0, vcc_lo
	v_fma_f32 v0, v6, s9, s6
	v_fma_f32 v5, v6, s11, s8
	s_cbranch_scc0 .LBB0_5
; %bb.4:
	v_fma_f32 v1, v6, s10, s7
	v_fma_f32 v2, v6, s11, s8
	s_branch .LBB0_6
.LBB0_5:
	s_mov_b32 s3, -1
.LBB0_6:                                ; %Flow137
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccnz .LBB0_26
; %bb.7:
	v_mov_b32_e32 v1, v5
	v_mov_b32_e32 v2, v5
	s_mov_b32 s3, exec_lo
	v_cmpx_ngt_f32_e32 0, v0
	s_cbranch_execz .LBB0_25
; %bb.8:                                ; %NodeBlock124
	v_cvt_f64_f32_e32 v[0:1], v0
	s_mov_b32 s4, 0x1111111b
	s_mov_b32 s5, 0x3f911111
	v_fma_f32 v6, v6, s10, s7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f64 v[0:1], v[0:1], s[4:5]
	s_mov_b32 s4, exec_lo
	v_cvt_f32_f64_e32 v0, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_floor_f32_e32 v1, v0
	v_cvt_i32_f32_e32 v7, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v1, v7
	v_dual_sub_f32 v0, v0, v1 :: v_dual_and_b32 v1, 1, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_f32_e32 v2, 1.0, v0
	v_cmp_eq_u32_e32 vcc_lo, 0, v1
	v_sub_f32_e32 v1, 1.0, v6
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v0, v2, vcc_lo
	v_fma_f32 v2, -v6, v0, 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v0, v5, v1
                                        ; implicit-def: $vgpr6
                                        ; implicit-def: $vgpr1
	v_mul_f32_e32 v2, v5, v2
	v_cmpx_lt_i32_e32 2, v7
	s_xor_b32 s4, exec_lo, s4
	s_cbranch_execz .LBB0_16
; %bb.9:                                ; %NodeBlock122
	s_mov_b32 s5, exec_lo
                                        ; implicit-def: $vgpr6
                                        ; implicit-def: $vgpr1
	v_cmpx_lt_i32_e32 3, v7
	s_xor_b32 s5, exec_lo, s5
	s_cbranch_execz .LBB0_13
; %bb.10:                               ; %LeafBlock120
	v_dual_mov_b32 v6, v0 :: v_dual_mov_b32 v1, v2
	s_mov_b32 s6, exec_lo
	v_cmpx_eq_u32_e32 4, v7
; %bb.11:
	v_dual_mov_b32 v6, v5 :: v_dual_mov_b32 v1, v0
	v_mov_b32_e32 v5, v2
; %bb.12:                               ; %Flow126
	s_or_b32 exec_lo, exec_lo, s6
                                        ; implicit-def: $vgpr2
                                        ; implicit-def: $vgpr0
.LBB0_13:                               ; %Flow127
	s_and_not1_saveexec_b32 s5, s5
; %bb.14:
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v6, v5 :: v_dual_mov_b32 v1, v2
	v_mov_b32_e32 v5, v0
; %bb.15:                               ; %Flow128
	s_or_b32 exec_lo, exec_lo, s5
                                        ; implicit-def: $vgpr0
                                        ; implicit-def: $vgpr2
                                        ; implicit-def: $vgpr7
.LBB0_16:                               ; %Flow132
	s_and_not1_saveexec_b32 s4, s4
	s_cbranch_execz .LBB0_24
; %bb.17:                               ; %NodeBlock
	s_mov_b32 s5, exec_lo
	v_cmpx_lt_i32_e32 1, v7
	s_xor_b32 s5, exec_lo, s5
; %bb.18:
                                        ; implicit-def: $vgpr7
; %bb.19:                               ; %Flow130
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_saveexec_b32 s5, s5
	s_cbranch_execz .LBB0_23
; %bb.20:                               ; %LeafBlock
	v_mov_b32_e32 v1, v2
	s_mov_b32 s6, exec_lo
	v_cmpx_eq_u32_e32 1, v7
; %bb.21:
	v_mov_b32_e32 v1, v5
	v_mov_b32_e32 v5, v2
; %bb.22:                               ; %Flow129
	s_or_b32 exec_lo, exec_lo, s6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mov_b32_e32 v6, v5
	v_dual_mov_b32 v2, v0 :: v_dual_mov_b32 v5, v1
	s_delay_alu instid0(VALU_DEP_2)
	v_mov_b32_e32 v0, v6
.LBB0_23:                               ; %Flow131
	s_or_b32 exec_lo, exec_lo, s5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v1, v5
	v_mov_b32_e32 v5, v0
.LBB0_24:                               ; %Flow133
	s_or_b32 exec_lo, exec_lo, s4
	s_delay_alu instid0(VALU_DEP_1)
	v_dual_mov_b32 v2, v5 :: v_dual_mov_b32 v5, v6
.LBB0_25:                               ; %Flow135
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v0, v2
	v_mov_b32_e32 v2, v5
.LBB0_26:                               ; %_Z7HSV2RGBfffRfS_S_.exit
	s_load_b64 s[0:1], s[0:1], 0x38
	s_bfe_u32 s2, s2, 0x10008
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s2, 0
	s_mov_b32 s2, 0
	s_cbranch_scc0 .LBB0_28
; %bb.27:
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v6, vcc_lo, s0, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v5, vcc_lo
	v_add_co_u32 v4, vcc_lo, v6, 8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v7, vcc_lo
	global_store_b64 v[6:7], v[0:1], off
	s_branch .LBB0_29
.LBB0_28:
	s_mov_b32 s2, -1
                                        ; implicit-def: $vgpr4_vgpr5
.LBB0_29:                               ; %Flow
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_cbranch_vccnz .LBB0_31
; %bb.30:
	v_mul_lo_u32 v4, v3, 12
	v_dual_mov_b32 v3, v0 :: v_dual_mov_b32 v6, v1
	v_dual_mov_b32 v7, v2 :: v_dual_mov_b32 v8, v0
	v_dual_mov_b32 v9, v1 :: v_dual_mov_b32 v10, v2
	v_dual_mov_b32 v11, v0 :: v_dual_mov_b32 v12, v1
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[4:5], 2, v[4:5]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v13, vcc_lo, s0, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v14, vcc_lo, s1, v5, vcc_lo
	s_clause 0x2
	global_store_b128 v[13:14], v[0:3], off
	global_store_b128 v[13:14], v[6:9], off offset:16
	global_store_b96 v[13:14], v[10:12], off offset:32
	v_add_co_u32 v4, vcc_lo, v13, 44
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v14, vcc_lo
.LBB0_31:                               ; %.sink.split
	global_store_b32 v[4:5], v2, off
.LBB0_32:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z20gpu_calcColor_kerneliPfffffffffbbS_
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 15
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z20gpu_calcColor_kerneliPfffffffffbbS_, .Lfunc_end0-_Z20gpu_calcColor_kerneliPfffffffffbbS_
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 976
; NumSgprs: 18
; NumVgprs: 15
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 15
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .offset:         0
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         28
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           1
        .value_kind:     by_value
      - .offset:         49
        .size:           1
        .value_kind:     by_value
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         68
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         76
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         78
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         80
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         82
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         84
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         86
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         128
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 320
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z20gpu_calcColor_kerneliPfffffffffbbS_
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z20gpu_calcColor_kerneliPfffffffffbbS_.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     15
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
