#include <cuda_runtime.h>

#include "Floyd_blk.cuh"

void Floyd_Warshall(int *matrix, int size)
{
    int stages = size / TILE_WIDTH;

    // allocate memory
    int *matrixOnGPU;
    cudaMalloc(&matrixOnGPU, sizeof(int) * size * size);
    cudaMemcpy(matrixOnGPU, matrix, sizeof(int) * size * size, cudaMemcpyHostToDevice);

    // dimensions
    dim3 blockSize(TILE_WIDTH, TILE_WIDTH, 1);
    dim3 phase1Grid(1, 1, 1);
    dim3 phase2Grid(stages, 2, 1);
    dim3 phase3Grid(stages, stages, 1);

    // run kernel
    for(int k = 0; k < stages; ++k)
    {
		int base = TILE_WIDTH * k;
        phase1<<<phase1Grid, blockSize>>>(matrixOnGPU, size, base);
        phase2<<<phase2Grid, blockSize>>>(matrixOnGPU, size, k, base);
        phase3<<<phase3Grid, blockSize>>>(matrixOnGPU, size, k, base);
    }

    // get result back
    cudaMemcpy(matrix, matrixOnGPU, sizeof(int) * size * size, cudaMemcpyDeviceToHost);
    cudaFree(matrixOnGPU);
}

/*
 * This kernel computes the first phase (self-dependent block)
 *
 * @param matrix A pointer to the adjacency matrix
 * @param size   The width of the matrix
 * @param base   The base index for a block
 */
__global__ void phase1(int *matrix, int size, int base)
{
    // computes the index for a thread
    int index = (base + threadIdx.y) * size + (base + threadIdx.x);

    // loads data from global memory to shared memory
    __shared__ int subMatrix[TILE_WIDTH][TILE_WIDTH];
    subMatrix[threadIdx.y][threadIdx.x] = matrix[index];
    __syncthreads();

    // run Floyd-Warshall
    int sum;
    for (int k = 0; k < TILE_WIDTH; ++k)
    {
        sum = subMatrix[threadIdx.y][k] + subMatrix[k][threadIdx.x];
        if (sum < subMatrix[threadIdx.y][threadIdx.x])
            subMatrix[threadIdx.y][threadIdx.x] = sum;
    }

    // write back to global memory
    matrix[index] = subMatrix[threadIdx.y][threadIdx.x];
}

/*
 * This kernel computes the second phase (singly-dependent blocks)
 *
 * @param matrix A pointer to the adjacency matrix
 * @param size   The width of the matrix
 * @param stage  The current stage of the algorithm
 * @param base   The base index for a block
 */
__global__ void phase2(int *matrix, int size, int stage, int base)
{
    // computes the index for a thread
    if (blockIdx.x == stage) return;

    int i, j, i_prim, j_prim;
    i_prim = base + threadIdx.y;
    j_prim = base + threadIdx.x;
    if (blockIdx.y) // load for column
    {
        i = TILE_WIDTH * blockIdx.x + threadIdx.y;
        j = j_prim;
    } else { // load for row
        j = TILE_WIDTH * blockIdx.x + threadIdx.x;
        i = i_prim;
    }
    int index = i * size + j;
    int index_prim = i_prim * size + j_prim;

    // loads data from global memory to shared memory
    __shared__ int ownMatrix[TILE_WIDTH][TILE_WIDTH];
    __shared__ int primaryMatrix[TILE_WIDTH][TILE_WIDTH];
    ownMatrix[threadIdx.y][threadIdx.x] = matrix[index];
    primaryMatrix[threadIdx.y][threadIdx.x] = matrix[index_prim];
    __syncthreads();

    // run Floyd Warshall
    int sum;
    for (int k = 0; k < TILE_WIDTH; ++k)
    {
        sum = ownMatrix[threadIdx.y][k] + primaryMatrix[k][threadIdx.x];
        if (sum < ownMatrix[threadIdx.y][threadIdx.x])
            ownMatrix[threadIdx.y][threadIdx.x] = sum;
    }

    // write back to global memory
    matrix[index] = ownMatrix[threadIdx.y][threadIdx.x];
}


/*
 * This kernel computes the third phase (doubly-dependent blocks)
 *
 * @param matrix A pointer to the adjacency matrix
 * @param size   The width of the matrix
 * @param stage  The current stage of the algorithm
 * @param base   The base index for a block
 */
__global__ void phase3(int *matrix, int size, int stage, int base)
{
    // computes the index for a thread
    if (blockIdx.x == stage || blockIdx.y == stage) return;

    int i, j, j_col, i_row;
    i = TILE_WIDTH * blockIdx.y + threadIdx.y;
    j = TILE_WIDTH * blockIdx.x + threadIdx.x;
    i_row = base + threadIdx.y;
    j_col = base + threadIdx.x;
    int index, index_row, index_col;
    index = i * size + j;
    index_row = i_row * size + j;
    index_col = i * size + j_col;

    // loads data from global memory into shared memory
    __shared__ int rowMatrix[TILE_WIDTH][TILE_WIDTH];
    __shared__ int colMatrix[TILE_WIDTH][TILE_WIDTH];
    int i_j = matrix[index];
    rowMatrix[threadIdx.y][threadIdx.x] = matrix[index_row];
    colMatrix[threadIdx.y][threadIdx.x] = matrix[index_col];
    __syncthreads();

    // run Floyd Warshall
    int sum;
    for (int k = 0; k < TILE_WIDTH; ++k)
    {
        sum = colMatrix[threadIdx.y][k] + rowMatrix[k][threadIdx.x];
        if (sum < i_j)
		    i_j = sum;
    }

    // write back to global memory
    matrix[index] = i_j;
}

	.file	"tmpxft_003ac1f4_00000000-6_Floyd_blk.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2011:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2011:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z27__device_stub__Z6phase1PiiiPiii
	.type	_Z27__device_stub__Z6phase1PiiiPiii, @function
_Z27__device_stub__Z6phase1PiiiPiii:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	32(%rsp), %rdi
	movl	%esi, 4(%rsp)
	leaq	44(%rsp), %rsi
	movl	%edx, (%rsp)
	leaq	16(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	24(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z6phase1Piii(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 144
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L2:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z27__device_stub__Z6phase1PiiiPiii, .-_Z27__device_stub__Z6phase1PiiiPiii
	.globl	_Z6phase1Piii
	.type	_Z6phase1Piii, @function
_Z6phase1Piii:
.LFB2034:
	.cfi_startproc
	endbr64
	jmp	_Z27__device_stub__Z6phase1PiiiPiii
	.cfi_endproc
.LFE2034:
	.size	_Z6phase1Piii, .-_Z6phase1Piii
	.globl	_Z28__device_stub__Z6phase2PiiiiPiiii
	.type	_Z28__device_stub__Z6phase2PiiiiPiiii, @function
_Z28__device_stub__Z6phase2PiiiiPiiii:
.LFB2035:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z6phase2Piiii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L8:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2035:
	.size	_Z28__device_stub__Z6phase2PiiiiPiiii, .-_Z28__device_stub__Z6phase2PiiiiPiiii
	.globl	_Z6phase2Piiii
	.type	_Z6phase2Piiii, @function
_Z6phase2Piiii:
.LFB2036:
	.cfi_startproc
	endbr64
	jmp	_Z28__device_stub__Z6phase2PiiiiPiiii
	.cfi_endproc
.LFE2036:
	.size	_Z6phase2Piiii, .-_Z6phase2Piiii
	.globl	_Z28__device_stub__Z6phase3PiiiiPiiii
	.type	_Z28__device_stub__Z6phase3PiiiiPiiii, @function
_Z28__device_stub__Z6phase3PiiiiPiiii:
.LFB2037:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L13
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z6phase3Piiii(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L13:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2037:
	.size	_Z28__device_stub__Z6phase3PiiiiPiiii, .-_Z28__device_stub__Z6phase3PiiiiPiiii
	.globl	_Z6phase3Piiii
	.type	_Z6phase3Piiii, @function
_Z6phase3Piiii:
.LFB2038:
	.cfi_startproc
	endbr64
	jmp	_Z28__device_stub__Z6phase3PiiiiPiiii
	.cfi_endproc
.LFE2038:
	.size	_Z6phase3Piiii, .-_Z6phase3Piiii
	.globl	_Z14Floyd_WarshallPii
	.type	_Z14Floyd_WarshallPii, @function
_Z14Floyd_WarshallPii:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	movl	$32, %ecx
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	movq	%rdi, %r13
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	xorl	%ebp, %ebp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movslq	%esi, %rbx
	movq	%rbx, %r12
	subq	$72, %rsp
	.cfi_def_cfa_offset 128
	movq	%fs:40, %rax
	movq	%rax, 56(%rsp)
	xorl	%eax, %eax
	movl	%ebx, %eax
	imulq	%rbx, %rbx
	movq	%rsp, %rdi
	cltd
	idivl	%ecx
	salq	$2, %rbx
	movq	%rbx, %rsi
	movl	%eax, %r14d
	call	cudaMalloc@PLT
	movq	(%rsp), %rdi
	movq	%rbx, %rdx
	movq	%r13, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movl	$1, 16(%rsp)
	movabsq	$137438953504, %rax
	movq	%rax, 8(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 20(%rsp)
	incq	%rax
	movl	$1, 28(%rsp)
	movl	%r14d, 32(%rsp)
	movq	%rax, 36(%rsp)
	movl	%r14d, 44(%rsp)
	movl	%r14d, 48(%rsp)
	movl	$1, 52(%rsp)
.L19:
	cmpl	%r14d, %ebp
	jge	.L26
	movl	16(%rsp), %ecx
	movq	8(%rsp), %rdx
	movl	%ebp, %r15d
	xorl	%r9d, %r9d
	movq	20(%rsp), %rdi
	movl	28(%rsp), %esi
	xorl	%r8d, %r8d
	sall	$5, %r15d
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L20
	movq	(%rsp), %rdi
	movl	%r15d, %edx
	movl	%r12d, %esi
	call	_Z27__device_stub__Z6phase1PiiiPiii
.L20:
	movl	16(%rsp), %ecx
	movq	8(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	32(%rsp), %rdi
	movl	40(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L21
	movq	(%rsp), %rdi
	movl	%r15d, %ecx
	movl	%ebp, %edx
	movl	%r12d, %esi
	call	_Z28__device_stub__Z6phase2PiiiiPiiii
.L21:
	movl	16(%rsp), %ecx
	movq	8(%rsp), %rdx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	44(%rsp), %rdi
	movl	52(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L22
	movq	(%rsp), %rdi
	movl	%r15d, %ecx
	movl	%ebp, %edx
	movl	%r12d, %esi
	call	_Z28__device_stub__Z6phase3PiiiiPiiii
.L22:
	incl	%ebp
	jmp	.L19
.L26:
	movq	(%rsp), %rsi
	movq	%r13, %rdi
	movl	$2, %ecx
	movq	%rbx, %rdx
	call	cudaMemcpy@PLT
	movq	(%rsp), %rdi
	call	cudaFree@PLT
	movq	56(%rsp), %rax
	subq	%fs:40, %rax
	je	.L24
	call	__stack_chk_fail@PLT
.L24:
	addq	$72, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2008:
	.size	_Z14Floyd_WarshallPii, .-_Z14Floyd_WarshallPii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z6phase3Piiii"
.LC1:
	.string	"_Z6phase2Piiii"
.LC2:
	.string	"_Z6phase1Piii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2040:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z6phase3Piiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z6phase2Piiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC2(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z6phase1Piii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2040:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <hip/hip_runtime.h>

#include "Floyd_blk.cuh"

void Floyd_Warshall(int *matrix, int size)
{
    int stages = size / TILE_WIDTH;

    // allocate memory
    int *matrixOnGPU;
    hipMalloc(&matrixOnGPU, sizeof(int) * size * size);
    hipMemcpy(matrixOnGPU, matrix, sizeof(int) * size * size, hipMemcpyHostToDevice);

    // dimensions
    dim3 blockSize(TILE_WIDTH, TILE_WIDTH, 1);
    dim3 phase1Grid(1, 1, 1);
    dim3 phase2Grid(stages, 2, 1);
    dim3 phase3Grid(stages, stages, 1);

    // run kernel
    for(int k = 0; k < stages; ++k)
    {
		int base = TILE_WIDTH * k;
        phase1<<<phase1Grid, blockSize>>>(matrixOnGPU, size, base);
        phase2<<<phase2Grid, blockSize>>>(matrixOnGPU, size, k, base);
        phase3<<<phase3Grid, blockSize>>>(matrixOnGPU, size, k, base);
    }

    // get result back
    hipMemcpy(matrix, matrixOnGPU, sizeof(int) * size * size, hipMemcpyDeviceToHost);
    hipFree(matrixOnGPU);
}

/*
 * This kernel computes the first phase (self-dependent block)
 *
 * @param matrix A pointer to the adjacency matrix
 * @param size   The width of the matrix
 * @param base   The base index for a block
 */
__global__ void phase1(int *matrix, int size, int base)
{
    // computes the index for a thread
    int index = (base + threadIdx.y) * size + (base + threadIdx.x);

    // loads data from global memory to shared memory
    __shared__ int subMatrix[TILE_WIDTH][TILE_WIDTH];
    subMatrix[threadIdx.y][threadIdx.x] = matrix[index];
    __syncthreads();

    // run Floyd-Warshall
    int sum;
    for (int k = 0; k < TILE_WIDTH; ++k)
    {
        sum = subMatrix[threadIdx.y][k] + subMatrix[k][threadIdx.x];
        if (sum < subMatrix[threadIdx.y][threadIdx.x])
            subMatrix[threadIdx.y][threadIdx.x] = sum;
    }

    // write back to global memory
    matrix[index] = subMatrix[threadIdx.y][threadIdx.x];
}

/*
 * This kernel computes the second phase (singly-dependent blocks)
 *
 * @param matrix A pointer to the adjacency matrix
 * @param size   The width of the matrix
 * @param stage  The current stage of the algorithm
 * @param base   The base index for a block
 */
__global__ void phase2(int *matrix, int size, int stage, int base)
{
    // computes the index for a thread
    if (blockIdx.x == stage) return;

    int i, j, i_prim, j_prim;
    i_prim = base + threadIdx.y;
    j_prim = base + threadIdx.x;
    if (blockIdx.y) // load for column
    {
        i = TILE_WIDTH * blockIdx.x + threadIdx.y;
        j = j_prim;
    } else { // load for row
        j = TILE_WIDTH * blockIdx.x + threadIdx.x;
        i = i_prim;
    }
    int index = i * size + j;
    int index_prim = i_prim * size + j_prim;

    // loads data from global memory to shared memory
    __shared__ int ownMatrix[TILE_WIDTH][TILE_WIDTH];
    __shared__ int primaryMatrix[TILE_WIDTH][TILE_WIDTH];
    ownMatrix[threadIdx.y][threadIdx.x] = matrix[index];
    primaryMatrix[threadIdx.y][threadIdx.x] = matrix[index_prim];
    __syncthreads();

    // run Floyd Warshall
    int sum;
    for (int k = 0; k < TILE_WIDTH; ++k)
    {
        sum = ownMatrix[threadIdx.y][k] + primaryMatrix[k][threadIdx.x];
        if (sum < ownMatrix[threadIdx.y][threadIdx.x])
            ownMatrix[threadIdx.y][threadIdx.x] = sum;
    }

    // write back to global memory
    matrix[index] = ownMatrix[threadIdx.y][threadIdx.x];
}


/*
 * This kernel computes the third phase (doubly-dependent blocks)
 *
 * @param matrix A pointer to the adjacency matrix
 * @param size   The width of the matrix
 * @param stage  The current stage of the algorithm
 * @param base   The base index for a block
 */
__global__ void phase3(int *matrix, int size, int stage, int base)
{
    // computes the index for a thread
    if (blockIdx.x == stage || blockIdx.y == stage) return;

    int i, j, j_col, i_row;
    i = TILE_WIDTH * blockIdx.y + threadIdx.y;
    j = TILE_WIDTH * blockIdx.x + threadIdx.x;
    i_row = base + threadIdx.y;
    j_col = base + threadIdx.x;
    int index, index_row, index_col;
    index = i * size + j;
    index_row = i_row * size + j;
    index_col = i * size + j_col;

    // loads data from global memory into shared memory
    __shared__ int rowMatrix[TILE_WIDTH][TILE_WIDTH];
    __shared__ int colMatrix[TILE_WIDTH][TILE_WIDTH];
    int i_j = matrix[index];
    rowMatrix[threadIdx.y][threadIdx.x] = matrix[index_row];
    colMatrix[threadIdx.y][threadIdx.x] = matrix[index_col];
    __syncthreads();

    // run Floyd Warshall
    int sum;
    for (int k = 0; k < TILE_WIDTH; ++k)
    {
        sum = colMatrix[threadIdx.y][k] + rowMatrix[k][threadIdx.x];
        if (sum < i_j)
		    i_j = sum;
    }

    // write back to global memory
    matrix[index] = i_j;
}

	.text
	.file	"Floyd_blk.hip"
	.globl	_Z14Floyd_WarshallPii           # -- Begin function _Z14Floyd_WarshallPii
	.type	_Z14Floyd_WarshallPii,@function
_Z14Floyd_WarshallPii:                  # @_Z14Floyd_WarshallPii
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$40, %rsp
	.cfi_def_cfa_offset 96
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%esi, %r14d
	movq	%rdi, %r12
	leal	31(%r14), %ebp
	testl	%esi, %esi
	cmovnsl	%esi, %ebp
	movslq	%esi, %r15
	movq	%r15, %r13
	imulq	%r15, %r13
	shlq	$2, %r13
	leaq	8(%rsp), %rbx
	movq	%rbx, %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	movq	(%rbx), %rdi
	movq	%r12, 24(%rsp)                  # 8-byte Spill
	movq	%r12, %rsi
	movq	%r13, 16(%rsp)                  # 8-byte Spill
	movq	%r13, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	cmpl	$32, %r15d
	jl	.LBB0_9
# %bb.1:                                # %.lr.ph.preheader
	movq	%rbp, %rax
	sarl	$5, %eax
	movq	%rax, %r13
	btsq	$33, %r13
	movq	%rax, %rbp
	shlq	$32, %rbp
	movq	%rax, 32(%rsp)                  # 8-byte Spill
	orq	%rax, %rbp
	xorl	%ebx, %ebx
	movabsq	$137438953504, %r15             # imm = 0x2000000020
	xorl	%r12d, %r12d
.LBB0_2:                                # %.lr.ph
                                        # =>This Inner Loop Header: Depth=1
	movabsq	$4294967297, %rdi               # imm = 0x100000001
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_4
# %bb.3:                                #   in Loop: Header=BB0_2 Depth=1
	movq	8(%rsp), %rdi
	movl	%r14d, %esi
	movl	%ebx, %edx
	callq	_Z21__device_stub__phase1Piii
.LBB0_4:                                #   in Loop: Header=BB0_2 Depth=1
	movq	%r13, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_6
# %bb.5:                                #   in Loop: Header=BB0_2 Depth=1
	movq	8(%rsp), %rdi
	movl	%r14d, %esi
	movl	%r12d, %edx
	movl	%ebx, %ecx
	callq	_Z21__device_stub__phase2Piiii
.LBB0_6:                                #   in Loop: Header=BB0_2 Depth=1
	movq	%rbp, %rdi
	movl	$1, %esi
	movq	%r15, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB0_8
# %bb.7:                                #   in Loop: Header=BB0_2 Depth=1
	movq	8(%rsp), %rdi
	movl	%r14d, %esi
	movl	%r12d, %edx
	movl	%ebx, %ecx
	callq	_Z21__device_stub__phase3Piiii
.LBB0_8:                                #   in Loop: Header=BB0_2 Depth=1
	incl	%r12d
	addl	$32, %ebx
	cmpl	%r12d, 32(%rsp)                 # 4-byte Folded Reload
	jne	.LBB0_2
.LBB0_9:                                # %._crit_edge
	movq	8(%rsp), %rsi
	movq	24(%rsp), %rdi                  # 8-byte Reload
	movq	16(%rsp), %rdx                  # 8-byte Reload
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rdi
	callq	hipFree
	addq	$40, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z14Floyd_WarshallPii, .Lfunc_end0-_Z14Floyd_WarshallPii
	.cfi_endproc
                                        # -- End function
	.globl	_Z21__device_stub__phase1Piii   # -- Begin function _Z21__device_stub__phase1Piii
	.type	_Z21__device_stub__phase1Piii,@function
_Z21__device_stub__phase1Piii:          # @_Z21__device_stub__phase1Piii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$96, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	movq	%rsp, %rsi
	movl	%edx, (%rsi)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6phase1Piii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$112, %rsp
	.cfi_adjust_cfa_offset -112
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z21__device_stub__phase1Piii, .Lfunc_end1-_Z21__device_stub__phase1Piii
	.cfi_endproc
                                        # -- End function
	.globl	_Z21__device_stub__phase2Piiii  # -- Begin function _Z21__device_stub__phase2Piiii
	.type	_Z21__device_stub__phase2Piiii,@function
_Z21__device_stub__phase2Piiii:         # @_Z21__device_stub__phase2Piiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6phase2Piiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end2:
	.size	_Z21__device_stub__phase2Piiii, .Lfunc_end2-_Z21__device_stub__phase2Piiii
	.cfi_endproc
                                        # -- End function
	.globl	_Z21__device_stub__phase3Piiii  # -- Begin function _Z21__device_stub__phase3Piiii
	.type	_Z21__device_stub__phase3Piiii,@function
_Z21__device_stub__phase3Piiii:         # @_Z21__device_stub__phase3Piiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z6phase3Piiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end3:
	.size	_Z21__device_stub__phase3Piiii, .Lfunc_end3-_Z21__device_stub__phase3Piiii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB4_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB4_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6phase1Piii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6phase2Piiii, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z6phase3Piiii, %esi
	movl	$.L__unnamed_3, %edx
	movl	$.L__unnamed_3, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end4:
	.size	__hip_module_ctor, .Lfunc_end4-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB5_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB5_2:
	retq
.Lfunc_end5:
	.size	__hip_module_dtor, .Lfunc_end5-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z6phase1Piii,@object           # @_Z6phase1Piii
	.section	.rodata,"a",@progbits
	.globl	_Z6phase1Piii
	.p2align	3, 0x0
_Z6phase1Piii:
	.quad	_Z21__device_stub__phase1Piii
	.size	_Z6phase1Piii, 8

	.type	_Z6phase2Piiii,@object          # @_Z6phase2Piiii
	.globl	_Z6phase2Piiii
	.p2align	3, 0x0
_Z6phase2Piiii:
	.quad	_Z21__device_stub__phase2Piiii
	.size	_Z6phase2Piiii, 8

	.type	_Z6phase3Piiii,@object          # @_Z6phase3Piiii
	.globl	_Z6phase3Piiii
	.p2align	3, 0x0
_Z6phase3Piiii:
	.quad	_Z21__device_stub__phase3Piiii
	.size	_Z6phase3Piiii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z6phase1Piii"
	.size	.L__unnamed_1, 14

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z6phase2Piiii"
	.size	.L__unnamed_2, 15

	.type	.L__unnamed_3,@object           # @2
.L__unnamed_3:
	.asciz	"_Z6phase3Piiii"
	.size	.L__unnamed_3, 15

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z21__device_stub__phase1Piii
	.addrsig_sym _Z21__device_stub__phase2Piiii
	.addrsig_sym _Z21__device_stub__phase3Piiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z6phase1Piii
	.addrsig_sym _Z6phase2Piiii
	.addrsig_sym _Z6phase3Piiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z6phase1Piii           ; -- Begin function _Z6phase1Piii
	.globl	_Z6phase1Piii
	.p2align	8
	.type	_Z6phase1Piii,@function
_Z6phase1Piii:                          ; @_Z6phase1Piii
; %bb.0:
	s_load_b128 s[0:3], s[0:1], 0x0
	v_bfe_u32 v3, v0, 10, 10
	v_and_b32_e32 v2, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v1, s3, v3
	v_lshlrev_b32_e32 v3, 7, v3
	v_mul_lo_u32 v1, v1, s2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add3_u32 v0, v2, s3, v1
	v_lshlrev_b32_e32 v2, 2, v2
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v4, v3, v2
	v_lshlrev_b64 v[0:1], 2, v[0:1]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	s_mov_b32 s0, 0
	global_load_b32 v5, v[0:1], off
	s_waitcnt vmcnt(0)
	ds_store_b32 v4, v5
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v5, v4
.LBB0_1:                                ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v6, s0, v3
	s_mov_b32 s1, exec_lo
	ds_load_b32 v6, v6
	ds_load_b32 v7, v2
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v6, v7, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v6, v5
	s_cbranch_execz .LBB0_3
; %bb.2:                                ;   in Loop: Header=BB0_1 Depth=1
	v_mov_b32_e32 v5, v6
	ds_store_b32 v4, v6
.LBB0_3:                                ;   in Loop: Header=BB0_1 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_add_nc_u32_e32 v2, 0x80, v2
	s_add_i32 s0, s0, 4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmpk_eq_i32 s0, 0x80
	s_cbranch_scc0 .LBB0_1
; %bb.4:
	global_store_b32 v[0:1], v5, off
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6phase1Piii
		.amdhsa_group_segment_fixed_size 4096
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 16
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 4
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z6phase1Piii, .Lfunc_end0-_Z6phase1Piii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 256
; NumSgprs: 6
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4096 bytes/workgroup (compile time only)
; SGPRBlocks: 0
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 6
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z6phase2Piiii          ; -- Begin function _Z6phase2Piiii
	.globl	_Z6phase2Piiii
	.p2align	8
	.type	_Z6phase2Piiii,@function
_Z6phase2Piiii:                         ; @_Z6phase2Piiii
; %bb.0:
	s_load_b128 s[4:7], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_cmp_eq_u32 s14, s5
	s_cbranch_scc1 .LBB1_6
; %bb.1:
	s_cmp_eq_u32 s15, 0
	v_bfe_u32 v7, v0, 10, 10
	s_cselect_b32 vcc_lo, -1, 0
	v_and_b32_e32 v6, 0x3ff, v0
	s_lshl_b32 s2, s14, 5
	s_load_b64 s[0:1], s[0:1], 0x0
	v_add_nc_u32_e32 v8, s6, v7
	v_add_nc_u32_e32 v2, s2, v7
	v_add_nc_u32_e32 v0, s6, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v4, v2, v8 :: v_dual_add_nc_u32 v1, s2, v6
	v_cndmask_b32_e32 v1, v0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[2:3], null, v4, s4, v[1:2]
	v_mad_u64_u32 v[4:5], null, v8, s4, v[0:1]
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[0:1], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[2:3], 2, v[4:5]
	v_lshlrev_b32_e32 v5, 7, v7
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v0, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	s_clause 0x1
	global_load_b32 v4, v[0:1], off
	global_load_b32 v3, v[2:3], off
	v_lshlrev_b32_e32 v2, 2, v6
	s_mov_b32 s0, 0
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v6, v5, v2
	v_add_nc_u32_e32 v5, 0x1000, v5
	s_waitcnt vmcnt(0)
	ds_store_2addr_stride64_b32 v6, v3, v4 offset1:16
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_b32 v4, v6 offset:4096
	v_add_nc_u32_e32 v3, 0x1000, v6
.LBB1_2:                                ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v6, s0, v5
	s_mov_b32 s1, exec_lo
	ds_load_b32 v6, v6
	ds_load_b32 v7, v2
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v6, v7, v6
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_lt_i32_e64 v6, v4
	s_cbranch_execz .LBB1_4
; %bb.3:                                ;   in Loop: Header=BB1_2 Depth=1
	v_mov_b32_e32 v4, v6
	ds_store_b32 v3, v6
.LBB1_4:                                ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s1
	v_add_nc_u32_e32 v2, 0x80, v2
	s_add_i32 s0, s0, 4
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmpk_eq_i32 s0, 0x80
	s_cbranch_scc0 .LBB1_2
; %bb.5:
	global_store_b32 v[0:1], v4, off
.LBB1_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6phase2Piiii
		.amdhsa_group_segment_fixed_size 8192
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 20
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 9
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z6phase2Piiii, .Lfunc_end1-_Z6phase2Piiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 368
; NumSgprs: 18
; NumVgprs: 9
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8192 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 9
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z6phase3Piiii          ; -- Begin function _Z6phase3Piiii
	.globl	_Z6phase3Piiii
	.p2align	8
	.type	_Z6phase3Piiii,@function
_Z6phase3Piiii:                         ; @_Z6phase3Piiii
; %bb.0:
	s_load_b128 s[4:7], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_cmp_eq_u32 s14, s5
	s_cbranch_scc1 .LBB2_5
; %bb.1:
	s_cmp_eq_u32 s15, s5
	s_cbranch_scc1 .LBB2_5
; %bb.2:
	v_bfe_u32 v8, v0, 10, 10
	v_and_b32_e32 v9, 0x3ff, v0
	s_load_b64 s[0:1], s[0:1], 0x0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshl_add_u32 v1, s15, 5, v8
	v_lshl_add_u32 v0, s14, 5, v9
	v_add_nc_u32_e32 v3, s6, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v4, v1, s4
	v_mad_u64_u32 v[1:2], null, v3, s4, v[0:1]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v3, v4, v0
	v_add3_u32 v5, v4, v9, s6
	v_ashrrev_i32_e32 v2, 31, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_ashrrev_i32_e32 v4, 31, v3
	v_ashrrev_i32_e32 v6, 31, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[0:1], 2, v[1:2]
	v_lshlrev_b64 v[2:3], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[4:5], 2, v[5:6]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v6, vcc_lo, s0, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v7, vcc_lo, s1, v1, vcc_lo
	v_add_co_u32 v4, vcc_lo, s0, v4
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v5, vcc_lo, s1, v5, vcc_lo
	v_add_co_u32 v0, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v3, vcc_lo
	s_clause 0x2
	global_load_b32 v6, v[6:7], off
	global_load_b32 v5, v[4:5], off
	global_load_b32 v2, v[0:1], off
	v_lshlrev_b32_e32 v7, 2, v9
	v_lshlrev_b32_e32 v3, 7, v8
	s_mov_b32 s0, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v4, 0x1000, v7
	v_add_nc_u32_e32 v7, v3, v7
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v8, v4, v3
	s_waitcnt vmcnt(2)
	ds_store_b32 v8, v6
	s_waitcnt vmcnt(1)
	ds_store_b32 v7, v5
	s_waitcnt vmcnt(0) lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
.LBB2_3:                                ; =>This Inner Loop Header: Depth=1
	v_add_nc_u32_e32 v5, s0, v3
	s_add_i32 s0, s0, 4
	ds_load_b32 v6, v4
	ds_load_b32 v5, v5
	v_add_nc_u32_e32 v4, 0x80, v4
	s_cmpk_eq_i32 s0, 0x80
	s_waitcnt lgkmcnt(0)
	v_add_nc_u32_e32 v5, v6, v5
	s_delay_alu instid0(VALU_DEP_1)
	v_min_i32_e32 v2, v5, v2
	s_cbranch_scc0 .LBB2_3
; %bb.4:
	global_store_b32 v[0:1], v2, off
.LBB2_5:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z6phase3Piiii
		.amdhsa_group_segment_fixed_size 8192
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 20
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 10
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end2:
	.size	_Z6phase3Piiii, .Lfunc_end2-_Z6phase3Piiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 388
; NumSgprs: 18
; NumVgprs: 10
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 8192 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 10
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 4096
    .kernarg_segment_align: 8
    .kernarg_segment_size: 16
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6phase1Piii
    .private_segment_fixed_size: 0
    .sgpr_count:     6
    .sgpr_spill_count: 0
    .symbol:         _Z6phase1Piii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 8192
    .kernarg_segment_align: 8
    .kernarg_segment_size: 20
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6phase2Piiii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z6phase2Piiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     9
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 8192
    .kernarg_segment_align: 8
    .kernarg_segment_size: 20
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z6phase3Piiii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z6phase3Piiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     10
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
