#include "includes.h"
__global__ void THCudaTensor_kernel_indexAdd( float *res, float *src, long* res_stride, float *index, long res_nDim, int dim, long idx_size, long src_size, long size_dim )
{
int thread_idx = blockIdx.x * blockDim.x * blockDim.y + threadIdx.y * blockDim.x + threadIdx.x;

long flat_size = src_size / idx_size;

if (thread_idx < flat_size)
{
long coeff = 0;
for (int i=0; i<idx_size; i++)
{
int leftover = thread_idx;
int targetIdx = 0;
int resIdx = 0;
for (int d=0; d<res_nDim; d++)
{
if (d < dim)
{
long stride_d = res_stride[d] / size_dim;
coeff = leftover / stride_d;
leftover -= coeff * stride_d;
targetIdx += coeff * stride_d * idx_size;
resIdx += coeff * res_stride[d];
}
else if (d > dim)
{
coeff = leftover / res_stride[d];
leftover -= coeff * res_stride[d];
targetIdx += coeff * res_stride[d];
resIdx += coeff * res_stride[d];
}
}
atomicAdd(&res[resIdx + ((long)(index[i])-1)*res_stride[dim]], src[targetIdx + i*res_stride[dim]]);
}
}
}
	.file	"tmpxft_0025eae4_00000000-6_THCudaTensor_kernel_indexAdd.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z59__device_stub__Z28THCudaTensor_kernel_indexAddPfS_PlS_lilllPfS_PlS_lilll
	.type	_Z59__device_stub__Z28THCudaTensor_kernel_indexAddPfS_PlS_lilllPfS_PlS_lilll, @function
_Z59__device_stub__Z28THCudaTensor_kernel_indexAddPfS_PlS_lilllPfS_PlS_lilll:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$200, %rsp
	.cfi_def_cfa_offset 208
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movq	%r8, 8(%rsp)
	movl	%r9d, 4(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 184(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	208(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	216(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 176(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	56(%rsp)
	.cfi_def_cfa_offset 216
	leaq	_Z28THCudaTensor_kernel_indexAddPfS_PlS_lilll(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 224
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 216
	popq	%rdx
	.cfi_def_cfa_offset 208
.L2:
	movq	184(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$200, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z59__device_stub__Z28THCudaTensor_kernel_indexAddPfS_PlS_lilllPfS_PlS_lilll, .-_Z59__device_stub__Z28THCudaTensor_kernel_indexAddPfS_PlS_lilllPfS_PlS_lilll
	.globl	_Z28THCudaTensor_kernel_indexAddPfS_PlS_lilll
	.type	_Z28THCudaTensor_kernel_indexAddPfS_PlS_lilll, @function
_Z28THCudaTensor_kernel_indexAddPfS_PlS_lilll:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z59__device_stub__Z28THCudaTensor_kernel_indexAddPfS_PlS_lilllPfS_PlS_lilll
	.cfi_endproc
.LFE2033:
	.size	_Z28THCudaTensor_kernel_indexAddPfS_PlS_lilll, .-_Z28THCudaTensor_kernel_indexAddPfS_PlS_lilll
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z28THCudaTensor_kernel_indexAddPfS_PlS_lilll"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2035:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z28THCudaTensor_kernel_indexAddPfS_PlS_lilll(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2035:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__global__ void THCudaTensor_kernel_indexAdd( float *res, float *src, long* res_stride, float *index, long res_nDim, int dim, long idx_size, long src_size, long size_dim )
{
int thread_idx = blockIdx.x * blockDim.x * blockDim.y + threadIdx.y * blockDim.x + threadIdx.x;

long flat_size = src_size / idx_size;

if (thread_idx < flat_size)
{
long coeff = 0;
for (int i=0; i<idx_size; i++)
{
int leftover = thread_idx;
int targetIdx = 0;
int resIdx = 0;
for (int d=0; d<res_nDim; d++)
{
if (d < dim)
{
long stride_d = res_stride[d] / size_dim;
coeff = leftover / stride_d;
leftover -= coeff * stride_d;
targetIdx += coeff * stride_d * idx_size;
resIdx += coeff * res_stride[d];
}
else if (d > dim)
{
coeff = leftover / res_stride[d];
leftover -= coeff * res_stride[d];
targetIdx += coeff * res_stride[d];
resIdx += coeff * res_stride[d];
}
}
atomicAdd(&res[resIdx + ((long)(index[i])-1)*res_stride[dim]], src[targetIdx + i*res_stride[dim]]);
}
}
}
	.text
	.file	"THCudaTensor_kernel_indexAdd.hip"
	.globl	_Z43__device_stub__THCudaTensor_kernel_indexAddPfS_PlS_lilll # -- Begin function _Z43__device_stub__THCudaTensor_kernel_indexAddPfS_PlS_lilll
	.type	_Z43__device_stub__THCudaTensor_kernel_indexAddPfS_PlS_lilll,@function
_Z43__device_stub__THCudaTensor_kernel_indexAddPfS_PlS_lilll: # @_Z43__device_stub__THCudaTensor_kernel_indexAddPfS_PlS_lilll
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	24(%rsp), %rcx
	movq	%r8, (%rcx)
	leaq	4(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z28THCudaTensor_kernel_indexAddPfS_PlS_lilll, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z43__device_stub__THCudaTensor_kernel_indexAddPfS_PlS_lilll, .Lfunc_end0-_Z43__device_stub__THCudaTensor_kernel_indexAddPfS_PlS_lilll
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z28THCudaTensor_kernel_indexAddPfS_PlS_lilll, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z28THCudaTensor_kernel_indexAddPfS_PlS_lilll,@object # @_Z28THCudaTensor_kernel_indexAddPfS_PlS_lilll
	.section	.rodata,"a",@progbits
	.globl	_Z28THCudaTensor_kernel_indexAddPfS_PlS_lilll
	.p2align	3, 0x0
_Z28THCudaTensor_kernel_indexAddPfS_PlS_lilll:
	.quad	_Z43__device_stub__THCudaTensor_kernel_indexAddPfS_PlS_lilll
	.size	_Z28THCudaTensor_kernel_indexAddPfS_PlS_lilll, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z28THCudaTensor_kernel_indexAddPfS_PlS_lilll"
	.size	.L__unnamed_1, 46

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z43__device_stub__THCudaTensor_kernel_indexAddPfS_PlS_lilll
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z28THCudaTensor_kernel_indexAddPfS_PlS_lilll
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z28THCudaTensor_kernel_indexAddPfS_PlS_lilll ; -- Begin function _Z28THCudaTensor_kernel_indexAddPfS_PlS_lilll
	.globl	_Z28THCudaTensor_kernel_indexAddPfS_PlS_lilll
	.p2align	8
	.type	_Z28THCudaTensor_kernel_indexAddPfS_PlS_lilll,@function
_Z28THCudaTensor_kernel_indexAddPfS_PlS_lilll: ; @_Z28THCudaTensor_kernel_indexAddPfS_PlS_lilll
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x54
	s_load_b128 s[16:19], s[0:1], 0x30
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s10, s2, 16
	s_ashr_i32 s4, s17, 31
	s_and_b32 s11, s2, 0xffff
	s_add_u32 s2, s16, s4
	s_mov_b32 s5, s4
	s_addc_u32 s3, s17, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b64 s[2:3], s[2:3], s[4:5]
	v_cvt_f32_u32_e32 v1, s2
	v_cvt_f32_u32_e32 v2, s3
	s_sub_u32 s8, 0, s2
	s_subb_u32 s9, 0, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v1, 0x4f800000, v2
	v_rcp_f32_e32 v1, v1
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x5f7ffffc, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, 0x2f800000, v1
	v_trunc_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v1, 0xcf800000, v2
	v_cvt_u32_f32_e32 v2, v2
	v_cvt_u32_f32_e32 v1, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s6, v2
	v_readfirstlane_b32 s7, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_mul_i32 s12, s8, s6
	s_mul_hi_u32 s14, s8, s7
	s_mul_i32 s13, s9, s7
	s_add_i32 s12, s14, s12
	s_mul_i32 s20, s8, s7
	s_add_i32 s12, s12, s13
	s_mul_hi_u32 s14, s7, s20
	s_mul_hi_u32 s21, s6, s20
	s_mul_i32 s13, s6, s20
	s_mul_hi_u32 s20, s7, s12
	s_mul_i32 s7, s7, s12
	s_mul_hi_u32 s22, s6, s12
	s_add_u32 s7, s14, s7
	s_addc_u32 s14, 0, s20
	s_add_u32 s7, s7, s13
	s_mul_i32 s12, s6, s12
	s_addc_u32 s7, s14, s21
	s_addc_u32 s13, s22, 0
	s_add_u32 s7, s7, s12
	s_addc_u32 s12, 0, s13
	v_add_co_u32 v1, s7, v1, s7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s7, 0
	s_addc_u32 s6, s6, s12
	v_readfirstlane_b32 s7, v1
	s_mul_i32 s12, s8, s6
	s_delay_alu instid0(VALU_DEP_1)
	s_mul_hi_u32 s13, s8, s7
	s_mul_i32 s9, s9, s7
	s_add_i32 s12, s13, s12
	s_mul_i32 s8, s8, s7
	s_add_i32 s12, s12, s9
	s_mul_hi_u32 s13, s6, s8
	s_mul_i32 s14, s6, s8
	s_mul_hi_u32 s8, s7, s8
	s_mul_hi_u32 s20, s7, s12
	s_mul_i32 s7, s7, s12
	s_mul_hi_u32 s9, s6, s12
	s_add_u32 s7, s8, s7
	s_addc_u32 s8, 0, s20
	s_add_u32 s7, s7, s14
	s_mul_i32 s12, s6, s12
	s_addc_u32 s7, s8, s13
	s_addc_u32 s8, s9, 0
	s_add_u32 s7, s7, s12
	s_addc_u32 s8, 0, s8
	v_add_co_u32 v1, s7, v1, s7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s7, 0
	s_addc_u32 s12, s6, s8
	s_ashr_i32 s6, s19, 31
	v_readfirstlane_b32 s13, v1
	s_add_u32 s8, s18, s6
	s_mov_b32 s7, s6
	s_addc_u32 s9, s19, s6
	v_bfe_u32 v1, v0, 10, 10
	s_xor_b64 s[8:9], s[8:9], s[6:7]
	v_and_b32_e32 v0, 0x3ff, v0
	s_mul_i32 s18, s8, s12
	s_mul_hi_u32 s19, s8, s13
	s_mul_hi_u32 s14, s8, s12
	s_mul_hi_u32 s21, s9, s13
	s_mul_i32 s13, s9, s13
	s_add_u32 s18, s19, s18
	s_addc_u32 s14, 0, s14
	s_mul_hi_u32 s20, s9, s12
	s_add_u32 s13, s18, s13
	s_mul_i32 s12, s9, s12
	s_addc_u32 s13, s14, s21
	s_addc_u32 s14, s20, 0
	s_add_u32 s12, s13, s12
	s_addc_u32 s13, 0, s14
	s_mul_i32 s20, s2, s12
	s_mul_hi_u32 s14, s2, s12
	s_mul_i32 s19, s2, s13
	v_sub_co_u32 v4, s8, s8, s20
	s_mul_i32 s18, s3, s12
	s_add_i32 s14, s14, s19
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s14, s14, s18
	v_sub_co_u32 v2, s19, v4, s2
	s_sub_i32 s18, s9, s14
	s_cmp_lg_u32 s8, 0
	s_subb_u32 s18, s18, s3
	s_cmp_lg_u32 s19, 0
	v_cmp_le_u32_e32 vcc_lo, s2, v2
	s_subb_u32 s18, s18, 0
	v_mad_u64_u32 v[2:3], null, s15, s10, v[1:2]
	s_cmp_ge_u32 s18, s3
	v_cndmask_b32_e64 v5, 0, -1, vcc_lo
	s_cselect_b32 s19, -1, 0
	s_cmp_eq_u32 s18, s3
	s_cselect_b32 vcc_lo, -1, 0
	s_add_u32 s10, s12, 1
	s_addc_u32 s15, s13, 0
	s_add_u32 s18, s12, 2
	v_cndmask_b32_e32 v1, s19, v5, vcc_lo
	s_addc_u32 s19, s13, 0
	s_cmp_lg_u32 s8, 0
	v_cmp_le_u32_e32 vcc_lo, s2, v4
	s_subb_u32 s2, s9, s14
	v_mov_b32_e32 v4, s18
	s_cmp_ge_u32 s2, s3
	v_mul_lo_u32 v2, v2, s11
	v_cndmask_b32_e64 v3, 0, -1, vcc_lo
	s_cselect_b32 s8, -1, 0
	s_cmp_eq_u32 s2, s3
	v_cmp_ne_u32_e32 vcc_lo, 0, v1
	v_mov_b32_e32 v1, s19
	s_cselect_b32 s2, -1, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v3, s8, v3, s2
	v_cndmask_b32_e32 v4, s10, v4, vcc_lo
	v_cndmask_b32_e32 v1, s15, v1, vcc_lo
	s_xor_b64 s[2:3], s[6:7], s[4:5]
	v_add_nc_u32_e32 v0, v2, v0
	v_cmp_ne_u32_e32 vcc_lo, 0, v3
	v_cmp_gt_i64_e64 s4, s[16:17], 0
	v_cndmask_b32_e32 v3, s12, v4, vcc_lo
	v_cndmask_b32_e32 v1, s13, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v2, s2, v3
	v_xor_b32_e32 v3, s3, v1
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_co_u32 v2, vcc_lo, v2, s2
	v_subrev_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
	s_mov_b64 s[2:3], 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i64_e32 vcc_lo, v[2:3], v[0:1]
	s_and_b32 s4, vcc_lo, s4
	s_and_saveexec_b32 s5, s4
	s_cbranch_execz .LBB0_16
; %bb.1:                                ; %.preheader.lr.ph
	s_clause 0x3
	s_load_b32 s12, s[0:1], 0x28
	s_load_b64 s[14:15], s[0:1], 0x20
	s_load_b256 s[4:11], s[0:1], 0x0
	s_load_b64 s[18:19], s[0:1], 0x40
	v_mov_b32_e32 v7, 0
	s_waitcnt lgkmcnt(0)
	s_ashr_i32 s13, s12, 31
	v_cmp_gt_i64_e64 s30, s[14:15], 0
	s_lshl_b64 s[0:1], s[12:13], 3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s20, s8, s0
	s_addc_u32 s21, s9, s1
.LBB0_2:                                ; %.preheader
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
                                        ;     Child Loop BB0_14 Depth 2
	v_mov_b32_e32 v3, 0
	v_mov_b32_e32 v5, 0
	s_and_not1_b32 vcc_lo, exec_lo, s30
	s_cbranch_vccnz .LBB0_13
; %bb.3:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB0_2 Depth=1
	v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v8, v0
	v_mov_b32_e32 v2, 0
	s_mov_b64 s[22:23], 0
	s_mov_b64 s[24:25], s[8:9]
.LBB0_4:                                ; %.lr.ph
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_cmp_ge_i32 s22, s12
	s_cbranch_scc0 .LBB0_8
; %bb.5:                                ;   in Loop: Header=BB0_4 Depth=2
	v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v4, v8
	v_mov_b32_e32 v5, v2
	s_cmp_le_i32 s22, s12
	s_cbranch_scc1 .LBB0_7
; %bb.6:                                ;   in Loop: Header=BB0_4 Depth=2
	global_load_b64 v[3:4], v7, s[24:25]
	s_waitcnt vmcnt(0)
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, v5
	v_add_co_ci_u32_e32 v4, vcc_lo, v4, v5, vcc_lo
	v_xor_b32_e32 v11, v3, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_xor_b32_e32 v12, v4, v5
	v_cvt_f32_u32_e32 v3, v11
	v_sub_co_u32 v5, vcc_lo, 0, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cvt_f32_u32_e32 v4, v12
	v_sub_co_ci_u32_e32 v6, vcc_lo, 0, v12, vcc_lo
	v_fmac_f32_e32 v3, 0x4f800000, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, 0x5f7ffffc, v3
	v_mul_f32_e32 v4, 0x2f800000, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_trunc_f32_e32 v4, v4
	v_fmac_f32_e32 v3, 0xcf800000, v4
	v_cvt_u32_f32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v3, v3
	v_mul_lo_u32 v9, v5, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v10, v5, v3
	v_mul_lo_u32 v13, v6, v3
	v_add_nc_u32_e32 v9, v10, v9
	v_mul_lo_u32 v10, v5, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v9, v9, v13
	v_mul_hi_u32 v13, v3, v10
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_lo_u32 v14, v3, v9
	v_mul_hi_u32 v15, v3, v9
	v_mul_hi_u32 v16, v4, v10
	v_mul_lo_u32 v10, v4, v10
	v_mul_hi_u32 v17, v4, v9
	v_mul_lo_u32 v9, v4, v9
	v_add_co_u32 v13, vcc_lo, v13, v14
	v_add_co_ci_u32_e32 v14, vcc_lo, 0, v15, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v13, v10
	v_add_co_ci_u32_e32 v10, vcc_lo, v14, v16, vcc_lo
	v_add_co_ci_u32_e32 v13, vcc_lo, 0, v17, vcc_lo
	v_ashrrev_i32_e32 v14, 31, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v9, vcc_lo, v10, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, v9
	v_add_co_ci_u32_e32 v4, vcc_lo, v4, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v9, v5, v3
	v_mul_lo_u32 v6, v6, v3
	v_mul_lo_u32 v10, v5, v4
	v_mul_lo_u32 v5, v5, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v9, v9, v10
	v_mul_hi_u32 v15, v4, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v6, v9, v6
	v_mul_hi_u32 v9, v3, v5
	v_mul_lo_u32 v5, v4, v5
	v_mul_lo_u32 v10, v3, v6
	v_mul_hi_u32 v13, v3, v6
	v_mul_hi_u32 v16, v4, v6
	v_mul_lo_u32 v6, v4, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v9, vcc_lo, v9, v10
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, v9, v5
	v_add_co_ci_u32_e32 v5, vcc_lo, v10, v15, vcc_lo
	v_add_co_ci_u32_e32 v9, vcc_lo, 0, v16, vcc_lo
	v_add_co_u32 v10, vcc_lo, v8, v14
	v_add_co_ci_u32_e32 v13, vcc_lo, v14, v14, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, v5, v6
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v15, v10, v14
	v_add_co_u32 v9, vcc_lo, v3, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v16, vcc_lo, v4, v6, vcc_lo
	v_xor_b32_e32 v13, v13, v14
	v_mul_hi_u32 v17, v15, v9
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[3:4], null, v15, v16, 0
	v_mad_u64_u32 v[5:6], null, v13, v9, 0
	v_mad_u64_u32 v[9:10], null, v13, v16, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, v17, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, v5
	v_add_co_ci_u32_e32 v3, vcc_lo, v4, v6, vcc_lo
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, v3, v9
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v9, v12, v5
	v_mad_u64_u32 v[3:4], null, v11, v5, 0
	v_mul_lo_u32 v5, v11, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_co_u32 v3, vcc_lo, v15, v3
	v_add3_u32 v4, v4, v5, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v5, v13, v4
	v_sub_co_ci_u32_e64 v5, s0, v5, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_sub_co_u32 v6, s0, v3, v11
	v_sub_co_ci_u32_e32 v4, vcc_lo, v13, v4, vcc_lo
	v_subrev_co_ci_u32_e64 v5, s0, 0, v5, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cmp_ge_u32_e32 vcc_lo, v6, v11
	v_cndmask_b32_e64 v9, 0, -1, vcc_lo
	v_cmp_ge_u32_e32 vcc_lo, v5, v12
	v_cndmask_b32_e64 v10, 0, -1, vcc_lo
	v_cmp_ge_u32_e32 vcc_lo, v3, v11
	v_cndmask_b32_e64 v13, 0, -1, vcc_lo
	v_cmp_ge_u32_e32 vcc_lo, v4, v12
	v_cndmask_b32_e64 v15, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, v5, v12
	v_cndmask_b32_e32 v5, v10, v9, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, v4, v12
	v_sub_nc_u32_e32 v9, v6, v11
	v_cndmask_b32_e32 v4, v15, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_ne_u32_e32 vcc_lo, 0, v5
	v_cndmask_b32_e32 v5, v6, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ne_u32_e32 vcc_lo, 0, v4
	v_cndmask_b32_e32 v3, v3, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v3, v3, v14
	v_sub_nc_u32_e32 v4, v3, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v3, v8, v4
	v_add_nc_u32_e32 v5, v3, v2
	v_add_nc_u32_e32 v3, v3, v1
.LBB0_7:                                ; %Flow
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_mov_b32 s0, 0
	s_branch .LBB0_9
.LBB0_8:                                ;   in Loop: Header=BB0_4 Depth=2
	s_mov_b32 s0, -1
                                        ; implicit-def: $vgpr3
                                        ; implicit-def: $vgpr5
                                        ; implicit-def: $vgpr4
.LBB0_9:                                ; %Flow109
                                        ;   in Loop: Header=BB0_4 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_11
; %bb.10:                               ;   in Loop: Header=BB0_4 Depth=2
	global_load_b64 v[9:10], v7, s[24:25]
	s_ashr_i32 s0, s19, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_add_u32 s26, s18, s0
	s_mov_b32 s1, s0
	s_addc_u32 s27, s19, s0
	s_xor_b64 s[26:27], s[26:27], s[0:1]
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v3, s26
	v_cvt_f32_u32_e32 v4, s27
	s_sub_u32 s29, 0, s26
	s_subb_u32 s31, 0, s27
	v_fmac_f32_e32 v3, 0x4f800000, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, 0x5f7ffffc, v3
	v_mul_f32_e32 v4, 0x2f800000, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_trunc_f32_e32 v4, v4
	v_fmac_f32_e32 v3, 0xcf800000, v4
	v_cvt_u32_f32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v3, v3
	v_readfirstlane_b32 s13, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_readfirstlane_b32 s28, v3
	s_mul_i32 s33, s29, s13
	s_delay_alu instid0(VALU_DEP_1)
	s_mul_hi_u32 s35, s29, s28
	s_mul_i32 s34, s31, s28
	s_add_i32 s33, s35, s33
	s_mul_i32 s36, s29, s28
	s_add_i32 s33, s33, s34
	s_mul_hi_u32 s35, s28, s36
	s_mul_hi_u32 s37, s13, s36
	s_mul_i32 s34, s13, s36
	s_mul_hi_u32 s36, s28, s33
	s_mul_i32 s28, s28, s33
	s_mul_hi_u32 s38, s13, s33
	s_add_u32 s28, s35, s28
	s_addc_u32 s35, 0, s36
	s_add_u32 s28, s28, s34
	s_mul_i32 s33, s13, s33
	s_addc_u32 s28, s35, s37
	s_addc_u32 s34, s38, 0
	s_add_u32 s28, s28, s33
	s_addc_u32 s33, 0, s34
	v_add_co_u32 v3, s28, v3, s28
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_cmp_lg_u32 s28, 0
	s_addc_u32 s13, s13, s33
	v_readfirstlane_b32 s28, v3
	s_mul_i32 s33, s29, s13
	s_delay_alu instid0(VALU_DEP_1)
	s_mul_hi_u32 s34, s29, s28
	s_mul_i32 s31, s31, s28
	s_add_i32 s33, s34, s33
	s_mul_i32 s29, s29, s28
	s_add_i32 s33, s33, s31
	s_mul_hi_u32 s34, s13, s29
	s_mul_i32 s35, s13, s29
	s_mul_hi_u32 s29, s28, s29
	s_mul_hi_u32 s36, s28, s33
	s_mul_i32 s28, s28, s33
	s_mul_hi_u32 s31, s13, s33
	s_add_u32 s28, s29, s28
	s_addc_u32 s29, 0, s36
	s_add_u32 s28, s28, s35
	s_mul_i32 s33, s13, s33
	s_addc_u32 s28, s29, s34
	s_addc_u32 s29, s31, 0
	s_add_u32 s28, s28, s33
	s_addc_u32 s29, 0, s29
	v_add_co_u32 v3, s28, v3, s28
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	s_cmp_lg_u32 s28, 0
	s_addc_u32 s13, s13, s29
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s31, v10
	v_readfirstlane_b32 s33, v9
	s_ashr_i32 s28, s31, 31
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	s_add_u32 s34, s33, s28
	s_addc_u32 s35, s31, s28
	v_readfirstlane_b32 s31, v3
	s_mov_b32 s29, s28
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_xor_b64 s[34:35], s[34:35], s[28:29]
	s_mul_i32 s36, s34, s13
	s_delay_alu instid0(VALU_DEP_1)
	s_mul_hi_u32 s37, s34, s31
	s_mul_hi_u32 s33, s34, s13
	s_mul_hi_u32 s39, s35, s31
	s_mul_i32 s31, s35, s31
	s_add_u32 s36, s37, s36
	s_addc_u32 s33, 0, s33
	s_mul_hi_u32 s38, s35, s13
	s_add_u32 s31, s36, s31
	s_mul_i32 s13, s35, s13
	s_addc_u32 s31, s33, s39
	s_addc_u32 s33, s38, 0
	s_add_u32 s13, s31, s13
	s_addc_u32 s31, 0, s33
	s_mul_i32 s38, s26, s13
	s_mul_hi_u32 s33, s26, s13
	s_mul_i32 s37, s26, s31
	v_sub_co_u32 v3, s34, s34, s38
	s_mul_i32 s36, s27, s13
	s_add_i32 s33, s33, s37
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_i32 s33, s33, s36
	v_sub_co_u32 v4, s37, v3, s26
	s_sub_i32 s36, s35, s33
	s_cmp_lg_u32 s34, 0
	s_subb_u32 s36, s36, s27
	s_cmp_lg_u32 s37, 0
	v_readfirstlane_b32 s37, v4
	s_subb_u32 s36, s36, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_cmp_ge_u32 s36, s27
	s_cselect_b32 s38, -1, 0
	s_cmp_ge_u32 s37, s26
	s_cselect_b32 s37, -1, 0
	s_cmp_eq_u32 s36, s27
	s_cselect_b32 s36, s37, s38
	s_add_u32 s37, s13, 1
	s_addc_u32 s38, s31, 0
	s_add_u32 s39, s13, 2
	s_addc_u32 s40, s31, 0
	s_cmp_lg_u32 s36, 0
	s_cselect_b32 s36, s39, s37
	s_cselect_b32 s37, s40, s38
	s_cmp_lg_u32 s34, 0
	v_readfirstlane_b32 s34, v3
	s_subb_u32 s33, s35, s33
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	s_cmp_ge_u32 s33, s27
	s_cselect_b32 s35, -1, 0
	s_cmp_ge_u32 s34, s26
	s_cselect_b32 s26, -1, 0
	s_cmp_eq_u32 s33, s27
	s_cselect_b32 s26, s26, s35
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
	s_cmp_lg_u32 s26, 0
	s_cselect_b32 s27, s37, s31
	s_cselect_b32 s26, s36, s13
	s_xor_b64 s[0:1], s[28:29], s[0:1]
	s_xor_b64 s[26:27], s[26:27], s[0:1]
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_sub_u32 s13, s26, s0
	s_subb_u32 s1, s27, s1
	s_ashr_i32 s26, s1, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_add_u32 s0, s13, s26
	s_mov_b32 s27, s26
	s_addc_u32 s1, s1, s26
	s_xor_b64 s[28:29], s[0:1], s[26:27]
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
	v_cvt_f32_u32_e32 v3, s28
	v_cvt_f32_u32_e32 v4, s29
	s_sub_u32 s0, 0, s28
	s_subb_u32 s1, 0, s29
	v_fmac_f32_e32 v3, 0x4f800000, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v3, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v3, 0x5f7ffffc, v3
	v_mul_f32_e32 v4, 0x2f800000, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_trunc_f32_e32 v4, v4
	v_fmac_f32_e32 v3, 0xcf800000, v4
	v_cvt_u32_f32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v3, v3
	v_mul_lo_u32 v5, s0, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v6, s0, v3
	v_mul_lo_u32 v10, s1, v3
	v_add_nc_u32_e32 v5, v6, v5
	v_mul_lo_u32 v6, s0, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v5, v10
	v_mul_hi_u32 v10, v3, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_lo_u32 v11, v3, v5
	v_mul_hi_u32 v12, v3, v5
	v_mul_hi_u32 v13, v4, v6
	v_mul_lo_u32 v6, v4, v6
	v_mul_hi_u32 v14, v4, v5
	v_mul_lo_u32 v5, v4, v5
	v_add_co_u32 v10, vcc_lo, v10, v11
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v10, v6
	v_add_co_ci_u32_e32 v6, vcc_lo, v11, v13, vcc_lo
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v14, vcc_lo
	v_ashrrev_i32_e32 v13, 31, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v5, vcc_lo, v6, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, v5
	v_add_co_ci_u32_e32 v4, vcc_lo, v4, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v5, s0, v3
	v_mul_lo_u32 v10, s1, v3
	v_mul_lo_u32 v6, s0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v5, v5, v6
	v_mul_lo_u32 v6, s0, v3
	v_add_nc_u32_e32 v5, v5, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v10, v3, v6
	v_mul_lo_u32 v11, v3, v5
	v_mul_hi_u32 v12, v3, v5
	v_mul_hi_u32 v14, v4, v6
	v_mul_lo_u32 v6, v4, v6
	v_mul_hi_u32 v15, v4, v5
	v_mul_lo_u32 v5, v4, v5
	v_add_co_u32 v10, vcc_lo, v10, v11
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v12, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v6, vcc_lo, v10, v6
	v_add_co_ci_u32_e32 v6, vcc_lo, v11, v14, vcc_lo
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v15, vcc_lo
	v_add_co_u32 v11, vcc_lo, v8, v13
	v_add_co_ci_u32_e32 v12, vcc_lo, v13, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v5, vcc_lo, v6, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v14, v11, v13
	v_add_co_u32 v10, vcc_lo, v3, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v15, vcc_lo, v4, v6, vcc_lo
	v_xor_b32_e32 v12, v12, v13
	v_mul_hi_u32 v16, v14, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[3:4], null, v14, v15, 0
	v_mad_u64_u32 v[5:6], null, v12, v10, 0
	v_mad_u64_u32 v[10:11], null, v12, v15, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, v16, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v3, vcc_lo, v3, v5
	v_add_co_ci_u32_e32 v3, vcc_lo, v4, v6, vcc_lo
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v5, vcc_lo, v3, v10
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v10, s29, v5
	v_mad_u64_u32 v[3:4], null, s28, v5, 0
	v_mul_lo_u32 v6, s28, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_co_u32 v3, vcc_lo, v14, v3
	v_add3_u32 v4, v4, v6, v10
	v_add_nc_u32_e32 v10, 2, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v6, v12, v4
	v_subrev_co_ci_u32_e64 v6, s0, s29, v6, vcc_lo
	v_sub_co_u32 v11, s0, v3, s28
	v_sub_co_ci_u32_e32 v4, vcc_lo, v12, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_subrev_co_ci_u32_e64 v6, s0, 0, v6, s0
	v_cmp_le_u32_e32 vcc_lo, s28, v11
	v_cndmask_b32_e64 v11, 0, -1, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s29, v6
	v_cndmask_b32_e64 v12, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s28, v3
	v_cndmask_b32_e64 v3, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s29, v4
	v_cndmask_b32_e64 v14, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s29, v6
	v_cndmask_b32_e32 v6, v12, v11, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s29, v4
	v_add_nc_u32_e32 v11, 1, v5
	v_cndmask_b32_e32 v3, v14, v3, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cmp_ne_u32_e32 vcc_lo, 0, v6
	v_xor_b32_e32 v6, s26, v13
	v_cndmask_b32_e32 v4, v11, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ne_u32_e32 vcc_lo, 0, v3
	v_cndmask_b32_e32 v3, v5, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v3, v3, v6
	v_sub_nc_u32_e32 v10, v3, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v11, v10, s13
	v_mad_u64_u32 v[5:6], null, v11, s16, v[2:3]
	v_mad_u64_u32 v[3:4], null, v10, v9, v[1:2]
	v_sub_nc_u32_e32 v4, v8, v11
.LBB0_11:                               ;   in Loop: Header=BB0_4 Depth=2
	s_add_u32 s22, s22, 1
	s_addc_u32 s23, s23, 0
	s_add_u32 s24, s24, 8
	v_cmp_ge_i64_e64 s0, s[22:23], s[14:15]
	s_addc_u32 s25, s25, 0
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_13
; %bb.12:                               ;   in Loop: Header=BB0_4 Depth=2
	v_dual_mov_b32 v8, v4 :: v_dual_mov_b32 v1, v3
	v_mov_b32_e32 v2, v5
	s_branch .LBB0_4
.LBB0_13:                               ; %._crit_edge
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_lshl_b64 s[0:1], s[2:3], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s0, s10, s0
	s_addc_u32 s1, s11, s1
	s_clause 0x1
	global_load_b32 v4, v7, s[0:1]
	global_load_b64 v[1:2], v7, s[20:21]
	s_waitcnt vmcnt(1)
	v_trunc_f32_e32 v4, v4
	s_waitcnt vmcnt(0)
	v_readfirstlane_b32 s13, v1
	v_readfirstlane_b32 s26, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e64 v6, 0x2f800000, |v4|
	v_readfirstlane_b32 s0, v4
	v_floor_f32_e32 v6, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_ashr_i32 s0, s0, 31
	s_mov_b32 s1, s0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_not_b64 s[24:25], s[0:1]
	v_fma_f32 v8, 0xcf800000, v6, |v4|
	v_cvt_u32_f32_e32 v9, v6
	v_ashrrev_i32_e32 v6, 31, v5
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_u32_f32_e32 v8, v8
	v_readfirstlane_b32 s23, v9
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_lshlrev_b64 v[1:2], 2, v[5:6]
	v_lshlrev_b64 v[3:4], 2, v[3:4]
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_readfirstlane_b32 s22, v8
	s_xor_b64 s[0:1], s[22:23], s[0:1]
	s_mul_i32 s22, s13, s3
	s_add_u32 s0, s24, s0
	s_addc_u32 s1, s25, s1
	s_mul_i32 s23, s0, s26
	s_mul_hi_u32 s24, s0, s13
	s_mul_i32 s1, s1, s13
	s_add_i32 s23, s24, s23
	s_mul_i32 s0, s0, s13
	s_add_i32 s1, s23, s1
	s_mul_hi_u32 s23, s13, s2
	s_lshl_b64 s[0:1], s[0:1], 2
	s_mul_i32 s26, s26, s2
	s_add_u32 s24, s4, s0
	s_addc_u32 s25, s5, s1
	s_add_i32 s1, s23, s22
	s_mul_i32 s0, s13, s2
	s_add_i32 s1, s1, s26
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[0:1], s[0:1], 2
	s_add_u32 s0, s6, s0
	s_addc_u32 s1, s7, s1
	v_add_co_u32 v5, vcc_lo, s0, v1
	v_add_co_ci_u32_e32 v6, vcc_lo, s1, v2, vcc_lo
	v_add_co_u32 v1, vcc_lo, s24, v3
	v_add_co_ci_u32_e32 v2, vcc_lo, s25, v4, vcc_lo
	global_load_b32 v5, v[5:6], off
	global_load_b32 v4, v[1:2], off
	s_mov_b32 s0, 0
.LBB0_14:                               ; %atomicrmw.start
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_waitcnt vmcnt(0)
	v_add_f32_e32 v3, v4, v5
	global_atomic_cmpswap_b32 v3, v[1:2], v[3:4], off glc
	s_waitcnt vmcnt(0)
	v_cmp_eq_u32_e32 vcc_lo, v3, v4
	v_mov_b32_e32 v4, v3
	s_or_b32 s0, vcc_lo, s0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s0
	s_cbranch_execnz .LBB0_14
; %bb.15:                               ; %atomicrmw.end
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s0
	s_add_u32 s2, s2, 1
	s_addc_u32 s3, s3, 0
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_i64_e64 s0, s[2:3], s[16:17]
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccz .LBB0_2
.LBB0_16:                               ; %.loopexit
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z28THCudaTensor_kernel_indexAddPfS_PlS_lilll
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 328
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 18
		.amdhsa_next_free_sgpr 41
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z28THCudaTensor_kernel_indexAddPfS_PlS_lilll, .Lfunc_end0-_Z28THCudaTensor_kernel_indexAddPfS_PlS_lilll
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3584
; NumSgprs: 43
; NumVgprs: 18
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 5
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 43
; NumVGPRsForWavesPerEU: 18
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           8
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           8
        .value_kind:     by_value
      - .offset:         56
        .size:           8
        .value_kind:     by_value
      - .offset:         64
        .size:           8
        .value_kind:     by_value
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         76
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         80
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         84
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         86
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         88
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         90
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         92
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         94
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         128
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         136
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 328
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z28THCudaTensor_kernel_indexAddPfS_PlS_lilll
    .private_segment_fixed_size: 0
    .sgpr_count:     43
    .sgpr_spill_count: 0
    .symbol:         _Z28THCudaTensor_kernel_indexAddPfS_PlS_lilll.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     18
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
