extern "C"
__global__ void createKernels(
float* kernels,
int size,
int nrOfOrientations,
int nrOfScales,
float sigma_min,
int N)
{
    int index = threadIdx.x + blockIdx.x * blockDim.x;
    int orientation = threadIdx.x;
    int scale = blockIdx.x;

    if (index < N)
    {
        int s2 = size / 2;
        int nn = 11;
        float gamma = 20;
        // see: http://en.wikipedia.org/wiki/Gabor_filter

        float alpha = (3.141592654 * orientation) / nrOfOrientations;
        float sigma_adjusted = 0.6 * sigma_min * scale + sigma_min;
        float s2d_min = 2 * sigma_adjusted * sigma_adjusted;
        float s2d_max = 200;

        float lambda = 5 * sigma_adjusted;

        float totalSum = 0;
        for (int j = -s2; j <= s2; j++) {
            for (int i = -s2; i <= s2; i++) {
                float sum = 0;
                for (int ii = 0; ii < nn; ii++) {
                    float xx = i - 0.5 + (1 + 2 * ii) / (2.0 * nn);
                    for (int jj = 0; jj < nn; jj++)
                    {
                        float yy = j - 0.5 + (1 + 2 * jj) / (2.0 * nn);

                        float xx_ = yy * sinf(alpha) + xx * cosf(alpha);
                        float yy_ = yy * cosf(alpha) - xx * sinf(alpha);

                        //sum += expf(-(xx_ * xx_) / s2d_max - (yy_ * yy_) / s2d_min) * cosf(2 * 3.141592654 * yy_ / (size));
                        // Gabor filter
                        sum += expf(-(xx_ * xx_) / s2d_min / gamma  - (yy_ * yy_) / s2d_min) * cosf(2 * 3.141592654 * yy_ / lambda);
                    }
                }

                kernels[(i + s2) + (j + s2) * size + size * size * orientation + size * size * nrOfOrientations * scale] = sum;
                totalSum += sum;
            }
        }
        for (int j = -s2; j <= s2; j++) {
            for (int i = -s2; i <= s2; i++) {
                //kernels[(i + s2) + (j + s2) * size + size * size * orientation + size * size * nrOfOrientations * scale] /= totalSum;
            }
        }
    }
}

extern "C"
__global__ void applyKernels(
float* kernels,
float* inimg,
float* outimg,
int* positions,
int size,
int nrOfOrientations,
int scale,
int dimsx,
int dimsy,
int N_threads,
int NN)
{
    int index = threadIdx.x + blockIdx.x * blockDim.x;
    int tid = index;

    while (tid < NN)
    {
        int x = positions[2 * tid];
        int y = positions[2 * tid + 1];
        int s2 = size / 2;

        int bestOrientation = 0;
        float bestResponse = 0;
        for (int r = 0; r < nrOfOrientations; r++) {
            float sum = 0;
            for (int j = -s2; j <= s2; j++) {
                for (int i = -s2; i <= s2; i++) {
                    sum += inimg[x + i + dimsx * (y + j)] * kernels[i + s2 + size * (j + s2) + size * size * r + size * size * nrOfOrientations * scale];
                }
            }
            if (sum > bestResponse) {
                bestResponse = sum;
                bestOrientation = r;
            }
        }
        if (outimg[x + dimsx * y] < bestResponse)
        {
            outimg[x + dimsx * y] = bestResponse;
        }

        tid += N_threads;
    }

 }
	.file	"tmpxft_003a5b29_00000000-6_myCUDA.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z38__device_stub__Z13createKernelsPfiiifiPfiiifi
	.type	_Z38__device_stub__Z13createKernelsPfiiifiPfiiifi, @function
_Z38__device_stub__Z13createKernelsPfiiifiPfiiifi:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$168, %rsp
	.cfi_def_cfa_offset 176
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movl	%esi, 20(%rsp)
	leaq	68(%rsp), %rsi
	movl	%edx, 16(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 12(%rsp)
	leaq	48(%rsp), %rcx
	movl	%r8d, 4(%rsp)
	movss	%xmm0, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 152(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	20(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 144(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	48(%rsp)
	.cfi_def_cfa_offset 184
	leaq	createKernels(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 192
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 184
	popq	%rdx
	.cfi_def_cfa_offset 176
.L2:
	movq	152(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$168, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z38__device_stub__Z13createKernelsPfiiifiPfiiifi, .-_Z38__device_stub__Z13createKernelsPfiiifiPfiiifi
	.globl	createKernels
	.type	createKernels, @function
createKernels:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z38__device_stub__Z13createKernelsPfiiifiPfiiifi
	.cfi_endproc
.LFE2033:
	.size	createKernels, .-createKernels
	.globl	_Z45__device_stub__Z12applyKernelsPfS_S_PiiiiiiiiPfS_S_Piiiiiiii
	.type	_Z45__device_stub__Z12applyKernelsPfS_S_PiiiiiiiiPfS_S_Piiiiiiii, @function
_Z45__device_stub__Z12applyKernelsPfS_S_PiiiiiiiiPfS_S_Piiiiiiii:
.LFB2034:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movl	%r9d, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	232(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	248(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	256(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	56(%rsp)
	.cfi_def_cfa_offset 232
	leaq	applyKernels(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 240
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L8:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2034:
	.size	_Z45__device_stub__Z12applyKernelsPfS_S_PiiiiiiiiPfS_S_Piiiiiiii, .-_Z45__device_stub__Z12applyKernelsPfS_S_PiiiiiiiiPfS_S_Piiiiiiii
	.globl	applyKernels
	.type	applyKernels, @function
applyKernels:
.LFB2035:
	.cfi_startproc
	endbr64
	jmp	_Z45__device_stub__Z12applyKernelsPfS_S_PiiiiiiiiPfS_S_Piiiiiiii
	.cfi_endproc
.LFE2035:
	.size	applyKernels, .-applyKernels
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"applyKernels"
.LC1:
	.string	"createKernels"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2037:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	applyKernels(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	createKernels(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2037:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
extern "C"
__global__ void createKernels(
float* kernels,
int size,
int nrOfOrientations,
int nrOfScales,
float sigma_min,
int N)
{
    int index = threadIdx.x + blockIdx.x * blockDim.x;
    int orientation = threadIdx.x;
    int scale = blockIdx.x;

    if (index < N)
    {
        int s2 = size / 2;
        int nn = 11;
        float gamma = 20;
        // see: http://en.wikipedia.org/wiki/Gabor_filter

        float alpha = (3.141592654 * orientation) / nrOfOrientations;
        float sigma_adjusted = 0.6 * sigma_min * scale + sigma_min;
        float s2d_min = 2 * sigma_adjusted * sigma_adjusted;
        float s2d_max = 200;

        float lambda = 5 * sigma_adjusted;

        float totalSum = 0;
        for (int j = -s2; j <= s2; j++) {
            for (int i = -s2; i <= s2; i++) {
                float sum = 0;
                for (int ii = 0; ii < nn; ii++) {
                    float xx = i - 0.5 + (1 + 2 * ii) / (2.0 * nn);
                    for (int jj = 0; jj < nn; jj++)
                    {
                        float yy = j - 0.5 + (1 + 2 * jj) / (2.0 * nn);

                        float xx_ = yy * sinf(alpha) + xx * cosf(alpha);
                        float yy_ = yy * cosf(alpha) - xx * sinf(alpha);

                        //sum += expf(-(xx_ * xx_) / s2d_max - (yy_ * yy_) / s2d_min) * cosf(2 * 3.141592654 * yy_ / (size));
                        // Gabor filter
                        sum += expf(-(xx_ * xx_) / s2d_min / gamma  - (yy_ * yy_) / s2d_min) * cosf(2 * 3.141592654 * yy_ / lambda);
                    }
                }

                kernels[(i + s2) + (j + s2) * size + size * size * orientation + size * size * nrOfOrientations * scale] = sum;
                totalSum += sum;
            }
        }
        for (int j = -s2; j <= s2; j++) {
            for (int i = -s2; i <= s2; i++) {
                //kernels[(i + s2) + (j + s2) * size + size * size * orientation + size * size * nrOfOrientations * scale] /= totalSum;
            }
        }
    }
}

extern "C"
__global__ void applyKernels(
float* kernels,
float* inimg,
float* outimg,
int* positions,
int size,
int nrOfOrientations,
int scale,
int dimsx,
int dimsy,
int N_threads,
int NN)
{
    int index = threadIdx.x + blockIdx.x * blockDim.x;
    int tid = index;

    while (tid < NN)
    {
        int x = positions[2 * tid];
        int y = positions[2 * tid + 1];
        int s2 = size / 2;

        int bestOrientation = 0;
        float bestResponse = 0;
        for (int r = 0; r < nrOfOrientations; r++) {
            float sum = 0;
            for (int j = -s2; j <= s2; j++) {
                for (int i = -s2; i <= s2; i++) {
                    sum += inimg[x + i + dimsx * (y + j)] * kernels[i + s2 + size * (j + s2) + size * size * r + size * size * nrOfOrientations * scale];
                }
            }
            if (sum > bestResponse) {
                bestResponse = sum;
                bestOrientation = r;
            }
        }
        if (outimg[x + dimsx * y] < bestResponse)
        {
            outimg[x + dimsx * y] = bestResponse;
        }

        tid += N_threads;
    }

 }
	.text
	.file	"myCUDA.hip"
	.globl	__device_stub__createKernels    # -- Begin function __device_stub__createKernels
	.type	__device_stub__createKernels,@function
__device_stub__createKernels:           # @__device_stub__createKernels
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$128, %rsp
	.cfi_def_cfa_offset 176
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	20(%rsp), %rdi
	movl	%esi, (%rdi)
	leaq	16(%rsp), %rsi
	movl	%edx, (%rsi)
	leaq	12(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	8(%rsp), %rcx
	movss	%xmm0, (%rcx)
	leaq	4(%rsp), %r9
	movl	%r8d, (%r9)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r9, 40(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	32(%rsp), %r12
	leaq	24(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$createKernels, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$144, %rsp
	.cfi_adjust_cfa_offset -144
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	__device_stub__createKernels, .Lfunc_end0-__device_stub__createKernels
	.cfi_endproc
                                        # -- End function
	.globl	__device_stub__applyKernels     # -- Begin function __device_stub__applyKernels
	.type	__device_stub__applyKernels,@function
__device_stub__applyKernels:            # @__device_stub__applyKernels
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$192, %rsp
	.cfi_def_cfa_offset 240
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	256(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	264(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	272(%rsp), %rax
	movq	%rax, 80(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$applyKernels, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$208, %rsp
	.cfi_adjust_cfa_offset -208
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	__device_stub__applyKernels, .Lfunc_end1-__device_stub__applyKernels
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$createKernels, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$applyKernels, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	createKernels,@object           # @createKernels
	.section	.rodata,"a",@progbits
	.globl	createKernels
	.p2align	3, 0x0
createKernels:
	.quad	__device_stub__createKernels
	.size	createKernels, 8

	.type	applyKernels,@object            # @applyKernels
	.globl	applyKernels
	.p2align	3, 0x0
applyKernels:
	.quad	__device_stub__applyKernels
	.size	applyKernels, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"createKernels"
	.size	.L__unnamed_1, 14

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"applyKernels"
	.size	.L__unnamed_2, 13

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __device_stub__createKernels
	.addrsig_sym __device_stub__applyKernels
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym createKernels
	.addrsig_sym applyKernels
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	createKernels           ; -- Begin function createKernels
	.globl	createKernels
	.p2align	8
	.type	createKernels,@function
createKernels:                          ; @createKernels
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x2c
	s_load_b64 s[2:3], s[0:1], 0x14
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s4, v[0:1]
	v_cmp_gt_i32_e32 vcc_lo, s3, v1
	s_and_saveexec_b32 s3, vcc_lo
	s_cbranch_execz .LBB0_14
; %bb.1:
	s_load_b64 s[4:5], s[0:1], 0x8
	s_waitcnt lgkmcnt(0)
	s_cmp_lt_i32 s4, -1
	s_cbranch_scc1 .LBB0_14
; %bb.2:                                ; %.preheader123.lr.ph
	v_cvt_f64_i32_e32 v[1:2], v0
	s_mov_b32 s7, 0x400921fb
	s_mov_b32 s6, 0x54524550
	v_cvt_f64_i32_e32 v[3:4], s5
	s_mov_b32 s9, 0x7fffff
	s_mov_b32 s10, 0x33333333
	s_mov_b32 s11, 0x3fe33333
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mul_f64 v[1:2], v[1:2], s[6:7]
	s_lshr_b32 s7, s4, 31
	v_div_scale_f64 v[5:6], null, v[3:4], v[3:4], v[1:2]
	v_div_scale_f64 v[11:12], vcc_lo, v[1:2], v[3:4], v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[7:8], v[5:6]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[9:10], -v[5:6], v[7:8], 1.0
	v_fma_f64 v[7:8], v[7:8], v[9:10], v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[9:10], v[11:12], v[7:8]
	v_fma_f64 v[5:6], -v[5:6], v[9:10], v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f64 v[5:6], v[5:6], v[7:8], v[9:10]
	v_cvt_f64_f32_e32 v[8:9], s2
	v_div_fixup_f64 v[1:2], v[5:6], v[3:4], v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_f64 v[16:17], v[8:9], s[10:11]
	s_mov_b32 s10, 0xb94c1982
	s_mov_b32 s11, 0x37d75334
	v_cvt_f32_f64_e32 v18, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v2, 0 :: v_dual_and_b32 v19, 0x7fffffff, v18
	v_and_or_b32 v14, v19, s9, 0x800000
	v_lshrrev_b32_e32 v10, 23, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, 0xfe5163ab, v14, 0
	v_mov_b32_e32 v1, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[4:5], null, 0x3c439041, v14, v[1:2]
	v_mov_b32_e32 v1, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[5:6], null, 0xdb629599, v14, v[1:2]
	v_mov_b32_e32 v1, v6
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[6:7], null, 0xf534ddc0, v14, v[1:2]
	v_mov_b32_e32 v1, v7
	v_add_nc_u32_e32 v7, 0xffffff88, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[10:11], null, 0xfc2757d1, v14, v[1:2]
	v_cmp_lt_u32_e32 vcc_lo, 63, v7
	v_cndmask_b32_e32 v4, v6, v4, vcc_lo
	v_cndmask_b32_e64 v12, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mov_b32_e32 v1, v11
	v_cndmask_b32_e32 v3, v5, v3, vcc_lo
	v_add_nc_u32_e32 v7, v12, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[11:12], null, 0x4e441529, v14, v[1:2]
	v_cmp_lt_u32_e64 s2, 31, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v1, v12
	v_cndmask_b32_e64 v13, 0, 0xffffffe0, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e32 v20, v11, v6, vcc_lo
	v_cndmask_b32_e64 v3, v4, v3, s2
	v_add_nc_u32_e32 v7, v13, v7
	v_mad_u64_u32 v[12:13], null, 0xa2f9836e, v14, v[1:2]
	v_cvt_f64_i32_e32 v[14:15], s15
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_lt_u32_e64 s3, 31, v7
	v_cndmask_b32_e32 v12, v12, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v1, 0, 0xffffffe0, s3
	v_dual_cndmask_b32 v11, v13, v11 :: v_dual_cndmask_b32 v10, v10, v5
	v_cndmask_b32_e64 v6, v12, v20, s2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v1, v1, v7
	v_cndmask_b32_e64 v7, v11, v12, s2
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v11, v20, v10, s2
	v_cndmask_b32_e64 v10, v10, v4, s2
	v_sub_nc_u32_e32 v12, 32, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v7, v7, v6, s3
	v_cndmask_b32_e64 v6, v6, v11, s3
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v11, v11, v10, s3
	v_cmp_eq_u32_e32 vcc_lo, 0, v1
	v_alignbit_b32 v13, v7, v6, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v5, v6, v11, v12
	v_cndmask_b32_e32 v1, v13, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2)
	v_cndmask_b32_e32 v5, v5, v6, vcc_lo
	v_cndmask_b32_e64 v7, v10, v3, s3
	s_load_b64 s[2:3], s[0:1], 0x0
	s_add_i32 s0, s4, s7
	v_bfe_u32 v6, v1, 29, 1
	v_alignbit_b32 v3, v1, v5, 30
	v_alignbit_b32 v4, v11, v7, v12
	s_ashr_i32 s8, s0, 1
	s_mov_b32 s7, 0x401921fb
	v_sub_nc_u32_e32 v10, 0, v6
	s_abs_i32 s12, s8
	v_cndmask_b32_e32 v11, v4, v11, vcc_lo
	v_cmp_gt_f32_e64 vcc_lo, 0x48000000, |v18|
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v12, v3, v10
	v_fma_f64 v[3:4], v[16:17], v[14:15], v[8:9]
	v_alignbit_b32 v5, v5, v11, 30
	v_alignbit_b32 v7, v11, v7, 30
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_clz_i32_u32_e32 v13, v12
	v_xor_b32_e32 v5, v5, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v7, v7, v10
	v_min_u32_e32 v8, 32, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v9, 31, v8
	v_lshlrev_b32_e32 v13, 23, v8
	v_alignbit_b32 v10, v12, v5, v9
	v_alignbit_b32 v5, v5, v7, v9
	v_lshrrev_b32_e32 v9, 29, v1
	v_lshrrev_b32_e32 v1, 30, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v7, v10, v5, 9
	v_lshrrev_b32_e32 v10, 9, v10
	v_add_nc_u32_e32 v1, v6, v1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_clz_i32_u32_e32 v11, v7
	v_min_u32_e32 v11, 32, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v14, 31, v11
	v_alignbit_b32 v5, v7, v5, v14
	v_cvt_f32_f64_e32 v7, v[3:4]
	v_add_lshl_u32 v4, v11, v8, 23
	v_mul_f32_e64 v8, 0x3f22f983, |v18|
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshrrev_b32_e32 v5, 9, v5
	v_sub_nc_u32_e32 v4, v5, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rndne_f32_e32 v5, v8
	v_add_nc_u32_e32 v4, 0x33000000, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v11, 0xbfc90fda, v5, |v18|
	v_fmac_f32_e32 v11, 0xb3a22168, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v11, 0xa7c234c4, v5
	v_lshlrev_b32_e32 v9, 31, v9
	v_cvt_i32_f32_e32 v5, v5
	v_or_b32_e32 v12, 0.5, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v1, v1, v5, vcc_lo
	v_sub_nc_u32_e32 v12, v12, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_or_b32_e32 v3, v10, v12
	v_mul_f32_e32 v10, 0x3fc90fda, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v8, 0x3fc90fda, v3, -v10
	v_fmac_f32_e32 v8, 0x33a22168, v3
	v_or_b32_e32 v3, v4, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v8, 0x3fc90fda, v3
	v_add_f32_e32 v3, v10, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v8, v3, v11, vcc_lo
	v_mul_f32_e32 v3, 0x40a00000, v7
	v_mul_f32_e32 v9, v8, v8
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_f64_f32_e32 v[3:4], v3
	v_fmaak_f32 v10, s10, v9, 0x3c0881c4
	v_fmaak_f32 v11, s11, v9, 0xbab64f3b
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmaak_f32 v6, v9, v10, 0xbe2aaa9d
	v_fmaak_f32 v10, v9, v11, 0x3d2aabf7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v5, v9, v6
	v_fmaak_f32 v6, v9, v10, 0xbf000004
	v_and_b32_e32 v10, 1, v1
	v_lshlrev_b32_e32 v1, 30, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v8, v8, v5
	v_fma_f32 v9, v9, v6, 1.0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_eq_u32_e32 vcc_lo, 0, v10
	v_mad_u64_u32 v[5:6], null, s15, s5, v[0:1]
	v_and_b32_e32 v0, 0x80000000, v1
	s_sub_i32 s5, 0, s8
	v_cndmask_b32_e32 v10, v9, v8, vcc_lo
	v_cndmask_b32_e64 v1, -v8, v9, vcc_lo
	v_add_f32_e32 v8, v7, v7
	v_cmp_class_f32_e64 vcc_lo, v18, 0x1f8
	s_mov_b32 s13, s5
	v_xor_b32_e32 v6, v10, v18
	v_xor_b32_e32 v11, v0, v1
	v_mul_f32_e32 v9, v8, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_xor3_b32 v6, v6, v19, v0
	v_mad_u64_u32 v[0:1], null, v5, s4, s[8:9]
	v_cndmask_b32_e32 v11, 0x7fc00000, v11, vcc_lo
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e32 v10, 0x7fc00000, v6, vcc_lo
.LBB0_3:                                ; %.preheader123
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_4 Depth 2
                                        ;       Child Loop BB0_5 Depth 3
                                        ;         Child Loop BB0_6 Depth 4
	v_cvt_f64_i32_e32 v[5:6], s13
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, s13, v0
	s_mov_b32 s14, s5
	v_mul_lo_u32 v12, v1, s4
	s_delay_alu instid0(VALU_DEP_3)
	v_add_f64 v[5:6], v[5:6], -0.5
.LBB0_4:                                ; %.preheader122
                                        ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_5 Depth 3
                                        ;         Child Loop BB0_6 Depth 4
	v_cvt_f64_i32_e32 v[7:8], s14
	v_mov_b32_e32 v13, 0
	s_mov_b32 s15, 0
	s_delay_alu instid0(VALU_DEP_2)
	v_add_f64 v[7:8], v[7:8], -0.5
.LBB0_5:                                ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_6 Depth 4
	s_lshl_b32 s0, s15, 1
	s_mov_b32 s16, 1
	s_or_b32 s0, s0, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_i32_e32 v[14:15], s0
	v_div_scale_f64 v[16:17], null, 0x40360000, 0x40360000, v[14:15]
	v_div_scale_f64 v[22:23], vcc_lo, v[14:15], 0x40360000, v[14:15]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[18:19], v[16:17]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0
	v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], -v[16:17], v[18:19], 1.0
	v_fma_f64 v[18:19], v[18:19], v[20:21], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[20:21], v[22:23], v[18:19]
	v_fma_f64 v[16:17], -v[16:17], v[20:21], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[16:17], v[16:17], v[18:19], v[20:21]
	v_div_fixup_f64 v[14:15], v[16:17], 0x40360000, v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[14:15], v[7:8], v[14:15]
	v_cvt_f32_f64_e32 v1, v[14:15]
	s_delay_alu instid0(VALU_DEP_1)
	v_mul_f32_e32 v14, v11, v1
	v_mul_f32_e32 v15, v10, v1
.LBB0_6:                                ; %_ZL4sinff.exit
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_4 Depth=2
                                        ;       Parent Loop BB0_5 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	v_cvt_f64_i32_e32 v[16:17], s16
                                        ; implicit-def: $vgpr1
	s_mov_b32 s1, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f64 v[18:19], null, 0x40360000, 0x40360000, v[16:17]
	v_div_scale_f64 v[24:25], vcc_lo, v[16:17], 0x40360000, v[16:17]
	v_rcp_f64_e32 v[20:21], v[18:19]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[22:23], -v[18:19], v[20:21], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[20:21], v[22:23], v[20:21]
	v_fma_f64 v[22:23], -v[18:19], v[20:21], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[20:21], v[20:21], v[22:23], v[20:21]
	v_mul_f64 v[22:23], v[24:25], v[20:21]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[18:19], -v[18:19], v[22:23], v[24:25]
	v_div_fmas_f64 v[18:19], v[18:19], v[20:21], v[22:23]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[16:17], v[18:19], 0x40360000, v[16:17]
	v_add_f64 v[16:17], v[5:6], v[16:17]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_f64_e32 v18, v[16:17]
	v_fma_f32 v17, v11, v18, -v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f64_f32_e32 v[19:20], v17
	v_mul_f64 v[19:20], v[19:20], s[6:7]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_scale_f64 v[21:22], null, v[3:4], v[3:4], v[19:20]
	v_rcp_f64_e32 v[23:24], v[21:22]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[25:26], -v[21:22], v[23:24], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[23:24], v[23:24], v[25:26], v[23:24]
	v_fma_f64 v[25:26], -v[21:22], v[23:24], 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[23:24], v[23:24], v[25:26], v[23:24]
	v_div_scale_f64 v[25:26], vcc_lo, v[19:20], v[3:4], v[19:20]
	v_mul_f64 v[27:28], v[25:26], v[23:24]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[21:22], -v[21:22], v[27:28], v[25:26]
	v_div_fmas_f64 v[21:22], v[21:22], v[23:24], v[27:28]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f64 v[19:20], v[21:22], v[3:4], v[19:20]
	v_cvt_f32_f64_e32 v16, v[19:20]
                                        ; implicit-def: $vgpr19
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_ngt_f32_e64 0x48000000, |v16|
	s_xor_b32 s17, exec_lo, s1
	s_cbranch_execz .LBB0_8
; %bb.7:                                ;   in Loop: Header=BB0_6 Depth=4
	v_and_b32_e32 v24, 0x7fffffff, v16
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_and_or_b32 v27, v24, s9, 0x800000
	v_mad_u64_u32 v[19:20], null, 0xfe5163ab, v27, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mov_b32_e32 v1, v20
	v_lshrrev_b32_e32 v24, 23, v24
	v_mad_u64_u32 v[20:21], null, 0x3c439041, v27, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v25, 0xffffff88, v24
	v_cmp_lt_u32_e32 vcc_lo, 63, v25
	v_cndmask_b32_e64 v26, 0, 0xffffffc0, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v1, v21 :: v_dual_add_nc_u32 v26, v26, v25
	v_mad_u64_u32 v[21:22], null, 0xdb629599, v27, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_lt_u32_e64 s0, 31, v26
	v_cndmask_b32_e32 v19, v21, v19, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v28, 0, 0xffffffe0, s0
	v_dual_mov_b32 v1, v22 :: v_dual_add_nc_u32 v28, v28, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[22:23], null, 0xf534ddc0, v27, v[1:2]
	v_cmp_lt_u32_e64 s1, 31, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_mov_b32 v1, v23 :: v_dual_cndmask_b32 v20, v22, v20
	v_mad_u64_u32 v[23:24], null, 0xfc2757d1, v27, v[1:2]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cndmask_b32_e64 v19, v20, v19, s0
	v_mov_b32_e32 v1, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[24:25], null, 0x4e441529, v27, v[1:2]
	v_mov_b32_e32 v1, v25
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[25:26], null, 0xa2f9836e, v27, v[1:2]
	v_cndmask_b32_e64 v1, 0, 0xffffffe0, s1
	v_cndmask_b32_e32 v27, v24, v22, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_nc_u32_e32 v1, v1, v28
	v_dual_cndmask_b32 v25, v25, v23 :: v_dual_cndmask_b32 v24, v26, v24
	v_cndmask_b32_e32 v23, v23, v21, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v26, 32, v1
	v_cndmask_b32_e64 v22, v25, v27, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v24, v24, v25, s0
	v_cndmask_b32_e64 v25, v27, v23, s0
	v_cndmask_b32_e64 v23, v23, v20, s0
	v_cmp_eq_u32_e32 vcc_lo, 0, v1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cndmask_b32_e64 v24, v24, v22, s1
	v_cndmask_b32_e64 v22, v22, v25, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v25, v25, v23, s1
	v_cndmask_b32_e64 v19, v23, v19, s1
	v_alignbit_b32 v27, v24, v22, v26
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_alignbit_b32 v21, v22, v25, v26
	v_dual_cndmask_b32 v1, v27, v24 :: v_dual_cndmask_b32 v20, v21, v22
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_alignbit_b32 v24, v25, v19, v26
	v_bfe_u32 v21, v1, 29, 1
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_alignbit_b32 v22, v1, v20, 30
	v_cndmask_b32_e32 v24, v24, v25, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_sub_nc_u32_e32 v23, 0, v21
	v_alignbit_b32 v20, v20, v24, 30
	v_alignbit_b32 v19, v24, v19, 30
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_xor_b32_e32 v22, v22, v23
	v_xor_b32_e32 v20, v20, v23
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_xor_b32_e32 v19, v19, v23
	v_lshrrev_b32_e32 v23, 29, v1
	v_clz_i32_u32_e32 v25, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b32_e32 v23, 31, v23
	v_min_u32_e32 v25, 32, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_or_b32_e32 v26, 0.5, v23
	v_sub_nc_u32_e32 v24, 31, v25
	v_lshlrev_b32_e32 v27, 23, v25
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_alignbit_b32 v22, v22, v20, v24
	v_alignbit_b32 v19, v20, v19, v24
	v_sub_nc_u32_e32 v26, v26, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_alignbit_b32 v20, v22, v19, 9
	v_lshrrev_b32_e32 v22, 9, v22
	v_clz_i32_u32_e32 v24, v20
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_min_u32_e32 v24, 32, v24
	v_sub_nc_u32_e32 v28, 31, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_alignbit_b32 v19, v20, v19, v28
	v_or_b32_e32 v20, v22, v26
	v_add_lshl_u32 v22, v24, v25, 23
	v_lshrrev_b32_e32 v19, 9, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v24, 0x3fc90fda, v20
	v_sub_nc_u32_e32 v19, v19, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v22, 0x3fc90fda, v20, -v24
	v_add_nc_u32_e32 v19, 0x33000000, v19
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v22, 0x33a22168, v20
	v_or_b32_e32 v19, v19, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v22, 0x3fc90fda, v19
	v_lshrrev_b32_e32 v19, 30, v1
	v_add_f32_e32 v1, v24, v22
	s_delay_alu instid0(VALU_DEP_2)
	v_add_nc_u32_e32 v19, v21, v19
.LBB0_8:                                ; %Flow
                                        ;   in Loop: Header=BB0_6 Depth=4
	s_and_not1_saveexec_b32 s0, s17
; %bb.9:                                ;   in Loop: Header=BB0_6 Depth=4
	v_mul_f32_e64 v1, 0x3f22f983, |v16|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rndne_f32_e32 v19, v1
	v_fma_f32 v1, 0xbfc90fda, v19, |v16|
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v1, 0xb3a22168, v19
	v_fmac_f32_e32 v1, 0xa7c234c4, v19
	v_cvt_i32_f32_e32 v19, v19
; %bb.10:                               ; %_ZL4cosff.exit109
                                        ;   in Loop: Header=BB0_6 Depth=4
	s_or_b32 exec_lo, exec_lo, s0
	v_fma_f32 v18, v10, v18, v14
	s_add_i32 s16, s16, 2
	v_mul_f32_e32 v17, v17, v17
	s_cmp_eq_u32 s16, 23
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v18, v18, v18
	v_div_scale_f32 v20, null, v9, v9, v18
	v_div_scale_f32 v23, vcc_lo, v18, v9, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v21, v20
	s_waitcnt_depctr 0xfff
	v_fma_f32 v22, -v20, v21, 1.0
	v_fmac_f32_e32 v21, v22, v21
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v22, v23, v21
	v_fma_f32 v24, -v20, v22, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v22, v24, v21
	v_fma_f32 v20, -v20, v22, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v20, v20, v21, v22
	v_div_scale_f32 v21, null, v9, v9, v17
	v_div_fixup_f32 v18, v20, v9, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v23, v21
	v_div_scale_f32 v20, null, 0xc1a00000, 0xc1a00000, v18
	v_div_scale_f32 v26, vcc_lo, v18, 0xc1a00000, v18
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v22, v20
	s_waitcnt_depctr 0xfff
	v_fma_f32 v25, -v21, v23, 1.0
	v_fmac_f32_e32 v23, v25, v23
	v_fma_f32 v24, -v20, v22, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_fmac_f32_e32 v22, v24, v22
	v_div_scale_f32 v24, s0, v17, v9, v17
	v_mul_f32_e32 v25, v26, v22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v27, v24, v23
	v_fma_f32 v28, -v20, v25, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v25, v28, v22
	v_fma_f32 v20, -v20, v25, v26
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v20, v20, v22, v25
	s_mov_b32 vcc_lo, s0
	v_div_fixup_f32 v18, v20, 0xc1a00000, v18
	v_mul_f32_e32 v20, v1, v1
	v_fma_f32 v29, -v21, v27, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v27, v29, v23
	v_fma_f32 v21, -v21, v27, v24
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmaak_f32 v24, s11, v20, 0xbab64f3b
	v_div_fmas_f32 v21, v21, v23, v27
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fmaak_f32 v24, v20, v24, 0x3d2aabf7
	v_div_fixup_f32 v17, v21, v9, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_f32_e32 v17, v18, v17
	v_mul_f32_e32 v18, 0x3fb8aa3b, v17
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_fma_f32 v21, 0x3fb8aa3b, v17, -v18
	v_rndne_f32_e32 v22, v18
	v_fmaak_f32 v23, s10, v20, 0x3c0881c4
	v_dual_fmac_f32 v21, 0x32a5705f, v17 :: v_dual_sub_f32 v18, v18, v22
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_fmaak_f32 v23, v20, v23, 0xbe2aaa9d :: v_dual_add_f32 v18, v18, v21
	v_mul_f32_e32 v21, v20, v23
	v_dual_fmaak_f32 v23, v20, v24, 0xbf000004 :: v_dual_and_b32 v24, 1, v19
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_exp_f32_e32 v18, v18
	v_fmac_f32_e32 v1, v1, v21
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_fma_f32 v20, v20, v23, 1.0
	v_cvt_i32_f32_e32 v21, v22
	v_cmp_eq_u32_e32 vcc_lo, 0, v24
	v_cndmask_b32_e64 v1, -v1, v20, vcc_lo
	s_waitcnt_depctr 0xfff
	v_ldexp_f32 v18, v18, v21
	v_cmp_ngt_f32_e32 vcc_lo, 0xc2ce8ed0, v17
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v18, 0, v18 :: v_dual_lshlrev_b32 v19, 30, v19
	v_cmp_class_f32_e64 vcc_lo, v16, 0x1f8
	v_and_b32_e32 v19, 0x80000000, v19
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_xor_b32_e32 v1, v19, v1
	v_cndmask_b32_e32 v1, 0x7fc00000, v1, vcc_lo
	v_cmp_nlt_f32_e32 vcc_lo, 0x42b17218, v17
	v_cndmask_b32_e32 v16, 0x7f800000, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v13, v16, v1
	s_cbranch_scc0 .LBB0_6
; %bb.11:                               ;   in Loop: Header=BB0_5 Depth=3
	s_add_i32 s15, s15, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_eq_u32 s15, 11
	s_cbranch_scc0 .LBB0_5
; %bb.12:                               ;   in Loop: Header=BB0_4 Depth=2
	v_add3_u32 v7, s14, s8, v12
	s_add_i32 s0, s14, 1
	s_cmp_eq_u32 s14, s12
	s_mov_b32 s14, s0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v8, 31, v7
	v_lshlrev_b64 v[7:8], 2, v[7:8]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v7, vcc_lo, s2, v7
	v_add_co_ci_u32_e32 v8, vcc_lo, s3, v8, vcc_lo
	global_store_b32 v[7:8], v13, off
	s_cbranch_scc0 .LBB0_4
; %bb.13:                               ; %._crit_edge
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_add_i32 s0, s13, 1
	s_cmp_eq_u32 s13, s12
	s_mov_b32 s13, s0
	s_cbranch_scc0 .LBB0_3
.LBB0_14:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel createKernels
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 288
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 30
		.amdhsa_next_free_sgpr 18
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	createKernels, .Lfunc_end0-createKernels
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 3252
; NumSgprs: 20
; NumVgprs: 30
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 3
; NumSGPRsForWavesPerEU: 20
; NumVGPRsForWavesPerEU: 30
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.protected	applyKernels            ; -- Begin function applyKernels
	.globl	applyKernels
	.p2align	8
	.type	applyKernels,@function
applyKernels:                           ; @applyKernels
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x4c
	s_load_b64 s[12:13], s[0:1], 0x34
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_mov_b32 s2, exec_lo
	v_cmpx_gt_i32_e64 s13, v1
	s_cbranch_execz .LBB1_14
; %bb.1:                                ; %.lr.ph85
	s_clause 0x1
	s_load_b128 s[8:11], s[0:1], 0x20
	s_load_b256 s[0:7], s[0:1], 0x0
	v_mov_b32_e32 v0, 0
	s_mov_b32 s16, 0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s14, s8, 31
	s_mul_i32 s22, s10, s9
	s_add_i32 s14, s8, s14
	s_mul_i32 s20, s8, s8
	s_ashr_i32 s14, s14, 1
	s_mul_i32 s22, s22, s20
	s_sub_i32 s17, 0, s14
	s_cmp_gt_i32 s9, 0
	s_cselect_b32 s10, -1, 0
	s_cmp_gt_i32 s8, -2
	s_cselect_b32 s18, -1, 0
	s_abs_i32 s19, s14
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s21, s14, s19
	s_add_i32 s21, s21, 1
.LBB1_2:                                ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB1_4 Depth 2
                                        ;       Child Loop BB1_6 Depth 3
                                        ;         Child Loop BB1_7 Depth 4
	v_lshlrev_b32_e32 v2, 1, v1
	v_mov_b32_e32 v6, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 2, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s7, v3, vcc_lo
	s_and_not1_b32 vcc_lo, exec_lo, s10
	global_load_b64 v[2:3], v[2:3], off
	s_cbranch_vccnz .LBB1_11
; %bb.3:                                ; %.lr.ph80.preheader
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_waitcnt vmcnt(0)
	v_add_nc_u32_e32 v4, s17, v3
	v_mov_b32_e32 v6, 0
	s_mov_b32 s23, 0
	s_mov_b32 s24, s22
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v4, s11, v4
	v_add3_u32 v7, s17, v2, v4
.LBB1_4:                                ; %.lr.ph80
                                        ;   Parent Loop BB1_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB1_6 Depth 3
                                        ;         Child Loop BB1_7 Depth 4
	v_mov_b32_e32 v8, 0
	s_and_not1_b32 vcc_lo, exec_lo, s18
	s_cbranch_vccnz .LBB1_10
; %bb.5:                                ; %.preheader.lr.ph
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_delay_alu instid0(VALU_DEP_2)
	v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, v7
	s_mov_b32 s25, s24
	s_mov_b32 s26, s17
.LBB1_6:                                ; %.preheader
                                        ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB1_7 Depth 4
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v4, v9
	s_mov_b32 s14, s25
	s_mov_b32 s27, s21
.LBB1_7:                                ;   Parent Loop BB1_2 Depth=1
                                        ;     Parent Loop BB1_4 Depth=2
                                        ;       Parent Loop BB1_6 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_ashrrev_i32_e32 v5, 31, v4
	s_ashr_i32 s15, s14, 31
	s_lshl_b64 s[28:29], s[14:15], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_add_u32 s28, s0, s28
	v_lshlrev_b64 v[10:11], 2, v[4:5]
	s_addc_u32 s29, s1, s29
	v_add_nc_u32_e32 v4, 1, v4
	s_add_i32 s27, s27, -1
	s_add_i32 s14, s14, 1
	s_cmp_eq_u32 s27, 0
	v_add_co_u32 v10, vcc_lo, s2, v10
	v_add_co_ci_u32_e32 v11, vcc_lo, s3, v11, vcc_lo
	global_load_b32 v5, v0, s[28:29]
	global_load_b32 v10, v[10:11], off
	s_waitcnt vmcnt(0)
	v_fmac_f32_e32 v8, v10, v5
	s_cbranch_scc0 .LBB1_7
; %bb.8:                                ; %._crit_edge
                                        ;   in Loop: Header=BB1_6 Depth=3
	v_add_nc_u32_e32 v9, s11, v9
	s_add_i32 s14, s26, 1
	s_add_i32 s25, s25, s8
	s_cmp_eq_u32 s26, s19
	s_cbranch_scc1 .LBB1_10
; %bb.9:                                ;   in Loop: Header=BB1_6 Depth=3
	s_mov_b32 s26, s14
	s_branch .LBB1_6
.LBB1_10:                               ; %._crit_edge75
                                        ;   in Loop: Header=BB1_4 Depth=2
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_gt_f32_e32 vcc_lo, v8, v6
	s_add_i32 s23, s23, 1
	s_add_i32 s24, s24, s20
	s_cmp_eq_u32 s23, s9
	v_cndmask_b32_e32 v6, v6, v8, vcc_lo
	s_cbranch_scc0 .LBB1_4
.LBB1_11:                               ; %Flow131
                                        ;   in Loop: Header=BB1_2 Depth=1
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[4:5], null, v3, s11, v[2:3]
	s_mov_b32 s14, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	v_lshlrev_b64 v[2:3], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s4, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s5, v3, vcc_lo
	global_load_b32 v4, v[2:3], off
	s_waitcnt vmcnt(0)
	v_cmpx_lt_f32_e32 v4, v6
	s_cbranch_execz .LBB1_13
; %bb.12:                               ;   in Loop: Header=BB1_2 Depth=1
	global_store_b32 v[2:3], v6, off
.LBB1_13:                               ;   in Loop: Header=BB1_2 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
	v_add_nc_u32_e32 v1, s12, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_le_i32_e32 vcc_lo, s13, v1
	s_or_b32 s16, vcc_lo, s16
	s_and_not1_b32 exec_lo, exec_lo, s16
	s_cbranch_execnz .LBB1_2
.LBB1_14:                               ; %._crit_edge86
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel applyKernels
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 320
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 12
		.amdhsa_next_free_sgpr 30
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	applyKernels, .Lfunc_end1-applyKernels
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 560
; NumSgprs: 32
; NumVgprs: 12
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 3
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 32
; NumVGPRsForWavesPerEU: 12
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     by_value
      - .offset:         20
        .size:           4
        .value_kind:     by_value
      - .offset:         24
        .size:           4
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         36
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         40
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         44
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         46
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         48
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         50
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         52
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         54
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         80
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         96
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 288
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           createKernels
    .private_segment_fixed_size: 0
    .sgpr_count:     20
    .sgpr_spill_count: 0
    .symbol:         createKernels.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     30
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     by_value
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         68
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         72
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         76
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         78
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         80
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         82
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         84
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         86
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         120
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         128
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 320
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           applyKernels
    .private_segment_fixed_size: 0
    .sgpr_count:     32
    .sgpr_spill_count: 0
    .symbol:         applyKernels.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     12
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
