#define BLOCK_SIZE 512
#include <stdio.h>
__global__ 
void force (float *virialArray, float *potentialArray, float *pval, float *vval, float *rx, float *ry, float *rz, float *fx, float *fy, float *fz, float sigma, float rcut, float vrcut, float dvrc12, float dvrcut, int *head, int *list, int mx, int my, int mz, int natoms, int step, float sfx, float sfy, float sfz)
{
   float sigsq, rcutsq;
   float rxi, ryi, rzi, fxi, fyi, fzi;
   float rxij, ryij, rzij, rijsq;
   float rij, sr2, sr6, vij, wij, fij, fxij, fyij, fzij;
   float potential, virial;
   int i, icell, j, jcell, nabor;
   int xi, yi, zi, ix, jx, kx, xcell, ycell, zcell;
   __shared__ float vArray[BLOCK_SIZE];
   __shared__ float pArray[BLOCK_SIZE];
   int p_start = BLOCK_SIZE;
   sigsq  = sigma*sigma;
   rcutsq = rcut*rcut;

   potential = 0.0f;
   virial    = 0.0f;
   
   int element = blockIdx.x * blockDim.x + threadIdx.x;
   if (element < natoms)
   {
  	 rxi = rx[element];
  	 ryi = ry[element];
  	 rzi = rz[element];
  	 fxi = 0.0f;
  	 fyi = 0.0f;
  	 fzi = 0.0f;
  	 xi = (int)((rxi+0.5f)/sfx) + 1;
  	 yi = (int)((ryi+0.5f)/sfy) + 1;
  	 zi = (int)((rzi+0.5f)/sfz) + 1;
           if(xi > mx) xi = mx;
           if(yi > my) yi = my;
           if(zi > mz) zi = mz;
  	   icell = xi + (mx+2)*(yi+zi*(my+2));
           for (ix=-1;ix<=1;ix++)
               for (jx=-1;jx<=1;jx++)
                   for (kx=-1;kx<=1;kx++){
  		     xcell = ix+xi;
  		     ycell = jx+yi;
  		     zcell = kx+zi;
                       jcell = xcell + (mx+2)*(ycell+(my+2)*zcell);
                       j = head[jcell];
                       while (j>=0) {
                           if (j!=element) {
                               rxij = rxi - rx[j];
                               ryij = ryi - ry[j];
                               rzij = rzi - rz[j];
                               rijsq = rxij*rxij + ryij*ryij + rzij*rzij;
                               if (rijsq < rcutsq) {
  			                           //START FORCE_IJ
                                    
                                    rij = (float) sqrt ((float)rijsq);
                                    sr2 = sigsq/rijsq;
                                    sr6 = sr2*sr2*sr2;
                                    vij = sr6*(sr6-1.0f) - vrcut - dvrc12*(rij-rcut);
                                    wij = sr6*(sr6-0.5f) + dvrcut*rij;
                                    fij = wij/rijsq;
                                    fxij = fij*rxij;
                                    fyij = fij*ryij;
                                    fzij = fij*rzij;
                                   //END FORCE_IJ
                                   wij *= 0.5f;
                                   vij *= 0.5f;
                                   potential += vij;
                                   virial    += wij;
                                   fxi       += fxij;
                                   fyi       += fyij;
                                   fzi       += fzij;
                               }
  			 }
                           j = list[j];
                        }
  	         }
           *(fx+element) = 48.0f*fxi;
           *(fy+element) = 48.0f*fyi;
           *(fz+element) = 48.0f*fzi;

            vArray[threadIdx.x] = virial;
            pArray[threadIdx.x] = potential;
            unsigned int stride;
            unsigned int t = threadIdx.x;
            __syncthreads();
            if (t == 0)
            {
             // __syncthreads();
              for(stride = 1; stride < blockDim.x; stride += 1)
              {
                vArray[t]+= vArray[stride];
                pArray[t]+= pArray[stride];
              }
            }
            //__syncthreads();
            if(t == 0)
            {
              virialArray[blockIdx.x] = vArray[0];
              potentialArray[blockIdx.x] = pArray[0];
            }


     }

}

	.file	"tmpxft_002f1fd4_00000000-6_force.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2029:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2029:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z60__device_stub__Z5forcePfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifffPfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifff
	.type	_Z60__device_stub__Z5forcePfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifffPfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifff, @function
_Z60__device_stub__Z5forcePfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifffPfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifff:
.LFB2051:
	.cfi_startproc
	endbr64
	subq	$408, %rsp
	.cfi_def_cfa_offset 416
	movq	416(%rsp), %rax
	movq	%rdi, 120(%rsp)
	leaq	144(%rsp), %rdi
	movq	%rsi, 112(%rsp)
	leaq	156(%rsp), %rsi
	movq	%rax, 72(%rsp)
	movq	424(%rsp), %rax
	movq	%rdx, 104(%rsp)
	leaq	128(%rsp), %rdx
	movq	%rax, 64(%rsp)
	movq	432(%rsp), %rax
	movq	%rcx, 96(%rsp)
	leaq	136(%rsp), %rcx
	movq	%rax, 56(%rsp)
	movq	440(%rsp), %rax
	movq	%r8, 88(%rsp)
	movq	%rax, 48(%rsp)
	movq	448(%rsp), %rax
	movq	%r9, 80(%rsp)
	movq	%rax, 16(%rsp)
	movq	456(%rsp), %rax
	movss	%xmm0, 44(%rsp)
	movq	%rax, 8(%rsp)
	movss	%xmm1, 40(%rsp)
	movss	%xmm2, 36(%rsp)
	movss	%xmm3, 32(%rsp)
	movss	%xmm4, 28(%rsp)
	movss	%xmm5, 24(%rsp)
	movss	%xmm6, 4(%rsp)
	movss	%xmm7, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 392(%rsp)
	xorl	%eax, %eax
	leaq	120(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	112(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	104(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	96(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	88(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 248(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 256(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 264(%rsp)
	leaq	44(%rsp), %rax
	movq	%rax, 272(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 280(%rsp)
	leaq	36(%rsp), %rax
	movq	%rax, 288(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 296(%rsp)
	leaq	28(%rsp), %rax
	movq	%rax, 304(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 312(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 320(%rsp)
	leaq	464(%rsp), %rax
	movq	%rax, 328(%rsp)
	leaq	472(%rsp), %rax
	movq	%rax, 336(%rsp)
	leaq	480(%rsp), %rax
	movq	%rax, 344(%rsp)
	leaq	488(%rsp), %rax
	movq	%rax, 352(%rsp)
	leaq	496(%rsp), %rax
	movq	%rax, 360(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 368(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 376(%rsp)
	movq	%rsp, %rax
	movq	%rax, 384(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 144(%rsp)
	movl	$1, 152(%rsp)
	movq	%rax, 156(%rsp)
	movl	$1, 164(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	136(%rsp)
	.cfi_def_cfa_offset 424
	leaq	_Z5forcePfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifff(%rip), %rdi
	pushq	136(%rsp)
	.cfi_def_cfa_offset 432
	movq	172(%rsp), %rcx
	movl	180(%rsp), %r8d
	movq	160(%rsp), %rsi
	movl	168(%rsp), %edx
	leaq	208(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 424
	popq	%rdx
	.cfi_def_cfa_offset 416
.L2:
	movq	392(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$408, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2051:
	.size	_Z60__device_stub__Z5forcePfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifffPfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifff, .-_Z60__device_stub__Z5forcePfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifffPfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifff
	.globl	_Z5forcePfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifff
	.type	_Z5forcePfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifff, @function
_Z5forcePfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifff:
.LFB2052:
	.cfi_startproc
	endbr64
	jmp	_Z60__device_stub__Z5forcePfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifffPfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifff
	.cfi_endproc
.LFE2052:
	.size	_Z5forcePfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifff, .-_Z5forcePfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifff
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z5forcePfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifff"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2054:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z5forcePfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifff(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2054:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#define BLOCK_SIZE 512

#include <hip/hip_runtime.h>
#include <stdio.h>
__global__ 
void force (float *virialArray, float *potentialArray, float *pval, float *vval, float *rx, float *ry, float *rz, float *fx, float *fy, float *fz, float sigma, float rcut, float vrcut, float dvrc12, float dvrcut, int *head, int *list, int mx, int my, int mz, int natoms, int step, float sfx, float sfy, float sfz)
{
   float sigsq, rcutsq;
   float rxi, ryi, rzi, fxi, fyi, fzi;
   float rxij, ryij, rzij, rijsq;
   float rij, sr2, sr6, vij, wij, fij, fxij, fyij, fzij;
   float potential, virial;
   int i, icell, j, jcell, nabor;
   int xi, yi, zi, ix, jx, kx, xcell, ycell, zcell;
   __shared__ float vArray[BLOCK_SIZE];
   __shared__ float pArray[BLOCK_SIZE];
   int p_start = BLOCK_SIZE;
   sigsq  = sigma*sigma;
   rcutsq = rcut*rcut;

   potential = 0.0f;
   virial    = 0.0f;
   
   int element = blockIdx.x * blockDim.x + threadIdx.x;
   if (element < natoms)
   {
  	 rxi = rx[element];
  	 ryi = ry[element];
  	 rzi = rz[element];
  	 fxi = 0.0f;
  	 fyi = 0.0f;
  	 fzi = 0.0f;
  	 xi = (int)((rxi+0.5f)/sfx) + 1;
  	 yi = (int)((ryi+0.5f)/sfy) + 1;
  	 zi = (int)((rzi+0.5f)/sfz) + 1;
           if(xi > mx) xi = mx;
           if(yi > my) yi = my;
           if(zi > mz) zi = mz;
  	   icell = xi + (mx+2)*(yi+zi*(my+2));
           for (ix=-1;ix<=1;ix++)
               for (jx=-1;jx<=1;jx++)
                   for (kx=-1;kx<=1;kx++){
  		     xcell = ix+xi;
  		     ycell = jx+yi;
  		     zcell = kx+zi;
                       jcell = xcell + (mx+2)*(ycell+(my+2)*zcell);
                       j = head[jcell];
                       while (j>=0) {
                           if (j!=element) {
                               rxij = rxi - rx[j];
                               ryij = ryi - ry[j];
                               rzij = rzi - rz[j];
                               rijsq = rxij*rxij + ryij*ryij + rzij*rzij;
                               if (rijsq < rcutsq) {
  			                           //START FORCE_IJ
                                    
                                    rij = (float) sqrt ((float)rijsq);
                                    sr2 = sigsq/rijsq;
                                    sr6 = sr2*sr2*sr2;
                                    vij = sr6*(sr6-1.0f) - vrcut - dvrc12*(rij-rcut);
                                    wij = sr6*(sr6-0.5f) + dvrcut*rij;
                                    fij = wij/rijsq;
                                    fxij = fij*rxij;
                                    fyij = fij*ryij;
                                    fzij = fij*rzij;
                                   //END FORCE_IJ
                                   wij *= 0.5f;
                                   vij *= 0.5f;
                                   potential += vij;
                                   virial    += wij;
                                   fxi       += fxij;
                                   fyi       += fyij;
                                   fzi       += fzij;
                               }
  			 }
                           j = list[j];
                        }
  	         }
           *(fx+element) = 48.0f*fxi;
           *(fy+element) = 48.0f*fyi;
           *(fz+element) = 48.0f*fzi;

            vArray[threadIdx.x] = virial;
            pArray[threadIdx.x] = potential;
            unsigned int stride;
            unsigned int t = threadIdx.x;
            __syncthreads();
            if (t == 0)
            {
             // __syncthreads();
              for(stride = 1; stride < blockDim.x; stride += 1)
              {
                vArray[t]+= vArray[stride];
                pArray[t]+= pArray[stride];
              }
            }
            //__syncthreads();
            if(t == 0)
            {
              virialArray[blockIdx.x] = vArray[0];
              potentialArray[blockIdx.x] = pArray[0];
            }


     }

}

	.text
	.file	"force.hip"
	.globl	_Z20__device_stub__forcePfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifff # -- Begin function _Z20__device_stub__forcePfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifff
	.type	_Z20__device_stub__forcePfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifff,@function
_Z20__device_stub__forcePfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifff: # @_Z20__device_stub__forcePfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifff
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$328, %rsp                      # imm = 0x148
	.cfi_def_cfa_offset 384
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	leaq	88(%rsp), %r10
	movq	%rdi, (%r10)
	leaq	80(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	72(%rsp), %r11
	movq	%rdx, (%r11)
	leaq	64(%rsp), %r14
	movq	%rcx, (%r14)
	leaq	56(%rsp), %r15
	movq	%r8, (%r15)
	leaq	48(%rsp), %r8
	movq	%r9, (%r8)
	leaq	28(%rsp), %rsi
	movss	%xmm0, (%rsi)
	leaq	24(%rsp), %r9
	movss	%xmm1, (%r9)
	leaq	20(%rsp), %r12
	movss	%xmm2, (%r12)
	leaq	16(%rsp), %r13
	movss	%xmm3, (%r13)
	leaq	12(%rsp), %rbp
	movss	%xmm4, (%rbp)
	leaq	8(%rsp), %rax
	movss	%xmm5, (%rax)
	leaq	4(%rsp), %rcx
	movss	%xmm6, (%rcx)
	movq	%rsp, %rdx
	movss	%xmm7, (%rdx)
	leaq	128(%rsp), %rbx
	movq	%r10, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%r11, 16(%rbx)
	movq	%r14, 24(%rbx)
	movq	%r15, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	384(%rsp), %rdi
	movq	%rdi, 48(%rbx)
	leaq	392(%rsp), %rdi
	movq	%rdi, 56(%rbx)
	leaq	400(%rsp), %rdi
	movq	%rdi, 64(%rbx)
	leaq	408(%rsp), %rdi
	movq	%rdi, 72(%rbx)
	movq	%rsi, 80(%rbx)
	movq	%r9, 88(%rbx)
	movq	%r12, 96(%rbx)
	movq	%r13, 104(%rbx)
	movq	%rbp, 112(%rbx)
	leaq	416(%rsp), %rsi
	movq	%rsi, 120(%rbx)
	leaq	424(%rsp), %rsi
	movq	%rsi, 128(%rbx)
	leaq	432(%rsp), %rsi
	movq	%rsi, 136(%rbx)
	leaq	440(%rsp), %rsi
	movq	%rsi, 144(%rbx)
	leaq	448(%rsp), %rsi
	movq	%rsi, 152(%rbx)
	leaq	456(%rsp), %rsi
	movq	%rsi, 160(%rbx)
	leaq	464(%rsp), %rsi
	movq	%rsi, 168(%rbx)
	movq	%rax, 176(%rbx)
	movq	%rcx, 184(%rbx)
	movq	%rdx, 192(%rbx)
	leaq	112(%rsp), %r14
	leaq	96(%rsp), %r15
	leaq	40(%rsp), %r12
	leaq	32(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z5forcePfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifff, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$344, %rsp                      # imm = 0x158
	.cfi_adjust_cfa_offset -344
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z20__device_stub__forcePfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifff, .Lfunc_end0-_Z20__device_stub__forcePfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifff
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z5forcePfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifff, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z5forcePfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifff,@object # @_Z5forcePfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifff
	.section	.rodata,"a",@progbits
	.globl	_Z5forcePfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifff
	.p2align	3, 0x0
_Z5forcePfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifff:
	.quad	_Z20__device_stub__forcePfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifff
	.size	_Z5forcePfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifff, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z5forcePfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifff"
	.size	.L__unnamed_1, 47

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z20__device_stub__forcePfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifff
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z5forcePfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifff
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z5forcePfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifff ; -- Begin function _Z5forcePfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifff
	.globl	_Z5forcePfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifff
	.p2align	8
	.type	_Z5forcePfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifff,@function
_Z5forcePfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifff: ; @_Z5forcePfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifff
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0xa4
	s_load_b128 s[24:27], s[0:1], 0x78
	s_mov_b32 s34, s15
	s_waitcnt lgkmcnt(0)
	s_and_b32 s33, s2, 0xffff
	s_mov_b32 s2, exec_lo
	v_mad_u64_u32 v[1:2], null, s34, s33, v[0:1]
	s_delay_alu instid0(VALU_DEP_1)
	v_cmpx_gt_i32_e64 s27, v1
	s_cbranch_execz .LBB0_21
; %bb.1:
	s_load_b256 s[4:11], s[0:1], 0x20
	v_ashrrev_i32_e32 v2, 31, v1
	s_clause 0x1
	s_load_b128 s[28:31], s[0:1], 0x8c
	s_load_b256 s[12:19], s[0:1], 0x40
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 2, v[1:2]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v4, vcc_lo, s4, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v3, vcc_lo
	v_add_co_u32 v6, vcc_lo, s6, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
	v_add_co_u32 v8, vcc_lo, s8, v2
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v3, vcc_lo
	global_load_b32 v10, v[4:5], off
	global_load_b32 v11, v[6:7], off
	global_load_b32 v12, v[8:9], off
	s_clause 0x1
	s_load_b32 s27, s[0:1], 0x60
	s_load_b128 s[20:23], s[0:1], 0x68
	s_waitcnt vmcnt(0)
	v_dual_add_f32 v4, 0.5, v10 :: v_dual_add_f32 v7, 0.5, v12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_div_scale_f32 v5, null, s28, s28, v4
	v_div_scale_f32 v9, null, s30, s30, v7
	v_div_scale_f32 v17, vcc_lo, v4, s28, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_rcp_f32_e32 v13, v5
	v_rcp_f32_e32 v16, v9
	v_div_scale_f32 v21, s3, v7, s30, v7
	s_waitcnt_depctr 0xfff
	v_fma_f32 v14, -v5, v13, 1.0
	v_add_f32_e32 v6, 0.5, v11
	v_fma_f32 v20, -v9, v16, 1.0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v13, v14, v13
	v_div_scale_f32 v8, null, s29, s29, v6
	v_div_scale_f32 v18, s2, v6, s29, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v16, v20, v16
	v_rcp_f32_e32 v15, v8
	s_waitcnt_depctr 0xfff
	v_fma_f32 v19, -v8, v15, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v15, v19, v15
	v_dual_mul_f32 v19, v17, v13 :: v_dual_mul_f32 v20, v18, v15
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_fma_f32 v14, -v5, v19, v17
	v_mul_f32_e32 v22, v21, v16
	v_fma_f32 v23, -v8, v20, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fmac_f32_e32 v19, v14, v13
	v_fma_f32 v24, -v9, v22, v21
	v_mov_b32_e32 v14, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_fmac_f32_e32 v20, v23, v15
	v_fma_f32 v5, -v5, v19, v17
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_fmac_f32 v22, v24, v16 :: v_dual_mov_b32 v17, 0
	v_div_fmas_f32 v13, v5, v13, v19
	v_mov_b32_e32 v5, 0
	v_fma_f32 v8, -v8, v20, v18
	s_mov_b32 vcc_lo, s2
	v_fma_f32 v9, -v9, v22, v21
	v_div_fixup_f32 v4, v13, s28, v4
	v_mul_f32_e64 v18, s16, s16
	v_div_fmas_f32 v8, v8, v15, v20
	s_mov_b32 vcc_lo, s3
	v_mov_b32_e32 v15, 0
	v_div_fmas_f32 v9, v9, v16, v22
	v_cvt_i32_f32_e32 v4, v4
	v_div_fixup_f32 v6, v8, s29, v6
	v_mov_b32_e32 v13, 0
	v_mul_f32_e64 v19, s17, s17
	v_div_fixup_f32 v7, v9, s30, v7
	v_add_nc_u32_e32 v8, 1, v4
	v_cvt_i32_f32_e32 v6, v6
	v_cmp_gt_i32_e32 vcc_lo, s24, v4
	s_add_i32 s16, s24, 2
	v_cvt_i32_f32_e32 v7, v7
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_dual_cndmask_b32 v20, s24, v8 :: v_dual_add_nc_u32 v9, 1, v6
	v_cmp_gt_i32_e32 vcc_lo, s25, v6
	v_add_nc_u32_e32 v16, 1, v7
	s_add_i32 s24, s25, 2
	s_delay_alu instid0(VALU_DEP_3)
	v_cndmask_b32_e32 v21, s25, v9, vcc_lo
	v_cmp_gt_i32_e32 vcc_lo, s26, v7
	s_mov_b32 s25, -1
	v_cndmask_b32_e32 v22, s26, v16, vcc_lo
	v_mov_b32_e32 v16, 0
.LBB0_2:                                ; %.preheader182
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_3 Depth 2
                                        ;       Child Loop BB0_4 Depth 3
                                        ;         Child Loop BB0_6 Depth 4
	v_add_nc_u32_e32 v6, s25, v20
	s_mov_b32 s26, -1
.LBB0_3:                                ; %.preheader181
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_4 Depth 3
                                        ;         Child Loop BB0_6 Depth 4
	s_delay_alu instid0(SALU_CYCLE_1)
	v_add_nc_u32_e32 v7, s26, v21
	s_mov_b32 s28, -1
.LBB0_4:                                ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_3 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_6 Depth 4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v4, s28, v22
	s_mov_b32 s29, exec_lo
	v_mad_u64_u32 v[8:9], null, v4, s24, v[7:8]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[23:24], null, v8, s16, v[6:7]
	v_ashrrev_i32_e32 v24, 31, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[8:9], 2, v[23:24]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v8, vcc_lo, s20, v8
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v9, vcc_lo, s21, v9, vcc_lo
	global_load_b32 v4, v[8:9], off
	s_waitcnt vmcnt(0)
	v_cmpx_lt_i32_e32 -1, v4
	s_cbranch_execz .LBB0_12
; %bb.5:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB0_4 Depth=3
	s_mov_b32 s30, 0
.LBB0_6:                                ; %.lr.ph
                                        ;   Parent Loop BB0_2 Depth=1
                                        ;     Parent Loop BB0_3 Depth=2
                                        ;       Parent Loop BB0_4 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	v_lshlrev_b64 v[8:9], 2, v[4:5]
	s_mov_b32 s31, exec_lo
	v_cmpx_ne_u32_e64 v4, v1
	s_cbranch_execz .LBB0_10
; %bb.7:                                ;   in Loop: Header=BB0_6 Depth=4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v23, vcc_lo, s4, v8
	v_add_co_ci_u32_e32 v24, vcc_lo, s5, v9, vcc_lo
	v_add_co_u32 v25, vcc_lo, s6, v8
	v_add_co_ci_u32_e32 v26, vcc_lo, s7, v9, vcc_lo
	s_mov_b32 s35, exec_lo
	global_load_b32 v27, v[23:24], off
	global_load_b32 v4, v[25:26], off
	v_add_co_u32 v23, vcc_lo, s8, v8
	v_add_co_ci_u32_e32 v24, vcc_lo, s9, v9, vcc_lo
	global_load_b32 v23, v[23:24], off
	s_waitcnt vmcnt(0)
	v_dual_sub_f32 v4, v11, v4 :: v_dual_sub_f32 v23, v12, v23
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_sub_f32 v24, v10, v27 :: v_dual_mul_f32 v25, v4, v4
	v_fmac_f32_e32 v25, v24, v24
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v25, v23, v23
	v_cmpx_lt_f32_e32 v25, v19
	s_cbranch_execz .LBB0_9
; %bb.8:                                ;   in Loop: Header=BB0_6 Depth=4
	v_div_scale_f32 v26, null, v25, v25, v18
	v_cmp_gt_f32_e64 s2, 0xf800000, v25
	v_div_scale_f32 v30, vcc_lo, v18, v25, v18
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v27, v26
	s_waitcnt_depctr 0xfff
	v_fma_f32 v29, -v26, v27, 1.0
	v_dual_mul_f32 v28, 0x4f800000, v25 :: v_dual_fmac_f32 v27, v29, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v28, v25, v28, s2
	v_sqrt_f32_e32 v29, v28
	s_waitcnt_depctr 0xfff
	v_dual_mul_f32 v31, v30, v27 :: v_dual_add_nc_u32 v34, 1, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v32, -v26, v31, v30
	v_fma_f32 v35, -v34, v29, v28
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v31, v32, v27
	v_fma_f32 v26, -v26, v31, v30
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_div_fmas_f32 v26, v26, v27, v31
	v_cmp_lt_f32_e32 vcc_lo, 0, v35
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v26, v26, v25, v18
	v_dual_mul_f32 v30, v26, v26 :: v_dual_add_nc_u32 v33, -1, v29
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v32, -v33, v29, v28
	v_fma_f32 v31, v26, v30, -0.5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s3, 0, v32
	v_cndmask_b32_e64 v29, v29, v33, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v27, v29, v34, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v28, 0x260
	v_mul_f32_e32 v29, 0x37800000, v27
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v27, v27, v29, s2
	v_cndmask_b32_e32 v27, v27, v28, vcc_lo
	v_mul_f32_e32 v29, v26, v30
	v_fma_f32 v26, v26, v30, -1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v28, v29, v31
	v_fmac_f32_e32 v28, s27, v27
	v_subrev_f32_e32 v27, s17, v27
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v26, v29, v26, -s18
	v_div_scale_f32 v31, null, v25, v25, v28
	v_div_scale_f32 v34, vcc_lo, v28, v25, v28
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_fma_f32 v26, -v27, s19, v26
	v_rcp_f32_e32 v32, v31
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_dual_fmac_f32 v16, 0.5, v28 :: v_dual_fmac_f32 v13, 0.5, v26
	s_waitcnt_depctr 0xfff
	v_fma_f32 v33, -v31, v32, 1.0
	v_fmac_f32_e32 v32, v33, v32
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v33, v34, v32
	v_fma_f32 v35, -v31, v33, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v33, v35, v32
	v_fma_f32 v30, -v31, v33, v34
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v29, v30, v32, v33
	v_div_fixup_f32 v25, v29, v25, v28
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v14, v24, v25
	v_fmac_f32_e32 v17, v4, v25
	v_fmac_f32_e32 v15, v23, v25
.LBB0_9:                                ; %Flow293
                                        ;   in Loop: Header=BB0_6 Depth=4
	s_or_b32 exec_lo, exec_lo, s35
.LBB0_10:                               ; %.lr.ph._crit_edge
                                        ;   in Loop: Header=BB0_6 Depth=4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s31
	v_add_co_u32 v8, vcc_lo, s22, v8
	v_add_co_ci_u32_e32 v9, vcc_lo, s23, v9, vcc_lo
	global_load_b32 v4, v[8:9], off
	s_waitcnt vmcnt(0)
	v_cmp_gt_i32_e32 vcc_lo, 0, v4
	s_or_b32 s30, vcc_lo, s30
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s30
	s_cbranch_execnz .LBB0_6
; %bb.11:                               ; %Flow294
                                        ;   in Loop: Header=BB0_4 Depth=3
	s_or_b32 exec_lo, exec_lo, s30
.LBB0_12:                               ; %Flow295
                                        ;   in Loop: Header=BB0_4 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	s_or_b32 exec_lo, exec_lo, s29
	s_add_i32 s28, s28, 1
	s_cmp_lg_u32 s28, 2
	s_cbranch_scc1 .LBB0_4
; %bb.13:                               ;   in Loop: Header=BB0_3 Depth=2
	s_add_i32 s26, s26, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s26, 2
	s_cbranch_scc1 .LBB0_3
; %bb.14:                               ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s25, s25, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s25, 2
	s_cbranch_scc1 .LBB0_2
; %bb.15:
	v_add_co_u32 v4, vcc_lo, s10, v2
	v_add_co_ci_u32_e32 v5, vcc_lo, s11, v3, vcc_lo
	v_add_co_u32 v6, vcc_lo, s12, v2
	v_add_co_ci_u32_e32 v7, vcc_lo, s13, v3, vcc_lo
	v_add_co_u32 v1, vcc_lo, s14, v2
	v_add_co_ci_u32_e32 v2, vcc_lo, s15, v3, vcc_lo
	v_dual_mul_f32 v8, 0x42400000, v14 :: v_dual_mul_f32 v9, 0x42400000, v17
	v_dual_mul_f32 v10, 0x42400000, v15 :: v_dual_lshlrev_b32 v3, 2, v0
	v_cmp_eq_u32_e32 vcc_lo, 0, v0
	global_store_b32 v[4:5], v8, off
	global_store_b32 v[6:7], v9, off
	global_store_b32 v[1:2], v10, off
	ds_store_2addr_stride64_b32 v3, v13, v16 offset1:8
	s_waitcnt lgkmcnt(0)
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
	s_and_b32 exec_lo, exec_lo, vcc_lo
	s_cbranch_execz .LBB0_21
; %bb.16:                               ; %.preheader
	v_mov_b32_e32 v0, 0
	s_cmp_lt_u32 s33, 2
	ds_load_2addr_stride64_b32 v[0:1], v0 offset1:8
	s_cbranch_scc1 .LBB0_20
; %bb.17:                               ; %.lr.ph213.preheader
	s_add_i32 s2, s33, -1
	s_mov_b32 s3, 4
.LBB0_18:                               ; %.lr.ph213
                                        ; =>This Inner Loop Header: Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	v_mov_b32_e32 v2, s3
	s_add_i32 s2, s2, -1
	s_add_i32 s3, s3, 4
	s_cmp_lg_u32 s2, 0
	ds_load_2addr_stride64_b32 v[2:3], v2 offset1:8
	s_waitcnt lgkmcnt(0)
	v_dual_add_f32 v1, v3, v1 :: v_dual_add_f32 v0, v2, v0
	s_cbranch_scc1 .LBB0_18
; %bb.19:                               ; %._crit_edge214
	v_mov_b32_e32 v2, 0
	ds_store_2addr_stride64_b32 v2, v0, v1 offset1:8
.LBB0_20:
	s_load_b128 s[0:3], s[0:1], 0x0
	s_mov_b32 s35, 0
	v_mov_b32_e32 v2, 0
	s_lshl_b64 s[4:5], s[34:35], 2
	s_waitcnt lgkmcnt(0)
	s_add_u32 s2, s2, s4
	s_addc_u32 s3, s3, s5
	s_add_u32 s0, s0, s4
	s_addc_u32 s1, s1, s5
	s_clause 0x1
	global_store_b32 v2, v1, s[0:1]
	global_store_b32 v2, v0, s[2:3]
.LBB0_21:                               ; %.critedge
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z5forcePfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifff
		.amdhsa_group_segment_fixed_size 4096
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 408
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 36
		.amdhsa_next_free_sgpr 36
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z5forcePfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifff, .Lfunc_end0-_Z5forcePfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifff
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1640
; NumSgprs: 38
; NumVgprs: 36
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 4096 bytes/workgroup (compile time only)
; SGPRBlocks: 4
; VGPRBlocks: 4
; NumSGPRsForWavesPerEU: 38
; NumVGPRsForWavesPerEU: 36
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         32
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         40
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         48
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         56
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         64
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         72
        .size:           8
        .value_kind:     global_buffer
      - .offset:         80
        .size:           4
        .value_kind:     by_value
      - .offset:         84
        .size:           4
        .value_kind:     by_value
      - .offset:         88
        .size:           4
        .value_kind:     by_value
      - .offset:         92
        .size:           4
        .value_kind:     by_value
      - .offset:         96
        .size:           4
        .value_kind:     by_value
      - .address_space:  global
        .offset:         104
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         112
        .size:           8
        .value_kind:     global_buffer
      - .offset:         120
        .size:           4
        .value_kind:     by_value
      - .offset:         124
        .size:           4
        .value_kind:     by_value
      - .offset:         128
        .size:           4
        .value_kind:     by_value
      - .offset:         132
        .size:           4
        .value_kind:     by_value
      - .offset:         136
        .size:           4
        .value_kind:     by_value
      - .offset:         140
        .size:           4
        .value_kind:     by_value
      - .offset:         144
        .size:           4
        .value_kind:     by_value
      - .offset:         148
        .size:           4
        .value_kind:     by_value
      - .offset:         152
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         156
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         160
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         164
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         166
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         168
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         170
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         172
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         174
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         192
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         200
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         208
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         216
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 4096
    .kernarg_segment_align: 8
    .kernarg_segment_size: 408
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z5forcePfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifff
    .private_segment_fixed_size: 0
    .sgpr_count:     38
    .sgpr_spill_count: 0
    .symbol:         _Z5forcePfS_S_S_S_S_S_S_S_S_fffffPiS0_iiiiifff.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     36
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
