#include <stdio.h>
#include <cuda_runtime.h>
#include <float.h>

__device__ void swap(float *a, float *b)
{
	float tmp = *a;
	*a = *b;
	*b = tmp;
}

extern __shared__ float BlockShMem[];
__global__ void CUDAJacobi(float *Aptr, float *Zptr, const unsigned int *Mptr, const int Nmat)
{
	const int N = sqrtf(Mptr[blockIdx.x]);
	float *A = Aptr + Mptr[blockIdx.x];
	float *Z = Zptr + Mptr[blockIdx.x];

	float *z = (float*)&BlockShMem[0];
	float *b = (float*)&BlockShMem[N];
	float *D = (float*)&BlockShMem[2 * N];

	// initialize Z as identity matrix
	//            D with A main diagonal
	//            b = D
	//            and z = 0
	for (int i = 0; i < N; ++i) {

		D[i] = A[i * N + i];
		b[i] = D[i];
		z[i] = 0.0;

		for (int j = 0; j < N; ++j) {
			Z[i * N + j] = (i == j)? 1.0 : 0.0;
		}
	}

	float g, h, t, theta, c, s, tau;
	const float EPSILON = FLT_EPSILON;
	int iteration = -1;
	const int MAX_ITERATIONS = 50;

	for (iteration = 0; iteration < MAX_ITERATIONS; ++iteration) {

		// convergence test: if we have a diagonal matrix (to machine precision) we're done
		float sm = 0.0;
		for (int i = 0; i < N - 1; ++i)
			for (int j = i + 1; j < N; ++j)
				sm += fabs(A[i * N + j]);

		if (sm == 0.0f)
			break;

		for (int ip = 0; ip < N - 1; ++ip) {
			for (int iq = ip + 1; iq < N; ++iq) {

				float Apq = A[ip * N + iq];
				g = 100.0f * fabsf(Apq);

				if (iteration > 4 && (g <= EPSILON * fabsf(D[ip])) && (g <= EPSILON * fabsf(D[iq]))) {

					A[ip * N + iq] = 0.0f;

				} else if (fabsf(Apq) > 0.0f) {

					h = D[iq] - D[ip];
					if (g <= EPSILON * fabsf(h)) {
						t = Apq / h;
					} else {
						theta = 0.5f * h / Apq;
						t = 1.0f / (fabsf(theta) + sqrtf(1.0f + theta * theta));
						if (theta < 0.0f)
							t = -t;
					}
					c = 1.0f / sqrtf(1 + t * t);
					s = t * c;
					tau = s / (1.0f + c);
					h = t * Apq;

					z[ip] -= h;
					D[ip] -= h;

					z[iq] += h;
					D[iq] += h;

					A[ip * N + iq] = 0.0f;

					// case of rotations 0 <= j < p
					for (int j = 0; j < ip; ++j) {
						float Aij = A[j * N + ip];
						float Akl = A[j * N + iq];
						A[j * N + ip] = Aij - s * (Akl + Aij * tau);
						A[j * N + iq] = Akl + s * (Aij - Akl * tau);
					}

					// case of rotations p <= j < q
					for (int j = ip + 1; j < iq; ++j) {
						float Aij = A[ip * N + j];
						float Akl = A[j * N + iq];
						A[ip * N + j] = Aij - s * (Akl + Aij * tau);
						A[j * N + iq] = Akl + s * (Aij - Akl * tau);
					}

					// case of rotations q <= j < n
					for (int j = iq + 1; j < N; ++j) {
						float Aij = A[ip * N + j];
						float Akl = A[iq * N + j];
						A[ip * N + j] = Aij - s * (Akl + Aij * tau);
						A[iq * N + j] = Akl + s * (Aij - Akl * tau);
					}

					// accumulate rotations for eigenvectors
					for (int j = 0; j < N; ++j) {
						float Aij = Z[j * N + ip];
						float Akl = Z[j * N + iq];
						Z[j * N + ip] = Aij - s * (Akl + Aij * tau);
						Z[j * N + iq] = Akl + s * (Aij - Akl * tau);
					}
				}
			}
		}

		for (int i = 0; i < N; ++i) {
			b[i] += z[i];
			D[i] = b[i];
			z[i] = 0.0;
		}
	}

	if (iteration < MAX_ITERATIONS) {

		// converged, now put eigenvalues in ascending order
		int min_idx;
		for (int i = 0; i < N; ++i) {
			min_idx = i;
			for (int j = i + 1; j < N; ++j)
				if (D[j] < D[min_idx])
					min_idx = j;

			if (i != min_idx)
				swap(&D[i], &D[min_idx]);
		}

	} else {

		for (int i = 0; i < N; ++i)
			D[i] = -1.0f;

	}
}


extern "C"
void eigenpairs_gpu(float *gpuA, float *gpuZ, const unsigned MaxMatrixSize, const unsigned *gpuMatrixSize, const int MatrixCount)
{
	dim3 gridDim(MatrixCount, 1);
	dim3 blockDim(1, 1);
	int shMemSize = 3 * MaxMatrixSize * sizeof(float);

	CUDAJacobi<<<gridDim, blockDim, shMemSize>>>(gpuA, gpuZ, gpuMatrixSize, MatrixCount);
}

	.file	"tmpxft_003275a9_00000000-6_eigensolver.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2031:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2031:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z4swapPfS_
	.type	_Z4swapPfS_, @function
_Z4swapPfS_:
.LFB2027:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2027:
	.size	_Z4swapPfS_, .-_Z4swapPfS_
	.globl	_Z36__device_stub__Z10CUDAJacobiPfS_PKjiPfS_PKji
	.type	_Z36__device_stub__Z10CUDAJacobiPfS_PKjiPfS_PKji, @function
_Z36__device_stub__Z10CUDAJacobiPfS_PKjiPfS_PKji:
.LFB2053:
	.cfi_startproc
	endbr64
	subq	$152, %rsp
	.cfi_def_cfa_offset 160
	movq	%rdi, 24(%rsp)
	leaq	56(%rsp), %rdi
	movq	%rsi, 16(%rsp)
	leaq	68(%rsp), %rsi
	movq	%rdx, 8(%rsp)
	leaq	40(%rsp), %rdx
	movl	%ecx, 4(%rsp)
	leaq	48(%rsp), %rcx
	movq	%fs:40, %rax
	movq	%rax, 136(%rsp)
	xorl	%eax, %eax
	leaq	24(%rsp), %rax
	movl	$1, 64(%rsp)
	movq	%rax, 104(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 112(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 128(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 56(%rsp)
	movq	%rax, 68(%rsp)
	movl	$1, 76(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	48(%rsp)
	.cfi_def_cfa_offset 168
	leaq	_Z10CUDAJacobiPfS_PKji(%rip), %rdi
	pushq	48(%rsp)
	.cfi_def_cfa_offset 176
	movq	84(%rsp), %rcx
	movl	92(%rsp), %r8d
	movq	72(%rsp), %rsi
	movl	80(%rsp), %edx
	leaq	120(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 168
	popq	%rdx
	.cfi_def_cfa_offset 160
.L4:
	movq	136(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$152, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2053:
	.size	_Z36__device_stub__Z10CUDAJacobiPfS_PKjiPfS_PKji, .-_Z36__device_stub__Z10CUDAJacobiPfS_PKjiPfS_PKji
	.globl	_Z10CUDAJacobiPfS_PKji
	.type	_Z10CUDAJacobiPfS_PKji, @function
_Z10CUDAJacobiPfS_PKji:
.LFB2054:
	.cfi_startproc
	endbr64
	jmp	_Z36__device_stub__Z10CUDAJacobiPfS_PKjiPfS_PKji
	.cfi_endproc
.LFE2054:
	.size	_Z10CUDAJacobiPfS_PKji, .-_Z10CUDAJacobiPfS_PKji
	.globl	eigenpairs_gpu
	.type	eigenpairs_gpu, @function
eigenpairs_gpu:
.LFB2028:
	.cfi_startproc
	endbr64
	pushq	%r13
	.cfi_def_cfa_offset 16
	.cfi_offset 13, -16
	imull	$12, %edx, %edx
	movq	%rcx, %r13
	xorl	%r9d, %r9d
	pushq	%r12
	.cfi_def_cfa_offset 24
	.cfi_offset 12, -24
	movq	%rsi, %r12
	movl	$1, %ecx
	movabsq	$4294967297, %rax
	pushq	%rbp
	.cfi_def_cfa_offset 32
	.cfi_offset 6, -32
	movq	%rdi, %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 40
	.cfi_offset 3, -40
	movl	%r8d, %ebx
	subq	$40, %rsp
	.cfi_def_cfa_offset 80
	movl	%r8d, 8(%rsp)
	movslq	%edx, %r8
	movq	%rax, %rdx
	movq	%rax, 12(%rsp)
	movq	8(%rsp), %rdi
	movl	16(%rsp), %esi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L10
	addq	$40, %rsp
	.cfi_remember_state
	.cfi_def_cfa_offset 40
	movl	%ebx, %ecx
	movq	%r13, %rdx
	movq	%r12, %rsi
	popq	%rbx
	.cfi_def_cfa_offset 32
	movq	%rbp, %rdi
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	jmp	_Z36__device_stub__Z10CUDAJacobiPfS_PKjiPfS_PKji
.L10:
	.cfi_restore_state
	addq	$40, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%rbp
	.cfi_def_cfa_offset 24
	popq	%r12
	.cfi_def_cfa_offset 16
	popq	%r13
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2028:
	.size	eigenpairs_gpu, .-eigenpairs_gpu
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z10CUDAJacobiPfS_PKji"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2056:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z10CUDAJacobiPfS_PKji(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2056:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <stdio.h>
#include <hip/hip_runtime.h>
#include <float.h>

__device__ void swap(float *a, float *b)
{
	float tmp = *a;
	*a = *b;
	*b = tmp;
}

extern __shared__ float BlockShMem[];
__global__ void CUDAJacobi(float *Aptr, float *Zptr, const unsigned int *Mptr, const int Nmat)
{
	const int N = sqrtf(Mptr[blockIdx.x]);
	float *A = Aptr + Mptr[blockIdx.x];
	float *Z = Zptr + Mptr[blockIdx.x];

	float *z = (float*)&BlockShMem[0];
	float *b = (float*)&BlockShMem[N];
	float *D = (float*)&BlockShMem[2 * N];

	// initialize Z as identity matrix
	//            D with A main diagonal
	//            b = D
	//            and z = 0
	for (int i = 0; i < N; ++i) {

		D[i] = A[i * N + i];
		b[i] = D[i];
		z[i] = 0.0;

		for (int j = 0; j < N; ++j) {
			Z[i * N + j] = (i == j)? 1.0 : 0.0;
		}
	}

	float g, h, t, theta, c, s, tau;
	const float EPSILON = FLT_EPSILON;
	int iteration = -1;
	const int MAX_ITERATIONS = 50;

	for (iteration = 0; iteration < MAX_ITERATIONS; ++iteration) {

		// convergence test: if we have a diagonal matrix (to machine precision) we're done
		float sm = 0.0;
		for (int i = 0; i < N - 1; ++i)
			for (int j = i + 1; j < N; ++j)
				sm += fabs(A[i * N + j]);

		if (sm == 0.0f)
			break;

		for (int ip = 0; ip < N - 1; ++ip) {
			for (int iq = ip + 1; iq < N; ++iq) {

				float Apq = A[ip * N + iq];
				g = 100.0f * fabsf(Apq);

				if (iteration > 4 && (g <= EPSILON * fabsf(D[ip])) && (g <= EPSILON * fabsf(D[iq]))) {

					A[ip * N + iq] = 0.0f;

				} else if (fabsf(Apq) > 0.0f) {

					h = D[iq] - D[ip];
					if (g <= EPSILON * fabsf(h)) {
						t = Apq / h;
					} else {
						theta = 0.5f * h / Apq;
						t = 1.0f / (fabsf(theta) + sqrtf(1.0f + theta * theta));
						if (theta < 0.0f)
							t = -t;
					}
					c = 1.0f / sqrtf(1 + t * t);
					s = t * c;
					tau = s / (1.0f + c);
					h = t * Apq;

					z[ip] -= h;
					D[ip] -= h;

					z[iq] += h;
					D[iq] += h;

					A[ip * N + iq] = 0.0f;

					// case of rotations 0 <= j < p
					for (int j = 0; j < ip; ++j) {
						float Aij = A[j * N + ip];
						float Akl = A[j * N + iq];
						A[j * N + ip] = Aij - s * (Akl + Aij * tau);
						A[j * N + iq] = Akl + s * (Aij - Akl * tau);
					}

					// case of rotations p <= j < q
					for (int j = ip + 1; j < iq; ++j) {
						float Aij = A[ip * N + j];
						float Akl = A[j * N + iq];
						A[ip * N + j] = Aij - s * (Akl + Aij * tau);
						A[j * N + iq] = Akl + s * (Aij - Akl * tau);
					}

					// case of rotations q <= j < n
					for (int j = iq + 1; j < N; ++j) {
						float Aij = A[ip * N + j];
						float Akl = A[iq * N + j];
						A[ip * N + j] = Aij - s * (Akl + Aij * tau);
						A[iq * N + j] = Akl + s * (Aij - Akl * tau);
					}

					// accumulate rotations for eigenvectors
					for (int j = 0; j < N; ++j) {
						float Aij = Z[j * N + ip];
						float Akl = Z[j * N + iq];
						Z[j * N + ip] = Aij - s * (Akl + Aij * tau);
						Z[j * N + iq] = Akl + s * (Aij - Akl * tau);
					}
				}
			}
		}

		for (int i = 0; i < N; ++i) {
			b[i] += z[i];
			D[i] = b[i];
			z[i] = 0.0;
		}
	}

	if (iteration < MAX_ITERATIONS) {

		// converged, now put eigenvalues in ascending order
		int min_idx;
		for (int i = 0; i < N; ++i) {
			min_idx = i;
			for (int j = i + 1; j < N; ++j)
				if (D[j] < D[min_idx])
					min_idx = j;

			if (i != min_idx)
				swap(&D[i], &D[min_idx]);
		}

	} else {

		for (int i = 0; i < N; ++i)
			D[i] = -1.0f;

	}
}


extern "C"
void eigenpairs_gpu(float *gpuA, float *gpuZ, const unsigned MaxMatrixSize, const unsigned *gpuMatrixSize, const int MatrixCount)
{
	dim3 gridDim(MatrixCount, 1);
	dim3 blockDim(1, 1);
	int shMemSize = 3 * MaxMatrixSize * sizeof(float);

	CUDAJacobi<<<gridDim, blockDim, shMemSize>>>(gpuA, gpuZ, gpuMatrixSize, MatrixCount);
}

	.text
	.file	"eigensolver.hip"
	.globl	_Z25__device_stub__CUDAJacobiPfS_PKji # -- Begin function _Z25__device_stub__CUDAJacobiPfS_PKji
	.type	_Z25__device_stub__CUDAJacobiPfS_PKji,@function
_Z25__device_stub__CUDAJacobiPfS_PKji:  # @_Z25__device_stub__CUDAJacobiPfS_PKji
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$112, %rsp
	.cfi_def_cfa_offset 160
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	40(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	32(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	24(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	4(%rsp), %rdx
	movl	%ecx, (%rdx)
	leaq	80(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	leaq	64(%rsp), %r14
	leaq	48(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z10CUDAJacobiPfS_PKji, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$128, %rsp
	.cfi_adjust_cfa_offset -128
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z25__device_stub__CUDAJacobiPfS_PKji, .Lfunc_end0-_Z25__device_stub__CUDAJacobiPfS_PKji
	.cfi_endproc
                                        # -- End function
	.globl	eigenpairs_gpu                  # -- Begin function eigenpairs_gpu
	.type	eigenpairs_gpu,@function
eigenpairs_gpu:                         # @eigenpairs_gpu
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r12
	.cfi_def_cfa_offset 32
	pushq	%rbx
	.cfi_def_cfa_offset 40
	pushq	%rax
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -40
	.cfi_offset %r12, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	movl	%r8d, %ebx
	movq	%rcx, %r14
                                        # kill: def $edx killed $edx def $rdx
	movq	%rsi, %r15
	movq	%rdi, %r12
	movl	%r8d, %edi
	btsq	$32, %rdi
	shll	$2, %edx
	leal	(%rdx,%rdx,2), %eax
	movslq	%eax, %r8
	movabsq	$4294967296, %rdx               # imm = 0x100000000
	orq	$1, %rdx
	movl	$1, %esi
	movl	$1, %ecx
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	je	.LBB1_2
# %bb.1:
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.LBB1_2:
	.cfi_def_cfa_offset 48
	movq	%r12, %rdi
	movq	%r15, %rsi
	movq	%r14, %rdx
	movl	%ebx, %ecx
	addq	$8, %rsp
	.cfi_def_cfa_offset 40
	popq	%rbx
	.cfi_def_cfa_offset 32
	popq	%r12
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	jmp	_Z25__device_stub__CUDAJacobiPfS_PKji # TAILCALL
.Lfunc_end1:
	.size	eigenpairs_gpu, .Lfunc_end1-eigenpairs_gpu
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z10CUDAJacobiPfS_PKji, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z10CUDAJacobiPfS_PKji,@object  # @_Z10CUDAJacobiPfS_PKji
	.section	.rodata,"a",@progbits
	.globl	_Z10CUDAJacobiPfS_PKji
	.p2align	3, 0x0
_Z10CUDAJacobiPfS_PKji:
	.quad	_Z25__device_stub__CUDAJacobiPfS_PKji
	.size	_Z10CUDAJacobiPfS_PKji, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z10CUDAJacobiPfS_PKji"
	.size	.L__unnamed_1, 23

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z25__device_stub__CUDAJacobiPfS_PKji
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z10CUDAJacobiPfS_PKji
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z10CUDAJacobiPfS_PKji  ; -- Begin function _Z10CUDAJacobiPfS_PKji
	.globl	_Z10CUDAJacobiPfS_PKji
	.p2align	8
	.type	_Z10CUDAJacobiPfS_PKji,@function
_Z10CUDAJacobiPfS_PKji:                 ; @_Z10CUDAJacobiPfS_PKji
; %bb.0:
	s_load_b64 s[2:3], s[0:1], 0x10
	s_mov_b32 s8, s15
	s_mov_b32 s9, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	s_lshl_b64 s[4:5], s[8:9], 2
	s_waitcnt lgkmcnt(0)
	s_add_u32 s2, s2, s4
	s_addc_u32 s3, s3, s5
	s_load_b128 s[4:7], s[0:1], 0x0
	s_load_b32 s8, s[2:3], 0x0
	s_waitcnt lgkmcnt(0)
	v_cvt_f32_u32_e32 v0, s8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v1, 0x4f800000, v0
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v0
	v_cndmask_b32_e32 v0, v0, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v1, v0
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v2, -1, v1
	v_add_nc_u32_e32 v3, 1, v1
	v_fma_f32 v4, -v2, v1, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v5, -v3, v1, v0
	v_cmp_ge_f32_e64 s2, 0, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v1, v1, v2, s2
	v_cmp_lt_f32_e64 s2, 0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cndmask_b32_e64 v1, v1, v3, s2
	s_lshl_b64 s[2:3], s[8:9], 2
	s_add_u32 s19, s4, s2
	s_addc_u32 s20, s5, s3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v2, 0x37800000, v1
	v_cndmask_b32_e32 v1, v1, v2, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v0, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v0, v1, v0, vcc_lo
	v_cvt_i32_f32_e32 v3, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_lshlrev_b32_e32 v1, 2, v3
	v_cmp_gt_i32_e32 vcc_lo, 1, v3
	v_readfirstlane_b32 s18, v3
	v_cmp_lt_i32_e64 s0, 0, v3
	v_add_nc_u32_e32 v2, 0, v1
	s_delay_alu instid0(VALU_DEP_1)
	v_add_nc_u32_e32 v0, v2, v1
	s_cbranch_vccnz .LBB0_5
; %bb.1:                                ; %.lr.ph307.preheader
	v_mov_b32_e32 v3, 0
	s_mov_b32 s11, 0
	s_add_u32 s1, s6, s2
	s_addc_u32 s8, s7, s3
	s_mov_b32 s10, s11
	s_mov_b32 s14, s11
.LBB0_2:                                ; %.lr.ph307
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_3 Depth 2
	s_lshl_b64 s[12:13], s[10:11], 2
	s_mul_i32 s15, s14, s18
	s_add_u32 s12, s1, s12
	s_addc_u32 s13, s8, s13
	s_add_i32 s16, s15, s14
	s_mov_b32 s17, s11
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[16:17], s[16:17], 2
	s_add_u32 s16, s19, s16
	s_addc_u32 s17, s20, s17
	s_lshl_b32 s15, s14, 2
	global_load_b32 v4, v3, s[16:17]
	v_add_nc_u32_e32 v5, s15, v0
	s_add_i32 s16, s15, 0
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v7, s16 :: v_dual_add_nc_u32 v6, s15, v2
	s_mov_b32 s15, 0
	s_waitcnt vmcnt(0)
	ds_store_b32 v5, v4
	ds_store_b32 v6, v4
	ds_store_b32 v7, v3
.LBB0_3:                                ; %.lr.ph
                                        ;   Parent Loop BB0_2 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_cmp_eq_u32 s14, s15
	s_cselect_b32 s16, -1, 0
	s_add_i32 s15, s15, 1
	v_cndmask_b32_e64 v4, 0, 1.0, s16
	global_store_b32 v3, v4, s[12:13]
	s_add_u32 s12, s12, 4
	s_addc_u32 s13, s13, 0
	s_cmp_eq_u32 s18, s15
	s_cbranch_scc0 .LBB0_3
; %bb.4:                                ; %._crit_edge
                                        ;   in Loop: Header=BB0_2 Depth=1
	s_add_i32 s14, s14, 1
	s_add_i32 s10, s10, s18
	s_cmp_eq_u32 s14, s18
	s_cbranch_scc0 .LBB0_2
.LBB0_5:                                ; %.preheader303
	s_add_u32 s22, s6, s2
	s_addc_u32 s23, s7, s3
	s_add_i32 s24, s18, -1
	s_cmp_gt_i32 s18, 1
	v_mov_b32_e32 v3, 0
	s_cselect_b32 s1, -1, 0
	s_add_u32 s25, s4, s2
	v_cndmask_b32_e64 v2, 0, 1, s1
	s_addc_u32 s26, s5, s3
	s_add_i32 s27, s18, 1
	s_add_i32 s28, s18, 2
	s_lshl_b32 s21, s18, 3
	v_cmp_ne_u32_e64 s1, 1, v2
	v_cndmask_b32_e64 v2, 0, 1, s0
	s_mov_b32 s29, 0
.LBB0_6:                                ; %.preheader302
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_8 Depth 2
                                        ;       Child Loop BB0_9 Depth 3
                                        ;     Child Loop BB0_14 Depth 2
                                        ;       Child Loop BB0_15 Depth 3
                                        ;         Child Loop BB0_30 Depth 4
                                        ;         Child Loop BB0_32 Depth 4
                                        ;         Child Loop BB0_35 Depth 4
                                        ;         Child Loop BB0_38 Depth 4
                                        ;     Child Loop BB0_43 Depth 2
	v_mov_b32_e32 v4, 0
	s_delay_alu instid0(VALU_DEP_3)
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_11
; %bb.7:                                ; %.lr.ph314.preheader
                                        ;   in Loop: Header=BB0_6 Depth=1
	v_mov_b32_e32 v4, 0
	s_mov_b32 s4, 0
	s_mov_b32 s8, 1
.LBB0_8:                                ; %.lr.ph314
                                        ;   Parent Loop BB0_6 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_9 Depth 3
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[2:3], s[8:9], 2
	s_add_u32 s2, s25, s2
	s_addc_u32 s3, s26, s3
	s_add_i32 s4, s4, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s5, s4
.LBB0_9:                                ;   Parent Loop BB0_6 Depth=1
                                        ;     Parent Loop BB0_8 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	global_load_b32 v5, v3, s[2:3]
	s_add_i32 s5, s5, 1
	s_add_u32 s2, s2, 4
	s_addc_u32 s3, s3, 0
	s_cmp_ge_i32 s5, s18
	s_waitcnt vmcnt(0)
	v_add_f32_e64 v4, v4, |v5|
	s_cbranch_scc0 .LBB0_9
; %bb.10:                               ; %.loopexit299
                                        ;   in Loop: Header=BB0_8 Depth=2
	s_add_i32 s8, s8, s27
	s_cmp_lg_u32 s4, s24
	s_cbranch_scc1 .LBB0_8
.LBB0_11:                               ; %._crit_edge315
                                        ;   in Loop: Header=BB0_6 Depth=1
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_eq_f32_e32 vcc_lo, 0, v4
	s_cbranch_vccnz .LBB0_45
; %bb.12:                               ; %.preheader301
                                        ;   in Loop: Header=BB0_6 Depth=1
	s_and_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_41
; %bb.13:                               ; %.lr.ph333
                                        ;   in Loop: Header=BB0_6 Depth=1
	s_cmp_gt_u32 s29, 4
	s_mov_b32 s34, 0
	s_cselect_b32 s2, -1, 0
	s_cmp_lt_u32 s29, 5
	v_cndmask_b32_e64 v4, 0, 1, s2
	s_cselect_b32 s30, -1, 0
	s_mov_b32 s6, 1
	s_mov_b32 s31, 2
	s_mov_b32 s33, s28
	v_cmp_ne_u32_e64 s2, 1, v4
	s_mov_b32 s35, s27
.LBB0_14:                               ; %.lr.ph331
                                        ;   Parent Loop BB0_6 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_15 Depth 3
                                        ;         Child Loop BB0_30 Depth 4
                                        ;         Child Loop BB0_32 Depth 4
                                        ;         Child Loop BB0_35 Depth 4
                                        ;         Child Loop BB0_38 Depth 4
	s_mov_b32 s7, s9
	s_mov_b32 s12, s33
	s_lshl_b64 s[4:5], s[6:7], 2
	s_mov_b32 s7, s34
	s_add_u32 s10, s25, s4
	s_addc_u32 s11, s26, s5
	s_lshl_b32 s3, s34, 2
	s_add_i32 s34, s34, 1
	s_add_i32 s36, s3, 0
	s_cmp_lg_u32 s7, 0
	v_add_nc_u32_e32 v4, s3, v0
	s_cselect_b32 s4, -1, 0
	s_mul_i32 s37, s7, s18
	v_cndmask_b32_e64 v5, 0, 1, s4
	s_mov_b32 s14, s31
	s_mov_b32 s38, s35
	s_mov_b32 s39, s34
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_ne_u32_e64 s3, 1, v5
.LBB0_15:                               ;   Parent Loop BB0_6 Depth=1
                                        ;     Parent Loop BB0_14 Depth=2
                                        ; =>    This Loop Header: Depth=3
                                        ;         Child Loop BB0_30 Depth 4
                                        ;         Child Loop BB0_32 Depth 4
                                        ;         Child Loop BB0_35 Depth 4
                                        ;         Child Loop BB0_38 Depth 4
	s_add_i32 s8, s39, s37
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[4:5], s[8:9], 2
	s_add_u32 s16, s19, s4
	s_addc_u32 s17, s20, s5
	s_and_b32 vcc_lo, exec_lo, s2
	global_load_b32 v5, v3, s[16:17]
	s_mov_b32 s4, s30
	s_waitcnt vmcnt(0)
	v_mul_f32_e64 v8, 0x42c80000, |v5|
	s_cbranch_vccnz .LBB0_20
; %bb.16:                               ;   in Loop: Header=BB0_15 Depth=3
	ds_load_b32 v6, v4
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e64 v6, 0x34000000, |v6|
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_le_f32_e32 vcc_lo, v8, v6
	s_cbranch_vccz .LBB0_19
; %bb.17:                               ;   in Loop: Header=BB0_15 Depth=3
	s_lshl_b32 s4, s39, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v6, s4, v0
	s_mov_b32 s4, -1
	ds_load_b32 v6, v6
	s_waitcnt lgkmcnt(0)
	v_mul_f32_e64 v6, 0x34000000, |v6|
	v_cmp_le_f32_e32 vcc_lo, v8, v6
	s_cbranch_vccz .LBB0_20
; %bb.18:                               ;   in Loop: Header=BB0_15 Depth=3
	s_mov_b32 s4, 0
	global_store_b32 v3, v3, s[16:17]
	s_branch .LBB0_20
.LBB0_19:                               ;   in Loop: Header=BB0_15 Depth=3
	v_cmp_nle_f32_e64 s4, v8, v6
.LBB0_20:                               ; %Flow448
                                        ;   in Loop: Header=BB0_15 Depth=3
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccz .LBB0_39
; %bb.21:                               ;   in Loop: Header=BB0_15 Depth=3
	v_cmp_nlg_f32_e32 vcc_lo, 0, v5
	s_cbranch_vccnz .LBB0_39
; %bb.22:                               ;   in Loop: Header=BB0_15 Depth=3
	s_lshl_b32 s5, s39, 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v7, s5, v0
	ds_load_b32 v9, v7
	ds_load_b32 v6, v4
	s_waitcnt lgkmcnt(0)
	v_sub_f32_e32 v9, v9, v6
	v_mul_f32_e64 v10, 0x34000000, |v9|
	s_delay_alu instid0(VALU_DEP_1)
	v_cmp_nle_f32_e32 vcc_lo, v8, v10
	s_cbranch_vccnz .LBB0_24
; %bb.23:                               ;   in Loop: Header=BB0_15 Depth=3
	v_div_scale_f32 v8, null, v9, v9, v5
	s_mov_b32 s4, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v10, v8
	s_waitcnt_depctr 0xfff
	v_fma_f32 v11, -v8, v10, 1.0
	v_fmac_f32_e32 v10, v11, v10
	v_div_scale_f32 v11, vcc_lo, v5, v9, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v12, v11, v10
	v_fma_f32 v13, -v8, v12, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v12, v13, v10
	v_fma_f32 v8, -v8, v12, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v8, v8, v10, v12
	v_div_fixup_f32 v8, v8, v9, v5
	s_branch .LBB0_25
.LBB0_24:                               ;   in Loop: Header=BB0_15 Depth=3
	s_mov_b32 s4, -1
                                        ; implicit-def: $vgpr8
.LBB0_25:                               ; %Flow444
                                        ;   in Loop: Header=BB0_15 Depth=3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s4
	s_cbranch_vccnz .LBB0_28
; %bb.26:                               ;   in Loop: Header=BB0_15 Depth=3
	v_mul_f32_e32 v8, 0.5, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_scale_f32 v9, null, v5, v5, v8
	v_div_scale_f32 v12, vcc_lo, v8, v5, v8
	v_rcp_f32_e32 v10, v9
	s_waitcnt_depctr 0xfff
	v_fma_f32 v11, -v9, v10, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v10, v11, v10
	v_mul_f32_e32 v11, v12, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v13, -v9, v11, v12
	v_fmac_f32_e32 v11, v13, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v9, -v9, v11, v12
	v_div_fmas_f32 v9, v9, v10, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fixup_f32 v8, v9, v5, v8
	v_fma_f32 v9, v8, v8, 1.0
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v10, 0x4f800000, v9
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v9
	v_cndmask_b32_e32 v9, v9, v10, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
	v_sqrt_f32_e32 v10, v9
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v11, -1, v10
	v_add_nc_u32_e32 v12, 1, v10
	v_fma_f32 v13, -v11, v10, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v14, -v12, v10, v9
	v_cmp_ge_f32_e64 s4, 0, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v10, v10, v11, s4
	v_cmp_lt_f32_e64 s4, 0, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v10, v10, v12, s4
	v_mul_f32_e32 v11, 0x37800000, v10
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v10, v10, v11, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v9, 0x260
	v_cndmask_b32_e32 v9, v10, v9, vcc_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f32_e64 v9, |v8|, v9
	v_div_scale_f32 v10, null, v9, v9, 1.0
	v_div_scale_f32 v13, vcc_lo, 1.0, v9, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v11, v10
	s_waitcnt_depctr 0xfff
	v_fma_f32 v12, -v10, v11, 1.0
	v_fmac_f32_e32 v11, v12, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v12, v13, v11
	v_fma_f32 v14, -v10, v12, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v12, v14, v11
	v_fma_f32 v10, -v10, v12, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fmas_f32 v10, v10, v11, v12
	v_cmp_ngt_f32_e32 vcc_lo, 0, v8
	v_div_fixup_f32 v8, v10, v9, 1.0
	s_cbranch_vccnz .LBB0_28
; %bb.27:                               ;   in Loop: Header=BB0_15 Depth=3
	s_delay_alu instid0(VALU_DEP_1)
	v_xor_b32_e32 v8, 0x80000000, v8
.LBB0_28:                               ;   in Loop: Header=BB0_15 Depth=3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f32 v9, v8, v8, 1.0
	v_dual_mov_b32 v15, s36 :: v_dual_mul_f32 v10, 0x4f800000, v9
	v_cmp_gt_f32_e32 vcc_lo, 0xf800000, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v9, v9, v10, vcc_lo
	v_sqrt_f32_e32 v10, v9
	s_waitcnt_depctr 0xfff
	v_add_nc_u32_e32 v11, -1, v10
	v_add_nc_u32_e32 v12, 1, v10
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v13, -v11, v10, v9
	v_fma_f32 v14, -v12, v10, v9
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_ge_f32_e64 s4, 0, v13
	v_cndmask_b32_e64 v10, v10, v11, s4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_lt_f32_e64 s4, 0, v14
	v_cndmask_b32_e64 v10, v10, v12, s4
	s_add_i32 s4, s5, 0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v11, 0x37800000, v10
	v_cndmask_b32_e32 v10, v10, v11, vcc_lo
	v_cmp_class_f32_e64 vcc_lo, v9, 0x260
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v9, v10, v9, vcc_lo
	v_div_scale_f32 v10, null, v9, v9, 1.0
	v_div_scale_f32 v13, vcc_lo, 1.0, v9, 1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v11, v10
	s_waitcnt_depctr 0xfff
	v_fma_f32 v12, -v10, v11, 1.0
	v_fmac_f32_e32 v11, v12, v11
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f32_e32 v12, v13, v11
	v_fma_f32 v14, -v10, v12, v13
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_fmac_f32_e32 v12, v14, v11
	ds_load_b32 v14, v15
	v_fma_f32 v10, -v10, v12, v13
	v_div_fmas_f32 v10, v10, v11, v12
	v_mov_b32_e32 v12, s4
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_div_fixup_f32 v9, v10, v9, 1.0
	v_fma_f32 v10, -v5, v8, v6
	v_mul_f32_e32 v6, v8, v9
	v_add_f32_e32 v9, 1.0, v9
	s_waitcnt lgkmcnt(0)
	v_fma_f32 v11, -v5, v8, v14
	ds_store_b32 v15, v11
	ds_store_b32 v4, v10
	v_div_scale_f32 v13, null, v9, v9, v6
	ds_load_b32 v10, v12
	global_store_b32 v3, v3, s[16:17]
	v_rcp_f32_e32 v11, v13
	s_waitcnt_depctr 0xfff
	v_fma_f32 v14, -v13, v11, 1.0
	s_delay_alu instid0(VALU_DEP_1)
	v_fmac_f32_e32 v11, v14, v11
	v_div_scale_f32 v14, vcc_lo, v6, v9, v6
	s_waitcnt lgkmcnt(0)
	v_fmac_f32_e32 v10, v5, v8
	ds_store_b32 v12, v10
	ds_load_b32 v10, v7
	s_waitcnt lgkmcnt(0)
	v_dual_mul_f32 v15, v14, v11 :: v_dual_fmac_f32 v10, v5, v8
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_fma_f32 v12, -v13, v15, v14
	ds_store_b32 v7, v10
	v_fmac_f32_e32 v15, v12, v11
	v_fma_f32 v12, -v13, v15, v14
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_div_fmas_f32 v11, v12, v11, v15
	s_and_b32 vcc_lo, exec_lo, s3
	v_div_fixup_f32 v5, v11, v9, v6
	s_cbranch_vccnz .LBB0_31
; %bb.29:                               ; %.lr.ph320.preheader
                                        ;   in Loop: Header=BB0_15 Depth=3
	s_mov_b32 s4, 0
	s_mov_b32 s5, 0
.LBB0_30:                               ; %.lr.ph320
                                        ;   Parent Loop BB0_6 Depth=1
                                        ;     Parent Loop BB0_14 Depth=2
                                        ;       Parent Loop BB0_15 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_add_i32 s8, s7, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[16:17], s[8:9], 2
	s_add_u32 s16, s19, s16
	s_addc_u32 s17, s20, s17
	s_add_i32 s8, s39, s4
	global_load_b32 v7, v3, s[16:17]
	s_lshl_b64 s[40:41], s[8:9], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s40, s19, s40
	s_addc_u32 s41, s20, s41
	s_add_i32 s5, s5, 1
	global_load_b32 v8, v3, s[40:41]
	s_add_i32 s4, s4, s18
	s_cmp_ge_u32 s5, s7
	s_waitcnt vmcnt(0)
	v_fma_f32 v9, v5, v7, v8
	v_fma_f32 v10, -v5, v8, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v7, -v6, v9, v7
	v_fmac_f32_e32 v8, v6, v10
	s_clause 0x1
	global_store_b32 v3, v7, s[16:17]
	global_store_b32 v3, v8, s[40:41]
	s_cbranch_scc0 .LBB0_30
.LBB0_31:                               ; %.preheader297
                                        ;   in Loop: Header=BB0_15 Depth=3
	s_cmp_ge_u32 s34, s39
	s_mov_b64 s[4:5], s[10:11]
	s_mov_b32 s8, s38
	s_mov_b32 s13, s34
	s_cbranch_scc1 .LBB0_33
.LBB0_32:                               ; %.lr.ph322
                                        ;   Parent Loop BB0_6 Depth=1
                                        ;     Parent Loop BB0_14 Depth=2
                                        ;       Parent Loop BB0_15 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_lshl_b64 s[16:17], s[8:9], 2
	global_load_b32 v7, v3, s[4:5]
	s_add_u32 s16, s19, s16
	s_addc_u32 s17, s20, s17
	s_add_i32 s13, s13, 1
	global_load_b32 v8, v3, s[16:17]
	s_add_i32 s8, s8, s18
	s_waitcnt vmcnt(0)
	v_fma_f32 v9, v5, v7, v8
	v_fma_f32 v10, -v5, v8, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v7, -v6, v9, v7
	v_fmac_f32_e32 v8, v6, v10
	global_store_b32 v3, v7, s[4:5]
	s_add_u32 s4, s4, 4
	s_addc_u32 s5, s5, 0
	s_cmp_ge_u32 s13, s39
	global_store_b32 v3, v8, s[16:17]
	s_cbranch_scc0 .LBB0_32
.LBB0_33:                               ; %.preheader296
                                        ;   in Loop: Header=BB0_15 Depth=3
	s_add_i32 s8, s39, 1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_ge_i32 s8, s18
	s_cbranch_scc1 .LBB0_36
; %bb.34:                               ; %.lr.ph325
                                        ;   in Loop: Header=BB0_15 Depth=3
	s_mov_b32 s15, s9
	s_mov_b32 s13, s9
	s_lshl_b64 s[4:5], s[14:15], 2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
	s_add_u32 s4, s25, s4
	s_addc_u32 s5, s26, s5
	s_lshl_b64 s[16:17], s[12:13], 2
	s_add_u32 s16, s25, s16
	s_addc_u32 s17, s26, s17
.LBB0_35:                               ;   Parent Loop BB0_6 Depth=1
                                        ;     Parent Loop BB0_14 Depth=2
                                        ;       Parent Loop BB0_15 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_clause 0x1
	global_load_b32 v7, v3, s[4:5]
	global_load_b32 v8, v3, s[16:17]
	s_add_i32 s8, s8, 1
	s_waitcnt vmcnt(0)
	v_fma_f32 v9, v5, v7, v8
	v_fma_f32 v10, -v5, v8, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v7, -v6, v9, v7
	v_fmac_f32_e32 v8, v6, v10
	s_clause 0x1
	global_store_b32 v3, v7, s[4:5]
	global_store_b32 v3, v8, s[16:17]
	s_add_u32 s4, s4, 4
	s_addc_u32 s5, s5, 0
	s_add_u32 s16, s16, 4
	s_addc_u32 s17, s17, 0
	s_cmp_ge_i32 s8, s18
	s_cbranch_scc0 .LBB0_35
.LBB0_36:                               ; %.preheader294
                                        ;   in Loop: Header=BB0_15 Depth=3
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_39
; %bb.37:                               ; %.lr.ph327.preheader
                                        ;   in Loop: Header=BB0_15 Depth=3
	s_mov_b32 s4, 0
	s_mov_b32 s5, s18
.LBB0_38:                               ; %.lr.ph327
                                        ;   Parent Loop BB0_6 Depth=1
                                        ;     Parent Loop BB0_14 Depth=2
                                        ;       Parent Loop BB0_15 Depth=3
                                        ; =>      This Inner Loop Header: Depth=4
	s_add_i32 s8, s7, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_lshl_b64 s[16:17], s[8:9], 2
	s_add_u32 s16, s22, s16
	s_addc_u32 s17, s23, s17
	s_add_i32 s8, s39, s4
	global_load_b32 v7, v3, s[16:17]
	s_lshl_b64 s[40:41], s[8:9], 2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_add_u32 s40, s22, s40
	s_addc_u32 s41, s23, s41
	s_add_i32 s5, s5, -1
	global_load_b32 v8, v3, s[40:41]
	s_add_i32 s4, s4, s18
	s_cmp_lg_u32 s5, 0
	s_waitcnt vmcnt(0)
	v_fma_f32 v9, v5, v7, v8
	v_fma_f32 v10, -v5, v8, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_fma_f32 v7, -v6, v9, v7
	v_fmac_f32_e32 v8, v6, v10
	s_clause 0x1
	global_store_b32 v3, v7, s[16:17]
	global_store_b32 v3, v8, s[40:41]
	s_cbranch_scc1 .LBB0_38
.LBB0_39:                               ; %.loopexit295
                                        ;   in Loop: Header=BB0_15 Depth=3
	s_add_i32 s39, s39, 1
	s_add_i32 s38, s38, 1
	s_add_i32 s14, s14, 1
	s_add_i32 s12, s12, s27
	s_cmp_ge_i32 s39, s18
	s_cbranch_scc0 .LBB0_15
; %bb.40:                               ; %.loopexit298
                                        ;   in Loop: Header=BB0_14 Depth=2
	s_add_i32 s35, s35, s27
	s_add_i32 s6, s6, s27
	s_add_i32 s31, s31, s27
	s_add_i32 s33, s33, s27
	s_cmp_lg_u32 s34, s24
	s_cbranch_scc1 .LBB0_14
.LBB0_41:                               ; %.preheader300
                                        ;   in Loop: Header=BB0_6 Depth=1
	s_and_not1_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_44
; %bb.42:                               ; %.lr.ph335.preheader
                                        ;   in Loop: Header=BB0_6 Depth=1
	s_mov_b32 s2, 0
	s_mov_b32 s3, s18
.LBB0_43:                               ; %.lr.ph335
                                        ;   Parent Loop BB0_6 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	v_dual_mov_b32 v4, s2 :: v_dual_add_nc_u32 v5, s2, v1
	s_add_i32 s4, s2, s21
	s_add_i32 s3, s3, -1
	v_mov_b32_e32 v8, s4
	ds_load_b32 v6, v4
	ds_load_b32 v7, v5
	s_add_i32 s2, s2, 4
	s_cmp_lg_u32 s3, 0
	s_waitcnt lgkmcnt(0)
	v_add_f32_e32 v6, v6, v7
	ds_store_b32 v5, v6
	ds_store_b32 v8, v6
	ds_store_b32 v4, v3
	s_cbranch_scc1 .LBB0_43
.LBB0_44:                               ; %._crit_edge336
                                        ;   in Loop: Header=BB0_6 Depth=1
	s_add_i32 s29, s29, 1
	s_mov_b32 s2, 0
	s_cmp_eq_u32 s29, 50
	s_cselect_b32 s3, -1, 0
	s_branch .LBB0_46
.LBB0_45:                               ;   in Loop: Header=BB0_6 Depth=1
	s_mov_b32 s2, -1
	s_mov_b32 s3, -1
                                        ; implicit-def: $sgpr29
.LBB0_46:                               ; %Flow457
                                        ;   in Loop: Header=BB0_6 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_b32 vcc_lo, exec_lo, s3
	s_cbranch_vccz .LBB0_6
; %bb.47:                               ; %loop.exit.guard
	v_cmp_ne_u32_e64 s0, 1, v2
	s_and_not1_b32 vcc_lo, exec_lo, s2
	s_mov_b32 s1, -1
	s_cbranch_vccz .LBB0_52
; %bb.48:                               ; %.critedge
	s_delay_alu instid0(VALU_DEP_1)
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_51
; %bb.49:
	v_dual_mov_b32 v1, -1.0 :: v_dual_mov_b32 v2, v0
	s_mov_b32 s1, s18
.LBB0_50:                               ; %.lr.ph339
                                        ; =>This Inner Loop Header: Depth=1
	ds_store_b32 v2, v1
	v_add_nc_u32_e32 v2, 4, v2
	s_add_i32 s1, s1, -1
	s_delay_alu instid0(SALU_CYCLE_1)
	s_cmp_lg_u32 s1, 0
	s_cbranch_scc1 .LBB0_50
.LBB0_51:                               ; %Flow427
	s_mov_b32 s1, 0
.LBB0_52:                               ; %Flow432
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 vcc_lo, exec_lo, s1
	s_cbranch_vccnz .LBB0_60
; %bb.53:                               ; %.preheader
	s_and_b32 vcc_lo, exec_lo, s0
	s_cbranch_vccnz .LBB0_60
; %bb.54:                               ; %.lr.ph347.preheader
	s_add_i32 s0, s21, 0
	s_mov_b32 s2, 0
	s_add_i32 s0, s0, 4
.LBB0_55:                               ; %.lr.ph347
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_56 Depth 2
	s_add_i32 s1, s2, 1
	s_mov_b32 s3, s2
	s_cmp_ge_i32 s1, s18
	s_mov_b32 s4, s0
	s_mov_b32 s5, s1
	s_cbranch_scc1 .LBB0_57
.LBB0_56:                               ; %.lr.ph343
                                        ;   Parent Loop BB0_55 Depth=1
                                        ; =>  This Inner Loop Header: Depth=2
	s_lshl_b32 s6, s3, 2
	s_delay_alu instid0(SALU_CYCLE_1)
	v_dual_mov_b32 v1, s4 :: v_dual_add_nc_u32 v2, s6, v0
	ds_load_b32 v1, v1
	ds_load_b32 v2, v2
	s_waitcnt lgkmcnt(0)
	v_cmp_lt_f32_e32 vcc_lo, v1, v2
	s_and_b32 s6, vcc_lo, exec_lo
	s_cselect_b32 s3, s5, s3
	s_add_i32 s5, s5, 1
	s_add_i32 s4, s4, 4
	s_cmp_ge_i32 s5, s18
	s_cbranch_scc0 .LBB0_56
.LBB0_57:                               ; %Flow429
                                        ;   in Loop: Header=BB0_55 Depth=1
	s_cmp_lg_u32 s2, s3
	s_cbranch_scc0 .LBB0_59
; %bb.58:                               ;   in Loop: Header=BB0_55 Depth=1
	s_lshl_b32 s3, s3, 2
	s_lshl_b32 s2, s2, 2
	v_add_nc_u32_e32 v1, s3, v0
	v_add_nc_u32_e32 v2, s2, v0
	ds_load_b32 v3, v1
	ds_load_b32 v4, v2
	s_waitcnt lgkmcnt(1)
	ds_store_b32 v2, v3
	s_waitcnt lgkmcnt(1)
	ds_store_b32 v1, v4
.LBB0_59:                               ;   in Loop: Header=BB0_55 Depth=1
	s_add_i32 s0, s0, 4
	s_cmp_eq_u32 s1, s18
	s_mov_b32 s2, s1
	s_cbranch_scc0 .LBB0_55
.LBB0_60:                               ; %.loopexit
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z10CUDAJacobiPfS_PKji
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 28
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 16
		.amdhsa_next_free_sgpr 42
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z10CUDAJacobiPfS_PKji, .Lfunc_end0-_Z10CUDAJacobiPfS_PKji
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2996
; NumSgprs: 44
; NumVgprs: 16
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 5
; VGPRBlocks: 1
; NumSGPRsForWavesPerEU: 44
; NumVGPRsForWavesPerEU: 16
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           4
        .value_kind:     by_value
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 28
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z10CUDAJacobiPfS_PKji
    .private_segment_fixed_size: 0
    .sgpr_count:     44
    .sgpr_spill_count: 0
    .symbol:         _Z10CUDAJacobiPfS_PKji.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     16
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
