/*

	Implement your CUDA kernel in this file

*/

#define TILE_DIM 32

__global__ void mirror_boundaries(double *E_prev, const int n, const int m)
{
  int row = blockIdx.y*blockDim.y + threadIdx.y + 1;
  int col = blockIdx.x*blockDim.x + threadIdx.x + 1;

  if (col == 1) {
    E_prev[row*(n+2)] = E_prev[row*(n+2) + 2];
    E_prev[row*(n+2) + n + 1] = E_prev[row*(n+2) + n - 1];
  }
  if (row == 1) {
    E_prev[col] = E_prev[2*(n+2) + col];
    E_prev[(m+1)*(n+2) + col] = E_prev[(m-1)*(n+2) + col];
  }
}

__global__ void simulate (double *E, double *E_prev, double *R, const double alpha,
			  const int n, const int m, const double kk,
			  const double dt, const double a, const double epsilon,
			  const double M1,const double  M2, const double b)
{

  // __shared__ double E_Block[TILE_DIM][TILE_DIM];
  // __shared__ double R_Block[TILE_DIM][TILE_DIM];

  // int ty = threadIdx.y;
  // int tx = threadIdx.x;

  // int row = blockIdx.y*blockDim.y + threadIdx.y + 1;
  // int col = blockIdx.x*blockDim.x + threadIdx.x + 1;

  // if ((row - 1 < m) && (col - 1 < n)) {

  //   E_Block[ty][tx] = E[row*(n+2) + col];
  //   R_Block[ty][tx] = R[row*(n+2) + col];

  //   E[row*(n+2)+col] = E_prev[row*(n+2)+col] + alpha*(E_prev[row*(n+2)+col+1] + E_prev[row*(n+2)+col-1] - 4*E_prev[row*(n+2)+col] + E_prev[(row+1)*(n+2)+col] + E_prev[(row-1)*(n+2)+col]);

  //   E[row*(n+2)+col] = E_Block[ty][tx] = E_Block[ty][tx] - dt*(kk*E_Block[ty][tx]*(E_Block[ty][tx] - a)*(E_Block[ty][tx] - 1) + E_Block[ty][tx]*R_Block[ty][tx]);
  //   R[row*(n+2)+col] = R_Block[ty][tx] + dt*(epsilon + M1*R_Block[ty][tx]/(E_Block[ty][tx] + M2))*(-R_Block[ty][tx] - kk*E_Block[ty][tx]*(E_Block[ty][tx] - b - 1));
  // }



  __shared__ double E_Block[TILE_DIM][TILE_DIM];
  __shared__ double R_Block[TILE_DIM][TILE_DIM];
  __shared__ double E_prev_Block[TILE_DIM+2][TILE_DIM+2];

  int ty = threadIdx.y;
  int tx = threadIdx.x;

  int row = blockIdx.y*blockDim.y + threadIdx.y + 1;
  int col = blockIdx.x*blockDim.x + threadIdx.x + 1;

  if ((row - 1 < m) && (col - 1 < n)) {
    // E_prev_Block[ty][tx] = E_prev[row*(n+2) + col];

    // if (ty == 2) {
    //   E_prev_Block[0][tx] = E_prev[(row-2)*(n+2) + col];
    //   E_prev_Block[TILE_DIM+1][tx] = E_prev[(row+TILE_DIM-1)*(n+2) + col];
    // }

    // if (tx == 2) {
    //   E_prev_Block[ty][0] = E_prev[row*(n+2) + col-2];
    //   E_prev_Block[ty][TILE_DIM+1] = E_prev[row*(n+2) + col+TILE_DIM-1];
    // }

    // E[row*(n+2)+col] = E_prev_Block[ty][tx] + alpha*(E_prev_Block[ty][tx+1] + E_prev_Block[ty][tx-1] - 4*E_prev_Block[ty][tx] + E_prev_Block[ty+1][tx] + E_prev_Block[ty-1][tx]);


    E_prev_Block[ty+1][tx+1] = E_prev[row*(n+2) + col];

    if (ty == 1) {
      E_prev_Block[0][tx+1] = E_prev[(row-2)*(n+2) + col];
      E_prev_Block[TILE_DIM+1][tx+1] = E_prev[(row+TILE_DIM-1)*(n+2) + col];
    }

    if (tx == 1) {
      E_prev_Block[ty+1][0] = E_prev[row*(n+2) + col-2];
      E_prev_Block[ty+1][TILE_DIM+1] = E_prev[row*(n+2) + col+TILE_DIM-1];
    }

    __syncthreads();

    E[row*(n+2)+col] = E_prev_Block[ty+1][tx+1] + alpha*(E_prev_Block[ty+1][tx+2] + E_prev_Block[ty+1][tx] - 4*E_prev_Block[ty+1][tx+1] + E_prev_Block[ty+2][tx+1] + E_prev_Block[ty][tx+1]);

    // E[row*(n+2)+col] = E_prev[row*(n+2)+col] + alpha*(E_prev[row*(n+2)+col+1] + E_prev[row*(n+2)+col-1] - 4*E_prev[row*(n+2)+col] + E_prev[(row+1)*(n+2)+col] + E_prev[(row-1)*(n+2)+col]);

    E_Block[ty][tx] = E[row*(n+2) + col];
    R_Block[ty][tx] = R[row*(n+2) + col];

    E[row*(n+2)+col] = E_Block[ty][tx] = E_Block[ty][tx] - dt*(kk*E_Block[ty][tx]*(E_Block[ty][tx] - a)*(E_Block[ty][tx] - 1) + E_Block[ty][tx]*R_Block[ty][tx]);
    R[row*(n+2)+col] = R_Block[ty][tx] + dt*(epsilon + M1*R_Block[ty][tx]/(E_Block[ty][tx] + M2))*(-R_Block[ty][tx] - kk*E_Block[ty][tx]*(E_Block[ty][tx] - b - 1));
  }

}

	.file	"tmpxft_0023032d_00000000-6_cardiacsim_kernels_prev_shared.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2010:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2010:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z39__device_stub__Z17mirror_boundariesPdiiPdii
	.type	_Z39__device_stub__Z17mirror_boundariesPdiiPdii, @function
_Z39__device_stub__Z17mirror_boundariesPdiiPdii:
.LFB2032:
	.cfi_startproc
	endbr64
	subq	$120, %rsp
	.cfi_def_cfa_offset 128
	movq	%rdi, 8(%rsp)
	leaq	24(%rsp), %rcx
	leaq	32(%rsp), %rdi
	movl	%esi, 4(%rsp)
	leaq	44(%rsp), %rsi
	movl	%edx, (%rsp)
	leaq	16(%rsp), %rdx
	movq	%fs:40, %rax
	movq	%rax, 104(%rsp)
	xorl	%eax, %eax
	leaq	8(%rsp), %rax
	movl	$1, 40(%rsp)
	movq	%rax, 80(%rsp)
	leaq	4(%rsp), %rax
	movq	%rax, 88(%rsp)
	movq	%rsp, %rax
	movq	%rax, 96(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 32(%rsp)
	movq	%rax, 44(%rsp)
	movl	$1, 52(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L2
	pushq	24(%rsp)
	.cfi_def_cfa_offset 136
	leaq	_Z17mirror_boundariesPdii(%rip), %rdi
	pushq	24(%rsp)
	.cfi_def_cfa_offset 144
	movq	60(%rsp), %rcx
	movl	68(%rsp), %r8d
	movq	48(%rsp), %rsi
	movl	56(%rsp), %edx
	leaq	96(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 136
	popq	%rdx
	.cfi_def_cfa_offset 128
.L2:
	movq	104(%rsp), %rax
	subq	%fs:40, %rax
	je	.L4
	call	__stack_chk_fail@PLT
.L4:
	addq	$120, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2032:
	.size	_Z39__device_stub__Z17mirror_boundariesPdiiPdii, .-_Z39__device_stub__Z17mirror_boundariesPdiiPdii
	.globl	_Z17mirror_boundariesPdii
	.type	_Z17mirror_boundariesPdii, @function
_Z17mirror_boundariesPdii:
.LFB2033:
	.cfi_startproc
	endbr64
	jmp	_Z39__device_stub__Z17mirror_boundariesPdiiPdii
	.cfi_endproc
.LFE2033:
	.size	_Z17mirror_boundariesPdii, .-_Z17mirror_boundariesPdii
	.globl	_Z41__device_stub__Z8simulatePdS_S_diidddddddPdS_S_diiddddddd
	.type	_Z41__device_stub__Z8simulatePdS_S_diidddddddPdS_S_diiddddddd, @function
_Z41__device_stub__Z8simulatePdS_S_diidddddddPdS_S_diiddddddd:
.LFB2034:
	.cfi_startproc
	endbr64
	subq	$280, %rsp
	.cfi_def_cfa_offset 288
	movq	%rdi, 88(%rsp)
	leaq	112(%rsp), %rdi
	movq	%rsi, 80(%rsp)
	leaq	124(%rsp), %rsi
	movq	%rdx, 72(%rsp)
	leaq	96(%rsp), %rdx
	movl	%ecx, 60(%rsp)
	leaq	104(%rsp), %rcx
	movl	%r8d, 56(%rsp)
	movsd	%xmm0, 64(%rsp)
	movsd	%xmm1, 48(%rsp)
	movsd	%xmm2, 40(%rsp)
	movsd	%xmm3, 32(%rsp)
	movsd	%xmm4, 24(%rsp)
	movsd	%xmm5, 16(%rsp)
	movsd	%xmm6, 8(%rsp)
	movsd	%xmm7, (%rsp)
	movq	%fs:40, %rax
	movq	%rax, 264(%rsp)
	xorl	%eax, %eax
	leaq	88(%rsp), %rax
	movl	$1, 120(%rsp)
	movq	%rax, 160(%rsp)
	leaq	80(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	72(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	64(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	60(%rsp), %rax
	movq	%rax, 192(%rsp)
	leaq	56(%rsp), %rax
	movq	%rax, 200(%rsp)
	leaq	48(%rsp), %rax
	movq	%rax, 208(%rsp)
	leaq	40(%rsp), %rax
	movq	%rax, 216(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 224(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 232(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 240(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 248(%rsp)
	movq	%rsp, %rax
	movq	%rax, 256(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 112(%rsp)
	movq	%rax, 124(%rsp)
	movl	$1, 132(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L8
	pushq	104(%rsp)
	.cfi_def_cfa_offset 296
	leaq	_Z8simulatePdS_S_diiddddddd(%rip), %rdi
	pushq	104(%rsp)
	.cfi_def_cfa_offset 304
	movq	140(%rsp), %rcx
	movl	148(%rsp), %r8d
	movq	128(%rsp), %rsi
	movl	136(%rsp), %edx
	leaq	176(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 296
	popq	%rdx
	.cfi_def_cfa_offset 288
.L8:
	movq	264(%rsp), %rax
	subq	%fs:40, %rax
	je	.L10
	call	__stack_chk_fail@PLT
.L10:
	addq	$280, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2034:
	.size	_Z41__device_stub__Z8simulatePdS_S_diidddddddPdS_S_diiddddddd, .-_Z41__device_stub__Z8simulatePdS_S_diidddddddPdS_S_diiddddddd
	.globl	_Z8simulatePdS_S_diiddddddd
	.type	_Z8simulatePdS_S_diiddddddd, @function
_Z8simulatePdS_S_diiddddddd:
.LFB2035:
	.cfi_startproc
	endbr64
	jmp	_Z41__device_stub__Z8simulatePdS_S_diidddddddPdS_S_diiddddddd
	.cfi_endproc
.LFE2035:
	.size	_Z8simulatePdS_S_diiddddddd, .-_Z8simulatePdS_S_diiddddddd
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z8simulatePdS_S_diiddddddd"
.LC1:
	.string	"_Z17mirror_boundariesPdii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2037:
	.cfi_startproc
	endbr64
	pushq	%rbx
	.cfi_def_cfa_offset 16
	.cfi_offset 3, -16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	movq	%rax, %rbx
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	leaq	_Z8simulatePdS_S_diiddddddd(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	movq	%rbx, %rdi
	xorl	%r9d, %r9d
	pushq	$0
	.cfi_def_cfa_offset 24
	leaq	.LC1(%rip), %rdx
	orl	$-1, %r8d
	leaq	_Z17mirror_boundariesPdii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 32
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 40
	pushq	$0
	.cfi_def_cfa_offset 48
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2037:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
/*

	Implement your CUDA kernel in this file

*/

#define TILE_DIM 32

__global__ void mirror_boundaries(double *E_prev, const int n, const int m)
{
  int row = blockIdx.y*blockDim.y + threadIdx.y + 1;
  int col = blockIdx.x*blockDim.x + threadIdx.x + 1;

  if (col == 1) {
    E_prev[row*(n+2)] = E_prev[row*(n+2) + 2];
    E_prev[row*(n+2) + n + 1] = E_prev[row*(n+2) + n - 1];
  }
  if (row == 1) {
    E_prev[col] = E_prev[2*(n+2) + col];
    E_prev[(m+1)*(n+2) + col] = E_prev[(m-1)*(n+2) + col];
  }
}

__global__ void simulate (double *E, double *E_prev, double *R, const double alpha,
			  const int n, const int m, const double kk,
			  const double dt, const double a, const double epsilon,
			  const double M1,const double  M2, const double b)
{

  // __shared__ double E_Block[TILE_DIM][TILE_DIM];
  // __shared__ double R_Block[TILE_DIM][TILE_DIM];

  // int ty = threadIdx.y;
  // int tx = threadIdx.x;

  // int row = blockIdx.y*blockDim.y + threadIdx.y + 1;
  // int col = blockIdx.x*blockDim.x + threadIdx.x + 1;

  // if ((row - 1 < m) && (col - 1 < n)) {

  //   E_Block[ty][tx] = E[row*(n+2) + col];
  //   R_Block[ty][tx] = R[row*(n+2) + col];

  //   E[row*(n+2)+col] = E_prev[row*(n+2)+col] + alpha*(E_prev[row*(n+2)+col+1] + E_prev[row*(n+2)+col-1] - 4*E_prev[row*(n+2)+col] + E_prev[(row+1)*(n+2)+col] + E_prev[(row-1)*(n+2)+col]);

  //   E[row*(n+2)+col] = E_Block[ty][tx] = E_Block[ty][tx] - dt*(kk*E_Block[ty][tx]*(E_Block[ty][tx] - a)*(E_Block[ty][tx] - 1) + E_Block[ty][tx]*R_Block[ty][tx]);
  //   R[row*(n+2)+col] = R_Block[ty][tx] + dt*(epsilon + M1*R_Block[ty][tx]/(E_Block[ty][tx] + M2))*(-R_Block[ty][tx] - kk*E_Block[ty][tx]*(E_Block[ty][tx] - b - 1));
  // }



  __shared__ double E_Block[TILE_DIM][TILE_DIM];
  __shared__ double R_Block[TILE_DIM][TILE_DIM];
  __shared__ double E_prev_Block[TILE_DIM+2][TILE_DIM+2];

  int ty = threadIdx.y;
  int tx = threadIdx.x;

  int row = blockIdx.y*blockDim.y + threadIdx.y + 1;
  int col = blockIdx.x*blockDim.x + threadIdx.x + 1;

  if ((row - 1 < m) && (col - 1 < n)) {
    // E_prev_Block[ty][tx] = E_prev[row*(n+2) + col];

    // if (ty == 2) {
    //   E_prev_Block[0][tx] = E_prev[(row-2)*(n+2) + col];
    //   E_prev_Block[TILE_DIM+1][tx] = E_prev[(row+TILE_DIM-1)*(n+2) + col];
    // }

    // if (tx == 2) {
    //   E_prev_Block[ty][0] = E_prev[row*(n+2) + col-2];
    //   E_prev_Block[ty][TILE_DIM+1] = E_prev[row*(n+2) + col+TILE_DIM-1];
    // }

    // E[row*(n+2)+col] = E_prev_Block[ty][tx] + alpha*(E_prev_Block[ty][tx+1] + E_prev_Block[ty][tx-1] - 4*E_prev_Block[ty][tx] + E_prev_Block[ty+1][tx] + E_prev_Block[ty-1][tx]);


    E_prev_Block[ty+1][tx+1] = E_prev[row*(n+2) + col];

    if (ty == 1) {
      E_prev_Block[0][tx+1] = E_prev[(row-2)*(n+2) + col];
      E_prev_Block[TILE_DIM+1][tx+1] = E_prev[(row+TILE_DIM-1)*(n+2) + col];
    }

    if (tx == 1) {
      E_prev_Block[ty+1][0] = E_prev[row*(n+2) + col-2];
      E_prev_Block[ty+1][TILE_DIM+1] = E_prev[row*(n+2) + col+TILE_DIM-1];
    }

    __syncthreads();

    E[row*(n+2)+col] = E_prev_Block[ty+1][tx+1] + alpha*(E_prev_Block[ty+1][tx+2] + E_prev_Block[ty+1][tx] - 4*E_prev_Block[ty+1][tx+1] + E_prev_Block[ty+2][tx+1] + E_prev_Block[ty][tx+1]);

    // E[row*(n+2)+col] = E_prev[row*(n+2)+col] + alpha*(E_prev[row*(n+2)+col+1] + E_prev[row*(n+2)+col-1] - 4*E_prev[row*(n+2)+col] + E_prev[(row+1)*(n+2)+col] + E_prev[(row-1)*(n+2)+col]);

    E_Block[ty][tx] = E[row*(n+2) + col];
    R_Block[ty][tx] = R[row*(n+2) + col];

    E[row*(n+2)+col] = E_Block[ty][tx] = E_Block[ty][tx] - dt*(kk*E_Block[ty][tx]*(E_Block[ty][tx] - a)*(E_Block[ty][tx] - 1) + E_Block[ty][tx]*R_Block[ty][tx]);
    R[row*(n+2)+col] = R_Block[ty][tx] + dt*(epsilon + M1*R_Block[ty][tx]/(E_Block[ty][tx] + M2))*(-R_Block[ty][tx] - kk*E_Block[ty][tx]*(E_Block[ty][tx] - b - 1));
  }

}

	.text
	.file	"cardiacsim_kernels_prev_shared.hip"
	.globl	_Z32__device_stub__mirror_boundariesPdii # -- Begin function _Z32__device_stub__mirror_boundariesPdii
	.type	_Z32__device_stub__mirror_boundariesPdii,@function
_Z32__device_stub__mirror_boundariesPdii: # @_Z32__device_stub__mirror_boundariesPdii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$96, %rsp
	.cfi_def_cfa_offset 144
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	24(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	4(%rsp), %rcx
	movl	%esi, (%rcx)
	movq	%rsp, %rsi
	movl	%edx, (%rsi)
	leaq	64(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rcx, 8(%rbx)
	movq	%rsi, 16(%rbx)
	leaq	48(%rsp), %r14
	leaq	32(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z17mirror_boundariesPdii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$112, %rsp
	.cfi_adjust_cfa_offset -112
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z32__device_stub__mirror_boundariesPdii, .Lfunc_end0-_Z32__device_stub__mirror_boundariesPdii
	.cfi_endproc
                                        # -- End function
	.globl	_Z23__device_stub__simulatePdS_S_diiddddddd # -- Begin function _Z23__device_stub__simulatePdS_S_diiddddddd
	.type	_Z23__device_stub__simulatePdS_S_diiddddddd,@function
_Z23__device_stub__simulatePdS_S_diiddddddd: # @_Z23__device_stub__simulatePdS_S_diiddddddd
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$256, %rsp                      # imm = 0x100
	.cfi_def_cfa_offset 304
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	104(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	96(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	88(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	80(%rsp), %rdx
	movsd	%xmm0, (%rdx)
	leaq	4(%rsp), %r9
	movl	%ecx, (%r9)
	movq	%rsp, %rcx
	movl	%r8d, (%rcx)
	leaq	72(%rsp), %r8
	movsd	%xmm1, (%r8)
	leaq	64(%rsp), %r10
	movsd	%xmm2, (%r10)
	leaq	56(%rsp), %r11
	movsd	%xmm3, (%r11)
	leaq	48(%rsp), %r14
	movsd	%xmm4, (%r14)
	leaq	40(%rsp), %r15
	movsd	%xmm5, (%r15)
	leaq	32(%rsp), %r12
	movsd	%xmm6, (%r12)
	leaq	24(%rsp), %r13
	movsd	%xmm7, (%r13)
	leaq	144(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%r9, 32(%rbx)
	movq	%rcx, 40(%rbx)
	movq	%r8, 48(%rbx)
	movq	%r10, 56(%rbx)
	movq	%r11, 64(%rbx)
	movq	%r14, 72(%rbx)
	movq	%r15, 80(%rbx)
	movq	%r12, 88(%rbx)
	movq	%r13, 96(%rbx)
	leaq	128(%rsp), %r14
	leaq	112(%rsp), %r15
	leaq	16(%rsp), %r12
	leaq	8(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z8simulatePdS_S_diiddddddd, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$272, %rsp                      # imm = 0x110
	.cfi_adjust_cfa_offset -272
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	_Z23__device_stub__simulatePdS_S_diiddddddd, .Lfunc_end1-_Z23__device_stub__simulatePdS_S_diiddddddd
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	pushq	%rbx
	.cfi_def_cfa_offset 16
	subq	$32, %rsp
	.cfi_def_cfa_offset 48
	.cfi_offset %rbx, -16
	movq	__hip_gpubin_handle(%rip), %rbx
	testq	%rbx, %rbx
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rbx
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z17mirror_boundariesPdii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z8simulatePdS_S_diiddddddd, %esi
	movl	$.L__unnamed_2, %edx
	movl	$.L__unnamed_2, %ecx
	movq	%rbx, %rdi
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	popq	%rbx
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z17mirror_boundariesPdii,@object # @_Z17mirror_boundariesPdii
	.section	.rodata,"a",@progbits
	.globl	_Z17mirror_boundariesPdii
	.p2align	3, 0x0
_Z17mirror_boundariesPdii:
	.quad	_Z32__device_stub__mirror_boundariesPdii
	.size	_Z17mirror_boundariesPdii, 8

	.type	_Z8simulatePdS_S_diiddddddd,@object # @_Z8simulatePdS_S_diiddddddd
	.globl	_Z8simulatePdS_S_diiddddddd
	.p2align	3, 0x0
_Z8simulatePdS_S_diiddddddd:
	.quad	_Z23__device_stub__simulatePdS_S_diiddddddd
	.size	_Z8simulatePdS_S_diiddddddd, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z17mirror_boundariesPdii"
	.size	.L__unnamed_1, 26

	.type	.L__unnamed_2,@object           # @1
.L__unnamed_2:
	.asciz	"_Z8simulatePdS_S_diiddddddd"
	.size	.L__unnamed_2, 28

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z32__device_stub__mirror_boundariesPdii
	.addrsig_sym _Z23__device_stub__simulatePdS_S_diiddddddd
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z17mirror_boundariesPdii
	.addrsig_sym _Z8simulatePdS_S_diiddddddd
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z17mirror_boundariesPdii ; -- Begin function _Z17mirror_boundariesPdii
	.globl	_Z17mirror_boundariesPdii
	.p2align	8
	.type	_Z17mirror_boundariesPdii,@function
_Z17mirror_boundariesPdii:              ; @_Z17mirror_boundariesPdii
; %bb.0:
	s_clause 0x1
	s_load_b32 s4, s[0:1], 0x1c
	s_load_b128 s[0:3], s[0:1], 0x0
	v_and_b32_e32 v2, 0x3ff, v0
	v_bfe_u32 v3, v0, 10, 10
	s_waitcnt lgkmcnt(0)
	s_and_b32 s5, s4, 0xffff
	s_lshr_b32 s4, s4, 16
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[0:1], null, s14, s5, v[2:3]
	v_mad_u64_u32 v[1:2], null, s15, s4, v[3:4]
	s_mov_b32 s4, exec_lo
	v_cmpx_eq_u32_e32 0, v0
	s_cbranch_execz .LBB0_2
; %bb.1:
	s_add_i32 s6, s2, 2
	s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
	v_mad_u64_u32 v[2:3], null, s6, v1, s[6:7]
	s_ashr_i32 s7, s2, 31
	s_mov_b32 s6, s2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_lshl_b64 s[6:7], s[6:7], 3
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	v_add_co_u32 v6, vcc_lo, v2, s6
	global_load_b64 v[4:5], v[2:3], off offset:16
	v_add_co_ci_u32_e32 v7, vcc_lo, s7, v3, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[2:3], v[4:5], off
	global_load_b64 v[2:3], v[6:7], off offset:-8
	s_waitcnt vmcnt(0)
	global_store_b64 v[6:7], v[2:3], off offset:8
.LBB0_2:
	s_or_b32 exec_lo, exec_lo, s4
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	s_mov_b32 s4, exec_lo
	v_cmpx_eq_u32_e32 0, v1
	s_cbranch_execz .LBB0_4
; %bb.3:
	v_add_nc_u32_e32 v1, 1, v0
	s_add_i32 s2, s2, 2
	s_add_i32 s3, s3, -1
	s_lshl_b32 s4, s2, 1
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_add_nc_u32_e32 v2, s4, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v3, 31, v2
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v2, vcc_lo, s0, v2
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	global_load_b64 v[2:3], v[2:3], off
	s_waitcnt vmcnt(0)
	v_mad_u64_u32 v[4:5], null, s3, s2, v[1:2]
	v_ashrrev_i32_e32 v1, 31, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	v_ashrrev_i32_e32 v5, 31, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, s0, v0
	v_lshlrev_b64 v[5:6], 3, v[4:5]
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
	global_store_b64 v[0:1], v[2:3], off offset:8
	v_add_co_u32 v5, vcc_lo, s0, v5
	v_add_co_ci_u32_e32 v6, vcc_lo, s1, v6, vcc_lo
	v_add_nc_u32_e32 v2, s4, v4
	global_load_b64 v[0:1], v[5:6], off
	v_ashrrev_i32_e32 v3, 31, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[2:3], 3, v[2:3]
	v_add_co_u32 v2, vcc_lo, s0, v2
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, s1, v3, vcc_lo
	s_waitcnt vmcnt(0)
	global_store_b64 v[2:3], v[0:1], off
.LBB0_4:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z17mirror_boundariesPdii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 272
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 8
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z17mirror_boundariesPdii, .Lfunc_end0-_Z17mirror_boundariesPdii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 432
; NumSgprs: 18
; NumVgprs: 8
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 0
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 8
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.protected	_Z8simulatePdS_S_diiddddddd ; -- Begin function _Z8simulatePdS_S_diiddddddd
	.globl	_Z8simulatePdS_S_diiddddddd
	.p2align	8
	.type	_Z8simulatePdS_S_diiddddddd,@function
_Z8simulatePdS_S_diiddddddd:            ; @_Z8simulatePdS_S_diiddddddd
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x6c
	s_load_b64 s[4:5], s[0:1], 0x20
	v_bfe_u32 v2, v0, 10, 10
	v_and_b32_e32 v3, 0x3ff, v0
	s_waitcnt lgkmcnt(0)
	s_lshr_b32 s3, s2, 16
	s_and_b32 s2, s2, 0xffff
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[0:1], null, s15, s3, v[2:3]
	v_mad_u64_u32 v[4:5], null, s14, s2, v[3:4]
	v_cmp_gt_i32_e32 vcc_lo, s5, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cmp_gt_i32_e64 s2, s4, v4
	s_and_b32 s2, vcc_lo, s2
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_saveexec_b32 s3, s2
	s_cbranch_execz .LBB1_6
; %bb.1:
	s_add_i32 s2, s4, 2
	v_add_nc_u32_e32 v9, 1, v4
	v_mad_u64_u32 v[6:7], null, s2, v0, s[2:3]
	s_load_b256 s[4:11], s[0:1], 0x0
	v_lshlrev_b32_e32 v8, 3, v3
	s_mov_b32 s3, exec_lo
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mad_u32_u24 v7, 0x110, v2, v8
	v_add_nc_u32_e32 v0, v6, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v1, 31, v0
	v_lshlrev_b64 v[0:1], 3, v[0:1]
	s_waitcnt lgkmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, s6, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v1, vcc_lo
	global_load_b64 v[10:11], v[4:5], off
	s_waitcnt vmcnt(0)
	ds_store_b64 v7, v[10:11] offset:280
	v_cmpx_eq_u32_e32 1, v2
	s_cbranch_execz .LBB1_3
; %bb.2:
	s_lshl_b32 s12, s2, 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_subrev_nc_u32_e32 v6, s12, v6
	v_add_nc_u32_e32 v9, v6, v9
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v10, 31, v9
	v_mad_u64_u32 v[11:12], null, s2, 33, v[9:10]
	v_lshlrev_b64 v[9:10], 3, v[9:10]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v9, vcc_lo, s6, v9
	v_ashrrev_i32_e32 v12, 31, v11
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v10, vcc_lo, s7, v10, vcc_lo
	v_lshlrev_b64 v[11:12], 3, v[11:12]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v11, vcc_lo, s6, v11
	v_add_co_ci_u32_e32 v12, vcc_lo, s7, v12, vcc_lo
	s_clause 0x1
	global_load_b64 v[9:10], v[9:10], off
	global_load_b64 v[11:12], v[11:12], off
	s_waitcnt vmcnt(1)
	ds_store_b64 v8, v[9:10] offset:8
	s_waitcnt vmcnt(0)
	ds_store_b64 v8, v[11:12] offset:8984
.LBB1_3:
	s_or_b32 exec_lo, exec_lo, s3
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mov_b32 s2, exec_lo
	v_cmpx_eq_u32_e32 1, v3
	s_cbranch_execz .LBB1_5
; %bb.4:
	s_clause 0x1
	global_load_b64 v[8:9], v[4:5], off offset:-16
	global_load_b64 v[3:4], v[4:5], off offset:248
	v_mul_u32_u24_e32 v2, 0x110, v2
	s_waitcnt vmcnt(0)
	ds_store_2addr_b64 v2, v[8:9], v[3:4] offset0:34 offset1:67
.LBB1_5:
	s_or_b32 exec_lo, exec_lo, s2
	s_waitcnt lgkmcnt(0)
	s_barrier
	buffer_gl0_inv
	ds_load_2addr_b64 v[2:5], v7 offset0:1 offset1:36
	ds_load_2addr_b64 v[8:11], v7 offset0:34 offset1:35
	ds_load_b64 v[6:7], v7 offset:552
	s_waitcnt lgkmcnt(1)
	v_add_f64 v[4:5], v[4:5], v[8:9]
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_fma_f64 v[4:5], v[10:11], -4.0, v[4:5]
	s_waitcnt lgkmcnt(0)
	v_add_f64 v[4:5], v[6:7], v[4:5]
	s_delay_alu instid0(VALU_DEP_1)
	v_add_f64 v[2:3], v[2:3], v[4:5]
	v_add_co_u32 v4, vcc_lo, s4, v0
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, s8, v0
	v_add_co_ci_u32_e32 v1, vcc_lo, s9, v1, vcc_lo
	v_fma_f64 v[2:3], v[2:3], s[10:11], v[10:11]
	s_load_b256 s[4:11], s[0:1], 0x28
	global_store_b64 v[4:5], v[2:3], off
	global_load_b64 v[6:7], v[0:1], off
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[8:9], v[2:3], s[4:5]
	v_add_f64 v[10:11], v[2:3], -s[8:9]
	v_add_f64 v[12:13], v[2:3], -1.0
	s_clause 0x1
	s_load_b128 s[12:15], s[0:1], 0x48
	s_load_b64 s[0:1], s[0:1], 0x58
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[8:9], v[8:9], v[10:11]
	v_mul_f64 v[8:9], v[12:13], v[8:9]
	s_waitcnt vmcnt(0)
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[8:9], v[6:7], v[2:3], v[8:9]
	v_fma_f64 v[2:3], -v[8:9], s[6:7], v[2:3]
	s_waitcnt lgkmcnt(0)
	v_mul_f64 v[8:9], v[6:7], s[12:13]
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_f64 v[10:11], v[2:3], s[14:15]
	v_div_scale_f64 v[12:13], null, v[10:11], v[10:11], v[8:9]
	v_div_scale_f64 v[18:19], vcc_lo, v[8:9], v[10:11], v[8:9]
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f64_e32 v[14:15], v[12:13]
	s_waitcnt_depctr 0xfff
	v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0
	v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_fma_f64 v[16:17], -v[12:13], v[14:15], 1.0
	v_fma_f64 v[14:15], v[14:15], v[16:17], v[14:15]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_f64 v[16:17], v[18:19], v[14:15]
	v_fma_f64 v[12:13], -v[12:13], v[16:17], v[18:19]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_div_fmas_f64 v[12:13], v[12:13], v[14:15], v[16:17]
	v_div_fixup_f64 v[8:9], v[12:13], v[10:11], v[8:9]
	v_add_f64 v[10:11], v[2:3], -s[0:1]
	v_mul_f64 v[12:13], v[2:3], s[4:5]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_f64 v[8:9], v[8:9], s[10:11]
	v_add_f64 v[10:11], v[10:11], -1.0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_mul_f64 v[8:9], v[8:9], s[6:7]
	v_fma_f64 v[10:11], -v[12:13], v[10:11], -v[6:7]
	s_delay_alu instid0(VALU_DEP_1)
	v_fma_f64 v[6:7], v[8:9], v[10:11], v[6:7]
	global_store_b64 v[4:5], v[2:3], off
	global_store_b64 v[0:1], v[6:7], off
.LBB1_6:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z8simulatePdS_S_diiddddddd
		.amdhsa_group_segment_fixed_size 9248
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 352
		.amdhsa_user_sgpr_count 14
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 1
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 1
		.amdhsa_next_free_vgpr 20
		.amdhsa_next_free_sgpr 16
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end1:
	.size	_Z8simulatePdS_S_diiddddddd, .Lfunc_end1-_Z8simulatePdS_S_diiddddddd
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 876
; NumSgprs: 18
; NumVgprs: 20
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 9248 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 18
; NumVGPRsForWavesPerEU: 20
; Occupancy: 16
; WaveLimiterHint : 1
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 14
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 1
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           4
        .value_kind:     by_value
      - .offset:         12
        .size:           4
        .value_kind:     by_value
      - .offset:         16
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         20
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         24
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         28
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         30
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         32
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         34
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         36
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         38
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         56
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         64
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         72
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         80
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 272
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z17mirror_boundariesPdii
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z17mirror_boundariesPdii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     8
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           8
        .value_kind:     by_value
      - .offset:         48
        .size:           8
        .value_kind:     by_value
      - .offset:         56
        .size:           8
        .value_kind:     by_value
      - .offset:         64
        .size:           8
        .value_kind:     by_value
      - .offset:         72
        .size:           8
        .value_kind:     by_value
      - .offset:         80
        .size:           8
        .value_kind:     by_value
      - .offset:         88
        .size:           8
        .value_kind:     by_value
      - .offset:         96
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         100
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         104
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         108
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         110
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         112
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         114
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         116
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         118
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         136
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         144
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         152
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         160
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 9248
    .kernarg_segment_align: 8
    .kernarg_segment_size: 352
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z8simulatePdS_S_diiddddddd
    .private_segment_fixed_size: 0
    .sgpr_count:     18
    .sgpr_spill_count: 0
    .symbol:         _Z8simulatePdS_S_diiddddddd.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     20
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
