#include <cuda.h>
#include <iostream>

using namespace std;

__global__ void InitialClusteringKernel_CUDA (float* im_vals, unsigned short* max_response_r, unsigned short* max_response_c, unsigned short* max_response_z , int r, int c, int z, int scale_xy, int scale_z, int offset)
{
	int iGID = blockIdx.x * blockDim.x + threadIdx.x + offset; //global index
	
	if (iGID >= r * c * z)
		return;

	int rem = ((long)iGID) % (r*c);
	int k1 = ((int)iGID-rem) / (r*c); 
	int j1 = ((long)rem) % c;
	int i1 = (rem-j1)/c;

	int min_r = (int) max((float)(0.0),(float)(i1-scale_xy));
	int min_c = (int) max((float)(0.0),(float)(j1-scale_xy));
	int min_z = (int) max((float)(0.0),(float)(k1-scale_z));
	int max_r = (int) min((float)(r-1),(float)(i1+scale_xy));
	int max_c = (int) min((float)(c-1),(float)(j1+scale_xy));                         
	int max_z = (int) min((float)(z-1),(float)(k1+scale_z));

	//If we are running on the GPU, it makes no sense to load this big array just to save computation since seed point should be the maximum anyways
	//if(local_max_vals[(k1*r*c)+(i1*c)+j1] == 0) //if current pixel is not a seed point		
	//{
		float mx = im_vals[(min_z*r*c)+(min_r*c)+min_c];//A[r1][c1][z1];
		
		//Do not access arrays in a hot loop if you can just just do all the updates at the end, much faster to use registers
		int r_temp = min_r;
		int c_temp = min_c;
		int z_temp = min_z;	    

		float im_vals_temp;
		
		for(int i= min_r; i<= max_r; i++)
		{
			for(int j= min_c; j <= max_c; j++)
			{
				for(int k = min_z; k <= max_z; k++)
				{
					im_vals_temp = im_vals[(k*r*c)+(i*c)+j];

					if( im_vals_temp >= mx)
					{
						mx = im_vals_temp;

						r_temp = i;
						c_temp = j;
						z_temp = k;
					}
				}
			}
		} 

		max_response_r[i1 * (c * z) + j1 * z + k1] = r_temp;
		max_response_c[i1 * (c * z) + j1 * z + k1] = c_temp;
		max_response_z[i1 * (c * z) + j1 * z + k1] = z_temp;
	//}
}


extern "C"
void initialClustering_CUDA (float* im_vals, unsigned short* local_max_vals, unsigned short* max_response_r, unsigned short* max_response_c, unsigned short* max_response_z , int r, int c, int z, int scale_xy, int scale_z)
{
	cout << "Entering initialClustering_CUDA" << endl;
	
	cudaError_t errorcode;

	float* dev_im_vals; 
	//unsigned short* dev_local_max_vals;
	unsigned short* dev_max_response_r;
	unsigned short* dev_max_response_c;
	unsigned short* dev_max_response_z;

	size_t free_mem, total_mem;
	cudaMemGetInfo(&free_mem, &total_mem);

	cout << free_mem / (double)(1024 * 1024) << " " << total_mem / (double)(1024 * 1024) << endl;

	cout << "Allocating " << (sizeof(*im_vals) * r * c * z)/(double)(1024*1024) << " MB of memory on GPU for im_vals" << endl;
	//cout << "Allocating " << (sizeof(*local_max_vals) * r * c * z)/(double)(1024*1024) << " MB of memory on GPU for local_max_vals" << endl;
	cout << "Allocating " << (sizeof(*max_response_r) * r * c * z)/(double)(1024*1024) << " MB of memory on GPU for max_response_r" << endl;
	cout << "Allocating " << (sizeof(*max_response_c) * r * c * z)/(double)(1024*1024) << " MB of memory on GPU for max_response_c" << endl;
	cout << "Allocating " << (sizeof(*max_response_z) * r * c * z)/(double)(1024*1024) << " MB of memory on GPU for max_response_z" << endl;
	
	//Allocate memory on device
	errorcode = cudaMalloc((void**) &dev_im_vals, r * c * z * sizeof(*im_vals));
	//errorcode = cudaMalloc((void**) &dev_local_max_vals, r * c * z * sizeof(*local_max_vals));
	errorcode = cudaMalloc((void**) &dev_max_response_r, r * c * z * sizeof(*dev_max_response_r));
	errorcode = cudaMalloc((void**) &dev_max_response_c, r * c * z * sizeof(*dev_max_response_c));
	errorcode = cudaMalloc((void**) &dev_max_response_z, r * c * z * sizeof(*dev_max_response_z));

	//cout << errorcode << endl;

	//Copy host memory contents to device contents
	cudaMemcpy(dev_im_vals, im_vals, r * c * z * sizeof(*im_vals), cudaMemcpyHostToDevice);
	//cudaMemcpy(dev_local_max_vals, local_max_vals, r * c * z * sizeof(*local_max_vals), cudaMemcpyHostToDevice);

	//prefer 48 KB L1
	CUresult drivererrorcode = cuCtxSetCacheConfig(CU_FUNC_CACHE_PREFER_L1);
	//cout << drivererrorcode << endl;

	int device;
	cudaDeviceProp device_prop;

	cudaGetDevice(&device);
	cudaGetDeviceProperties(&device_prop, device);
	
	int threadsPerBlock = device_prop.maxThreadsDim[0];
	//int threadsPerBlock = 32;
	//int numBlocks = device_prop.multiProcessorCount;
	int numBlocks = device_prop.maxGridSize[0];
	
	//Run kernel repeatedly with offset since we cannot launch too many threads at once
	for (int k = 0; k < r * c * z; k+= numBlocks * threadsPerBlock) //Run kernel on groups of pixels at a time
	{
		InitialClusteringKernel_CUDA<<< numBlocks , threadsPerBlock >>>(dev_im_vals, dev_max_response_r, dev_max_response_c, dev_max_response_z , r, c, z, scale_xy, scale_z, k);
	}
	
	//Copy device memory contents back to host memory
	cudaMemcpy(max_response_r, dev_max_response_r, r * c * z * sizeof(*max_response_r), cudaMemcpyDeviceToHost);
	cudaMemcpy(max_response_c, dev_max_response_c, r * c * z * sizeof(*max_response_c), cudaMemcpyDeviceToHost);
	cudaMemcpy(max_response_z, dev_max_response_z, r * c * z * sizeof(*max_response_z), cudaMemcpyDeviceToHost);

	cout << cudaGetErrorString(cudaGetLastError()) << endl;
	
	//Block until all precious commands are complete
	cudaThreadSynchronize();

	cudaFree(dev_im_vals);
	//cudaFree(dev_local_max_vals);
	cudaFree(max_response_r);
	cudaFree(max_response_c);
	cudaFree(max_response_z);
	
	cout << "CUDA done" << endl;
}
	.file	"tmpxft_003a2916_00000000-6_Local_Max_Clust_3D.cudafe1.cpp"
	.text
#APP
	.globl _ZSt21ios_base_library_initv

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB3638:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE3638:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.align 2
	.type	_ZNSolsEPFRSoS_E.isra.0, @function
_ZNSolsEPFRSoS_E.isra.0:
.LFB4293:
	.cfi_startproc
	jmp	*%rsi
	.cfi_endproc
.LFE4293:
	.size	_ZNSolsEPFRSoS_E.isra.0, .-_ZNSolsEPFRSoS_E.isra.0
	.globl	_Z62__device_stub__Z28InitialClusteringKernel_CUDAPfPtS0_S0_iiiiiiPfPtS0_S0_iiiiii
	.type	_Z62__device_stub__Z28InitialClusteringKernel_CUDAPfPtS0_S0_iiiiiiPfPtS0_S0_iiiiii, @function
_Z62__device_stub__Z28InitialClusteringKernel_CUDAPfPtS0_S0_iiiiiiPfPtS0_S0_iiiiii:
.LFB3660:
	.cfi_startproc
	endbr64
	subq	$216, %rsp
	.cfi_def_cfa_offset 224
	movq	%rdi, 40(%rsp)
	leaq	72(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	84(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	56(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	64(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movl	%r9d, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 200(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 80(%rsp)
	movq	%rax, 120(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 160(%rsp)
	leaq	224(%rsp), %rax
	movq	%rax, 168(%rsp)
	leaq	232(%rsp), %rax
	movq	%rax, 176(%rsp)
	leaq	240(%rsp), %rax
	movq	%rax, 184(%rsp)
	leaq	248(%rsp), %rax
	movq	%rax, 192(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 72(%rsp)
	movq	%rax, 84(%rsp)
	movl	$1, 92(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L3
	pushq	64(%rsp)
	.cfi_def_cfa_offset 232
	leaq	_Z28InitialClusteringKernel_CUDAPfPtS0_S0_iiiiii(%rip), %rdi
	pushq	64(%rsp)
	.cfi_def_cfa_offset 240
	movq	100(%rsp), %rcx
	movl	108(%rsp), %r8d
	movq	88(%rsp), %rsi
	movl	96(%rsp), %edx
	leaq	136(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 232
	popq	%rdx
	.cfi_def_cfa_offset 224
.L3:
	movq	200(%rsp), %rax
	subq	%fs:40, %rax
	je	.L5
	call	__stack_chk_fail@PLT
.L5:
	addq	$216, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3660:
	.size	_Z62__device_stub__Z28InitialClusteringKernel_CUDAPfPtS0_S0_iiiiiiPfPtS0_S0_iiiiii, .-_Z62__device_stub__Z28InitialClusteringKernel_CUDAPfPtS0_S0_iiiiiiPfPtS0_S0_iiiiii
	.globl	_Z28InitialClusteringKernel_CUDAPfPtS0_S0_iiiiii
	.type	_Z28InitialClusteringKernel_CUDAPfPtS0_S0_iiiiii, @function
_Z28InitialClusteringKernel_CUDAPfPtS0_S0_iiiiii:
.LFB3661:
	.cfi_startproc
	endbr64
	jmp	_Z62__device_stub__Z28InitialClusteringKernel_CUDAPfPtS0_S0_iiiiiiPfPtS0_S0_iiiiii
	.cfi_endproc
.LFE3661:
	.size	_Z28InitialClusteringKernel_CUDAPfPtS0_S0_iiiiii, .-_Z28InitialClusteringKernel_CUDAPfPtS0_S0_iiiiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"Entering initialClustering_CUDA"
.LC2:
	.string	" "
.LC3:
	.string	"Allocating "
.LC4:
	.string	" MB of memory on GPU for im_vals"
.LC5:
	.string	" MB of memory on GPU for max_response_r"
.LC6:
	.string	" MB of memory on GPU for max_response_c"
.LC7:
	.string	" MB of memory on GPU for max_response_z"
.LC8:
	.string	"CUDA done"
	.text
	.globl	initialClustering_CUDA
	.type	initialClustering_CUDA, @function
initialClustering_CUDA:
.LFB3635:
	.cfi_startproc
	endbr64
	pushq	%r15
	.cfi_def_cfa_offset 16
	.cfi_offset 15, -16
	leaq	.LC0(%rip), %rsi
	pushq	%r14
	.cfi_def_cfa_offset 24
	.cfi_offset 14, -24
	pushq	%r13
	.cfi_def_cfa_offset 32
	.cfi_offset 13, -32
	pushq	%r12
	.cfi_def_cfa_offset 40
	.cfi_offset 12, -40
	movq	%rdi, %r12
	pushq	%rbp
	.cfi_def_cfa_offset 48
	.cfi_offset 6, -48
	leaq	_ZSt4cout(%rip), %rbp
	pushq	%rbx
	.cfi_def_cfa_offset 56
	.cfi_offset 3, -56
	movq	%rbp, %rdi
	movl	%r9d, %ebx
	subq	$1176, %rsp
	.cfi_def_cfa_offset 1232
	movq	%rdx, 16(%rsp)
	movq	%rcx, 24(%rsp)
	movq	%r8, 32(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 1160(%rsp)
	xorl	%eax, %eax
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	leaq	96(%rsp), %rsi
	leaq	88(%rsp), %rdi
	call	cudaMemGetInfo@PLT
	movq	88(%rsp), %rax
	testq	%rax, %rax
	js	.L10
	cvtsi2sdq	%rax, %xmm0
	jmp	.L11
.L10:
	movq	%rax, %rdx
	andl	$1, %eax
	shrq	%rdx
	orq	%rax, %rdx
	cvtsi2sdq	%rdx, %xmm0
	addsd	%xmm0, %xmm0
.L11:
	mulsd	.LC1(%rip), %xmm0
	movq	%rbp, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC2(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	96(%rsp), %rdx
	movq	%rax, %rdi
	testq	%rdx, %rdx
	js	.L12
	cvtsi2sdq	%rdx, %xmm0
	jmp	.L13
.L12:
	movq	%rdx, %rax
	andl	$1, %edx
	shrq	%rax
	orq	%rdx, %rax
	cvtsi2sdq	%rax, %xmm0
	addsd	%xmm0, %xmm0
.L13:
	mulsd	.LC1(%rip), %xmm0
	leaq	.LC3(%rip), %r13
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movq	%rbp, %rdi
	movq	%r13, %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movslq	1232(%rsp), %r14
	movq	%rax, %rdi
	movslq	1240(%rsp), %rax
	imulq	%rax, %r14
	movslq	%ebx, %rax
	imulq	%rax, %r14
	movq	%r14, %rax
	salq	$2, %rax
	js	.L14
	cvtsi2sdq	%rax, %xmm0
	jmp	.L15
.L14:
	shrq	%rax
	cvtsi2sdq	%rax, %xmm0
	addsd	%xmm0, %xmm0
.L15:
	mulsd	.LC1(%rip), %xmm0
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC4(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movq	%rbp, %rdi
	movq	%r13, %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rax, %rdi
	addq	%r14, %r14
	js	.L16
	cvtsi2sdq	%r14, %xmm0
	jmp	.L17
.L16:
	movq	%r14, %rax
	andl	$1, %r14d
	shrq	%rax
	orq	%r14, %rax
	cvtsi2sdq	%rax, %xmm0
	addsd	%xmm0, %xmm0
.L17:
	mulsd	.LC1(%rip), %xmm0
	leaq	.LC3(%rip), %r13
	xorl	%r15d, %r15d
	movq	%xmm0, %rbp
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC5(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movq	%r13, %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rbp, %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC6(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movq	%r13, %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	%rbp, %xmm0
	movq	%rax, %rdi
	call	_ZNSo9_M_insertIdEERSoT_@PLT
	leaq	.LC7(%rip), %rsi
	movq	%rax, %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movl	1232(%rsp), %ebp
	leaq	56(%rsp), %rdi
	imull	%ebx, %ebp
	imull	1240(%rsp), %ebp
	movslq	%ebp, %r14
	leaq	0(,%r14,4), %r13
	movq	%r13, %rsi
	call	cudaMalloc@PLT
	leaq	(%r14,%r14), %rax
	leaq	64(%rsp), %rdi
	movabsq	$4294967297, %r14
	movq	%rax, %rsi
	movq	%rax, 8(%rsp)
	call	cudaMalloc@PLT
	movq	8(%rsp), %rsi
	leaq	72(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	8(%rsp), %rsi
	leaq	80(%rsp), %rdi
	call	cudaMalloc@PLT
	movq	56(%rsp), %rdi
	movq	%r13, %rdx
	movq	%r12, %rsi
	movl	$1, %ecx
	call	cudaMemcpy@PLT
	movl	$2, %edi
	call	cuCtxSetCacheConfig@PLT
	leaq	52(%rsp), %rdi
	call	cudaGetDevice@PLT
	movl	52(%rsp), %esi
	leaq	128(%rsp), %rdi
	call	cudaGetDeviceProperties_v2@PLT
	movl	452(%rsp), %r12d
	movl	464(%rsp), %r13d
	movl	%r12d, %eax
	imull	%r13d, %eax
	movl	%eax, 44(%rsp)
.L18:
	cmpl	%r15d, %ebp
	jle	.L23
	movq	%r14, 120(%rsp)
	movl	124(%rsp), %ecx
	xorl	%r9d, %r9d
	xorl	%r8d, %r8d
	movq	%r14, 108(%rsp)
	movl	112(%rsp), %esi
	movl	%r12d, 116(%rsp)
	movq	116(%rsp), %rdx
	movl	%r13d, 104(%rsp)
	movq	104(%rsp), %rdi
	call	__cudaPushCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L19
	pushq	%r15
	.cfi_def_cfa_offset 1240
	movl	1264(%rsp), %eax
	movl	%ebx, %r8d
	pushq	%rax
	.cfi_def_cfa_offset 1248
	movl	1264(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 1256
	movl	1264(%rsp), %eax
	pushq	%rax
	.cfi_def_cfa_offset 1264
	movl	1264(%rsp), %r9d
	movq	112(%rsp), %rcx
	movq	104(%rsp), %rdx
	movq	96(%rsp), %rsi
	movq	88(%rsp), %rdi
	call	_Z62__device_stub__Z28InitialClusteringKernel_CUDAPfPtS0_S0_iiiiiiPfPtS0_S0_iiiiii
	addq	$32, %rsp
	.cfi_def_cfa_offset 1232
.L19:
	movl	44(%rsp), %eax
	addl	%eax, %r15d
	jmp	.L18
.L23:
	movq	8(%rsp), %rdx
	movq	64(%rsp), %rsi
	movl	$2, %ecx
	movq	16(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdx
	movq	72(%rsp), %rsi
	movl	$2, %ecx
	movq	24(%rsp), %rdi
	call	cudaMemcpy@PLT
	movq	8(%rsp), %rdx
	movq	80(%rsp), %rsi
	movl	$2, %ecx
	movq	32(%rsp), %rdi
	call	cudaMemcpy@PLT
	call	cudaGetLastError@PLT
	movl	%eax, %edi
	call	cudaGetErrorString@PLT
	leaq	_ZSt4cout(%rip), %rdi
	movq	%rax, %rsi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	call	cudaThreadSynchronize@PLT
	movq	56(%rsp), %rdi
	call	cudaFree@PLT
	movq	16(%rsp), %rdi
	call	cudaFree@PLT
	movq	24(%rsp), %rdi
	call	cudaFree@PLT
	movq	32(%rsp), %rdi
	call	cudaFree@PLT
	leaq	.LC8(%rip), %rsi
	leaq	_ZSt4cout(%rip), %rdi
	call	_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc@PLT
	movq	_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_@GOTPCREL(%rip), %rsi
	movq	%rax, %rdi
	call	_ZNSolsEPFRSoS_E.isra.0
	movq	1160(%rsp), %rax
	subq	%fs:40, %rax
	je	.L21
	call	__stack_chk_fail@PLT
.L21:
	addq	$1176, %rsp
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%rbp
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE3635:
	.size	initialClustering_CUDA, .-initialClustering_CUDA
	.section	.rodata.str1.1
.LC9:
	.string	"_Z28InitialClusteringKernel_CUDAPfPtS0_S0_iiiiii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB3663:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC9(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z28InitialClusteringKernel_CUDAPfPtS0_S0_iiiiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE3663:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.section	.rodata.cst8,"aM",@progbits,8
	.align 8
.LC1:
	.long	0
	.long	1051721728
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:

#include <hip/hip_runtime.h>
#include <iostream>

using namespace std;

__global__ void InitialClusteringKernel_CUDA (float* im_vals, unsigned short* max_response_r, unsigned short* max_response_c, unsigned short* max_response_z , int r, int c, int z, int scale_xy, int scale_z, int offset)
{
	int iGID = blockIdx.x * blockDim.x + threadIdx.x + offset; //global index
	
	if (iGID >= r * c * z)
		return;

	int rem = ((long)iGID) % (r*c);
	int k1 = ((int)iGID-rem) / (r*c); 
	int j1 = ((long)rem) % c;
	int i1 = (rem-j1)/c;

	int min_r = (int) max((float)(0.0),(float)(i1-scale_xy));
	int min_c = (int) max((float)(0.0),(float)(j1-scale_xy));
	int min_z = (int) max((float)(0.0),(float)(k1-scale_z));
	int max_r = (int) min((float)(r-1),(float)(i1+scale_xy));
	int max_c = (int) min((float)(c-1),(float)(j1+scale_xy));                         
	int max_z = (int) min((float)(z-1),(float)(k1+scale_z));

	//If we are running on the GPU, it makes no sense to load this big array just to save computation since seed point should be the maximum anyways
	//if(local_max_vals[(k1*r*c)+(i1*c)+j1] == 0) //if current pixel is not a seed point		
	//{
		float mx = im_vals[(min_z*r*c)+(min_r*c)+min_c];//A[r1][c1][z1];
		
		//Do not access arrays in a hot loop if you can just just do all the updates at the end, much faster to use registers
		int r_temp = min_r;
		int c_temp = min_c;
		int z_temp = min_z;	    

		float im_vals_temp;
		
		for(int i= min_r; i<= max_r; i++)
		{
			for(int j= min_c; j <= max_c; j++)
			{
				for(int k = min_z; k <= max_z; k++)
				{
					im_vals_temp = im_vals[(k*r*c)+(i*c)+j];

					if( im_vals_temp >= mx)
					{
						mx = im_vals_temp;

						r_temp = i;
						c_temp = j;
						z_temp = k;
					}
				}
			}
		} 

		max_response_r[i1 * (c * z) + j1 * z + k1] = r_temp;
		max_response_c[i1 * (c * z) + j1 * z + k1] = c_temp;
		max_response_z[i1 * (c * z) + j1 * z + k1] = z_temp;
	//}
}


extern "C"
void initialClustering_CUDA (float* im_vals, unsigned short* local_max_vals, unsigned short* max_response_r, unsigned short* max_response_c, unsigned short* max_response_z , int r, int c, int z, int scale_xy, int scale_z)
{
	cout << "Entering initialClustering_CUDA" << endl;
	
	hipError_t errorcode;

	float* dev_im_vals; 
	//unsigned short* dev_local_max_vals;
	unsigned short* dev_max_response_r;
	unsigned short* dev_max_response_c;
	unsigned short* dev_max_response_z;

	size_t free_mem, total_mem;
	hipMemGetInfo(&free_mem, &total_mem);

	cout << free_mem / (double)(1024 * 1024) << " " << total_mem / (double)(1024 * 1024) << endl;

	cout << "Allocating " << (sizeof(*im_vals) * r * c * z)/(double)(1024*1024) << " MB of memory on GPU for im_vals" << endl;
	//cout << "Allocating " << (sizeof(*local_max_vals) * r * c * z)/(double)(1024*1024) << " MB of memory on GPU for local_max_vals" << endl;
	cout << "Allocating " << (sizeof(*max_response_r) * r * c * z)/(double)(1024*1024) << " MB of memory on GPU for max_response_r" << endl;
	cout << "Allocating " << (sizeof(*max_response_c) * r * c * z)/(double)(1024*1024) << " MB of memory on GPU for max_response_c" << endl;
	cout << "Allocating " << (sizeof(*max_response_z) * r * c * z)/(double)(1024*1024) << " MB of memory on GPU for max_response_z" << endl;
	
	//Allocate memory on device
	errorcode = hipMalloc((void**) &dev_im_vals, r * c * z * sizeof(*im_vals));
	//errorcode = cudaMalloc((void**) &dev_local_max_vals, r * c * z * sizeof(*local_max_vals));
	errorcode = hipMalloc((void**) &dev_max_response_r, r * c * z * sizeof(*dev_max_response_r));
	errorcode = hipMalloc((void**) &dev_max_response_c, r * c * z * sizeof(*dev_max_response_c));
	errorcode = hipMalloc((void**) &dev_max_response_z, r * c * z * sizeof(*dev_max_response_z));

	//cout << errorcode << endl;

	//Copy host memory contents to device contents
	hipMemcpy(dev_im_vals, im_vals, r * c * z * sizeof(*im_vals), hipMemcpyHostToDevice);
	//cudaMemcpy(dev_local_max_vals, local_max_vals, r * c * z * sizeof(*local_max_vals), cudaMemcpyHostToDevice);

	//prefer 48 KB L1
	hipError_t drivererrorcode = hipCtxSetCacheConfig(hipFuncCachePreferL1);
	//cout << drivererrorcode << endl;

	int device;
	hipDeviceProp_t device_prop;

	hipGetDevice(&device);
	hipGetDeviceProperties(&device_prop, device);
	
	int threadsPerBlock = device_prop.maxThreadsDim[0];
	//int threadsPerBlock = 32;
	//int numBlocks = device_prop.multiProcessorCount;
	int numBlocks = device_prop.maxGridSize[0];
	
	//Run kernel repeatedly with offset since we cannot launch too many threads at once
	for (int k = 0; k < r * c * z; k+= numBlocks * threadsPerBlock) //Run kernel on groups of pixels at a time
	{
		InitialClusteringKernel_CUDA<<< numBlocks , threadsPerBlock >>>(dev_im_vals, dev_max_response_r, dev_max_response_c, dev_max_response_z , r, c, z, scale_xy, scale_z, k);
	}
	
	//Copy device memory contents back to host memory
	hipMemcpy(max_response_r, dev_max_response_r, r * c * z * sizeof(*max_response_r), hipMemcpyDeviceToHost);
	hipMemcpy(max_response_c, dev_max_response_c, r * c * z * sizeof(*max_response_c), hipMemcpyDeviceToHost);
	hipMemcpy(max_response_z, dev_max_response_z, r * c * z * sizeof(*max_response_z), hipMemcpyDeviceToHost);

	cout << hipGetErrorString(hipGetLastError()) << endl;
	
	//Block until all precious commands are complete
	hipDeviceSynchronize();

	hipFree(dev_im_vals);
	//cudaFree(dev_local_max_vals);
	hipFree(max_response_r);
	hipFree(max_response_c);
	hipFree(max_response_z);
	
	cout << "CUDA done" << endl;
}
	.text
	.file	"Local_Max_Clust_3D.hip"
                                        # Start of file scope inline assembly
	.globl	_ZSt21ios_base_library_initv

                                        # End of file scope inline assembly
	.globl	_Z43__device_stub__InitialClusteringKernel_CUDAPfPtS0_S0_iiiiii # -- Begin function _Z43__device_stub__InitialClusteringKernel_CUDAPfPtS0_S0_iiiiii
	.type	_Z43__device_stub__InitialClusteringKernel_CUDAPfPtS0_S0_iiiiii,@function
_Z43__device_stub__InitialClusteringKernel_CUDAPfPtS0_S0_iiiiii: # @_Z43__device_stub__InitialClusteringKernel_CUDAPfPtS0_S0_iiiiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$176, %rsp
	.cfi_def_cfa_offset 224
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	224(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	232(%rsp), %rax
	movq	%rax, 56(%rbx)
	leaq	240(%rsp), %rax
	movq	%rax, 64(%rbx)
	leaq	248(%rsp), %rax
	movq	%rax, 72(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z28InitialClusteringKernel_CUDAPfPtS0_S0_iiiiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$192, %rsp
	.cfi_adjust_cfa_offset -192
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z43__device_stub__InitialClusteringKernel_CUDAPfPtS0_S0_iiiiii, .Lfunc_end0-_Z43__device_stub__InitialClusteringKernel_CUDAPfPtS0_S0_iiiiii
	.cfi_endproc
                                        # -- End function
	.section	.rodata.cst16,"aM",@progbits,16
	.p2align	4, 0x0                          # -- Begin function initialClustering_CUDA
.LCPI1_0:
	.long	1127219200                      # 0x43300000
	.long	1160773632                      # 0x45300000
	.long	0                               # 0x0
	.long	0                               # 0x0
.LCPI1_1:
	.quad	0x4330000000000000              # double 4503599627370496
	.quad	0x4530000000000000              # double 1.9342813113834067E+25
	.section	.rodata.cst8,"aM",@progbits,8
	.p2align	3, 0x0
.LCPI1_2:
	.quad	0x3eb0000000000000              # double 9.5367431640625E-7
	.text
	.globl	initialClustering_CUDA
	.type	initialClustering_CUDA,@function
initialClustering_CUDA:                 # @initialClustering_CUDA
	.cfi_startproc
# %bb.0:
	pushq	%rbp
	.cfi_def_cfa_offset 16
	pushq	%r15
	.cfi_def_cfa_offset 24
	pushq	%r14
	.cfi_def_cfa_offset 32
	pushq	%r13
	.cfi_def_cfa_offset 40
	pushq	%r12
	.cfi_def_cfa_offset 48
	pushq	%rbx
	.cfi_def_cfa_offset 56
	subq	$1592, %rsp                     # imm = 0x638
	.cfi_def_cfa_offset 1648
	.cfi_offset %rbx, -56
	.cfi_offset %r12, -48
	.cfi_offset %r13, -40
	.cfi_offset %r14, -32
	.cfi_offset %r15, -24
	.cfi_offset %rbp, -16
	movl	%r9d, %r15d
	movq	%r8, 80(%rsp)                   # 8-byte Spill
	movq	%rcx, 72(%rsp)                  # 8-byte Spill
	movq	%rdx, 64(%rsp)                  # 8-byte Spill
	movq	%rdi, 56(%rsp)                  # 8-byte Spill
	movslq	1656(%rsp), %r13
	movslq	1648(%rsp), %r12
	movl	$_ZSt4cout, %ebx
	movl	$_ZSt4cout, %edi
	movl	$.L.str, %esi
	movl	$31, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	leaq	112(%rsp), %r14
	leaq	104(%rsp), %rbx
	movq	%r14, %rdi
	movq	%rbx, %rsi
	callq	hipMemGetInfo
	movsd	(%r14), %xmm1                   # xmm1 = mem[0],zero
	unpcklps	.LCPI1_0(%rip), %xmm1           # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
	subpd	.LCPI1_1(%rip), %xmm1
	movapd	%xmm1, %xmm0
	unpckhpd	%xmm1, %xmm0                    # xmm0 = xmm0[1],xmm1[1]
	addsd	%xmm1, %xmm0
	mulsd	.LCPI1_2(%rip), %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %r14
	movl	$.L.str.1, %esi
	movl	$1, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movsd	(%rbx), %xmm1                   # xmm1 = mem[0],zero
	unpcklps	.LCPI1_0(%rip), %xmm1           # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
	subpd	.LCPI1_1(%rip), %xmm1
	movapd	%xmm1, %xmm0
	unpckhpd	%xmm1, %xmm0                    # xmm0 = xmm0[1],xmm1[1]
	addsd	%xmm1, %xmm0
	mulsd	.LCPI1_2(%rip), %xmm0
	movq	%r14, %rdi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movq	(%rax), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$_ZSt4cout, %edi
	movl	$.L.str.2, %esi
	movl	$11, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movslq	%r15d, %rax
	movq	%r13, %r14
	imulq	%r12, %r14
	imulq	%rax, %r14
	leaq	(,%r14,4), %rax
	movq	%rax, %xmm1
	punpckldq	.LCPI1_0(%rip), %xmm1   # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
	subpd	.LCPI1_1(%rip), %xmm1
	movapd	%xmm1, %xmm0
	unpckhpd	%xmm1, %xmm0                    # xmm0 = xmm0[1],xmm1[1]
	addsd	%xmm1, %xmm0
	mulsd	.LCPI1_2(%rip), %xmm0
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movl	$.L.str.3, %esi
	movl	$32, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	(%rbx), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$_ZSt4cout, %edi
	movl	$.L.str.2, %esi
	movl	$11, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	addq	%r14, %r14
	movq	%r14, %xmm1
	punpckldq	.LCPI1_0(%rip), %xmm1   # xmm1 = xmm1[0],mem[0],xmm1[1],mem[1]
	subpd	.LCPI1_1(%rip), %xmm1
	movapd	%xmm1, %xmm0
	unpckhpd	%xmm1, %xmm0                    # xmm0 = xmm0[1],xmm1[1]
	addsd	%xmm1, %xmm0
	mulsd	.LCPI1_2(%rip), %xmm0
	movapd	%xmm0, 32(%rsp)                 # 16-byte Spill
	movl	$_ZSt4cout, %edi
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movl	$.L.str.4, %esi
	movl	$39, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	(%rbx), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$_ZSt4cout, %edi
	movl	$.L.str.2, %esi
	movl	$11, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movaps	32(%rsp), %xmm0                 # 16-byte Reload
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movl	$.L.str.5, %esi
	movl	$39, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	(%rbx), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movl	$_ZSt4cout, %edi
	movl	$.L.str.2, %esi
	movl	$11, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movl	$_ZSt4cout, %edi
	movaps	32(%rsp), %xmm0                 # 16-byte Reload
	callq	_ZNSo9_M_insertIdEERSoT_
	movq	%rax, %rbx
	movl	$.L.str.6, %esi
	movl	$39, %edx
	movq	%rax, %rdi
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	(%rbx), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movq	%rbx, %rdi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	movq	%r12, 88(%rsp)                  # 8-byte Spill
	movl	%r12d, %ebp
	movl	%r15d, 32(%rsp)                 # 4-byte Spill
	imull	%r15d, %ebp
	movq	%r13, %r12
	imull	%r13d, %ebp
	movslq	%ebp, %rbx
	leaq	(,%rbx,4), %r14
	leaq	24(%rsp), %r15
	movq	%r15, %rdi
	movq	%r14, %rsi
	callq	hipMalloc
	leaq	(%rbx,%rbx), %r13
	leaq	16(%rsp), %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	leaq	8(%rsp), %rdi
	movq	%r13, %rsi
	callq	hipMalloc
	movq	%rsp, %rdi
	movq	%r13, 48(%rsp)                  # 8-byte Spill
	movq	%r13, %rsi
	callq	hipMalloc
	movq	(%r15), %rdi
	movq	56(%rsp), %rsi                  # 8-byte Reload
	movq	%r14, %rdx
	movl	$1, %ecx
	callq	hipMemcpy
	movl	$2, %edi
	callq	hipCtxSetCacheConfig
	leaq	100(%rsp), %r14
	movq	%r14, %rdi
	callq	hipGetDevice
	movl	(%r14), %esi
	leaq	120(%rsp), %rdi
	callq	hipGetDevicePropertiesR0600
	testl	%ebx, %ebx
	jle	.LBB1_5
# %bb.1:                                # %.lr.ph
	movl	444(%rsp), %r15d
	movl	456(%rsp), %r14d
	movq	%r15, %r13
	imull	%r14d, %r15d
	btsq	$32, %r14
	btsq	$32, %r13
	xorl	%ebx, %ebx
.LBB1_2:                                # =>This Inner Loop Header: Depth=1
	movq	%r14, %rdi
	movl	$1, %esi
	movq	%r13, %rdx
	movl	$1, %ecx
	xorl	%r8d, %r8d
	xorl	%r9d, %r9d
	callq	__hipPushCallConfiguration
	testl	%eax, %eax
	jne	.LBB1_4
# %bb.3:                                #   in Loop: Header=BB1_2 Depth=1
	movq	24(%rsp), %rdi
	movq	16(%rsp), %rsi
	movq	8(%rsp), %rdx
	movq	(%rsp), %rcx
	movl	32(%rsp), %r8d                  # 4-byte Reload
	movq	88(%rsp), %r9                   # 8-byte Reload
                                        # kill: def $r9d killed $r9d killed $r9
	pushq	%rbx
	.cfi_adjust_cfa_offset 8
	movl	1680(%rsp), %eax
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	movl	1680(%rsp), %eax
	pushq	%rax
	.cfi_adjust_cfa_offset 8
	pushq	%r12
	.cfi_adjust_cfa_offset 8
	callq	_Z43__device_stub__InitialClusteringKernel_CUDAPfPtS0_S0_iiiiii
	addq	$32, %rsp
	.cfi_adjust_cfa_offset -32
.LBB1_4:                                #   in Loop: Header=BB1_2 Depth=1
	addl	%r15d, %ebx
	cmpl	%ebp, %ebx
	jl	.LBB1_2
.LBB1_5:                                # %._crit_edge
	movq	16(%rsp), %rsi
	movq	64(%rsp), %r12                  # 8-byte Reload
	movq	%r12, %rdi
	movq	48(%rsp), %rbx                  # 8-byte Reload
	movq	%rbx, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	8(%rsp), %rsi
	movq	72(%rsp), %r15                  # 8-byte Reload
	movq	%r15, %rdi
	movq	%rbx, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	movq	(%rsp), %rsi
	movq	80(%rsp), %r14                  # 8-byte Reload
	movq	%r14, %rdi
	movq	%rbx, %rdx
	movl	$2, %ecx
	callq	hipMemcpy
	callq	hipGetLastError
	movl	%eax, %edi
	callq	hipGetErrorString
	testq	%rax, %rax
	je	.LBB1_6
# %bb.7:
	movq	%rax, %rbx
	movq	%rax, %rdi
	callq	strlen
	movl	$_ZSt4cout, %edi
	movq	%rbx, %rsi
	movq	%rax, %rdx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	jmp	.LBB1_8
.LBB1_6:
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rax
	leaq	_ZSt4cout(%rax), %rdi
	movl	32(%rdi), %esi
	orl	$1, %esi
	callq	_ZNSt9basic_iosIcSt11char_traitsIcEE5clearESt12_Ios_Iostate
.LBB1_8:                                # %_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc.exit
	movq	_ZSt4cout(%rip), %rax
	movl	$_ZSt4cout, %ebx
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	callq	hipDeviceSynchronize
	movq	24(%rsp), %rdi
	callq	hipFree
	movq	%r12, %rdi
	callq	hipFree
	movq	%r15, %rdi
	callq	hipFree
	movq	%r14, %rdi
	callq	hipFree
	movl	$_ZSt4cout, %edi
	movl	$.L.str.7, %esi
	movl	$9, %edx
	callq	_ZSt16__ostream_insertIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_PKS3_l
	movq	_ZSt4cout(%rip), %rax
	movq	-24(%rax), %rdi
	addq	%rbx, %rdi
	movl	$10, %esi
	callq	_ZNKSt9basic_iosIcSt11char_traitsIcEE5widenEc
	movsbl	%al, %esi
	movl	$_ZSt4cout, %edi
	callq	_ZNSo3putEc
	movq	%rax, %rdi
	callq	_ZNSo5flushEv
	addq	$1592, %rsp                     # imm = 0x638
	.cfi_def_cfa_offset 56
	popq	%rbx
	.cfi_def_cfa_offset 48
	popq	%r12
	.cfi_def_cfa_offset 40
	popq	%r13
	.cfi_def_cfa_offset 32
	popq	%r14
	.cfi_def_cfa_offset 24
	popq	%r15
	.cfi_def_cfa_offset 16
	popq	%rbp
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end1:
	.size	initialClustering_CUDA, .Lfunc_end1-initialClustering_CUDA
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB2_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB2_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z28InitialClusteringKernel_CUDAPfPtS0_S0_iiiiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end2:
	.size	__hip_module_ctor, .Lfunc_end2-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB3_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB3_2:
	retq
.Lfunc_end3:
	.size	__hip_module_dtor, .Lfunc_end3-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z28InitialClusteringKernel_CUDAPfPtS0_S0_iiiiii,@object # @_Z28InitialClusteringKernel_CUDAPfPtS0_S0_iiiiii
	.section	.rodata,"a",@progbits
	.globl	_Z28InitialClusteringKernel_CUDAPfPtS0_S0_iiiiii
	.p2align	3, 0x0
_Z28InitialClusteringKernel_CUDAPfPtS0_S0_iiiiii:
	.quad	_Z43__device_stub__InitialClusteringKernel_CUDAPfPtS0_S0_iiiiii
	.size	_Z28InitialClusteringKernel_CUDAPfPtS0_S0_iiiiii, 8

	.type	.L.str,@object                  # @.str
	.section	.rodata.str1.1,"aMS",@progbits,1
.L.str:
	.asciz	"Entering initialClustering_CUDA"
	.size	.L.str, 32

	.type	.L.str.1,@object                # @.str.1
.L.str.1:
	.asciz	" "
	.size	.L.str.1, 2

	.type	.L.str.2,@object                # @.str.2
.L.str.2:
	.asciz	"Allocating "
	.size	.L.str.2, 12

	.type	.L.str.3,@object                # @.str.3
.L.str.3:
	.asciz	" MB of memory on GPU for im_vals"
	.size	.L.str.3, 33

	.type	.L.str.4,@object                # @.str.4
.L.str.4:
	.asciz	" MB of memory on GPU for max_response_r"
	.size	.L.str.4, 40

	.type	.L.str.5,@object                # @.str.5
.L.str.5:
	.asciz	" MB of memory on GPU for max_response_c"
	.size	.L.str.5, 40

	.type	.L.str.6,@object                # @.str.6
.L.str.6:
	.asciz	" MB of memory on GPU for max_response_z"
	.size	.L.str.6, 40

	.type	.L.str.7,@object                # @.str.7
.L.str.7:
	.asciz	"CUDA done"
	.size	.L.str.7, 10

	.type	.L__unnamed_1,@object           # @0
.L__unnamed_1:
	.asciz	"_Z28InitialClusteringKernel_CUDAPfPtS0_S0_iiiiii"
	.size	.L__unnamed_1, 49

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z43__device_stub__InitialClusteringKernel_CUDAPfPtS0_S0_iiiiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z28InitialClusteringKernel_CUDAPfPtS0_S0_iiiiii
	.addrsig_sym _ZSt4cout
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z28InitialClusteringKernel_CUDAPfPtS0_S0_iiiiii ; -- Begin function _Z28InitialClusteringKernel_CUDAPfPtS0_S0_iiiiii
	.globl	_Z28InitialClusteringKernel_CUDAPfPtS0_S0_iiiiii
	.p2align	8
	.type	_Z28InitialClusteringKernel_CUDAPfPtS0_S0_iiiiii,@function
_Z28InitialClusteringKernel_CUDAPfPtS0_S0_iiiiii: ; @_Z28InitialClusteringKernel_CUDAPfPtS0_S0_iiiiii
; %bb.0:
	s_clause 0x2
	s_load_b32 s4, s[0:1], 0x44
	s_load_b64 s[2:3], s[0:1], 0x30
	s_load_b128 s[16:19], s[0:1], 0x20
	s_waitcnt lgkmcnt(0)
	s_and_b32 s4, s4, 0xffff
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_mul_i32 s15, s15, s4
	v_add3_u32 v0, s15, s3, v0
	s_mul_i32 s3, s17, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_mul_i32 s4, s3, s18
	s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_i32_e32 vcc_lo, s4, v0
	s_and_saveexec_b32 s4, vcc_lo
	s_cbranch_execz .LBB0_16
; %bb.1:
	s_ashr_i32 s4, s3, 31
	v_ashrrev_i32_e32 v3, 31, v0
	s_add_i32 s5, s3, s4
	s_mov_b32 s13, 0
	s_xor_b32 s5, s5, s4
	s_mov_b32 s12, exec_lo
	v_cvt_f32_u32_e32 v1, s5
	s_sub_i32 s6, 0, s5
	v_add_nc_u32_e32 v4, v0, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_rcp_iflag_f32_e32 v1, v1
	v_xor_b32_e32 v4, v4, v3
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v1, 0x4f7ffffe, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_u32_f32_e32 v1, v1
	v_mul_lo_u32 v2, s6, v1
	s_ashr_i32 s6, s17, 31
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_add_i32 s7, s17, s6
	s_xor_b32 s7, s7, s6
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	s_sub_i32 s8, 0, s7
	v_mul_hi_u32 v2, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_nc_u32_e32 v1, v1, v2
	v_mul_hi_u32 v2, v4, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v2, v2, s5
	v_sub_nc_u32_e32 v2, v4, v2
	v_cvt_f32_u32_e32 v4, s7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_subrev_nc_u32_e32 v5, s5, v2
	v_cmp_le_u32_e32 vcc_lo, s5, v2
	v_rcp_iflag_f32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v2, v2, v5, vcc_lo
	v_subrev_nc_u32_e32 v5, s5, v2
	v_cmp_le_u32_e32 vcc_lo, s5, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cndmask_b32_e32 v2, v2, v5, vcc_lo
	v_xor_b32_e32 v2, v2, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v6, v2, v3
	v_ashrrev_i32_e32 v2, 31, v6
	s_delay_alu instid0(TRANS32_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_f32_e32 v4, 0x4f7ffffe, v4
	v_sub_nc_u32_e32 v0, v0, v6
	v_cvt_u32_f32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_lo_u32 v5, s8, v4
	v_mul_hi_u32 v3, v4, v5
	v_add_nc_u32_e32 v5, v6, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v4, v3
	v_xor_b32_e32 v4, v5, v2
	v_ashrrev_i32_e32 v5, 31, v0
	v_xor_b32_e32 v2, s6, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v3, v4, v3
	v_mul_lo_u32 v7, v3, s7
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v4, v4, v7
	v_subrev_nc_u32_e32 v9, s7, v4
	v_cmp_le_u32_e32 vcc_lo, s7, v4
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_dual_cndmask_b32 v4, v4, v9 :: v_dual_add_nc_u32 v7, 1, v3
	v_dual_cndmask_b32 v3, v3, v7 :: v_dual_add_nc_u32 v0, v0, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s7, v4
	v_xor_b32_e32 v0, v0, v5
	v_xor_b32_e32 v5, s4, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mul_hi_u32 v1, v0, v1
	v_mul_lo_u32 v8, v1, s5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v0, v0, v8
	v_subrev_nc_u32_e32 v9, s5, v0
	v_add_nc_u32_e32 v7, 1, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v3, v3, v7 :: v_dual_add_nc_u32 v8, 1, v1
	v_cmp_le_u32_e32 vcc_lo, s5, v0
	v_xor_b32_e32 v3, v3, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_cndmask_b32 v1, v1, v8 :: v_dual_cndmask_b32 v0, v0, v9
	v_sub_nc_u32_e32 v2, v3, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_cmp_le_u32_e32 vcc_lo, s5, v0
	s_load_b256 s[4:11], s[0:1], 0x0
	s_add_i32 s0, s16, -1
	v_subrev_nc_u32_e32 v3, s19, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v3, v3
	v_dual_max_f32 v3, 0, v3 :: v_dual_add_nc_u32 v4, 1, v1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_cndmask_b32_e32 v0, v1, v4, vcc_lo
	v_mul_lo_u32 v1, v2, s17
	v_xor_b32_e32 v0, v0, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v0, v0, v5
	v_sub_nc_u32_e32 v5, v6, v1
	v_add_nc_u32_e32 v1, s19, v2
	v_cvt_f32_i32_e32 v2, s0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_subrev_nc_u32_e32 v4, s2, v0
	v_subrev_nc_u32_e32 v7, s19, v5
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f32_i32_e32 v1, v1
	v_cvt_f32_i32_e32 v4, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_f32_i32_e32 v7, v7
	v_min_f32_e32 v1, v2, v1
	v_cvt_i32_f32_e32 v2, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_dual_max_f32 v3, 0, v4 :: v_dual_max_f32 v4, 0, v7
	v_cvt_i32_f32_e32 v8, v1
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cvt_i32_f32_e32 v7, v3
	v_cvt_i32_f32_e32 v1, v4
	s_delay_alu instid0(VALU_DEP_3)
	v_cmpx_le_i32_e64 v2, v8
	s_cbranch_execz .LBB0_15
; %bb.2:                                ; %.preheader114.lr.ph
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[9:10], null, v7, s16, v[2:3]
	s_add_i32 s0, s17, -1
	v_mov_b32_e32 v12, v2
	v_dual_mov_b32 v14, v7 :: v_dual_mov_b32 v13, v1
	v_mad_u64_u32 v[3:4], null, v9, s17, v[1:2]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v4, 31, v3
	v_lshlrev_b64 v[9:10], 2, v[3:4]
	v_add_nc_u32_e32 v4, s19, v5
	v_add_nc_u32_e32 v5, s2, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_cvt_f32_i32_e32 v4, v4
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v9, vcc_lo, s4, v9
	v_add_co_ci_u32_e32 v10, vcc_lo, s5, v10, vcc_lo
	v_cvt_f32_i32_e32 v5, v5
	global_load_b32 v9, v[9:10], off
	v_cvt_f32_i32_e32 v10, s0
	s_add_i32 s0, s18, -1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_cvt_f32_i32_e32 v11, s0
	v_dual_min_f32 v4, v10, v4 :: v_dual_min_f32 v5, v11, v5
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_i32_f32_e32 v10, v4
	v_cvt_i32_f32_e32 v11, v5
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_le_i32_e32 vcc_lo, v1, v10
	v_cmp_le_i32_e64 s0, v7, v11
.LBB0_3:                                ; %.preheader114
                                        ; =>This Loop Header: Depth=1
                                        ;     Child Loop BB0_5 Depth 2
                                        ;       Child Loop BB0_7 Depth 3
	s_and_saveexec_b32 s2, vcc_lo
	s_cbranch_execz .LBB0_13
; %bb.4:                                ; %.preheader.preheader
                                        ;   in Loop: Header=BB0_3 Depth=1
	v_dual_mov_b32 v15, v3 :: v_dual_mov_b32 v16, v1
	s_mov_b32 s14, 0
.LBB0_5:                                ; %.preheader
                                        ;   Parent Loop BB0_3 Depth=1
                                        ; =>  This Loop Header: Depth=2
                                        ;       Child Loop BB0_7 Depth 3
	s_and_saveexec_b32 s15, s0
	s_cbranch_execz .LBB0_11
; %bb.6:                                ; %.lr.ph.preheader
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_delay_alu instid0(VALU_DEP_1)
	v_mov_b32_e32 v4, v15
	v_mov_b32_e32 v17, v7
	s_mov_b32 s16, 0
.LBB0_7:                                ; %.lr.ph
                                        ;   Parent Loop BB0_3 Depth=1
                                        ;     Parent Loop BB0_5 Depth=2
                                        ; =>    This Inner Loop Header: Depth=3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_ashrrev_i32_e32 v5, 31, v4
	s_mov_b32 s19, exec_lo
	v_lshlrev_b64 v[18:19], 2, v[4:5]
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_add_co_u32 v18, s1, s4, v18
	v_add_co_ci_u32_e64 v19, s1, s5, v19, s1
	global_load_b32 v5, v[18:19], off
	s_waitcnt vmcnt(0)
	v_cmpx_ge_f32_e32 v5, v9
; %bb.8:                                ;   in Loop: Header=BB0_7 Depth=3
	v_dual_mov_b32 v9, v5 :: v_dual_mov_b32 v12, v2
	v_dual_mov_b32 v13, v16 :: v_dual_mov_b32 v14, v17
; %bb.9:                                ;   in Loop: Header=BB0_7 Depth=3
	s_or_b32 exec_lo, exec_lo, s19
	v_add_nc_u32_e32 v5, 1, v17
	v_cmp_ge_i32_e64 s1, v17, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_dual_mov_b32 v17, v5 :: v_dual_add_nc_u32 v4, s3, v4
	s_or_b32 s16, s1, s16
	s_delay_alu instid0(SALU_CYCLE_1)
	s_and_not1_b32 exec_lo, exec_lo, s16
	s_cbranch_execnz .LBB0_7
; %bb.10:                               ; %Flow
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_or_b32 exec_lo, exec_lo, s16
.LBB0_11:                               ; %Flow178
                                        ;   in Loop: Header=BB0_5 Depth=2
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s15
	v_add_nc_u32_e32 v4, 1, v16
	v_cmp_ge_i32_e64 s1, v16, v10
	v_dual_mov_b32 v16, v4 :: v_dual_add_nc_u32 v15, 1, v15
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s14, s1, s14
	s_and_not1_b32 exec_lo, exec_lo, s14
	s_cbranch_execnz .LBB0_5
; %bb.12:                               ; %Flow179
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_or_b32 exec_lo, exec_lo, s14
.LBB0_13:                               ; %Flow180
                                        ;   in Loop: Header=BB0_3 Depth=1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	s_or_b32 exec_lo, exec_lo, s2
	v_add_nc_u32_e32 v4, 1, v2
	v_cmp_ge_i32_e64 s1, v2, v8
	v_dual_mov_b32 v2, v4 :: v_dual_add_nc_u32 v3, s17, v3
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(SALU_CYCLE_1)
	s_or_b32 s13, s1, s13
	s_and_not1_b32 exec_lo, exec_lo, s13
	s_cbranch_execnz .LBB0_3
; %bb.14:                               ; %Flow181
	s_or_b32 exec_lo, exec_lo, s13
	v_dual_mov_b32 v7, v14 :: v_dual_mov_b32 v2, v12
	v_mov_b32_e32 v1, v13
.LBB0_15:                               ; %Flow182
	s_or_b32 exec_lo, exec_lo, s12
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_mad_u64_u32 v[3:4], null, v6, s18, v[0:1]
	v_ashrrev_i32_e32 v4, 31, v3
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_lshlrev_b64 v[3:4], 1, v[3:4]
	s_waitcnt lgkmcnt(0)
	v_add_co_u32 v5, vcc_lo, s6, v3
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v4, vcc_lo
	v_add_co_u32 v8, vcc_lo, s8, v3
	s_waitcnt vmcnt(0)
	v_add_co_ci_u32_e32 v9, vcc_lo, s9, v4, vcc_lo
	v_add_co_u32 v3, vcc_lo, s10, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, s11, v4, vcc_lo
	global_store_b16 v[5:6], v2, off
	global_store_b16 v[8:9], v1, off
	global_store_b16 v[3:4], v7, off
.LBB0_16:
	s_nop 0
	s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z28InitialClusteringKernel_CUDAPfPtS0_S0_iiiiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 312
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 20
		.amdhsa_next_free_sgpr 20
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z28InitialClusteringKernel_CUDAPfPtS0_S0_iiiiii, .Lfunc_end0-_Z28InitialClusteringKernel_CUDAPfPtS0_S0_iiiiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 1192
; NumSgprs: 22
; NumVgprs: 20
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 22
; NumVGPRsForWavesPerEU: 20
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         8
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         16
        .size:           8
        .value_kind:     global_buffer
      - .address_space:  global
        .offset:         24
        .size:           8
        .value_kind:     global_buffer
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         44
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     by_value
      - .offset:         52
        .size:           4
        .value_kind:     by_value
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         60
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         64
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         68
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         70
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         72
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         74
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         76
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         78
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         112
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         120
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 312
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z28InitialClusteringKernel_CUDAPfPtS0_S0_iiiiii
    .private_segment_fixed_size: 0
    .sgpr_count:     22
    .sgpr_spill_count: 0
    .symbol:         _Z28InitialClusteringKernel_CUDAPfPtS0_S0_iiiiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     20
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
