#include "includes.h"
__device__ void exchange(float &a, float &b){
float temp = a;
a = b;
b = temp;
}
__global__ void flip_3D(float* coords, size_t dim_z, size_t dim_y, size_t dim_x, int do_z, int do_y, int do_x){
size_t index = blockIdx.x * blockDim.x + threadIdx.x;
size_t total = dim_x * dim_y * dim_z;
size_t total_xy = dim_x * dim_y;
size_t id_x = index % dim_x;
size_t id_y = (index / dim_x) % dim_x;
size_t id_z = index / (dim_x * dim_y);
if(index < total){
if(do_x && id_x < (dim_x / 2)){
exchange(coords[2 * total + id_z * total_xy + id_y * dim_x + id_x],
coords[2 * total + id_z * total_xy + id_y * dim_x + dim_x-1 - id_x]);
__syncthreads();
}
if(do_y && id_y < (dim_y / 2)){
exchange(coords[total + id_z * total_xy + id_y * dim_x + id_x],
coords[total + id_z * total_xy + (dim_y-1 - id_y) * dim_x + id_x]);
__syncthreads();
}
if(do_z && id_z < (dim_z / 2)){
exchange(coords[id_z * total_xy + id_y * dim_x + id_x],
coords[(dim_z-1 -id_z) * total_xy + id_y * dim_x + id_x]);
__syncthreads();
}
}
}
	.file	"tmpxft_0023ef34_00000000-6_flip_3D.cudafe1.cpp"
	.text
#APP

#NO_APP
	.type	_ZL26__cudaUnregisterBinaryUtilv, @function
_ZL26__cudaUnregisterBinaryUtilv:
.LFB2011:
	.cfi_startproc
	endbr64
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	jmp	__cudaUnregisterFatBinary@PLT
	.cfi_endproc
.LFE2011:
	.size	_ZL26__cudaUnregisterBinaryUtilv, .-_ZL26__cudaUnregisterBinaryUtilv
	.globl	_Z8exchangeRfS_
	.type	_Z8exchangeRfS_, @function
_Z8exchangeRfS_:
.LFB2008:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	popq	%rax
	.cfi_def_cfa_offset 8
	subq	$24, %rsp
	.cfi_def_cfa_offset 32
	movl	$1, 12(%rsp)
	movl	12(%rsp), %edi
	call	exit@PLT
	.cfi_endproc
.LFE2008:
	.size	_Z8exchangeRfS_, .-_Z8exchangeRfS_
	.globl	_Z32__device_stub__Z7flip_3DPfmmmiiiPfmmmiii
	.type	_Z32__device_stub__Z7flip_3DPfmmmiiiPfmmmiii, @function
_Z32__device_stub__Z7flip_3DPfmmmiiiPfmmmiii:
.LFB2033:
	.cfi_startproc
	endbr64
	subq	$184, %rsp
	.cfi_def_cfa_offset 192
	movq	%rdi, 40(%rsp)
	leaq	64(%rsp), %rdi
	movq	%rsi, 32(%rsp)
	leaq	76(%rsp), %rsi
	movq	%rdx, 24(%rsp)
	leaq	48(%rsp), %rdx
	movq	%rcx, 16(%rsp)
	leaq	56(%rsp), %rcx
	movl	%r8d, 12(%rsp)
	movl	%r9d, 8(%rsp)
	movq	%fs:40, %rax
	movq	%rax, 168(%rsp)
	xorl	%eax, %eax
	leaq	40(%rsp), %rax
	movl	$1, 72(%rsp)
	movq	%rax, 112(%rsp)
	leaq	32(%rsp), %rax
	movq	%rax, 120(%rsp)
	leaq	24(%rsp), %rax
	movq	%rax, 128(%rsp)
	leaq	16(%rsp), %rax
	movq	%rax, 136(%rsp)
	leaq	12(%rsp), %rax
	movq	%rax, 144(%rsp)
	leaq	8(%rsp), %rax
	movq	%rax, 152(%rsp)
	leaq	192(%rsp), %rax
	movq	%rax, 160(%rsp)
	movabsq	$4294967297, %rax
	movq	%rax, 64(%rsp)
	movq	%rax, 76(%rsp)
	movl	$1, 84(%rsp)
	call	__cudaPopCallConfiguration@PLT
	testl	%eax, %eax
	jne	.L4
	pushq	56(%rsp)
	.cfi_def_cfa_offset 200
	leaq	_Z7flip_3DPfmmmiii(%rip), %rdi
	pushq	56(%rsp)
	.cfi_def_cfa_offset 208
	movq	92(%rsp), %rcx
	movl	100(%rsp), %r8d
	movq	80(%rsp), %rsi
	movl	88(%rsp), %edx
	leaq	128(%rsp), %r9
	call	cudaLaunchKernel@PLT
	popq	%rax
	.cfi_def_cfa_offset 200
	popq	%rdx
	.cfi_def_cfa_offset 192
.L4:
	movq	168(%rsp), %rax
	subq	%fs:40, %rax
	je	.L6
	call	__stack_chk_fail@PLT
.L6:
	addq	$184, %rsp
	.cfi_def_cfa_offset 8
	ret
	.cfi_endproc
.LFE2033:
	.size	_Z32__device_stub__Z7flip_3DPfmmmiiiPfmmmiii, .-_Z32__device_stub__Z7flip_3DPfmmmiiiPfmmmiii
	.globl	_Z7flip_3DPfmmmiii
	.type	_Z7flip_3DPfmmmiii, @function
_Z7flip_3DPfmmmiii:
.LFB2034:
	.cfi_startproc
	endbr64
	jmp	_Z32__device_stub__Z7flip_3DPfmmmiiiPfmmmiii
	.cfi_endproc
.LFE2034:
	.size	_Z7flip_3DPfmmmiii, .-_Z7flip_3DPfmmmiii
	.section	.rodata.str1.1,"aMS",@progbits,1
.LC0:
	.string	"_Z7flip_3DPfmmmiii"
	.section	.text.startup,"ax",@progbits
	.type	_ZL24__sti____cudaRegisterAllv, @function
_ZL24__sti____cudaRegisterAllv:
.LFB2036:
	.cfi_startproc
	endbr64
	pushq	%rax
	.cfi_def_cfa_offset 16
	leaq	_ZL15__fatDeviceText(%rip), %rdi
	call	__cudaRegisterFatBinary@PLT
	pushq	$0
	.cfi_def_cfa_offset 24
	xorl	%r9d, %r9d
	orl	$-1, %r8d
	pushq	$0
	.cfi_def_cfa_offset 32
	leaq	.LC0(%rip), %rdx
	movq	%rax, %rdi
	leaq	_Z7flip_3DPfmmmiii(%rip), %rsi
	pushq	$0
	.cfi_def_cfa_offset 40
	movq	%rdx, %rcx
	pushq	$0
	.cfi_def_cfa_offset 48
	movq	%rax, _ZL20__cudaFatCubinHandle(%rip)
	call	__cudaRegisterFunction@PLT
	movq	_ZL20__cudaFatCubinHandle(%rip), %rdi
	addq	$32, %rsp
	.cfi_def_cfa_offset 16
	call	__cudaRegisterFatBinaryEnd@PLT
	leaq	_ZL26__cudaUnregisterBinaryUtilv(%rip), %rdi
	popq	%rdx
	.cfi_def_cfa_offset 8
	jmp	atexit@PLT
	.cfi_endproc
.LFE2036:
	.size	_ZL24__sti____cudaRegisterAllv, .-_ZL24__sti____cudaRegisterAllv
	.section	.init_array,"aw"
	.align 8
	.quad	_ZL24__sti____cudaRegisterAllv
	.section	.nvFatBinSegment,"aw"
	.align 8
	.type	_ZL15__fatDeviceText, @object
	.size	_ZL15__fatDeviceText, 24
_ZL15__fatDeviceText:
	.long	1180844977
	.long	1
	.quad	fatbinData
	.quad	0
	.local	_ZL20__cudaFatCubinHandle
	.comm	_ZL20__cudaFatCubinHandle,8,8
	.ident	"GCC: (Ubuntu 13.3.0-6ubuntu2~24.04) 13.3.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	1f - 0f
	.long	4f - 1f
	.long	5
0:
	.string	"GNU"
1:
	.align 8
	.long	0xc0000002
	.long	3f - 2f
2:
	.long	0x3
3:
	.align 8
4:


#include <hip/hip_runtime.h>
#include "includes.h"
__device__ void exchange(float &a, float &b){
float temp = a;
a = b;
b = temp;
}
__global__ void flip_3D(float* coords, size_t dim_z, size_t dim_y, size_t dim_x, int do_z, int do_y, int do_x){
size_t index = blockIdx.x * blockDim.x + threadIdx.x;
size_t total = dim_x * dim_y * dim_z;
size_t total_xy = dim_x * dim_y;
size_t id_x = index % dim_x;
size_t id_y = (index / dim_x) % dim_x;
size_t id_z = index / (dim_x * dim_y);
if(index < total){
if(do_x && id_x < (dim_x / 2)){
exchange(coords[2 * total + id_z * total_xy + id_y * dim_x + id_x],
coords[2 * total + id_z * total_xy + id_y * dim_x + dim_x-1 - id_x]);
__syncthreads();
}
if(do_y && id_y < (dim_y / 2)){
exchange(coords[total + id_z * total_xy + id_y * dim_x + id_x],
coords[total + id_z * total_xy + (dim_y-1 - id_y) * dim_x + id_x]);
__syncthreads();
}
if(do_z && id_z < (dim_z / 2)){
exchange(coords[id_z * total_xy + id_y * dim_x + id_x],
coords[(dim_z-1 -id_z) * total_xy + id_y * dim_x + id_x]);
__syncthreads();
}
}
}
	.text
	.file	"flip_3D.hip"
	.globl	_Z22__device_stub__flip_3DPfmmmiii # -- Begin function _Z22__device_stub__flip_3DPfmmmiii
	.type	_Z22__device_stub__flip_3DPfmmmiii,@function
_Z22__device_stub__flip_3DPfmmmiii:     # @_Z22__device_stub__flip_3DPfmmmiii
	.cfi_startproc
# %bb.0:
	pushq	%r15
	.cfi_def_cfa_offset 16
	pushq	%r14
	.cfi_def_cfa_offset 24
	pushq	%r13
	.cfi_def_cfa_offset 32
	pushq	%r12
	.cfi_def_cfa_offset 40
	pushq	%rbx
	.cfi_def_cfa_offset 48
	subq	$160, %rsp
	.cfi_def_cfa_offset 208
	.cfi_offset %rbx, -48
	.cfi_offset %r12, -40
	.cfi_offset %r13, -32
	.cfi_offset %r14, -24
	.cfi_offset %r15, -16
	leaq	56(%rsp), %rax
	movq	%rdi, (%rax)
	leaq	48(%rsp), %rdi
	movq	%rsi, (%rdi)
	leaq	40(%rsp), %rsi
	movq	%rdx, (%rsi)
	leaq	32(%rsp), %rdx
	movq	%rcx, (%rdx)
	leaq	12(%rsp), %rcx
	movl	%r8d, (%rcx)
	leaq	8(%rsp), %r8
	movl	%r9d, (%r8)
	leaq	96(%rsp), %rbx
	movq	%rax, (%rbx)
	movq	%rdi, 8(%rbx)
	movq	%rsi, 16(%rbx)
	movq	%rdx, 24(%rbx)
	movq	%rcx, 32(%rbx)
	movq	%r8, 40(%rbx)
	leaq	208(%rsp), %rax
	movq	%rax, 48(%rbx)
	leaq	80(%rsp), %r14
	leaq	64(%rsp), %r15
	leaq	24(%rsp), %r12
	leaq	16(%rsp), %r13
	movq	%r14, %rdi
	movq	%r15, %rsi
	movq	%r12, %rdx
	movq	%r13, %rcx
	callq	__hipPopCallConfiguration
	movq	(%r14), %rsi
	movl	8(%r14), %edx
	movq	(%r15), %rcx
	movl	8(%r15), %r8d
	movl	$_Z7flip_3DPfmmmiii, %edi
	movq	%rbx, %r9
	pushq	(%r13)
	.cfi_adjust_cfa_offset 8
	pushq	(%r12)
	.cfi_adjust_cfa_offset 8
	callq	hipLaunchKernel
	addq	$176, %rsp
	.cfi_adjust_cfa_offset -176
	popq	%rbx
	.cfi_def_cfa_offset 40
	popq	%r12
	.cfi_def_cfa_offset 32
	popq	%r13
	.cfi_def_cfa_offset 24
	popq	%r14
	.cfi_def_cfa_offset 16
	popq	%r15
	.cfi_def_cfa_offset 8
	retq
.Lfunc_end0:
	.size	_Z22__device_stub__flip_3DPfmmmiii, .Lfunc_end0-_Z22__device_stub__flip_3DPfmmmiii
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_ctor
	.type	__hip_module_ctor,@function
__hip_module_ctor:                      # @__hip_module_ctor
	.cfi_startproc
# %bb.0:
	subq	$40, %rsp
	.cfi_def_cfa_offset 48
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	jne	.LBB1_2
# %bb.1:
	movl	$__hip_fatbin_wrapper, %edi
	callq	__hipRegisterFatBinary
	movq	%rax, %rdi
	movq	%rax, __hip_gpubin_handle(%rip)
.LBB1_2:
	xorps	%xmm0, %xmm0
	movups	%xmm0, 16(%rsp)
	movups	%xmm0, (%rsp)
	movl	$_Z7flip_3DPfmmmiii, %esi
	movl	$.L__unnamed_1, %edx
	movl	$.L__unnamed_1, %ecx
	movl	$-1, %r8d
	xorl	%r9d, %r9d
	callq	__hipRegisterFunction
	movl	$__hip_module_dtor, %edi
	addq	$40, %rsp
	.cfi_def_cfa_offset 8
	jmp	atexit                          # TAILCALL
.Lfunc_end1:
	.size	__hip_module_ctor, .Lfunc_end1-__hip_module_ctor
	.cfi_endproc
                                        # -- End function
	.p2align	4, 0x90                         # -- Begin function __hip_module_dtor
	.type	__hip_module_dtor,@function
__hip_module_dtor:                      # @__hip_module_dtor
	.cfi_startproc
# %bb.0:
	movq	__hip_gpubin_handle(%rip), %rdi
	testq	%rdi, %rdi
	je	.LBB2_2
# %bb.1:
	pushq	%rax
	.cfi_def_cfa_offset 16
	callq	__hipUnregisterFatBinary
	movq	$0, __hip_gpubin_handle(%rip)
	addq	$8, %rsp
	.cfi_def_cfa_offset 8
.LBB2_2:
	retq
.Lfunc_end2:
	.size	__hip_module_dtor, .Lfunc_end2-__hip_module_dtor
	.cfi_endproc
                                        # -- End function
	.type	_Z7flip_3DPfmmmiii,@object      # @_Z7flip_3DPfmmmiii
	.section	.rodata,"a",@progbits
	.globl	_Z7flip_3DPfmmmiii
	.p2align	3, 0x0
_Z7flip_3DPfmmmiii:
	.quad	_Z22__device_stub__flip_3DPfmmmiii
	.size	_Z7flip_3DPfmmmiii, 8

	.type	.L__unnamed_1,@object           # @0
	.section	.rodata.str1.1,"aMS",@progbits,1
.L__unnamed_1:
	.asciz	"_Z7flip_3DPfmmmiii"
	.size	.L__unnamed_1, 19

	.type	__hip_fatbin_wrapper,@object    # @__hip_fatbin_wrapper
	.section	.hipFatBinSegment,"a",@progbits
	.p2align	3, 0x0
__hip_fatbin_wrapper:
	.long	1212764230                      # 0x48495046
	.long	1                               # 0x1
	.quad	__hip_fatbin
	.quad	0
	.size	__hip_fatbin_wrapper, 24

	.type	__hip_gpubin_handle,@object     # @__hip_gpubin_handle
	.local	__hip_gpubin_handle
	.comm	__hip_gpubin_handle,8,8
	.section	.init_array,"aw",@init_array
	.p2align	3, 0x0
	.quad	__hip_module_ctor
	.type	__hip_cuid_,@object             # @__hip_cuid_
	.bss
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               # 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym _Z22__device_stub__flip_3DPfmmmiii
	.addrsig_sym __hip_module_ctor
	.addrsig_sym __hip_module_dtor
	.addrsig_sym _Z7flip_3DPfmmmiii
	.addrsig_sym __hip_fatbin
	.addrsig_sym __hip_fatbin_wrapper
	.addrsig_sym __hip_cuid_

	.text
	.amdgcn_target "amdgcn-amd-amdhsa--gfx1100"
	.protected	_Z7flip_3DPfmmmiii      ; -- Begin function _Z7flip_3DPfmmmiii
	.globl	_Z7flip_3DPfmmmiii
	.p2align	8
	.type	_Z7flip_3DPfmmmiii,@function
_Z7flip_3DPfmmmiii:                     ; @_Z7flip_3DPfmmmiii
; %bb.0:
	s_clause 0x1
	s_load_b32 s2, s[0:1], 0x3c
	s_load_b256 s[4:11], s[0:1], 0x0
	s_waitcnt lgkmcnt(0)
	s_and_b32 s2, s2, 0xffff
	s_mul_i32 s3, s10, s9
	s_mul_hi_u32 s12, s10, s8
	s_mul_i32 s13, s11, s8
	s_mul_i32 s16, s10, s8
	v_mad_u64_u32 v[1:2], null, s15, s2, v[0:1]
	s_add_i32 s17, s12, s3
	s_mul_i32 s2, s16, s7
	s_mul_hi_u32 s3, s16, s6
	s_add_i32 s17, s17, s13
	v_mov_b32_e32 v2, 0
	s_add_i32 s2, s3, s2
	s_mul_i32 s3, s17, s6
	s_mov_b32 s12, exec_lo
	s_add_i32 s3, s2, s3
	s_mul_i32 s2, s16, s6
	s_delay_alu instid0(SALU_CYCLE_1)
	v_cmpx_gt_u64_e64 s[2:3], v[1:2]
	s_cbranch_execz .LBB0_7
; %bb.1:
	v_cvt_f32_u32_e32 v0, s10
	v_cvt_f32_u32_e32 v2, s11
	s_sub_u32 s12, 0, s10
	s_subb_u32 s13, 0, s11
	s_sub_u32 s18, 0, s16
	s_subb_u32 s19, 0, s17
	v_fmac_f32_e32 v0, 0x4f800000, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_rcp_f32_e32 v0, v0
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v0, 0x5f7ffffc, v0
	v_mul_f32_e32 v2, 0x2f800000, v0
	s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
	v_trunc_f32_e32 v2, v2
	v_fmac_f32_e32 v0, 0xcf800000, v2
	v_cvt_u32_f32_e32 v2, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cvt_u32_f32_e32 v0, v0
	v_mul_lo_u32 v3, s12, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_mul_hi_u32 v4, s12, v0
	v_mul_lo_u32 v5, s13, v0
	v_add_nc_u32_e32 v3, v4, v3
	v_mul_lo_u32 v4, s12, v0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v3, v5
	v_mul_hi_u32 v5, v0, v4
	s_delay_alu instid0(VALU_DEP_2)
	v_mul_lo_u32 v6, v0, v3
	v_mul_hi_u32 v7, v0, v3
	v_mul_hi_u32 v8, v2, v4
	v_mul_lo_u32 v4, v2, v4
	v_mul_hi_u32 v9, v2, v3
	v_mul_lo_u32 v3, v2, v3
	v_add_co_u32 v5, vcc_lo, v5, v6
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v5, v4
	v_add_co_ci_u32_e32 v4, vcc_lo, v6, v8, vcc_lo
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v9, vcc_lo
	v_cvt_f32_u32_e32 v6, s17
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, v3
	v_add_co_ci_u32_e32 v2, vcc_lo, v2, v4, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v3, s12, v0
	v_mul_lo_u32 v5, s13, v0
	v_mul_lo_u32 v4, s12, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_add_nc_u32_e32 v3, v3, v4
	v_mul_lo_u32 v4, s12, v0
	s_load_b128 s[12:15], s[0:1], 0x20
	v_add_nc_u32_e32 v3, v3, v5
	v_cvt_f32_u32_e32 v5, s16
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v7, v0, v4
	v_mul_lo_u32 v8, v0, v3
	v_mul_hi_u32 v9, v0, v3
	s_delay_alu instid0(VALU_DEP_4)
	v_fmac_f32_e32 v5, 0x4f800000, v6
	v_mul_hi_u32 v6, v2, v4
	v_mul_lo_u32 v4, v2, v4
	v_mul_hi_u32 v10, v2, v3
	v_mul_lo_u32 v3, v2, v3
	v_rcp_f32_e32 v5, v5
	v_add_co_u32 v7, vcc_lo, v7, v8
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v9, vcc_lo
	s_waitcnt lgkmcnt(0)
	s_cmp_lg_u32 s14, 0
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v4, vcc_lo, v7, v4
	v_add_co_ci_u32_e32 v4, vcc_lo, v8, v6, vcc_lo
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v10, vcc_lo
	s_waitcnt_depctr 0xfff
	v_mul_f32_e32 v9, 0x5f7ffffc, v5
	v_add_co_u32 v3, vcc_lo, v4, v3
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v6, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_f32_e32 v11, 0x2f800000, v9
	v_add_co_u32 v0, vcc_lo, v0, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v8, vcc_lo, v2, v4, vcc_lo
	s_cselect_b32 s20, -1, 0
	v_mul_hi_u32 v10, v1, v0
	v_mad_u64_u32 v[4:5], null, 0, v0, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mad_u64_u32 v[2:3], null, v1, v8, 0
	v_mad_u64_u32 v[6:7], null, 0, v8, 0
	s_lshr_b64 s[14:15], s[10:11], 1
	v_add_co_u32 v2, vcc_lo, v10, v2
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	v_trunc_f32_e32 v10, v11
	v_add_co_u32 v2, vcc_lo, v2, v4
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v2, vcc_lo, v3, v5, vcc_lo
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v7, vcc_lo
	v_fmac_f32_e32 v9, 0xcf800000, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v4, vcc_lo, v2, v6
	v_add_co_ci_u32_e32 v5, vcc_lo, 0, v3, vcc_lo
	v_cvt_u32_f32_e32 v10, v10
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cvt_u32_f32_e32 v9, v9
	v_mul_lo_u32 v6, s11, v4
	v_mad_u64_u32 v[2:3], null, s10, v4, 0
	v_mul_lo_u32 v7, s10, v5
	v_mul_lo_u32 v11, s18, v10
	v_mul_hi_u32 v12, s18, v9
	v_mul_lo_u32 v13, s18, v9
	v_sub_co_u32 v2, vcc_lo, v1, v2
	v_add3_u32 v3, v3, v7, v6
	v_mul_lo_u32 v6, s19, v9
	v_add_nc_u32_e32 v7, v12, v11
	v_mul_hi_u32 v12, v9, v13
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_sub_nc_u32_e32 v11, 0, v3
	v_add_nc_u32_e32 v6, v7, v6
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_subrev_co_ci_u32_e64 v11, s0, s11, v11, vcc_lo
	v_add_co_u32 v14, s0, v4, 2
	v_add_co_ci_u32_e64 v15, s0, 0, v5, s0
	v_sub_co_u32 v16, s0, v2, s10
	v_sub_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	v_subrev_co_ci_u32_e64 v11, s0, 0, v11, s0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e32 vcc_lo, s10, v16
	v_cmp_eq_u32_e64 s0, s11, v3
	v_mul_hi_u32 v19, v10, v6
	v_mul_lo_u32 v20, v10, v6
	v_cndmask_b32_e64 v16, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s11, v11
	v_cndmask_b32_e64 v17, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s10, v2
	v_cndmask_b32_e64 v2, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s11, v3
	v_cndmask_b32_e64 v18, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s11, v11
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
	v_cndmask_b32_e64 v2, v18, v2, s0
	v_cndmask_b32_e32 v11, v17, v16, vcc_lo
	v_add_co_u32 v16, vcc_lo, v4, 1
	v_add_co_ci_u32_e32 v17, vcc_lo, 0, v5, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v11
	v_mul_hi_u32 v11, v10, v13
	v_mul_lo_u32 v13, v10, v13
	v_cndmask_b32_e32 v3, v16, v14, vcc_lo
	v_cndmask_b32_e32 v7, v17, v15, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v2
	v_mul_lo_u32 v16, v9, v6
	v_mul_hi_u32 v15, v9, v6
	v_cndmask_b32_e32 v14, v4, v3, vcc_lo
	v_cndmask_b32_e32 v17, v5, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_mad_u64_u32 v[2:3], null, v14, v8, 0
	v_mul_hi_u32 v18, v14, v0
	v_mad_u64_u32 v[4:5], null, v17, v0, 0
	v_mad_u64_u32 v[6:7], null, v17, v8, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_add_co_u32 v0, vcc_lo, v18, v2
	v_add_co_ci_u32_e32 v2, vcc_lo, 0, v3, vcc_lo
	v_add_co_u32 v3, vcc_lo, v12, v16
	v_add_co_ci_u32_e32 v8, vcc_lo, 0, v15, vcc_lo
	v_add_co_u32 v0, vcc_lo, v0, v4
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v0, vcc_lo, v2, v5, vcc_lo
	v_add_co_ci_u32_e32 v4, vcc_lo, 0, v7, vcc_lo
	v_add_co_u32 v2, vcc_lo, v3, v13
	v_add_co_ci_u32_e32 v2, vcc_lo, v8, v11, vcc_lo
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v19, vcc_lo
	v_add_co_u32 v2, vcc_lo, v2, v20
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
	v_add_co_u32 v7, vcc_lo, v9, v2
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add_co_ci_u32_e32 v8, vcc_lo, v10, v3, vcc_lo
	v_add_co_u32 v0, vcc_lo, v0, v6
	v_mul_hi_u32 v2, s18, v7
	s_delay_alu instid0(VALU_DEP_3)
	v_mul_lo_u32 v3, s18, v8
	v_mul_lo_u32 v5, s19, v7
	v_mul_lo_u32 v10, s18, v7
	v_mul_lo_u32 v12, s11, v0
	v_mul_lo_u32 v9, v14, s11
	v_add_nc_u32_e32 v11, v2, v3
	v_mad_u64_u32 v[2:3], null, v14, s10, 0
	v_mul_hi_u32 v13, v7, v10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_add_nc_u32_e32 v6, v11, v5
	v_add_co_ci_u32_e32 v11, vcc_lo, 0, v4, vcc_lo
	v_mad_u64_u32 v[4:5], null, s10, v0, 0
	v_mul_lo_u32 v15, v7, v6
	v_mul_hi_u32 v16, v7, v6
	v_mul_hi_u32 v0, v8, v10
	v_mul_lo_u32 v10, v8, v10
	v_mul_hi_u32 v18, v8, v6
	v_mul_lo_u32 v6, v8, v6
	v_mul_lo_u32 v11, s10, v11
	v_add_co_u32 v13, vcc_lo, v13, v15
	v_add_co_ci_u32_e32 v15, vcc_lo, 0, v16, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v10, vcc_lo, v13, v10
	v_add_co_ci_u32_e32 v0, vcc_lo, v15, v0, vcc_lo
	v_add_co_ci_u32_e32 v10, vcc_lo, 0, v18, vcc_lo
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_u32 v0, vcc_lo, v0, v6
	v_add_co_ci_u32_e32 v6, vcc_lo, 0, v10, vcc_lo
	v_mul_lo_u32 v10, v17, s10
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v0, vcc_lo, v7, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, v8, v6, vcc_lo
	v_add3_u32 v8, v5, v11, v12
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_hi_u32 v0, v1, v0
	v_mad_u64_u32 v[5:6], null, v1, v7, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
	v_sub_nc_u32_e32 v7, v17, v8
	v_add3_u32 v9, v3, v9, v10
	v_sub_co_u32 v10, vcc_lo, v14, v4
	v_subrev_co_ci_u32_e64 v7, s0, s11, v7, vcc_lo
	v_add_co_u32 v0, s0, v0, v5
	v_sub_co_ci_u32_e32 v8, vcc_lo, v17, v8, vcc_lo
	v_add_co_ci_u32_e64 v11, s0, 0, v6, s0
	v_cmp_le_u32_e32 vcc_lo, s10, v10
	v_sub_co_u32 v6, s0, v10, s10
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_mad_u64_u32 v[3:4], null, s16, v11, 0
	v_cndmask_b32_e64 v12, 0, -1, vcc_lo
	v_subrev_co_ci_u32_e64 v13, vcc_lo, 0, v7, s0
	v_cmp_le_u32_e32 vcc_lo, s10, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_4)
	v_mov_b32_e32 v0, v4
	v_cndmask_b32_e64 v14, 0, -1, vcc_lo
	v_subrev_co_ci_u32_e64 v7, vcc_lo, s11, v7, s0
	v_cmp_le_u32_e32 vcc_lo, s11, v13
	v_mad_u64_u32 v[4:5], null, s17, v11, v[0:1]
	v_sub_co_u32 v3, s0, v1, v3
	v_cndmask_b32_e64 v15, 0, -1, vcc_lo
	v_cmp_le_u32_e32 vcc_lo, s11, v8
	v_cndmask_b32_e64 v16, 0, -1, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s11, v13
	s_delay_alu instid0(VALU_DEP_4)
	v_cndmask_b32_e32 v0, v15, v14, vcc_lo
	v_sub_co_u32 v5, vcc_lo, v6, s10
	v_subrev_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
	v_cmp_eq_u32_e32 vcc_lo, s11, v8
	v_sub_nc_u32_e32 v14, 0, v4
	v_cndmask_b32_e32 v12, v16, v12, vcc_lo
	v_cmp_ne_u32_e32 vcc_lo, 0, v0
	v_cndmask_b32_e32 v0, v13, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_subrev_co_ci_u32_e64 v7, s1, s17, v14, s0
	v_add_co_u32 v13, s1, v11, 2
	v_add_co_ci_u32_e64 v14, null, 0, 0, s1
	v_sub_co_u32 v15, s1, v3, s16
	v_sub_co_ci_u32_e64 v4, s0, 0, v4, s0
	v_subrev_co_ci_u32_e64 v7, s1, 0, v7, s1
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
	v_cmp_le_u32_e64 s0, s16, v15
	v_cmp_ne_u32_e64 s1, 0, v12
	v_cndmask_b32_e32 v12, v6, v5, vcc_lo
	v_cndmask_b32_e64 v15, 0, -1, s0
	v_cmp_le_u32_e64 s0, s17, v7
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v16, 0, -1, s0
	v_cmp_le_u32_e64 s0, s16, v3
	v_cndmask_b32_e64 v3, 0, -1, s0
	v_cmp_le_u32_e64 s0, s17, v4
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_cndmask_b32_e64 v17, 0, -1, s0
	v_cmp_eq_u32_e64 s0, s17, v7
	v_cndmask_b32_e64 v7, v16, v15, s0
	v_add_co_u32 v15, s0, v11, 1
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
	v_add_co_ci_u32_e64 v16, null, 0, 0, s0
	v_cmp_eq_u32_e64 s0, s17, v4
	v_cndmask_b32_e64 v3, v17, v3, s0
	v_cmp_ne_u32_e64 s0, 0, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_cmp_ne_u32_e32 vcc_lo, 0, v3
	v_cndmask_b32_e64 v4, v16, v14, s0
	v_cndmask_b32_e64 v13, v15, v13, s0
	v_sub_co_u32 v6, s0, v1, v2
	s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_sub_co_ci_u32_e64 v7, s0, 0, v9, s0
	v_cndmask_b32_e64 v3, v8, v0, s1
	v_dual_cndmask_b32 v5, 0, v4 :: v_dual_cndmask_b32 v4, v11, v13
	v_cndmask_b32_e64 v2, v10, v12, s1
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_cmp_gt_u64_e32 vcc_lo, s[14:15], v[6:7]
	v_mul_lo_u32 v8, v3, s10
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
	v_mul_lo_u32 v9, v5, s16
	v_mul_lo_u32 v10, v4, s17
	v_mul_lo_u32 v11, v2, s11
	v_lshlrev_b64 v[0:1], 2, v[6:7]
	s_and_b32 s1, s20, vcc_lo
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_3
; %bb.2:
	v_mad_u64_u32 v[12:13], null, v4, s16, 0
	v_mad_u64_u32 v[14:15], null, v2, s10, 0
	s_lshl_b64 s[2:3], s[2:3], 3
	v_not_b32_e32 v7, v7
	s_add_u32 s1, s4, s2
	s_addc_u32 s2, s5, s3
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
	v_add3_u32 v13, v13, v10, v9
	v_not_b32_e32 v6, v6
	v_add3_u32 v15, v15, v11, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[14:15], 2, v[14:15]
	v_add_co_u32 v12, vcc_lo, s1, v12
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v13, vcc_lo, s2, v13, vcc_lo
	s_lshl_b64 s[2:3], s[10:11], 2
	v_add_co_u32 v12, vcc_lo, v12, v14
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v13, vcc_lo, v13, v15, vcc_lo
	v_add_co_u32 v14, vcc_lo, v12, s2
	s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_add_co_ci_u32_e32 v15, vcc_lo, s3, v13, vcc_lo
	v_add_co_u32 v6, vcc_lo, v14, v6
	s_delay_alu instid0(VALU_DEP_2)
	v_add_co_ci_u32_e32 v7, vcc_lo, v15, v7, vcc_lo
	v_add_co_u32 v12, vcc_lo, v12, v0
	v_add_co_ci_u32_e32 v13, vcc_lo, v13, v1, vcc_lo
	s_clause 0x1
	global_load_b32 v14, v[6:7], off
	global_load_b32 v15, v[12:13], off
	s_waitcnt vmcnt(1)
	global_store_b32 v[12:13], v14, off
	s_waitcnt vmcnt(0)
	global_store_b32 v[6:7], v15, off
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
.LBB0_3:
	s_or_b32 exec_lo, exec_lo, s0
	s_cmp_lg_u32 s13, 0
	s_cselect_b32 s2, -1, 0
	s_lshr_b64 s[0:1], s[8:9], 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[2:3]
	s_and_b32 s1, s2, vcc_lo
	s_and_saveexec_b32 s0, s1
	s_cbranch_execz .LBB0_5
; %bb.4:
	v_add_co_u32 v12, vcc_lo, v4, s6
	v_not_b32_e32 v7, v2
	v_add_co_ci_u32_e32 v6, vcc_lo, s7, v5, vcc_lo
	v_not_b32_e32 v3, v3
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v15, v12, s17
	v_add_co_u32 v16, vcc_lo, v7, s8
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_mul_lo_u32 v14, v6, s16
	v_add_co_ci_u32_e32 v3, vcc_lo, s9, v3, vcc_lo
	v_mad_u64_u32 v[6:7], null, v12, s16, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_mul_lo_u32 v17, v16, s11
	v_mul_lo_u32 v3, v3, s10
	v_mad_u64_u32 v[12:13], null, v16, s10, 0
	s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add3_u32 v7, v7, v15, v14
	v_mad_u64_u32 v[14:15], null, v2, s10, 0
	v_add3_u32 v13, v13, v17, v3
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[6:7], 2, v[6:7]
	v_add3_u32 v15, v15, v11, v8
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_lshlrev_b64 v[12:13], 2, v[12:13]
	v_add_co_u32 v3, vcc_lo, s4, v6
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v16, vcc_lo, s5, v7, vcc_lo
	v_lshlrev_b64 v[6:7], 2, v[14:15]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v12, vcc_lo, v3, v12
	v_add_co_ci_u32_e32 v13, vcc_lo, v16, v13, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v3, vcc_lo, v3, v6
	v_add_co_ci_u32_e32 v14, vcc_lo, v16, v7, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v6, vcc_lo, v12, v0
	v_add_co_ci_u32_e32 v7, vcc_lo, v13, v1, vcc_lo
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_u32 v12, vcc_lo, v3, v0
	v_add_co_ci_u32_e32 v13, vcc_lo, v14, v1, vcc_lo
	s_clause 0x1
	global_load_b32 v3, v[6:7], off
	global_load_b32 v14, v[12:13], off
	s_waitcnt vmcnt(1)
	global_store_b32 v[12:13], v3, off
	s_waitcnt vmcnt(0)
	global_store_b32 v[6:7], v14, off
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
.LBB0_5:
	s_or_b32 exec_lo, exec_lo, s0
	s_cmp_lg_u32 s12, 0
	s_cselect_b32 s2, -1, 0
	s_lshr_b64 s[0:1], s[6:7], 1
	s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
	v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[4:5]
	s_and_b32 s0, s2, vcc_lo
	s_and_b32 exec_lo, exec_lo, s0
	s_cbranch_execz .LBB0_7
; %bb.6:
	v_not_b32_e32 v3, v4
	v_not_b32_e32 v5, v5
	v_mad_u64_u32 v[12:13], null, v4, s16, 0
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add_co_u32 v3, vcc_lo, v3, s6
	v_add_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
	v_add3_u32 v13, v13, v10, v9
	v_mul_lo_u32 v14, v3, s17
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
	v_mul_lo_u32 v7, v5, s16
	v_mad_u64_u32 v[5:6], null, v3, s16, 0
	v_mad_u64_u32 v[3:4], null, v2, s10, 0
	v_add3_u32 v6, v6, v14, v7
	s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
	v_add3_u32 v4, v4, v11, v8
	v_lshlrev_b64 v[7:8], 2, v[12:13]
	v_lshlrev_b64 v[5:6], 2, v[5:6]
	s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
	v_lshlrev_b64 v[2:3], 2, v[3:4]
	v_add_co_u32 v4, vcc_lo, s4, v5
	s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v5, vcc_lo, s5, v6, vcc_lo
	v_add_co_u32 v6, vcc_lo, s4, v7
	v_add_co_ci_u32_e32 v7, vcc_lo, s5, v8, vcc_lo
	v_add_co_u32 v4, vcc_lo, v4, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v5, vcc_lo, v5, v3, vcc_lo
	v_add_co_u32 v6, vcc_lo, v6, v2
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v7, vcc_lo, v7, v3, vcc_lo
	v_add_co_u32 v2, vcc_lo, v4, v0
	s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
	v_add_co_ci_u32_e32 v3, vcc_lo, v5, v1, vcc_lo
	v_add_co_u32 v0, vcc_lo, v6, v0
	s_delay_alu instid0(VALU_DEP_4)
	v_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo
	s_clause 0x1
	global_load_b32 v4, v[2:3], off
	global_load_b32 v5, v[0:1], off
	s_waitcnt vmcnt(1)
	global_store_b32 v[0:1], v4, off
	s_waitcnt vmcnt(0)
	global_store_b32 v[2:3], v5, off
	s_waitcnt_vscnt null, 0x0
	s_barrier
	buffer_gl0_inv
.LBB0_7:
	s_endpgm
	.section	.rodata,"a",@progbits
	.p2align	6, 0x0
	.amdhsa_kernel _Z7flip_3DPfmmmiii
		.amdhsa_group_segment_fixed_size 0
		.amdhsa_private_segment_fixed_size 0
		.amdhsa_kernarg_size 304
		.amdhsa_user_sgpr_count 15
		.amdhsa_user_sgpr_dispatch_ptr 0
		.amdhsa_user_sgpr_queue_ptr 0
		.amdhsa_user_sgpr_kernarg_segment_ptr 1
		.amdhsa_user_sgpr_dispatch_id 0
		.amdhsa_user_sgpr_private_segment_size 0
		.amdhsa_wavefront_size32 1
		.amdhsa_uses_dynamic_stack 0
		.amdhsa_enable_private_segment 0
		.amdhsa_system_sgpr_workgroup_id_x 1
		.amdhsa_system_sgpr_workgroup_id_y 0
		.amdhsa_system_sgpr_workgroup_id_z 0
		.amdhsa_system_sgpr_workgroup_info 0
		.amdhsa_system_vgpr_workitem_id 0
		.amdhsa_next_free_vgpr 21
		.amdhsa_next_free_sgpr 21
		.amdhsa_float_round_mode_32 0
		.amdhsa_float_round_mode_16_64 0
		.amdhsa_float_denorm_mode_32 3
		.amdhsa_float_denorm_mode_16_64 3
		.amdhsa_dx10_clamp 1
		.amdhsa_ieee_mode 1
		.amdhsa_fp16_overflow 0
		.amdhsa_workgroup_processor_mode 1
		.amdhsa_memory_ordered 1
		.amdhsa_forward_progress 0
		.amdhsa_shared_vgpr_count 0
		.amdhsa_exception_fp_ieee_invalid_op 0
		.amdhsa_exception_fp_denorm_src 0
		.amdhsa_exception_fp_ieee_div_zero 0
		.amdhsa_exception_fp_ieee_overflow 0
		.amdhsa_exception_fp_ieee_underflow 0
		.amdhsa_exception_fp_ieee_inexact 0
		.amdhsa_exception_int_div_zero 0
	.end_amdhsa_kernel
	.text
.Lfunc_end0:
	.size	_Z7flip_3DPfmmmiii, .Lfunc_end0-_Z7flip_3DPfmmmiii
                                        ; -- End function
	.section	.AMDGPU.csdata,"",@progbits
; Kernel info:
; codeLenInByte = 2840
; NumSgprs: 23
; NumVgprs: 21
; ScratchSize: 0
; MemoryBound: 0
; FloatMode: 240
; IeeeMode: 1
; LDSByteSize: 0 bytes/workgroup (compile time only)
; SGPRBlocks: 2
; VGPRBlocks: 2
; NumSGPRsForWavesPerEU: 23
; NumVGPRsForWavesPerEU: 21
; Occupancy: 16
; WaveLimiterHint : 0
; COMPUTE_PGM_RSRC2:SCRATCH_EN: 0
; COMPUTE_PGM_RSRC2:USER_SGPR: 15
; COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
; COMPUTE_PGM_RSRC2:TGID_X_EN: 1
; COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
; COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
; COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
	.text
	.p2alignl 7, 3214868480
	.fill 96, 4, 3214868480
	.type	__hip_cuid_,@object             ; @__hip_cuid_
	.section	.bss,"aw",@nobits
	.globl	__hip_cuid_
__hip_cuid_:
	.byte	0                               ; 0x0
	.size	__hip_cuid_, 1

	.ident	"AMD clang version 18.0.0git (https://github.com/RadeonOpenCompute/llvm-project roc-6.3.2 25012 e5bf7e55c91490b07c49d8960fa7983d864936c4)"
	.section	".note.GNU-stack","",@progbits
	.addrsig
	.addrsig_sym __hip_cuid_
	.amdgpu_metadata
---
amdhsa.kernels:
  - .args:
      - .address_space:  global
        .offset:         0
        .size:           8
        .value_kind:     global_buffer
      - .offset:         8
        .size:           8
        .value_kind:     by_value
      - .offset:         16
        .size:           8
        .value_kind:     by_value
      - .offset:         24
        .size:           8
        .value_kind:     by_value
      - .offset:         32
        .size:           4
        .value_kind:     by_value
      - .offset:         36
        .size:           4
        .value_kind:     by_value
      - .offset:         40
        .size:           4
        .value_kind:     by_value
      - .offset:         48
        .size:           4
        .value_kind:     hidden_block_count_x
      - .offset:         52
        .size:           4
        .value_kind:     hidden_block_count_y
      - .offset:         56
        .size:           4
        .value_kind:     hidden_block_count_z
      - .offset:         60
        .size:           2
        .value_kind:     hidden_group_size_x
      - .offset:         62
        .size:           2
        .value_kind:     hidden_group_size_y
      - .offset:         64
        .size:           2
        .value_kind:     hidden_group_size_z
      - .offset:         66
        .size:           2
        .value_kind:     hidden_remainder_x
      - .offset:         68
        .size:           2
        .value_kind:     hidden_remainder_y
      - .offset:         70
        .size:           2
        .value_kind:     hidden_remainder_z
      - .offset:         88
        .size:           8
        .value_kind:     hidden_global_offset_x
      - .offset:         96
        .size:           8
        .value_kind:     hidden_global_offset_y
      - .offset:         104
        .size:           8
        .value_kind:     hidden_global_offset_z
      - .offset:         112
        .size:           2
        .value_kind:     hidden_grid_dims
    .group_segment_fixed_size: 0
    .kernarg_segment_align: 8
    .kernarg_segment_size: 304
    .language:       OpenCL C
    .language_version:
      - 2
      - 0
    .max_flat_workgroup_size: 1024
    .name:           _Z7flip_3DPfmmmiii
    .private_segment_fixed_size: 0
    .sgpr_count:     23
    .sgpr_spill_count: 0
    .symbol:         _Z7flip_3DPfmmmiii.kd
    .uniform_work_group_size: 1
    .uses_dynamic_stack: false
    .vgpr_count:     21
    .vgpr_spill_count: 0
    .wavefront_size: 32
    .workgroup_processor_mode: 1
amdhsa.target:   amdgcn-amd-amdhsa--gfx1100
amdhsa.version:
  - 1
  - 2
...

	.end_amdgpu_metadata
